--- /dev/null
+build
+ChibiOS_*
+
--- /dev/null
+##############################################################################\r
+# Build global options\r
+# NOTE: Can be overridden externally.\r
+#\r
+\r
+# Compiler options here.\r
+ifeq ($(USE_OPT),)\r
+ USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16\r
+endif\r
+\r
+# C specific options here (added to USE_OPT).\r
+ifeq ($(USE_COPT),)\r
+ USE_COPT = \r
+endif\r
+\r
+# C++ specific options here (added to USE_OPT).\r
+ifeq ($(USE_CPPOPT),)\r
+ USE_CPPOPT = -std=c++2a -fno-rtti -fno-exceptions\r
+endif\r
+\r
+# Enable this if you want the linker to remove unused code and data.\r
+ifeq ($(USE_LINK_GC),)\r
+ USE_LINK_GC = yes\r
+endif\r
+\r
+# Linker extra options here.\r
+ifeq ($(USE_LDOPT),)\r
+ USE_LDOPT = \r
+endif\r
+\r
+# Enable this if you want link time optimizations (LTO).\r
+ifeq ($(USE_LTO),)\r
+ USE_LTO = yes\r
+endif\r
+\r
+# Enable this if you want to see the full log while compiling.\r
+ifeq ($(USE_VERBOSE_COMPILE),)\r
+ USE_VERBOSE_COMPILE = no\r
+endif\r
+\r
+# If enabled, this option makes the build process faster by not compiling\r
+# modules not used in the current configuration.\r
+ifeq ($(USE_SMART_BUILD),)\r
+ USE_SMART_BUILD = yes\r
+endif\r
+\r
+#\r
+# Build global options\r
+##############################################################################\r
+\r
+##############################################################################\r
+# Architecture or project specific options\r
+#\r
+\r
+# Stack size to be allocated to the Cortex-M process stack. This stack is\r
+# the stack used by the main() thread.\r
+ifeq ($(USE_PROCESS_STACKSIZE),)\r
+ USE_PROCESS_STACKSIZE = 0x400\r
+endif\r
+\r
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This\r
+# stack is used for processing interrupts and exceptions.\r
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)\r
+ USE_EXCEPTIONS_STACKSIZE = 0x400\r
+endif\r
+\r
+# Enables the use of FPU (no, softfp, hard).\r
+ifeq ($(USE_FPU),)\r
+ USE_FPU = hard\r
+endif\r
+\r
+# FPU-related options.\r
+ifeq ($(USE_FPU_OPT),)\r
+ USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16\r
+endif\r
+\r
+#\r
+# Architecture or project specific options\r
+##############################################################################\r
+\r
+##############################################################################\r
+# Project, target, sources and paths\r
+#\r
+\r
+# Define project name here\r
+PROJECT = stmadc\r
+\r
+# Target settings.\r
+MCU = cortex-m4\r
+\r
+# Imported source files and paths.\r
+CHIBIOS := ChibiOS_20.3.1\r
+CONFDIR := ./cfg\r
+BUILDDIR := ./build\r
+DEPDIR := ./.dep\r
+\r
+# Licensing files.\r
+include $(CHIBIOS)/os/license/license.mk\r
+# Startup files.\r
+include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk\r
+# HAL-OSAL files (optional).\r
+include $(CHIBIOS)/os/hal/hal.mk\r
+include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk\r
+include $(CHIBIOS)/os/hal/boards/ST_STM32L476_DISCOVERY/board.mk\r
+include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk\r
+# RTOS files (optional).\r
+include $(CHIBIOS)/os/rt/rt.mk\r
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk\r
+# Auto-build files in ./source recursively.\r
+include $(CHIBIOS)/tools/mk/autobuild.mk\r
+# Other files (optional).\r
+#include $(CHIBIOS)/test/lib/test.mk\r
+#include $(CHIBIOS)/test/rt/rt_test.mk\r
+#include $(CHIBIOS)/test/oslib/oslib_test.mk\r
+\r
+# Define linker script file here.\r
+LDSCRIPT= $(STARTUPLD)/STM32L476xG.ld\r
+\r
+# C sources that can be compiled in ARM or THUMB mode depending on the global\r
+# setting.\r
+CSRC = $(ALLCSRC)\r
+\r
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global\r
+# setting.\r
+CPPSRC = $(ALLCPPSRC)\r
+\r
+# List ASM source files here.\r
+ASMSRC = $(ALLASMSRC)\r
+\r
+# List ASM with preprocessor source files here.\r
+ASMXSRC = $(ALLXASMSRC)\r
+\r
+# Inclusion directories.\r
+INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC)\r
+\r
+# Define C warning options here.\r
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -pedantic\r
+\r
+# Define C++ warning options here.\r
+CPPWARN = -Wall -Wextra -Wundef -pedantic\r
+\r
+#\r
+# Project, target, sources and paths\r
+##############################################################################\r
+\r
+##############################################################################\r
+# Start of user section\r
+#\r
+\r
+# List all user C define here, like -D_DEBUG=1\r
+UDEFS =\r
+\r
+# Define ASM defines here\r
+UADEFS =\r
+\r
+# List all user directories here\r
+UINCDIR =\r
+\r
+# List the user directory to look for the libraries here\r
+ULIBDIR =\r
+\r
+# List all user libraries here\r
+ULIBS =\r
+\r
+#\r
+# End of user section\r
+##############################################################################\r
+\r
+##############################################################################\r
+# Common rules\r
+#\r
+\r
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk\r
+include $(RULESPATH)/arm-none-eabi.mk\r
+include $(RULESPATH)/rules.mk\r
+\r
+#\r
+# Common rules\r
+##############################################################################\r
+\r
+##############################################################################\r
+# Custom rules\r
+#\r
+\r
+#\r
+# Custom rules\r
+##############################################################################\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/**\r
+ * @file rt/templates/chconf.h\r
+ * @brief Configuration file template.\r
+ * @details A copy of this file must be placed in each project directory, it\r
+ * contains the application specific kernel settings.\r
+ *\r
+ * @addtogroup config\r
+ * @details Kernel related settings and hooks.\r
+ * @{\r
+ */\r
+\r
+#ifndef CHCONF_H\r
+#define CHCONF_H\r
+\r
+#define _CHIBIOS_RT_CONF_\r
+#define _CHIBIOS_RT_CONF_VER_6_1_\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name System timers settings\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief System time counter resolution.\r
+ * @note Allowed values are 16 or 32 bits.\r
+ */\r
+#if !defined(CH_CFG_ST_RESOLUTION)\r
+#define CH_CFG_ST_RESOLUTION 32\r
+#endif\r
+\r
+/**\r
+ * @brief System tick frequency.\r
+ * @details Frequency of the system timer that drives the system ticks. This\r
+ * setting also defines the system tick time unit.\r
+ */\r
+#if !defined(CH_CFG_ST_FREQUENCY)\r
+#define CH_CFG_ST_FREQUENCY 10000\r
+#endif\r
+\r
+/**\r
+ * @brief Time intervals data size.\r
+ * @note Allowed values are 16, 32 or 64 bits.\r
+ */\r
+#if !defined(CH_CFG_INTERVALS_SIZE)\r
+#define CH_CFG_INTERVALS_SIZE 32\r
+#endif\r
+\r
+/**\r
+ * @brief Time types data size.\r
+ * @note Allowed values are 16 or 32 bits.\r
+ */\r
+#if !defined(CH_CFG_TIME_TYPES_SIZE)\r
+#define CH_CFG_TIME_TYPES_SIZE 32\r
+#endif\r
+\r
+/**\r
+ * @brief Time delta constant for the tick-less mode.\r
+ * @note If this value is zero then the system uses the classic\r
+ * periodic tick. This value represents the minimum number\r
+ * of ticks that is safe to specify in a timeout directive.\r
+ * The value one is not valid, timeouts are rounded up to\r
+ * this value.\r
+ */\r
+#if !defined(CH_CFG_ST_TIMEDELTA)\r
+#define CH_CFG_ST_TIMEDELTA 2\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Kernel parameters and options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Round robin interval.\r
+ * @details This constant is the number of system ticks allowed for the\r
+ * threads before preemption occurs. Setting this value to zero\r
+ * disables the preemption for threads with equal priority and the\r
+ * round robin becomes cooperative. Note that higher priority\r
+ * threads can still preempt, the kernel is always preemptive.\r
+ * @note Disabling the round robin preemption makes the kernel more compact\r
+ * and generally faster.\r
+ * @note The round robin preemption is not supported in tickless mode and\r
+ * must be set to zero in that case.\r
+ */\r
+#if !defined(CH_CFG_TIME_QUANTUM)\r
+#define CH_CFG_TIME_QUANTUM 0\r
+#endif\r
+\r
+/**\r
+ * @brief Idle thread automatic spawn suppression.\r
+ * @details When this option is activated the function @p chSysInit()\r
+ * does not spawn the idle thread. The application @p main()\r
+ * function becomes the idle thread and must implement an\r
+ * infinite loop.\r
+ */\r
+#if !defined(CH_CFG_NO_IDLE_THREAD)\r
+#define CH_CFG_NO_IDLE_THREAD FALSE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Performance options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief OS optimization.\r
+ * @details If enabled then time efficient rather than space efficient code\r
+ * is used when two possible implementations exist.\r
+ *\r
+ * @note This is not related to the compiler optimization options.\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_OPTIMIZE_SPEED)\r
+#define CH_CFG_OPTIMIZE_SPEED TRUE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Subsystem options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Time Measurement APIs.\r
+ * @details If enabled then the time measurement APIs are included in\r
+ * the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_TM)\r
+#define CH_CFG_USE_TM TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Threads registry APIs.\r
+ * @details If enabled then the registry APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_REGISTRY)\r
+#define CH_CFG_USE_REGISTRY TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Threads synchronization APIs.\r
+ * @details If enabled then the @p chThdWait() function is included in\r
+ * the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_WAITEXIT)\r
+#define CH_CFG_USE_WAITEXIT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Semaphores APIs.\r
+ * @details If enabled then the Semaphores APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_SEMAPHORES)\r
+#define CH_CFG_USE_SEMAPHORES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Semaphores queuing mode.\r
+ * @details If enabled then the threads are enqueued on semaphores by\r
+ * priority rather than in FIFO order.\r
+ *\r
+ * @note The default is @p FALSE. Enable this if you have special\r
+ * requirements.\r
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.\r
+ */\r
+#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)\r
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Mutexes APIs.\r
+ * @details If enabled then the mutexes APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_MUTEXES)\r
+#define CH_CFG_USE_MUTEXES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables recursive behavior on mutexes.\r
+ * @note Recursive mutexes are heavier and have an increased\r
+ * memory footprint.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ * @note Requires @p CH_CFG_USE_MUTEXES.\r
+ */\r
+#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)\r
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Conditional Variables APIs.\r
+ * @details If enabled then the conditional variables APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_MUTEXES.\r
+ */\r
+#if !defined(CH_CFG_USE_CONDVARS)\r
+#define CH_CFG_USE_CONDVARS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Conditional Variables APIs with timeout.\r
+ * @details If enabled then the conditional variables APIs with timeout\r
+ * specification are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_CONDVARS.\r
+ */\r
+#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)\r
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Events Flags APIs.\r
+ * @details If enabled then the event flags APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_EVENTS)\r
+#define CH_CFG_USE_EVENTS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Events Flags APIs with timeout.\r
+ * @details If enabled then the events APIs with timeout specification\r
+ * are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_EVENTS.\r
+ */\r
+#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)\r
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Synchronous Messages APIs.\r
+ * @details If enabled then the synchronous messages APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_MESSAGES)\r
+#define CH_CFG_USE_MESSAGES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Synchronous Messages queuing mode.\r
+ * @details If enabled then messages are served by priority rather than in\r
+ * FIFO order.\r
+ *\r
+ * @note The default is @p FALSE. Enable this if you have special\r
+ * requirements.\r
+ * @note Requires @p CH_CFG_USE_MESSAGES.\r
+ */\r
+#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)\r
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Dynamic Threads APIs.\r
+ * @details If enabled then the dynamic threads creation APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_WAITEXIT.\r
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.\r
+ */\r
+#if !defined(CH_CFG_USE_DYNAMIC)\r
+#define CH_CFG_USE_DYNAMIC TRUE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name OSLIB options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Mailboxes APIs.\r
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are\r
+ * included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.\r
+ */\r
+#if !defined(CH_CFG_USE_MAILBOXES)\r
+#define CH_CFG_USE_MAILBOXES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Core Memory Manager APIs.\r
+ * @details If enabled then the core memory manager APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_MEMCORE)\r
+#define CH_CFG_USE_MEMCORE TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Managed RAM size.\r
+ * @details Size of the RAM area to be managed by the OS. If set to zero\r
+ * then the whole available RAM is used. The core memory is made\r
+ * available to the heap allocator and/or can be used directly through\r
+ * the simplified core memory allocator.\r
+ *\r
+ * @note In order to let the OS manage the whole RAM the linker script must\r
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.\r
+ * @note Requires @p CH_CFG_USE_MEMCORE.\r
+ */\r
+#if !defined(CH_CFG_MEMCORE_SIZE)\r
+#define CH_CFG_MEMCORE_SIZE 0\r
+#endif\r
+\r
+/**\r
+ * @brief Heap Allocator APIs.\r
+ * @details If enabled then the memory heap allocator APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or\r
+ * @p CH_CFG_USE_SEMAPHORES.\r
+ * @note Mutexes are recommended.\r
+ */\r
+#if !defined(CH_CFG_USE_HEAP)\r
+#define CH_CFG_USE_HEAP TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Memory Pools Allocator APIs.\r
+ * @details If enabled then the memory pools allocator APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_MEMPOOLS)\r
+#define CH_CFG_USE_MEMPOOLS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Objects FIFOs APIs.\r
+ * @details If enabled then the objects FIFOs APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_OBJ_FIFOS)\r
+#define CH_CFG_USE_OBJ_FIFOS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Pipes APIs.\r
+ * @details If enabled then the pipes APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_PIPES)\r
+#define CH_CFG_USE_PIPES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Objects Caches APIs.\r
+ * @details If enabled then the objects caches APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_OBJ_CACHES)\r
+#define CH_CFG_USE_OBJ_CACHES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Delegate threads APIs.\r
+ * @details If enabled then the delegate threads APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_DELEGATES)\r
+#define CH_CFG_USE_DELEGATES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Jobs Queues APIs.\r
+ * @details If enabled then the jobs queues APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_JOBS)\r
+#define CH_CFG_USE_JOBS TRUE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Objects factory options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Objects Factory APIs.\r
+ * @details If enabled then the objects factory APIs are included in the\r
+ * kernel.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_CFG_USE_FACTORY)\r
+#define CH_CFG_USE_FACTORY TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Maximum length for object names.\r
+ * @details If the specified length is zero then the name is stored by\r
+ * pointer but this could have unintended side effects.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)\r
+#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the registry of generic objects.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)\r
+#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables factory for generic buffers.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)\r
+#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables factory for semaphores.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_SEMAPHORES)\r
+#define CH_CFG_FACTORY_SEMAPHORES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables factory for mailboxes.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_MAILBOXES)\r
+#define CH_CFG_FACTORY_MAILBOXES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables factory for objects FIFOs.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)\r
+#define CH_CFG_FACTORY_OBJ_FIFOS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables factory for Pipes.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)\r
+#define CH_CFG_FACTORY_PIPES TRUE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Debug options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Debug option, kernel statistics.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_STATISTICS)\r
+#define CH_DBG_STATISTICS FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, system state check.\r
+ * @details If enabled the correct call protocol for system APIs is checked\r
+ * at runtime.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK)\r
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, parameters checks.\r
+ * @details If enabled then the checks on the API functions input\r
+ * parameters are activated.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_ENABLE_CHECKS)\r
+#define CH_DBG_ENABLE_CHECKS FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, consistency checks.\r
+ * @details If enabled then all the assertions in the kernel code are\r
+ * activated. This includes consistency checks inside the kernel,\r
+ * runtime anomalies and port-defined checks.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_ENABLE_ASSERTS)\r
+#define CH_DBG_ENABLE_ASSERTS FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, trace buffer.\r
+ * @details If enabled then the trace buffer is activated.\r
+ *\r
+ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.\r
+ */\r
+#if !defined(CH_DBG_TRACE_MASK)\r
+#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED\r
+#endif\r
+\r
+/**\r
+ * @brief Trace buffer entries.\r
+ * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is\r
+ * different from @p CH_DBG_TRACE_MASK_DISABLED.\r
+ */\r
+#if !defined(CH_DBG_TRACE_BUFFER_SIZE)\r
+#define CH_DBG_TRACE_BUFFER_SIZE 128\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, stack checks.\r
+ * @details If enabled then a runtime stack check is performed.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ * @note The stack check is performed in a architecture/port dependent way.\r
+ * It may not be implemented or some ports.\r
+ * @note The default failure mode is to halt the system with the global\r
+ * @p panic_msg variable set to @p NULL.\r
+ */\r
+#if !defined(CH_DBG_ENABLE_STACK_CHECK)\r
+#define CH_DBG_ENABLE_STACK_CHECK FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, stacks initialization.\r
+ * @details If enabled then the threads working area is filled with a byte\r
+ * value when a thread is created. This can be useful for the\r
+ * runtime measurement of the used stack.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_FILL_THREADS)\r
+#define CH_DBG_FILL_THREADS FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, threads profiling.\r
+ * @details If enabled then a field is added to the @p thread_t structure that\r
+ * counts the system ticks occurred while executing the thread.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ * @note This debug option is not currently compatible with the\r
+ * tickless mode.\r
+ */\r
+#if !defined(CH_DBG_THREADS_PROFILING)\r
+#define CH_DBG_THREADS_PROFILING FALSE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Kernel hooks\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief System structure extension.\r
+ * @details User fields added to the end of the @p ch_system_t structure.\r
+ */\r
+#define CH_CFG_SYSTEM_EXTRA_FIELDS \\r
+ /* Add threads custom fields here.*/\r
+\r
+/**\r
+ * @brief System initialization hook.\r
+ * @details User initialization code added to the @p chSysInit() function\r
+ * just before interrupts are enabled globally.\r
+ */\r
+#define CH_CFG_SYSTEM_INIT_HOOK() { \\r
+ /* Add threads initialization code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Threads descriptor structure extension.\r
+ * @details User fields added to the end of the @p thread_t structure.\r
+ */\r
+#define CH_CFG_THREAD_EXTRA_FIELDS \\r
+ /* Add threads custom fields here.*/\r
+\r
+/**\r
+ * @brief Threads initialization hook.\r
+ * @details User initialization code added to the @p _thread_init() function.\r
+ *\r
+ * @note It is invoked from within @p _thread_init() and implicitly from all\r
+ * the threads creation APIs.\r
+ */\r
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \\r
+ /* Add threads initialization code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Threads finalization hook.\r
+ * @details User finalization code added to the @p chThdExit() API.\r
+ */\r
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \\r
+ /* Add threads finalization code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Context switch hook.\r
+ * @details This hook is invoked just before switching between threads.\r
+ */\r
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \\r
+ /* Context switch code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief ISR enter hook.\r
+ */\r
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \\r
+ /* IRQ prologue code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief ISR exit hook.\r
+ */\r
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \\r
+ /* IRQ epilogue code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Idle thread enter hook.\r
+ * @note This hook is invoked within a critical zone, no OS functions\r
+ * should be invoked from here.\r
+ * @note This macro can be used to activate a power saving mode.\r
+ */\r
+#define CH_CFG_IDLE_ENTER_HOOK() { \\r
+ /* Idle-enter code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Idle thread leave hook.\r
+ * @note This hook is invoked within a critical zone, no OS functions\r
+ * should be invoked from here.\r
+ * @note This macro can be used to deactivate a power saving mode.\r
+ */\r
+#define CH_CFG_IDLE_LEAVE_HOOK() { \\r
+ /* Idle-leave code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Idle Loop hook.\r
+ * @details This hook is continuously invoked by the idle thread loop.\r
+ */\r
+#define CH_CFG_IDLE_LOOP_HOOK() { \\r
+ /* Idle loop code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief System tick event hook.\r
+ * @details This hook is invoked in the system tick handler immediately\r
+ * after processing the virtual timers queue.\r
+ */\r
+#define CH_CFG_SYSTEM_TICK_HOOK() { \\r
+ /* System tick event code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief System halt hook.\r
+ * @details This hook is invoked in case to a system halting error before\r
+ * the system is halted.\r
+ */\r
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \\r
+ /* System halt code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Trace hook.\r
+ * @details This hook is invoked each time a new record is written in the\r
+ * trace buffer.\r
+ */\r
+#define CH_CFG_TRACE_HOOK(tep) { \\r
+ /* Trace code here.*/ \\r
+}\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/* Port-specific settings (override port settings defaulted in chcore.h). */\r
+/*===========================================================================*/\r
+\r
+#endif /* CHCONF_H */\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/**\r
+ * @file templates/halconf.h\r
+ * @brief HAL configuration header.\r
+ * @details HAL configuration file, this file allows to enable or disable the\r
+ * various device drivers from your application. You may also use\r
+ * this file in order to override the device drivers default settings.\r
+ *\r
+ * @addtogroup HAL_CONF\r
+ * @{\r
+ */\r
+\r
+#ifndef HALCONF_H\r
+#define HALCONF_H\r
+\r
+#define _CHIBIOS_HAL_CONF_\r
+#define _CHIBIOS_HAL_CONF_VER_7_1_\r
+\r
+#include "mcuconf.h"\r
+\r
+/**\r
+ * @brief Enables the PAL subsystem.\r
+ */\r
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)\r
+#define HAL_USE_PAL TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the ADC subsystem.\r
+ */\r
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)\r
+#define HAL_USE_ADC TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the CAN subsystem.\r
+ */\r
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)\r
+#define HAL_USE_CAN FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the cryptographic subsystem.\r
+ */\r
+#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)\r
+#define HAL_USE_CRY FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the DAC subsystem.\r
+ */\r
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)\r
+#define HAL_USE_DAC TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the EFlash subsystem.\r
+ */\r
+#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)\r
+#define HAL_USE_EFL FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the GPT subsystem.\r
+ */\r
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)\r
+#define HAL_USE_GPT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the I2C subsystem.\r
+ */\r
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)\r
+#define HAL_USE_I2C FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the I2S subsystem.\r
+ */\r
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)\r
+#define HAL_USE_I2S FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the ICU subsystem.\r
+ */\r
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)\r
+#define HAL_USE_ICU FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the MAC subsystem.\r
+ */\r
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)\r
+#define HAL_USE_MAC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the MMC_SPI subsystem.\r
+ */\r
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)\r
+#define HAL_USE_MMC_SPI FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the PWM subsystem.\r
+ */\r
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)\r
+#define HAL_USE_PWM FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the RTC subsystem.\r
+ */\r
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)\r
+#define HAL_USE_RTC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SDC subsystem.\r
+ */\r
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)\r
+#define HAL_USE_SDC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SERIAL subsystem.\r
+ */\r
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)\r
+#define HAL_USE_SERIAL TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SERIAL over USB subsystem.\r
+ */\r
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)\r
+#define HAL_USE_SERIAL_USB TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SIO subsystem.\r
+ */\r
+#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)\r
+#define HAL_USE_SIO FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SPI subsystem.\r
+ */\r
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)\r
+#define HAL_USE_SPI FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the TRNG subsystem.\r
+ */\r
+#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)\r
+#define HAL_USE_TRNG FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the UART subsystem.\r
+ */\r
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)\r
+#define HAL_USE_UART FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the USB subsystem.\r
+ */\r
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)\r
+#define HAL_USE_USB TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the WDG subsystem.\r
+ */\r
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)\r
+#define HAL_USE_WDG FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the WSPI subsystem.\r
+ */\r
+#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)\r
+#define HAL_USE_WSPI FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* PAL driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)\r
+#define PAL_USE_CALLBACKS FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)\r
+#define PAL_USE_WAIT FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* ADC driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)\r
+#define ADC_USE_WAIT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define ADC_USE_MUTUAL_EXCLUSION TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* CAN driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Sleep mode related APIs inclusion switch.\r
+ */\r
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)\r
+#define CAN_USE_SLEEP_MODE TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enforces the driver to use direct callbacks rather than OSAL events.\r
+ */\r
+#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)\r
+#define CAN_ENFORCE_USE_CALLBACKS FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* CRY driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables the SW fall-back of the cryptographic driver.\r
+ * @details When enabled, this option, activates a fall-back software\r
+ * implementation for algorithms not supported by the underlying\r
+ * hardware.\r
+ * @note Fall-back implementations may not be present for all algorithms.\r
+ */\r
+#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)\r
+#define HAL_CRY_USE_FALLBACK FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Makes the driver forcibly use the fall-back implementations.\r
+ */\r
+#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)\r
+#define HAL_CRY_ENFORCE_FALLBACK FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* DAC driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)\r
+#define DAC_USE_WAIT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define DAC_USE_MUTUAL_EXCLUSION TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* I2C driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables the mutual exclusion APIs on the I2C bus.\r
+ */\r
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define I2C_USE_MUTUAL_EXCLUSION TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* MAC driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables the zero-copy API.\r
+ */\r
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)\r
+#define MAC_USE_ZERO_COPY FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables an event sources for incoming packets.\r
+ */\r
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)\r
+#define MAC_USE_EVENTS TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* MMC_SPI driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Delays insertions.\r
+ * @details If enabled this options inserts delays into the MMC waiting\r
+ * routines releasing some extra CPU time for the threads with\r
+ * lower priority, this may slow down the driver a bit however.\r
+ * This option is recommended also if the SPI driver does not\r
+ * use a DMA channel and heavily loads the CPU.\r
+ */\r
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)\r
+#define MMC_NICE_WAITING TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* SDC driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Number of initialization attempts before rejecting the card.\r
+ * @note Attempts are performed at 10mS intervals.\r
+ */\r
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)\r
+#define SDC_INIT_RETRY 100\r
+#endif\r
+\r
+/**\r
+ * @brief Include support for MMC cards.\r
+ * @note MMC support is not yet implemented so this option must be kept\r
+ * at @p FALSE.\r
+ */\r
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)\r
+#define SDC_MMC_SUPPORT FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Delays insertions.\r
+ * @details If enabled this options inserts delays into the MMC waiting\r
+ * routines releasing some extra CPU time for the threads with\r
+ * lower priority, this may slow down the driver a bit however.\r
+ */\r
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)\r
+#define SDC_NICE_WAITING TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief OCR initialization constant for V20 cards.\r
+ */\r
+#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)\r
+#define SDC_INIT_OCR_V20 0x50FF8000U\r
+#endif\r
+\r
+/**\r
+ * @brief OCR initialization constant for non-V20 cards.\r
+ */\r
+#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)\r
+#define SDC_INIT_OCR 0x80100000U\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* SERIAL driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Default bit rate.\r
+ * @details Configuration parameter, this is the baud rate selected for the\r
+ * default configuration.\r
+ */\r
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)\r
+#define SERIAL_DEFAULT_BITRATE 38400\r
+#endif\r
+\r
+/**\r
+ * @brief Serial buffers size.\r
+ * @details Configuration parameter, you can change the depth of the queue\r
+ * buffers depending on the requirements of your application.\r
+ * @note The default is 16 bytes for both the transmission and receive\r
+ * buffers.\r
+ */\r
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)\r
+#define SERIAL_BUFFERS_SIZE 16\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* SERIAL_USB driver related setting. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Serial over USB buffers size.\r
+ * @details Configuration parameter, the buffer size must be a multiple of\r
+ * the USB data endpoint maximum packet size.\r
+ * @note The default is 256 bytes for both the transmission and receive\r
+ * buffers.\r
+ */\r
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)\r
+#define SERIAL_USB_BUFFERS_SIZE 256\r
+#endif\r
+\r
+/**\r
+ * @brief Serial over USB number of buffers.\r
+ * @note The default is 2 buffers.\r
+ */\r
+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)\r
+#define SERIAL_USB_BUFFERS_NUMBER 2\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* SPI driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)\r
+#define SPI_USE_WAIT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables circular transfers APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)\r
+#define SPI_USE_CIRCULAR FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define SPI_USE_MUTUAL_EXCLUSION TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Handling method for SPI CS line.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)\r
+#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* UART driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)\r
+#define UART_USE_WAIT FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define UART_USE_MUTUAL_EXCLUSION FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* USB driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)\r
+#define USB_USE_WAIT FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* WSPI driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)\r
+#define WSPI_USE_WAIT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define WSPI_USE_MUTUAL_EXCLUSION TRUE\r
+#endif\r
+\r
+#endif /* HALCONF_H */\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/*\r
+ * STM32L4xx drivers configuration.\r
+ * The following settings override the default settings present in\r
+ * the various device driver implementation headers.\r
+ * Note that the settings for each driver only have effect if the whole\r
+ * driver is enabled in halconf.h.\r
+ *\r
+ * IRQ priorities:\r
+ * 15...0 Lowest...Highest.\r
+ *\r
+ * DMA priorities:\r
+ * 0...3 Lowest...Highest.\r
+ */\r
+\r
+#ifndef MCUCONF_H\r
+#define MCUCONF_H\r
+\r
+#define STM32L4xx_MCUCONF\r
+#define STM32L476_MCUCONF\r
+#define STM32L486_MCUCONF\r
+\r
+/*\r
+ * HAL driver system settings.\r
+ */\r
+#define STM32_NO_INIT FALSE\r
+#define STM32_VOS STM32_VOS_RANGE1\r
+#define STM32_PVD_ENABLE FALSE\r
+#define STM32_PLS STM32_PLS_LEV0\r
+#define STM32_HSI16_ENABLED TRUE\r
+#define STM32_LSI_ENABLED TRUE\r
+#define STM32_HSE_ENABLED FALSE\r
+#define STM32_LSE_ENABLED TRUE\r
+#define STM32_MSIPLL_ENABLED TRUE\r
+#define STM32_MSIRANGE STM32_MSIRANGE_48M\r
+#define STM32_MSISRANGE STM32_MSISRANGE_4M\r
+#define STM32_SW STM32_SW_PLL\r
+#define STM32_PLLSRC STM32_PLLSRC_HSI16\r
+#define STM32_PLLM_VALUE 4\r
+#define STM32_PLLN_VALUE 80\r
+#define STM32_PLLP_VALUE 7\r
+#define STM32_PLLQ_VALUE 6\r
+#define STM32_PLLR_VALUE 4\r
+#define STM32_HPRE STM32_HPRE_DIV1\r
+#define STM32_PPRE1 STM32_PPRE1_DIV1\r
+#define STM32_PPRE2 STM32_PPRE2_DIV1\r
+#define STM32_STOPWUCK STM32_STOPWUCK_MSI\r
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK\r
+#define STM32_MCOPRE STM32_MCOPRE_DIV1\r
+#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK\r
+#define STM32_PLLSAI1N_VALUE 72\r
+#define STM32_PLLSAI1P_VALUE 7\r
+#define STM32_PLLSAI1Q_VALUE 6\r
+#define STM32_PLLSAI1R_VALUE 6\r
+#define STM32_PLLSAI2N_VALUE 72\r
+#define STM32_PLLSAI2P_VALUE 7\r
+#define STM32_PLLSAI2R_VALUE 6\r
+\r
+/*\r
+ * Peripherals clock sources.\r
+ */\r
+#define STM32_USART1SEL STM32_USART1SEL_SYSCLK\r
+#define STM32_USART2SEL STM32_USART2SEL_SYSCLK\r
+#define STM32_USART3SEL STM32_USART3SEL_SYSCLK\r
+#define STM32_UART4SEL STM32_UART4SEL_SYSCLK\r
+#define STM32_UART5SEL STM32_UART5SEL_SYSCLK\r
+#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK\r
+#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK\r
+#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK\r
+#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK\r
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1\r
+#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1\r
+#define STM32_SAI1SEL STM32_SAI1SEL_OFF\r
+#define STM32_SAI2SEL STM32_SAI2SEL_OFF\r
+#define STM32_CLK48SEL STM32_CLK48SEL_MSI\r
+#define STM32_ADCSEL STM32_ADCSEL_SYSCLK\r
+#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1\r
+#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2\r
+#define STM32_RTCSEL STM32_RTCSEL_LSI\r
+\r
+/*\r
+ * IRQ system settings.\r
+ */\r
+#define STM32_IRQ_EXTI0_PRIORITY 6\r
+#define STM32_IRQ_EXTI1_PRIORITY 6\r
+#define STM32_IRQ_EXTI2_PRIORITY 6\r
+#define STM32_IRQ_EXTI3_PRIORITY 6\r
+#define STM32_IRQ_EXTI4_PRIORITY 6\r
+#define STM32_IRQ_EXTI5_9_PRIORITY 6\r
+#define STM32_IRQ_EXTI10_15_PRIORITY 6\r
+#define STM32_IRQ_EXTI1635_38_PRIORITY 6\r
+#define STM32_IRQ_EXTI18_PRIORITY 6\r
+#define STM32_IRQ_EXTI19_PRIORITY 6\r
+#define STM32_IRQ_EXTI20_PRIORITY 6\r
+#define STM32_IRQ_EXTI21_22_PRIORITY 15\r
+\r
+#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7\r
+#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7\r
+#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7\r
+#define STM32_IRQ_TIM1_CC_PRIORITY 7\r
+#define STM32_IRQ_TIM2_PRIORITY 7\r
+#define STM32_IRQ_TIM3_PRIORITY 7\r
+#define STM32_IRQ_TIM4_PRIORITY 7\r
+#define STM32_IRQ_TIM5_PRIORITY 7\r
+#define STM32_IRQ_TIM6_PRIORITY 7\r
+#define STM32_IRQ_TIM7_PRIORITY 7\r
+#define STM32_IRQ_TIM8_UP_PRIORITY 7\r
+#define STM32_IRQ_TIM8_CC_PRIORITY 7\r
+\r
+#define STM32_IRQ_USART1_PRIORITY 12\r
+#define STM32_IRQ_USART2_PRIORITY 12\r
+#define STM32_IRQ_USART3_PRIORITY 12\r
+#define STM32_IRQ_UART4_PRIORITY 12\r
+#define STM32_IRQ_UART5_PRIORITY 12\r
+#define STM32_IRQ_LPUART1_PRIORITY 12\r
+\r
+/*\r
+ * ADC driver system settings.\r
+ */\r
+#define STM32_ADC_DUAL_MODE FALSE\r
+#define STM32_ADC_COMPACT_SAMPLES FALSE\r
+#define STM32_ADC_USE_ADC1 TRUE\r
+#define STM32_ADC_USE_ADC2 TRUE\r
+#define STM32_ADC_USE_ADC3 TRUE\r
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)\r
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)\r
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)\r
+#define STM32_ADC_ADC1_DMA_PRIORITY 2\r
+#define STM32_ADC_ADC2_DMA_PRIORITY 2\r
+#define STM32_ADC_ADC3_DMA_PRIORITY 2\r
+#define STM32_ADC_ADC12_IRQ_PRIORITY 5\r
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5\r
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5\r
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5\r
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5\r
+#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1\r
+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2\r
+\r
+/*\r
+ * CAN driver system settings.\r
+ */\r
+#define STM32_CAN_USE_CAN1 FALSE\r
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11\r
+\r
+/*\r
+ * DAC driver system settings.\r
+ */\r
+#define STM32_DAC_DUAL_MODE FALSE\r
+#define STM32_DAC_USE_DAC1_CH1 TRUE\r
+#define STM32_DAC_USE_DAC1_CH2 FALSE\r
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10\r
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10\r
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2\r
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2\r
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)\r
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)\r
+\r
+/*\r
+ * GPT driver system settings.\r
+ */\r
+#define STM32_GPT_USE_TIM1 FALSE\r
+#define STM32_GPT_USE_TIM2 FALSE\r
+#define STM32_GPT_USE_TIM3 FALSE\r
+#define STM32_GPT_USE_TIM4 TRUE\r
+#define STM32_GPT_USE_TIM5 FALSE\r
+#define STM32_GPT_USE_TIM6 FALSE\r
+#define STM32_GPT_USE_TIM7 FALSE\r
+#define STM32_GPT_USE_TIM8 FALSE\r
+#define STM32_GPT_USE_TIM15 FALSE\r
+#define STM32_GPT_USE_TIM16 FALSE\r
+#define STM32_GPT_USE_TIM17 FALSE\r
+\r
+/*\r
+ * I2C driver system settings.\r
+ */\r
+#define STM32_I2C_USE_I2C1 FALSE\r
+#define STM32_I2C_USE_I2C2 FALSE\r
+#define STM32_I2C_USE_I2C3 FALSE\r
+#define STM32_I2C_BUSY_TIMEOUT 50\r
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)\r
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)\r
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)\r
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)\r
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)\r
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)\r
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5\r
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5\r
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5\r
+#define STM32_I2C_I2C1_DMA_PRIORITY 3\r
+#define STM32_I2C_I2C2_DMA_PRIORITY 3\r
+#define STM32_I2C_I2C3_DMA_PRIORITY 3\r
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")\r
+\r
+/*\r
+ * ICU driver system settings.\r
+ */\r
+#define STM32_ICU_USE_TIM1 FALSE\r
+#define STM32_ICU_USE_TIM2 FALSE\r
+#define STM32_ICU_USE_TIM3 FALSE\r
+#define STM32_ICU_USE_TIM4 FALSE\r
+#define STM32_ICU_USE_TIM5 FALSE\r
+#define STM32_ICU_USE_TIM8 FALSE\r
+#define STM32_ICU_USE_TIM15 FALSE\r
+#define STM32_ICU_USE_TIM16 FALSE\r
+#define STM32_ICU_USE_TIM17 FALSE\r
+\r
+/*\r
+ * PWM driver system settings.\r
+ */\r
+#define STM32_PWM_USE_ADVANCED FALSE\r
+#define STM32_PWM_USE_TIM1 FALSE\r
+#define STM32_PWM_USE_TIM2 FALSE\r
+#define STM32_PWM_USE_TIM3 FALSE\r
+#define STM32_PWM_USE_TIM4 FALSE\r
+#define STM32_PWM_USE_TIM5 FALSE\r
+#define STM32_PWM_USE_TIM8 FALSE\r
+#define STM32_PWM_USE_TIM15 FALSE\r
+#define STM32_PWM_USE_TIM16 FALSE\r
+#define STM32_PWM_USE_TIM17 FALSE\r
+\r
+/*\r
+ * RTC driver system settings.\r
+ */\r
+#define STM32_RTC_PRESA_VALUE 32\r
+#define STM32_RTC_PRESS_VALUE 1024\r
+#define STM32_RTC_CR_INIT 0\r
+#define STM32_RTC_TAMPCR_INIT 0\r
+\r
+/*\r
+ * SDC driver system settings.\r
+ */\r
+#define STM32_SDC_USE_SDMMC1 FALSE\r
+#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE\r
+#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000\r
+#define STM32_SDC_SDMMC_READ_TIMEOUT 1000\r
+#define STM32_SDC_SDMMC_CLOCK_DELAY 10\r
+#define STM32_SDC_SDMMC1_DMA_PRIORITY 3\r
+#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9\r
+#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)\r
+\r
+/*\r
+ * SERIAL driver system settings.\r
+ */\r
+#define STM32_SERIAL_USE_USART1 FALSE\r
+#define STM32_SERIAL_USE_USART2 TRUE\r
+#define STM32_SERIAL_USE_USART3 FALSE\r
+#define STM32_SERIAL_USE_UART4 FALSE\r
+#define STM32_SERIAL_USE_UART5 FALSE\r
+#define STM32_SERIAL_USE_LPUART1 FALSE\r
+#define STM32_SERIAL_USART1_PRIORITY 12\r
+#define STM32_SERIAL_USART2_PRIORITY 12\r
+#define STM32_SERIAL_USART3_PRIORITY 12\r
+#define STM32_SERIAL_UART4_PRIORITY 12\r
+#define STM32_SERIAL_UART5_PRIORITY 12\r
+#define STM32_SERIAL_LPUART1_PRIORITY 12\r
+\r
+/*\r
+ * SPI driver system settings.\r
+ */\r
+#define STM32_SPI_USE_SPI1 FALSE\r
+#define STM32_SPI_USE_SPI2 FALSE\r
+#define STM32_SPI_USE_SPI3 FALSE\r
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)\r
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)\r
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)\r
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)\r
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)\r
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)\r
+#define STM32_SPI_SPI1_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI2_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI3_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10\r
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10\r
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10\r
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")\r
+\r
+/*\r
+ * ST driver system settings.\r
+ */\r
+#define STM32_ST_IRQ_PRIORITY 8\r
+#define STM32_ST_USE_TIMER 2\r
+\r
+/*\r
+ * TRNG driver system settings.\r
+ */\r
+#define STM32_TRNG_USE_RNG1 FALSE\r
+\r
+/*\r
+ * UART driver system settings.\r
+ */\r
+#define STM32_UART_USE_USART1 FALSE\r
+#define STM32_UART_USE_USART2 FALSE\r
+#define STM32_UART_USE_USART3 FALSE\r
+#define STM32_UART_USE_UART4 FALSE\r
+#define STM32_UART_USE_UART5 FALSE\r
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)\r
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)\r
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)\r
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)\r
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)\r
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)\r
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)\r
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)\r
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)\r
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)\r
+#define STM32_UART_USART1_IRQ_PRIORITY 12\r
+#define STM32_UART_USART2_IRQ_PRIORITY 12\r
+#define STM32_UART_USART3_IRQ_PRIORITY 12\r
+#define STM32_UART_UART4_IRQ_PRIORITY 12\r
+#define STM32_UART_UART5_IRQ_PRIORITY 12\r
+#define STM32_UART_USART1_DMA_PRIORITY 0\r
+#define STM32_UART_USART2_DMA_PRIORITY 0\r
+#define STM32_UART_USART3_DMA_PRIORITY 0\r
+#define STM32_UART_UART4_DMA_PRIORITY 0\r
+#define STM32_UART_UART5_DMA_PRIORITY 0\r
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")\r
+\r
+/*\r
+ * USB driver system settings.\r
+ */\r
+#define STM32_USB_USE_OTG1 TRUE\r
+#define STM32_USB_OTG1_IRQ_PRIORITY 14\r
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512\r
+\r
+/*\r
+ * WDG driver system settings.\r
+ */\r
+#define STM32_WDG_USE_IWDG FALSE\r
+\r
+/*\r
+ * WSPI driver system settings.\r
+ */\r
+#define STM32_WSPI_USE_QUADSPI1 FALSE\r
+#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)\r
+\r
+#endif /* MCUCONF_H */\r
--- /dev/null
+#include "ch.h"\r
+#include "hal.h"\r
+#include "usbcfg.h"\r
+\r
+class dDAC\r
+{\r
+public:\r
+ constexpr dDAC(DACDriver& driver, const DACConfig& config) :\r
+ m_driver(&driver), m_config(config) {}\r
+\r
+ void init() {\r
+ dacStart(m_driver, &m_config);\r
+ }\r
+\r
+ void writeX(unsigned int channel, uint16_t value) {\r
+ if (channel < 2)\r
+ dacPutChannelX(m_driver, channel, value);\r
+ }\r
+\r
+private:\r
+ DACDriver *m_driver;\r
+ DACConfig m_config;\r
+};\r
+\r
+//static const DACConversionGroup dacGroupConfig = {\r
+// .num_channels = 1,\r
+// .end_cb = NULL,\r
+// .error_cb = NULL,\r
+// .trigger = DAC_TRG(0)\r
+//};\r
+\r
+class dGPT {\r
+public:\r
+ constexpr dGPT(GPTDriver& driver, const GPTConfig& config) :\r
+ m_driver(&driver), m_config(config) {}\r
+\r
+ void init() {\r
+ gptStart(m_driver, &m_config);\r
+ }\r
+\r
+ void startContinuous(unsigned int interval) {\r
+ gptStartContinuous(m_driver, interval);\r
+ }\r
+\r
+ void stop() {\r
+ gptStopTimer(m_driver);\r
+ }\r
+\r
+private:\r
+ GPTDriver *m_driver;\r
+ GPTConfig m_config;\r
+};\r
+\r
+static dGPT gpt (GPTD4, {\r
+ .frequency = 1000000,\r
+ .callback = NULL,\r
+ .cr2 = TIM_CR2_MMS_1, /* MMS = 010 = TRGO on Update Event. */\r
+ .dier = 0\r
+});\r
+\r
+static const ADCConfig adcConfig = {\r
+ .difsel = 0\r
+};\r
+\r
+volatile bool adcFinished = false;\r
+void adcEndCallback(ADCDriver *adcd)\r
+{\r
+ (void)adcd;\r
+ gpt.stop();\r
+ adcFinished = true;\r
+}\r
+\r
+static const ADCConversionGroup adcGroupConfig = {\r
+ .circular = false,\r
+ .num_channels = 1,\r
+ .end_cb = adcEndCallback,\r
+ .error_cb = NULL,\r
+ .cfgr = ADC_CFGR_EXTEN_RISING |\r
+ ADC_CFGR_EXTSEL_SRC(12), /* TIM4_TRGO */\r
+ .cfgr2 = 0,\r
+ .tr1 = ADC_TR(0, 4095),\r
+ .smpr = {\r
+ ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_247P5), 0\r
+ },\r
+ .sqr = {\r
+ ADC_SQR1_SQ1_N(ADC_CHANNEL_IN5),\r
+ 0, 0, 0\r
+ }\r
+};\r
+\r
+#if CACHE_LINE_SIZE > 0\r
+CC_ALIGN(CACHE_LINE_SIZE)\r
+#endif\r
+adcsample_t samples[CACHE_SIZE_ALIGN(adcsample_t, 10)];\r
+\r
+int main(void) {\r
+ halInit();\r
+ chSysInit();\r
+\r
+ palSetPadMode(GPIOA, 5, PAL_MODE_OUTPUT_PUSHPULL); // LED\r
+ palSetPadMode(GPIOA, 11, PAL_MODE_ALTERNATE(10)); // USB\r
+ palSetPadMode(GPIOA, 12, PAL_MODE_ALTERNATE(10));\r
+ palSetPadMode(GPIOA, 0, PAL_MODE_INPUT_ANALOG); // Channel A in (1in5)\r
+\r
+ palSetPadMode(GPIOA, 4, PAL_MODE_INPUT_ANALOG); // DAC out1, out2\r
+ palSetPadMode(GPIOA, 5, PAL_MODE_INPUT_ANALOG);\r
+\r
+ gpt.init();\r
+\r
+ //dDAC dac (DACD1, {\r
+ // .init = 0,\r
+ // .datamode = DAC_DHRM_12BIT_RIGHT,\r
+ // .cr = 0\r
+ //});\r
+\r
+ //dac.init();\r
+ //dac.writeX(0, 1024);\r
+\r
+ adcStart(&ADCD1, &adcConfig);\r
+ adcSTM32EnableVREF(&ADCD1);\r
+\r
+ sduObjectInit(&SDU1);\r
+ sduStart(&SDU1, &serusbcfg);\r
+ usbDisconnectBus(serusbcfg.usbp);\r
+ chThdSleepMilliseconds(1500);\r
+ usbStart(serusbcfg.usbp, &usbcfg);\r
+ usbConnectBus(serusbcfg.usbp);\r
+\r
+ while (true) {\r
+ if (SDU1.config->usbp->state == USB_ACTIVE) {\r
+ BaseSequentialStream *bss = (BaseSequentialStream *)&SDU1;\r
+ char c = 0;\r
+ if (streamRead(bss, (uint8_t *)&c, 1) > 0 && c == 's') {\r
+ adcFinished = false;\r
+ adcStartConversion(&ADCD1, &adcGroupConfig, samples, 10);\r
+ gpt.startContinuous(100);\r
+ while (!adcFinished);\r
+ for (int i = 0; i < 10; i++) {\r
+ uint8_t str[5] = {\r
+ static_cast<uint8_t>(samples[i] / 1000 % 10 + '0'),\r
+ static_cast<uint8_t>(samples[i] / 100 % 10 + '0'),\r
+ static_cast<uint8_t>(samples[i] / 10 % 10 + '0'),\r
+ static_cast<uint8_t>(samples[i] % 10 + '0'),\r
+ ' '\r
+ };\r
+ streamWrite(bss, str, 5);\r
+ }\r
+ streamWrite(bss, (uint8_t *)"\r\n", 2);\r
+ }\r
+ }\r
+ chThdSleepMilliseconds(250);\r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+#include "hal.h"\r
+\r
+/* Virtual serial port over USB.*/\r
+SerialUSBDriver SDU1;\r
+\r
+/*\r
+ * Endpoints to be used for USBD1.\r
+ */\r
+#define USBD1_DATA_REQUEST_EP 1\r
+#define USBD1_DATA_AVAILABLE_EP 1\r
+#define USBD1_INTERRUPT_REQUEST_EP 2\r
+\r
+/*\r
+ * USB Device Descriptor.\r
+ */\r
+static const uint8_t vcom_device_descriptor_data[18] = {\r
+ USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */\r
+ 0x02, /* bDeviceClass (CDC). */\r
+ 0x00, /* bDeviceSubClass. */\r
+ 0x00, /* bDeviceProtocol. */\r
+ 0x40, /* bMaxPacketSize. */\r
+ 0x0483, /* idVendor (ST). */\r
+ 0x5740, /* idProduct. */\r
+ 0x0200, /* bcdDevice. */\r
+ 1, /* iManufacturer. */\r
+ 2, /* iProduct. */\r
+ 3, /* iSerialNumber. */\r
+ 1) /* bNumConfigurations. */\r
+};\r
+\r
+/*\r
+ * Device Descriptor wrapper.\r
+ */\r
+static const USBDescriptor vcom_device_descriptor = {\r
+ sizeof vcom_device_descriptor_data,\r
+ vcom_device_descriptor_data\r
+};\r
+\r
+/* Configuration Descriptor tree for a CDC.*/\r
+static const uint8_t vcom_configuration_descriptor_data[67] = {\r
+ /* Configuration Descriptor.*/\r
+ USB_DESC_CONFIGURATION(67, /* wTotalLength. */\r
+ 0x02, /* bNumInterfaces. */\r
+ 0x01, /* bConfigurationValue. */\r
+ 0, /* iConfiguration. */\r
+ 0xC0, /* bmAttributes (self powered). */\r
+ 50), /* bMaxPower (100mA). */\r
+ /* Interface Descriptor.*/\r
+ USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */\r
+ 0x00, /* bAlternateSetting. */\r
+ 0x01, /* bNumEndpoints. */\r
+ 0x02, /* bInterfaceClass (Communications\r
+ Interface Class, CDC section\r
+ 4.2). */\r
+ 0x02, /* bInterfaceSubClass (Abstract\r
+ Control Model, CDC section 4.3). */\r
+ 0x01, /* bInterfaceProtocol (AT commands,\r
+ CDC section 4.4). */\r
+ 0), /* iInterface. */\r
+ /* Header Functional Descriptor (CDC section 5.2.3).*/\r
+ USB_DESC_BYTE (5), /* bLength. */\r
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */\r
+ USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header\r
+ Functional Descriptor. */\r
+ USB_DESC_BCD (0x0110), /* bcdCDC. */\r
+ /* Call Management Functional Descriptor. */\r
+ USB_DESC_BYTE (5), /* bFunctionLength. */\r
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */\r
+ USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management\r
+ Functional Descriptor). */\r
+ USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */\r
+ USB_DESC_BYTE (0x01), /* bDataInterface. */\r
+ /* ACM Functional Descriptor.*/\r
+ USB_DESC_BYTE (4), /* bFunctionLength. */\r
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */\r
+ USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract\r
+ Control Management Descriptor). */\r
+ USB_DESC_BYTE (0x02), /* bmCapabilities. */\r
+ /* Union Functional Descriptor.*/\r
+ USB_DESC_BYTE (5), /* bFunctionLength. */\r
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */\r
+ USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union\r
+ Functional Descriptor). */\r
+ USB_DESC_BYTE (0x00), /* bMasterInterface (Communication\r
+ Class Interface). */\r
+ USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class\r
+ Interface). */\r
+ /* Endpoint 2 Descriptor.*/\r
+ USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80,\r
+ 0x03, /* bmAttributes (Interrupt). */\r
+ 0x0008, /* wMaxPacketSize. */\r
+ 0xFF), /* bInterval. */\r
+ /* Interface Descriptor.*/\r
+ USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */\r
+ 0x00, /* bAlternateSetting. */\r
+ 0x02, /* bNumEndpoints. */\r
+ 0x0A, /* bInterfaceClass (Data Class\r
+ Interface, CDC section 4.5). */\r
+ 0x00, /* bInterfaceSubClass (CDC section\r
+ 4.6). */\r
+ 0x00, /* bInterfaceProtocol (CDC section\r
+ 4.7). */\r
+ 0x00), /* iInterface. */\r
+ /* Endpoint 3 Descriptor.*/\r
+ USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/\r
+ 0x02, /* bmAttributes (Bulk). */\r
+ 0x0040, /* wMaxPacketSize. */\r
+ 0x00), /* bInterval. */\r
+ /* Endpoint 1 Descriptor.*/\r
+ USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/\r
+ 0x02, /* bmAttributes (Bulk). */\r
+ 0x0040, /* wMaxPacketSize. */\r
+ 0x00) /* bInterval. */\r
+};\r
+\r
+/*\r
+ * Configuration Descriptor wrapper.\r
+ */\r
+static const USBDescriptor vcom_configuration_descriptor = {\r
+ sizeof vcom_configuration_descriptor_data,\r
+ vcom_configuration_descriptor_data\r
+};\r
+\r
+/*\r
+ * U.S. English language identifier.\r
+ */\r
+static const uint8_t vcom_string0[] = {\r
+ USB_DESC_BYTE(4), /* bLength. */\r
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */\r
+ USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */\r
+};\r
+\r
+/*\r
+ * Vendor string.\r
+ */\r
+static const uint8_t vcom_string1[] = {\r
+ USB_DESC_BYTE(38), /* bLength. */\r
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */\r
+ 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,\r
+ 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,\r
+ 'c', 0, 's', 0\r
+};\r
+\r
+/*\r
+ * Device Description string.\r
+ */\r
+static const uint8_t vcom_string2[] = {\r
+ USB_DESC_BYTE(56), /* bLength. */\r
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */\r
+ 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0,\r
+ 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0,\r
+ 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0,\r
+ 'o', 0, 'r', 0, 't', 0\r
+};\r
+\r
+/*\r
+ * Serial Number string.\r
+ */\r
+static const uint8_t vcom_string3[] = {\r
+ USB_DESC_BYTE(8), /* bLength. */\r
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */\r
+ '0' + CH_KERNEL_MAJOR, 0,\r
+ '0' + CH_KERNEL_MINOR, 0,\r
+ '0' + CH_KERNEL_PATCH, 0\r
+};\r
+\r
+/*\r
+ * Strings wrappers array.\r
+ */\r
+static const USBDescriptor vcom_strings[] = {\r
+ {sizeof vcom_string0, vcom_string0},\r
+ {sizeof vcom_string1, vcom_string1},\r
+ {sizeof vcom_string2, vcom_string2},\r
+ {sizeof vcom_string3, vcom_string3}\r
+};\r
+\r
+/*\r
+ * Handles the GET_DESCRIPTOR callback. All required descriptors must be\r
+ * handled here.\r
+ */\r
+static const USBDescriptor *get_descriptor(USBDriver *usbp,\r
+ uint8_t dtype,\r
+ uint8_t dindex,\r
+ uint16_t lang) {\r
+\r
+ (void)usbp;\r
+ (void)lang;\r
+ switch (dtype) {\r
+ case USB_DESCRIPTOR_DEVICE:\r
+ return &vcom_device_descriptor;\r
+ case USB_DESCRIPTOR_CONFIGURATION:\r
+ return &vcom_configuration_descriptor;\r
+ case USB_DESCRIPTOR_STRING:\r
+ if (dindex < 4)\r
+ return &vcom_strings[dindex];\r
+ }\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ * @brief IN EP1 state.\r
+ */\r
+static USBInEndpointState ep1instate;\r
+\r
+/**\r
+ * @brief OUT EP1 state.\r
+ */\r
+static USBOutEndpointState ep1outstate;\r
+\r
+/**\r
+ * @brief EP1 initialization structure (both IN and OUT).\r
+ */\r
+static const USBEndpointConfig ep1config = {\r
+ USB_EP_MODE_TYPE_BULK,\r
+ NULL,\r
+ sduDataTransmitted,\r
+ sduDataReceived,\r
+ 0x0040,\r
+ 0x0040,\r
+ &ep1instate,\r
+ &ep1outstate,\r
+ 1,\r
+ NULL\r
+};\r
+\r
+/**\r
+ * @brief IN EP2 state.\r
+ */\r
+static USBInEndpointState ep2instate;\r
+\r
+/**\r
+ * @brief EP2 initialization structure (IN only).\r
+ */\r
+static const USBEndpointConfig ep2config = {\r
+ USB_EP_MODE_TYPE_INTR,\r
+ NULL,\r
+ sduInterruptTransmitted,\r
+ NULL,\r
+ 0x0010,\r
+ 0x0000,\r
+ &ep2instate,\r
+ NULL,\r
+ 1,\r
+ NULL\r
+};\r
+\r
+/*\r
+ * Handles the USB driver global events.\r
+ */\r
+static void usb_event(USBDriver *usbp, usbevent_t event) {\r
+ extern SerialUSBDriver SDU1;\r
+\r
+ switch (event) {\r
+ case USB_EVENT_ADDRESS:\r
+ return;\r
+ case USB_EVENT_CONFIGURED:\r
+ chSysLockFromISR();\r
+\r
+ /* Enables the endpoints specified into the configuration.\r
+ Note, this callback is invoked from an ISR so I-Class functions\r
+ must be used.*/\r
+ usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config);\r
+ usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config);\r
+\r
+ /* Resetting the state of the CDC subsystem.*/\r
+ sduConfigureHookI(&SDU1);\r
+\r
+ chSysUnlockFromISR();\r
+ return;\r
+ case USB_EVENT_RESET:\r
+ /* Falls into.*/\r
+ case USB_EVENT_UNCONFIGURED:\r
+ /* Falls into.*/\r
+ case USB_EVENT_SUSPEND:\r
+ chSysLockFromISR();\r
+\r
+ /* Disconnection event on suspend.*/\r
+ sduSuspendHookI(&SDU1);\r
+\r
+ chSysUnlockFromISR();\r
+ return;\r
+ case USB_EVENT_WAKEUP:\r
+ chSysLockFromISR();\r
+\r
+ /* Connection event on wakeup.*/\r
+ sduWakeupHookI(&SDU1);\r
+\r
+ chSysUnlockFromISR();\r
+ return;\r
+ case USB_EVENT_STALLED:\r
+ return;\r
+ }\r
+ return;\r
+}\r
+\r
+/*\r
+ * Handles the USB driver global events.\r
+ */\r
+static void sof_handler(USBDriver *usbp) {\r
+\r
+ (void)usbp;\r
+\r
+ osalSysLockFromISR();\r
+ sduSOFHookI(&SDU1);\r
+ osalSysUnlockFromISR();\r
+}\r
+\r
+/*\r
+ * USB driver configuration.\r
+ */\r
+const USBConfig usbcfg = {\r
+ usb_event,\r
+ get_descriptor,\r
+ sduRequestsHook,\r
+ sof_handler\r
+};\r
+\r
+/*\r
+ * Serial over USB driver configuration.\r
+ */\r
+const SerialUSBConfig serusbcfg = {\r
+ &USBD1,\r
+ USBD1_DATA_REQUEST_EP,\r
+ USBD1_DATA_AVAILABLE_EP,\r
+ USBD1_INTERRUPT_REQUEST_EP\r
+};\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+#ifndef USBCFG_H\r
+#define USBCFG_H\r
+\r
+extern const USBConfig usbcfg;\r
+extern SerialUSBConfig serusbcfg;\r
+extern SerialUSBDriver SDU1;\r
+\r
+#endif /* USBCFG_H */\r
+\r
+/** @} */\r
projects / clyne / stmdsp.git / commitdiff