msp430: include core-ext and tools

diff --git a/Makefile b/Makefile
index c0c818a6eeaa198c90a1d8e6da82f0c411d9c1e2..af43bf35197e7e1214c6a3b4ad8e000260ac3429 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -18,7 +18,7 @@ msp430: CXXFLAGS += -DMEMDICTSIZE=1024 -flto -fno-asynchronous-unwind-tables -fn
 msp430: LDFLAGS += -L/usr/msp430-elf/usr/include -Tmsp430/msp430fr2476.ld -Wl,-gc-sections
 msp430: msp430/alee-msp430
 
-msp430-prep: STANDALONE += forth/msp430.fth
+msp430-prep: STANDALONE += forth/core-ext.fth forth/tools.fth forth/msp430.fth
 msp430-prep: core.fth.h
 msp430-prep: clean-lib
 

diff --git a/forth/msp430.fth b/forth/msp430.fth
index 9ba88bfe9250147fe1a9627c906b1aee332c835e..9fb041f37e9d1019bc6298cb3ae284d20035bdb2 100644 (file)
--- a/forth/msp430.fth
+++ b/forth/msp430.fth
@@ -840,3 +840,4 @@
 : UCB1IV_H           05AF ;
 
 decimal
+

diff --git a/forth/tools.fth b/forth/tools.fth
index 8992d483f2c02cbdf689a0abe57198a90cd98ea9..b27955d40cd13421c023290d96b9c70e329e9ce6 100644 (file)
--- a/forth/tools.fth
+++ b/forth/tools.fth
@@ -11,14 +11,3 @@
            >r cell+ rot drop r> @ then
            -rot swap type space \ lt adv
            over _begin <> while - repeat 2drop ;
-
-( xt -- caddr u )
-: _nameof  _latest @ begin \ xt lt
-           2dup < while \ xt lt
-           dup @ \ xt lt l
-           dup 6 >> 1023 < if \ xt lt l
-           6 >> - else
-           drop dup cell+ @ - then \ xt lt
-           repeat nip \ lt
-           dup @ swap cell+ over 31 & \ l lt len
-           rot 6 >> 1023 = if swap cell+ swap then ; \ lt len

diff --git a/msp430/alee-msp430.cpp b/msp430/alee-msp430.cpp
index 92f3aa5152c3d2ecaebce273aad4e13d9e90ca29..1d8d157f05a3fbeb112b58a7fe2724f487582a19 100644 (file)
--- a/msp430/alee-msp430.cpp
+++ b/msp430/alee-msp430.cpp
@@ -178,6 +178,13 @@ void initGPIO()
     P5DIR |= BIT5 | BIT6 | BIT7;
     P5OUT |= BIT5 | BIT6 | BIT7;
 
+    // Setup buttons w/ pullups
+    P3DIR &= ~BIT4; P3REN |= BIT4; P3OUT |= BIT4;
+    P2DIR &= ~BIT3; P2REN |= BIT3; P2OUT |= BIT3;
+
+    // XT1 pins (P2.0 and P2.1)
+    //P2SEL1 |= BIT0 | BIT1;
+
     // Allow GPIO configurations to be applied
     PM5CTL0 &= ~LOCKLPM5;
 
@@ -198,6 +205,19 @@ void initClock()
 
     CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                                // default DCODIV as MCLK and SMCLK source
+
+//    // ACLK to XT1
+//    do
+//    {
+//        CSCTL7 &= ~(XT1OFFG | DCOFFG);                // Clear XT1 and DCO fault flag
+//        SFRIFG1 &= ~OFIFG;
+//    }while (SFRIFG1 & OFIFG);                         // Test oscillator fault flag
+//
+//    CSCTL4 = SELMS__DCOCLKDIV | SELA__XT1CLK;  // set ACLK = XT1CLK = 32768Hz
+//                                               // DCOCLK = MCLK and SMCLK source
+//
+//    // Now that osc is running enable fault interrupt
+//    SFRIE1 |= OFIE;
 }
 
 void initUART()