--- /dev/null
+//*****************************************************************************\r
+//\r
+// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/\r
+//\r
+// Redistribution and use in source and binary forms, with or without\r
+// modification, are permitted provided that the following conditions\r
+// are met:\r
+//\r
+// Redistributions of source code must retain the above copyright\r
+// notice, this list of conditions and the following disclaimer.\r
+//\r
+// Redistributions in binary form must reproduce the above copyright\r
+// notice, this list of conditions and the following disclaimer in the\r
+// documentation and/or other materials provided with the\r
+// distribution.\r
+//\r
+// Neither the name of Texas Instruments Incorporated nor the names of\r
+// its contributors may be used to endorse or promote products derived\r
+// from this software without specific prior written permission.\r
+//\r
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+//****************************************************************************\r
+\r
+/********************************************************************\r
+*\r
+* Standard register and bit definitions for the Texas Instruments\r
+* MSP430 microcontroller.\r
+*\r
+* This file supports assembler and C development for\r
+* MSP430FR2476 devices.\r
+*\r
+********************************************************************/\r
+\r
+#ifndef __MSP430FR2476\r
+#define __MSP430FR2476\r
+\r
+#define __MSP430_HEADER_VERSION__ 1212\r
+\r
+#define __MSP430_HAS_MSP430XV2_CPU__ /* CPU type */\r
+#define __MSP430FR2XX_4XX_FAMILY__\r
+\r
+#include "in430.h"\r
+\r
+#define __MSP430_TI_HEADERS__\r
+\r
+#ifndef __AUTOGENERATED__\r
+#define __AUTOGENERATED__\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <iomacros.h>\r
+\r
+/************************************************************\r
+* STANDARD BITS\r
+************************************************************/\r
+\r
+#define BIT0 (0x0001)\r
+#define BIT1 (0x0002)\r
+#define BIT2 (0x0004)\r
+#define BIT3 (0x0008)\r
+#define BIT4 (0x0010)\r
+#define BIT5 (0x0020)\r
+#define BIT6 (0x0040)\r
+#define BIT7 (0x0080)\r
+#define BIT8 (0x0100)\r
+#define BIT9 (0x0200)\r
+#define BITA (0x0400)\r
+#define BITB (0x0800)\r
+#define BITC (0x1000)\r
+#define BITD (0x2000)\r
+#define BITE (0x4000)\r
+#define BITF (0x8000)\r
+\r
+/************************************************************\r
+* STATUS REGISTER BITS\r
+************************************************************/\r
+\r
+#define C (0x0001)\r
+#define Z (0x0002)\r
+#define N (0x0004)\r
+#define V (0x0100)\r
+#define GIE (0x0008)\r
+#define CPUOFF (0x0010)\r
+#define OSCOFF (0x0020)\r
+#define SCG0 (0x0040)\r
+#define SCG1 (0x0080)\r
+\r
+/* Low Power Modes coded with Bits 4-7 in SR */\r
+\r
+#ifndef __STDC__ /* Begin #defines for assembler */\r
+#define LPM0 (CPUOFF)\r
+#define LPM1 (SCG0+CPUOFF)\r
+#define LPM2 (SCG1+CPUOFF)\r
+#define LPM3 (SCG1+SCG0+CPUOFF)\r
+#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)\r
+/* End #defines for assembler */\r
+\r
+#else /* Begin #defines for C */\r
+#define LPM0_bits (CPUOFF)\r
+#define LPM1_bits (SCG0+CPUOFF)\r
+#define LPM2_bits (SCG1+CPUOFF)\r
+#define LPM3_bits (SCG1+SCG0+CPUOFF)\r
+#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)\r
+\r
+#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */\r
+#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */\r
+#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */\r
+#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */\r
+#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */\r
+#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */\r
+#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */\r
+#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */\r
+#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */\r
+#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */\r
+#endif /* End #defines for C */\r
+\r
+/************************************************************\r
+* PERIPHERAL FILE MAP\r
+************************************************************/\r
+\r
+\r
+/*****************************************************************************\r
+ ADC Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_ADC__ /* Definition to show that module is available */\r
+#define __MSP430_BASEADDRESS_ADC__ 0x0700\r
+#define ADC_BASE __MSP430_BASEADDRESS_ADC__\r
+\r
+sfr_w(ADCCTL0); /* ADC Control 0 */\r
+sfr_b(ADCCTL0_L);\r
+sfr_b(ADCCTL0_H);\r
+sfr_w(ADCCTL1); /* ADC Control 1 */\r
+sfr_b(ADCCTL1_L);\r
+sfr_b(ADCCTL1_H);\r
+sfr_w(ADCCTL2); /* ADC Control 2 */\r
+sfr_b(ADCCTL2_L);\r
+sfr_b(ADCCTL2_H);\r
+sfr_w(ADCLO); /* ADC Window Comparator Low Threshold Register */\r
+sfr_b(ADCLO_L);\r
+sfr_b(ADCLO_H);\r
+sfr_w(ADCHI); /* ADC Window Comparator High Threshold Register */\r
+sfr_b(ADCHI_L);\r
+sfr_b(ADCHI_H);\r
+sfr_w(ADCMCTL0); /* ADC Conversion Memory Control Register */\r
+sfr_b(ADCMCTL0_L);\r
+sfr_b(ADCMCTL0_H);\r
+sfr_w(ADCMEM0); /* ADC Conversion Memory Register */\r
+sfr_b(ADCMEM0_L);\r
+sfr_b(ADCMEM0_H);\r
+sfr_w(ADCIE); /* ADC Interrupt Enable 0 */\r
+sfr_b(ADCIE_L);\r
+sfr_b(ADCIE_H);\r
+sfr_w(ADCIFG); /* ADC Interrupt Flag */\r
+sfr_b(ADCIFG_L);\r
+sfr_b(ADCIFG_H);\r
+sfr_w(ADCIV); /* ADC Interrupt Vector */\r
+sfr_b(ADCIV_L);\r
+sfr_b(ADCIV_H);\r
+\r
+/* ADC Register Offsets */\r
+#define OFS_ADCCTL0 (0x0000)\r
+#define OFS_ADCCTL1 (0x0002)\r
+#define OFS_ADCCTL2 (0x0004)\r
+#define OFS_ADCLO (0x0006)\r
+#define OFS_ADCHI (0x0008)\r
+#define OFS_ADCMCTL0 (0x000A)\r
+#define OFS_ADCMEM0 (0x0012)\r
+#define OFS_ADCIE (0x001A)\r
+#define OFS_ADCIFG (0x001C)\r
+#define OFS_ADCIV (0x001E)\r
+\r
+/* ADC Control Bits */\r
+\r
+/* ADCCTL0 Control Bits */\r
+#define ADCSC (0x0001) /* start conversion */\r
+#define ADCSC_0 (0x0000) /* No sample-and-conversion-start */\r
+#define ADCSC_1 (0x0001) /* Start sample-and-conversion */\r
+#define ADCENC (0x0002) /* enable conversion */\r
+#define ADCENC_0 (0x0000) /* ADC disabled */\r
+#define ADCENC_1 (0x0002) /* ADC enabled */\r
+#define ADCON (0x0010) /* ADC on */\r
+#define ADCON_0 (0x0000) /* ADC off */\r
+#define ADCON_1 (0x0010) /* ADC on */\r
+#define ADCMSC (0x0080) /* sample-and-hold time. */\r
+#define ADCMSC_0 (0x0000) /* The sampling timer requires a rising edge of the SHI signal to\r
+ trigger each sample-and-convert. */\r
+#define ADCMSC_1 (0x0080) /* The incidence of a positive(or for devices first rising edge \r
+ of the) SHI signal triggers the sampling timer, but further \r
+ sample-and-conversions are performed automatically as soon as \r
+ the prior conversion is completed. */\r
+#define ADCSHT (0x0f00) /* sample-and-hold time. */\r
+#define ADCSHT0 (0x0100) /* sample-and-hold time. */\r
+#define ADCSHT1 (0x0200) /* sample-and-hold time. */\r
+#define ADCSHT2 (0x0400) /* sample-and-hold time. */\r
+#define ADCSHT3 (0x0800) /* sample-and-hold time. */\r
+#define ADCSHT_0 (0x0000) /* 4 ADCCLK cycles */\r
+#define ADCSHT_1 (0x0100) /* 8 ADCCLK cycles */\r
+#define ADCSHT_2 (0x0200) /* 16 ADCCLK cycles */\r
+#define ADCSHT_3 (0x0300) /* 32 ADCCLK cycles */\r
+#define ADCSHT_4 (0x0400) /* 64 ADCCLK cycles */\r
+#define ADCSHT_5 (0x0500) /* 96 ADCCLK cycles */\r
+#define ADCSHT_6 (0x0600) /* 128 ADCCLK cycles */\r
+#define ADCSHT_7 (0x0700) /* 192 ADCCLK cycles */\r
+#define ADCSHT_8 (0x0800) /* 256 ADCCLK cycles */\r
+#define ADCSHT_9 (0x0900) /* 384 ADCCLK cycles */\r
+#define ADCSHT_10 (0x0a00) /* 512 ADCCLK cycles */\r
+#define ADCSHT_11 (0x0b00) /* 768 ADCCLK cycles */\r
+#define ADCSHT_12 (0x0c00) /* 1024 ADCCLK cycles */\r
+#define ADCSHT_13 (0x0d00) /* 1024 ADCCLK cycles */\r
+#define ADCSHT_14 (0x0e00) /* 1024 ADCCLK cycles */\r
+#define ADCSHT_15 (0x0f00) /* 1024 ADCCLK cycles */\r
+\r
+/* ADCCTL1 Control Bits */\r
+#define ADCBUSY (0x0001) /* ADC busy */\r
+#define ADCBUSY_0 (0x0000) /* No operation is active. */\r
+#define ADCBUSY_1 (0x0001) /* A sequence, sample, or conversion is active. */\r
+#define ADCCONSEQ (0x0006) /* conversion sequence mode select */\r
+#define ADCCONSEQ0 (0x0002) /* conversion sequence mode select */\r
+#define ADCCONSEQ1 (0x0004) /* conversion sequence mode select */\r
+#define ADCCONSEQ_0 (0x0000) /* Single-channel, single-conversion */\r
+#define ADCCONSEQ_1 (0x0002) /* Sequence-of-channels */\r
+#define ADCCONSEQ_2 (0x0004) /* Repeat-single-channel */\r
+#define ADCCONSEQ_3 (0x0006) /* Repeat-sequence-of-channels */\r
+#define ADCSSEL (0x0018) /* clock source select */\r
+#define ADCSSEL0 (0x0008) /* clock source select */\r
+#define ADCSSEL1 (0x0010) /* clock source select */\r
+#define ADCSSEL_0 (0x0000) /* ADCOSC (MODOSC) */\r
+#define ADCSSEL_1 (0x0008) /* ACLK */\r
+#define ADCSSEL_2 (0x0010) /* MCLK */\r
+#define ADCSSEL_3 (0x0018) /* SMCLK */\r
+#define ADCDIV (0x00e0) /* clock divider */\r
+#define ADCDIV0 (0x0020) /* clock divider */\r
+#define ADCDIV1 (0x0040) /* clock divider */\r
+#define ADCDIV2 (0x0080) /* clock divider */\r
+#define ADCDIV_0 (0x0000) /* /1 */\r
+#define ADCDIV_1 (0x0020) /* /2 */\r
+#define ADCDIV_2 (0x0040) /* /3 */\r
+#define ADCDIV_3 (0x0060) /* /4 */\r
+#define ADCDIV_4 (0x0080) /* /5 */\r
+#define ADCDIV_5 (0x00a0) /* /6 */\r
+#define ADCDIV_6 (0x00c0) /* /7 */\r
+#define ADCDIV_7 (0x00e0) /* /8 */\r
+#define ADCISSH (0x0100) /* invert signal sample-and-hold */\r
+#define ADCISSH_0 (0x0000) /* The sample-input signal is not inverted. */\r
+#define ADCISSH_1 (0x0100) /* The sample-input signal is inverted. */\r
+#define ADCSHP (0x0200) /* sample-and-hold pulse-mode select */\r
+#define ADCSHP_0 (0x0000) /* SAMPCON signal is sourced from the sample-input signal. */\r
+#define ADCSHP_1 (0x0200) /* SAMPCON signal is sourced from the sampling timer. */\r
+#define ADCSHS (0x0c00) /* sample-and-hold source select */\r
+#define ADCSHS0 (0x0400) /* sample-and-hold source select */\r
+#define ADCSHS1 (0x0800) /* sample-and-hold source select */\r
+#define ADCSHS_0 (0x0000) /* ADCSC bit */\r
+#define ADCSHS_1 (0x0400) /* see the device-specific data sheet for source */\r
+#define ADCSHS_2 (0x0800) /* see the device-specific data sheet for source */\r
+#define ADCSHS_3 (0x0c00) /* see the device-specific data sheet for source */\r
+\r
+/* ADCCTL2 Control Bits */\r
+#define ADCDF (0x0008) /* data read-back format */\r
+#define ADCDF_0 (0x0000) /* Binary unsigned. Theoretically the analog input voltage V(REF)\r
+ results in 0000h, the analog input voltage +V(REF) results in \r
+ 03FFh. */\r
+#define ADCDF_1 (0x0008) /* Signed binary (2s complement), left aligned. Theoretically the\r
+ analog input voltage V(REF) results in 8000h, the analog input\r
+ voltage +V(REF) results in 7FC0h. */\r
+#define ADCRES (0x0030) /* resolution */\r
+#define ADCRES0 (0x0010) /* resolution */\r
+#define ADCRES1 (0x0020) /* resolution */\r
+#define ADCRES_0 (0x0000) /* 8 bit */\r
+#define ADCRES_1 (0x0010) /* 10 bit */\r
+#define ADCRES_2 (0x0020) /* 12 bit */\r
+#define ADCRES_3 (0x0030) /* Reserved */\r
+#define ADCSR (0x0004) /* ADC sampling rate. */\r
+#define ADCPDIV (0x0300) /* */\r
+#define ADCPDIV0 (0x0100) /* */\r
+#define ADCPDIV1 (0x0200) /* */\r
+#define ADCPDIV_0 (0x0000) /* Predivide by 1 */\r
+#define ADCPDIV_1 (0x0100) /* Predivide by 4 */\r
+#define ADCPDIV_2 (0x0200) /* Predivide by 64 */\r
+#define ADCPDIV_3 (0x0300) /* Reserved */\r
+#define ADCPDIV__1 (0x0000) /* Predivide by 1 */\r
+#define ADCPDIV__4 (0x0100) /* Predivide by 4 */\r
+#define ADCPDIV__64 (0x0200) /* Predivide by 64 */\r
+\r
+/* ADCMCTL0 Control Bits */\r
+#define ADCINCH (0x000f) /* Input channel select */\r
+#define ADCINCH0 (0x0001) /* Input channel select */\r
+#define ADCINCH1 (0x0002) /* Input channel select */\r
+#define ADCINCH2 (0x0004) /* Input channel select */\r
+#define ADCINCH3 (0x0008) /* Input channel select */\r
+#define ADCINCH_0 (0x0000) /* A0 - see device-specific data sheet */\r
+#define ADCINCH_1 (0x0001) /* A1 - see device-specific data sheet */\r
+#define ADCINCH_2 (0x0002) /* A2 - see device-specific data sheet */\r
+#define ADCINCH_3 (0x0003) /* A3 - see device-specific data sheet */\r
+#define ADCINCH_4 (0x0004) /* A4 - see device-specific data sheet */\r
+#define ADCINCH_5 (0x0005) /* A5 - see device-specific data sheet */\r
+#define ADCINCH_6 (0x0006) /* A2 - see device-specific data sheet */\r
+#define ADCINCH_7 (0x0007) /* A7 - see device-specific data sheet */\r
+#define ADCINCH_8 (0x0008) /* A8 - see device-specific data sheet */\r
+#define ADCINCH_9 (0x0009) /* A9 - see device-specific data sheet */\r
+#define ADCINCH_10 (0x000a) /* A10 - see device-specific data sheet */\r
+#define ADCINCH_11 (0x000b) /* A11 - see device-specific data sheet */\r
+#define ADCINCH_12 (0x000c) /* A12 - see device-specific data sheet */\r
+#define ADCINCH_13 (0x000d) /* A13 - see device-specific data sheet */\r
+#define ADCINCH_14 (0x000e) /* A14 - see device-specific data sheet */\r
+#define ADCINCH_15 (0x000f) /* A15 - see device-specific data sheet */\r
+#define ADCSREF (0x0070) /* */\r
+#define ADCSREF0 (0x0010) /* */\r
+#define ADCSREF1 (0x0020) /* */\r
+#define ADCSREF2 (0x0040) /* */\r
+#define ADCSREF_0 (0x0000) /* 000b = V(R+) = AVCC and V(R-) = AVSS */\r
+#define ADCSREF_1 (0x0010) /* 001b = V(R+) = VREF and V(R-) = AVSS */\r
+#define ADCSREF_2 (0x0020) /* 010b = V(R+) = VEREF+ buffered and V(R-) = AVSS */\r
+#define ADCSREF_3 (0x0030) /* 011b =V(R+) = VEREF+ and V(R-) = AVSS */\r
+#define ADCSREF_4 (0x0040) /* 100b = V(R+) = AVCC and V(R-) = VEREF- */\r
+#define ADCSREF_5 (0x0050) /* 101b = V(R+) = VREF and V(R-) = VEREF- */\r
+#define ADCSREF_6 (0x0060) /* 110b = V(R+) = VEREF+ buffered and V(R-) = VEREF- */\r
+#define ADCSREF_7 (0x0070) /* 111b = V(R+) = VEREF+ and V(R-) = VEREF- */\r
+#define EXPCHEN (0x0100) /* */\r
+#define EXPCHEN_0 (0x0000) /* ADC channel expanded disable */\r
+#define EXPCHEN_1 (0x0100) /* ADC channel expanded enable */\r
+\r
+/* ADCMEM0 Control Bits */\r
+#define CONVERSION_RESULTS (0xffff) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS0 (0x0001) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS1 (0x0002) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS2 (0x0004) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS3 (0x0008) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS4 (0x0010) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS5 (0x0020) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS6 (0x0040) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS7 (0x0080) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS8 (0x0100) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS9 (0x0200) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS10 (0x0400) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS11 (0x0800) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS12 (0x1000) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS13 (0x2000) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS14 (0x4000) /* Conversion Results/Reset Value is undefined */\r
+#define CONVERSION_RESULTS15 (0x8000) /* Conversion Results/Reset Value is undefined */\r
+\r
+/* ADCIE Control Bits */\r
+#define ADCIE0 (0x0001) /* */\r
+#define ADCIE0_0 (0x0000) /* 0b = Interrupt disabled */\r
+#define ADCIE0_1 (0x0001) /* 1b = Interrupt enabled */\r
+#define ADCINIE (0x0002) /* */\r
+#define ADCINIE_0 (0x0000) /* 0b = Inside of window interrupt disabled */\r
+#define ADCINIE_1 (0x0002) /* 1b = Inside of window interrupt enabled */\r
+#define ADCLOIE (0x0004) /* */\r
+#define ADCLOIE_0 (0x0000) /* 0b = Below lower threshold interrupt disabled */\r
+#define ADCLOIE_1 (0x0004) /* 1b = Below lower threshold interrupt enabled */\r
+#define ADCHIIE (0x0008) /* */\r
+#define ADCHIIE_0 (0x0000) /* 0b = Above upper threshold interrupt disabled */\r
+#define ADCHIIE_1 (0x0008) /* 1b = Above upper threshold interrupt enabled */\r
+#define ADCOVIE (0x0010) /* */\r
+#define ADCOVIE_0 (0x0000) /* 0b = Overflow interrupt disabled */\r
+#define ADCOVIE_1 (0x0010) /* 1b = Overflow interrupt enabled */\r
+#define ADCTOVIE (0x0020) /* */\r
+#define ADCTOVIE_0 (0x0000) /* 0b = Conversion time overflow interrupt disabled */\r
+#define ADCTOVIE_1 (0x0020) /* 1b = Conversion time overflow interrupt enabled */\r
+\r
+/* ADCIFG Control Bits */\r
+#define ADCIFG0 (0x0001) /* ADCMEM0 interrupt flag */\r
+#define ADCIFG0_0 (0x0000) /* No interrupt pending */\r
+#define ADCIFG0_1 (0x0001) /* Interrupt pending */\r
+#define ADCINIFG (0x0002) /* */\r
+#define ADCINIFG_0 (0x0000) /* No interrupt pending */\r
+#define ADCINIFG_1 (0x0002) /* Interrupt pending */\r
+#define ADCLOIFG (0x0004) /* */\r
+#define ADCLOIFG_0 (0x0000) /* No interrupt pending */\r
+#define ADCLOIFG_1 (0x0004) /* Interrupt pending */\r
+#define ADCHIIFG (0x0008) /* */\r
+#define ADCHIIFG_0 (0x0000) /* No interrupt pending */\r
+#define ADCHIIFG_1 (0x0008) /* Interrupt pending */\r
+#define ADCOVIFG (0x0010) /* */\r
+#define ADCOVIFG_0 (0x0000) /* No interrupt pending */\r
+#define ADCOVIFG_1 (0x0010) /* Interrupt pending */\r
+#define ADCTOVIFG (0x0020) /* */\r
+#define ADCTOVIFG_1 (0x0020) /* Interrupt pending */\r
+\r
+/* ADCIV Control Bits */\r
+#define ADCIV0 (0x0001) /* interrupt vector value */\r
+#define ADCIV1 (0x0002) /* interrupt vector value */\r
+#define ADCIV2 (0x0004) /* interrupt vector value */\r
+#define ADCIV3 (0x0008) /* interrupt vector value */\r
+#define ADCIV4 (0x0010) /* interrupt vector value */\r
+#define ADCIV5 (0x0020) /* interrupt vector value */\r
+#define ADCIV6 (0x0040) /* interrupt vector value */\r
+#define ADCIV7 (0x0080) /* interrupt vector value */\r
+#define ADCIV8 (0x0100) /* interrupt vector value */\r
+#define ADCIV9 (0x0200) /* interrupt vector value */\r
+#define ADCIV10 (0x0400) /* interrupt vector value */\r
+#define ADCIV11 (0x0800) /* interrupt vector value */\r
+#define ADCIV12 (0x1000) /* interrupt vector value */\r
+#define ADCIV13 (0x2000) /* interrupt vector value */\r
+#define ADCIV14 (0x4000) /* interrupt vector value */\r
+#define ADCIV15 (0x8000) /* interrupt vector value */\r
+#define ADCIV_0 (0x0000) /* No interrupt pending */\r
+#define ADCIV_2 (0x0002) /* Interrupt Source: ADCMEM0 overflow; Interrupt Flag: ADCOVIFG; \r
+ Interrupt Priority: Highest */\r
+#define ADCIV_4 (0x0004) /* Interrupt Source: Conversion time overflow; Interrupt Flag: \r
+ ADCTOVIFG */\r
+#define ADCIV_6 (0x0006) /* Interrupt Source: ADCHI Interrupt flag; Interrupt Flag: \r
+ ADCHIIFG */\r
+#define ADCIV_8 (0x0008) /* Interrupt Source: ADCLO Interrupt flag; Interrupt Flag: \r
+ ADCLOIFG */\r
+#define ADCIV_10 (0x000a) /* nterrupt Source: ADCIN Interrupt flag; Interrupt Flag: \r
+ ADCINIFG */\r
+#define ADCIV_12 (0x000c) /* Interrupt Source: ADC memory Interrupt flag; Interrupt Flag: \r
+ ADCIFG0; Interrupt Priority: Lowest */\r
+#define ADCIV__NONE (0x0000) /* No interrupt pending */\r
+#define ADCIV__ADCOVIFG (0x0002) /* Interrupt Source: ADCMEM0 overflow; Interrupt Flag: ADCOVIFG; \r
+ Interrupt Priority: Highest */\r
+#define ADCIV__ADCTOVIFG (0x0004) /* Interrupt Source: Conversion time overflow; Interrupt Flag: \r
+ ADCTOVIFG */\r
+#define ADCIV__ADCHIIFG (0x0006) /* Interrupt Source: ADCHI Interrupt flag; Interrupt Flag: \r
+ ADCHIIFG */\r
+#define ADCIV__ADCLOIFG (0x0008) /* Interrupt Source: ADCLO Interrupt flag; Interrupt Flag: \r
+ ADCLOIFG */\r
+#define ADCIV__ADCINIFG (0x000a) /* nterrupt Source: ADCIN Interrupt flag; Interrupt Flag: \r
+ ADCINIFG */\r
+#define ADCIV__ADCIFG0 (0x000c) /* Interrupt Source: ADC memory Interrupt flag; Interrupt Flag: \r
+ ADCIFG0; Interrupt Priority: Lowest */\r
+\r
+\r
+/*****************************************************************************\r
+ BKMEM Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_BKMEM__ /* Definition to show that module is available */\r
+#define __MSP430_BASEADDRESS_BKMEM__ 0x0660\r
+#define BKMEM_BASE __MSP430_BASEADDRESS_BKMEM__\r
+\r
+sfr_w(BAKMEM0); /* Backup Memory registers. Backup Memory 0. */\r
+sfr_b(BAKMEM0_L);\r
+sfr_b(BAKMEM0_H);\r
+sfr_w(BAKMEM1); /* Backup Memory 1. */\r
+sfr_b(BAKMEM1_L);\r
+sfr_b(BAKMEM1_H);\r
+sfr_w(BAKMEM2); /* Backup Memory 2. */\r
+sfr_b(BAKMEM2_L);\r
+sfr_b(BAKMEM2_H);\r
+sfr_w(BAKMEM3); /* Backup Memory 3. */\r
+sfr_b(BAKMEM3_L);\r
+sfr_b(BAKMEM3_H);\r
+sfr_w(BAKMEM4); /* Backup Memory 4. */\r
+sfr_b(BAKMEM4_L);\r
+sfr_b(BAKMEM4_H);\r
+sfr_w(BAKMEM5); /* Backup Memory 5. */\r
+sfr_b(BAKMEM5_L);\r
+sfr_b(BAKMEM5_H);\r
+sfr_w(BAKMEM6); /* Backup Memory 6. */\r
+sfr_b(BAKMEM6_L);\r
+sfr_b(BAKMEM6_H);\r
+sfr_w(BAKMEM7); /* Backup Memory 7. */\r
+sfr_b(BAKMEM7_L);\r
+sfr_b(BAKMEM7_H);\r
+sfr_w(BAKMEM8); /* Backup Memory 8. */\r
+sfr_b(BAKMEM8_L);\r
+sfr_b(BAKMEM8_H);\r
+sfr_w(BAKMEM9); /* Backup Memory 9. */\r
+sfr_b(BAKMEM9_L);\r
+sfr_b(BAKMEM9_H);\r
+sfr_w(BAKMEM10); /* Backup Memory registers. Backup Memory 10. */\r
+sfr_b(BAKMEM10_L);\r
+sfr_b(BAKMEM10_H);\r
+sfr_w(BAKMEM11); /* Backup Memory 11. */\r
+sfr_b(BAKMEM11_L);\r
+sfr_b(BAKMEM11_H);\r
+sfr_w(BAKMEM12); /* Backup Memory 12. */\r
+sfr_b(BAKMEM12_L);\r
+sfr_b(BAKMEM12_H);\r
+sfr_w(BAKMEM13); /* Backup Memory 13. */\r
+sfr_b(BAKMEM13_L);\r
+sfr_b(BAKMEM13_H);\r
+sfr_w(BAKMEM14); /* Backup Memory 14. */\r
+sfr_b(BAKMEM14_L);\r
+sfr_b(BAKMEM14_H);\r
+sfr_w(BAKMEM15); /* Backup Memory 15. */\r
+sfr_b(BAKMEM15_L);\r
+sfr_b(BAKMEM15_H);\r
+\r
+/* BKMEM Register Offsets */\r
+#define OFS_BAKMEM0 (0x0000)\r
+#define OFS_BAKMEM1 (0x0002)\r
+#define OFS_BAKMEM2 (0x0004)\r
+#define OFS_BAKMEM3 (0x0006)\r
+#define OFS_BAKMEM4 (0x0008)\r
+#define OFS_BAKMEM5 (0x000A)\r
+#define OFS_BAKMEM6 (0x000C)\r
+#define OFS_BAKMEM7 (0x000E)\r
+#define OFS_BAKMEM8 (0x0010)\r
+#define OFS_BAKMEM9 (0x0012)\r
+#define OFS_BAKMEM10 (0x0014)\r
+#define OFS_BAKMEM11 (0x0016)\r
+#define OFS_BAKMEM12 (0x0018)\r
+#define OFS_BAKMEM13 (0x001A)\r
+#define OFS_BAKMEM14 (0x001C)\r
+#define OFS_BAKMEM15 (0x001E)\r
+\r
+/* No control bits available or already defined for another module */\r
+\r
+/*****************************************************************************\r
+ CRC Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_CRC__ /* Definition to show that module is available */\r
+#define __MSP430_BASEADDRESS_CRC__ 0x01C0\r
+#define CRC_BASE __MSP430_BASEADDRESS_CRC__\r
+\r
+sfr_w(CRCDI); /* CRC Data In */\r
+sfr_b(CRCDI_L);\r
+sfr_b(CRCDI_H);\r
+sfr_w(CRCDIRB); /* CRC Data In Reverse Byte */\r
+sfr_b(CRCDIRB_L);\r
+sfr_b(CRCDIRB_H);\r
+sfr_w(CRCINIRES); /* CRC Initialization and Result */\r
+sfr_b(CRCINIRES_L);\r
+sfr_b(CRCINIRES_H);\r
+sfr_w(CRCRESR); /* CRC Result Reverse */\r
+sfr_b(CRCRESR_L);\r
+sfr_b(CRCRESR_H);\r
+\r
+/* CRC Register Offsets */\r
+#define OFS_CRCDI (0x0000)\r
+#define OFS_CRCDIRB (0x0002)\r
+#define OFS_CRCINIRES (0x0004)\r
+#define OFS_CRCRESR (0x0006)\r
+\r
+/* No control bits available or already defined for another module */\r
+\r
+/*****************************************************************************\r
+ CS Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_CS__ /* Definition to show that module is available */\r
+#define __MSP430_BASEADDRESS_CS__ 0x0180\r
+#define CS_BASE __MSP430_BASEADDRESS_CS__\r
+\r
+sfr_w(CSCTL0); /* Clock System Control 0 */\r
+sfr_b(CSCTL0_L);\r
+sfr_b(CSCTL0_H);\r
+sfr_w(CSCTL1); /* Clock System Control 1 */\r
+sfr_b(CSCTL1_L);\r
+sfr_b(CSCTL1_H);\r
+sfr_w(CSCTL2); /* Clock System Control 2 */\r
+sfr_b(CSCTL2_L);\r
+sfr_b(CSCTL2_H);\r
+sfr_w(CSCTL3); /* Clock System Control 3 */\r
+sfr_b(CSCTL3_L);\r
+sfr_b(CSCTL3_H);\r
+sfr_w(CSCTL4); /* Clock System Control 4 */\r
+sfr_b(CSCTL4_L);\r
+sfr_b(CSCTL4_H);\r
+sfr_w(CSCTL5); /* Clock System Control 5 */\r
+sfr_b(CSCTL5_L);\r
+sfr_b(CSCTL5_H);\r
+sfr_w(CSCTL6); /* Clock System Control 6 */\r
+sfr_b(CSCTL6_L);\r
+sfr_b(CSCTL6_H);\r
+sfr_w(CSCTL7); /* Clock System Control Register 7 */\r
+sfr_b(CSCTL7_L);\r
+sfr_b(CSCTL7_H);\r
+sfr_w(CSCTL8); /* Clock System Control Register 8 */\r
+sfr_b(CSCTL8_L);\r
+sfr_b(CSCTL8_H);\r
+\r
+/* CS Register Offsets */\r
+#define OFS_CSCTL0 (0x0000)\r
+#define OFS_CSCTL1 (0x0002)\r
+#define OFS_CSCTL2 (0x0004)\r
+#define OFS_CSCTL3 (0x0006)\r
+#define OFS_CSCTL4 (0x0008)\r
+#define OFS_CSCTL5 (0x000A)\r
+#define OFS_CSCTL6 (0x000C)\r
+#define OFS_CSCTL7 (0x000E)\r
+#define OFS_CSCTL8 (0x0010)\r
+\r
+/* CS Control Bits */\r
+\r
+/* CSCTL0 Control Bits */\r
+#define DCO (0x01ff) /* */\r
+#define DCO0 (0x0001) /* */\r
+#define DCO1 (0x0002) /* */\r
+#define DCO2 (0x0004) /* */\r
+#define DCO3 (0x0008) /* */\r
+#define DCO4 (0x0010) /* */\r
+#define DCO5 (0x0020) /* */\r
+#define DCO6 (0x0040) /* */\r
+#define DCO7 (0x0080) /* */\r
+#define DCO8 (0x0100) /* */\r
+#define MOD (0x3e00) /* */\r
+#define MOD0 (0x0200) /* */\r
+#define MOD1 (0x0400) /* */\r
+#define MOD2 (0x0800) /* */\r
+#define MOD3 (0x1000) /* */\r
+#define MOD4 (0x2000) /* */\r
+\r
+/* CSCTL1 Control Bits */\r
+#define DISMOD (0x0001) /* */\r
+#define DISMOD_0 (0x0000) /* Modulation enabled */\r
+#define DISMOD_1 (0x0001) /* Modulation disabled */\r
+#define DCORSEL (0x000e) /* */\r
+#define DCORSEL0 (0x0002) /* */\r
+#define DCORSEL1 (0x0004) /* */\r
+#define DCORSEL2 (0x0008) /* */\r
+#define DCORSEL_0 (0x0000) /* 1 MHz */\r
+#define DCORSEL_1 (0x0002) /* 2 MHz */\r
+#define DCORSEL_2 (0x0004) /* 4 MHz */\r
+#define DCORSEL_3 (0x0006) /* 8 MHz */\r
+#define DCORSEL_4 (0x0008) /* 12 MHz */\r
+#define DCORSEL_5 (0x000a) /* 16 MHz */\r
+#define DCORSEL_6 (0x000c) /* 20 MHz(Only avaliable in 24MHz clock system) */\r
+#define DCORSEL_7 (0x000e) /* 24 MHz(Only avaliable in 24MHz clock system) */\r
+#define DCOFTRIM (0x0070) /* */\r
+#define DCOFTRIM0 (0x0010) /* */\r
+#define DCOFTRIM1 (0x0020) /* */\r
+#define DCOFTRIM2 (0x0040) /* */\r
+#define DCOFTRIMEN (0x0080) /* */\r
+#define DCOFTRIMEN_0 (0x0000) /* Disable frequency trim */\r
+#define DCOFTRIMEN_1 (0x0080) /* Enable frequency trim */\r
+\r
+/* CSCTL2 Control Bits */\r
+#define FLLN (0x03ff) /* */\r
+#define FLLN0 (0x0001) /* */\r
+#define FLLN1 (0x0002) /* */\r
+#define FLLN2 (0x0004) /* */\r
+#define FLLN3 (0x0008) /* */\r
+#define FLLN4 (0x0010) /* */\r
+#define FLLN5 (0x0020) /* */\r
+#define FLLN6 (0x0040) /* */\r
+#define FLLN7 (0x0080) /* */\r
+#define FLLN8 (0x0100) /* */\r
+#define FLLN9 (0x0200) /* */\r
+#define FLLD (0x7000) /* */\r
+#define FLLD0 (0x1000) /* */\r
+#define FLLD1 (0x2000) /* */\r
+#define FLLD2 (0x4000) /* */\r
+#define FLLD_0 (0x0000) /* fDCOCLK / 1 */\r
+#define FLLD_1 (0x1000) /* fDCOCLK / 2 */\r
+#define FLLD_2 (0x2000) /* fDCOCLK / 4 */\r
+#define FLLD_3 (0x3000) /* fDCOCLK / 8 */\r
+#define FLLD_4 (0x4000) /* fDCOCLK / 16 */\r
+#define FLLD_5 (0x5000) /* fDCOCLK / 32 */\r
+#define FLLD_6 (0x6000) /* fDCOCLK / 40(Only avaliable in 24MHz clock system) */\r
+#define FLLD_7 (0x7000) /* fDCOCLK / 48(Only avaliable in 24MHz clock system) */\r
+#define FLLD__1 (0x0000) /* fDCOCLK / 1 */\r
+#define FLLD__2 (0x1000) /* fDCOCLK / 2 */\r
+#define FLLD__4 (0x2000) /* fDCOCLK / 4 */\r
+#define FLLD__8 (0x3000) /* fDCOCLK / 8 */\r
+#define FLLD__16 (0x4000) /* fDCOCLK / 16 */\r
+#define FLLD__32 (0x5000) /* fDCOCLK / 32 */\r
+\r
+/* CSCTL3 Control Bits */\r
+#define FLLREFDIV (0x0007) /* */\r
+#define FLLREFDIV0 (0x0001) /* */\r
+#define FLLREFDIV1 (0x0002) /* */\r
+#define FLLREFDIV2 (0x0004) /* */\r
+#define FLLREFDIV_0 (0x0000) /* fFLLREFCLK / 1 */\r
+#define FLLREFDIV_1 (0x0001) /* fFLLREFCLK / 32 */\r
+#define FLLREFDIV_2 (0x0002) /* fFLLREFCLK / 64 */\r
+#define FLLREFDIV_3 (0x0003) /* fFLLREFCLK / 128 */\r
+#define FLLREFDIV_4 (0x0004) /* fFLLREFCLK / 256 */\r
+#define FLLREFDIV_5 (0x0005) /* fFLLREFCLK / 512 */\r
+#define FLLREFDIV_6 (0x0006) /* fFLLREFCLK / 640 (only available in 24MHz clock system) */\r
+#define FLLREFDIV_7 (0x0007) /* fFLLREFCLK / 768(only available in 24MHz clock system) */\r
+#define FLLREFDIV__1 (0x0000) /* fFLLREFCLK / 1 */\r
+#define FLLREFDIV__32 (0x0001) /* fFLLREFCLK / 32 */\r
+#define FLLREFDIV__64 (0x0002) /* fFLLREFCLK / 64 */\r
+#define FLLREFDIV__128 (0x0003) /* fFLLREFCLK / 128 */\r
+#define FLLREFDIV__256 (0x0004) /* fFLLREFCLK / 256 */\r
+#define FLLREFDIV__512 (0x0005) /* fFLLREFCLK / 512 */\r
+#define SELREF (0x0030) /* */\r
+#define SELREF0 (0x0010) /* */\r
+#define SELREF1 (0x0020) /* */\r
+#define SELREF_0 (0x0000) /* XT1CLK */\r
+#define SELREF_1 (0x0010) /* REFOCLK */\r
+#define SELREF_2 (0x0020) /* served for future use */\r
+#define SELREF_3 (0x0030) /* served for future use */\r
+#define SELREF__XT1CLK (0x0000) /* XT1CLK */\r
+#define SELREF__REFOCLK (0x0010) /* REFOCLK */\r
+#define REFOLP (0x0080) /* */\r
+#define REFOLP_0 (0x0000) /* REFO Low Power Disabled (High Power Mode) */\r
+#define REFOLP_1 (0x0080) /* REFO Low Power Enabled */\r
+\r
+/* CSCTL4 Control Bits */\r
+#define SELMS (0x0007) /* */\r
+#define SELMS0 (0x0001) /* */\r
+#define SELMS1 (0x0002) /* */\r
+#define SELMS2 (0x0004) /* */\r
+#define SELMS_0 (0x0000) /* DCOCLKDIV */\r
+#define SELMS_1 (0x0001) /* REFOCLK */\r
+#define SELMS_2 (0x0002) /* XT1CLK */\r
+#define SELMS_3 (0x0003) /* VLOCLK */\r
+#define SELMS_4 (0x0004) /* Reserved for future use */\r
+#define SELMS_5 (0x0005) /* Reserved for future use */\r
+#define SELMS_6 (0x0006) /* Reserved for future use */\r
+#define SELMS_7 (0x0007) /* Reserved for future use */\r
+#define SELMS__DCOCLKDIV (0x0000) /* DCOCLKDIV */\r
+#define SELMS__REFOCLK (0x0001) /* REFOCLK */\r
+#define SELMS__XT1CLK (0x0002) /* XT1CLK */\r
+#define SELMS__VLOCLK (0x0003) /* VLOCLK */\r
+#define SELA (0x0300) /* */\r
+#define SELA0 (0x0100) /* */\r
+#define SELA1 (0x0200) /* */\r
+#define SELA_0 (0x0000) /* XT1CLK with divider (must be no more than 40 kHz) */\r
+#define SELA_1 (0x0100) /* REFO (internal 32-kHz clock source) */\r
+#define SELA_2 (0x0200) /* VLO (internal 10-kHz clock source) */\r
+#define SELA_3 (0x0300) /* Reserved */\r
+#define SELA__XT1CLK (0x0000) /* XT1CLK with divider (must be no more than 40 kHz) */\r
+#define SELA__REFOCLK (0x0100) /* REFO (internal 32-kHz clock source) */\r
+#define SELA__VLOCLK (0x0200) /* VLO (internal 10-kHz clock source) */\r
+#define SELA__RESERVED (0x0300) /* Reserved */\r
+\r
+/* CSCTL5 Control Bits */\r
+#define DIVM (0x0007) /* */\r
+#define DIVM0 (0x0001) /* */\r
+#define DIVM1 (0x0002) /* */\r
+#define DIVM2 (0x0004) /* */\r
+#define DIVM_0 (0x0000) /* /1 */\r
+#define DIVM_1 (0x0001) /* /2 */\r
+#define DIVM_2 (0x0002) /* /4 */\r
+#define DIVM_3 (0x0003) /* /8 */\r
+#define DIVM_4 (0x0004) /* /16 */\r
+#define DIVM_5 (0x0005) /* /32 */\r
+#define DIVM_6 (0x0006) /* /64 */\r
+#define DIVM_7 (0x0007) /* /128 */\r
+#define DIVM__1 (0x0000) /* /1 */\r
+#define DIVM__2 (0x0001) /* /2 */\r
+#define DIVM__4 (0x0002) /* /4 */\r
+#define DIVM__8 (0x0003) /* /8 */\r
+#define DIVM__16 (0x0004) /* /16 */\r
+#define DIVM__32 (0x0005) /* /32 */\r
+#define DIVM__64 (0x0006) /* /64 */\r
+#define DIVM__128 (0x0007) /* /128 */\r
+#define DIVS (0x0030) /* */\r
+#define DIVS0 (0x0010) /* */\r
+#define DIVS1 (0x0020) /* */\r
+#define DIVS_0 (0x0000) /* /1 */\r
+#define DIVS_1 (0x0010) /* /2 */\r
+#define DIVS_2 (0x0020) /* /4 */\r
+#define DIVS_3 (0x0030) /* /8 */\r
+#define DIVS__1 (0x0000) /* /1 */\r
+#define DIVS__2 (0x0010) /* /2 */\r
+#define DIVS__4 (0x0020) /* /4 */\r
+#define DIVS__8 (0x0030) /* /8 */\r
+#define SMCLKOFF (0x0100) /* */\r
+#define SMCLKOFF_0 (0x0000) /* SMCLK on */\r
+#define SMCLKOFF_1 (0x0100) /* SMCLK off */\r
+#define VLOAUTOOFF (0x1000) /* */\r
+#define VLOAUTOOFF_0 (0x0000) /* VLO always on */\r
+#define VLOAUTOOFF_1 (0x1000) /* VLO automatically turned off if not used(default) */\r
+\r
+/* CSCTL6 Control Bits */\r
+#define XT1AUTOOFF (0x0001) /* */\r
+#define XT1AUTOOFF_0 (0x0000) /* XT1 is on if XT1 is selected by the port selection and XT1 is \r
+ not in bypass mode of operation. */\r
+#define XT1AUTOOFF_1 (0x0001) /* XT1 is off if it is not used as a source for ACLK, MCLK, or \r
+ SMCLK or is not used as a reference source required for FLL \r
+ operation. */\r
+#define XT1AGCOFF (0x0002) /* */\r
+#define XT1AGCOFF_0 (0x0000) /* AGC on */\r
+#define XT1AGCOFF_1 (0x0002) /* AGC off */\r
+#define XT1HFFREQ (0x000c) /* */\r
+#define XT1HFFREQ0 (0x0004) /* */\r
+#define XT1HFFREQ1 (0x0008) /* */\r
+#define XT1HFFREQ_0 (0x0000) /* 1 to 4 MHz */\r
+#define XT1HFFREQ_1 (0x0004) /* >4 MHz to 6 MHz */\r
+#define XT1HFFREQ_2 (0x0008) /* >6 MHz to 16 MHz */\r
+#define XT1HFFREQ_3 (0x000c) /* >16 MHz to 24 MHz */\r
+#define XT1BYPASS (0x0010) /* */\r
+#define XT1BYPASS_0 (0x0000) /* XT1 source internally */\r
+#define XT1BYPASS_1 (0x0010) /* XT1 sources externally from pin */\r
+#define XTS (0x0020) /* */\r
+#define XTS_0 (0x0000) /* Low-frequency mode. */\r
+#define XTS_1 (0x0020) /* High-frequency mode. */\r
+#define XT1DRIVE (0x00c0) /* */\r
+#define XT1DRIVE0 (0x0040) /* */\r
+#define XT1DRIVE1 (0x0080) /* */\r
+#define XT1DRIVE_0 (0x0000) /* Lowest drive strength and current consumption */\r
+#define XT1DRIVE_1 (0x0040) /* Lower drive strength and current consumption */\r
+#define XT1DRIVE_2 (0x0080) /* Higher drive strength and current consumption */\r
+#define XT1DRIVE_3 (0x00c0) /* Highest drive strength and current consumption */\r
+#define DIVA (0x0f00) /* */\r
+#define DIVA0 (0x0100) /* */\r
+#define DIVA1 (0x0200) /* */\r
+#define DIVA2 (0x0400) /* */\r
+#define DIVA3 (0x0800) /* */\r
+#define DIVA_0 (0x0000) /* /1 */\r
+#define DIVA_1 (0x0100) /* /16 */\r
+#define DIVA_2 (0x0200) /* /32 */\r
+#define DIVA_3 (0x0300) /* /64 */\r
+#define DIVA_4 (0x0400) /* /128 */\r
+#define DIVA_5 (0x0500) /* /256 */\r
+#define DIVA_6 (0x0600) /* /384 */\r
+#define DIVA_7 (0x0700) /* /512 */\r
+#define DIVA_8 (0x0800) /* /768(Only available in 24MHz clock system, 24 MHz preference) */\r
+#define DIVA_9 (0x0900) /* /1024(Only available in 24MHz clock system, 24 MHz preference) */\r
+#define DIVA_10 (0x0a00) /* /108(Only available in 24MHz clock system, 24 MHz preference) */\r
+#define DIVA_11 (0x0b00) /* 338(Only available in 24MHz clock system, 24 MHz preference) */\r
+#define DIVA_12 (0x0c00) /* 414(Only available in 24MHz clock system, 24 MHz preference) */\r
+#define DIVA_13 (0x0d00) /* 640(Only available in 24MHz clock system, 24 MHz preference) */\r
+#define DIVA_14 (0x0e00) /* Reserved */\r
+#define DIVA_15 (0x0f00) /* Reserved */\r
+#define DIVA__1 (0x0000) /* /1 */\r
+#define DIVA__16 (0x0100) /* /16 */\r
+#define DIVA__32 (0x0200) /* /32 */\r
+#define DIVA__64 (0x0300) /* /64 */\r
+#define DIVA__128 (0x0400) /* /128 */\r
+#define DIVA__256 (0x0500) /* /256 */\r
+#define DIVA__384 (0x0600) /* /384 */\r
+#define DIVA__512 (0x0700) /* /512 */\r
+#define DIVA__768 (0x0800) /* /768(Only available in 24MHz clock system, 24 MHz preference) */\r
+#define DIVA__1024 (0x0900) /* /1024(Only available in 24MHz clock system, 24 MHz preference) */\r
+#define DIVA__108 (0x0a00) /* /108(Only available in 24MHz clock system, 24 MHz preference) */\r
+#define DIVA__338 (0x0b00) /* 338(Only available in 24MHz clock system, 24 MHz preference) */\r
+#define DIVA__414 (0x0c00) /* 414(Only available in 24MHz clock system, 24 MHz preference) */\r
+#define DIVA__640 (0x0d00) /* 640(Only available in 24MHz clock system, 24 MHz preference) */\r
+#define XT1FAULTOFF (0x2000) /* */\r
+#define XT1FAULTOFF_0 (0x0000) /* Enabling XT1 fault to switch ACLK to REFO */\r
+#define XT1FAULTOFF_1 (0x2000) /* Disabling XT1 fault to switch ACLK to REFO */\r
+\r
+/* CSCTL7 Control Bits */\r
+#define REFOREADY (0x0004) /* */\r
+#define REFOREADY_0 (0x0000) /* REFO unstable */\r
+#define REFOREADY_1 (0x0004) /* REFO ready to go */\r
+#define DCOFFG (0x0001) /* */\r
+#define DCOFFG_0 (0x0000) /* No fault condition occurred after the last reset. */\r
+#define DCOFFG_1 (0x0001) /* DCO fault. A DCO fault occurred after the last reset. */\r
+#define XT1OFFG (0x0002) /* */\r
+#define XT1OFFG_0 (0x0000) /* No fault condition occurred after the last reset. */\r
+#define XT1OFFG_1 (0x0002) /* XT1 fault. An XT1 fault occurred after the last reset. */\r
+#define FLLULIFG (0x0010) /* */\r
+#define FLLULIFG_0 (0x0000) /* FLLUNLOCK bits not equal to 10b */\r
+#define FLLULIFG_1 (0x0010) /* FLLUNLOCK bits equal to 10b */\r
+#define ENSTFCNT1 (0x0040) /* */\r
+#define ENSTFCNT1_0 (0x0000) /* Startup fault counter disabled. Counter is cleared.. */\r
+#define ENSTFCNT1_1 (0x0040) /* Startup fault counter enabled. */\r
+#define FLLUNLOCK (0x0300) /* */\r
+#define FLLUNLOCK0 (0x0100) /* */\r
+#define FLLUNLOCK1 (0x0200) /* */\r
+#define FLLUNLOCK_0 (0x0000) /* FLL is locked. No unlock condition currently active. */\r
+#define FLLUNLOCK_1 (0x0100) /* DCOCLK is currently too slow. */\r
+#define FLLUNLOCK_2 (0x0200) /* DCOCLK is currently too fast. */\r
+#define FLLUNLOCK_3 (0x0300) /* DCOERROR. DCO out of range. */\r
+#define FLLUNLOCKHIS (0x0c00) /* */\r
+#define FLLUNLOCKHIS0 (0x0400) /* */\r
+#define FLLUNLOCKHIS1 (0x0800) /* */\r
+#define FLLUNLOCKHIS_0 (0x0000) /* FLL is locked. No unlock situation has been detected since the\r
+ last reset of these bits. */\r
+#define FLLUNLOCKHIS_1 (0x0400) /* DCOCLK has been too slow since the bits were cleared. */\r
+#define FLLUNLOCKHIS_2 (0x0800) /* DCOCLK has been too fast since the bits were cleared. */\r
+#define FLLUNLOCKHIS_3 (0x0c00) /* DCOCLK has been both too fast and too slow since the bits were\r
+ cleared. */\r
+#define FLLULPUC (0x1000) /* */\r
+#define FLLWARNEN (0x2000) /* */\r
+#define FLLWARNEN_0 (0x0000) /* FLLUNLOCKHIS status cannot set OFIFG. */\r
+#define FLLWARNEN_1 (0x2000) /* FLLUNLOCKHIS status can set OFIFG. */\r
+\r
+/* CSCTL8 Control Bits */\r
+#define ACLKREQEN (0x0001) /* */\r
+#define ACLKREQEN_0 (0x0000) /* ACLK conditional requests are disabled. */\r
+#define ACLKREQEN_1 (0x0001) /* ACLK conditional requests are enabled. */\r
+#define MCLKREQEN (0x0002) /* */\r
+#define MCLKREQEN_0 (0x0000) /* MCLK conditional requests are disabled. */\r
+#define MCLKREQEN_1 (0x0002) /* MCLK conditional requests are enabled. */\r
+#define SMCLKREQEN (0x0004) /* */\r
+#define SMCLKREQEN_0 (0x0000) /* SMCLK conditional requests are disabled. */\r
+#define SMCLKREQEN_1 (0x0004) /* SMCLK conditional requests are enabled. */\r
+#define MODOSCREQEN (0x0008) /* */\r
+#define MODOSCREQEN_0 (0x0000) /* MODOSC conditional requests are disabled. */\r
+#define MODOSCREQEN_1 (0x0008) /* MODOSC conditional requests are enabled. */\r
+\r
+\r
+/*****************************************************************************\r
+ DIO Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_DIO__ 6 /* Definition to show that module is available */\r
+#define __MSP430_BASEADDRESS_DIO__ 0x0200\r
+#define DIO_BASE __MSP430_BASEADDRESS_DIO__\r
+#define __MSP430_HAS_PORTA_R__ /* Definition to show that port is available */\r
+#define __MSP430_BASEADDRESS_PORTA_R__ 0x200\r
+#define PA_BASE __MSP430_BASEADDRESS_PORTA_R__\r
+#define __MSP430_HAS_PORTB_R__ /* Definition to show that port is available */\r
+#define __MSP430_BASEADDRESS_PORTB_R__ 0x220\r
+#define PB_BASE __MSP430_BASEADDRESS_PORTB_R__\r
+#define __MSP430_HAS_PORTC_R__ /* Definition to show that port is available */\r
+#define __MSP430_BASEADDRESS_PORTC_R__ 0x240\r
+#define PC_BASE __MSP430_BASEADDRESS_PORTC_R__\r
+#define __MSP430_HAS_PORTJ_R__ /* Definition to show that port is available */\r
+#define __MSP430_BASEADDRESS_PORTJ_R__ 0x320\r
+#define PJ_BASE __MSP430_BASEADDRESS_PORTJ_R__\r
+#define __MSP430_HAS_PORT1_R__ /* Definition to show that port is available */\r
+#define __MSP430_BASEADDRESS_PORT1_R__ 0x200\r
+#define P1_BASE __MSP430_BASEADDRESS_PORT1_R__\r
+#define __MSP430_HAS_PORT2_R__ /* Definition to show that port is available */\r
+#define __MSP430_BASEADDRESS_PORT2_R__ 0x200\r
+#define P2_BASE __MSP430_BASEADDRESS_PORT2_R__\r
+#define __MSP430_HAS_PORT3_R__ /* Definition to show that port is available */\r
+#define __MSP430_BASEADDRESS_PORT3_R__ 0x220\r
+#define P3_BASE __MSP430_BASEADDRESS_PORT3_R__\r
+#define __MSP430_HAS_PORT4_R__ /* Definition to show that port is available */\r
+#define __MSP430_BASEADDRESS_PORT4_R__ 0x220\r
+#define P4_BASE __MSP430_BASEADDRESS_PORT4_R__\r
+#define __MSP430_HAS_PORT5_R__ /* Definition to show that port is available */\r
+#define __MSP430_BASEADDRESS_PORT5_R__ 0x240\r
+#define P5_BASE __MSP430_BASEADDRESS_PORT5_R__\r
+#define __MSP430_HAS_PORT6_R__ /* Definition to show that port is available */\r
+#define __MSP430_BASEADDRESS_PORT6_R__ 0x240\r
+#define P6_BASE __MSP430_BASEADDRESS_PORT6_R__\r
+#define __MSP430_HAS_PASEL0__ /* Define for DriverLib */\r
+#define __MSP430_HAS_PASEL1__ /* Define for DriverLib */\r
+#define __MSP430_HAS_PBSEL0__ /* Define for DriverLib */\r
+#define __MSP430_HAS_PBSEL1__ /* Define for DriverLib */\r
+#define __MSP430_HAS_PCSEL0__ /* Define for DriverLib */\r
+#define __MSP430_HAS_PCSEL1__ /* Define for DriverLib */\r
+#define __MSP430_HAS_PJSEL0__ /* Define for DriverLib */\r
+#define __MSP430_HAS_PJSEL1__ /* Define for DriverLib */\r
+#define __MSP430_HAS_P1SEL0__ /* Define for DriverLib */\r
+#define __MSP430_HAS_P2SEL0__ /* Define for DriverLib */\r
+#define __MSP430_HAS_P1SEL1__ /* Define for DriverLib */\r
+#define __MSP430_HAS_P2SEL1__ /* Define for DriverLib */\r
+#define __MSP430_HAS_P4SEL0__ /* Define for DriverLib */\r
+#define __MSP430_HAS_P3SEL0__ /* Define for DriverLib */\r
+#define __MSP430_HAS_P3SEL1__ /* Define for DriverLib */\r
+#define __MSP430_HAS_P4SEL1__ /* Define for DriverLib */\r
+#define __MSP430_HAS_P5SEL0__ /* Define for DriverLib */\r
+#define __MSP430_HAS_P6SEL0__ /* Define for DriverLib */\r
+#define __MSP430_HAS_P5SEL1__ /* Define for DriverLib */\r
+#define __MSP430_HAS_P6SEL1__ /* Define for DriverLib */\r
+\r
+sfr_w(PAIN); /* Port A Input */\r
+sfr_b(PAIN_L);\r
+sfr_b(PAIN_H);\r
+sfr_w(PAOUT); /* Port A Output */\r
+sfr_b(PAOUT_L);\r
+sfr_b(PAOUT_H);\r
+sfr_w(PADIR); /* Port A Direction */\r
+sfr_b(PADIR_L);\r
+sfr_b(PADIR_H);\r
+sfr_w(PAREN); /* Port A Resistor Enable */\r
+sfr_b(PAREN_L);\r
+sfr_b(PAREN_H);\r
+sfr_w(PASEL0); /* Port A Select 0 */\r
+sfr_b(PASEL0_L);\r
+sfr_b(PASEL0_H);\r
+sfr_w(PASEL1); /* Port A Select 1 */\r
+sfr_b(PASEL1_L);\r
+sfr_b(PASEL1_H);\r
+sfr_w(P1IV); /* Port 1 Interrupt Vector Register */\r
+sfr_b(P1IV_L);\r
+sfr_b(P1IV_H);\r
+sfr_w(PASELC); /* Port A Complement Select */\r
+sfr_b(PASELC_L);\r
+sfr_b(PASELC_H);\r
+sfr_w(PAIES); /* Port A Interrupt Edge Select */\r
+sfr_b(PAIES_L);\r
+sfr_b(PAIES_H);\r
+sfr_w(PAIE); /* Port A Interrupt Enable */\r
+sfr_b(PAIE_L);\r
+sfr_b(PAIE_H);\r
+sfr_w(PAIFG); /* Port A Interrupt Flag */\r
+sfr_b(PAIFG_L);\r
+sfr_b(PAIFG_H);\r
+sfr_w(P2IV); /* Port 2 Interrupt Vector Register */\r
+sfr_b(P2IV_L);\r
+sfr_b(P2IV_H);\r
+sfr_w(PBIN); /* Port B Input */\r
+sfr_b(PBIN_L);\r
+sfr_b(PBIN_H);\r
+sfr_w(PBOUT); /* Port B Output */\r
+sfr_b(PBOUT_L);\r
+sfr_b(PBOUT_H);\r
+sfr_w(PBDIR); /* Port B Direction */\r
+sfr_b(PBDIR_L);\r
+sfr_b(PBDIR_H);\r
+sfr_w(PBREN); /* Port B Resistor Enable */\r
+sfr_b(PBREN_L);\r
+sfr_b(PBREN_H);\r
+sfr_w(PBSEL0); /* Port B Select 0 */\r
+sfr_b(PBSEL0_L);\r
+sfr_b(PBSEL0_H);\r
+sfr_w(PBSEL1); /* Port B Select 1 */\r
+sfr_b(PBSEL1_L);\r
+sfr_b(PBSEL1_H);\r
+sfr_w(P3IV); /* Port 3 Interrupt Vector Register */\r
+sfr_b(P3IV_L);\r
+sfr_b(P3IV_H);\r
+sfr_w(PBSELC); /* Port B Complement Select */\r
+sfr_b(PBSELC_L);\r
+sfr_b(PBSELC_H);\r
+sfr_w(PBIES); /* Port B Interrupt Edge Select */\r
+sfr_b(PBIES_L);\r
+sfr_b(PBIES_H);\r
+sfr_w(PBIE); /* Port B Interrupt Enable */\r
+sfr_b(PBIE_L);\r
+sfr_b(PBIE_H);\r
+sfr_w(PBIFG); /* Port B Interrupt Flag */\r
+sfr_b(PBIFG_L);\r
+sfr_b(PBIFG_H);\r
+sfr_w(P4IV); /* Port 4 Interrupt Vector Register */\r
+sfr_b(P4IV_L);\r
+sfr_b(P4IV_H);\r
+sfr_w(PCIN); /* Port C Input */\r
+sfr_b(PCIN_L);\r
+sfr_b(PCIN_H);\r
+sfr_w(PCOUT); /* Port C Output */\r
+sfr_b(PCOUT_L);\r
+sfr_b(PCOUT_H);\r
+sfr_w(PCDIR); /* Port C Direction */\r
+sfr_b(PCDIR_L);\r
+sfr_b(PCDIR_H);\r
+sfr_w(PCREN); /* Port C Resistor Enable */\r
+sfr_b(PCREN_L);\r
+sfr_b(PCREN_H);\r
+sfr_w(PCSEL0); /* Port C Select 0 */\r
+sfr_b(PCSEL0_L);\r
+sfr_b(PCSEL0_H);\r
+sfr_w(PCSEL1); /* Port C Select 1 */\r
+sfr_b(PCSEL1_L);\r
+sfr_b(PCSEL1_H);\r
+sfr_w(P5IV); /* Port 5 Interrupt Vector Register */\r
+sfr_b(P5IV_L);\r
+sfr_b(P5IV_H);\r
+sfr_w(PCSELC); /* Port C Complement Select */\r
+sfr_b(PCSELC_L);\r
+sfr_b(PCSELC_H);\r
+sfr_w(PCIES); /* Port C Interrupt Edge Select */\r
+sfr_b(PCIES_L);\r
+sfr_b(PCIES_H);\r
+sfr_w(PCIE); /* Port C Interrupt Enable */\r
+sfr_b(PCIE_L);\r
+sfr_b(PCIE_H);\r
+sfr_w(PCIFG); /* Port C Interrupt Flag */\r
+sfr_b(PCIFG_L);\r
+sfr_b(PCIFG_H);\r
+sfr_w(P6IV); /* Port 6 Interrupt Vector Register */\r
+sfr_b(P6IV_L);\r
+sfr_b(P6IV_H);\r
+sfr_w(PJIN); /* Port J Input */\r
+sfr_b(PJIN_L);\r
+sfr_b(PJIN_H);\r
+sfr_w(PJOUT); /* Port J Output */\r
+sfr_b(PJOUT_L);\r
+sfr_b(PJOUT_H);\r
+sfr_w(PJDIR); /* Port J Direction */\r
+sfr_b(PJDIR_L);\r
+sfr_b(PJDIR_H);\r
+sfr_w(PJREN); /* Port J Resistor Enable */\r
+sfr_b(PJREN_L);\r
+sfr_b(PJREN_H);\r
+sfr_w(PJSEL0); /* Port J Select 0 */\r
+sfr_b(PJSEL0_L);\r
+sfr_b(PJSEL0_H);\r
+sfr_w(PJSEL1); /* Port J Select 1 */\r
+sfr_b(PJSEL1_L);\r
+sfr_b(PJSEL1_H);\r
+sfr_w(PJSELC); /* Port J Complement Select */\r
+sfr_b(PJSELC_L);\r
+sfr_b(PJSELC_H);\r
+sfr_b(P1IN); /* Port 1 Input */\r
+\r
+sfr_b(P2IN); /* Port 2 Input */\r
+\r
+sfr_b(P2OUT); /* Port 2 Output */\r
+\r
+sfr_b(P1OUT); /* Port 1 Output */\r
+\r
+sfr_b(P1DIR); /* Port 1 Direction */\r
+\r
+sfr_b(P2DIR); /* Port 2 Direction */\r
+\r
+sfr_b(P1REN); /* Port 1 Resistor Enable */\r
+\r
+sfr_b(P2REN); /* Port 2 Resistor Enable */\r
+\r
+sfr_b(P1SEL0); /* Port 1 Select 0 */\r
+\r
+sfr_b(P2SEL0); /* Port 2 Select 0 */\r
+\r
+sfr_b(P1SEL1); /* Port 1 Select 1 */\r
+\r
+sfr_b(P2SEL1); /* Port 2 Select 1 */\r
+\r
+sfr_b(P1SELC); /* Port 1 Complement Select */\r
+\r
+sfr_b(P2SELC); /* Port 2 Complement Select */\r
+\r
+sfr_b(P1IES); /* Port 1 Interrupt Edge Select */\r
+\r
+sfr_b(P2IES); /* Port 2 Interrupt Edge Select */\r
+\r
+sfr_b(P1IE); /* Port 1 Interrupt Enable */\r
+\r
+sfr_b(P2IE); /* Port 2 Interrupt Enable */\r
+\r
+sfr_b(P1IFG); /* Port 1 Interrupt Flag */\r
+\r
+sfr_b(P2IFG); /* Port 2 Interrupt Flag */\r
+\r
+sfr_b(P3IN); /* Port 3 Input */\r
+\r
+sfr_b(P4IN); /* Port 4 Input */\r
+\r
+sfr_b(P3OUT); /* Port 3 Output */\r
+\r
+sfr_b(P4OUT); /* Port 4 Output */\r
+\r
+sfr_b(P3DIR); /* Port 3 Direction */\r
+\r
+sfr_b(P4DIR); /* Port 4 Direction */\r
+\r
+sfr_b(P3REN); /* Port 3 Resistor Enable */\r
+\r
+sfr_b(P4REN); /* Port 4 Resistor Enable */\r
+\r
+sfr_b(P4SEL0); /* Port 4 Select 0 */\r
+\r
+sfr_b(P3SEL0); /* Port 3 Select 0 */\r
+\r
+sfr_b(P3SEL1); /* Port 3 Select 1 */\r
+\r
+sfr_b(P4SEL1); /* Port 4 Select 1 */\r
+\r
+sfr_b(P3SELC); /* Port 3 Complement Select */\r
+\r
+sfr_b(P4SELC); /* Port 4 Complement Select */\r
+\r
+sfr_b(P3IES); /* Port 3 Interrupt Edge Select */\r
+\r
+sfr_b(P4IES); /* Port 4 Interrupt Edge Select */\r
+\r
+sfr_b(P3IE); /* Port 3 Interrupt Enable */\r
+\r
+sfr_b(P4IE); /* Port 4 Interrupt Enable */\r
+\r
+sfr_b(P3IFG); /* Port 3 Interrupt Flag */\r
+\r
+sfr_b(P4IFG); /* Port 4 Interrupt Flag */\r
+\r
+sfr_b(P5IN); /* Port 5 Input */\r
+\r
+sfr_b(P6IN); /* Port 6 Input */\r
+\r
+sfr_b(P5OUT); /* Port 5 Output */\r
+\r
+sfr_b(P6OUT); /* Port 6 Output */\r
+\r
+sfr_b(P5DIR); /* Port 5 Direction */\r
+\r
+sfr_b(P6DIR); /* Port 6 Direction */\r
+\r
+sfr_b(P5REN); /* Port 5 Resistor Enable */\r
+\r
+sfr_b(P6REN); /* Port 6 Resistor Enable */\r
+\r
+sfr_b(P5SEL0); /* Port 5 Select 0 */\r
+\r
+sfr_b(P6SEL0); /* Port 6 Select 0 */\r
+\r
+sfr_b(P5SEL1); /* Port 5 Select 1 */\r
+\r
+sfr_b(P6SEL1); /* Port 6 Select 1 */\r
+\r
+sfr_b(P5SELC); /* Port 5 Complement Select */\r
+\r
+sfr_b(P6SELC); /* Port 6 Complement Select */\r
+\r
+sfr_b(P5IES); /* Port 5 Interrupt Edge Select */\r
+\r
+sfr_b(P6IES); /* Port 6 Interrupt Edge Select */\r
+\r
+sfr_b(P5IE); /* Port 5 Interrupt Enable */\r
+\r
+sfr_b(P6IE); /* Port 6 Interrupt Enable */\r
+\r
+sfr_b(P5IFG); /* Port 5 Interrupt Flag */\r
+\r
+sfr_b(P6IFG); /* Port 6 Interrupt Flag */\r
+\r
+\r
+/* DIO Register Offsets */\r
+#define OFS_PAIN (0x0000)\r
+#define OFS_PAOUT (0x0002)\r
+#define OFS_PADIR (0x0004)\r
+#define OFS_PAREN (0x0006)\r
+#define OFS_PASEL0 (0x000A)\r
+#define OFS_PASEL1 (0x000C)\r
+#define OFS_P1IV (0x000E)\r
+#define OFS_PASELC (0x0016)\r
+#define OFS_PAIES (0x0018)\r
+#define OFS_PAIE (0x001A)\r
+#define OFS_PAIFG (0x001C)\r
+#define OFS_P2IV (0x001E)\r
+#define OFS_PBIN (0x0000)\r
+#define OFS_PBOUT (0x0002)\r
+#define OFS_PBDIR (0x0004)\r
+#define OFS_PBREN (0x0006)\r
+#define OFS_PBSEL0 (0x000A)\r
+#define OFS_PBSEL1 (0x000C)\r
+#define OFS_P3IV (0x000E)\r
+#define OFS_PBSELC (0x0016)\r
+#define OFS_PBIES (0x0018)\r
+#define OFS_PBIE (0x001A)\r
+#define OFS_PBIFG (0x001C)\r
+#define OFS_P4IV (0x001E)\r
+#define OFS_PCIN (0x0000)\r
+#define OFS_PCOUT (0x0002)\r
+#define OFS_PCDIR (0x0004)\r
+#define OFS_PCREN (0x0006)\r
+#define OFS_PCSEL0 (0x000A)\r
+#define OFS_PCSEL1 (0x000C)\r
+#define OFS_P5IV (0x000E)\r
+#define OFS_PCSELC (0x0016)\r
+#define OFS_PCIES (0x0018)\r
+#define OFS_PCIE (0x001A)\r
+#define OFS_PCIFG (0x001C)\r
+#define OFS_P6IV (0x001E)\r
+#define OFS_PJIN (0x0000)\r
+#define OFS_PJOUT (0x0002)\r
+#define OFS_PJDIR (0x0004)\r
+#define OFS_PJREN (0x0006)\r
+#define OFS_PJSEL0 (0x000A)\r
+#define OFS_PJSEL1 (0x000C)\r
+#define OFS_PJSELC (0x0016)\r
+#define OFS_P1IN (0x0000)\r
+#define OFS_P2IN (0x0001)\r
+#define OFS_P2OUT (0x0003)\r
+#define OFS_P1OUT (0x0002)\r
+#define OFS_P1DIR (0x0004)\r
+#define OFS_P2DIR (0x0005)\r
+#define OFS_P1REN (0x0006)\r
+#define OFS_P2REN (0x0007)\r
+#define OFS_P1SEL0 (0x000A)\r
+#define OFS_P2SEL0 (0x000B)\r
+#define OFS_P1SEL1 (0x000C)\r
+#define OFS_P2SEL1 (0x000D)\r
+#define OFS_P1SELC (0x0016)\r
+#define OFS_P2SELC (0x0017)\r
+#define OFS_P1IES (0x0018)\r
+#define OFS_P2IES (0x0019)\r
+#define OFS_P1IE (0x001A)\r
+#define OFS_P2IE (0x001B)\r
+#define OFS_P1IFG (0x001C)\r
+#define OFS_P2IFG (0x001D)\r
+#define OFS_P3IN (0x0000)\r
+#define OFS_P4IN (0x0001)\r
+#define OFS_P3OUT (0x0002)\r
+#define OFS_P4OUT (0x0003)\r
+#define OFS_P3DIR (0x0004)\r
+#define OFS_P4DIR (0x0005)\r
+#define OFS_P3REN (0x0006)\r
+#define OFS_P4REN (0x0007)\r
+#define OFS_P4SEL0 (0x000B)\r
+#define OFS_P3SEL0 (0x000A)\r
+#define OFS_P3SEL1 (0x000C)\r
+#define OFS_P4SEL1 (0x000D)\r
+#define OFS_P3SELC (0x0016)\r
+#define OFS_P4SELC (0x0017)\r
+#define OFS_P3IES (0x0018)\r
+#define OFS_P4IES (0x0019)\r
+#define OFS_P3IE (0x001A)\r
+#define OFS_P4IE (0x001B)\r
+#define OFS_P3IFG (0x001C)\r
+#define OFS_P4IFG (0x001D)\r
+#define OFS_P5IN (0x0000)\r
+#define OFS_P6IN (0x0001)\r
+#define OFS_P5OUT (0x0002)\r
+#define OFS_P6OUT (0x0003)\r
+#define OFS_P5DIR (0x0004)\r
+#define OFS_P6DIR (0x0005)\r
+#define OFS_P5REN (0x0006)\r
+#define OFS_P6REN (0x0007)\r
+#define OFS_P5SEL0 (0x000A)\r
+#define OFS_P6SEL0 (0x000B)\r
+#define OFS_P5SEL1 (0x000C)\r
+#define OFS_P6SEL1 (0x000D)\r
+#define OFS_P5SELC (0x0016)\r
+#define OFS_P6SELC (0x0017)\r
+#define OFS_P5IES (0x0018)\r
+#define OFS_P6IES (0x0019)\r
+#define OFS_P5IE (0x001A)\r
+#define OFS_P6IE (0x001B)\r
+#define OFS_P5IFG (0x001C)\r
+#define OFS_P6IFG (0x001D)\r
+\r
+/*****************************************************************************\r
+ FRCTL Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_FRCTL__ /* Definition to show that module is available */\r
+#define __MSP430_BASEADDRESS_FRCTL__ 0x01A0\r
+#define FRCTL_BASE __MSP430_BASEADDRESS_FRCTL__\r
+\r
+sfr_w(FRCTL0); /* FRAM Controller Control Register 0 */\r
+sfr_b(FRCTL0_L);\r
+sfr_b(FRCTL0_H);\r
+sfr_w(GCCTL0); /* General Control Register 0 */\r
+sfr_b(GCCTL0_L);\r
+sfr_b(GCCTL0_H);\r
+sfr_w(GCCTL1); /* General Control Register 1 */\r
+sfr_b(GCCTL1_L);\r
+sfr_b(GCCTL1_H);\r
+\r
+/* FRCTL Register Offsets */\r
+#define OFS_FRCTL0 (0x0000)\r
+#define OFS_GCCTL0 (0x0004)\r
+#define OFS_GCCTL1 (0x0006)\r
+\r
+/* FRCTL Control Bits */\r
+\r
+/* FRCTL0 Control Bits */\r
+#define NWAITS (0x0070) /* Wait state numbers */\r
+#define NWAITS0 (0x0010) /* Wait state numbers */\r
+#define NWAITS1 (0x0020) /* Wait state numbers */\r
+#define NWAITS2 (0x0040) /* Wait state numbers */\r
+#define NWAITS_0 (0x0000) /* FRAM wait states: 0 */\r
+#define NWAITS_1 (0x0010) /* FRAM wait states: 1 */\r
+#define NWAITS_2 (0x0020) /* FRAM wait states: 2 */\r
+#define NWAITS_3 (0x0030) /* FRAM wait states: 3 */\r
+#define NWAITS_4 (0x0040) /* FRAM wait states: 4 */\r
+#define NWAITS_5 (0x0050) /* FRAM wait states: 5 */\r
+#define NWAITS_6 (0x0060) /* FRAM wait states: 6 */\r
+#define NWAITS_7 (0x0070) /* FRAM wait states: 7 */\r
+#define FRCTLPW (0xa500) /* FRCTLPW password */\r
+#define FRCTLPW0 (0x0100) /* FRCTLPW password */\r
+#define FRCTLPW1 (0x0200) /* FRCTLPW password */\r
+#define FRCTLPW2 (0x0400) /* FRCTLPW password */\r
+#define FRCTLPW3 (0x0800) /* FRCTLPW password */\r
+#define FRCTLPW4 (0x1000) /* FRCTLPW password */\r
+#define FRCTLPW5 (0x2000) /* FRCTLPW password */\r
+#define FRCTLPW6 (0x4000) /* FRCTLPW password */\r
+#define FRCTLPW7 (0x8000) /* FRCTLPW password */\r
+\r
+/* GCCTL0 Control Bits */\r
+#define UBDRSTEN (0x0080) /* Enable Power Up Clear (PUC) reset for the uncorrectable bit \r
+ error detection flag (UBDIFG) */\r
+#define UBDRSTEN_0 (0x0000) /* PUC not initiated on uncorrectable bit error detection flag. */\r
+#define UBDRSTEN_1 (0x0080) /* PUC initiated on uncorrectable bit error detection flag. \r
+ Generates vector in SYSRSTIV. Clear the UBDIE bit. */\r
+#define UBDIE (0x0040) /* Enable NMI event for the uncorrectable bit error detection \r
+ flag (UBDIFG) */\r
+#define UBDIE_0 (0x0000) /* Disable NMI for the uncorrectable bit error detection flag \r
+ (UBDIFG). */\r
+#define UBDIE_1 (0x0040) /* Enable NMI for the uncorrectable bit error detection flag \r
+ (UBDIFG). Generates vector in SYSSNIV. Clear the UBDRSTEN bit. */\r
+#define CBDIE (0x0020) /* Enable NMI event for the correctable bit error detection flag \r
+ (CBDIFG) */\r
+#define CBDIE_0 (0x0000) /* Disable NMI for the correctable bit error detection flag \r
+ (CBDIFG). */\r
+#define CBDIE_1 (0x0020) /* Disable NMI for the correctable bit error detection flag \r
+ (CBDIFG). Generates vector in SYSSNIV. */\r
+#define FRPWR (0x0004) /* FRAM Memory Power Control Request */\r
+#define FRPWR_0 (0x0000) /* Enable INACTIVE mode. */\r
+#define FRPWR_1 (0x0004) /* Enable ACTIVE mode. */\r
+#define FRLPMPWR (0x0002) /* Enables FRAM auto power up after LPM */\r
+#define FRLPMPWR_0 (0x0000) /* FRAM startup is delayed to the first FRAM access after exit \r
+ from LPM */\r
+#define FRLPMPWR_1 (0x0002) /* FRAM is powered up immediately on exit from LPM */\r
+\r
+/* GCCTL1 Control Bits */\r
+#define ACCTEIFG (0x0008) /* Access time error flag */\r
+#define ACCTEIFG_0 (0x0000) /* No interrupt pending. */\r
+#define ACCTEIFG_1 (0x0008) /* Interrupt pending. Can be cleared by writing '0' or by reading\r
+ SYSSNIV when it is the highest pending interrupt. */\r
+#define UBDIFG (0x0004) /* FRAM uncorrectable bit error detection flag */\r
+#define UBDIFG_0 (0x0000) /* No interrupt pending. */\r
+#define UBDIFG_1 (0x0004) /* Interrupt pending. Can be cleared by writing '0' or by reading\r
+ SYSSNIV when it is the highest pending interrupt. */\r
+#define CBDIFG (0x0002) /* FRAM correctable bit error detection flag */\r
+#define CBDIFG_0 (0x0000) /* No interrupt is pending */\r
+#define CBDIFG_1 (0x0002) /* Interrupt pending. Can be cleared by writing '0' or by reading\r
+ SYSSNIV if it is the highest pending interrupt. */\r
+\r
+\r
+/*****************************************************************************\r
+ MPY32 Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_MPY32__ /* Definition to show that module is available */\r
+#define __MSP430_BASEADDRESS_MPY32__ 0x04C0\r
+#define MPY32_BASE __MSP430_BASEADDRESS_MPY32__\r
+\r
+sfr_w(MPY); /* 16-bit operand one multiply */\r
+sfr_b(MPY_L);\r
+sfr_b(MPY_H);\r
+sfr_w(MPYS); /* 16-bit operand one signed multiply */\r
+sfr_b(MPYS_L);\r
+sfr_b(MPYS_H);\r
+sfr_w(MAC); /* 16-bit operand one multiply accumulate */\r
+sfr_b(MAC_L);\r
+sfr_b(MAC_H);\r
+sfr_w(MACS); /* 16-bit operand one signed multiply accumulate */\r
+sfr_b(MACS_L);\r
+sfr_b(MACS_H);\r
+sfr_w(OP2); /* 16-bit operand two */\r
+sfr_b(OP2_L);\r
+sfr_b(OP2_H);\r
+sfr_w(RESLO); /* 16x16-bit result low word */\r
+sfr_b(RESLO_L);\r
+sfr_b(RESLO_H);\r
+sfr_w(RESHI); /* 16x16-bit result high word */\r
+sfr_b(RESHI_L);\r
+sfr_b(RESHI_H);\r
+sfr_w(SUMEXT); /* 16x16-bit sum extension register */\r
+sfr_b(SUMEXT_L);\r
+sfr_b(SUMEXT_H);\r
+sfr_w(MPY32L); /* 32-bit operand 1 multiply low word */\r
+sfr_b(MPY32L_L);\r
+sfr_b(MPY32L_H);\r
+sfr_w(MPY32H); /* 32-bit operand 1 multiply high word */\r
+sfr_b(MPY32H_L);\r
+sfr_b(MPY32H_H);\r
+sfr_w(MPYS32L); /* 32-bit operand 1 signed multiply low word */\r
+sfr_b(MPYS32L_L);\r
+sfr_b(MPYS32L_H);\r
+sfr_w(MPYS32H); /* 32-bit operand 1 signed multiply high word */\r
+sfr_b(MPYS32H_L);\r
+sfr_b(MPYS32H_H);\r
+sfr_w(MAC32L); /* 32-bit operand 1 multiply accumulate low word */\r
+sfr_b(MAC32L_L);\r
+sfr_b(MAC32L_H);\r
+sfr_w(MAC32H); /* 32-bit operand 1 multiply accumulate high word */\r
+sfr_b(MAC32H_L);\r
+sfr_b(MAC32H_H);\r
+sfr_w(MACS32L); /* 32-bit operand 1 signed multiply accumulate low word */\r
+sfr_b(MACS32L_L);\r
+sfr_b(MACS32L_H);\r
+sfr_w(MACS32H); /* 32-bit operand 1 signed multiply accumulate high word */\r
+sfr_b(MACS32H_L);\r
+sfr_b(MACS32H_H);\r
+sfr_w(OP2L); /* 32-bit operand 2 low word */\r
+sfr_b(OP2L_L);\r
+sfr_b(OP2L_H);\r
+sfr_w(OP2H); /* 32-bit operand 2 high word */\r
+sfr_b(OP2H_L);\r
+sfr_b(OP2H_H);\r
+sfr_w(RES0); /* 32x32-bit result 0 least significant word */\r
+sfr_b(RES0_L);\r
+sfr_b(RES0_H);\r
+sfr_w(RES1); /* 32x32-bit result 1 */\r
+sfr_b(RES1_L);\r
+sfr_b(RES1_H);\r
+sfr_w(RES2); /* 32x32-bit result 2 */\r
+sfr_b(RES2_L);\r
+sfr_b(RES2_H);\r
+sfr_w(RES3); /* 32x32-bit result 3 most significant word */\r
+sfr_b(RES3_L);\r
+sfr_b(RES3_H);\r
+sfr_w(MPY32CTL0); /* MPY32 control register 0 */\r
+sfr_b(MPY32CTL0_L);\r
+sfr_b(MPY32CTL0_H);\r
+\r
+/* MPY32 Register Offsets */\r
+#define OFS_MPY (0x0000)\r
+#define OFS_MPYS (0x0002)\r
+#define OFS_MAC (0x0004)\r
+#define OFS_MACS (0x0006)\r
+#define OFS_OP2 (0x0008)\r
+#define OFS_RESLO (0x000A)\r
+#define OFS_RESHI (0x000C)\r
+#define OFS_SUMEXT (0x000E)\r
+#define OFS_MPY32L (0x0010)\r
+#define OFS_MPY32H (0x0012)\r
+#define OFS_MPYS32L (0x0014)\r
+#define OFS_MPYS32H (0x0016)\r
+#define OFS_MAC32L (0x0018)\r
+#define OFS_MAC32H (0x001A)\r
+#define OFS_MACS32L (0x001C)\r
+#define OFS_MACS32H (0x001E)\r
+#define OFS_OP2L (0x0020)\r
+#define OFS_OP2H (0x0022)\r
+#define OFS_RES0 (0x0024)\r
+#define OFS_RES1 (0x0026)\r
+#define OFS_RES2 (0x0028)\r
+#define OFS_RES3 (0x002A)\r
+#define OFS_MPY32CTL0 (0x002C)\r
+\r
+/* MPY32 Control Bits */\r
+\r
+/* MACS32H Control Bits */\r
+#define MACS32H0 (0x0100) /* 32-bit operand 1 signed multiply accumulate high word */\r
+#define MACS32H1 (0x0200) /* 32-bit operand 1 signed multiply accumulate high word */\r
+#define MACS32H2 (0x0400) /* 32-bit operand 1 signed multiply accumulate high word */\r
+#define MACS32H3 (0x0800) /* 32-bit operand 1 signed multiply accumulate high word */\r
+#define MACS32H4 (0x1000) /* 32-bit operand 1 signed multiply accumulate high word */\r
+#define MACS32H5 (0x2000) /* 32-bit operand 1 signed multiply accumulate high word */\r
+#define MACS32H6 (0x4000) /* 32-bit operand 1 signed multiply accumulate high word */\r
+#define MACS32H7 (0x8000) /* 32-bit operand 1 signed multiply accumulate high word */\r
+\r
+/* MPY32CTL0 Control Bits */\r
+#define MPYDLY32 (0x0200) /* Delayed write mode. */\r
+#define MPYDLY32_0 (0x0000) /* Writes are delayed until 64-bit result (RES0 to RES3) is \r
+ available. */\r
+#define MPYDLY32_1 (0x0200) /* Writes are delayed until 32-bit result (RES0 to RES1) is \r
+ available. 8 MPYDLYWRTEN */\r
+#define MPYDLYWRTEN (0x0100) /* Delayed write enable. */\r
+#define MPYDLYWRTEN_0 (0x0000) /* Writes are not delayed. */\r
+#define MPYDLYWRTEN_1 (0x0100) /* Writes are delayed. */\r
+#define MPYOP2_32 (0x0080) /* Multiplier bit width of operand 2 */\r
+#define MPYOP2_32_0 (0x0000) /* 16 bits. */\r
+#define MPYOP2_32_1 (0x0080) /* 32 bits. */\r
+#define MPYOP2_32__16 (0x0000) /* 16 bits. */\r
+#define MPYOP2_32__32 (0x0080) /* 32 bits. */\r
+#define MPYOP1_32 (0x0040) /* Multiplier bit width of operand 1 */\r
+#define MPYOP1_32_0 (0x0000) /* 16 bits. */\r
+#define MPYOP1_32_1 (0x0040) /* 32 bits. */\r
+#define MPYOP1_32__16 (0x0000) /* 16 bits. */\r
+#define MPYOP1_32__32 (0x0040) /* 32 bits. */\r
+#define MPYM (0x0030) /* Multiplier mode */\r
+#define MPYM0 (0x0010) /* Multiplier mode */\r
+#define MPYM1 (0x0020) /* Multiplier mode */\r
+#define MPYM_0 (0x0000) /* MPY Multiply */\r
+#define MPYM_1 (0x0010) /* MPYS Signed multiply */\r
+#define MPYM_2 (0x0020) /* MAC Multiply accumulate */\r
+#define MPYM_3 (0x0030) /* MACS Signed multiply accumulate */\r
+#define MPYM__MPY (0x0000) /* MPY Multiply */\r
+#define MPYM__MPYS (0x0010) /* MPYS Signed multiply */\r
+#define MPYM__MAC (0x0020) /* MAC Multiply accumulate */\r
+#define MPYM__MACS (0x0030) /* MACS Signed multiply accumulate */\r
+#define MPYSAT (0x0008) /* Saturation mode */\r
+#define MPYSAT_0 (0x0000) /* Saturation mode disabled. */\r
+#define MPYSAT_1 (0x0008) /* Saturation mode enabled. */\r
+#define MPYSAT__DISABLE (0x0000) /* Saturation mode disabled. */\r
+#define MPYSAT__ENABLE (0x0008) /* Saturation mode enabled. */\r
+#define MPYFRAC (0x0004) /* Fractional mode. */\r
+#define MPYFRAC_0 (0x0000) /* Fractional mode disabled. */\r
+#define MPYFRAC_1 (0x0004) /* Fractional mode enabled. */\r
+#define MPYFRAC__DISABLE (0x0000) /* Fractional mode disabled. */\r
+#define MPYFRAC__ENABLE (0x0004) /* Fractional mode enabled. */\r
+#define MPYC (0x0001) /* Carry of the multiplier */\r
+#define MPYC_0 (0x0000) /* No carry for result. */\r
+#define MPYC_1 (0x0001) /* Result has a carry. */\r
+\r
+\r
+/*****************************************************************************\r
+ PMM Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_PMM__ /* Definition to show that module is available */\r
+#define __MSP430_BASEADDRESS_PMM__ 0x0120\r
+#define PMM_BASE __MSP430_BASEADDRESS_PMM__\r
+\r
+sfr_w(PMMCTL0); /* Power Management Module control register 0 */\r
+sfr_b(PMMCTL0_L);\r
+sfr_b(PMMCTL0_H);\r
+sfr_w(PMMCTL1); /* Power Management Module Control Register 1. Allows manual \r
+ overwrite of predictive LDO settings. */\r
+sfr_b(PMMCTL1_L);\r
+sfr_b(PMMCTL1_H);\r
+sfr_w(PMMCTL2); /* Power Management Module Control Register 2 */\r
+sfr_b(PMMCTL2_L);\r
+sfr_b(PMMCTL2_H);\r
+sfr_w(PMMIFG); /* PMM interrupt flag register */\r
+sfr_b(PMMIFG_L);\r
+sfr_b(PMMIFG_H);\r
+sfr_w(PM5CTL0); /* Power mode 5 control register 0 */\r
+sfr_b(PM5CTL0_L);\r
+sfr_b(PM5CTL0_H);\r
+\r
+/* PMM Register Offsets */\r
+#define OFS_PMMCTL0 (0x0000)\r
+#define OFS_PMMCTL1 (0x0002)\r
+#define OFS_PMMCTL2 (0x0004)\r
+#define OFS_PMMIFG (0x000A)\r
+#define OFS_PM5CTL0 (0x0010)\r
+\r
+/* PMM Control Bits */\r
+\r
+/* PMMCTL0 Control Bits */\r
+#define PMMSWBOR (0x0004) /* Software brownout reset. */\r
+#define PMMSWBOR_0 (0x0000) /* Normal operation */\r
+#define PMMSWBOR_1 (0x0004) /* Set to 1 to trigger a BOR */\r
+#define PMMSWPOR (0x0008) /* Software POR. */\r
+#define PMMSWPOR_0 (0x0000) /* Normal operation */\r
+#define PMMSWPOR_1 (0x0008) /* Set to 1 to trigger a POR */\r
+#define PMMREGOFF (0x0010) /* Regulator off */\r
+#define PMMREGOFF_0 (0x0000) /* Regulator remains on when going into LPM3 or LPM4 */\r
+#define PMMREGOFF_1 (0x0010) /* Regulator is turned off when going to LPM3 or LPM4. System \r
+ enters LPM3.5 or LPM4.5, respectively. */\r
+#define SVSHE (0x0040) /* High-side SVS enable. */\r
+#define SVSHE_0 (0x0000) /* High-side SVS (SVSH) is disabled in LPM2, LPM3, LPM4, LPM3.5, \r
+ and LPM4.5. SVSH is always enabled in active mode, LPM0, and \r
+ LPM1. */\r
+#define SVSHE_1 (0x0040) /* SVSH is always enabled. */\r
+#define PMMPW (0xa500) /* PMM password. */\r
+#define PMMPW0 (0x0100) /* PMM password. */\r
+#define PMMPW1 (0x0200) /* PMM password. */\r
+#define PMMPW2 (0x0400) /* PMM password. */\r
+#define PMMPW3 (0x0800) /* PMM password. */\r
+#define PMMPW4 (0x1000) /* PMM password. */\r
+#define PMMPW5 (0x2000) /* PMM password. */\r
+#define PMMPW6 (0x4000) /* PMM password. */\r
+#define PMMPW7 (0x8000) /* PMM password. */\r
+\r
+/* PMMCTL2 Control Bits */\r
+#define INTREFEN (0x0001) /* */\r
+#define INTREFEN_0 (0x0000) /* Disable internal reference */\r
+#define INTREFEN_1 (0x0001) /* Enable internal reference */\r
+#define EXTREFEN (0x0002) /* */\r
+#define EXTREFEN_0 (0x0000) /* Disable external reference output */\r
+#define EXTREFEN_1 (0x0002) /* Enable internal reference output */\r
+#define PWRMODE (0xc000) /* */\r
+#define PWRMODE0 (0x4000) /* */\r
+#define PWRMODE1 (0x8000) /* */\r
+#define TSENSOREN (0x0008) /* */\r
+#define TSENSOREN_0 (0x0000) /* Disable temperature sensor */\r
+#define TSENSOREN_1 (0x0008) /* Enable temperature sensor */\r
+#define REFGENACT (0x0100) /* */\r
+#define REFGENACT_0 (0x0000) /* Reference generator not active */\r
+#define REFGENACT_1 (0x0100) /* Reference generator active */\r
+#define REFBGACT (0x0200) /* */\r
+#define REFBGACT_0 (0x0000) /* Reference bandgap buffer not active */\r
+#define REFBGACT_1 (0x0200) /* Reference bandgap buffer active */\r
+#define BGMODE (0x0800) /* */\r
+#define BGMODE_0 (0x0000) /* Static mode (higher precision) */\r
+#define BGMODE_1 (0x0800) /* Sampled mode (lower power consumption) */\r
+#define REFGENRDY (0x1000) /* */\r
+#define REFGENRDY_0 (0x0000) /* Reference voltage output is not ready to be used. */\r
+#define REFGENRDY_1 (0x1000) /* Reference voltage output is ready to be used */\r
+#define REFBGRDY (0x2000) /* */\r
+#define REFBGRDY_0 (0x0000) /* Buffered bandgap voltage is not ready to be used */\r
+#define REFBGRDY_1 (0x2000) /* Buffered bandgap voltage is ready to be used */\r
+#define REFVSEL (0x0030) /* */\r
+#define REFVSEL0 (0x0010) /* */\r
+#define REFVSEL1 (0x0020) /* */\r
+#define REFVSEL_0 (0x0000) /* 00b = 1.5V */\r
+#define REFVSEL_1 (0x0010) /* 01b = 2.0V */\r
+#define REFVSEL_2 (0x0020) /* 10b = 2.5V */\r
+#define REFVSEL_3 (0x0030) /* 11b = Reserved */\r
+#define REFGEN (0x0040) /* */\r
+#define REFGEN_0 (0x0000) /* No trigger */\r
+#define REFGEN_1 (0x0040) /* Generation of the reference voltage is started by writing 1 or\r
+ by a hardware trigger */\r
+#define REFBGEN (0x0080) /* */\r
+#define REFBG_0 (0x0000) /* No trigger */\r
+#define REFBG_1 (0x0080) /* Generation of the bandgap voltage is started by writing 1 or \r
+ by a hardware trigger */\r
+\r
+/* PMMIFG Control Bits */\r
+#define PMMBORIFG (0x0100) /* PMM software brownout reset interrupt flag. */\r
+#define PMMBORIFG_0 (0x0000) /* Reset not due to PMMSWBOR */\r
+#define PMMBORIFG_1 (0x0100) /* Reset due to PMMSWBOR */\r
+#define PMMRSTIFG (0x0200) /* PMM reset pin interrupt flag. */\r
+#define PMMRSTIFG_0 (0x0000) /* Reset not due to reset pin */\r
+#define PMMRSTIFG_1 (0x0200) /* Reset due to reset pin */\r
+#define PMMPORIFG (0x0400) /* PMM software POR interrupt flag. */\r
+#define PMMPORIFG_0 (0x0000) /* Reset not due to PMMSWPOR */\r
+#define PMMPORIFG_1 (0x0400) /* Reset due to PMMSWPOR */\r
+#define SPWRIFG (0x0800) /* */\r
+#define SVSHIFG (0x2000) /* High-side SVS interrupt flag. */\r
+#define SVSHIFG_0 (0x0000) /* Reset not due to SVSH */\r
+#define SVSHIFG_1 (0x2000) /* Reset due to SVSH */\r
+#define PMMLPM5IFG (0x8000) /* LPMx.5 flag. */\r
+#define PMMLPM5IFG_0 (0x0000) /* Reset not due to wake-up from LPMx.5 */\r
+#define PMMLPM5IFG_1 (0x8000) /* Reset due to wake-up from LPMx.5 */\r
+#define PMMSPSIFG (0x0001) /* */\r
+#define PPWRIFG (0x1000) /* */\r
+\r
+/* PM5CTL0 Control Bits */\r
+#define LOCKLPM5 (0x0001) /* LPMx.5 Lock Bit */\r
+#define LOCKLPM5_0 (0x0000) /* LPMx.5 configuration is not locked and defaults to its reset \r
+ condition. */\r
+#define LOCKLPM5_1 (0x0001) /* LPMx.5 configuration remains locked. Pin state is held during \r
+ LPMx.5 entry and exit. */\r
+#define LPM5SW (0x0010) /* */\r
+#define LPM5SW_0 (0x0000) /* LPMx.5 switch disconnected */\r
+#define LPM5SW_1 (0x0010) /* LPMx.5 switch connected */\r
+#define LPM5SM (0x0020) /* */\r
+#define LPM5SM_0 (0x0000) /* Automatic mode for LPM3.5 switch that the switch is fully \r
+ handled by the circuitry during mode switch. */\r
+#define LPM5SM_1 (0x0020) /* Manual mode for LPM3.5 switch that the switch is specified by \r
+ LPM5SW bit setting in software. */\r
+\r
+\r
+/*****************************************************************************\r
+ RTC Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_RTC__ /* Definition to show that module is available */\r
+#define __MSP430_BASEADDRESS_RTC__ 0x0300\r
+#define RTC_BASE __MSP430_BASEADDRESS_RTC__\r
+\r
+sfr_w(RTCCTL); /* RTCCTL0 Register */\r
+sfr_b(RTCCTL_L);\r
+sfr_b(RTCCTL_H);\r
+sfr_w(RTCIV); /* Real-Time Clock Interrupt Vector Register */\r
+sfr_b(RTCIV_L);\r
+sfr_b(RTCIV_H);\r
+sfr_w(RTCMOD); /* RTC Counter Modulo Register */\r
+sfr_b(RTCMOD_L);\r
+sfr_b(RTCMOD_H);\r
+sfr_w(RTCCNT); /* RTC Counter Register */\r
+sfr_b(RTCCNT_L);\r
+sfr_b(RTCCNT_H);\r
+\r
+/* RTC Register Offsets */\r
+#define OFS_RTCCTL (0x0000)\r
+#define OFS_RTCIV (0x0004)\r
+#define OFS_RTCMOD (0x0008)\r
+#define OFS_RTCCNT (0x000C)\r
+\r
+/* RTC Control Bits */\r
+\r
+/* RTCCTL Control Bits */\r
+#define RTCIFG (0x0001) /* */\r
+#define RTCIFG_0 (0x0000) /* No interrupt pending */\r
+#define RTCIFG_1 (0x0001) /* Interrupt pending */\r
+#define RTCIE (0x0002) /* */\r
+#define RTCIE_0 (0x0000) /* Interrupt disabled */\r
+#define RTCIE_1 (0x0002) /* Interrupt enabled */\r
+#define RTCSR (0x0040) /* */\r
+#define RTCSR_0 (0x0000) /* Write 0 has no effect */\r
+#define RTCSR_1 (0x0040) /* Write 1 to this bit clears the counter value and reloads the \r
+ shadow register value from the modulo register at the next \r
+ tick of the selected source clock. No overflow event or \r
+ interrupt is generated. */\r
+#define RTCPS (0x0700) /* */\r
+#define RTCPS0 (0x0100) /* */\r
+#define RTCPS1 (0x0200) /* */\r
+#define RTCPS2 (0x0400) /* */\r
+#define RTCPS_0 (0x0000) /* /1 */\r
+#define RTCPS_1 (0x0100) /* /10 */\r
+#define RTCPS_2 (0x0200) /* /100 */\r
+#define RTCPS_3 (0x0300) /* /1000 */\r
+#define RTCPS_4 (0x0400) /* /16 */\r
+#define RTCPS_5 (0x0500) /* /64 */\r
+#define RTCPS_6 (0x0600) /* /256 */\r
+#define RTCPS_7 (0x0700) /* /1024 */\r
+#define RTCPS__1 (0x0000) /* /1 */\r
+#define RTCPS__10 (0x0100) /* /10 */\r
+#define RTCPS__100 (0x0200) /* /100 */\r
+#define RTCPS__1000 (0x0300) /* /1000 */\r
+#define RTCPS__16 (0x0400) /* /16 */\r
+#define RTCPS__64 (0x0500) /* /64 */\r
+#define RTCPS__256 (0x0600) /* /256 */\r
+#define RTCPS__1024 (0x0700) /* /1024 */\r
+#define RTCSS (0x3000) /* */\r
+#define RTCSS0 (0x1000) /* */\r
+#define RTCSS1 (0x2000) /* */\r
+#define RTCSS_0 (0x0000) /* Disabled */\r
+#define RTCSS_1 (0x1000) /* SMCLK */\r
+#define RTCSS_2 (0x2000) /* XT1CLK */\r
+#define RTCSS_3 (0x3000) /* VLOCLK */\r
+#define RTCSS__DISABLED (0x0000) /* Disabled */\r
+#define RTCSS__SMCLK (0x1000) /* SMCLK */\r
+#define RTCSS__XT1CLK (0x2000) /* XT1CLK */\r
+#define RTCSS__VLOCLK (0x3000) /* VLOCLK */\r
+\r
+/* RTCIV Control Bits */\r
+#define RTCIV0 (0x0001) /* Real-time clock interrupt vector value */\r
+#define RTCIV1 (0x0002) /* Real-time clock interrupt vector value */\r
+#define RTCIV2 (0x0004) /* Real-time clock interrupt vector value */\r
+#define RTCIV3 (0x0008) /* Real-time clock interrupt vector value */\r
+#define RTCIV4 (0x0010) /* Real-time clock interrupt vector value */\r
+#define RTCIV5 (0x0020) /* Real-time clock interrupt vector value */\r
+#define RTCIV6 (0x0040) /* Real-time clock interrupt vector value */\r
+#define RTCIV7 (0x0080) /* Real-time clock interrupt vector value */\r
+#define RTCIV8 (0x0100) /* Real-time clock interrupt vector value */\r
+#define RTCIV9 (0x0200) /* Real-time clock interrupt vector value */\r
+#define RTCIV10 (0x0400) /* Real-time clock interrupt vector value */\r
+#define RTCIV11 (0x0800) /* Real-time clock interrupt vector value */\r
+#define RTCIV12 (0x1000) /* Real-time clock interrupt vector value */\r
+#define RTCIV13 (0x2000) /* Real-time clock interrupt vector value */\r
+#define RTCIV14 (0x4000) /* Real-time clock interrupt vector value */\r
+#define RTCIV15 (0x8000) /* Real-time clock interrupt vector value */\r
+#define RTCIV_0 (0x0000) /* No interrupt pending */\r
+#define RTCIV_2 (0x0002) /* upt Source: RTC Counter Overflow; Interrupt Flag: RTCIFG */\r
+#define RTCIV__NONE (0x0000) /* No interrupt pending */\r
+#define RTCIV__RTCIFG (0x0002) /* upt Source: RTC Counter Overflow; Interrupt Flag: RTCIFG */\r
+\r
+\r
+/*****************************************************************************\r
+ SFR Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_SFR__ /* Definition to show that module is available */\r
+#define __MSP430_BASEADDRESS_SFR__ 0x0100\r
+#define SFR_BASE __MSP430_BASEADDRESS_SFR__\r
+\r
+sfr_w(SFRIE1); /* Interrupt Enable */\r
+sfr_b(SFRIE1_L);\r
+sfr_b(SFRIE1_H);\r
+sfr_w(SFRIFG1); /* Interrupt Flag */\r
+sfr_b(SFRIFG1_L);\r
+sfr_b(SFRIFG1_H);\r
+sfr_w(SFRRPCR); /* Reset Pin Control */\r
+sfr_b(SFRRPCR_L);\r
+sfr_b(SFRRPCR_H);\r
+\r
+/* SFR Register Offsets */\r
+#define OFS_SFRIE1 (0x0000)\r
+#define OFS_SFRIFG1 (0x0002)\r
+#define OFS_SFRRPCR (0x0004)\r
+\r
+/* SFR Control Bits */\r
+\r
+/* SFRIE1 Control Bits */\r
+#define WDTIE (0x0001) /* Watchdog timer interrupt enable */\r
+#define WDTIE_0 (0x0000) /* Interrupts disabled */\r
+#define WDTIE_1 (0x0001) /* Interrupts enabled */\r
+#define WDTIE__DISABLE (0x0000) /* Interrupts disabled */\r
+#define WDTIE__ENABLE (0x0001) /* Interrupts enabled */\r
+#define OFIE (0x0002) /* Oscillator fault interrupt enable */\r
+#define OFIE_0 (0x0000) /* Interrupts disabled */\r
+#define OFIE_1 (0x0002) /* Interrupts enabled */\r
+#define OFIE__DISABLE (0x0000) /* Interrupts disabled */\r
+#define OFIE__ENABLE (0x0002) /* Interrupts enabled */\r
+#define VMAIE (0x0008) /* Vacant memory access interrupt enable */\r
+#define VMAIE_0 (0x0000) /* Interrupts disabled */\r
+#define VMAIE_1 (0x0008) /* Interrupts enabled */\r
+#define VMAIE__DISABLE (0x0000) /* Interrupts disabled */\r
+#define VMAIE__ENABLE (0x0008) /* Interrupts enabled */\r
+#define NMIIE (0x0010) /* NMI pin interrupt enable */\r
+#define NMIIE_0 (0x0000) /* Interrupts disabled */\r
+#define NMIIE_1 (0x0010) /* Interrupts enabled */\r
+#define NMIIE__DISABLE (0x0000) /* Interrupts disabled */\r
+#define NMIIE__ENABLE (0x0010) /* Interrupts enabled */\r
+#define JMBINIE (0x0040) /* JTAG mailbox input interrupt enable */\r
+#define JMBINIE_0 (0x0000) /* Interrupts disabled */\r
+#define JMBINIE_1 (0x0040) /* Interrupts enabled */\r
+#define JMBINIE__DISABLE (0x0000) /* Interrupts disabled */\r
+#define JMBINIE__ENABLE (0x0040) /* Interrupts enabled */\r
+#define JMBOUTIE (0x0080) /* JTAG mailbox output interrupt enable */\r
+#define JMBOUTIE_0 (0x0000) /* Interrupts disabled */\r
+#define JMBOUTIE_1 (0x0080) /* Interrupts enabled */\r
+#define JMBOUTIE__DISABLE (0x0000) /* Interrupts disabled */\r
+#define JMBOUTIE__ENABLE (0x0080) /* Interrupts enabled */\r
+\r
+/* SFRIFG1 Control Bits */\r
+#define OFIFG (0x0002) /* Oscillator fault interrupt flag */\r
+#define OFIFG_0 (0x0000) /* No interrupt pending */\r
+#define OFIFG_1 (0x0002) /* Interrupt pending */\r
+#define VMAIFG (0x0008) /* Vacant memory access interrupt flag */\r
+#define VMAIFG_0 (0x0000) /* No interrupt pending */\r
+#define VMAIFG_1 (0x0008) /* Interrupt pending */\r
+#define NMIIFG (0x0010) /* NMI pin interrupt flag */\r
+#define NMIIFG_0 (0x0000) /* No interrupt pending */\r
+#define NMIIFG_1 (0x0010) /* Interrupt pending */\r
+#define WDTIFG (0x0001) /* Watchdog timer interrupt flag */\r
+#define WDTIFG_0 (0x0000) /* No interrupt pending */\r
+#define WDTIFG_1 (0x0001) /* Interrupt pending */\r
+#define JMBINIFG (0x0040) /* JTAG mailbox input interrupt flag */\r
+#define JMBINIFG_0 (0x0000) /* No interrupt pending. When in 16-bit mode (JMBMODE = 0), this \r
+ bit is cleared automatically when JMBI0 is read by the CPU. \r
+ When in 32-bit mode (JMBMODE = 1), this bit is cleared \r
+ automatically when both JMBI0 and JMBI1 have been read by the \r
+ CPU. This bit is also cleared when the associated vector in \r
+ SYSUNIV has been read */\r
+#define JMBINIFG_1 (0x0040) /* Interrupt pending. A message is waiting in the JMBIN \r
+ registers. In 16-bit mode (JMBMODE = 0) when JMBI0 has been \r
+ written by the JTAG module. In 32-bit mode (JMBMODE = 1) when \r
+ JMBI0 and JMBI1 have been written by the JTAG module. */\r
+#define JMBOUTIFG (0x0080) /* JTAG mailbox output interrupt flag */\r
+#define JMBOUTIFG_0 (0x0000) /* No interrupt pending. When in 16-bit mode (JMBMODE = 0), this \r
+ bit is cleared automatically when JMBO0 has been written with \r
+ a new message to the JTAG module by the CPU. When in 32-bit \r
+ mode (JMBMODE = 1), this bit is cleared automatically when \r
+ both JMBO0 and JMBO1 have been written with new messages to \r
+ the JTAG module by the CPU. This bit is also cleared when the \r
+ associated vector in SYSUNIV has been read. */\r
+#define JMBOUTIFG_1 (0x0080) /* Interrupt pending. JMBO registers are ready for new messages. \r
+ In 16-bit mode (JMBMODE = 0), JMBO0 has been received by the \r
+ JTAG module and is ready for a new message from the CPU. In \r
+ 32-bit mode (JMBMODE = 1), JMBO0 and JMBO1 have been received \r
+ by the JTAG module and are ready for new messages from the \r
+ CPU. */\r
+\r
+/* SFRRPCR Control Bits */\r
+#define SYSNMI (0x0001) /* NMI select */\r
+#define SYSNMI_0 (0x0000) /* Reset function */\r
+#define SYSNMI_1 (0x0001) /* NMI function */\r
+#define SYSNMI__RESET (0x0000) /* Reset function */\r
+#define SYSNMI__NMI (0x0001) /* NMI function */\r
+#define SYSNMIIES (0x0002) /* NMI edge select */\r
+#define SYSNMIIES_0 (0x0000) /* NMI on rising edge */\r
+#define SYSNMIIES_1 (0x0002) /* NMI on falling edge */\r
+#define SYSNMIIES__RISING (0x0000) /* NMI on rising edge */\r
+#define SYSNMIIES__FALLING (0x0002) /* NMI on falling edge */\r
+#define SYSRSTUP (0x0004) /* Reset resistor pin pullup or pulldown */\r
+#define SYSRSTUP_0 (0x0000) /* Pulldown is selected */\r
+#define SYSRSTUP_1 (0x0004) /* Pullup is selected */\r
+#define SYSRSTUP__PULLDOWN (0x0000) /* Pulldown is selected */\r
+#define SYSRSTUP__PULLUP (0x0004) /* Pullup is selected */\r
+#define SYSRSTRE (0x0008) /* Reset pin resistor enable */\r
+#define SYSRSTRE_0 (0x0000) /* Pullup or pulldown resistor at the RST/NMI pin is disabled */\r
+#define SYSRSTRE_1 (0x0008) /* Pullup or pulldown resistor at the RST/NMI pin is enabled */\r
+#define SYSRSTRE__DISABLE (0x0000) /* Pullup or pulldown resistor at the RST/NMI pin is disabled */\r
+#define SYSRSTRE__ENABLE (0x0008) /* Pullup or pulldown resistor at the RST/NMI pin is enabled */\r
+#define SYSFLTE (0x0010) /* Reset pin filter enable */\r
+#define SYSFLTE_0 (0x0000) /* Digital filter on reset pin is disabled */\r
+#define SYSFLTE_1 (0x0010) /* Digital filter on reset pin is enabled */\r
+#define SYSFLTE__DISABLED (0x0000) /* Digital filter on reset pin is disabled */\r
+#define SYSFLTE__ENABLED (0x0010) /* Digital filter on reset pin is enabled */\r
+\r
+\r
+/*****************************************************************************\r
+ SYS Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_SYS__ /* Definition to show that module is available */\r
+#define __MSP430_BASEADDRESS_SYS__ 0x0140\r
+#define SYS_BASE __MSP430_BASEADDRESS_SYS__\r
+\r
+sfr_w(SYSCTL); /* System Control */\r
+sfr_b(SYSCTL_L);\r
+sfr_b(SYSCTL_H);\r
+sfr_w(SYSBSLC); /* Bootloader Configuration */\r
+sfr_b(SYSBSLC_L);\r
+sfr_b(SYSBSLC_H);\r
+sfr_w(SYSJMBC); /* JTAG Mailbox Control */\r
+sfr_b(SYSJMBC_L);\r
+sfr_b(SYSJMBC_H);\r
+sfr_w(SYSJMBI0); /* JTAG Mailbox Input 0 */\r
+sfr_b(SYSJMBI0_L);\r
+sfr_b(SYSJMBI0_H);\r
+sfr_w(SYSJMBI1); /* JTAG Mailbox Input 1 */\r
+sfr_b(SYSJMBI1_L);\r
+sfr_b(SYSJMBI1_H);\r
+sfr_w(SYSJMBO0); /* JTAG Mailbox Output 0 */\r
+sfr_b(SYSJMBO0_L);\r
+sfr_b(SYSJMBO0_H);\r
+sfr_w(SYSJMBO1); /* JTAG Mailbox Output 1 */\r
+sfr_b(SYSJMBO1_L);\r
+sfr_b(SYSJMBO1_H);\r
+sfr_w(SYSUNIV); /* User NMI Vector Generator */\r
+sfr_b(SYSUNIV_L);\r
+sfr_b(SYSUNIV_H);\r
+sfr_w(SYSSNIV); /* System NMI Vector Generator */\r
+sfr_b(SYSSNIV_L);\r
+sfr_b(SYSSNIV_H);\r
+sfr_w(SYSRSTIV); /* Reset Vector Generator */\r
+sfr_b(SYSRSTIV_L);\r
+sfr_b(SYSRSTIV_H);\r
+sfr_w(SYSCFG0); /* System Configuration 0 */\r
+sfr_b(SYSCFG0_L);\r
+sfr_b(SYSCFG0_H);\r
+sfr_w(SYSCFG1); /* System Configuration 1 */\r
+sfr_b(SYSCFG1_L);\r
+sfr_b(SYSCFG1_H);\r
+sfr_w(SYSCFG2); /* System Configuration 2 */\r
+sfr_b(SYSCFG2_L);\r
+sfr_b(SYSCFG2_H);\r
+sfr_w(SYSCFG3); /* System Configuration 3 */\r
+sfr_b(SYSCFG3_L);\r
+sfr_b(SYSCFG3_H);\r
+\r
+/* SYS Register Offsets */\r
+#define OFS_SYSCTL (0x0000)\r
+#define OFS_SYSBSLC (0x0002)\r
+#define OFS_SYSJMBC (0x0006)\r
+#define OFS_SYSJMBI0 (0x0008)\r
+#define OFS_SYSJMBI1 (0x000A)\r
+#define OFS_SYSJMBO0 (0x000C)\r
+#define OFS_SYSJMBO1 (0x000E)\r
+#define OFS_SYSUNIV (0x001A)\r
+#define OFS_SYSSNIV (0x001C)\r
+#define OFS_SYSRSTIV (0x001E)\r
+#define OFS_SYSCFG0 (0x0020)\r
+#define OFS_SYSCFG1 (0x0022)\r
+#define OFS_SYSCFG2 (0x0024)\r
+#define OFS_SYSCFG3 (0x0026)\r
+\r
+/* SYS Control Bits */\r
+\r
+/* SYSCTL Control Bits */\r
+#define SYSRIVECT (0x0001) /* RAM-based interrupt vectors */\r
+#define SYSRIVECT_0 (0x0000) /* Interrupt vectors generated with end address TOP of lower 64K \r
+ FRAM FFFFh */\r
+#define SYSRIVECT_1 (0x0001) /* Interrupt vectors generated with end address TOP of RAM, when \r
+ RAM available */\r
+#define SYSRIVECT__FRAM (0x0000) /* Interrupt vectors generated with end address TOP of lower 64K \r
+ FRAM FFFFh */\r
+#define SYSRIVECT__RAM (0x0001) /* Interrupt vectors generated with end address TOP of RAM, when \r
+ RAM available */\r
+#define SYSPMMPE (0x0004) /* PMM access protect */\r
+#define SYSPMMPE_0 (0x0000) /* Access from anywhere in memory */\r
+#define SYSPMMPE_1 (0x0004) /* Access only from the BSL segments */\r
+#define SYSPMMPE__DIS (0x0000) /* Access from anywhere in memory */\r
+#define SYSPMMPE__EN (0x0004) /* Access only from the BSL segments */\r
+#define SYSBSLIND (0x0010) /* BSL entry indication */\r
+#define SYSBSLIND_0 (0x0000) /* No BSL entry sequence detected */\r
+#define SYSBSLIND_1 (0x0010) /* BSL entry sequence detected */\r
+#define SYSBSLIND__CLR (0x0000) /* No BSL entry sequence detected */\r
+#define SYSBSLIND__SET (0x0010) /* BSL entry sequence detected */\r
+#define SYSJTAGPIN (0x0020) /* Dedicated JTAG pins enable */\r
+#define SYSJTAGPIN_0 (0x0000) /* Shared JTAG pins (JTAG mode selectable using SBW sequence) */\r
+#define SYSJTAGPIN_1 (0x0020) /* Dedicated JTAG pins (explicit 4-wire JTAG mode selection) */\r
+#define SYSJTAGPIN__SHARED (0x0000) /* Shared JTAG pins (JTAG mode selectable using SBW sequence) */\r
+#define SYSJTAGPIN__DEDICATED (0x0020) /* Dedicated JTAG pins (explicit 4-wire JTAG mode selection) */\r
+\r
+/* SYSBSLC Control Bits */\r
+#define SYSBSLR (0x0004) /* */\r
+#define SYSBSLR_0 (0x0000) /* No RAM assigned to BSL area */\r
+#define SYSBSLR_1 (0x0004) /* Lowest 16 bytes of RAM assigned to BSL */\r
+#define SYSBSLR__NORAM (0x0000) /* No RAM assigned to BSL area */\r
+#define SYSBSLR__RAM (0x0004) /* Lowest 16 bytes of RAM assigned to BSL */\r
+#define SYSBSLOFF (0x4000) /* */\r
+#define SYSBSLOFF_0 (0x0000) /* BSL memory is addressed when this area is read. */\r
+#define SYSBSLOFF_1 (0x4000) /* BSL memory behaves like vacant memory. Reads cause 3FFFh to be\r
+ read. Fetches cause JMP $ to be executed. */\r
+#define SYSBSLOFF__ON (0x0000) /* BSL memory is addressed when this area is read. */\r
+#define SYSBSLOFF__OFF (0x4000) /* BSL memory behaves like vacant memory. Reads cause 3FFFh to be\r
+ read. Fetches cause JMP $ to be executed. */\r
+#define SYSBSLPE (0x8000) /* */\r
+#define SYSBSLPE_0 (0x0000) /* Area not protected. Read, program, and erase of BSL memory is \r
+ possible. */\r
+#define SYSBSLPE_1 (0x8000) /* Area protected */\r
+#define SYSBSLPE__NOTPROT (0x0000) /* Area not protected. Read, program, and erase of BSL memory is \r
+ possible. */\r
+#define SYSBSLPE__PROT (0x8000) /* Area protected */\r
+\r
+/* SYSJMBC Control Bits */\r
+#define JMBIN0FG (0x0001) /* Incoming JTAG Mailbox 0 flag */\r
+#define JMBIN0FG_0 (0x0000) /* JMBI0 has no new data */\r
+#define JMBIN0FG_1 (0x0001) /* JMBI0 has new data available */\r
+#define JMBIN0FG__NODAT (0x0000) /* JMBI0 has no new data */\r
+#define JMBIN0FG__NEWDAT (0x0001) /* JMBI0 has new data available */\r
+#define JMBIN1FG (0x0002) /* Incoming JTAG Mailbox 1 flag */\r
+#define JMBIN1FG_0 (0x0000) /* JMBI1 has no new data */\r
+#define JMBIN1FG_1 (0x0002) /* JMBI1 has new data available */\r
+#define JMBIN1FG__NODAT (0x0000) /* JMBI1 has no new data */\r
+#define JMBIN1FG__NEWDAT (0x0002) /* JMBI1 has new data available */\r
+#define JMBOUT0FG (0x0004) /* Outgoing JTAG Mailbox 0 flag */\r
+#define JMBOUT0FG_0 (0x0000) /* JMBO0 is not ready to receive new data */\r
+#define JMBOUT0FG_1 (0x0004) /* JMBO0 is ready to receive new data */\r
+#define JMBOUT0FG__BUSY (0x0000) /* JMBO0 is not ready to receive new data */\r
+#define JMBOUT0FG__READY (0x0004) /* JMBO0 is ready to receive new data */\r
+#define JMBOUT1FG (0x0008) /* Outgoing JTAG Mailbox 1 flag */\r
+#define JMBOUT1FG_0 (0x0000) /* JMBO1 is not ready to receive new data */\r
+#define JMBOUT1FG_1 (0x0008) /* JMBO1 is ready to receive new data */\r
+#define JMBOUT1FG__BUSY (0x0000) /* JMBO1 is not ready to receive new data */\r
+#define JMBOUT1FG__READY (0x0008) /* JMBO1 is ready to receive new data */\r
+#define JMBMODE (0x0010) /* Operation mode of JMB */\r
+#define JMBMODE_0 (0x0000) /* 16-bit transfers using JMBO0 and JMBI0 only */\r
+#define JMBMODE_1 (0x0010) /* 32-bit transfers using JMBO0 with JMBO1 and JMBI0 with JMBI1 */\r
+#define JMBMODE__16BIT (0x0000) /* 16-bit transfers using JMBO0 and JMBI0 only */\r
+#define JMBMODE__32BIT (0x0010) /* 32-bit transfers using JMBO0 with JMBO1 and JMBI0 with JMBI1 */\r
+#define JMBCLR0OFF (0x0040) /* Incoming JTAG Mailbox 0 flag auto-clear disable */\r
+#define JMBCLR0OFF_0 (0x0000) /* JMBIN0FG cleared on read of JMB0IN register */\r
+#define JMBCLR0OFF_1 (0x0040) /* JMBIN0FG cleared by software */\r
+#define JMBCLR0OFF__CLRORD (0x0000) /* JMBIN0FG cleared on read of JMB0IN register */\r
+#define JMBCLR0OFF__CLRBSW (0x0040) /* JMBIN0FG cleared by software */\r
+#define JMBCLR1OFF (0x0080) /* Incoming JTAG Mailbox 1 flag auto-clear disable */\r
+#define JMBCLR1OFF_0 (0x0000) /* JMBIN1FG cleared on read of JMB1IN register */\r
+#define JMBCLR1OFF_1 (0x0080) /* JMBIN1FG cleared by software */\r
+#define JMBCLR1OFF__CLRORD (0x0000) /* JMBIN1FG cleared on read of JMB1IN register */\r
+#define JMBCLR1OFF__CLRBSW (0x0080) /* JMBIN1FG cleared by software */\r
+\r
+/* SYSJMBI0 Control Bits */\r
+#define MSGLO (0x00ff) /* JTAG mailbox incoming message low byte */\r
+#define MSGLO0 (0x0001) /* JTAG mailbox incoming message low byte */\r
+#define MSGLO1 (0x0002) /* JTAG mailbox incoming message low byte */\r
+#define MSGLO2 (0x0004) /* JTAG mailbox incoming message low byte */\r
+#define MSGLO3 (0x0008) /* JTAG mailbox incoming message low byte */\r
+#define MSGLO4 (0x0010) /* JTAG mailbox incoming message low byte */\r
+#define MSGLO5 (0x0020) /* JTAG mailbox incoming message low byte */\r
+#define MSGLO6 (0x0040) /* JTAG mailbox incoming message low byte */\r
+#define MSGLO7 (0x0080) /* JTAG mailbox incoming message low byte */\r
+#define MSGHI (0xff00) /* JTAG mailbox incoming message high byte */\r
+#define MSGHI0 (0x0100) /* JTAG mailbox incoming message high byte */\r
+#define MSGHI1 (0x0200) /* JTAG mailbox incoming message high byte */\r
+#define MSGHI2 (0x0400) /* JTAG mailbox incoming message high byte */\r
+#define MSGHI3 (0x0800) /* JTAG mailbox incoming message high byte */\r
+#define MSGHI4 (0x1000) /* JTAG mailbox incoming message high byte */\r
+#define MSGHI5 (0x2000) /* JTAG mailbox incoming message high byte */\r
+#define MSGHI6 (0x4000) /* JTAG mailbox incoming message high byte */\r
+#define MSGHI7 (0x8000) /* JTAG mailbox incoming message high byte */\r
+\r
+/* SYSUNIV Control Bits */\r
+#define SYSUNIV0 (0x0001) /* User NMI vector */\r
+#define SYSUNIV1 (0x0002) /* User NMI vector */\r
+#define SYSUNIV2 (0x0004) /* User NMI vector */\r
+#define SYSUNIV3 (0x0008) /* User NMI vector */\r
+#define SYSUNIV4 (0x0010) /* User NMI vector */\r
+#define SYSUNIV5 (0x0020) /* User NMI vector */\r
+#define SYSUNIV6 (0x0040) /* User NMI vector */\r
+#define SYSUNIV7 (0x0080) /* User NMI vector */\r
+#define SYSUNIV8 (0x0100) /* User NMI vector */\r
+#define SYSUNIV9 (0x0200) /* User NMI vector */\r
+#define SYSUNIV10 (0x0400) /* User NMI vector */\r
+#define SYSUNIV11 (0x0800) /* User NMI vector */\r
+#define SYSUNIV12 (0x1000) /* User NMI vector */\r
+#define SYSUNIV13 (0x2000) /* User NMI vector */\r
+#define SYSUNIV14 (0x4000) /* User NMI vector */\r
+#define SYSUNIV15 (0x8000) /* User NMI vector */\r
+#define SYSUNIV_0 (0x0000) /* No interrupt pending */\r
+#define SYSUNIV_2 (0x0002) /* NMIFG NMI pin or SVSH event */\r
+#define SYSUNIV_4 (0x0004) /* OFIFG oscillator fault */\r
+#define SYSUNIV__NONE (0x0000) /* No interrupt pending */\r
+#define SYSUNIV__NMIIFG (0x0002) /* NMIFG NMI pin or SVSH event */\r
+#define SYSUNIV__OFIFG (0x0004) /* OFIFG oscillator fault */\r
+\r
+/* SYSSNIV Control Bits */\r
+#define SYSSNIV0 (0x0001) /* System NMI vector */\r
+#define SYSSNIV1 (0x0002) /* System NMI vector */\r
+#define SYSSNIV2 (0x0004) /* System NMI vector */\r
+#define SYSSNIV3 (0x0008) /* System NMI vector */\r
+#define SYSSNIV4 (0x0010) /* System NMI vector */\r
+#define SYSSNIV5 (0x0020) /* System NMI vector */\r
+#define SYSSNIV6 (0x0040) /* System NMI vector */\r
+#define SYSSNIV7 (0x0080) /* System NMI vector */\r
+#define SYSSNIV8 (0x0100) /* System NMI vector */\r
+#define SYSSNIV9 (0x0200) /* System NMI vector */\r
+#define SYSSNIV10 (0x0400) /* System NMI vector */\r
+#define SYSSNIV11 (0x0800) /* System NMI vector */\r
+#define SYSSNIV12 (0x1000) /* System NMI vector */\r
+#define SYSSNIV13 (0x2000) /* System NMI vector */\r
+#define SYSSNIV14 (0x4000) /* System NMI vector */\r
+#define SYSSNIV15 (0x8000) /* System NMI vector */\r
+#define SYSSNIV_0 (0x0000) /* No interrupt pending */\r
+#define SYSSNIV_2 (0x0002) /* SVS low-power reset entry */\r
+#define SYSSNIV_4 (0x0004) /* Uncorrectable FRAM bit error detection */\r
+#define SYSSNIV_6 (0x0006) /* Reserved */\r
+#define SYSSNIV_8 (0x0008) /* Reserved */\r
+#define SYSSNIV_10 (0x000a) /* Reserved */\r
+#define SYSSNIV_12 (0x000c) /* Reserved */\r
+#define SYSSNIV_14 (0x000e) /* Reserved */\r
+#define SYSSNIV_16 (0x0010) /* Reserved */\r
+#define SYSSNIV_18 (0x0012) /* VMAIFG Vacant memory access */\r
+#define SYSSNIV_20 (0x0014) /* JMBINIFG JTAG mailbox input */\r
+#define SYSSNIV_22 (0x0016) /* JMBOUTIFG JTAG mailbox output */\r
+#define SYSSNIV_24 (0x0018) /* Correctable FRAM bit error detection */\r
+#define SYSSNIV__NONE (0x0000) /* No interrupt pending */\r
+#define SYSSNIV__SVSLIFG (0x0002) /* SVS low-power reset entry */\r
+#define SYSSNIV__UBDIFG (0x0004) /* Uncorrectable FRAM bit error detection */\r
+#define SYSSNIV__VMAIFG (0x0012) /* VMAIFG Vacant memory access */\r
+#define SYSSNIV__JMBINIFG (0x0014) /* JMBINIFG JTAG mailbox input */\r
+#define SYSSNIV__JMBOUTIFG (0x0016) /* JMBOUTIFG JTAG mailbox output */\r
+#define SYSSNIV__CBDIFG (0x0018) /* Correctable FRAM bit error detection */\r
+\r
+/* SYSRSTIV Control Bits */\r
+#define SYSRSTIV0 (0x0001) /* Reset interrupt vector */\r
+#define SYSRSTIV1 (0x0002) /* Reset interrupt vector */\r
+#define SYSRSTIV2 (0x0004) /* Reset interrupt vector */\r
+#define SYSRSTIV3 (0x0008) /* Reset interrupt vector */\r
+#define SYSRSTIV4 (0x0010) /* Reset interrupt vector */\r
+#define SYSRSTIV5 (0x0020) /* Reset interrupt vector */\r
+#define SYSRSTIV6 (0x0040) /* Reset interrupt vector */\r
+#define SYSRSTIV7 (0x0080) /* Reset interrupt vector */\r
+#define SYSRSTIV8 (0x0100) /* Reset interrupt vector */\r
+#define SYSRSTIV9 (0x0200) /* Reset interrupt vector */\r
+#define SYSRSTIV10 (0x0400) /* Reset interrupt vector */\r
+#define SYSRSTIV11 (0x0800) /* Reset interrupt vector */\r
+#define SYSRSTIV12 (0x1000) /* Reset interrupt vector */\r
+#define SYSRSTIV13 (0x2000) /* Reset interrupt vector */\r
+#define SYSRSTIV14 (0x4000) /* Reset interrupt vector */\r
+#define SYSRSTIV15 (0x8000) /* Reset interrupt vector */\r
+#define SYSRSTIV_0 (0x0000) /* No interrupt pending */\r
+#define SYSRSTIV_2 (0x0002) /* Brownout */\r
+#define SYSRSTIV_4 (0x0004) /* RSTIFG RST/NMI */\r
+#define SYSRSTIV_6 (0x0006) /* PMMSWBOR software BOR */\r
+#define SYSRSTIV_8 (0x0008) /* LPMx.5 wakeup */\r
+#define SYSRSTIV_10 (0x000a) /* Security violation */\r
+#define SYSRSTIV_12 (0x000c) /* Reserved */\r
+#define SYSRSTIV_14 (0x000e) /* SVSHIFG SVSH event */\r
+#define SYSRSTIV_16 (0x0010) /* Reserved */\r
+#define SYSRSTIV_18 (0x0012) /* Reserved */\r
+#define SYSRSTIV_20 (0x0014) /* PMMSWPOR software POR */\r
+#define SYSRSTIV_22 (0x0016) /* WDTIFG watchdog timeout */\r
+#define SYSRSTIV_24 (0x0018) /* WDTPW watchdog password violation */\r
+#define SYSRSTIV_26 (0x001a) /* FRCTLPW password violation */\r
+#define SYSRSTIV_28 (0x001c) /* Uncorrectable FRAM bit error detection */\r
+#define SYSRSTIV_30 (0x001e) /* Peripheral area fetch */\r
+#define SYSRSTIV_32 (0x0020) /* PMM password violation */\r
+#define SYSRSTIV_34 (0x0022) /* Reserved */\r
+#define SYSRSTIV_36 (0x0024) /* FLL unlock (PUC) */\r
+#define SYSRSTIV__NONE (0x0000) /* No interrupt pending */\r
+#define SYSRSTIV__BOR (0x0002) /* Brownout */\r
+#define SYSRSTIV__RSTNMI (0x0004) /* RSTIFG RST/NMI */\r
+#define SYSRSTIV__PMMSWBOR (0x0006) /* PMMSWBOR software BOR */\r
+#define SYSRSTIV__LPM5WU (0x0008) /* LPMx.5 wakeup */\r
+#define SYSRSTIV__SECYV (0x000a) /* Security violation */\r
+#define SYSRSTIV__SVSHIFG (0x000e) /* SVSHIFG SVSH event */\r
+#define SYSRSTIV__PMMSWPOR (0x0014) /* PMMSWPOR software POR */\r
+#define SYSRSTIV__WDTIFG (0x0016) /* WDTIFG watchdog timeout */\r
+#define SYSRSTIV__WDTPW (0x0018) /* WDTPW watchdog password violation */\r
+#define SYSRSTIV__FRCTLPW (0x001a) /* FRCTLPW password violation */\r
+#define SYSRSTIV__UBDIFG (0x001c) /* Uncorrectable FRAM bit error detection */\r
+#define SYSRSTIV__PERF (0x001e) /* Peripheral area fetch */\r
+#define SYSRSTIV__PMMPW (0x0020) /* PMM password violation */\r
+#define SYSRSTIV__FLLUL (0x0024) /* FLL unlock (PUC) */\r
+\r
+/* SYSCFG0 Control Bits */\r
+#define PFWP (0x0001) /* */\r
+#define PFWP_0 (0x0000) /* Program FRAM write enable */\r
+#define PFWP_1 (0x0001) /* Program FRAM write protected (not writable) */\r
+#define PFWP__WEN (0x0000) /* Program FRAM write enable */\r
+#define PFWP__WPROT (0x0001) /* Program FRAM write protected (not writable) */\r
+#define FRWPPW (0xa500) /* FRWPPW password. */\r
+#define FRWPPW0 (0x0100) /* FRWPPW password. */\r
+#define FRWPPW1 (0x0200) /* FRWPPW password. */\r
+#define FRWPPW2 (0x0400) /* FRWPPW password. */\r
+#define FRWPPW3 (0x0800) /* FRWPPW password. */\r
+#define FRWPPW4 (0x1000) /* FRWPPW password. */\r
+#define FRWPPW5 (0x2000) /* FRWPPW password. */\r
+#define FRWPPW6 (0x4000) /* FRWPPW password. */\r
+#define FRWPPW7 (0x8000) /* FRWPPW password. */\r
+#define DFWP (0x0002) /* */\r
+#define DFWP_0 (0x0000) /* Data FRAM write enable */\r
+#define DFWP_1 (0x0002) /* Data FRAM write protected (not writable) */\r
+#define DFWP__WEN (0x0000) /* Data FRAM write enable */\r
+#define DFWP__WPROT (0x0002) /* Data FRAM write protected (not writable) */\r
+#define FRWPOA (0x00fc) /* */\r
+#define FRWPOA0 (0x0004) /* */\r
+#define FRWPOA1 (0x0008) /* */\r
+#define FRWPOA2 (0x0010) /* */\r
+#define FRWPOA3 (0x0020) /* */\r
+#define FRWPOA4 (0x0040) /* */\r
+#define FRWPOA5 (0x0080) /* */\r
+\r
+/* SYSCFG1 Control Bits */\r
+#define IREN (0x0001) /* */\r
+#define IREN_0 (0x0000) /* Infrared function disabled */\r
+#define IREN_1 (0x0001) /* Infrared function enabled */\r
+#define IREN__DIS (0x0000) /* Infrared function disabled */\r
+#define IREN__EN (0x0001) /* Infrared function enabled */\r
+#define IRPSEL (0x0002) /* */\r
+#define IRPSEL_0 (0x0000) /* Normal polarity */\r
+#define IRPSEL_1 (0x0002) /* Inverted polarity */\r
+#define IRPSEL__NORM (0x0000) /* Normal polarity */\r
+#define IRPSEL__INV (0x0002) /* Inverted polarity */\r
+#define IRMSEL (0x0004) /* */\r
+#define IRMSEL_0 (0x0000) /* ASK mode */\r
+#define IRMSEL_1 (0x0004) /* FSK mode */\r
+#define IRMSEL__ASK (0x0000) /* ASK mode */\r
+#define IRMSEL__FSK (0x0004) /* FSK mode */\r
+#define IRDSSEL (0x0008) /* */\r
+#define IRDSSEL_0 (0x0000) /* From hardware peripherals upon device configuration */\r
+#define IRDSSEL_1 (0x0008) /* From IRDATA bit */\r
+#define IRDSSEL__HW (0x0000) /* From hardware peripherals upon device configuration */\r
+#define IRDSSEL__IRDATA (0x0008) /* From IRDATA bit */\r
+#define IRDATA (0x0010) /* */\r
+#define IRDATA_0 (0x0000) /* Infrared data logic 0 */\r
+#define IRDATA_1 (0x0010) /* Infrared data logic 1 */\r
+#define IRDATA__LOW (0x0000) /* Infrared data logic 0 */\r
+#define IRDATA__HIGH (0x0010) /* Infrared data logic 1 */\r
+#define SYNCSEL (0x00c0) /* */\r
+#define SYNCSEL0 (0x0040) /* */\r
+#define SYNCSEL1 (0x0080) /* */\r
+#define SYNCSEL_0 (0x0000) /* External source is selected */\r
+#define SYNCSEL_1 (0x0040) /* ADC as the source is selected */\r
+#define SYNCSEL_2 (0x0080) /* Comparator as the source is selected */\r
+#define SYNCSEL_3 (0x00c0) /* Reserved */\r
+\r
+/* SYSCFG2 Control Bits */\r
+#define RTCCKSEL (0x0400) /* */\r
+#define RTCCKSEL_0 (0x0000) /* SMCLK is selected */\r
+#define RTCCKSEL_1 (0x0400) /* ACLK is selected */\r
+#define USCIB0RMP (0x0800) /* */\r
+#define USCIB0RMP_0 (0x0000) /* Default function. See the device-specific data sheet for \r
+ details. */\r
+#define USCIB0RMP_1 (0x0800) /* Remapped function. See the device-specific data sheet for \r
+ details. */\r
+#define TB0TRGSEL (0x8000) /* */\r
+#define TB0TRGSEL_0 (0x0000) /* Internal source is selected */\r
+#define TB0TRGSEL_1 (0x8000) /* External source is selected */\r
+\r
+/* SYSCFG3 Control Bits */\r
+#define USCIA0RMP (0x0001) /* */\r
+#define USCIA0RMP_0 (0x0000) /* Default function. See the device-specific data sheet for \r
+ details. */\r
+#define USCIA0RMP_1 (0x0001) /* Remapped function. See the device-specific data sheet for \r
+ details. */\r
+#define TA2RMP (0x0004) /* */\r
+#define TA2RMP_0 (0x0000) /* Default function. See the device-specific data sheet for \r
+ details. */\r
+#define TA2RMP_1 (0x0004) /* Remapped function. See the device-specific data sheet for \r
+ details. */\r
+#define TA3RMP (0x0008) /* */\r
+#define TA3RMP_0 (0x0000) /* Default function. See the device-specific data sheet for \r
+ details. */\r
+#define TA3RMP_1 (0x0008) /* Remapped function. See the device-specific data sheet for \r
+ details. */\r
+#define USCIB1RMP (0x0010) /* */\r
+#define USCIB1RMP_0 (0x0000) /* Default function. See the device-specific data sheet for \r
+ details. */\r
+#define USCIB1RMP_1 (0x0010) /* Remapped function. See the device-specific data sheet for \r
+ details. */\r
+\r
+\r
+/*****************************************************************************\r
+ TA0 Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_TA0__ 3 /* Definition to show that module is available */\r
+#ifndef __MSP430_HAS_TAx__\r
+#define __MSP430_HAS_TAx__\r
+#endif\r
+#define __MSP430_BASEADDRESS_TA0__ 0x0380\r
+#define TA0_BASE __MSP430_BASEADDRESS_TA0__\r
+\r
+sfr_w(TA0CTL); /* TimerAx Control Register */\r
+sfr_b(TA0CTL_L);\r
+sfr_b(TA0CTL_H);\r
+sfr_w(TA0CCTL0); /* Timer_A Capture/Compare Control Register */\r
+sfr_b(TA0CCTL0_L);\r
+sfr_b(TA0CCTL0_H);\r
+sfr_w(TA0CCTL1); /* Timer_A Capture/Compare Control Register */\r
+sfr_b(TA0CCTL1_L);\r
+sfr_b(TA0CCTL1_H);\r
+sfr_w(TA0CCTL2); /* Timer_A Capture/Compare Control Register */\r
+sfr_b(TA0CCTL2_L);\r
+sfr_b(TA0CCTL2_H);\r
+sfr_w(TA0R); /* TimerA register */\r
+sfr_b(TA0R_L);\r
+sfr_b(TA0R_H);\r
+sfr_w(TA0CCR0); /* Timer_A Capture/Compare Register */\r
+sfr_b(TA0CCR0_L);\r
+sfr_b(TA0CCR0_H);\r
+sfr_w(TA0CCR1); /* Timer_A Capture/Compare Register */\r
+sfr_b(TA0CCR1_L);\r
+sfr_b(TA0CCR1_H);\r
+sfr_w(TA0CCR2); /* Timer_A Capture/Compare Register */\r
+sfr_b(TA0CCR2_L);\r
+sfr_b(TA0CCR2_H);\r
+sfr_w(TA0EX0); /* TimerAx Expansion 0 Register */\r
+sfr_b(TA0EX0_L);\r
+sfr_b(TA0EX0_H);\r
+sfr_w(TA0IV); /* TimerAx Interrupt Vector Register */\r
+sfr_b(TA0IV_L);\r
+sfr_b(TA0IV_H);\r
+\r
+/* TA0 Register Offsets */\r
+#define OFS_TA0CTL (0x0000)\r
+#define OFS_TA0CCTL0 (0x0002)\r
+#define OFS_TA0CCTL1 (0x0004)\r
+#define OFS_TA0CCTL2 (0x0006)\r
+#define OFS_TA0R (0x0010)\r
+#define OFS_TA0CCR0 (0x0012)\r
+#define OFS_TA0CCR1 (0x0014)\r
+#define OFS_TA0CCR2 (0x0016)\r
+#define OFS_TA0EX0 (0x0020)\r
+#define OFS_TA0IV (0x002E)\r
+\r
+/* TA0 Control Bits */\r
+\r
+/* TA0CTL Control Bits */\r
+#define TAIFG (0x0001) /* TimerA interrupt flag */\r
+#define TAIFG_0 (0x0000) /* No interrupt pending */\r
+#define TAIFG_1 (0x0001) /* Interrupt pending */\r
+#define TAIE (0x0002) /* TimerA interrupt enable */\r
+#define TAIE_0 (0x0000) /* Interrupt disabled */\r
+#define TAIE_1 (0x0002) /* Interrupt enabled */\r
+#define TACLR (0x0004) /* TimerA clear */\r
+#define MC (0x0030) /* Mode control */\r
+#define MC0 (0x0010) /* Mode control */\r
+#define MC1 (0x0020) /* Mode control */\r
+#define MC_0 (0x0000) /* Stop mode: Timer is halted */\r
+#define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */\r
+#define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */\r
+#define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */\r
+#define MC__STOP (0x0000) /* Stop mode: Timer is halted */\r
+#define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */\r
+#define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */\r
+#define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */\r
+#define ID (0x00c0) /* Input divider */\r
+#define ID0 (0x0040) /* Input divider */\r
+#define ID1 (0x0080) /* Input divider */\r
+#define ID_0 (0x0000) /* /1 */\r
+#define ID_1 (0x0040) /* /2 */\r
+#define ID_2 (0x0080) /* /4 */\r
+#define ID_3 (0x00c0) /* /8 */\r
+#define ID__1 (0x0000) /* /1 */\r
+#define ID__2 (0x0040) /* /2 */\r
+#define ID__4 (0x0080) /* /4 */\r
+#define ID__8 (0x00c0) /* /8 */\r
+#define TASSEL (0x0300) /* TimerA clock source select */\r
+#define TASSEL0 (0x0100) /* TimerA clock source select */\r
+#define TASSEL1 (0x0200) /* TimerA clock source select */\r
+#define TASSEL_0 (0x0000) /* TAxCLK */\r
+#define TASSEL_1 (0x0100) /* ACLK */\r
+#define TASSEL_2 (0x0200) /* SMCLK */\r
+#define TASSEL_3 (0x0300) /* INCLK */\r
+#define TASSEL__TACLK (0x0000) /* TAxCLK */\r
+#define TASSEL__ACLK (0x0100) /* ACLK */\r
+#define TASSEL__SMCLK (0x0200) /* SMCLK */\r
+#define TASSEL__INCLK (0x0300) /* INCLK */\r
+\r
+/* TA0CCTL Control Bits */\r
+#define CCIFG (0x0001) /* Capture/compare interrupt flag */\r
+#define CCIFG_0 (0x0000) /* No interrupt pending */\r
+#define CCIFG_1 (0x0001) /* Interrupt pending */\r
+#define COV (0x0002) /* Capture overflow */\r
+#define COV_0 (0x0000) /* No capture overflow occurred */\r
+#define COV_1 (0x0002) /* Capture overflow occurred */\r
+#define OUT (0x0004) /* Output */\r
+#define OUT_0 (0x0000) /* Output low */\r
+#define OUT_1 (0x0004) /* Output high */\r
+#define OUT__LOW (0x0000) /* Output low */\r
+#define OUT__HIGH (0x0004) /* Output high */\r
+#define CCI (0x0008) /* Capture/compare input */\r
+#define CCIE (0x0010) /* Capture/compare interrupt enable */\r
+#define CCIE_0 (0x0000) /* Interrupt disabled */\r
+#define CCIE_1 (0x0010) /* Interrupt enabled */\r
+#define OUTMOD (0x00e0) /* Output mode */\r
+#define OUTMOD0 (0x0020) /* Output mode */\r
+#define OUTMOD1 (0x0040) /* Output mode */\r
+#define OUTMOD2 (0x0080) /* Output mode */\r
+#define OUTMOD_0 (0x0000) /* OUT bit value */\r
+#define OUTMOD_1 (0x0020) /* Set */\r
+#define OUTMOD_2 (0x0040) /* Toggle/reset */\r
+#define OUTMOD_3 (0x0060) /* Set/reset */\r
+#define OUTMOD_4 (0x0080) /* Toggle */\r
+#define OUTMOD_5 (0x00a0) /* Reset */\r
+#define OUTMOD_6 (0x00c0) /* Toggle/set */\r
+#define OUTMOD_7 (0x00e0) /* Reset/set */\r
+#define CAP (0x0100) /* Capture mode */\r
+#define CAP_0 (0x0000) /* Compare mode */\r
+#define CAP_1 (0x0100) /* Capture mode */\r
+#define CAP__COMPARE (0x0000) /* Compare mode */\r
+#define CAP__CAPTURE (0x0100) /* Capture mode */\r
+#define SCCI (0x0400) /* Synchronized capture/compare input */\r
+#define SCS (0x0800) /* Synchronize capture source */\r
+#define SCS_0 (0x0000) /* Asynchronous capture */\r
+#define SCS_1 (0x0800) /* Synchronous capture */\r
+#define SCS__ASYNC (0x0000) /* Asynchronous capture */\r
+#define SCS__SYNC (0x0800) /* Synchronous capture */\r
+#define CCIS (0x3000) /* Capture/compare input select */\r
+#define CCIS0 (0x1000) /* Capture/compare input select */\r
+#define CCIS1 (0x2000) /* Capture/compare input select */\r
+#define CCIS_0 (0x0000) /* CCIxA */\r
+#define CCIS_1 (0x1000) /* CCIxB */\r
+#define CCIS_2 (0x2000) /* GND */\r
+#define CCIS_3 (0x3000) /* VCC */\r
+#define CCIS__CCIA (0x0000) /* CCIxA */\r
+#define CCIS__CCIB (0x1000) /* CCIxB */\r
+#define CCIS__GND (0x2000) /* GND */\r
+#define CCIS__VCC (0x3000) /* VCC */\r
+#define CM (0xc000) /* Capture mode */\r
+#define CM0 (0x4000) /* Capture mode */\r
+#define CM1 (0x8000) /* Capture mode */\r
+#define CM_0 (0x0000) /* No capture */\r
+#define CM_1 (0x4000) /* Capture on rising edge */\r
+#define CM_2 (0x8000) /* Capture on falling edge */\r
+#define CM_3 (0xc000) /* Capture on both rising and falling edges */\r
+#define CM__NONE (0x0000) /* No capture */\r
+#define CM__RISING (0x4000) /* Capture on rising edge */\r
+#define CM__FALLING (0x8000) /* Capture on falling edge */\r
+#define CM__BOTH (0xc000) /* Capture on both rising and falling edges */\r
+\r
+/* TA0EX0 Control Bits */\r
+#define TAIDEX (0x0007) /* Input divider expansion */\r
+#define TAIDEX0 (0x0001) /* Input divider expansion */\r
+#define TAIDEX1 (0x0002) /* Input divider expansion */\r
+#define TAIDEX2 (0x0004) /* Input divider expansion */\r
+#define TAIDEX_0 (0x0000) /* Divide by 1 */\r
+#define TAIDEX_1 (0x0001) /* Divide by 2 */\r
+#define TAIDEX_2 (0x0002) /* Divide by 3 */\r
+#define TAIDEX_3 (0x0003) /* Divide by 4 */\r
+#define TAIDEX_4 (0x0004) /* Divide by 5 */\r
+#define TAIDEX_5 (0x0005) /* Divide by 6 */\r
+#define TAIDEX_6 (0x0006) /* Divide by 7 */\r
+#define TAIDEX_7 (0x0007) /* Divide by 8 */\r
+#define TAIDEX__1 (0x0000) /* Divide by 1 */\r
+#define TAIDEX__2 (0x0001) /* Divide by 2 */\r
+#define TAIDEX__3 (0x0002) /* Divide by 3 */\r
+#define TAIDEX__4 (0x0003) /* Divide by 4 */\r
+#define TAIDEX__5 (0x0004) /* Divide by 5 */\r
+#define TAIDEX__6 (0x0005) /* Divide by 6 */\r
+#define TAIDEX__7 (0x0006) /* Divide by 7 */\r
+#define TAIDEX__8 (0x0007) /* Divide by 8 */\r
+\r
+/* TA0IV Control Bits */\r
+#define TAIV (0xffff) /* TimerA interrupt vector value */\r
+#define TAIV0 (0x0001) /* TimerA interrupt vector value */\r
+#define TAIV1 (0x0002) /* TimerA interrupt vector value */\r
+#define TAIV2 (0x0004) /* TimerA interrupt vector value */\r
+#define TAIV3 (0x0008) /* TimerA interrupt vector value */\r
+#define TAIV4 (0x0010) /* TimerA interrupt vector value */\r
+#define TAIV5 (0x0020) /* TimerA interrupt vector value */\r
+#define TAIV6 (0x0040) /* TimerA interrupt vector value */\r
+#define TAIV7 (0x0080) /* TimerA interrupt vector value */\r
+#define TAIV8 (0x0100) /* TimerA interrupt vector value */\r
+#define TAIV9 (0x0200) /* TimerA interrupt vector value */\r
+#define TAIV10 (0x0400) /* TimerA interrupt vector value */\r
+#define TAIV11 (0x0800) /* TimerA interrupt vector value */\r
+#define TAIV12 (0x1000) /* TimerA interrupt vector value */\r
+#define TAIV13 (0x2000) /* TimerA interrupt vector value */\r
+#define TAIV14 (0x4000) /* TimerA interrupt vector value */\r
+#define TAIV15 (0x8000) /* TimerA interrupt vector value */\r
+#define TAIV_0 (0x0000) /* No interrupt pending */\r
+#define TAIV_2 (0x0002) /* Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 \r
+ CCIFG; Interrupt Priority: Highest */\r
+#define TAIV_4 (0x0004) /* Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 \r
+ CCIFG */\r
+#define TAIV_6 (0x0006) /* Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 \r
+ CCIFG */\r
+#define TAIV_8 (0x0008) /* Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 \r
+ CCIFG */\r
+#define TAIV_10 (0x000a) /* Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 \r
+ CCIFG */\r
+#define TAIV_12 (0x000c) /* Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 \r
+ CCIFG */\r
+#define TAIV_14 (0x000e) /* Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL \r
+ TAIFG; Interrupt Priority: Lowest */\r
+#define TAIV__NONE (0x0000) /* No interrupt pending */\r
+#define TAIV__TACCR1 (0x0002) /* Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 \r
+ CCIFG; Interrupt Priority: Highest */\r
+#define TAIV__TACCR2 (0x0004) /* Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 \r
+ CCIFG */\r
+#define TAIV__TACCR3 (0x0006) /* Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 \r
+ CCIFG */\r
+#define TAIV__TACCR4 (0x0008) /* Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 \r
+ CCIFG */\r
+#define TAIV__TACCR5 (0x000a) /* Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 \r
+ CCIFG */\r
+#define TAIV__TACCR6 (0x000c) /* Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 \r
+ CCIFG */\r
+#define TAIV__TAIFG (0x000e) /* Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL \r
+ TAIFG; Interrupt Priority: Lowest */\r
+\r
+\r
+/*****************************************************************************\r
+ TA1 Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_TA1__ 3 /* Definition to show that module is available */\r
+#ifndef __MSP430_HAS_TAx__\r
+#define __MSP430_HAS_TAx__\r
+#endif\r
+#define __MSP430_BASEADDRESS_TA1__ 0x03C0\r
+#define TA1_BASE __MSP430_BASEADDRESS_TA1__\r
+\r
+sfr_w(TA1CTL); /* TimerAx Control Register */\r
+sfr_b(TA1CTL_L);\r
+sfr_b(TA1CTL_H);\r
+sfr_w(TA1CCTL0); /* Timer_A Capture/Compare Control Register */\r
+sfr_b(TA1CCTL0_L);\r
+sfr_b(TA1CCTL0_H);\r
+sfr_w(TA1CCTL1); /* Timer_A Capture/Compare Control Register */\r
+sfr_b(TA1CCTL1_L);\r
+sfr_b(TA1CCTL1_H);\r
+sfr_w(TA1CCTL2); /* Timer_A Capture/Compare Control Register */\r
+sfr_b(TA1CCTL2_L);\r
+sfr_b(TA1CCTL2_H);\r
+sfr_w(TA1R); /* TimerA register */\r
+sfr_b(TA1R_L);\r
+sfr_b(TA1R_H);\r
+sfr_w(TA1CCR0); /* Timer_A Capture/Compare Register */\r
+sfr_b(TA1CCR0_L);\r
+sfr_b(TA1CCR0_H);\r
+sfr_w(TA1CCR1); /* Timer_A Capture/Compare Register */\r
+sfr_b(TA1CCR1_L);\r
+sfr_b(TA1CCR1_H);\r
+sfr_w(TA1CCR2); /* Timer_A Capture/Compare Register */\r
+sfr_b(TA1CCR2_L);\r
+sfr_b(TA1CCR2_H);\r
+sfr_w(TA1EX0); /* TimerAx Expansion 0 Register */\r
+sfr_b(TA1EX0_L);\r
+sfr_b(TA1EX0_H);\r
+sfr_w(TA1IV); /* TimerAx Interrupt Vector Register */\r
+sfr_b(TA1IV_L);\r
+sfr_b(TA1IV_H);\r
+\r
+/* TA1 Register Offsets */\r
+#define OFS_TA1CTL (0x0000)\r
+#define OFS_TA1CCTL0 (0x0002)\r
+#define OFS_TA1CCTL1 (0x0004)\r
+#define OFS_TA1CCTL2 (0x0006)\r
+#define OFS_TA1R (0x0010)\r
+#define OFS_TA1CCR0 (0x0012)\r
+#define OFS_TA1CCR1 (0x0014)\r
+#define OFS_TA1CCR2 (0x0016)\r
+#define OFS_TA1EX0 (0x0020)\r
+#define OFS_TA1IV (0x002E)\r
+\r
+/* No control bits available or already defined for another module */\r
+\r
+/*****************************************************************************\r
+ TA2 Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_TA2__ 3 /* Definition to show that module is available */\r
+#ifndef __MSP430_HAS_TAx__\r
+#define __MSP430_HAS_TAx__\r
+#endif\r
+#define __MSP430_BASEADDRESS_TA2__ 0x0400\r
+#define TA2_BASE __MSP430_BASEADDRESS_TA2__\r
+\r
+sfr_w(TA2CTL); /* TimerAx Control Register */\r
+sfr_b(TA2CTL_L);\r
+sfr_b(TA2CTL_H);\r
+sfr_w(TA2CCTL0); /* Timer_A Capture/Compare Control Register */\r
+sfr_b(TA2CCTL0_L);\r
+sfr_b(TA2CCTL0_H);\r
+sfr_w(TA2CCTL1); /* Timer_A Capture/Compare Control Register */\r
+sfr_b(TA2CCTL1_L);\r
+sfr_b(TA2CCTL1_H);\r
+sfr_w(TA2CCTL2); /* Timer_A Capture/Compare Control Register */\r
+sfr_b(TA2CCTL2_L);\r
+sfr_b(TA2CCTL2_H);\r
+sfr_w(TA2R); /* TimerA register */\r
+sfr_b(TA2R_L);\r
+sfr_b(TA2R_H);\r
+sfr_w(TA2CCR0); /* Timer_A Capture/Compare Register */\r
+sfr_b(TA2CCR0_L);\r
+sfr_b(TA2CCR0_H);\r
+sfr_w(TA2CCR1); /* Timer_A Capture/Compare Register */\r
+sfr_b(TA2CCR1_L);\r
+sfr_b(TA2CCR1_H);\r
+sfr_w(TA2CCR2); /* Timer_A Capture/Compare Register */\r
+sfr_b(TA2CCR2_L);\r
+sfr_b(TA2CCR2_H);\r
+sfr_w(TA2EX0); /* TimerAx Expansion 0 Register */\r
+sfr_b(TA2EX0_L);\r
+sfr_b(TA2EX0_H);\r
+sfr_w(TA2IV); /* TimerAx Interrupt Vector Register */\r
+sfr_b(TA2IV_L);\r
+sfr_b(TA2IV_H);\r
+\r
+/* TA2 Register Offsets */\r
+#define OFS_TA2CTL (0x0000)\r
+#define OFS_TA2CCTL0 (0x0002)\r
+#define OFS_TA2CCTL1 (0x0004)\r
+#define OFS_TA2CCTL2 (0x0006)\r
+#define OFS_TA2R (0x0010)\r
+#define OFS_TA2CCR0 (0x0012)\r
+#define OFS_TA2CCR1 (0x0014)\r
+#define OFS_TA2CCR2 (0x0016)\r
+#define OFS_TA2EX0 (0x0020)\r
+#define OFS_TA2IV (0x002E)\r
+\r
+/* No control bits available or already defined for another module */\r
+\r
+/*****************************************************************************\r
+ TA3 Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_TA3__ 3 /* Definition to show that module is available */\r
+#ifndef __MSP430_HAS_TAx__\r
+#define __MSP430_HAS_TAx__\r
+#endif\r
+#define __MSP430_BASEADDRESS_TA3__ 0x0440\r
+#define TA3_BASE __MSP430_BASEADDRESS_TA3__\r
+\r
+sfr_w(TA3CTL); /* TimerAx Control Register */\r
+sfr_b(TA3CTL_L);\r
+sfr_b(TA3CTL_H);\r
+sfr_w(TA3CCTL0); /* Timer_A Capture/Compare Control Register */\r
+sfr_b(TA3CCTL0_L);\r
+sfr_b(TA3CCTL0_H);\r
+sfr_w(TA3CCTL1); /* Timer_A Capture/Compare Control Register */\r
+sfr_b(TA3CCTL1_L);\r
+sfr_b(TA3CCTL1_H);\r
+sfr_w(TA3CCTL2); /* Timer_A Capture/Compare Control Register */\r
+sfr_b(TA3CCTL2_L);\r
+sfr_b(TA3CCTL2_H);\r
+sfr_w(TA3R); /* TimerA register */\r
+sfr_b(TA3R_L);\r
+sfr_b(TA3R_H);\r
+sfr_w(TA3CCR0); /* Timer_A Capture/Compare Register */\r
+sfr_b(TA3CCR0_L);\r
+sfr_b(TA3CCR0_H);\r
+sfr_w(TA3CCR1); /* Timer_A Capture/Compare Register */\r
+sfr_b(TA3CCR1_L);\r
+sfr_b(TA3CCR1_H);\r
+sfr_w(TA3CCR2); /* Timer_A Capture/Compare Register */\r
+sfr_b(TA3CCR2_L);\r
+sfr_b(TA3CCR2_H);\r
+sfr_w(TA3EX0); /* TimerAx Expansion 0 Register */\r
+sfr_b(TA3EX0_L);\r
+sfr_b(TA3EX0_H);\r
+sfr_w(TA3IV); /* TimerAx Interrupt Vector Register */\r
+sfr_b(TA3IV_L);\r
+sfr_b(TA3IV_H);\r
+\r
+/* TA3 Register Offsets */\r
+#define OFS_TA3CTL (0x0000)\r
+#define OFS_TA3CCTL0 (0x0002)\r
+#define OFS_TA3CCTL1 (0x0004)\r
+#define OFS_TA3CCTL2 (0x0006)\r
+#define OFS_TA3R (0x0010)\r
+#define OFS_TA3CCR0 (0x0012)\r
+#define OFS_TA3CCR1 (0x0014)\r
+#define OFS_TA3CCR2 (0x0016)\r
+#define OFS_TA3EX0 (0x0020)\r
+#define OFS_TA3IV (0x002E)\r
+\r
+/* No control bits available or already defined for another module */\r
+\r
+/*****************************************************************************\r
+ TB0 Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_TB0__ 7 /* Definition to show that module is available */\r
+#ifndef __MSP430_HAS_TBx__\r
+#define __MSP430_HAS_TBx__\r
+#endif\r
+#define __MSP430_BASEADDRESS_TB0__ 0x0480\r
+#define TB0_BASE __MSP430_BASEADDRESS_TB0__\r
+\r
+sfr_w(TB0CTL); /* Timer_B Control Register */\r
+sfr_b(TB0CTL_L);\r
+sfr_b(TB0CTL_H);\r
+sfr_w(TB0CCTL0); /* Timer_B Capture/Compare Control Register */\r
+sfr_b(TB0CCTL0_L);\r
+sfr_b(TB0CCTL0_H);\r
+sfr_w(TB0CCTL1); /* Timer_B Capture/Compare Control Register */\r
+sfr_b(TB0CCTL1_L);\r
+sfr_b(TB0CCTL1_H);\r
+sfr_w(TB0CCTL2); /* Timer_B Capture/Compare Control Register */\r
+sfr_b(TB0CCTL2_L);\r
+sfr_b(TB0CCTL2_H);\r
+sfr_w(TB0CCTL3); /* Timer_B Capture/Compare Control Register */\r
+sfr_b(TB0CCTL3_L);\r
+sfr_b(TB0CCTL3_H);\r
+sfr_w(TB0CCTL4); /* Timer_B Capture/Compare Control Register */\r
+sfr_b(TB0CCTL4_L);\r
+sfr_b(TB0CCTL4_H);\r
+sfr_w(TB0CCTL5); /* Timer_B Capture/Compare Control Register */\r
+sfr_b(TB0CCTL5_L);\r
+sfr_b(TB0CCTL5_H);\r
+sfr_w(TB0CCTL6); /* Timer_B Capture/Compare Control Register */\r
+sfr_b(TB0CCTL6_L);\r
+sfr_b(TB0CCTL6_H);\r
+sfr_w(TB0R); /* Timer_B count register */\r
+sfr_b(TB0R_L);\r
+sfr_b(TB0R_H);\r
+sfr_w(TB0CCR0); /* Timer_B Capture/Compare Register */\r
+sfr_b(TB0CCR0_L);\r
+sfr_b(TB0CCR0_H);\r
+sfr_w(TB0CCR1); /* Timer_B Capture/Compare Register */\r
+sfr_b(TB0CCR1_L);\r
+sfr_b(TB0CCR1_H);\r
+sfr_w(TB0CCR2); /* Timer_B Capture/Compare Register */\r
+sfr_b(TB0CCR2_L);\r
+sfr_b(TB0CCR2_H);\r
+sfr_w(TB0CCR3); /* Timer_B Capture/Compare Register */\r
+sfr_b(TB0CCR3_L);\r
+sfr_b(TB0CCR3_H);\r
+sfr_w(TB0CCR4); /* Timer_B Capture/Compare Register */\r
+sfr_b(TB0CCR4_L);\r
+sfr_b(TB0CCR4_H);\r
+sfr_w(TB0CCR5); /* Timer_B Capture/Compare Register */\r
+sfr_b(TB0CCR5_L);\r
+sfr_b(TB0CCR5_H);\r
+sfr_w(TB0CCR6); /* Timer_B Capture/Compare Register */\r
+sfr_b(TB0CCR6_L);\r
+sfr_b(TB0CCR6_H);\r
+sfr_w(TB0EX0); /* Timer_Bx Expansion Register 0 */\r
+sfr_b(TB0EX0_L);\r
+sfr_b(TB0EX0_H);\r
+sfr_w(TB0IV); /* Timer_Bx Interrupt Vector Register */\r
+sfr_b(TB0IV_L);\r
+sfr_b(TB0IV_H);\r
+\r
+/* TB0 Register Offsets */\r
+#define OFS_TB0CTL (0x0000)\r
+#define OFS_TB0CCTL0 (0x0002)\r
+#define OFS_TB0CCTL1 (0x0004)\r
+#define OFS_TB0CCTL2 (0x0006)\r
+#define OFS_TB0CCTL3 (0x0008)\r
+#define OFS_TB0CCTL4 (0x000A)\r
+#define OFS_TB0CCTL5 (0x000C)\r
+#define OFS_TB0CCTL6 (0x000E)\r
+#define OFS_TB0R (0x0010)\r
+#define OFS_TB0CCR0 (0x0012)\r
+#define OFS_TB0CCR1 (0x0014)\r
+#define OFS_TB0CCR2 (0x0016)\r
+#define OFS_TB0CCR3 (0x0018)\r
+#define OFS_TB0CCR4 (0x001A)\r
+#define OFS_TB0CCR5 (0x001C)\r
+#define OFS_TB0CCR6 (0x001E)\r
+#define OFS_TB0EX0 (0x0020)\r
+#define OFS_TB0IV (0x002E)\r
+\r
+/* TB0 Control Bits */\r
+\r
+/* TB0CTL Control Bits */\r
+#define TBIFG (0x0001) /* TimerB interrupt flag */\r
+#define TBIFG_0 (0x0000) /* No interrupt pending */\r
+#define TBIFG_1 (0x0001) /* Interrupt pending */\r
+#define TBIE (0x0002) /* TimerB interrupt enable */\r
+#define TBIE_0 (0x0000) /* Interrupt disabled */\r
+#define TBIE_1 (0x0002) /* Interrupt enabled */\r
+#define TBCLR (0x0004) /* TimerB clear */\r
+#define TBSSEL (0x0300) /* TimerB clock source select */\r
+#define TBSSEL0 (0x0100) /* TimerB clock source select */\r
+#define TBSSEL1 (0x0200) /* TimerB clock source select */\r
+#define TBSSEL_0 (0x0000) /* TBxCLK */\r
+#define TBSSEL_1 (0x0100) /* ACLK */\r
+#define TBSSEL_2 (0x0200) /* SMCLK */\r
+#define TBSSEL_3 (0x0300) /* INCLK */\r
+#define TBSSEL__TBCLK (0x0000) /* TBxCLK */\r
+#define TBSSEL__ACLK (0x0100) /* ACLK */\r
+#define TBSSEL__SMCLK (0x0200) /* SMCLK */\r
+#define TBSSEL__INCLK (0x0300) /* INCLK */\r
+#define CNTL (0x1800) /* Counter length */\r
+#define CNTL0 (0x0800) /* Counter length */\r
+#define CNTL1 (0x1000) /* Counter length */\r
+#define CNTL_0 (0x0000) /* 16-bit, TBxR(max) = 0FFFFh */\r
+#define CNTL_1 (0x0800) /* 12-bit, TBxR(max) = 0FFFh */\r
+#define CNTL_2 (0x1000) /* 10-bit, TBxR(max) = 03FFh */\r
+#define CNTL_3 (0x1800) /* 8-bit, TBxR(max) = 0FFh */\r
+#define CNTL__16 (0x0000) /* 16-bit, TBxR(max) = 0FFFFh */\r
+#define CNTL__12 (0x0800) /* 12-bit, TBxR(max) = 0FFFh */\r
+#define CNTL__10 (0x1000) /* 10-bit, TBxR(max) = 03FFh */\r
+#define CNTL__8 (0x1800) /* 8-bit, TBxR(max) = 0FFh */\r
+#define TBCLGRP (0x6000) /* TBxCLn group */\r
+#define TBCLGRP0 (0x2000) /* TBxCLn group */\r
+#define TBCLGRP1 (0x4000) /* TBxCLn group */\r
+#define TBCLGRP_0 (0x0000) /* Each TBxCLn latch loads independently */\r
+#define TBCLGRP_1 (0x2000) /* TBxCL1+TBxCL2 (TBxCCR1 CLLD bits control the update); \r
+ TBxCL3+TBxCL4 (TBxCCR3 CLLD bits control the update); \r
+ TBxCL5+TBxCL6 (TBxCCR5 CLLD bits control the update); TBxCL0 \r
+ independent */\r
+#define TBCLGRP_2 (0x4000) /* TBxCL1+TBxCL2+TBxCL3 (TBxCCR1 CLLD bits control the update); \r
+ TBxCL4+TBxCL5+TBxCL6 (TBxCCR4 CLLD bits control the update); \r
+ TBxCL0 independent */\r
+#define TBCLGRP_3 (0x6000) /* TBxCL0+TBxCL1+TBxCL2+TBxCL3+TBxCL4+TBxCL5+TBxCL6 (TBxCCR1 CLLD\r
+ bits control the update) */\r
+\r
+/* TB0CCTL Control Bits */\r
+#define CLLD (0x0600) /* Compare latch load */\r
+#define CLLD0 (0x0200) /* Compare latch load */\r
+#define CLLD1 (0x0400) /* Compare latch load */\r
+#define CLLD_0 (0x0000) /* TBxCLn loads on write to TBxCCRn */\r
+#define CLLD_1 (0x0200) /* TBxCLn loads when TBxR counts to 0 */\r
+#define CLLD_2 (0x0400) /* TBxCLn loads when TBxR counts to 0 (up or continuous mode). \r
+ TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down \r
+ mode). */\r
+#define CLLD_3 (0x0600) /* TBxCLn loads when TBxR counts to TBxCLn */\r
+\r
+/* TB0EX0 Control Bits */\r
+#define TBIDEX (0x0007) /* Input divider expansion */\r
+#define TBIDEX0 (0x0001) /* Input divider expansion */\r
+#define TBIDEX1 (0x0002) /* Input divider expansion */\r
+#define TBIDEX2 (0x0004) /* Input divider expansion */\r
+#define TBIDEX_0 (0x0000) /* Divide by 1 */\r
+#define TBIDEX_1 (0x0001) /* Divide by 2 */\r
+#define TBIDEX_2 (0x0002) /* Divide by 3 */\r
+#define TBIDEX_3 (0x0003) /* Divide by 4 */\r
+#define TBIDEX_4 (0x0004) /* Divide by 5 */\r
+#define TBIDEX_5 (0x0005) /* Divide by 6 */\r
+#define TBIDEX_6 (0x0006) /* Divide by 7 */\r
+#define TBIDEX_7 (0x0007) /* Divide by 8 */\r
+#define TBIDEX__1 (0x0000) /* Divide by 1 */\r
+#define TBIDEX__2 (0x0001) /* Divide by 2 */\r
+#define TBIDEX__3 (0x0002) /* Divide by 3 */\r
+#define TBIDEX__4 (0x0003) /* Divide by 4 */\r
+#define TBIDEX__5 (0x0004) /* Divide by 5 */\r
+#define TBIDEX__6 (0x0005) /* Divide by 6 */\r
+#define TBIDEX__7 (0x0006) /* Divide by 7 */\r
+#define TBIDEX__8 (0x0007) /* Divide by 8 */\r
+\r
+/* TB0IV Control Bits */\r
+#define TBIV (0xffff) /* Timer_B interrupt vector value */\r
+#define TBIV0 (0x0001) /* Timer_B interrupt vector value */\r
+#define TBIV1 (0x0002) /* Timer_B interrupt vector value */\r
+#define TBIV2 (0x0004) /* Timer_B interrupt vector value */\r
+#define TBIV3 (0x0008) /* Timer_B interrupt vector value */\r
+#define TBIV4 (0x0010) /* Timer_B interrupt vector value */\r
+#define TBIV5 (0x0020) /* Timer_B interrupt vector value */\r
+#define TBIV6 (0x0040) /* Timer_B interrupt vector value */\r
+#define TBIV7 (0x0080) /* Timer_B interrupt vector value */\r
+#define TBIV8 (0x0100) /* Timer_B interrupt vector value */\r
+#define TBIV9 (0x0200) /* Timer_B interrupt vector value */\r
+#define TBIV10 (0x0400) /* Timer_B interrupt vector value */\r
+#define TBIV11 (0x0800) /* Timer_B interrupt vector value */\r
+#define TBIV12 (0x1000) /* Timer_B interrupt vector value */\r
+#define TBIV13 (0x2000) /* Timer_B interrupt vector value */\r
+#define TBIV14 (0x4000) /* Timer_B interrupt vector value */\r
+#define TBIV15 (0x8000) /* Timer_B interrupt vector value */\r
+#define TBIV_0 (0x0000) /* No interrupt pending */\r
+#define TBIV_2 (0x0002) /* Interrupt Source: Capture/compare 1; Interrupt Flag: TBxCCR1 \r
+ CCIFG; Interrupt Priority: Highest */\r
+#define TBIV_4 (0x0004) /* Interrupt Source: Capture/compare 2; Interrupt Flag: TBxCCR2 \r
+ CCIFG */\r
+#define TBIV_6 (0x0006) /* Interrupt Source: Capture/compare 3; Interrupt Flag: TBxCCR3 \r
+ CCIFG */\r
+#define TBIV_8 (0x0008) /* Interrupt Source: Capture/compare 4; Interrupt Flag: TBxCCR4 \r
+ CCIFG */\r
+#define TBIV_10 (0x000a) /* Interrupt Source: Capture/compare 5; Interrupt Flag: TBxCCR5 \r
+ CCIFG */\r
+#define TBIV_12 (0x000c) /* Interrupt Source: Capture/compare 6; Interrupt Flag: TBxCCR6 \r
+ CCIFG */\r
+#define TBIV_14 (0x000e) /* Interrupt Source: Timer overflow; Interrupt Flag: TBxCTL \r
+ TBIFG; Interrupt Priority: Lowest */\r
+#define TBIV__NONE (0x0000) /* No interrupt pending */\r
+#define TBIV__TBCCR1 (0x0002) /* Interrupt Source: Capture/compare 1; Interrupt Flag: TBxCCR1 \r
+ CCIFG; Interrupt Priority: Highest */\r
+#define TBIV__TBCCR2 (0x0004) /* Interrupt Source: Capture/compare 2; Interrupt Flag: TBxCCR2 \r
+ CCIFG */\r
+#define TBIV__TBCCR3 (0x0006) /* Interrupt Source: Capture/compare 3; Interrupt Flag: TBxCCR3 \r
+ CCIFG */\r
+#define TBIV__TBCCR4 (0x0008) /* Interrupt Source: Capture/compare 4; Interrupt Flag: TBxCCR4 \r
+ CCIFG */\r
+#define TBIV__TBCCR5 (0x000a) /* Interrupt Source: Capture/compare 5; Interrupt Flag: TBxCCR5 \r
+ CCIFG */\r
+#define TBIV__TBCCR6 (0x000c) /* Interrupt Source: Capture/compare 6; Interrupt Flag: TBxCCR6 \r
+ CCIFG */\r
+#define TBIV__TBIFG (0x000e) /* Interrupt Source: Timer overflow; Interrupt Flag: TBxCTL \r
+ TBIFG; Interrupt Priority: Lowest */\r
+\r
+\r
+/*****************************************************************************\r
+ WDT_A Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_WDT_A__ /* Definition to show that module is available */\r
+#define __MSP430_BASEADDRESS_WDT_A__ 0x01CC\r
+#define WDT_A_BASE __MSP430_BASEADDRESS_WDT_A__\r
+\r
+sfr_w(WDTCTL); /* Watchdog Timer Control Register */\r
+sfr_b(WDTCTL_L);\r
+sfr_b(WDTCTL_H);\r
+\r
+/* WDT_A Register Offsets */\r
+#define OFS_WDTCTL (0x0000)\r
+\r
+/* WDT_A Control Bits */\r
+\r
+/* WDTCTL Control Bits */\r
+#define WDTIS (0x0007) /* Watchdog timer interval select */\r
+#define WDTIS0 (0x0001) /* Watchdog timer interval select */\r
+#define WDTIS1 (0x0002) /* Watchdog timer interval select */\r
+#define WDTIS2 (0x0004) /* Watchdog timer interval select */\r
+#define WDTIS_0 (0x0000) /* Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */\r
+#define WDTIS_1 (0x0001) /* Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */\r
+#define WDTIS_2 (0x0002) /* Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */\r
+#define WDTIS_3 (0x0003) /* Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */\r
+#define WDTIS_4 (0x0004) /* Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */\r
+#define WDTIS_5 (0x0005) /* Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */\r
+#define WDTIS_6 (0x0006) /* Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */\r
+#define WDTIS_7 (0x0007) /* Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */\r
+#define WDTIS__2G (0x0000) /* Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */\r
+#define WDTIS__128M (0x0001) /* Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */\r
+#define WDTIS__8192K (0x0002) /* Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */\r
+#define WDTIS__512K (0x0003) /* Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */\r
+#define WDTIS__32K (0x0004) /* Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */\r
+#define WDTIS__8192 (0x0005) /* Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */\r
+#define WDTIS__512 (0x0006) /* Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */\r
+#define WDTIS__64 (0x0007) /* Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */\r
+#define WDTCNTCL (0x0008) /* Watchdog timer counter clear */\r
+#define WDTCNTCL_0 (0x0000) /* No action */\r
+#define WDTCNTCL_1 (0x0008) /* WDTCNT = 0000h */\r
+#define WDTTMSEL (0x0010) /* Watchdog timer mode select */\r
+#define WDTTMSEL_0 (0x0000) /* Watchdog mode */\r
+#define WDTTMSEL_1 (0x0010) /* Interval timer mode */\r
+#define WDTSSEL (0x0060) /* Watchdog timer clock source select */\r
+#define WDTSSEL0 (0x0020) /* Watchdog timer clock source select */\r
+#define WDTSSEL1 (0x0040) /* Watchdog timer clock source select */\r
+#define WDTSSEL_0 (0x0000) /* SMCLK */\r
+#define WDTSSEL_1 (0x0020) /* ACLK */\r
+#define WDTSSEL_2 (0x0040) /* VLOCLK */\r
+#define WDTSSEL_3 (0x0060) /* BCLK */\r
+#define WDTSSEL__SMCLK (0x0000) /* SMCLK */\r
+#define WDTSSEL__ACLK (0x0020) /* ACLK */\r
+#define WDTSSEL__VLOCLK (0x0040) /* VLOCLK */\r
+#define WDTSSEL__BCLK (0x0060) /* BCLK */\r
+#define WDTHOLD (0x0080) /* Watchdog timer hold */\r
+#define WDTHOLD_0 (0x0000) /* Watchdog timer is not stopped */\r
+#define WDTHOLD_1 (0x0080) /* Watchdog timer is stopped */\r
+#define WDTHOLD__UNHOLD (0x0000) /* Watchdog timer is not stopped */\r
+#define WDTHOLD__HOLD (0x0080) /* Watchdog timer is stopped */\r
+#define WDTPW (0x5a00) /* Watchdog timer password */\r
+#define WDTPW0 (0x0100) /* Watchdog timer password */\r
+#define WDTPW1 (0x0200) /* Watchdog timer password */\r
+#define WDTPW2 (0x0400) /* Watchdog timer password */\r
+#define WDTPW3 (0x0800) /* Watchdog timer password */\r
+#define WDTPW4 (0x1000) /* Watchdog timer password */\r
+#define WDTPW5 (0x2000) /* Watchdog timer password */\r
+#define WDTPW6 (0x4000) /* Watchdog timer password */\r
+#define WDTPW7 (0x8000) /* Watchdog timer password */\r
+\r
+\r
+/*****************************************************************************\r
+ eCOMP0 Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_ECOMP0__ /* Definition to show that module is available */\r
+#ifndef __MSP430_HAS_ECOMPx__\r
+#define __MSP430_HAS_ECOMPx__\r
+#endif\r
+#define __MSP430_BASEADDRESS_ECOMP0__ 0x08E0\r
+#define ECOMP0_BASE __MSP430_BASEADDRESS_ECOMP0__\r
+\r
+sfr_w(CP0CTL0); /* Comparator Control Register 0 */\r
+sfr_b(CP0CTL0_L);\r
+sfr_b(CP0CTL0_H);\r
+sfr_w(CP0CTL1); /* Comparator Control Register 1 */\r
+sfr_b(CP0CTL1_L);\r
+sfr_b(CP0CTL1_H);\r
+sfr_w(CP0INT); /* Comparator Interrupt Control Register */\r
+sfr_b(CP0INT_L);\r
+sfr_b(CP0INT_H);\r
+sfr_w(CP0IV); /* Comparator Interrupt Vector Word Register */\r
+sfr_b(CP0IV_L);\r
+sfr_b(CP0IV_H);\r
+sfr_w(CP0DACCTL); /* 6-bit Comparator built-in DAC Control Register */\r
+sfr_b(CP0DACCTL_L);\r
+sfr_b(CP0DACCTL_H);\r
+sfr_w(CP0DACDATA); /* 6-bit Comparator built-in DAC Data Register */\r
+sfr_b(CP0DACDATA_L);\r
+sfr_b(CP0DACDATA_H);\r
+\r
+/* eCOMP0 Register Offsets */\r
+#define OFS_CP0CTL0 (0x0000)\r
+#define OFS_CP0CTL1 (0x0002)\r
+#define OFS_CP0INT (0x0006)\r
+#define OFS_CP0IV (0x0008)\r
+#define OFS_CP0DACCTL (0x0010)\r
+#define OFS_CP0DACDATA (0x0012)\r
+\r
+/* eCOMP0 Control Bits */\r
+\r
+/* CP0CTL0 Control Bits */\r
+#define CPPEN (0x0010) /* Channel input enable for the V+ terminal */\r
+#define CPPEN_0 (0x0000) /* Selected analog input channel for V+ terminal is disabled. */\r
+#define CPPEN_1 (0x0010) /* Selected analog input channel for V+ terminal is enabled. */\r
+#define CPNSEL (0x0700) /* Channel input selected for the - terminal */\r
+#define CPNSEL0 (0x0100) /* Channel input selected for the - terminal */\r
+#define CPNSEL1 (0x0200) /* Channel input selected for the - terminal */\r
+#define CPNSEL2 (0x0400) /* Channel input selected for the - terminal */\r
+#define CPNSEL_0 (0x0000) /* select external input source */\r
+#define CPNSEL_1 (0x0100) /* select external input source */\r
+#define CPNSEL_2 (0x0200) /* select external input source */\r
+#define CPNSEL_3 (0x0300) /* select external input source */\r
+#define CPNSEL_4 (0x0400) /* device specific, please refer to device data sheet for details */\r
+#define CPNSEL_5 (0x0500) /* device specific, please refer to device data sheet for details */\r
+#define CPNSEL_6 (0x0600) /* 6-bit DAC */\r
+#define CPNSEL_7 (0x0700) /* Reserved */\r
+#define CPNEN (0x1000) /* Channel input enable for the - terminal */\r
+#define CPNEN_0 (0x0000) /* Selected analog input channel for V- terminal is disabled. */\r
+#define CPNEN_1 (0x1000) /* Selected analog input channel for V- terminal is enabled. */\r
+#define CPPSEL (0x0007) /* Channel input selected for the V+ terminal */\r
+#define CPPSEL0 (0x0001) /* Channel input selected for the V+ terminal */\r
+#define CPPSEL1 (0x0002) /* Channel input selected for the V+ terminal */\r
+#define CPPSEL2 (0x0004) /* Channel input selected for the V+ terminal */\r
+#define CPPSEL_0 (0x0000) /* select external input source */\r
+#define CPPSEL_1 (0x0001) /* select external input source */\r
+#define CPPSEL_2 (0x0002) /* select external input source */\r
+#define CPPSEL_3 (0x0003) /* select external input source */\r
+#define CPPSEL_4 (0x0004) /* device specific, please refer to device data sheet for details */\r
+#define CPPSEL_5 (0x0005) /* device specific, please refer to device data sheet for details */\r
+#define CPPSEL_6 (0x0006) /* 6-bit DAC */\r
+#define CPPSEL_7 (0x0007) /* Reserved */\r
+\r
+/* CP0CTL1 Control Bits */\r
+#define CPOUT (0x0001) /* Comparator output value */\r
+#define CPINV (0x0002) /* Comparator output polarity */\r
+#define CPINV_0 (0x0000) /* Comparator output is non-inverted */\r
+#define CPINV_1 (0x0002) /* Comparator output is inverted */\r
+#define CPIES (0x0010) /* Interrupt edge select for CEIIFG and CEIFG */\r
+#define CPIES_0 (0x0000) /* Rising edge for CPIFG, falling edge for CPIIFG */\r
+#define CPIES_1 (0x0010) /* Falling edge for CPIFG, rising edge for CPIIFG */\r
+#define CPFLT (0x0020) /* */\r
+#define CPFLT_0 (0x0000) /* Comparator output is not filtered */\r
+#define CPFLT_1 (0x0020) /* Comparator output is filtered */\r
+#define CPFLTDLY (0x00c0) /* */\r
+#define CPFLTDLY0 (0x0040) /* */\r
+#define CPFLTDLY1 (0x0080) /* */\r
+#define CPFLTDLY_0 (0x0000) /* Typical filter delay of 450ns */\r
+#define CPFLTDLY_1 (0x0040) /* Typical filter delay of 900ns */\r
+#define CPFLTDLY_2 (0x0080) /* Typical filter delay of 1800ns */\r
+#define CPFLTDLY_3 (0x00c0) /* Typical filter delay of 3600ns */\r
+#define CPMSEL (0x0100) /* */\r
+#define CPMSEL_0 (0x0000) /* High-power & High speed mode (500nA) */\r
+#define CPMSEL_1 (0x0100) /* Low-power & Low speed mode (10nA) */\r
+#define CPEN (0x0200) /* */\r
+#define CPEN_0 (0x0000) /* Comparator is disabled */\r
+#define CPEN_1 (0x0200) /* Comparator is enabled */\r
+#define CPHSEL (0x0c00) /* */\r
+#define CPHSEL0 (0x0400) /* */\r
+#define CPHSEL1 (0x0800) /* */\r
+#define CPHSEL_0 (0x0000) /* disable */\r
+#define CPHSEL_1 (0x0400) /* 10mV */\r
+#define CPHSEL_2 (0x0800) /* 20mV */\r
+#define CPHSEL_3 (0x0c00) /* 30mV */\r
+#define CPIE (0x4000) /* */\r
+#define CPIE_0 (0x0000) /* Interrupt output is disabled */\r
+#define CPIE_1 (0x4000) /* Interrupt output is enabled */\r
+#define CPIIE (0x8000) /* */\r
+#define CPIIE_0 (0x0000) /* Interrupt inverted output is disabled */\r
+#define CPIIE_1 (0x8000) /* Interrupt inverted output is enabled */\r
+\r
+/* CP0INT Control Bits */\r
+#define CPIFG (0x0001) /* Comparator output interrupt flag */\r
+#define CPIFG_0 (0x0000) /* No interrupt pending. */\r
+#define CPIFG_1 (0x0001) /* Output interrupt pending. */\r
+#define CPIIFG (0x0002) /* Comparator output inverted interrupt flag */\r
+#define CPIIFG_0 (0x0000) /* No interrupt pending. */\r
+#define CPIIFG_1 (0x0002) /* Output interrupt pending. */\r
+\r
+/* CP0IV Control Bits */\r
+#define CPIV (0xffff) /* Comparator interrupt vector word register */\r
+#define CPIV0 (0x0001) /* Comparator interrupt vector word register */\r
+#define CPIV1 (0x0002) /* Comparator interrupt vector word register */\r
+#define CPIV2 (0x0004) /* Comparator interrupt vector word register */\r
+#define CPIV3 (0x0008) /* Comparator interrupt vector word register */\r
+#define CPIV4 (0x0010) /* Comparator interrupt vector word register */\r
+#define CPIV5 (0x0020) /* Comparator interrupt vector word register */\r
+#define CPIV6 (0x0040) /* Comparator interrupt vector word register */\r
+#define CPIV7 (0x0080) /* Comparator interrupt vector word register */\r
+#define CPIV8 (0x0100) /* Comparator interrupt vector word register */\r
+#define CPIV9 (0x0200) /* Comparator interrupt vector word register */\r
+#define CPIV10 (0x0400) /* Comparator interrupt vector word register */\r
+#define CPIV11 (0x0800) /* Comparator interrupt vector word register */\r
+#define CPIV12 (0x1000) /* Comparator interrupt vector word register */\r
+#define CPIV13 (0x2000) /* Comparator interrupt vector word register */\r
+#define CPIV14 (0x4000) /* Comparator interrupt vector word register */\r
+#define CPIV15 (0x8000) /* Comparator interrupt vector word register */\r
+#define CPIV_0 (0x0000) /* No interrupt pending */\r
+#define CEIV_2 (0x0002) /* CPIFG */\r
+#define CPIV_4 (0x0004) /* CPIIFG */\r
+#define CPIV__NONE (0x0000) /* No interrupt pending */\r
+#define CPIV__CPIFG (0x0002) /* CPIFG */\r
+#define CPIV__CPIIFG (0x0004) /* CPIIFG */\r
+\r
+/* CP0DACCTL Control Bits */\r
+#define CPDACSW (0x0001) /* */\r
+#define CPDACSW_0 (0x0000) /* CPDACBUF1 selected */\r
+#define CPDACSW_1 (0x0001) /* CPDACBUF2 selected */\r
+#define CPDACBUFS (0x0002) /* */\r
+#define CPDACBUFS_0 (0x0000) /* Comparator output is selected as the buffer control source */\r
+#define CPDACBUFS_1 (0x0002) /* CPDACSW bit is selected as the buffer control source */\r
+#define CPDACREFS (0x0004) /* */\r
+#define CPDACREFS_0 (0x0000) /* VDD selected */\r
+#define CPDACREFS_1 (0x0004) /* on-chip VREF selected */\r
+#define CPDACEN (0x0080) /* */\r
+#define CPDACEN_0 (0x0000) /* DAC output is disabled. */\r
+#define CPDACEN_1 (0x0080) /* DAC output is enabled. */\r
+\r
+/* CP0DACDATA Control Bits */\r
+#define CPDACBUF1 (0x003f) /* */\r
+#define CPDACBUF10 (0x0001) /* */\r
+#define CPDACBUF11 (0x0002) /* */\r
+#define CPDACBUF12 (0x0004) /* */\r
+#define CPDACBUF13 (0x0008) /* */\r
+#define CPDACBUF14 (0x0010) /* */\r
+#define CPDACBUF15 (0x0020) /* */\r
+#define CPDACBUF1_0 (0x0000) /* 0v */\r
+#define CPDACBUF1_1 (0x0001) /* selected reference voltage * 1/64 */\r
+#define CPDACBUF1_2 (0x0002) /* selected reference voltage * 2/64 */\r
+#define CPDACBUF1_3 (0x0003) /* selected reference voltage * 3/64 */\r
+#define CPDACBUF1_4 (0x0004) /* selected reference voltage * 4/64 */\r
+#define CPDACBUF1_5 (0x0005) /* selected reference voltage * 5/64 */\r
+#define CPDACBUF1_6 (0x0006) /* selected reference voltage * 6/64 */\r
+#define CPDACBUF1_7 (0x0007) /* selected reference voltage * 7/64 */\r
+#define CPDACBUF1_8 (0x0008) /* selected reference voltage * 8/64 */\r
+#define CPDACBUF1_9 (0x0009) /* selected reference voltage *9/64 */\r
+#define CPDACBUF1_10 (0x000a) /* selected reference voltage * 10/64 */\r
+#define CPDACBUF1_11 (0x000b) /* selected reference voltage * 11/64 */\r
+#define CPDACBUF1_12 (0x000c) /* selected reference voltage * 12/64 */\r
+#define CPDACBUF1_13 (0x000d) /* selected reference voltage * 13/64 */\r
+#define CPDACBUF1_14 (0x000e) /* selected reference voltage * 14/64 */\r
+#define CPDACBUF1_15 (0x000f) /* selected reference voltage * 15/64 */\r
+#define CPDACBUF1_16 (0x0010) /* selected reference voltage * 16/64 */\r
+#define CPDACBUF1_17 (0x0011) /* selected reference voltage * 17/64 */\r
+#define CPDACBUF1_18 (0x0012) /* selected reference voltage * 18/64 */\r
+#define CPDACBUF1_19 (0x0013) /* selected reference voltage * 19/64 */\r
+#define CPDACBUF1_20 (0x0014) /* selected reference voltage * 20/64 */\r
+#define CPDACBUF1_21 (0x0015) /* selected reference voltage * 21/64 */\r
+#define CPDACBUF1_22 (0x0016) /* selected reference voltage * 22/64 */\r
+#define CPDACBUF1_23 (0x0017) /* selected reference voltage * 23/64 */\r
+#define CPDACBUF1_24 (0x0018) /* selected reference voltage * 24/64 */\r
+#define CPDACBUF1_25 (0x0019) /* selected reference voltage * 25/64 */\r
+#define CPDACBUF1_26 (0x001a) /* selected reference voltage * 26/64 */\r
+#define CPDACBUF1_27 (0x001b) /* selected reference voltage * 27/64 */\r
+#define CPDACBUF1_28 (0x001c) /* selected reference voltage * 28/64 */\r
+#define CPDACBUF1_29 (0x001d) /* selected reference voltage * 29/64 */\r
+#define CPDACBUF1_30 (0x001e) /* selected reference voltage * 30/64 */\r
+#define CPDACBUF1_31 (0x001f) /* selected reference voltage * 31/64 */\r
+#define CPDACBUF1_32 (0x0020) /* selected reference voltage * 32/64 */\r
+#define CPDACBUF1_33 (0x0021) /* selected reference voltage * 33/64 */\r
+#define CPDACBUF1_34 (0x0022) /* selected reference voltage * 34/64 */\r
+#define CPDACBUF1_35 (0x0023) /* selected reference voltage * 35/64 */\r
+#define CPDACBUF1_36 (0x0024) /* selected reference voltage * 36/64 */\r
+#define CPDACBUF1_37 (0x0025) /* selected reference voltage * 37/64 */\r
+#define CPDACBUF1_38 (0x0026) /* selected reference voltage * 38/64 */\r
+#define CPDACBUF1_39 (0x0027) /* selected reference voltage * 39/64 */\r
+#define CPDACBUF1_40 (0x0028) /* selected reference voltage * 40/64 */\r
+#define CPDACBUF1_41 (0x0029) /* selected reference voltage * 41/64 */\r
+#define CPDACBUF1_42 (0x002a) /* selected reference voltage * 42/64 */\r
+#define CPDACBUF1_43 (0x002b) /* selected reference voltage * 43/64 */\r
+#define CPDACBUF1_44 (0x002c) /* selected reference voltage * 44/64 */\r
+#define CPDACBUF1_45 (0x002d) /* selected reference voltage * 45/64 */\r
+#define CPDACBUF1_46 (0x002e) /* selected reference voltage * 46/64 */\r
+#define CPDACBUF1_47 (0x002f) /* selected reference voltage * 47/64 */\r
+#define CPDACBUF1_48 (0x0030) /* selected reference voltage * 48/64 */\r
+#define CPDACBUF1_49 (0x0031) /* selected reference voltage * 49/64 */\r
+#define CPDACBUF1_50 (0x0032) /* selected reference voltage * 50/64 */\r
+#define CPDACBUF1_51 (0x0033) /* selected reference voltage * 51/64 */\r
+#define CPDACBUF1_52 (0x0034) /* selected reference voltage * 52/64 */\r
+#define CPDACBUF1_53 (0x0035) /* selected reference voltage * 53/64 */\r
+#define CPDACBUF1_54 (0x0036) /* selected reference voltage * 54/64 */\r
+#define CPDACBUF1_55 (0x0037) /* selected reference voltage * 55/64 */\r
+#define CPDACBUF1_56 (0x0038) /* selected reference voltage * 56/64 */\r
+#define CPDACBUF1_57 (0x0039) /* selected reference voltage * 57/64 */\r
+#define CPDACBUF1_58 (0x003a) /* selected reference voltage * 58/64 */\r
+#define CPDACBUF1_59 (0x003b) /* selected reference voltage * 59/64 */\r
+#define CPDACBUF1_60 (0x003c) /* selected reference voltage * 60/64 */\r
+#define CPDACBUF1_61 (0x003d) /* selected reference voltage * 61/64 */\r
+#define CPDACBUF1_62 (0x003e) /* selected reference voltage * 62/64 */\r
+#define CPDACBUF1_63 (0x003f) /* selected reference voltage * 63/64 */\r
+#define CPDACBUF2 (0x3f00) /* */\r
+#define CPDACBUF20 (0x0100) /* */\r
+#define CPDACBUF21 (0x0200) /* */\r
+#define CPDACBUF22 (0x0400) /* */\r
+#define CPDACBUF23 (0x0800) /* */\r
+#define CPDACBUF24 (0x1000) /* */\r
+#define CPDACBUF25 (0x2000) /* */\r
+#define CPDACBUF2_0 (0x0000) /* 0v */\r
+#define CPDACBUF2_1 (0x0100) /* selected reference voltage * 1/64 */\r
+#define CPDACBUF2_2 (0x0200) /* selected reference voltage * 2/64 */\r
+#define CPDACBUF2_3 (0x0300) /* selected reference voltage * 3/64 */\r
+#define CPDACBUF2_4 (0x0400) /* selected reference voltage * 4/64 */\r
+#define CPDACBUF2_5 (0x0500) /* selected reference voltage * 5/64 */\r
+#define CPDACBUF2_6 (0x0600) /* selected reference voltage * 6/64 */\r
+#define CPDACBUF2_7 (0x0700) /* selected reference voltage * 7/64 */\r
+#define CPDACBUF2_8 (0x0800) /* selected reference voltage * 8/64 */\r
+#define CPDACBUF2_9 (0x0900) /* selected reference voltage * 9/64 */\r
+#define CPDACBUF2_10 (0x0a00) /* selected reference voltage * 10/64 */\r
+#define CPDACBUF2_11 (0x0b00) /* selected reference voltage * 11/64 */\r
+#define CPDACBUF2_12 (0x0c00) /* selected reference voltage * 12/64 */\r
+#define CPDACBUF2_13 (0x0d00) /* selected reference voltage * 13/64 */\r
+#define CPDACBUF2_14 (0x0e00) /* selected reference voltage * 14/64 */\r
+#define CPDACBUF2_15 (0x0f00) /* selected reference voltage * 15/64 */\r
+#define CPDACBUF2_16 (0x1000) /* selected reference voltage * 16/64 */\r
+#define CPDACBUF2_17 (0x1100) /* selected reference voltage * 17/64 */\r
+#define CPDACBUF2_18 (0x1200) /* selected reference voltage * 18/64 */\r
+#define CPDACBUF2_19 (0x1300) /* selected reference voltage * 19/64 */\r
+#define CPDACBUF2_20 (0x1400) /* selected reference voltage * 20/64 */\r
+#define CPDACBUF2_21 (0x1500) /* selected reference voltage * 21/64 */\r
+#define CPDACBUF2_22 (0x1600) /* selected reference voltage * 22/64 */\r
+#define CPDACBUF2_23 (0x1700) /* selected reference voltage * 23/64 */\r
+#define CPDACBUF2_24 (0x1800) /* selected reference voltage * 24/64 */\r
+#define CPDACBUF2_25 (0x1900) /* selected reference voltage * 25/64 */\r
+#define CPDACBUF2_26 (0x1a00) /* selected reference voltage * 26/64 */\r
+#define CPDACBUF2_27 (0x1b00) /* selected reference voltage * 27/64 */\r
+#define CPDACBUF2_28 (0x1c00) /* selected reference voltage * 28/64 */\r
+#define CPDACBUF2_29 (0x1d00) /* selected reference voltage * 29/64 */\r
+#define CPDACBUF2_30 (0x1e00) /* selected reference voltage * 30/64 */\r
+#define CPDACBUF2_31 (0x1f00) /* selected reference voltage * 31/64 */\r
+#define CPDACBUF2_32 (0x2000) /* selected reference voltage * 32/64 */\r
+#define CPDACBUF2_33 (0x2100) /* selected reference voltage * 33/64 */\r
+#define CPDACBUF2_34 (0x2200) /* selected reference voltage * 34/64 */\r
+#define CPDACBUF2_35 (0x2300) /* selected reference voltage * 35/64 */\r
+#define CPDACBUF2_36 (0x2400) /* selected reference voltage * 36/64 */\r
+#define CPDACBUF2_37 (0x2500) /* selected reference voltage * 37/64 */\r
+#define CPDACBUF2_38 (0x2600) /* selected reference voltage * 38/64 */\r
+#define CPDACBUF2_39 (0x2700) /* selected reference voltage * 39/64 */\r
+#define CPDACBUF2_40 (0x2800) /* selected reference voltage * 40/64 */\r
+#define CPDACBUF2_41 (0x2900) /* selected reference voltage * 41/64 */\r
+#define CPDACBUF2_42 (0x2a00) /* selected reference voltage * 42/64 */\r
+#define CPDACBUF2_43 (0x2b00) /* selected reference voltage * 43/64 */\r
+#define CPDACBUF2_44 (0x2c00) /* selected reference voltage * 44/64 */\r
+#define CPDACBUF2_45 (0x2d00) /* selected reference voltage * 45/64 */\r
+#define CPDACBUF2_46 (0x2e00) /* selected reference voltage * 46/64 */\r
+#define CPDACBUF2_47 (0x2f00) /* selected reference voltage * 47/64 */\r
+#define CPDACBUF2_48 (0x3000) /* selected reference voltage * 48/64 */\r
+#define CPDACBUF2_49 (0x3100) /* selected reference voltage * 49/64 */\r
+#define CPDACBUF2_50 (0x3200) /* selected reference voltage * 50/64 */\r
+#define CPDACBUF2_51 (0x3300) /* selected reference voltage * 51/64 */\r
+#define CPDACBUF2_52 (0x3400) /* selected reference voltage * 52/64 */\r
+#define CPDACBUF2_53 (0x3500) /* selected reference voltage * 53/64 */\r
+#define CPDACBUF2_54 (0x3600) /* selected reference voltage * 54/64 */\r
+#define CPDACBUF2_55 (0x3700) /* selected reference voltage * 55/64 */\r
+#define CPDACBUF2_56 (0x3800) /* selected reference voltage * 56/64 */\r
+#define CPDACBUF2_57 (0x3900) /* selected reference voltage * 57/64 */\r
+#define CPDACBUF2_58 (0x3a00) /* selected reference voltage * 58/64 */\r
+#define CPDACBUF2_59 (0x3b00) /* selected reference voltage * 59/64 */\r
+#define CPDACBUF2_60 (0x3c00) /* selected reference voltage * 60/64 */\r
+#define CPDACBUF2_61 (0x3d00) /* selected reference voltage * 61/64 */\r
+#define CPDACBUF2_62 (0x3e00) /* selected reference voltage * 62/64 */\r
+#define CPDACBUF2_63 (0x3f00) /* selected reference voltage * 63/64 */\r
+\r
+\r
+/*****************************************************************************\r
+ eUSCI_A0 Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_EUSCI_A0__ /* Definition to show that module is available */\r
+#ifndef __MSP430_HAS_EUSCI_Ax__\r
+#define __MSP430_HAS_EUSCI_Ax__\r
+#endif\r
+#define __MSP430_BASEADDRESS_EUSCI_A0__ 0x0500\r
+#define EUSCI_A0_BASE __MSP430_BASEADDRESS_EUSCI_A0__\r
+\r
+sfr_w(UCA0CTLW0); /* eUSCI_Ax Control Word Register 0 */\r
+sfr_b(UCA0CTLW0_L);\r
+sfr_b(UCA0CTLW0_H);\r
+sfr_w(UCA0CTLW1); /* eUSCI_Ax Control Word Register 1 */\r
+sfr_b(UCA0CTLW1_L);\r
+sfr_b(UCA0CTLW1_H);\r
+sfr_w(UCA0BRW); /* eUSCI_Ax Baud Rate Control Word Register */\r
+sfr_b(UCA0BRW_L);\r
+sfr_b(UCA0BRW_H);\r
+sfr_w(UCA0MCTLW); /* eUSCI_Ax Modulation Control Word Register */\r
+sfr_b(UCA0MCTLW_L);\r
+sfr_b(UCA0MCTLW_H);\r
+sfr_w(UCA0STATW); /* eUSCI_Ax Status Register */\r
+sfr_b(UCA0STATW_L);\r
+sfr_b(UCA0STATW_H);\r
+sfr_w(UCA0RXBUF); /* eUSCI_Ax Receive Buffer Register */\r
+sfr_b(UCA0RXBUF_L);\r
+sfr_b(UCA0RXBUF_H);\r
+sfr_w(UCA0TXBUF); /* eUSCI_Ax Transmit Buffer Register */\r
+sfr_b(UCA0TXBUF_L);\r
+sfr_b(UCA0TXBUF_H);\r
+sfr_w(UCA0ABCTL); /* eUSCI_Ax Auto Baud Rate Control Register */\r
+sfr_b(UCA0ABCTL_L);\r
+sfr_b(UCA0ABCTL_H);\r
+sfr_w(UCA0IRCTL); /* eUSCI_Ax IrDA Control Word Register */\r
+sfr_b(UCA0IRCTL_L);\r
+sfr_b(UCA0IRCTL_H);\r
+sfr_w(UCA0IE); /* eUSCI_Ax Interrupt Enable Register */\r
+sfr_b(UCA0IE_L);\r
+sfr_b(UCA0IE_H);\r
+sfr_w(UCA0IFG); /* eUSCI_Ax Interrupt Flag Register */\r
+sfr_b(UCA0IFG_L);\r
+sfr_b(UCA0IFG_H);\r
+sfr_w(UCA0IV); /* eUSCI_Ax Interrupt Vector Register */\r
+sfr_b(UCA0IV_L);\r
+sfr_b(UCA0IV_H);\r
+\r
+/* eUSCI_A0 Register Offsets */\r
+#define OFS_UCA0CTLW0 (0x0000)\r
+#define OFS_UCA0CTLW1 (0x0002)\r
+#define OFS_UCA0BRW (0x0006)\r
+#define OFS_UCA0MCTLW (0x0008)\r
+#define OFS_UCA0STATW (0x000A)\r
+#define OFS_UCA0RXBUF (0x000C)\r
+#define OFS_UCA0TXBUF (0x000E)\r
+#define OFS_UCA0ABCTL (0x0010)\r
+#define OFS_UCA0IRCTL (0x0012)\r
+#define OFS_UCA0IE (0x001A)\r
+#define OFS_UCA0IFG (0x001C)\r
+#define OFS_UCA0IV (0x001E)\r
+\r
+/* eUSCI_A0 Control Bits */\r
+\r
+/* UCA0CTLW0 Control Bits */\r
+#define UCSWRST (0x0001) /* Software reset enable */\r
+#define UCSWRST_0 (0x0000) /* Disabled. eUSCI_A reset released for operation */\r
+#define UCSWRST_1 (0x0001) /* Enabled. eUSCI_A logic held in reset state */\r
+#define UCSWRST__DISABLE (0x0000) /* Disabled. eUSCI_A reset released for operation */\r
+#define UCSWRST__ENABLE (0x0001) /* Enabled. eUSCI_A logic held in reset state */\r
+#define UCTXBRK (0x0002) /* Transmit break */\r
+#define UCTXBRK_0 (0x0000) /* Next frame transmitted is not a break */\r
+#define UCTXBRK_1 (0x0002) /* Next frame transmitted is a break or a break/synch */\r
+#define UCTXADDR (0x0004) /* Transmit address */\r
+#define UCTXADDR_0 (0x0000) /* Next frame transmitted is data */\r
+#define UCTXADDR_1 (0x0004) /* Next frame transmitted is an address */\r
+#define UCDORM (0x0008) /* Dormant */\r
+#define UCDORM_0 (0x0000) /* Not dormant. All received characters set UCRXIFG. */\r
+#define UCDORM_1 (0x0008) /* Dormant. Only characters that are preceded by an idle-line or \r
+ with address bit set UCRXIFG. In UART mode with automatic \r
+ baud-rate detection, only the combination of a break and synch\r
+ field sets UCRXIFG. */\r
+#define UCBRKIE (0x0010) /* Receive break character interrupt enable */\r
+#define UCBRKIE_0 (0x0000) /* Received break characters do not set UCRXIFG */\r
+#define UCBRKIE_1 (0x0010) /* Received break characters set UCRXIFG */\r
+#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */\r
+#define UCRXEIE_0 (0x0000) /* Erroneous characters rejected and UCRXIFG is not set */\r
+#define UCRXEIE_1 (0x0020) /* Erroneous characters received set UCRXIFG */\r
+#define UCSSEL (0x00c0) /* eUSCI_A clock source select */\r
+#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
+#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
+#define UCSSEL_0 (0x0000) /* UCLK */\r
+#define UCSSEL_1 (0x0040) /* ACLK */\r
+#define UCSSEL_2 (0x0080) /* SMCLK */\r
+#define UCSSEL_3 (0x00c0) /* SMCLK */\r
+#define UCSSEL__UCLK (0x0000) /* UCLK */\r
+#define UCSSEL__ACLK (0x0040) /* ACLK */\r
+#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
+#define UCSYNC (0x0100) /* Synchronous mode enable */\r
+#define UCSYNC_0 (0x0000) /* Asynchronous mode */\r
+#define UCSYNC_1 (0x0100) /* Synchronous mode */\r
+#define UCSYNC__ASYNC (0x0000) /* Asynchronous mode */\r
+#define UCSYNC__SYNC (0x0100) /* Synchronous mode */\r
+#define UCMODE (0x0600) /* eUSCI_A mode */\r
+#define UCMODE0 (0x0200) /* eUSCI_A mode */\r
+#define UCMODE1 (0x0400) /* eUSCI_A mode */\r
+#define UCMODE_0 (0x0000) /* UART mode */\r
+#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */\r
+#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */\r
+#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */\r
+#define UCSPB (0x0800) /* Stop bit select */\r
+#define UCSPB_0 (0x0000) /* One stop bit */\r
+#define UCSPB_1 (0x0800) /* Two stop bits */\r
+#define UC7BIT (0x1000) /* Character length */\r
+#define UC7BIT_0 (0x0000) /* 8-bit data */\r
+#define UC7BIT_1 (0x1000) /* 7-bit data */\r
+#define UC7BIT__8BIT (0x0000) /* 8-bit data */\r
+#define UC7BIT__7BIT (0x1000) /* 7-bit data */\r
+#define UCMSB (0x2000) /* MSB first select */\r
+#define UCMSB_0 (0x0000) /* LSB first */\r
+#define UCMSB_1 (0x2000) /* MSB first */\r
+#define UCPAR (0x4000) /* Parity select */\r
+#define UCPAR_0 (0x0000) /* Odd parity */\r
+#define UCPAR_1 (0x4000) /* Even parity */\r
+#define UCPAR__ODD (0x0000) /* Odd parity */\r
+#define UCPAR__EVEN (0x4000) /* Even parity */\r
+#define UCPEN (0x8000) /* Parity enable */\r
+#define UCPEN_0 (0x0000) /* Parity disabled */\r
+#define UCPEN_1 (0x8000) /* Parity enabled. Parity bit is generated (UCAxTXD) and expected\r
+ (UCAxRXD). In address-bit multiprocessor mode, the address bit\r
+ is included in the parity calculation. */\r
+\r
+/* UCA0CTLW0_SPI Control Bits */\r
+#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
+#define UCSTEM_0 (0x0000) /* STE pin is used to prevent conflicts with other masters */\r
+#define UCSTEM_1 (0x0002) /* STE pin is used to generate the enable signal for a 4-wire \r
+ slave */\r
+#define UCMST (0x0800) /* Master mode select */\r
+#define UCMST_0 (0x0000) /* Slave mode */\r
+#define UCMST_1 (0x0800) /* Master mode */\r
+#define UCMST__SLAVE (0x0000) /* Slave mode */\r
+#define UCMST__MASTER (0x0800) /* Master mode */\r
+#define UCCKPL (0x4000) /* Clock polarity select */\r
+#define UCCKPL_0 (0x0000) /* The inactive state is low */\r
+#define UCCKPL_1 (0x4000) /* The inactive state is high */\r
+#define UCCKPL__LOW (0x0000) /* The inactive state is low */\r
+#define UCCKPL__HIGH (0x4000) /* The inactive state is high */\r
+#define UCCKPH (0x8000) /* Clock phase select */\r
+#define UCCKPH_0 (0x0000) /* Data is changed on the first UCLK edge and captured on the \r
+ following edge. */\r
+#define UCCKPH_1 (0x8000) /* Data is captured on the first UCLK edge and changed on the \r
+ following edge. */\r
+\r
+/* UCA0CTLW1 Control Bits */\r
+#define UCGLIT (0x0003) /* Deglitch time */\r
+#define UCGLIT0 (0x0001) /* Deglitch time */\r
+#define UCGLIT1 (0x0002) /* Deglitch time */\r
+#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */\r
+#define UCGLIT_1 (0x0001) /* Approximately 50 ns */\r
+#define UCGLIT_2 (0x0002) /* Approximately 100 ns */\r
+#define UCGLIT_3 (0x0003) /* Approximately 200 ns */\r
+\r
+/* UCA0BRW Control Bits */\r
+#define UCBR (0xffff) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR0 (0x0001) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR1 (0x0002) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR2 (0x0004) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR3 (0x0008) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR4 (0x0010) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR5 (0x0020) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR6 (0x0040) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR7 (0x0080) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR8 (0x0100) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR9 (0x0200) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR10 (0x0400) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR11 (0x0800) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR12 (0x1000) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR13 (0x2000) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR14 (0x4000) /* Clock prescaler setting of the Baud rate generator */\r
+#define UCBR15 (0x8000) /* Clock prescaler setting of the Baud rate generator */\r
+\r
+/* UCA0MCTLW Control Bits */\r
+#define UCOS16 (0x0001) /* Oversampling mode enabled */\r
+#define UCOS16_0 (0x0000) /* Disabled */\r
+#define UCOS16_1 (0x0001) /* Enabled */\r
+#define UCBRF (0x00f0) /* First modulation stage select */\r
+#define UCBRF0 (0x0010) /* First modulation stage select */\r
+#define UCBRF1 (0x0020) /* First modulation stage select */\r
+#define UCBRF2 (0x0040) /* First modulation stage select */\r
+#define UCBRF3 (0x0080) /* First modulation stage select */\r
+#define UCBRS (0xff00) /* Second modulation stage select */\r
+#define UCBRS0 (0x0100) /* Second modulation stage select */\r
+#define UCBRS1 (0x0200) /* Second modulation stage select */\r
+#define UCBRS2 (0x0400) /* Second modulation stage select */\r
+#define UCBRS3 (0x0800) /* Second modulation stage select */\r
+#define UCBRS4 (0x1000) /* Second modulation stage select */\r
+#define UCBRS5 (0x2000) /* Second modulation stage select */\r
+#define UCBRS6 (0x4000) /* Second modulation stage select */\r
+#define UCBRS7 (0x8000) /* Second modulation stage select */\r
+\r
+/* UCA0STATW Control Bits */\r
+#define UCBUSY (0x0001) /* eUSCI_A busy */\r
+#define UCBUSY_0 (0x0000) /* eUSCI_A inactive */\r
+#define UCBUSY_1 (0x0001) /* eUSCI_A transmitting or receiving */\r
+#define UCBUSY__IDLE (0x0000) /* eUSCI_A inactive */\r
+#define UCBUSY__BUSY (0x0001) /* eUSCI_A transmitting or receiving */\r
+#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */\r
+#define UCADDR_UCIDLE_0 (0x0000) /* UCADDR: Received character is data. UCIDLE: No idle line \r
+ detected */\r
+#define UCADDR_UCIDLE_1 (0x0002) /* UCADDR: Received character is an address. UCIDLE: Idle line \r
+ detected */\r
+#define UCRXERR (0x0004) /* Receive error flag */\r
+#define UCRXERR_0 (0x0000) /* No receive errors detected */\r
+#define UCRXERR_1 (0x0004) /* Receive error detected */\r
+#define UCBRK (0x0008) /* Break detect flag */\r
+#define UCBRK_0 (0x0000) /* No break condition */\r
+#define UCBRK_1 (0x0008) /* Break condition occurred */\r
+#define UCPE (0x0010) /* */\r
+#define UCPE_0 (0x0000) /* No error */\r
+#define UCPE_1 (0x0010) /* Character received with parity error */\r
+#define UCOE (0x0020) /* Overrun error flag */\r
+#define UCOE_0 (0x0000) /* No error */\r
+#define UCOE_1 (0x0020) /* Overrun error occurred */\r
+#define UCFE (0x0040) /* Framing error flag */\r
+#define UCFE_0 (0x0000) /* No error */\r
+#define UCFE_1 (0x0040) /* Character received with low stop bit */\r
+#define UCLISTEN (0x0080) /* Listen enable */\r
+#define UCLISTEN_0 (0x0000) /* Disabled */\r
+#define UCLISTEN_1 (0x0080) /* Enabled. UCAxTXD is internally fed back to the receiver */\r
+\r
+/* UCA0RXBUF Control Bits */\r
+#define UCRXBUF (0x00ff) /* Receive data buffer */\r
+#define UCRXBUF0 (0x0001) /* Receive data buffer */\r
+#define UCRXBUF1 (0x0002) /* Receive data buffer */\r
+#define UCRXBUF2 (0x0004) /* Receive data buffer */\r
+#define UCRXBUF3 (0x0008) /* Receive data buffer */\r
+#define UCRXBUF4 (0x0010) /* Receive data buffer */\r
+#define UCRXBUF5 (0x0020) /* Receive data buffer */\r
+#define UCRXBUF6 (0x0040) /* Receive data buffer */\r
+#define UCRXBUF7 (0x0080) /* Receive data buffer */\r
+\r
+/* UCA0TXBUF Control Bits */\r
+#define UCTXBUF (0x00ff) /* Transmit data buffer */\r
+#define UCTXBUF0 (0x0001) /* Transmit data buffer */\r
+#define UCTXBUF1 (0x0002) /* Transmit data buffer */\r
+#define UCTXBUF2 (0x0004) /* Transmit data buffer */\r
+#define UCTXBUF3 (0x0008) /* Transmit data buffer */\r
+#define UCTXBUF4 (0x0010) /* Transmit data buffer */\r
+#define UCTXBUF5 (0x0020) /* Transmit data buffer */\r
+#define UCTXBUF6 (0x0040) /* Transmit data buffer */\r
+#define UCTXBUF7 (0x0080) /* Transmit data buffer */\r
+\r
+/* UCA0ABCTL Control Bits */\r
+#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */\r
+#define UCABDEN_0 (0x0000) /* Baud-rate detection disabled. Length of break and synch field \r
+ is not measured. */\r
+#define UCABDEN_1 (0x0001) /* Baud-rate detection enabled. Length of break and synch field \r
+ is measured and baud-rate settings are changed accordingly. */\r
+#define UCBTOE (0x0004) /* Break time out error */\r
+#define UCBTOE_0 (0x0000) /* No error */\r
+#define UCBTOE_1 (0x0004) /* Length of break field exceeded 22 bit times */\r
+#define UCSTOE (0x0008) /* Synch field time out error */\r
+#define UCSTOE_0 (0x0000) /* No error */\r
+#define UCSTOE_1 (0x0008) /* Length of synch field exceeded measurable time */\r
+#define UCDELIM (0x0030) /* Break/synch delimiter length */\r
+#define UCDELIM0 (0x0010) /* Break/synch delimiter length */\r
+#define UCDELIM1 (0x0020) /* Break/synch delimiter length */\r
+#define UCDELIM_0 (0x0000) /* 1 bit time */\r
+#define UCDELIM_1 (0x0010) /* 2 bit times */\r
+#define UCDELIM_2 (0x0020) /* 3 bit times */\r
+#define UCDELIM_3 (0x0030) /* 4 bit times */\r
+\r
+/* UCA0IRCTL Control Bits */\r
+#define UCIREN (0x0001) /* IrDA encoder/decoder enable */\r
+#define UCIREN_0 (0x0000) /* IrDA encoder/decoder disabled */\r
+#define UCIREN_1 (0x0001) /* IrDA encoder/decoder enabled */\r
+#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */\r
+#define UCIRTXCLK_0 (0x0000) /* BRCLK */\r
+#define UCIRTXCLK_1 (0x0002) /* BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. */\r
+#define UCIRTXPL (0x00fc) /* Transmit pulse length */\r
+#define UCIRTXPL0 (0x0004) /* Transmit pulse length */\r
+#define UCIRTXPL1 (0x0008) /* Transmit pulse length */\r
+#define UCIRTXPL2 (0x0010) /* Transmit pulse length */\r
+#define UCIRTXPL3 (0x0020) /* Transmit pulse length */\r
+#define UCIRTXPL4 (0x0040) /* Transmit pulse length */\r
+#define UCIRTXPL5 (0x0080) /* Transmit pulse length */\r
+#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */\r
+#define UCIRRXFE_0 (0x0000) /* Receive filter disabled */\r
+#define UCIRRXFE_1 (0x0100) /* Receive filter enabled */\r
+#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */\r
+#define UCIRRXPL_0 (0x0000) /* IrDA transceiver delivers a high pulse when a light pulse is \r
+ seen */\r
+#define UCIRRXPL_1 (0x0200) /* IrDA transceiver delivers a low pulse when a light pulse is \r
+ seen */\r
+#define UCIRRXPL__HIGH (0x0000) /* IrDA transceiver delivers a high pulse when a light pulse is \r
+ seen */\r
+#define UCIRRXPL__LOW (0x0200) /* IrDA transceiver delivers a low pulse when a light pulse is \r
+ seen */\r
+#define UCIRRXFL (0xfc00) /* Receive filter length */\r
+#define UCIRRXFL0 (0x0400) /* Receive filter length */\r
+#define UCIRRXFL1 (0x0800) /* Receive filter length */\r
+#define UCIRRXFL2 (0x1000) /* Receive filter length */\r
+#define UCIRRXFL3 (0x2000) /* Receive filter length */\r
+#define UCIRRXFL4 (0x4000) /* Receive filter length */\r
+#define UCIRRXFL5 (0x8000) /* Receive filter length */\r
+\r
+/* UCA0IE Control Bits */\r
+#define UCRXIE (0x0001) /* Receive interrupt enable */\r
+#define UCRXIE_0 (0x0000) /* Interrupt disabled */\r
+#define UCRXIE_1 (0x0001) /* Interrupt enabled */\r
+#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
+#define UCTXIE_0 (0x0000) /* Interrupt disabled */\r
+#define UCTXIE_1 (0x0002) /* Interrupt enabled */\r
+#define UCSTTIE (0x0004) /* Start bit interrupt enable */\r
+#define UCSTTIE_0 (0x0000) /* Interrupt disabled */\r
+#define UCSTTIE_1 (0x0004) /* Interrupt enabled */\r
+#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */\r
+#define UCTXCPTIE_0 (0x0000) /* Interrupt disabled */\r
+#define UCTXCPTIE_1 (0x0008) /* Interrupt enabled */\r
+\r
+/* UCA0IFG Control Bits */\r
+#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
+#define UCRXIFG_0 (0x0000) /* No interrupt pending */\r
+#define UCRXIFG_1 (0x0001) /* Interrupt pending */\r
+#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
+#define UCTXIFG_0 (0x0000) /* No interrupt pending */\r
+#define UCTXIFG_1 (0x0002) /* Interrupt pending */\r
+#define UCSTTIFG (0x0004) /* Start bit interrupt flag */\r
+#define UCSTTIFG_0 (0x0000) /* No interrupt pending */\r
+#define UCSTTIFG_1 (0x0004) /* Interrupt pending */\r
+#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */\r
+#define UCTXCPTIFG_0 (0x0000) /* No interrupt pending */\r
+#define UCTXCPTIFG_1 (0x0008) /* Interrupt pending */\r
+\r
+/* UCA0IV Control Bits */\r
+#define UCIV (0xffff) /* eUSCI_A interrupt vector value */\r
+#define UCIV0 (0x0001) /* eUSCI_A interrupt vector value */\r
+#define UCIV1 (0x0002) /* eUSCI_A interrupt vector value */\r
+#define UCIV2 (0x0004) /* eUSCI_A interrupt vector value */\r
+#define UCIV3 (0x0008) /* eUSCI_A interrupt vector value */\r
+#define UCIV4 (0x0010) /* eUSCI_A interrupt vector value */\r
+#define UCIV5 (0x0020) /* eUSCI_A interrupt vector value */\r
+#define UCIV6 (0x0040) /* eUSCI_A interrupt vector value */\r
+#define UCIV7 (0x0080) /* eUSCI_A interrupt vector value */\r
+#define UCIV8 (0x0100) /* eUSCI_A interrupt vector value */\r
+#define UCIV9 (0x0200) /* eUSCI_A interrupt vector value */\r
+#define UCIV10 (0x0400) /* eUSCI_A interrupt vector value */\r
+#define UCIV11 (0x0800) /* eUSCI_A interrupt vector value */\r
+#define UCIV12 (0x1000) /* eUSCI_A interrupt vector value */\r
+#define UCIV13 (0x2000) /* eUSCI_A interrupt vector value */\r
+#define UCIV14 (0x4000) /* eUSCI_A interrupt vector value */\r
+#define UCIV15 (0x8000) /* eUSCI_A interrupt vector value */\r
+#define UCIV_0 (0x0000) /* No interrupt pending */\r
+#define UCIV_2 (0x0002) /* Interrupt Source: Receive buffer full; Interrupt Flag: \r
+ UCRXIFG; Interrupt Priority: Highest */\r
+#define UCIV_4 (0x0004) /* Interrupt Source: Transmit buffer empty; Interrupt Flag: \r
+ UCTXIFG */\r
+#define UCIV_6 (0x0006) /* Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG */\r
+#define UCIV_8 (0x0008) /* Interrupt Source: Transmit complete; Interrupt Flag: \r
+ UCTXCPTIFG; Interrupt Priority: Lowest */\r
+#define UCIV__NONE (0x0000) /* No interrupt pending */\r
+#define UCIV__UCRXIFG (0x0002) /* Interrupt Source: Receive buffer full; Interrupt Flag: \r
+ UCRXIFG; Interrupt Priority: Highest */\r
+#define UCIV__UCTXIFG (0x0004) /* Interrupt Source: Transmit buffer empty; Interrupt Flag: \r
+ UCTXIFG */\r
+#define UCIV__UCSTTIFG (0x0006) /* Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG */\r
+#define UCIV__UCTXCPTIFG (0x0008) /* Interrupt Source: Transmit complete; Interrupt Flag: \r
+ UCTXCPTIFG; Interrupt Priority: Lowest */\r
+\r
+\r
+/*****************************************************************************\r
+ eUSCI_A1 Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_EUSCI_A1__ /* Definition to show that module is available */\r
+#ifndef __MSP430_HAS_EUSCI_Ax__\r
+#define __MSP430_HAS_EUSCI_Ax__\r
+#endif\r
+#define __MSP430_BASEADDRESS_EUSCI_A1__ 0x0520\r
+#define EUSCI_A1_BASE __MSP430_BASEADDRESS_EUSCI_A1__\r
+\r
+sfr_w(UCA1CTLW0); /* eUSCI_Ax Control Word Register 0 */\r
+sfr_b(UCA1CTLW0_L);\r
+sfr_b(UCA1CTLW0_H);\r
+sfr_w(UCA1CTLW1); /* eUSCI_Ax Control Word Register 1 */\r
+sfr_b(UCA1CTLW1_L);\r
+sfr_b(UCA1CTLW1_H);\r
+sfr_w(UCA1BRW); /* eUSCI_Ax Baud Rate Control Word Register */\r
+sfr_b(UCA1BRW_L);\r
+sfr_b(UCA1BRW_H);\r
+sfr_w(UCA1MCTLW); /* eUSCI_Ax Modulation Control Word Register */\r
+sfr_b(UCA1MCTLW_L);\r
+sfr_b(UCA1MCTLW_H);\r
+sfr_w(UCA1STATW); /* eUSCI_Ax Status Register */\r
+sfr_b(UCA1STATW_L);\r
+sfr_b(UCA1STATW_H);\r
+sfr_w(UCA1RXBUF); /* eUSCI_Ax Receive Buffer Register */\r
+sfr_b(UCA1RXBUF_L);\r
+sfr_b(UCA1RXBUF_H);\r
+sfr_w(UCA1TXBUF); /* eUSCI_Ax Transmit Buffer Register */\r
+sfr_b(UCA1TXBUF_L);\r
+sfr_b(UCA1TXBUF_H);\r
+sfr_w(UCA1ABCTL); /* eUSCI_Ax Auto Baud Rate Control Register */\r
+sfr_b(UCA1ABCTL_L);\r
+sfr_b(UCA1ABCTL_H);\r
+sfr_w(UCA1IRCTL); /* eUSCI_Ax IrDA Control Word Register */\r
+sfr_b(UCA1IRCTL_L);\r
+sfr_b(UCA1IRCTL_H);\r
+sfr_w(UCA1IE); /* eUSCI_Ax Interrupt Enable Register */\r
+sfr_b(UCA1IE_L);\r
+sfr_b(UCA1IE_H);\r
+sfr_w(UCA1IFG); /* eUSCI_Ax Interrupt Flag Register */\r
+sfr_b(UCA1IFG_L);\r
+sfr_b(UCA1IFG_H);\r
+sfr_w(UCA1IV); /* eUSCI_Ax Interrupt Vector Register */\r
+sfr_b(UCA1IV_L);\r
+sfr_b(UCA1IV_H);\r
+\r
+/* eUSCI_A1 Register Offsets */\r
+#define OFS_UCA1CTLW0 (0x0000)\r
+#define OFS_UCA1CTLW1 (0x0002)\r
+#define OFS_UCA1BRW (0x0006)\r
+#define OFS_UCA1MCTLW (0x0008)\r
+#define OFS_UCA1STATW (0x000A)\r
+#define OFS_UCA1RXBUF (0x000C)\r
+#define OFS_UCA1TXBUF (0x000E)\r
+#define OFS_UCA1ABCTL (0x0010)\r
+#define OFS_UCA1IRCTL (0x0012)\r
+#define OFS_UCA1IE (0x001A)\r
+#define OFS_UCA1IFG (0x001C)\r
+#define OFS_UCA1IV (0x001E)\r
+\r
+/* No control bits available or already defined for another module */\r
+\r
+/*****************************************************************************\r
+ eUSCI_B0 Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_EUSCI_B0__ /* Definition to show that module is available */\r
+#ifndef __MSP430_HAS_EUSCI_Bx__\r
+#define __MSP430_HAS_EUSCI_Bx__\r
+#endif\r
+#define __MSP430_BASEADDRESS_EUSCI_B0__ 0x0540\r
+#define EUSCI_B0_BASE __MSP430_BASEADDRESS_EUSCI_B0__\r
+\r
+sfr_w(UCB0CTLW0); /* eUSCI_Bx Control Word Register 0 */\r
+sfr_b(UCB0CTLW0_L);\r
+sfr_b(UCB0CTLW0_H);\r
+sfr_w(UCB0CTLW1); /* eUSCI_Bx Control Word Register 1 */\r
+sfr_b(UCB0CTLW1_L);\r
+sfr_b(UCB0CTLW1_H);\r
+sfr_w(UCB0BRW); /* eUSCI_Bx Baud Rate Control Word Register */\r
+sfr_b(UCB0BRW_L);\r
+sfr_b(UCB0BRW_H);\r
+sfr_w(UCB0STATW); /* eUSCI_Bx Status Register */\r
+sfr_b(UCB0STATW_L);\r
+sfr_b(UCB0STATW_H);\r
+sfr_w(UCB0TBCNT); /* eUSCI_Bx Byte Counter Threshold Register */\r
+sfr_b(UCB0TBCNT_L);\r
+sfr_b(UCB0TBCNT_H);\r
+sfr_w(UCB0RXBUF); /* eUSCI_Bx Receive Buffer Register */\r
+sfr_b(UCB0RXBUF_L);\r
+sfr_b(UCB0RXBUF_H);\r
+sfr_w(UCB0TXBUF); /* eUSCI_Bx Transmit Buffer Register */\r
+sfr_b(UCB0TXBUF_L);\r
+sfr_b(UCB0TXBUF_H);\r
+sfr_w(UCB0I2COA0); /* eUSCI_Bx I2C Own Address 0 Register */\r
+sfr_b(UCB0I2COA0_L);\r
+sfr_b(UCB0I2COA0_H);\r
+sfr_w(UCB0I2COA1); /* eUSCI_Bx I2C Own Address 1 Register */\r
+sfr_b(UCB0I2COA1_L);\r
+sfr_b(UCB0I2COA1_H);\r
+sfr_w(UCB0I2COA2); /* eUSCI_Bx I2C Own Address 2 Register */\r
+sfr_b(UCB0I2COA2_L);\r
+sfr_b(UCB0I2COA2_H);\r
+sfr_w(UCB0I2COA3); /* eUSCI_Bx I2C Own Address 3 Register */\r
+sfr_b(UCB0I2COA3_L);\r
+sfr_b(UCB0I2COA3_H);\r
+sfr_w(UCB0ADDRX); /* eUSCI_Bx I2C Received Address Register */\r
+sfr_b(UCB0ADDRX_L);\r
+sfr_b(UCB0ADDRX_H);\r
+sfr_w(UCB0ADDMASK); /* eUSCI_Bx I2C Address Mask Register */\r
+sfr_b(UCB0ADDMASK_L);\r
+sfr_b(UCB0ADDMASK_H);\r
+sfr_w(UCB0I2CSA); /* eUSCI_Bx I2C Slave Address Register */\r
+sfr_b(UCB0I2CSA_L);\r
+sfr_b(UCB0I2CSA_H);\r
+sfr_w(UCB0IE); /* eUSCI_Bx Interrupt Enable Register */\r
+sfr_b(UCB0IE_L);\r
+sfr_b(UCB0IE_H);\r
+sfr_w(UCB0IFG); /* eUSCI_Bx Interrupt Flag Register */\r
+sfr_b(UCB0IFG_L);\r
+sfr_b(UCB0IFG_H);\r
+sfr_w(UCB0IV); /* eUSCI_Bx Interrupt Vector Register */\r
+sfr_b(UCB0IV_L);\r
+sfr_b(UCB0IV_H);\r
+\r
+/* eUSCI_B0 Register Offsets */\r
+#define OFS_UCB0CTLW0 (0x0000)\r
+#define OFS_UCB0CTLW1 (0x0002)\r
+#define OFS_UCB0BRW (0x0006)\r
+#define OFS_UCB0STATW (0x0008)\r
+#define OFS_UCB0TBCNT (0x000A)\r
+#define OFS_UCB0RXBUF (0x000C)\r
+#define OFS_UCB0TXBUF (0x000E)\r
+#define OFS_UCB0I2COA0 (0x0014)\r
+#define OFS_UCB0I2COA1 (0x0016)\r
+#define OFS_UCB0I2COA2 (0x0018)\r
+#define OFS_UCB0I2COA3 (0x001A)\r
+#define OFS_UCB0ADDRX (0x001C)\r
+#define OFS_UCB0ADDMASK (0x001E)\r
+#define OFS_UCB0I2CSA (0x0020)\r
+#define OFS_UCB0IE (0x002A)\r
+#define OFS_UCB0IFG (0x002C)\r
+#define OFS_UCB0IV (0x002E)\r
+\r
+/* eUSCI_B0 Control Bits */\r
+\r
+/* UCB0CTLW0 Control Bits */\r
+#define UCTXSTT (0x0002) /* Transmit START condition in master mode */\r
+#define UCTXSTT_0 (0x0000) /* Do not generate START condition */\r
+#define UCTXSTT_1 (0x0002) /* Generate START condition */\r
+#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */\r
+#define UCTXSTP_0 (0x0000) /* No STOP generated */\r
+#define UCTXSTP_1 (0x0004) /* Generate STOP */\r
+#define UCTXNACK (0x0008) /* Transmit a NACK */\r
+#define UCTXNACK_0 (0x0000) /* Acknowledge normally */\r
+#define UCTXNACK_1 (0x0008) /* Generate NACK */\r
+#define UCTR (0x0010) /* Transmitter/receiver */\r
+#define UCTR_0 (0x0000) /* Receiver */\r
+#define UCTR_1 (0x0010) /* Transmitter */\r
+#define UCTR__RX (0x0000) /* Receiver */\r
+#define UCTR__TX (0x0010) /* Transmitter */\r
+#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */\r
+#define UCTXACK_0 (0x0000) /* Do not acknowledge the slave address */\r
+#define UCTXACK_1 (0x0020) /* Acknowledge the slave address */\r
+#define UCSSEL__UCLKI (0x0000) /* UCLKI */\r
+#define UCMM (0x2000) /* Multi-master environment select */\r
+#define UCMM_0 (0x0000) /* Single master environment. There is no other master in the \r
+ system. The address compare unit is disabled. */\r
+#define UCMM_1 (0x2000) /* Multi-master environment */\r
+#define UCMM__SINGLE (0x0000) /* Single master environment. There is no other master in the \r
+ system. The address compare unit is disabled. */\r
+#define UCMM__MULTI (0x2000) /* Multi-master environment */\r
+#define UCSLA10 (0x4000) /* Slave addressing mode select */\r
+#define UCSLA10_0 (0x0000) /* Address slave with 7-bit address */\r
+#define UCSLA10_1 (0x4000) /* Address slave with 10-bit address */\r
+#define UCSLA10__7BIT (0x0000) /* Address slave with 7-bit address */\r
+#define UCSLA10__10BIT (0x4000) /* Address slave with 10-bit address */\r
+#define UCA10 (0x8000) /* Own addressing mode select */\r
+#define UCA10_0 (0x0000) /* Own address is a 7-bit address */\r
+#define UCA10_1 (0x8000) /* Own address is a 10-bit address */\r
+\r
+/* UCB0CTLW1 Control Bits */\r
+#define UCASTP (0x000c) /* Automatic STOP condition generation */\r
+#define UCASTP0 (0x0004) /* Automatic STOP condition generation */\r
+#define UCASTP1 (0x0008) /* Automatic STOP condition generation */\r
+#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated \r
+ after the user sets the UCTXSTP bit. The value in UCBxTBCNT is\r
+ a don't care. */\r
+#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold \r
+ defined in UCBxTBCNT */\r
+#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte \r
+ counter value reached UCBxTBCNT. UCBCNTIFG is set with the \r
+ byte counter reaching the threshold */\r
+#define UCASTP_3 (0x000c) /* Reserved */\r
+#define UCSWACK (0x0010) /* SW or HW ACK control */\r
+#define UCSWACK_0 (0x0000) /* The address acknowledge of the slave is controlled by the \r
+ eUSCI_B module */\r
+#define UCSWACK_1 (0x0010) /* The user needs to trigger the sending of the address ACK by \r
+ issuing UCTXACK */\r
+#define UCSTPNACK (0x0020) /* ACK all master bytes */\r
+#define UCSTPNACK_0 (0x0000) /* Send a non-acknowledge before the STOP condition as a master \r
+ receiver (conform to I2C standard) */\r
+#define UCSTPNACK_1 (0x0020) /* All bytes are acknowledged by the eUSCI_B when configured as \r
+ master receiver */\r
+#define UCCLTO (0x00c0) /* Clock low timeout select */\r
+#define UCCLTO0 (0x0040) /* Clock low timeout select */\r
+#define UCCLTO1 (0x0080) /* Clock low timeout select */\r
+#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */\r
+#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */\r
+#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */\r
+#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */\r
+#define UCETXINT (0x0100) /* Early UCTXIFG0 */\r
+#define UCETXINT_0 (0x0000) /* UCTXIFGx is set after an address match with UCxI2COAx and the \r
+ direction bit indicating slave transmit */\r
+#define UCETXINT_1 (0x0100) /* UCTXIFG0 is set for each START condition */\r
+\r
+/* UCB0STATW Control Bits */\r
+#define UCBBUSY (0x0010) /* Bus busy */\r
+#define UCBBUSY_0 (0x0000) /* Bus inactive */\r
+#define UCBBUSY_1 (0x0010) /* Bus busy */\r
+#define UCBBUSY__IDLE (0x0000) /* Bus inactive */\r
+#define UCBBUSY__BUSY (0x0010) /* Bus busy */\r
+#define UCGC (0x0020) /* General call address received */\r
+#define UCGC_0 (0x0000) /* No general call address received */\r
+#define UCGC_1 (0x0020) /* General call address received */\r
+#define UCSCLLOW (0x0040) /* SCL low */\r
+#define UCSCLLOW_0 (0x0000) /* SCL is not held low */\r
+#define UCSCLLOW_1 (0x0040) /* SCL is held low */\r
+#define UCBCNT (0xff00) /* Hardware byte counter value */\r
+#define UCBCNT0 (0x0100) /* Hardware byte counter value */\r
+#define UCBCNT1 (0x0200) /* Hardware byte counter value */\r
+#define UCBCNT2 (0x0400) /* Hardware byte counter value */\r
+#define UCBCNT3 (0x0800) /* Hardware byte counter value */\r
+#define UCBCNT4 (0x1000) /* Hardware byte counter value */\r
+#define UCBCNT5 (0x2000) /* Hardware byte counter value */\r
+#define UCBCNT6 (0x4000) /* Hardware byte counter value */\r
+#define UCBCNT7 (0x8000) /* Hardware byte counter value */\r
+\r
+/* UCB0TBCNT Control Bits */\r
+#define UCTBCNT (0x00ff) /* Byte counter threshold value */\r
+#define UCTBCNT0 (0x0001) /* Byte counter threshold value */\r
+#define UCTBCNT1 (0x0002) /* Byte counter threshold value */\r
+#define UCTBCNT2 (0x0004) /* Byte counter threshold value */\r
+#define UCTBCNT3 (0x0008) /* Byte counter threshold value */\r
+#define UCTBCNT4 (0x0010) /* Byte counter threshold value */\r
+#define UCTBCNT5 (0x0020) /* Byte counter threshold value */\r
+#define UCTBCNT6 (0x0040) /* Byte counter threshold value */\r
+#define UCTBCNT7 (0x0080) /* Byte counter threshold value */\r
+\r
+/* UCB0I2COA0 Control Bits */\r
+#define I2COA0 (0x03ff) /* I2C own address */\r
+#define I2COA00 (0x0001) /* I2C own address */\r
+#define I2COA01 (0x0002) /* I2C own address */\r
+#define I2COA02 (0x0004) /* I2C own address */\r
+#define I2COA03 (0x0008) /* I2C own address */\r
+#define I2COA04 (0x0010) /* I2C own address */\r
+#define I2COA05 (0x0020) /* I2C own address */\r
+#define I2COA06 (0x0040) /* I2C own address */\r
+#define I2COA07 (0x0080) /* I2C own address */\r
+#define I2COA08 (0x0100) /* I2C own address */\r
+#define I2COA09 (0x0200) /* I2C own address */\r
+#define UCOAEN (0x0400) /* Own Address enable register */\r
+#define UCOAEN_0 (0x0000) /* The slave address defined in I2COA0 is disabled */\r
+#define UCOAEN_1 (0x0400) /* The slave address defined in I2COA0 is enabled */\r
+#define UCOAEN__DISABLE (0x0000) /* The slave address defined in I2COA0 is disabled */\r
+#define UCOAEN__ENABLE (0x0400) /* The slave address defined in I2COA0 is enabled */\r
+#define UCGCEN (0x8000) /* General call response enable */\r
+#define UCGCEN_0 (0x0000) /* Do not respond to a general call */\r
+#define UCGCEN_1 (0x8000) /* Respond to a general call */\r
+\r
+/* UCB0I2COA1 Control Bits */\r
+#define I2COA1 (0x03ff) /* I2C own address */\r
+#define I2COA10 (0x0001) /* I2C own address */\r
+#define I2COA11 (0x0002) /* I2C own address */\r
+#define I2COA12 (0x0004) /* I2C own address */\r
+#define I2COA13 (0x0008) /* I2C own address */\r
+#define I2COA14 (0x0010) /* I2C own address */\r
+#define I2COA15 (0x0020) /* I2C own address */\r
+#define I2COA16 (0x0040) /* I2C own address */\r
+#define I2COA17 (0x0080) /* I2C own address */\r
+#define I2COA18 (0x0100) /* I2C own address */\r
+#define I2COA19 (0x0200) /* I2C own address */\r
+\r
+/* UCB0I2COA2 Control Bits */\r
+#define I2COA2 (0x03ff) /* I2C own address */\r
+#define I2COA20 (0x0001) /* I2C own address */\r
+#define I2COA21 (0x0002) /* I2C own address */\r
+#define I2COA22 (0x0004) /* I2C own address */\r
+#define I2COA23 (0x0008) /* I2C own address */\r
+#define I2COA24 (0x0010) /* I2C own address */\r
+#define I2COA25 (0x0020) /* I2C own address */\r
+#define I2COA26 (0x0040) /* I2C own address */\r
+#define I2COA27 (0x0080) /* I2C own address */\r
+#define I2COA28 (0x0100) /* I2C own address */\r
+#define I2COA29 (0x0200) /* I2C own address */\r
+\r
+/* UCB0I2COA3 Control Bits */\r
+#define I2COA3 (0x03ff) /* I2C own address */\r
+#define I2COA30 (0x0001) /* I2C own address */\r
+#define I2COA31 (0x0002) /* I2C own address */\r
+#define I2COA32 (0x0004) /* I2C own address */\r
+#define I2COA33 (0x0008) /* I2C own address */\r
+#define I2COA34 (0x0010) /* I2C own address */\r
+#define I2COA35 (0x0020) /* I2C own address */\r
+#define I2COA36 (0x0040) /* I2C own address */\r
+#define I2COA37 (0x0080) /* I2C own address */\r
+#define I2COA38 (0x0100) /* I2C own address */\r
+#define I2COA39 (0x0200) /* I2C own address */\r
+\r
+/* UCB0ADDRX Control Bits */\r
+#define ADDRX (0x03ff) /* Received Address Register */\r
+#define ADDRX0 (0x0001) /* Received Address Register */\r
+#define ADDRX1 (0x0002) /* Received Address Register */\r
+#define ADDRX2 (0x0004) /* Received Address Register */\r
+#define ADDRX3 (0x0008) /* Received Address Register */\r
+#define ADDRX4 (0x0010) /* Received Address Register */\r
+#define ADDRX5 (0x0020) /* Received Address Register */\r
+#define ADDRX6 (0x0040) /* Received Address Register */\r
+#define ADDRX7 (0x0080) /* Received Address Register */\r
+#define ADDRX8 (0x0100) /* Received Address Register */\r
+#define ADDRX9 (0x0200) /* Received Address Register */\r
+\r
+/* UCB0ADDMASK Control Bits */\r
+#define ADDMASK (0x03ff) /* */\r
+#define ADDMASK0 (0x0001) /* */\r
+#define ADDMASK1 (0x0002) /* */\r
+#define ADDMASK2 (0x0004) /* */\r
+#define ADDMASK3 (0x0008) /* */\r
+#define ADDMASK4 (0x0010) /* */\r
+#define ADDMASK5 (0x0020) /* */\r
+#define ADDMASK6 (0x0040) /* */\r
+#define ADDMASK7 (0x0080) /* */\r
+#define ADDMASK8 (0x0100) /* */\r
+#define ADDMASK9 (0x0200) /* */\r
+\r
+/* UCB0I2CSA Control Bits */\r
+#define I2CSA (0x03ff) /* I2C slave address */\r
+#define I2CSA0 (0x0001) /* I2C slave address */\r
+#define I2CSA1 (0x0002) /* I2C slave address */\r
+#define I2CSA2 (0x0004) /* I2C slave address */\r
+#define I2CSA3 (0x0008) /* I2C slave address */\r
+#define I2CSA4 (0x0010) /* I2C slave address */\r
+#define I2CSA5 (0x0020) /* I2C slave address */\r
+#define I2CSA6 (0x0040) /* I2C slave address */\r
+#define I2CSA7 (0x0080) /* I2C slave address */\r
+#define I2CSA8 (0x0100) /* I2C slave address */\r
+#define I2CSA9 (0x0200) /* I2C slave address */\r
+\r
+/* UCB0IE Control Bits */\r
+#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */\r
+#define UCRXIE0_0 (0x0000) /* Interrupt disabled */\r
+#define UCRXIE0_1 (0x0001) /* Interrupt enabled */\r
+#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */\r
+#define UCTXIE0_0 (0x0000) /* Interrupt disabled */\r
+#define UCTXIE0_1 (0x0002) /* Interrupt enabled */\r
+#define UCSTPIE (0x0008) /* STOP condition interrupt enable */\r
+#define UCSTPIE_0 (0x0000) /* Interrupt disabled */\r
+#define UCSTPIE_1 (0x0008) /* Interrupt enabled */\r
+#define UCALIE (0x0010) /* Arbitration lost interrupt enable */\r
+#define UCALIE_0 (0x0000) /* Interrupt disabled */\r
+#define UCALIE_1 (0x0010) /* Interrupt enabled */\r
+#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */\r
+#define UCNACKIE_0 (0x0000) /* Interrupt disabled */\r
+#define UCNACKIE_1 (0x0020) /* Interrupt enabled */\r
+#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */\r
+#define UCBCNTIE_0 (0x0000) /* Interrupt disabled */\r
+#define UCBCNTIE_1 (0x0040) /* Interrupt enabled */\r
+#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */\r
+#define UCCLTOIE_0 (0x0000) /* Interrupt disabled */\r
+#define UCCLTOIE_1 (0x0080) /* Interrupt enabled */\r
+#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */\r
+#define UCRXIE1_0 (0x0000) /* Interrupt disabled */\r
+#define UCRXIE1_1 (0x0100) /* Interrupt enabled */\r
+#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */\r
+#define UCTXIE1_0 (0x0000) /* Interrupt disabled */\r
+#define UCTXIE1_1 (0x0200) /* Interrupt enabled */\r
+#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */\r
+#define UCRXIE2_0 (0x0000) /* Interrupt disabled */\r
+#define UCRXIE2_1 (0x0400) /* Interrupt enabled */\r
+#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */\r
+#define UCTXIE2_0 (0x0000) /* Interrupt disabled */\r
+#define UCTXIE2_1 (0x0800) /* Interrupt enabled */\r
+#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */\r
+#define UCRXIE3_0 (0x0000) /* Interrupt disabled */\r
+#define UCRXIE3_1 (0x1000) /* Interrupt enabled */\r
+#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */\r
+#define UCTXIE3_0 (0x0000) /* Interrupt disabled */\r
+#define UCTXIE3_1 (0x2000) /* Interrupt enabled */\r
+#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */\r
+#define UCBIT9IE_0 (0x0000) /* Interrupt disabled */\r
+#define UCBIT9IE_1 (0x4000) /* Interrupt enabled */\r
+\r
+/* UCB0IFG Control Bits */\r
+#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */\r
+#define UCRXIFG0_0 (0x0000) /* No interrupt pending */\r
+#define UCRXIFG0_1 (0x0001) /* Interrupt pending */\r
+#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */\r
+#define UCTXIFG0_0 (0x0000) /* No interrupt pending */\r
+#define UCTXIFG0_1 (0x0002) /* Interrupt pending */\r
+#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */\r
+#define UCSTPIFG_0 (0x0000) /* No interrupt pending */\r
+#define UCSTPIFG_1 (0x0008) /* Interrupt pending */\r
+#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */\r
+#define UCALIFG_0 (0x0000) /* No interrupt pending */\r
+#define UCALIFG_1 (0x0010) /* Interrupt pending */\r
+#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */\r
+#define UCNACKIFG_0 (0x0000) /* No interrupt pending */\r
+#define UCNACKIFG_1 (0x0020) /* Interrupt pending */\r
+#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */\r
+#define UCBCNTIFG_0 (0x0000) /* No interrupt pending */\r
+#define UCBCNTIFG_1 (0x0040) /* Interrupt pending */\r
+#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */\r
+#define UCCLTOIFG_0 (0x0000) /* No interrupt pending */\r
+#define UCCLTOIFG_1 (0x0080) /* Interrupt pending */\r
+#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */\r
+#define UCRXIFG1_0 (0x0000) /* No interrupt pending */\r
+#define UCRXIFG1_1 (0x0100) /* Interrupt pending */\r
+#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */\r
+#define UCTXIFG1_0 (0x0000) /* No interrupt pending */\r
+#define UCTXIFG1_1 (0x0200) /* Interrupt pending */\r
+#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */\r
+#define UCRXIFG2_0 (0x0000) /* No interrupt pending */\r
+#define UCRXIFG2_1 (0x0400) /* Interrupt pending */\r
+#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */\r
+#define UCTXIFG2_0 (0x0000) /* No interrupt pending */\r
+#define UCTXIFG2_1 (0x0800) /* Interrupt pending */\r
+#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */\r
+#define UCRXIFG3_0 (0x0000) /* No interrupt pending */\r
+#define UCRXIFG3_1 (0x1000) /* Interrupt pending */\r
+#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */\r
+#define UCTXIFG3_0 (0x0000) /* No interrupt pending */\r
+#define UCTXIFG3_1 (0x2000) /* Interrupt pending */\r
+#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */\r
+#define UCBIT9IFG_0 (0x0000) /* No interrupt pending */\r
+#define UCBIT9IFG_1 (0x4000) /* Interrupt pending */\r
+\r
+#define UCIV__UCALIFG (0x0002) /* Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; \r
+ Interrupt Priority: Highest */\r
+#define UCIV__UCNACKIFG (0x0004) /* Interrupt Source: Not acknowledgment; Interrupt Flag: \r
+ UCNACKIFG */\r
+#define UCIV__UCSTPIFG (0x0008) /* Interrupt Source: Stop condition received; Interrupt Flag: \r
+ UCSTPIFG */\r
+#define UCIV__UCRXIFG3 (0x000a) /* Interrupt Source: Slave 3 Data received; Interrupt Flag: \r
+ UCRXIFG3 */\r
+#define UCIV__UCTXIFG3 (0x000c) /* Interrupt Source: Slave 3 Transmit buffer empty; Interrupt \r
+ Flag: UCTXIFG3 */\r
+#define UCIV__UCRXIFG2 (0x000e) /* Interrupt Source: Slave 2 Data received; Interrupt Flag: \r
+ UCRXIFG2 */\r
+#define UCIV__UCTXIFG2 (0x0010) /* Interrupt Source: Slave 2 Transmit buffer empty; Interrupt \r
+ Flag: UCTXIFG2 */\r
+#define UCIV__UCRXIFG1 (0x0012) /* Interrupt Source: Slave 1 Data received; Interrupt Flag: \r
+ UCRXIFG1 */\r
+#define UCIV__UCTXIFG1 (0x0014) /* Interrupt Source: Slave 1 Transmit buffer empty; Interrupt \r
+ Flag: UCTXIFG1 */\r
+#define UCIV__UCRXIFG0 (0x0016) /* Interrupt Source: Data received; Interrupt Flag: UCRXIFG0 */\r
+#define UCIV__UCTXIFG0 (0x0018) /* Interrupt Source: Transmit buffer empty; Interrupt Flag: \r
+ UCTXIFG0 */\r
+#define UCIV__UCBCNTIFG (0x001a) /* Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG */\r
+#define UCIV__UCCLTOIFG (0x001c) /* Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG */\r
+#define UCIV__UCBIT9IFG (0x001e) /* Interrupt Source: Nineth bit position; Interrupt Flag: \r
+ UCBIT9IFG; Priority: Lowest */\r
+\r
+\r
+/*****************************************************************************\r
+ eUSCI_B1 Registers\r
+*****************************************************************************/\r
+\r
+#define __MSP430_HAS_EUSCI_B1__ /* Definition to show that module is available */\r
+#ifndef __MSP430_HAS_EUSCI_Bx__\r
+#define __MSP430_HAS_EUSCI_Bx__\r
+#endif\r
+#define __MSP430_BASEADDRESS_EUSCI_B1__ 0x0580\r
+#define EUSCI_B1_BASE __MSP430_BASEADDRESS_EUSCI_B1__\r
+\r
+sfr_w(UCB1CTLW0); /* eUSCI_Bx Control Word Register 0 */\r
+sfr_b(UCB1CTLW0_L);\r
+sfr_b(UCB1CTLW0_H);\r
+sfr_w(UCB1CTLW1); /* eUSCI_Bx Control Word Register 1 */\r
+sfr_b(UCB1CTLW1_L);\r
+sfr_b(UCB1CTLW1_H);\r
+sfr_w(UCB1BRW); /* eUSCI_Bx Baud Rate Control Word Register */\r
+sfr_b(UCB1BRW_L);\r
+sfr_b(UCB1BRW_H);\r
+sfr_w(UCB1STATW); /* eUSCI_Bx Status Register */\r
+sfr_b(UCB1STATW_L);\r
+sfr_b(UCB1STATW_H);\r
+sfr_w(UCB1TBCNT); /* eUSCI_Bx Byte Counter Threshold Register */\r
+sfr_b(UCB1TBCNT_L);\r
+sfr_b(UCB1TBCNT_H);\r
+sfr_w(UCB1RXBUF); /* eUSCI_Bx Receive Buffer Register */\r
+sfr_b(UCB1RXBUF_L);\r
+sfr_b(UCB1RXBUF_H);\r
+sfr_w(UCB1TXBUF); /* eUSCI_Bx Transmit Buffer Register */\r
+sfr_b(UCB1TXBUF_L);\r
+sfr_b(UCB1TXBUF_H);\r
+sfr_w(UCB1I2COA0); /* eUSCI_Bx I2C Own Address 0 Register */\r
+sfr_b(UCB1I2COA0_L);\r
+sfr_b(UCB1I2COA0_H);\r
+sfr_w(UCB1I2COA1); /* eUSCI_Bx I2C Own Address 1 Register */\r
+sfr_b(UCB1I2COA1_L);\r
+sfr_b(UCB1I2COA1_H);\r
+sfr_w(UCB1I2COA2); /* eUSCI_Bx I2C Own Address 2 Register */\r
+sfr_b(UCB1I2COA2_L);\r
+sfr_b(UCB1I2COA2_H);\r
+sfr_w(UCB1I2COA3); /* eUSCI_Bx I2C Own Address 3 Register */\r
+sfr_b(UCB1I2COA3_L);\r
+sfr_b(UCB1I2COA3_H);\r
+sfr_w(UCB1ADDRX); /* eUSCI_Bx I2C Received Address Register */\r
+sfr_b(UCB1ADDRX_L);\r
+sfr_b(UCB1ADDRX_H);\r
+sfr_w(UCB1ADDMASK); /* eUSCI_Bx I2C Address Mask Register */\r
+sfr_b(UCB1ADDMASK_L);\r
+sfr_b(UCB1ADDMASK_H);\r
+sfr_w(UCB1I2CSA); /* eUSCI_Bx I2C Slave Address Register */\r
+sfr_b(UCB1I2CSA_L);\r
+sfr_b(UCB1I2CSA_H);\r
+sfr_w(UCB1IE); /* eUSCI_Bx Interrupt Enable Register */\r
+sfr_b(UCB1IE_L);\r
+sfr_b(UCB1IE_H);\r
+sfr_w(UCB1IFG); /* eUSCI_Bx Interrupt Flag Register */\r
+sfr_b(UCB1IFG_L);\r
+sfr_b(UCB1IFG_H);\r
+sfr_w(UCB1IV); /* eUSCI_Bx Interrupt Vector Register */\r
+sfr_b(UCB1IV_L);\r
+sfr_b(UCB1IV_H);\r
+\r
+/* eUSCI_B1 Register Offsets */\r
+#define OFS_UCB1CTLW0 (0x0000)\r
+#define OFS_UCB1CTLW1 (0x0002)\r
+#define OFS_UCB1BRW (0x0006)\r
+#define OFS_UCB1STATW (0x0008)\r
+#define OFS_UCB1TBCNT (0x000A)\r
+#define OFS_UCB1RXBUF (0x000C)\r
+#define OFS_UCB1TXBUF (0x000E)\r
+#define OFS_UCB1I2COA0 (0x0014)\r
+#define OFS_UCB1I2COA1 (0x0016)\r
+#define OFS_UCB1I2COA2 (0x0018)\r
+#define OFS_UCB1I2COA3 (0x001A)\r
+#define OFS_UCB1ADDRX (0x001C)\r
+#define OFS_UCB1ADDMASK (0x001E)\r
+#define OFS_UCB1I2CSA (0x0020)\r
+#define OFS_UCB1IE (0x002A)\r
+#define OFS_UCB1IFG (0x002C)\r
+#define OFS_UCB1IV (0x002E)\r
+\r
+/* No control bits available or already defined for another module */\r
+\r
+/************************************************************\r
+* TLV Descriptors\r
+************************************************************/\r
+\r
+#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */\r
+\r
+#define TLV_CRC_LENGTH (0x1A01) /* CRC length of the TLV structure */\r
+#define TLV_CRC_VALUE (0x1A02) /* CRC value of the TLV structure */\r
+#define TLV_START (0x1A08) /* Start Address of the TLV structure */\r
+#define TLV_END (0x1AFF) /* End Address of the TLV structure */\r
+#define TLV_CRC_START (0x1A04) /* Start Address of the CRC protected structure */\r
+#define TLV_CRC_END (0x1A77) /* End Address of the TLV protected structure */\r
+\r
+#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */\r
+#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */\r
+#define TLV_Reserved3 (0x03) /* Reserved for future use */\r
+#define TLV_Reserved4 (0x04) /* Reserved for future use */\r
+#define TLV_BLANK (0x05) /* Blank descriptor */\r
+#define TLV_Reserved6 (0x06) /* Reserved for future use */\r
+#define TLV_Reserved7 (0x07) /* Reserved for future use */\r
+#define TLV_DIERECORD (0x08) /* Unique Die Record */\r
+#define TLV_ADCCAL (0x11) /* ADC calibration */\r
+#define TLV_ADC12CAL (0x11) /* ADC12 calibration */\r
+#define TLV_ADC10CAL (0x13) /* ADC10 calibration */\r
+#define TLV_REFCAL (0x12) /* REF calibration */\r
+#define TLV_TAGEXT (0xFE) /* Tag extender */\r
+#define TLV_TAGEND (0xFF) /* Tag End of Table */\r
+\r
+/************************************************************\r
+* Interrupt Vectors (offset from 0xFF80 + 0x10 for Password)\r
+************************************************************/\r
+\r
+#define ECOMP0_VECTOR (20) /* 0xFFCA */\r
+#define PORT6_VECTOR (21) /* 0xFFCC */\r
+#define PORT5_VECTOR (22) /* 0xFFCE */\r
+#define PORT4_VECTOR (23) /* 0xFFD0 */\r
+#define PORT3_VECTOR (24) /* 0xFFD2 */\r
+#define PORT2_VECTOR (25) /* 0xFFD4 */\r
+#define PORT1_VECTOR (26) /* 0xFFD6 */\r
+#define ADC_VECTOR (27) /* 0xFFD8 */\r
+#define EUSCI_B1_VECTOR (28) /* 0xFFDA */\r
+#define EUSCI_B0_VECTOR (29) /* 0xFFDC */\r
+#define EUSCI_A1_VECTOR (30) /* 0xFFDE */\r
+#define EUSCI_A0_VECTOR (31) /* 0xFFE0 */\r
+#define WDT_VECTOR (32) /* 0xFFE2 */\r
+#define RTC_VECTOR (33) /* 0xFFE4 */\r
+#define TIMER0_B1_VECTOR (34) /* 0xFFE6 */\r
+#define TIMER0_B0_VECTOR (35) /* 0xFFE8 */\r
+#define TIMER3_A1_VECTOR (36) /* 0xFFEA */\r
+#define TIMER3_A0_VECTOR (37) /* 0xFFEC */\r
+#define TIMER2_A1_VECTOR (38) /* 0xFFEE */\r
+#define TIMER2_A0_VECTOR (39) /* 0xFFF0 */\r
+#define TIMER1_A1_VECTOR (40) /* 0xFFF2 */\r
+#define TIMER1_A0_VECTOR (41) /* 0xFFF4 */\r
+#define TIMER0_A1_VECTOR (42) /* 0xFFF6 */\r
+#define TIMER0_A0_VECTOR (43) /* 0xFFF8 */\r
+#define UNMI_VECTOR (44) /* 0xFFFA */\r
+#define SYSNMI_VECTOR (45) /* 0xFFFC */\r
+#define RESET_VECTOR ("reset") /* 0xFFFE Reset (Highest Priority) */\r
+\r
+\r
+/************************************************************\r
+* Memory Boundary Definitions\r
+************************************************************/\r
+\r
+#define TINYRAM_START 0x0006\r
+#define TINYRAM_LENGTH 0x001A\r
+#define BSL0_START 0x1000\r
+#define BSL0_LENGTH 0x0800\r
+#define INFO_START 0x1800\r
+#define INFO_LENGTH 0x0200\r
+#define TLVMEM_START 0x1A00\r
+#define TLVMEM_LENGTH 0x0200\r
+#define BOOTCODE_START 0x1C00\r
+#define BOOTCODE_LENGTH 0x0400\r
+#define RAM_START 0x2000\r
+#define RAM_LENGTH 0x2000\r
+#define FRAM_START 0x8000\r
+#define FRAM_LENGTH 0x10000\r
+#define ROMLIB_START 0xC0000\r
+#define ROMLIB_LENGTH 0x4000\r
+#define BSL1_START 0xFFC00\r
+#define BSL1_LENGTH 0x0400\r
+\r
+/************************************************************\r
+* End of Modules\r
+************************************************************/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* extern "C" */\r
+\r
+#ifndef EXCLUDE_LEGACY\r
+#include "legacy.h"\r
+#endif\r
+\r
+#endif /* #ifndef __MSP430FR2476 */\r
+\r
+\r
--- /dev/null
+/* ============================================================================ */\r
+/* Copyright (c) 2021, Texas Instruments Incorporated */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following conditions */\r
+/* are met: */\r
+/* */\r
+/* * Redistributions of source code must retain the above copyright */\r
+/* notice, this list of conditions and the following disclaimer. */\r
+/* */\r
+/* * Redistributions in binary form must reproduce the above copyright */\r
+/* notice, this list of conditions and the following disclaimer in the */\r
+/* documentation and/or other materials provided with the distribution. */\r
+/* */\r
+/* * Neither the name of Texas Instruments Incorporated nor the names of */\r
+/* its contributors may be used to endorse or promote products derived */\r
+/* from this software without specific prior written permission. */\r
+/* */\r
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */\r
+/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */\r
+/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */\r
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */\r
+/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */\r
+/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */\r
+/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */\r
+/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */\r
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */\r
+/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ============================================================================ */\r
+\r
+/* This file supports MSP430FR2476 devices. */\r
+\r
+/* 1.212 */\r
+\r
+/************************************************************\r
+* PERIPHERAL FILE MAP\r
+************************************************************/\r
+\r
+\r
+/*****************************************************************************\r
+ ADC\r
+*****************************************************************************/\r
+PROVIDE(ADCCTL0 = 0x0700);\r
+PROVIDE(ADCCTL0_L = 0x0700);\r
+PROVIDE(ADCCTL0_H = 0x0701);\r
+PROVIDE(ADCCTL1 = 0x0702);\r
+PROVIDE(ADCCTL1_L = 0x0702);\r
+PROVIDE(ADCCTL1_H = 0x0703);\r
+PROVIDE(ADCCTL2 = 0x0704);\r
+PROVIDE(ADCCTL2_L = 0x0704);\r
+PROVIDE(ADCCTL2_H = 0x0705);\r
+PROVIDE(ADCLO = 0x0706);\r
+PROVIDE(ADCLO_L = 0x0706);\r
+PROVIDE(ADCLO_H = 0x0707);\r
+PROVIDE(ADCHI = 0x0708);\r
+PROVIDE(ADCHI_L = 0x0708);\r
+PROVIDE(ADCHI_H = 0x0709);\r
+PROVIDE(ADCMCTL0 = 0x070A);\r
+PROVIDE(ADCMCTL0_L = 0x070A);\r
+PROVIDE(ADCMCTL0_H = 0x070B);\r
+PROVIDE(ADCMEM0 = 0x0712);\r
+PROVIDE(ADCMEM0_L = 0x0712);\r
+PROVIDE(ADCMEM0_H = 0x0713);\r
+PROVIDE(ADCIE = 0x071A);\r
+PROVIDE(ADCIE_L = 0x071A);\r
+PROVIDE(ADCIE_H = 0x071B);\r
+PROVIDE(ADCIFG = 0x071C);\r
+PROVIDE(ADCIFG_L = 0x071C);\r
+PROVIDE(ADCIFG_H = 0x071D);\r
+PROVIDE(ADCIV = 0x071E);\r
+PROVIDE(ADCIV_L = 0x071E);\r
+PROVIDE(ADCIV_H = 0x071F);\r
+\r
+\r
+/*****************************************************************************\r
+ BKMEM\r
+*****************************************************************************/\r
+PROVIDE(BAKMEM0 = 0x0660);\r
+PROVIDE(BAKMEM0_L = 0x0660);\r
+PROVIDE(BAKMEM0_H = 0x0661);\r
+PROVIDE(BAKMEM1 = 0x0662);\r
+PROVIDE(BAKMEM1_L = 0x0662);\r
+PROVIDE(BAKMEM1_H = 0x0663);\r
+PROVIDE(BAKMEM2 = 0x0664);\r
+PROVIDE(BAKMEM2_L = 0x0664);\r
+PROVIDE(BAKMEM2_H = 0x0665);\r
+PROVIDE(BAKMEM3 = 0x0666);\r
+PROVIDE(BAKMEM3_L = 0x0666);\r
+PROVIDE(BAKMEM3_H = 0x0667);\r
+PROVIDE(BAKMEM4 = 0x0668);\r
+PROVIDE(BAKMEM4_L = 0x0668);\r
+PROVIDE(BAKMEM4_H = 0x0669);\r
+PROVIDE(BAKMEM5 = 0x066A);\r
+PROVIDE(BAKMEM5_L = 0x066A);\r
+PROVIDE(BAKMEM5_H = 0x066B);\r
+PROVIDE(BAKMEM6 = 0x066C);\r
+PROVIDE(BAKMEM6_L = 0x066C);\r
+PROVIDE(BAKMEM6_H = 0x066D);\r
+PROVIDE(BAKMEM7 = 0x066E);\r
+PROVIDE(BAKMEM7_L = 0x066E);\r
+PROVIDE(BAKMEM7_H = 0x066F);\r
+PROVIDE(BAKMEM8 = 0x0670);\r
+PROVIDE(BAKMEM8_L = 0x0670);\r
+PROVIDE(BAKMEM8_H = 0x0671);\r
+PROVIDE(BAKMEM9 = 0x0672);\r
+PROVIDE(BAKMEM9_L = 0x0672);\r
+PROVIDE(BAKMEM9_H = 0x0673);\r
+PROVIDE(BAKMEM10 = 0x0674);\r
+PROVIDE(BAKMEM10_L = 0x0674);\r
+PROVIDE(BAKMEM10_H = 0x0675);\r
+PROVIDE(BAKMEM11 = 0x0676);\r
+PROVIDE(BAKMEM11_L = 0x0676);\r
+PROVIDE(BAKMEM11_H = 0x0677);\r
+PROVIDE(BAKMEM12 = 0x0678);\r
+PROVIDE(BAKMEM12_L = 0x0678);\r
+PROVIDE(BAKMEM12_H = 0x0679);\r
+PROVIDE(BAKMEM13 = 0x067A);\r
+PROVIDE(BAKMEM13_L = 0x067A);\r
+PROVIDE(BAKMEM13_H = 0x067B);\r
+PROVIDE(BAKMEM14 = 0x067C);\r
+PROVIDE(BAKMEM14_L = 0x067C);\r
+PROVIDE(BAKMEM14_H = 0x067D);\r
+PROVIDE(BAKMEM15 = 0x067E);\r
+PROVIDE(BAKMEM15_L = 0x067E);\r
+PROVIDE(BAKMEM15_H = 0x067F);\r
+\r
+\r
+/*****************************************************************************\r
+ CRC\r
+*****************************************************************************/\r
+PROVIDE(CRCDI = 0x01C0);\r
+PROVIDE(CRCDI_L = 0x01C0);\r
+PROVIDE(CRCDI_H = 0x01C1);\r
+PROVIDE(CRCDIRB = 0x01C2);\r
+PROVIDE(CRCDIRB_L = 0x01C2);\r
+PROVIDE(CRCDIRB_H = 0x01C3);\r
+PROVIDE(CRCINIRES = 0x01C4);\r
+PROVIDE(CRCINIRES_L = 0x01C4);\r
+PROVIDE(CRCINIRES_H = 0x01C5);\r
+PROVIDE(CRCRESR = 0x01C6);\r
+PROVIDE(CRCRESR_L = 0x01C6);\r
+PROVIDE(CRCRESR_H = 0x01C7);\r
+\r
+\r
+/*****************************************************************************\r
+ CS\r
+*****************************************************************************/\r
+PROVIDE(CSCTL0 = 0x0180);\r
+PROVIDE(CSCTL0_L = 0x0180);\r
+PROVIDE(CSCTL0_H = 0x0181);\r
+PROVIDE(CSCTL1 = 0x0182);\r
+PROVIDE(CSCTL1_L = 0x0182);\r
+PROVIDE(CSCTL1_H = 0x0183);\r
+PROVIDE(CSCTL2 = 0x0184);\r
+PROVIDE(CSCTL2_L = 0x0184);\r
+PROVIDE(CSCTL2_H = 0x0185);\r
+PROVIDE(CSCTL3 = 0x0186);\r
+PROVIDE(CSCTL3_L = 0x0186);\r
+PROVIDE(CSCTL3_H = 0x0187);\r
+PROVIDE(CSCTL4 = 0x0188);\r
+PROVIDE(CSCTL4_L = 0x0188);\r
+PROVIDE(CSCTL4_H = 0x0189);\r
+PROVIDE(CSCTL5 = 0x018A);\r
+PROVIDE(CSCTL5_L = 0x018A);\r
+PROVIDE(CSCTL5_H = 0x018B);\r
+PROVIDE(CSCTL6 = 0x018C);\r
+PROVIDE(CSCTL6_L = 0x018C);\r
+PROVIDE(CSCTL6_H = 0x018D);\r
+PROVIDE(CSCTL7 = 0x018E);\r
+PROVIDE(CSCTL7_L = 0x018E);\r
+PROVIDE(CSCTL7_H = 0x018F);\r
+PROVIDE(CSCTL8 = 0x0190);\r
+PROVIDE(CSCTL8_L = 0x0190);\r
+PROVIDE(CSCTL8_H = 0x0191);\r
+\r
+\r
+/*****************************************************************************\r
+ DIO\r
+*****************************************************************************/\r
+PROVIDE(PAIN = 0x0200);\r
+PROVIDE(PAIN_L = 0x0200);\r
+PROVIDE(PAIN_H = 0x0201);\r
+PROVIDE(PAOUT = 0x0202);\r
+PROVIDE(PAOUT_L = 0x0202);\r
+PROVIDE(PAOUT_H = 0x0203);\r
+PROVIDE(PADIR = 0x0204);\r
+PROVIDE(PADIR_L = 0x0204);\r
+PROVIDE(PADIR_H = 0x0205);\r
+PROVIDE(PAREN = 0x0206);\r
+PROVIDE(PAREN_L = 0x0206);\r
+PROVIDE(PAREN_H = 0x0207);\r
+PROVIDE(PASEL0 = 0x020A);\r
+PROVIDE(PASEL0_L = 0x020A);\r
+PROVIDE(PASEL0_H = 0x020B);\r
+PROVIDE(PASEL1 = 0x020C);\r
+PROVIDE(PASEL1_L = 0x020C);\r
+PROVIDE(PASEL1_H = 0x020D);\r
+PROVIDE(P1IV = 0x020E);\r
+PROVIDE(P1IV_L = 0x020E);\r
+PROVIDE(P1IV_H = 0x020F);\r
+PROVIDE(PASELC = 0x0216);\r
+PROVIDE(PASELC_L = 0x0216);\r
+PROVIDE(PASELC_H = 0x0217);\r
+PROVIDE(PAIES = 0x0218);\r
+PROVIDE(PAIES_L = 0x0218);\r
+PROVIDE(PAIES_H = 0x0219);\r
+PROVIDE(PAIE = 0x021A);\r
+PROVIDE(PAIE_L = 0x021A);\r
+PROVIDE(PAIE_H = 0x021B);\r
+PROVIDE(PAIFG = 0x021C);\r
+PROVIDE(PAIFG_L = 0x021C);\r
+PROVIDE(PAIFG_H = 0x021D);\r
+PROVIDE(P2IV = 0x021E);\r
+PROVIDE(P2IV_L = 0x021E);\r
+PROVIDE(P2IV_H = 0x021F);\r
+PROVIDE(PBIN = 0x0220);\r
+PROVIDE(PBIN_L = 0x0220);\r
+PROVIDE(PBIN_H = 0x0221);\r
+PROVIDE(PBOUT = 0x0222);\r
+PROVIDE(PBOUT_L = 0x0222);\r
+PROVIDE(PBOUT_H = 0x0223);\r
+PROVIDE(PBDIR = 0x0224);\r
+PROVIDE(PBDIR_L = 0x0224);\r
+PROVIDE(PBDIR_H = 0x0225);\r
+PROVIDE(PBREN = 0x0226);\r
+PROVIDE(PBREN_L = 0x0226);\r
+PROVIDE(PBREN_H = 0x0227);\r
+PROVIDE(PBSEL0 = 0x022A);\r
+PROVIDE(PBSEL0_L = 0x022A);\r
+PROVIDE(PBSEL0_H = 0x022B);\r
+PROVIDE(PBSEL1 = 0x022C);\r
+PROVIDE(PBSEL1_L = 0x022C);\r
+PROVIDE(PBSEL1_H = 0x022D);\r
+PROVIDE(P3IV = 0x022E);\r
+PROVIDE(P3IV_L = 0x022E);\r
+PROVIDE(P3IV_H = 0x022F);\r
+PROVIDE(PBSELC = 0x0236);\r
+PROVIDE(PBSELC_L = 0x0236);\r
+PROVIDE(PBSELC_H = 0x0237);\r
+PROVIDE(PBIES = 0x0238);\r
+PROVIDE(PBIES_L = 0x0238);\r
+PROVIDE(PBIES_H = 0x0239);\r
+PROVIDE(PBIE = 0x023A);\r
+PROVIDE(PBIE_L = 0x023A);\r
+PROVIDE(PBIE_H = 0x023B);\r
+PROVIDE(PBIFG = 0x023C);\r
+PROVIDE(PBIFG_L = 0x023C);\r
+PROVIDE(PBIFG_H = 0x023D);\r
+PROVIDE(P4IV = 0x023E);\r
+PROVIDE(P4IV_L = 0x023E);\r
+PROVIDE(P4IV_H = 0x023F);\r
+PROVIDE(PCIN = 0x0240);\r
+PROVIDE(PCIN_L = 0x0240);\r
+PROVIDE(PCIN_H = 0x0241);\r
+PROVIDE(PCOUT = 0x0242);\r
+PROVIDE(PCOUT_L = 0x0242);\r
+PROVIDE(PCOUT_H = 0x0243);\r
+PROVIDE(PCDIR = 0x0244);\r
+PROVIDE(PCDIR_L = 0x0244);\r
+PROVIDE(PCDIR_H = 0x0245);\r
+PROVIDE(PCREN = 0x0246);\r
+PROVIDE(PCREN_L = 0x0246);\r
+PROVIDE(PCREN_H = 0x0247);\r
+PROVIDE(PCSEL0 = 0x024A);\r
+PROVIDE(PCSEL0_L = 0x024A);\r
+PROVIDE(PCSEL0_H = 0x024B);\r
+PROVIDE(PCSEL1 = 0x024C);\r
+PROVIDE(PCSEL1_L = 0x024C);\r
+PROVIDE(PCSEL1_H = 0x024D);\r
+PROVIDE(P5IV = 0x024E);\r
+PROVIDE(P5IV_L = 0x024E);\r
+PROVIDE(P5IV_H = 0x024F);\r
+PROVIDE(PCSELC = 0x0256);\r
+PROVIDE(PCSELC_L = 0x0256);\r
+PROVIDE(PCSELC_H = 0x0257);\r
+PROVIDE(PCIES = 0x0258);\r
+PROVIDE(PCIES_L = 0x0258);\r
+PROVIDE(PCIES_H = 0x0259);\r
+PROVIDE(PCIE = 0x025A);\r
+PROVIDE(PCIE_L = 0x025A);\r
+PROVIDE(PCIE_H = 0x025B);\r
+PROVIDE(PCIFG = 0x025C);\r
+PROVIDE(PCIFG_L = 0x025C);\r
+PROVIDE(PCIFG_H = 0x025D);\r
+PROVIDE(P6IV = 0x025E);\r
+PROVIDE(P6IV_L = 0x025E);\r
+PROVIDE(P6IV_H = 0x025F);\r
+PROVIDE(PJIN = 0x0320);\r
+PROVIDE(PJIN_L = 0x0320);\r
+PROVIDE(PJIN_H = 0x0321);\r
+PROVIDE(PJOUT = 0x0322);\r
+PROVIDE(PJOUT_L = 0x0322);\r
+PROVIDE(PJOUT_H = 0x0323);\r
+PROVIDE(PJDIR = 0x0324);\r
+PROVIDE(PJDIR_L = 0x0324);\r
+PROVIDE(PJDIR_H = 0x0325);\r
+PROVIDE(PJREN = 0x0326);\r
+PROVIDE(PJREN_L = 0x0326);\r
+PROVIDE(PJREN_H = 0x0327);\r
+PROVIDE(PJSEL0 = 0x032A);\r
+PROVIDE(PJSEL0_L = 0x032A);\r
+PROVIDE(PJSEL0_H = 0x032B);\r
+PROVIDE(PJSEL1 = 0x032C);\r
+PROVIDE(PJSEL1_L = 0x032C);\r
+PROVIDE(PJSEL1_H = 0x032D);\r
+PROVIDE(PJSELC = 0x0336);\r
+PROVIDE(PJSELC_L = 0x0336);\r
+PROVIDE(PJSELC_H = 0x0337);\r
+PROVIDE(P1IN = 0x0200);\r
+\r
+PROVIDE(P2IN = 0x0201);\r
+\r
+PROVIDE(P2OUT = 0x0203);\r
+\r
+PROVIDE(P1OUT = 0x0202);\r
+\r
+PROVIDE(P1DIR = 0x0204);\r
+\r
+PROVIDE(P2DIR = 0x0205);\r
+\r
+PROVIDE(P1REN = 0x0206);\r
+\r
+PROVIDE(P2REN = 0x0207);\r
+\r
+PROVIDE(P1SEL0 = 0x020A);\r
+\r
+PROVIDE(P2SEL0 = 0x020B);\r
+\r
+PROVIDE(P1SEL1 = 0x020C);\r
+\r
+PROVIDE(P2SEL1 = 0x020D);\r
+\r
+PROVIDE(P1SELC = 0x0216);\r
+\r
+PROVIDE(P2SELC = 0x0217);\r
+\r
+PROVIDE(P1IES = 0x0218);\r
+\r
+PROVIDE(P2IES = 0x0219);\r
+\r
+PROVIDE(P1IE = 0x021A);\r
+\r
+PROVIDE(P2IE = 0x021B);\r
+\r
+PROVIDE(P1IFG = 0x021C);\r
+\r
+PROVIDE(P2IFG = 0x021D);\r
+\r
+PROVIDE(P3IN = 0x0220);\r
+\r
+PROVIDE(P4IN = 0x0221);\r
+\r
+PROVIDE(P3OUT = 0x0222);\r
+\r
+PROVIDE(P4OUT = 0x0223);\r
+\r
+PROVIDE(P3DIR = 0x0224);\r
+\r
+PROVIDE(P4DIR = 0x0225);\r
+\r
+PROVIDE(P3REN = 0x0226);\r
+\r
+PROVIDE(P4REN = 0x0227);\r
+\r
+PROVIDE(P4SEL0 = 0x022B);\r
+\r
+PROVIDE(P3SEL0 = 0x022A);\r
+\r
+PROVIDE(P3SEL1 = 0x022C);\r
+\r
+PROVIDE(P4SEL1 = 0x022D);\r
+\r
+PROVIDE(P3SELC = 0x0236);\r
+\r
+PROVIDE(P4SELC = 0x0237);\r
+\r
+PROVIDE(P3IES = 0x0238);\r
+\r
+PROVIDE(P4IES = 0x0239);\r
+\r
+PROVIDE(P3IE = 0x023A);\r
+\r
+PROVIDE(P4IE = 0x023B);\r
+\r
+PROVIDE(P3IFG = 0x023C);\r
+\r
+PROVIDE(P4IFG = 0x023D);\r
+\r
+PROVIDE(P5IN = 0x0240);\r
+\r
+PROVIDE(P6IN = 0x0241);\r
+\r
+PROVIDE(P5OUT = 0x0242);\r
+\r
+PROVIDE(P6OUT = 0x0243);\r
+\r
+PROVIDE(P5DIR = 0x0244);\r
+\r
+PROVIDE(P6DIR = 0x0245);\r
+\r
+PROVIDE(P5REN = 0x0246);\r
+\r
+PROVIDE(P6REN = 0x0247);\r
+\r
+PROVIDE(P5SEL0 = 0x024A);\r
+\r
+PROVIDE(P6SEL0 = 0x024B);\r
+\r
+PROVIDE(P5SEL1 = 0x024C);\r
+\r
+PROVIDE(P6SEL1 = 0x024D);\r
+\r
+PROVIDE(P5SELC = 0x0256);\r
+\r
+PROVIDE(P6SELC = 0x0257);\r
+\r
+PROVIDE(P5IES = 0x0258);\r
+\r
+PROVIDE(P6IES = 0x0259);\r
+\r
+PROVIDE(P5IE = 0x025A);\r
+\r
+PROVIDE(P6IE = 0x025B);\r
+\r
+PROVIDE(P5IFG = 0x025C);\r
+\r
+PROVIDE(P6IFG = 0x025D);\r
+\r
+\r
+\r
+/*****************************************************************************\r
+ FRCTL\r
+*****************************************************************************/\r
+PROVIDE(FRCTL0 = 0x01A0);\r
+PROVIDE(FRCTL0_L = 0x01A0);\r
+PROVIDE(FRCTL0_H = 0x01A1);\r
+PROVIDE(GCCTL0 = 0x01A4);\r
+PROVIDE(GCCTL0_L = 0x01A4);\r
+PROVIDE(GCCTL0_H = 0x01A5);\r
+PROVIDE(GCCTL1 = 0x01A6);\r
+PROVIDE(GCCTL1_L = 0x01A6);\r
+PROVIDE(GCCTL1_H = 0x01A7);\r
+\r
+\r
+/*****************************************************************************\r
+ MPY32\r
+*****************************************************************************/\r
+PROVIDE(MPY = 0x04C0);\r
+PROVIDE(MPY_L = 0x04C0);\r
+PROVIDE(MPY_H = 0x04C1);\r
+PROVIDE(MPYS = 0x04C2);\r
+PROVIDE(MPYS_L = 0x04C2);\r
+PROVIDE(MPYS_H = 0x04C3);\r
+PROVIDE(MAC = 0x04C4);\r
+PROVIDE(MAC_L = 0x04C4);\r
+PROVIDE(MAC_H = 0x04C5);\r
+PROVIDE(MACS = 0x04C6);\r
+PROVIDE(MACS_L = 0x04C6);\r
+PROVIDE(MACS_H = 0x04C7);\r
+PROVIDE(OP2 = 0x04C8);\r
+PROVIDE(OP2_L = 0x04C8);\r
+PROVIDE(OP2_H = 0x04C9);\r
+PROVIDE(RESLO = 0x04CA);\r
+PROVIDE(RESLO_L = 0x04CA);\r
+PROVIDE(RESLO_H = 0x04CB);\r
+PROVIDE(RESHI = 0x04CC);\r
+PROVIDE(RESHI_L = 0x04CC);\r
+PROVIDE(RESHI_H = 0x04CD);\r
+PROVIDE(SUMEXT = 0x04CE);\r
+PROVIDE(SUMEXT_L = 0x04CE);\r
+PROVIDE(SUMEXT_H = 0x04CF);\r
+PROVIDE(MPY32L = 0x04D0);\r
+PROVIDE(MPY32L_L = 0x04D0);\r
+PROVIDE(MPY32L_H = 0x04D1);\r
+PROVIDE(MPY32H = 0x04D2);\r
+PROVIDE(MPY32H_L = 0x04D2);\r
+PROVIDE(MPY32H_H = 0x04D3);\r
+PROVIDE(MPYS32L = 0x04D4);\r
+PROVIDE(MPYS32L_L = 0x04D4);\r
+PROVIDE(MPYS32L_H = 0x04D5);\r
+PROVIDE(MPYS32H = 0x04D6);\r
+PROVIDE(MPYS32H_L = 0x04D6);\r
+PROVIDE(MPYS32H_H = 0x04D7);\r
+PROVIDE(MAC32L = 0x04D8);\r
+PROVIDE(MAC32L_L = 0x04D8);\r
+PROVIDE(MAC32L_H = 0x04D9);\r
+PROVIDE(MAC32H = 0x04DA);\r
+PROVIDE(MAC32H_L = 0x04DA);\r
+PROVIDE(MAC32H_H = 0x04DB);\r
+PROVIDE(MACS32L = 0x04DC);\r
+PROVIDE(MACS32L_L = 0x04DC);\r
+PROVIDE(MACS32L_H = 0x04DD);\r
+PROVIDE(MACS32H = 0x04DE);\r
+PROVIDE(MACS32H_L = 0x04DE);\r
+PROVIDE(MACS32H_H = 0x04DF);\r
+PROVIDE(OP2L = 0x04E0);\r
+PROVIDE(OP2L_L = 0x04E0);\r
+PROVIDE(OP2L_H = 0x04E1);\r
+PROVIDE(OP2H = 0x04E2);\r
+PROVIDE(OP2H_L = 0x04E2);\r
+PROVIDE(OP2H_H = 0x04E3);\r
+PROVIDE(RES0 = 0x04E4);\r
+PROVIDE(RES0_L = 0x04E4);\r
+PROVIDE(RES0_H = 0x04E5);\r
+PROVIDE(RES1 = 0x04E6);\r
+PROVIDE(RES1_L = 0x04E6);\r
+PROVIDE(RES1_H = 0x04E7);\r
+PROVIDE(RES2 = 0x04E8);\r
+PROVIDE(RES2_L = 0x04E8);\r
+PROVIDE(RES2_H = 0x04E9);\r
+PROVIDE(RES3 = 0x04EA);\r
+PROVIDE(RES3_L = 0x04EA);\r
+PROVIDE(RES3_H = 0x04EB);\r
+PROVIDE(MPY32CTL0 = 0x04EC);\r
+PROVIDE(MPY32CTL0_L = 0x04EC);\r
+PROVIDE(MPY32CTL0_H = 0x04ED);\r
+\r
+\r
+/*****************************************************************************\r
+ PMM\r
+*****************************************************************************/\r
+PROVIDE(PMMCTL0 = 0x0120);\r
+PROVIDE(PMMCTL0_L = 0x0120);\r
+PROVIDE(PMMCTL0_H = 0x0121);\r
+PROVIDE(PMMCTL1 = 0x0122);\r
+PROVIDE(PMMCTL1_L = 0x0122);\r
+PROVIDE(PMMCTL1_H = 0x0123);\r
+PROVIDE(PMMCTL2 = 0x0124);\r
+PROVIDE(PMMCTL2_L = 0x0124);\r
+PROVIDE(PMMCTL2_H = 0x0125);\r
+PROVIDE(PMMIFG = 0x012A);\r
+PROVIDE(PMMIFG_L = 0x012A);\r
+PROVIDE(PMMIFG_H = 0x012B);\r
+PROVIDE(PM5CTL0 = 0x0130);\r
+PROVIDE(PM5CTL0_L = 0x0130);\r
+PROVIDE(PM5CTL0_H = 0x0131);\r
+\r
+\r
+/*****************************************************************************\r
+ RTC\r
+*****************************************************************************/\r
+PROVIDE(RTCCTL = 0x0300);\r
+PROVIDE(RTCCTL_L = 0x0300);\r
+PROVIDE(RTCCTL_H = 0x0301);\r
+PROVIDE(RTCIV = 0x0304);\r
+PROVIDE(RTCIV_L = 0x0304);\r
+PROVIDE(RTCIV_H = 0x0305);\r
+PROVIDE(RTCMOD = 0x0308);\r
+PROVIDE(RTCMOD_L = 0x0308);\r
+PROVIDE(RTCMOD_H = 0x0309);\r
+PROVIDE(RTCCNT = 0x030C);\r
+PROVIDE(RTCCNT_L = 0x030C);\r
+PROVIDE(RTCCNT_H = 0x030D);\r
+\r
+\r
+/*****************************************************************************\r
+ SFR\r
+*****************************************************************************/\r
+PROVIDE(SFRIE1 = 0x0100);\r
+PROVIDE(SFRIE1_L = 0x0100);\r
+PROVIDE(SFRIE1_H = 0x0101);\r
+PROVIDE(SFRIFG1 = 0x0102);\r
+PROVIDE(SFRIFG1_L = 0x0102);\r
+PROVIDE(SFRIFG1_H = 0x0103);\r
+PROVIDE(SFRRPCR = 0x0104);\r
+PROVIDE(SFRRPCR_L = 0x0104);\r
+PROVIDE(SFRRPCR_H = 0x0105);\r
+\r
+\r
+/*****************************************************************************\r
+ SYS\r
+*****************************************************************************/\r
+PROVIDE(SYSCTL = 0x0140);\r
+PROVIDE(SYSCTL_L = 0x0140);\r
+PROVIDE(SYSCTL_H = 0x0141);\r
+PROVIDE(SYSBSLC = 0x0142);\r
+PROVIDE(SYSBSLC_L = 0x0142);\r
+PROVIDE(SYSBSLC_H = 0x0143);\r
+PROVIDE(SYSJMBC = 0x0146);\r
+PROVIDE(SYSJMBC_L = 0x0146);\r
+PROVIDE(SYSJMBC_H = 0x0147);\r
+PROVIDE(SYSJMBI0 = 0x0148);\r
+PROVIDE(SYSJMBI0_L = 0x0148);\r
+PROVIDE(SYSJMBI0_H = 0x0149);\r
+PROVIDE(SYSJMBI1 = 0x014A);\r
+PROVIDE(SYSJMBI1_L = 0x014A);\r
+PROVIDE(SYSJMBI1_H = 0x014B);\r
+PROVIDE(SYSJMBO0 = 0x014C);\r
+PROVIDE(SYSJMBO0_L = 0x014C);\r
+PROVIDE(SYSJMBO0_H = 0x014D);\r
+PROVIDE(SYSJMBO1 = 0x014E);\r
+PROVIDE(SYSJMBO1_L = 0x014E);\r
+PROVIDE(SYSJMBO1_H = 0x014F);\r
+PROVIDE(SYSUNIV = 0x015A);\r
+PROVIDE(SYSUNIV_L = 0x015A);\r
+PROVIDE(SYSUNIV_H = 0x015B);\r
+PROVIDE(SYSSNIV = 0x015C);\r
+PROVIDE(SYSSNIV_L = 0x015C);\r
+PROVIDE(SYSSNIV_H = 0x015D);\r
+PROVIDE(SYSRSTIV = 0x015E);\r
+PROVIDE(SYSRSTIV_L = 0x015E);\r
+PROVIDE(SYSRSTIV_H = 0x015F);\r
+PROVIDE(SYSCFG0 = 0x0160);\r
+PROVIDE(SYSCFG0_L = 0x0160);\r
+PROVIDE(SYSCFG0_H = 0x0161);\r
+PROVIDE(SYSCFG1 = 0x0162);\r
+PROVIDE(SYSCFG1_L = 0x0162);\r
+PROVIDE(SYSCFG1_H = 0x0163);\r
+PROVIDE(SYSCFG2 = 0x0164);\r
+PROVIDE(SYSCFG2_L = 0x0164);\r
+PROVIDE(SYSCFG2_H = 0x0165);\r
+PROVIDE(SYSCFG3 = 0x0166);\r
+PROVIDE(SYSCFG3_L = 0x0166);\r
+PROVIDE(SYSCFG3_H = 0x0167);\r
+\r
+\r
+/*****************************************************************************\r
+ TA0\r
+*****************************************************************************/\r
+PROVIDE(TA0CTL = 0x0380);\r
+PROVIDE(TA0CTL_L = 0x0380);\r
+PROVIDE(TA0CTL_H = 0x0381);\r
+PROVIDE(TA0CCTL0 = 0x0382);\r
+PROVIDE(TA0CCTL0_L = 0x0382);\r
+PROVIDE(TA0CCTL0_H = 0x0383);\r
+PROVIDE(TA0CCTL1 = 0x0384);\r
+PROVIDE(TA0CCTL1_L = 0x0384);\r
+PROVIDE(TA0CCTL1_H = 0x0385);\r
+PROVIDE(TA0CCTL2 = 0x0386);\r
+PROVIDE(TA0CCTL2_L = 0x0386);\r
+PROVIDE(TA0CCTL2_H = 0x0387);\r
+PROVIDE(TA0R = 0x0390);\r
+PROVIDE(TA0R_L = 0x0390);\r
+PROVIDE(TA0R_H = 0x0391);\r
+PROVIDE(TA0CCR0 = 0x0392);\r
+PROVIDE(TA0CCR0_L = 0x0392);\r
+PROVIDE(TA0CCR0_H = 0x0393);\r
+PROVIDE(TA0CCR1 = 0x0394);\r
+PROVIDE(TA0CCR1_L = 0x0394);\r
+PROVIDE(TA0CCR1_H = 0x0395);\r
+PROVIDE(TA0CCR2 = 0x0396);\r
+PROVIDE(TA0CCR2_L = 0x0396);\r
+PROVIDE(TA0CCR2_H = 0x0397);\r
+PROVIDE(TA0EX0 = 0x03A0);\r
+PROVIDE(TA0EX0_L = 0x03A0);\r
+PROVIDE(TA0EX0_H = 0x03A1);\r
+PROVIDE(TA0IV = 0x03AE);\r
+PROVIDE(TA0IV_L = 0x03AE);\r
+PROVIDE(TA0IV_H = 0x03AF);\r
+\r
+\r
+/*****************************************************************************\r
+ TA1\r
+*****************************************************************************/\r
+PROVIDE(TA1CTL = 0x03C0);\r
+PROVIDE(TA1CTL_L = 0x03C0);\r
+PROVIDE(TA1CTL_H = 0x03C1);\r
+PROVIDE(TA1CCTL0 = 0x03C2);\r
+PROVIDE(TA1CCTL0_L = 0x03C2);\r
+PROVIDE(TA1CCTL0_H = 0x03C3);\r
+PROVIDE(TA1CCTL1 = 0x03C4);\r
+PROVIDE(TA1CCTL1_L = 0x03C4);\r
+PROVIDE(TA1CCTL1_H = 0x03C5);\r
+PROVIDE(TA1CCTL2 = 0x03C6);\r
+PROVIDE(TA1CCTL2_L = 0x03C6);\r
+PROVIDE(TA1CCTL2_H = 0x03C7);\r
+PROVIDE(TA1R = 0x03D0);\r
+PROVIDE(TA1R_L = 0x03D0);\r
+PROVIDE(TA1R_H = 0x03D1);\r
+PROVIDE(TA1CCR0 = 0x03D2);\r
+PROVIDE(TA1CCR0_L = 0x03D2);\r
+PROVIDE(TA1CCR0_H = 0x03D3);\r
+PROVIDE(TA1CCR1 = 0x03D4);\r
+PROVIDE(TA1CCR1_L = 0x03D4);\r
+PROVIDE(TA1CCR1_H = 0x03D5);\r
+PROVIDE(TA1CCR2 = 0x03D6);\r
+PROVIDE(TA1CCR2_L = 0x03D6);\r
+PROVIDE(TA1CCR2_H = 0x03D7);\r
+PROVIDE(TA1EX0 = 0x03E0);\r
+PROVIDE(TA1EX0_L = 0x03E0);\r
+PROVIDE(TA1EX0_H = 0x03E1);\r
+PROVIDE(TA1IV = 0x03EE);\r
+PROVIDE(TA1IV_L = 0x03EE);\r
+PROVIDE(TA1IV_H = 0x03EF);\r
+\r
+\r
+/*****************************************************************************\r
+ TA2\r
+*****************************************************************************/\r
+PROVIDE(TA2CTL = 0x0400);\r
+PROVIDE(TA2CTL_L = 0x0400);\r
+PROVIDE(TA2CTL_H = 0x0401);\r
+PROVIDE(TA2CCTL0 = 0x0402);\r
+PROVIDE(TA2CCTL0_L = 0x0402);\r
+PROVIDE(TA2CCTL0_H = 0x0403);\r
+PROVIDE(TA2CCTL1 = 0x0404);\r
+PROVIDE(TA2CCTL1_L = 0x0404);\r
+PROVIDE(TA2CCTL1_H = 0x0405);\r
+PROVIDE(TA2CCTL2 = 0x0406);\r
+PROVIDE(TA2CCTL2_L = 0x0406);\r
+PROVIDE(TA2CCTL2_H = 0x0407);\r
+PROVIDE(TA2R = 0x0410);\r
+PROVIDE(TA2R_L = 0x0410);\r
+PROVIDE(TA2R_H = 0x0411);\r
+PROVIDE(TA2CCR0 = 0x0412);\r
+PROVIDE(TA2CCR0_L = 0x0412);\r
+PROVIDE(TA2CCR0_H = 0x0413);\r
+PROVIDE(TA2CCR1 = 0x0414);\r
+PROVIDE(TA2CCR1_L = 0x0414);\r
+PROVIDE(TA2CCR1_H = 0x0415);\r
+PROVIDE(TA2CCR2 = 0x0416);\r
+PROVIDE(TA2CCR2_L = 0x0416);\r
+PROVIDE(TA2CCR2_H = 0x0417);\r
+PROVIDE(TA2EX0 = 0x0420);\r
+PROVIDE(TA2EX0_L = 0x0420);\r
+PROVIDE(TA2EX0_H = 0x0421);\r
+PROVIDE(TA2IV = 0x042E);\r
+PROVIDE(TA2IV_L = 0x042E);\r
+PROVIDE(TA2IV_H = 0x042F);\r
+\r
+\r
+/*****************************************************************************\r
+ TA3\r
+*****************************************************************************/\r
+PROVIDE(TA3CTL = 0x0440);\r
+PROVIDE(TA3CTL_L = 0x0440);\r
+PROVIDE(TA3CTL_H = 0x0441);\r
+PROVIDE(TA3CCTL0 = 0x0442);\r
+PROVIDE(TA3CCTL0_L = 0x0442);\r
+PROVIDE(TA3CCTL0_H = 0x0443);\r
+PROVIDE(TA3CCTL1 = 0x0444);\r
+PROVIDE(TA3CCTL1_L = 0x0444);\r
+PROVIDE(TA3CCTL1_H = 0x0445);\r
+PROVIDE(TA3CCTL2 = 0x0446);\r
+PROVIDE(TA3CCTL2_L = 0x0446);\r
+PROVIDE(TA3CCTL2_H = 0x0447);\r
+PROVIDE(TA3R = 0x0450);\r
+PROVIDE(TA3R_L = 0x0450);\r
+PROVIDE(TA3R_H = 0x0451);\r
+PROVIDE(TA3CCR0 = 0x0452);\r
+PROVIDE(TA3CCR0_L = 0x0452);\r
+PROVIDE(TA3CCR0_H = 0x0453);\r
+PROVIDE(TA3CCR1 = 0x0454);\r
+PROVIDE(TA3CCR1_L = 0x0454);\r
+PROVIDE(TA3CCR1_H = 0x0455);\r
+PROVIDE(TA3CCR2 = 0x0456);\r
+PROVIDE(TA3CCR2_L = 0x0456);\r
+PROVIDE(TA3CCR2_H = 0x0457);\r
+PROVIDE(TA3EX0 = 0x0460);\r
+PROVIDE(TA3EX0_L = 0x0460);\r
+PROVIDE(TA3EX0_H = 0x0461);\r
+PROVIDE(TA3IV = 0x046E);\r
+PROVIDE(TA3IV_L = 0x046E);\r
+PROVIDE(TA3IV_H = 0x046F);\r
+\r
+\r
+/*****************************************************************************\r
+ TB0\r
+*****************************************************************************/\r
+PROVIDE(TB0CTL = 0x0480);\r
+PROVIDE(TB0CTL_L = 0x0480);\r
+PROVIDE(TB0CTL_H = 0x0481);\r
+PROVIDE(TB0CCTL0 = 0x0482);\r
+PROVIDE(TB0CCTL0_L = 0x0482);\r
+PROVIDE(TB0CCTL0_H = 0x0483);\r
+PROVIDE(TB0CCTL1 = 0x0484);\r
+PROVIDE(TB0CCTL1_L = 0x0484);\r
+PROVIDE(TB0CCTL1_H = 0x0485);\r
+PROVIDE(TB0CCTL2 = 0x0486);\r
+PROVIDE(TB0CCTL2_L = 0x0486);\r
+PROVIDE(TB0CCTL2_H = 0x0487);\r
+PROVIDE(TB0CCTL3 = 0x0488);\r
+PROVIDE(TB0CCTL3_L = 0x0488);\r
+PROVIDE(TB0CCTL3_H = 0x0489);\r
+PROVIDE(TB0CCTL4 = 0x048A);\r
+PROVIDE(TB0CCTL4_L = 0x048A);\r
+PROVIDE(TB0CCTL4_H = 0x048B);\r
+PROVIDE(TB0CCTL5 = 0x048C);\r
+PROVIDE(TB0CCTL5_L = 0x048C);\r
+PROVIDE(TB0CCTL5_H = 0x048D);\r
+PROVIDE(TB0CCTL6 = 0x048E);\r
+PROVIDE(TB0CCTL6_L = 0x048E);\r
+PROVIDE(TB0CCTL6_H = 0x048F);\r
+PROVIDE(TB0R = 0x0490);\r
+PROVIDE(TB0R_L = 0x0490);\r
+PROVIDE(TB0R_H = 0x0491);\r
+PROVIDE(TB0CCR0 = 0x0492);\r
+PROVIDE(TB0CCR0_L = 0x0492);\r
+PROVIDE(TB0CCR0_H = 0x0493);\r
+PROVIDE(TB0CCR1 = 0x0494);\r
+PROVIDE(TB0CCR1_L = 0x0494);\r
+PROVIDE(TB0CCR1_H = 0x0495);\r
+PROVIDE(TB0CCR2 = 0x0496);\r
+PROVIDE(TB0CCR2_L = 0x0496);\r
+PROVIDE(TB0CCR2_H = 0x0497);\r
+PROVIDE(TB0CCR3 = 0x0498);\r
+PROVIDE(TB0CCR3_L = 0x0498);\r
+PROVIDE(TB0CCR3_H = 0x0499);\r
+PROVIDE(TB0CCR4 = 0x049A);\r
+PROVIDE(TB0CCR4_L = 0x049A);\r
+PROVIDE(TB0CCR4_H = 0x049B);\r
+PROVIDE(TB0CCR5 = 0x049C);\r
+PROVIDE(TB0CCR5_L = 0x049C);\r
+PROVIDE(TB0CCR5_H = 0x049D);\r
+PROVIDE(TB0CCR6 = 0x049E);\r
+PROVIDE(TB0CCR6_L = 0x049E);\r
+PROVIDE(TB0CCR6_H = 0x049F);\r
+PROVIDE(TB0EX0 = 0x04A0);\r
+PROVIDE(TB0EX0_L = 0x04A0);\r
+PROVIDE(TB0EX0_H = 0x04A1);\r
+PROVIDE(TB0IV = 0x04AE);\r
+PROVIDE(TB0IV_L = 0x04AE);\r
+PROVIDE(TB0IV_H = 0x04AF);\r
+\r
+\r
+/*****************************************************************************\r
+ WDT_A\r
+*****************************************************************************/\r
+PROVIDE(WDTCTL = 0x01CC);\r
+PROVIDE(WDTCTL_L = 0x01CC);\r
+PROVIDE(WDTCTL_H = 0x01CD);\r
+\r
+\r
+/*****************************************************************************\r
+ eCOMP0\r
+*****************************************************************************/\r
+PROVIDE(CP0CTL0 = 0x08E0);\r
+PROVIDE(CP0CTL0_L = 0x08E0);\r
+PROVIDE(CP0CTL0_H = 0x08E1);\r
+PROVIDE(CP0CTL1 = 0x08E2);\r
+PROVIDE(CP0CTL1_L = 0x08E2);\r
+PROVIDE(CP0CTL1_H = 0x08E3);\r
+PROVIDE(CP0INT = 0x08E6);\r
+PROVIDE(CP0INT_L = 0x08E6);\r
+PROVIDE(CP0INT_H = 0x08E7);\r
+PROVIDE(CP0IV = 0x08E8);\r
+PROVIDE(CP0IV_L = 0x08E8);\r
+PROVIDE(CP0IV_H = 0x08E9);\r
+PROVIDE(CP0DACCTL = 0x08F0);\r
+PROVIDE(CP0DACCTL_L = 0x08F0);\r
+PROVIDE(CP0DACCTL_H = 0x08F1);\r
+PROVIDE(CP0DACDATA = 0x08F2);\r
+PROVIDE(CP0DACDATA_L = 0x08F2);\r
+PROVIDE(CP0DACDATA_H = 0x08F3);\r
+\r
+\r
+/*****************************************************************************\r
+ eUSCI_A0\r
+*****************************************************************************/\r
+PROVIDE(UCA0CTLW0 = 0x0500);\r
+PROVIDE(UCA0CTLW0_L = 0x0500);\r
+PROVIDE(UCA0CTLW0_H = 0x0501);\r
+PROVIDE(UCA0CTLW1 = 0x0502);\r
+PROVIDE(UCA0CTLW1_L = 0x0502);\r
+PROVIDE(UCA0CTLW1_H = 0x0503);\r
+PROVIDE(UCA0BRW = 0x0506);\r
+PROVIDE(UCA0BRW_L = 0x0506);\r
+PROVIDE(UCA0BRW_H = 0x0507);\r
+PROVIDE(UCA0MCTLW = 0x0508);\r
+PROVIDE(UCA0MCTLW_L = 0x0508);\r
+PROVIDE(UCA0MCTLW_H = 0x0509);\r
+PROVIDE(UCA0STATW = 0x050A);\r
+PROVIDE(UCA0STATW_L = 0x050A);\r
+PROVIDE(UCA0STATW_H = 0x050B);\r
+PROVIDE(UCA0RXBUF = 0x050C);\r
+PROVIDE(UCA0RXBUF_L = 0x050C);\r
+PROVIDE(UCA0RXBUF_H = 0x050D);\r
+PROVIDE(UCA0TXBUF = 0x050E);\r
+PROVIDE(UCA0TXBUF_L = 0x050E);\r
+PROVIDE(UCA0TXBUF_H = 0x050F);\r
+PROVIDE(UCA0ABCTL = 0x0510);\r
+PROVIDE(UCA0ABCTL_L = 0x0510);\r
+PROVIDE(UCA0ABCTL_H = 0x0511);\r
+PROVIDE(UCA0IRCTL = 0x0512);\r
+PROVIDE(UCA0IRCTL_L = 0x0512);\r
+PROVIDE(UCA0IRCTL_H = 0x0513);\r
+PROVIDE(UCA0IE = 0x051A);\r
+PROVIDE(UCA0IE_L = 0x051A);\r
+PROVIDE(UCA0IE_H = 0x051B);\r
+PROVIDE(UCA0IFG = 0x051C);\r
+PROVIDE(UCA0IFG_L = 0x051C);\r
+PROVIDE(UCA0IFG_H = 0x051D);\r
+PROVIDE(UCA0IV = 0x051E);\r
+PROVIDE(UCA0IV_L = 0x051E);\r
+PROVIDE(UCA0IV_H = 0x051F);\r
+\r
+\r
+/*****************************************************************************\r
+ eUSCI_A1\r
+*****************************************************************************/\r
+PROVIDE(UCA1CTLW0 = 0x0520);\r
+PROVIDE(UCA1CTLW0_L = 0x0520);\r
+PROVIDE(UCA1CTLW0_H = 0x0521);\r
+PROVIDE(UCA1CTLW1 = 0x0522);\r
+PROVIDE(UCA1CTLW1_L = 0x0522);\r
+PROVIDE(UCA1CTLW1_H = 0x0523);\r
+PROVIDE(UCA1BRW = 0x0526);\r
+PROVIDE(UCA1BRW_L = 0x0526);\r
+PROVIDE(UCA1BRW_H = 0x0527);\r
+PROVIDE(UCA1MCTLW = 0x0528);\r
+PROVIDE(UCA1MCTLW_L = 0x0528);\r
+PROVIDE(UCA1MCTLW_H = 0x0529);\r
+PROVIDE(UCA1STATW = 0x052A);\r
+PROVIDE(UCA1STATW_L = 0x052A);\r
+PROVIDE(UCA1STATW_H = 0x052B);\r
+PROVIDE(UCA1RXBUF = 0x052C);\r
+PROVIDE(UCA1RXBUF_L = 0x052C);\r
+PROVIDE(UCA1RXBUF_H = 0x052D);\r
+PROVIDE(UCA1TXBUF = 0x052E);\r
+PROVIDE(UCA1TXBUF_L = 0x052E);\r
+PROVIDE(UCA1TXBUF_H = 0x052F);\r
+PROVIDE(UCA1ABCTL = 0x0530);\r
+PROVIDE(UCA1ABCTL_L = 0x0530);\r
+PROVIDE(UCA1ABCTL_H = 0x0531);\r
+PROVIDE(UCA1IRCTL = 0x0532);\r
+PROVIDE(UCA1IRCTL_L = 0x0532);\r
+PROVIDE(UCA1IRCTL_H = 0x0533);\r
+PROVIDE(UCA1IE = 0x053A);\r
+PROVIDE(UCA1IE_L = 0x053A);\r
+PROVIDE(UCA1IE_H = 0x053B);\r
+PROVIDE(UCA1IFG = 0x053C);\r
+PROVIDE(UCA1IFG_L = 0x053C);\r
+PROVIDE(UCA1IFG_H = 0x053D);\r
+PROVIDE(UCA1IV = 0x053E);\r
+PROVIDE(UCA1IV_L = 0x053E);\r
+PROVIDE(UCA1IV_H = 0x053F);\r
+\r
+\r
+/*****************************************************************************\r
+ eUSCI_B0\r
+*****************************************************************************/\r
+PROVIDE(UCB0CTLW0 = 0x0540);\r
+PROVIDE(UCB0CTLW0_L = 0x0540);\r
+PROVIDE(UCB0CTLW0_H = 0x0541);\r
+PROVIDE(UCB0CTLW1 = 0x0542);\r
+PROVIDE(UCB0CTLW1_L = 0x0542);\r
+PROVIDE(UCB0CTLW1_H = 0x0543);\r
+PROVIDE(UCB0BRW = 0x0546);\r
+PROVIDE(UCB0BRW_L = 0x0546);\r
+PROVIDE(UCB0BRW_H = 0x0547);\r
+PROVIDE(UCB0STATW = 0x0548);\r
+PROVIDE(UCB0STATW_L = 0x0548);\r
+PROVIDE(UCB0STATW_H = 0x0549);\r
+PROVIDE(UCB0TBCNT = 0x054A);\r
+PROVIDE(UCB0TBCNT_L = 0x054A);\r
+PROVIDE(UCB0TBCNT_H = 0x054B);\r
+PROVIDE(UCB0RXBUF = 0x054C);\r
+PROVIDE(UCB0RXBUF_L = 0x054C);\r
+PROVIDE(UCB0RXBUF_H = 0x054D);\r
+PROVIDE(UCB0TXBUF = 0x054E);\r
+PROVIDE(UCB0TXBUF_L = 0x054E);\r
+PROVIDE(UCB0TXBUF_H = 0x054F);\r
+PROVIDE(UCB0I2COA0 = 0x0554);\r
+PROVIDE(UCB0I2COA0_L = 0x0554);\r
+PROVIDE(UCB0I2COA0_H = 0x0555);\r
+PROVIDE(UCB0I2COA1 = 0x0556);\r
+PROVIDE(UCB0I2COA1_L = 0x0556);\r
+PROVIDE(UCB0I2COA1_H = 0x0557);\r
+PROVIDE(UCB0I2COA2 = 0x0558);\r
+PROVIDE(UCB0I2COA2_L = 0x0558);\r
+PROVIDE(UCB0I2COA2_H = 0x0559);\r
+PROVIDE(UCB0I2COA3 = 0x055A);\r
+PROVIDE(UCB0I2COA3_L = 0x055A);\r
+PROVIDE(UCB0I2COA3_H = 0x055B);\r
+PROVIDE(UCB0ADDRX = 0x055C);\r
+PROVIDE(UCB0ADDRX_L = 0x055C);\r
+PROVIDE(UCB0ADDRX_H = 0x055D);\r
+PROVIDE(UCB0ADDMASK = 0x055E);\r
+PROVIDE(UCB0ADDMASK_L = 0x055E);\r
+PROVIDE(UCB0ADDMASK_H = 0x055F);\r
+PROVIDE(UCB0I2CSA = 0x0560);\r
+PROVIDE(UCB0I2CSA_L = 0x0560);\r
+PROVIDE(UCB0I2CSA_H = 0x0561);\r
+PROVIDE(UCB0IE = 0x056A);\r
+PROVIDE(UCB0IE_L = 0x056A);\r
+PROVIDE(UCB0IE_H = 0x056B);\r
+PROVIDE(UCB0IFG = 0x056C);\r
+PROVIDE(UCB0IFG_L = 0x056C);\r
+PROVIDE(UCB0IFG_H = 0x056D);\r
+PROVIDE(UCB0IV = 0x056E);\r
+PROVIDE(UCB0IV_L = 0x056E);\r
+PROVIDE(UCB0IV_H = 0x056F);\r
+\r
+\r
+/*****************************************************************************\r
+ eUSCI_B1\r
+*****************************************************************************/\r
+PROVIDE(UCB1CTLW0 = 0x0580);\r
+PROVIDE(UCB1CTLW0_L = 0x0580);\r
+PROVIDE(UCB1CTLW0_H = 0x0581);\r
+PROVIDE(UCB1CTLW1 = 0x0582);\r
+PROVIDE(UCB1CTLW1_L = 0x0582);\r
+PROVIDE(UCB1CTLW1_H = 0x0583);\r
+PROVIDE(UCB1BRW = 0x0586);\r
+PROVIDE(UCB1BRW_L = 0x0586);\r
+PROVIDE(UCB1BRW_H = 0x0587);\r
+PROVIDE(UCB1STATW = 0x0588);\r
+PROVIDE(UCB1STATW_L = 0x0588);\r
+PROVIDE(UCB1STATW_H = 0x0589);\r
+PROVIDE(UCB1TBCNT = 0x058A);\r
+PROVIDE(UCB1TBCNT_L = 0x058A);\r
+PROVIDE(UCB1TBCNT_H = 0x058B);\r
+PROVIDE(UCB1RXBUF = 0x058C);\r
+PROVIDE(UCB1RXBUF_L = 0x058C);\r
+PROVIDE(UCB1RXBUF_H = 0x058D);\r
+PROVIDE(UCB1TXBUF = 0x058E);\r
+PROVIDE(UCB1TXBUF_L = 0x058E);\r
+PROVIDE(UCB1TXBUF_H = 0x058F);\r
+PROVIDE(UCB1I2COA0 = 0x0594);\r
+PROVIDE(UCB1I2COA0_L = 0x0594);\r
+PROVIDE(UCB1I2COA0_H = 0x0595);\r
+PROVIDE(UCB1I2COA1 = 0x0596);\r
+PROVIDE(UCB1I2COA1_L = 0x0596);\r
+PROVIDE(UCB1I2COA1_H = 0x0597);\r
+PROVIDE(UCB1I2COA2 = 0x0598);\r
+PROVIDE(UCB1I2COA2_L = 0x0598);\r
+PROVIDE(UCB1I2COA2_H = 0x0599);\r
+PROVIDE(UCB1I2COA3 = 0x059A);\r
+PROVIDE(UCB1I2COA3_L = 0x059A);\r
+PROVIDE(UCB1I2COA3_H = 0x059B);\r
+PROVIDE(UCB1ADDRX = 0x059C);\r
+PROVIDE(UCB1ADDRX_L = 0x059C);\r
+PROVIDE(UCB1ADDRX_H = 0x059D);\r
+PROVIDE(UCB1ADDMASK = 0x059E);\r
+PROVIDE(UCB1ADDMASK_L = 0x059E);\r
+PROVIDE(UCB1ADDMASK_H = 0x059F);\r
+PROVIDE(UCB1I2CSA = 0x05A0);\r
+PROVIDE(UCB1I2CSA_L = 0x05A0);\r
+PROVIDE(UCB1I2CSA_H = 0x05A1);\r
+PROVIDE(UCB1IE = 0x05AA);\r
+PROVIDE(UCB1IE_L = 0x05AA);\r
+PROVIDE(UCB1IE_H = 0x05AB);\r
+PROVIDE(UCB1IFG = 0x05AC);\r
+PROVIDE(UCB1IFG_L = 0x05AC);\r
+PROVIDE(UCB1IFG_H = 0x05AD);\r
+PROVIDE(UCB1IV = 0x05AE);\r
+PROVIDE(UCB1IV_L = 0x05AE);\r
+PROVIDE(UCB1IV_H = 0x05AF);\r
+\r
+/************************************************************\r
+* End of Modules\r
+************************************************************/\r
+\r
projects / bitgloo / alee-forth.git / commitdiff