\r
/* Private typedef -----------------------------------------------------------*/\r
/* USER CODE BEGIN PTD */\r
-\r
+typedef struct {\r
+ int32_t value : 18;\r
+} sample_t;\r
/* USER CODE END PTD */\r
\r
/* Private define ------------------------------------------------------------*/\r
static /*const*/ uint8_t I2S_Frame_Buffer[8] = {\r
0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF\r
};\r
-static uint8_t I2S_Receive_Buffer[2048];\r
+static uint8_t I2S_Receive_Buffer[4096];\r
/* USER CODE END PV */\r
\r
/* Private function prototypes -----------------------------------------------*/\r
MX_SPI1_Init();\r
MX_USART2_UART_Init();\r
/* USER CODE BEGIN 2 */\r
- puts("Hello, world!");\r
- \r
__enable_irq();\r
HAL_SPI_TransmitReceive_DMA_Mixed(&hspi1,\r
I2S_Frame_Buffer,\r
while (1)\r
{\r
/* USER CODE END WHILE */\r
- //__WFI();\r
+ __WFI();\r
/* USER CODE BEGIN 3 */\r
}\r
/* USER CODE END 3 */\r
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r
hspi1.Init.CRCPolynomial = 7;\r
hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;\r
- hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;\r
+ hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;\r
if (HAL_SPI_Init(&hspi1) != HAL_OK)\r
{\r
Error_Handler();\r
/* DMA1_Channel2_3_IRQn interrupt configuration */\r
HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0, 0);\r
HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);\r
+ /* DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQn interrupt configuration */\r
+ HAL_NVIC_SetPriority(DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQn, 0, 0);\r
+ HAL_NVIC_EnableIRQ(DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQn);\r
\r
}\r
\r
uint16_t TxSize,\r
uint16_t RxSize)\r
{\r
- uint32_t tmp_mode;\r
- HAL_SPI_StateTypeDef tmp_state;\r
HAL_StatusTypeDef errorcode = HAL_OK;\r
\r
- /* Check rx & tx dma handles */\r
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));\r
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));\r
-\r
- /* Check Direction parameter */\r
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
\r
- /* Process locked */\r
__HAL_LOCK(hspi);\r
\r
- /* Init temporary variables */\r
- tmp_state = hspi->State;\r
- tmp_mode = hspi->Init.Mode;\r
-\r
- if (!((tmp_state == HAL_SPI_STATE_READY) ||\r
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))\r
- {\r
- errorcode = HAL_BUSY;\r
- goto error;\r
- }\r
-\r
- if ((pTxData == NULL) || (pRxData == NULL) || (TxSize == 0U) || (RxSize == 0U))\r
- {\r
- errorcode = HAL_ERROR;\r
- goto error;\r
- }\r
-\r
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\r
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)\r
- {\r
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
- }\r
-\r
- /* Set the transaction information */\r
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
hspi->pTxBuffPtr = (uint8_t *)pTxData;\r
hspi->TxXferSize = TxSize;\r
hspi->pRxBuffPtr = (uint8_t *)pRxData;\r
hspi->RxXferSize = RxSize;\r
hspi->RxXferCount = RxSize;\r
-\r
- /* Init field not used in handle to zero */\r
hspi->RxISR = NULL;\r
hspi->TxISR = NULL;\r
\r
/* Reset the threshold bit */\r
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);\r
\r
- /* The packing mode management is enabled by the DMA settings according the spi data size */\r
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- {\r
- /* Set fiforxthreshold according the reception data length: 16bit */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- }\r
- else\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 8bit */\r
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-\r
- if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
- {\r
- if ((hspi->TxXferSize & 0x1U) == 0x0U)\r
- {\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
- hspi->TxXferCount = hspi->TxXferCount >> 1U;\r
- }\r
- else\r
- {\r
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
- hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;\r
- }\r
- }\r
-\r
- if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 16bit */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-\r
- if ((hspi->RxXferCount & 0x1U) == 0x0U)\r
- {\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
- hspi->RxXferCount = hspi->RxXferCount >> 1U;\r
- }\r
- else\r
- {\r
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
- hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;\r
- }\r
- }\r
- }\r
+ /* Set RX Fifo threshold according the reception data length: 8bit */\r
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
\r
- /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */\r
- if (hspi->State == HAL_SPI_STATE_BUSY_RX)\r
- {\r
- while (1); // TODO confirm if can remove\r
- }\r
- else\r
- {\r
- /* Set the SPI Tx/Rx DMA Half transfer complete callback */\r
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;\r
- hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;\r
- }\r
-\r
- /* Set the DMA error callback */\r
- hspi->hdmarx->XferErrorCallback = NULL;//SPI_DMAError;\r
-\r
- /* Set the DMA AbortCpltCallback */\r
- hspi->hdmarx->XferAbortCallback = NULL;\r
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;\r
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;\r
+ hspi->hdmarx->XferErrorCallback = NULL;\r
+ hspi->hdmarx->XferAbortCallback = NULL;\r
+ hspi->hdmatx->XferHalfCpltCallback = NULL;\r
+ hspi->hdmatx->XferCpltCallback = NULL;\r
+ hspi->hdmatx->XferErrorCallback = NULL;\r
+ hspi->hdmatx->XferAbortCallback = NULL;\r
\r
/* Enable the Rx DMA Stream/Channel */\r
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,\r
- hspi->RxXferCount))\r
- {\r
+ errorcode = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR,\r
+ (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);\r
+ if (HAL_OK != errorcode) {\r
/* Update SPI error code */\r
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
- errorcode = HAL_ERROR;\r
-\r
goto error;\r
}\r
\r
/* Enable Rx DMA Request */\r
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r
\r
- /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing\r
- is performed in DMA reception complete callback */\r
- hspi->hdmatx->XferHalfCpltCallback = NULL;\r
- hspi->hdmatx->XferCpltCallback = NULL;\r
- hspi->hdmatx->XferErrorCallback = NULL;\r
- hspi->hdmatx->XferAbortCallback = NULL;\r
-\r
/* Enable the Tx DMA Stream/Channel */\r
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,\r
- hspi->TxXferCount))\r
- {\r
+ errorcode = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr,\r
+ (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);\r
+ if (HAL_OK != errorcode) {\r
/* Update SPI error code */\r
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
- errorcode = HAL_ERROR;\r
-\r
goto error;\r
}\r
\r
/* Check if the SPI is already enabled */\r
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
- {\r
- /* Enable SPI peripheral */\r
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {\r
__HAL_SPI_ENABLE(hspi);\r
}\r
/* Enable the SPI Error Interrupt Bit */\r
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
\r
error :\r
- /* Process Unlocked */\r
__HAL_UNLOCK(hspi);\r
return errorcode;\r
}\r
\r
void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r
{\r
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);\r
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)hdma->Parent;\r
(void)hspi;\r
-\r
- puts("hey!\r\n");\r
}\r
\r
void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r
{\r
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);\r
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)hdma->Parent;\r
(void)hspi;\r
+\r
+ sample_t sample = *(sample_t *)I2S_Receive_Buffer;\r
+ printf("%d\r\n", sample.value);\r
}\r
/* USER CODE END 4 */\r
\r
/* USER CODE BEGIN Error_Handler_Debug */\r
/* User can add his own implementation to report the HAL error return state */\r
__disable_irq();\r
+ printf("Unhandled error, halting!\r\n");\r
while (1)\r
{\r
}\r
/* USER CODE BEGIN 6 */\r
/* User can add his own implementation to report the file name and line number,\r
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */\r
+ printf("Wrong parameters value: file %s on line %d\r\n", file, line);\r
/* USER CODE END 6 */\r
}\r
#endif /* USE_FULL_ASSERT */\r
##########################################################################################################################\r
-# File automatically-generated by tool: [projectgenerator] version: [4.5.0-RC5] date: [Wed Jan 29 20:12:35 EST 2025]\r
+# File automatically-generated by tool: [projectgenerator] version: [4.5.0-RC5] date: [Wed Jan 29 21:38:04 EST 2025] \r
##########################################################################################################################\r
\r
# ------------------------------------------------\r
# source\r
######################################\r
# C sources\r
-C_SOURCES = \
-Core/Src/main.c \
-Core/Src/stm32u0xx_it.c \
-Core/Src/stm32u0xx_hal_msp.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_cortex.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_rcc.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_rcc_ex.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_flash.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_flash_ex.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_gpio.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_dma.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_dma_ex.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pwr.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pwr_ex.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_exti.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_spi.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_spi_ex.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c \
-Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart_ex.c \
-Core/Src/system_stm32u0xx.c \
-Core/Src/sysmem.c \
-Core/Src/syscalls.c \r
+C_SOURCES = \\r
+Core/Src/main.c \\r
+Core/Src/stm32u0xx_it.c \\r
+Core/Src/stm32u0xx_hal_msp.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_cortex.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_rcc.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_rcc_ex.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_flash.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_flash_ex.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_gpio.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_dma.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_dma_ex.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pwr.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_pwr_ex.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_exti.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_spi.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_spi_ex.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c \\r
+Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart_ex.c \\r
+Core/Src/system_stm32u0xx.c \\r
+Core/Src/sysmem.c \\r
+Core/Src/syscalls.c\r
\r
# ASM sources\r
-ASM_SOURCES = \
+ASM_SOURCES = \\r
startup_stm32u083xx.s\r
\r
# ASM sources\r
AS_DEFS = \r
\r
# C defines\r
-C_DEFS = \
--DUSE_HAL_DRIVER \
+C_DEFS = \\r
+-DUSE_HAL_DRIVER \\r
-DSTM32U083xx\r
\r
\r
AS_INCLUDES = \r
\r
# C includes\r
-C_INCLUDES = \
--ICore/Inc \
--IDrivers/STM32U0xx_HAL_Driver/Inc \
--IDrivers/STM32U0xx_HAL_Driver/Inc/Legacy \
--IDrivers/CMSIS/Device/ST/STM32U0xx/Include \
+C_INCLUDES = \\r
+-ICore/Inc \\r
+-IDrivers/STM32U0xx_HAL_Driver/Inc \\r
+-IDrivers/STM32U0xx_HAL_Driver/Inc/Legacy \\r
+-IDrivers/CMSIS/Device/ST/STM32U0xx/Include \\r
-IDrivers/CMSIS/Include\r
\r
\r
#######################################\r
-include $(wildcard $(BUILD_DIR)/*.d)\r
\r
-# *** EOF ***
\ No newline at end of file
+# *** EOF ***\r