-build
**/.*
-gui/stmdspgui
**/*.o
**/*.so
perf*
+build
+eagle/*#*
+gui/stmdspgui
# Imported source files and paths.
CHIBIOS := ./ChibiOS_20.3.2
-CONFDIR := ./cfg
+CONFDIR := ./source/cfg
BUILDDIR := ./build
DEPDIR := ./.dep
else
include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk
endif
-include ./board/board.mk
+include ./source/board/board.mk
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
# Auto-build files in ./source recursively.
-include $(CHIBIOS)/tools/mk/autobuild.mk
+#include $(CHIBIOS)/tools/mk/autobuild.mk
+ALLCSRC += $(wildcard source/*.c)
+ALLCPPSRC += $(wildcard source/*.cpp)
+ALLASMSRC += $(wildcard source/*.s)
# Other files (optional).
#include $(CHIBIOS)/test/lib/test.mk
#include $(CHIBIOS)/test/rt/rt_test.mk
# Define linker script file here
ifeq ($(TARGET_PLATFORM),H7)
- LDSCRIPT = STM32H723xG.ld
+ LDSCRIPT = source/ld/STM32H723xG.ld
else
- LDSCRIPT = STM32L476xG.ld
+ LDSCRIPT = source/ld/STM32L476xG.ld
endif
# C sources that can be compiled in ARM or THUMB mode depending on the global
+++ /dev/null
-/*\r
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
-\r
- Licensed under the Apache License, Version 2.0 (the "License");\r
- you may not use this file except in compliance with the License.\r
- You may obtain a copy of the License at\r
-\r
- http://www.apache.org/licenses/LICENSE-2.0\r
-\r
- Unless required by applicable law or agreed to in writing, software\r
- distributed under the License is distributed on an "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- See the License for the specific language governing permissions and\r
- limitations under the License.\r
-*/\r
-\r
-/*\r
- * AXI SRAM - BSS, Data, Heap.\r
- * SRAM1 - SIGGEN.\r
- * SRAM2 - DAC.\r
- * SRAM4 - ADC.\r
- * DTCM-RAM - Process stacks.\r
- * ITCM-RAM - STMDSP Algorithm.\r
- * BCKP SRAM - None.\r
- */\r
-MEMORY\r
-{\r
- flash0 (rx) : org = 0x08000000, len = 1M /* Flash bank1 + bank2 */\r
- flash1 (rx) : org = 0x08000000, len = 510K /* Flash bank 1 */\r
- flashc (rx) : org = 0x0807F800, len = 2K /* Unprivileged firmware */\r
- flash2 (rx) : org = 0x08080000, len = 512K /* Flash bank 2 */\r
- flash3 (rx) : org = 0x00000000, len = 0\r
- flash4 (rx) : org = 0x00000000, len = 0\r
- flash5 (rx) : org = 0x00000000, len = 0\r
- flash6 (rx) : org = 0x00000000, len = 0\r
- flash7 (rx) : org = 0x00000000, len = 0\r
- ram0 (wx) : org = 0x24000000, len = 320K /* AXI SRAM */\r
- ram1 (wx) : org = 0x30000000, len = 16K /* AHB SRAM1 */\r
- ram2 (wx) : org = 0x30004000, len = 16K /* AHB SRAM2 */\r
- ram3 (wx) : org = 0x38000000, len = 16K /* AHB SRAM4 */\r
- ram4 (wx) : org = 0x00000000, len = 0\r
- ramc (wx) : org = 0x20000000, len = 64K /* Unprivileged data */\r
- ram5 (wx) : org = 0x20010000, len = 64K /* DTCM-RAM */\r
- ram6 (wx) : org = 0x00000000, len = 64K /* ITCM-RAM */\r
- ram7 (wx) : org = 0x38800000, len = 4K /* BCKP SRAM */\r
-}\r
-\r
-/* For each data/text section two region are defined, a virtual region\r
- and a load region (_LMA suffix).*/\r
-\r
-/* Flash region to be used for exception vectors.*/\r
-REGION_ALIAS("VECTORS_FLASH", flash0);\r
-REGION_ALIAS("VECTORS_FLASH_LMA", flash0);\r
-\r
-/* Flash region to be used for constructors and destructors.*/\r
-REGION_ALIAS("XTORS_FLASH", flash0);\r
-REGION_ALIAS("XTORS_FLASH_LMA", flash0);\r
-\r
-/* Flash region to be used for code text.*/\r
-REGION_ALIAS("TEXT_FLASH", flash0);\r
-REGION_ALIAS("TEXT_FLASH_LMA", flash0);\r
-\r
-/* Flash region to be used for read only data.*/\r
-REGION_ALIAS("RODATA_FLASH", flash0);\r
-REGION_ALIAS("RODATA_FLASH_LMA", flash0);\r
-\r
-/* Flash region to be used for various.*/\r
-REGION_ALIAS("VARIOUS_FLASH", flash0);\r
-REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);\r
-\r
-/* Flash region to be used for RAM(n) initialization data.*/\r
-REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);\r
-\r
-/* RAM region to be used for Main stack. This stack accommodates the processing\r
- of all exceptions and interrupts.*/\r
-REGION_ALIAS("MAIN_STACK_RAM", ram5);\r
-\r
-/* RAM region to be used for the process stack. This is the stack used by\r
- the main() function.*/\r
-REGION_ALIAS("PROCESS_STACK_RAM", ram5);\r
-\r
-/* RAM region to be used for data segment.*/\r
-REGION_ALIAS("DATA_RAM", ram0);\r
-REGION_ALIAS("DATA_RAM_LMA", flash0);\r
-\r
-/* RAM region to be used for BSS segment.*/\r
-REGION_ALIAS("BSS_RAM", ram0);\r
-\r
-/* RAM region to be used for the default heap.*/\r
-REGION_ALIAS("HEAP_RAM", ram0);\r
-\r
-/* Stack rules inclusion.*/\r
-INCLUDE rules_stacks.ld\r
-\r
-SECTIONS\r
-{\r
- .convdata : ALIGN(4)\r
- {\r
- *(.convdata)\r
- . = ALIGN(4);\r
- } > ramc\r
-\r
- .stacks : ALIGN(4)\r
- {\r
- *(.stacks)\r
- . = ALIGN(4);\r
- } > ram5\r
-\r
- .convcode : ALIGN(4)\r
- {\r
- *(.convcode)\r
- . = ALIGN(4);\r
- } > flashc\r
-}\r
-\r
-/* Code rules inclusion.*/\r
-INCLUDE rules_code.ld\r
-\r
-/* Data rules inclusion.*/\r
-INCLUDE rules_data.ld\r
-\r
-/* Memory rules inclusion.*/\r
-INCLUDE rules_memory.ld\r
-\r
+++ /dev/null
-/*\r
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
-\r
- Licensed under the Apache License, Version 2.0 (the "License");\r
- you may not use this file except in compliance with the License.\r
- You may obtain a copy of the License at\r
-\r
- http://www.apache.org/licenses/LICENSE-2.0\r
-\r
- Unless required by applicable law or agreed to in writing, software\r
- distributed under the License is distributed on an "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- See the License for the specific language governing permissions and\r
- limitations under the License.\r
-*/\r
-\r
-/*\r
- * STM32L476xG memory setup.\r
- * A total of 1MB of flash is available.\r
- * Firmware uses first 510K, then 2K after is used for unprivileged code.\r
- * A total of 128K of RAM is available.\r
- * SRAM2 (32K) is used for ELF binary loading.\r
- * 32K of SRAM1 is used for system RAM.\r
- * 48K is used for ADC and DAC buffers.\r
- * 16K is used for unprivileged data (incl. 8K stack).\r
- */\r
-MEMORY\r
-{\r
- flash0 (rx) : org = 0x08000000, len = 510K /* Flash bank 1 (reduced from 1M to 510K) */\r
- flash1 (rx) : org = 0x00000000, len = 0\r
- flash2 (rx) : org = 0x00000000, len = 0\r
- flash3 (rx) : org = 0x00000000, len = 0\r
- flash4 (rx) : org = 0x00000000, len = 0\r
- flash5 (rx) : org = 0x00000000, len = 0\r
- flash6 (rx) : org = 0x00000000, len = 0\r
- flash7 (rx) : org = 0x00000000, len = 0\r
- ram0 (wx) : org = 0x20000000, len = 32K /* SRAM (actual total = 96K) */\r
- ram1 (wx) : org = 0x20008000, len = 48K /* ADC/DAC buffers (16K * 3) */\r
- ram2 (wx) : org = 0x00000000, len = 0\r
- ram3 (wx) : org = 0x00000000, len = 0\r
- ram4 (wx) : org = 0x10000000, len = 32K /* User algorithm */\r
- ram5 (wx) : org = 0x00000000, len = 0\r
- ram6 (wx) : org = 0x00000000, len = 0\r
- ram7 (wx) : org = 0x00000000, len = 0\r
- flashc (rx) : org = 0x0807F800, len = 2K /* Unprivileged firmware */\r
- ramc (wx) : org = 0x20014000, len = 16K /* Unprivileged data */\r
-}\r
-\r
-/* For each data/text section two region are defined, a virtual region\r
- and a load region (_LMA suffix).*/\r
-\r
-/* Flash region to be used for exception vectors.*/\r
-REGION_ALIAS("VECTORS_FLASH", flash0);\r
-REGION_ALIAS("VECTORS_FLASH_LMA", flash0);\r
-\r
-/* Flash region to be used for constructors and destructors.*/\r
-REGION_ALIAS("XTORS_FLASH", flash0);\r
-REGION_ALIAS("XTORS_FLASH_LMA", flash0);\r
-\r
-/* Flash region to be used for code text.*/\r
-REGION_ALIAS("TEXT_FLASH", flash0);\r
-REGION_ALIAS("TEXT_FLASH_LMA", flash0);\r
-\r
-/* Flash region to be used for read only data.*/\r
-REGION_ALIAS("RODATA_FLASH", flash0);\r
-REGION_ALIAS("RODATA_FLASH_LMA", flash0);\r
-\r
-/* Flash region to be used for various.*/\r
-REGION_ALIAS("VARIOUS_FLASH", flash0);\r
-REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);\r
-\r
-/* Flash region to be used for RAM(n) initialization data.*/\r
-REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);\r
-\r
-/* RAM region to be used for Main stack. This stack accommodates the processing\r
- of all exceptions and interrupts.*/\r
-REGION_ALIAS("MAIN_STACK_RAM", ram0);\r
-\r
-/* RAM region to be used for the process stack. This is the stack used by\r
- the main() function.*/\r
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);\r
-\r
-/* RAM region to be used for data segment.*/\r
-REGION_ALIAS("DATA_RAM", ram0);\r
-REGION_ALIAS("DATA_RAM_LMA", flash0);\r
-\r
-/* RAM region to be used for BSS segment.*/\r
-REGION_ALIAS("BSS_RAM", ram0);\r
-\r
-/* RAM region to be used for the default heap.*/\r
-REGION_ALIAS("HEAP_RAM", ram0);\r
-\r
-SECTIONS\r
-{\r
- .convdata : ALIGN(4)\r
- {\r
- *(.convdata)\r
- . = ALIGN(4);\r
- } > ramc\r
-\r
- /*.stacks : ALIGN(4)\r
- {\r
- *(.stacks)\r
- . = ALIGN(4);\r
- } > ram5*/\r
-\r
- .convcode : ALIGN(4)\r
- {\r
- *(.convcode)\r
- . = ALIGN(4);\r
- } > flashc\r
-}\r
-\r
-\r
-/* Generic rules inclusion.*/\r
-INCLUDE rules.ld\r
+++ /dev/null
-# List of all the board related files.\r
-ifeq ($(TARGET_PLATFORM),H7)\r
- BOARDSRC = ./board/board_h7.c\r
-else\r
- BOARDSRC = ./board/board_l4.c\r
-endif\r
-\r
-# Required include directories\r
-ifeq ($(TARGET_PLATFORM),H7)\r
- BOARDINC = ./board/h7\r
-else\r
- BOARDINC = ./board/l4\r
-endif\r
-\r
-# Shared variables\r
-ALLCSRC += $(BOARDSRC)\r
-ALLINC += $(BOARDINC)\r
+++ /dev/null
-/*\r
- ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio\r
-\r
- Licensed under the Apache License, Version 2.0 (the "License");\r
- you may not use this file except in compliance with the License.\r
- You may obtain a copy of the License at\r
-\r
- http://www.apache.org/licenses/LICENSE-2.0\r
-\r
- Unless required by applicable law or agreed to in writing, software\r
- distributed under the License is distributed on an "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- See the License for the specific language governing permissions and\r
- limitations under the License.\r
-*/\r
-\r
-/*\r
- * This file has been automatically generated using ChibiStudio board\r
- * generator plugin. Do not edit manually.\r
- */\r
-\r
-#include "hal.h"\r
-#include "stm32_gpio.h"\r
-\r
-/*===========================================================================*/\r
-/* Driver local definitions. */\r
-/*===========================================================================*/\r
-\r
-/*===========================================================================*/\r
-/* Driver exported variables. */\r
-/*===========================================================================*/\r
-\r
-/*===========================================================================*/\r
-/* Driver local variables and types. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Type of STM32 GPIO port setup.\r
- */\r
-typedef struct {\r
- uint32_t moder;\r
- uint32_t otyper;\r
- uint32_t ospeedr;\r
- uint32_t pupdr;\r
- uint32_t odr;\r
- uint32_t afrl;\r
- uint32_t afrh;\r
-} gpio_setup_t;\r
-\r
-/**\r
- * @brief Type of STM32 GPIO initialization data.\r
- */\r
-typedef struct {\r
-#if STM32_HAS_GPIOA || defined(__DOXYGEN__)\r
- gpio_setup_t PAData;\r
-#endif\r
-#if STM32_HAS_GPIOB || defined(__DOXYGEN__)\r
- gpio_setup_t PBData;\r
-#endif\r
-#if STM32_HAS_GPIOC || defined(__DOXYGEN__)\r
- gpio_setup_t PCData;\r
-#endif\r
-#if STM32_HAS_GPIOD || defined(__DOXYGEN__)\r
- gpio_setup_t PDData;\r
-#endif\r
-#if STM32_HAS_GPIOE || defined(__DOXYGEN__)\r
- gpio_setup_t PEData;\r
-#endif\r
-#if STM32_HAS_GPIOF || defined(__DOXYGEN__)\r
- gpio_setup_t PFData;\r
-#endif\r
-#if STM32_HAS_GPIOG || defined(__DOXYGEN__)\r
- gpio_setup_t PGData;\r
-#endif\r
-#if STM32_HAS_GPIOH || defined(__DOXYGEN__)\r
- gpio_setup_t PHData;\r
-#endif\r
-#if STM32_HAS_GPIOI || defined(__DOXYGEN__)\r
- gpio_setup_t PIData;\r
-#endif\r
-#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)\r
- gpio_setup_t PJData;\r
-#endif\r
-#if STM32_HAS_GPIOK || defined(__DOXYGEN__)\r
- gpio_setup_t PKData;\r
-#endif\r
-} gpio_config_t;\r
-\r
-/**\r
- * @brief STM32 GPIO static initialization data.\r
- */\r
-static const gpio_config_t gpio_default_config = {\r
-#if STM32_HAS_GPIOA\r
- {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,\r
- VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},\r
-#endif\r
-#if STM32_HAS_GPIOB\r
- {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,\r
- VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},\r
-#endif\r
-#if STM32_HAS_GPIOC\r
- {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,\r
- VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},\r
-#endif\r
-#if STM32_HAS_GPIOD\r
- {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,\r
- VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},\r
-#endif\r
-#if STM32_HAS_GPIOE\r
- {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,\r
- VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},\r
-#endif\r
-#if STM32_HAS_GPIOF\r
- {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,\r
- VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},\r
-#endif\r
-#if STM32_HAS_GPIOG\r
- {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,\r
- VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},\r
-#endif\r
-#if STM32_HAS_GPIOH\r
- {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,\r
- VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},\r
-#endif\r
-#if STM32_HAS_GPIOI\r
- {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,\r
- VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},\r
-#endif\r
-#if STM32_HAS_GPIOJ\r
- {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,\r
- VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},\r
-#endif\r
-#if STM32_HAS_GPIOK\r
- {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,\r
- VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}\r
-#endif\r
-};\r
-\r
-/*===========================================================================*/\r
-/* Driver local functions. */\r
-/*===========================================================================*/\r
-\r
-static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {\r
-\r
- gpiop->OTYPER = config->otyper;\r
- gpiop->OSPEEDR = config->ospeedr;\r
- gpiop->PUPDR = config->pupdr;\r
- gpiop->ODR = config->odr;\r
- gpiop->AFRL = config->afrl;\r
- gpiop->AFRH = config->afrh;\r
- gpiop->MODER = config->moder;\r
-}\r
-\r
-static void stm32_gpio_init(void) {\r
-\r
- /* Enabling GPIO-related clocks, the mask comes from the\r
- registry header file.*/\r
- rccResetAHB4(STM32_GPIO_EN_MASK);\r
- rccEnableAHB4(STM32_GPIO_EN_MASK, true);\r
-\r
- /* Initializing all the defined GPIO ports.*/\r
-#if STM32_HAS_GPIOA\r
- gpio_init(GPIOA, &gpio_default_config.PAData);\r
-#endif\r
-#if STM32_HAS_GPIOB\r
- gpio_init(GPIOB, &gpio_default_config.PBData);\r
-#endif\r
-#if STM32_HAS_GPIOC\r
- gpio_init(GPIOC, &gpio_default_config.PCData);\r
-#endif\r
-#if STM32_HAS_GPIOD\r
- gpio_init(GPIOD, &gpio_default_config.PDData);\r
-#endif\r
-#if STM32_HAS_GPIOE\r
- gpio_init(GPIOE, &gpio_default_config.PEData);\r
-#endif\r
-#if STM32_HAS_GPIOF\r
- gpio_init(GPIOF, &gpio_default_config.PFData);\r
-#endif\r
-#if STM32_HAS_GPIOG\r
- gpio_init(GPIOG, &gpio_default_config.PGData);\r
-#endif\r
-#if STM32_HAS_GPIOH\r
- gpio_init(GPIOH, &gpio_default_config.PHData);\r
-#endif\r
-#if STM32_HAS_GPIOI\r
- gpio_init(GPIOI, &gpio_default_config.PIData);\r
-#endif\r
-#if STM32_HAS_GPIOJ\r
- gpio_init(GPIOJ, &gpio_default_config.PJData);\r
-#endif\r
-#if STM32_HAS_GPIOK\r
- gpio_init(GPIOK, &gpio_default_config.PKData);\r
-#endif\r
-}\r
-\r
-/*===========================================================================*/\r
-/* Driver interrupt handlers. */\r
-/*===========================================================================*/\r
-\r
-/*===========================================================================*/\r
-/* Driver exported functions. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Early initialization code.\r
- * @details GPIO ports and system clocks are initialized before everything\r
- * else.\r
- */\r
-void __early_init(void) {\r
-\r
- stm32_gpio_init();\r
- stm32_clock_init();\r
-}\r
-\r
-#if HAL_USE_SDC || defined(__DOXYGEN__)\r
-/**\r
- * @brief SDC card detection.\r
- */\r
-bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {\r
-\r
- (void)sdcp;\r
- /* CHTODO: Fill the implementation.*/\r
- return true;\r
-}\r
-\r
-/**\r
- * @brief SDC card write protection detection.\r
- */\r
-bool sdc_lld_is_write_protected(SDCDriver *sdcp) {\r
-\r
- (void)sdcp;\r
- /* CHTODO: Fill the implementation.*/\r
- return false;\r
-}\r
-#endif /* HAL_USE_SDC */\r
-\r
-#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)\r
-/**\r
- * @brief MMC_SPI card detection.\r
- */\r
-bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {\r
-\r
- (void)mmcp;\r
- /* CHTODO: Fill the implementation.*/\r
- return true;\r
-}\r
-\r
-/**\r
- * @brief MMC_SPI card write protection detection.\r
- */\r
-bool mmc_lld_is_write_protected(MMCDriver *mmcp) {\r
-\r
- (void)mmcp;\r
- /* CHTODO: Fill the implementation.*/\r
- return false;\r
-}\r
-#endif\r
-\r
-/**\r
- * @brief Board-specific initialization code.\r
- * @note You can add your board-specific code here.\r
- */\r
-void boardInit(void) {\r
-\r
-}\r
+++ /dev/null
-/*\r
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
-\r
- Licensed under the Apache License, Version 2.0 (the "License");\r
- you may not use this file except in compliance with the License.\r
- You may obtain a copy of the License at\r
-\r
- http://www.apache.org/licenses/LICENSE-2.0\r
-\r
- Unless required by applicable law or agreed to in writing, software\r
- distributed under the License is distributed on an "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- See the License for the specific language governing permissions and\r
- limitations under the License.\r
-*/\r
-\r
-/*\r
- * This file has been automatically generated using ChibiStudio board\r
- * generator plugin. Do not edit manually.\r
- */\r
-\r
-#include "hal.h"\r
-#include "stm32_gpio.h"\r
-\r
-/*===========================================================================*/\r
-/* Driver local definitions. */\r
-/*===========================================================================*/\r
-\r
-/*===========================================================================*/\r
-/* Driver exported variables. */\r
-/*===========================================================================*/\r
-\r
-/*===========================================================================*/\r
-/* Driver local variables and types. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Type of STM32 GPIO port setup.\r
- */\r
-typedef struct {\r
- uint32_t moder;\r
- uint32_t otyper;\r
- uint32_t ospeedr;\r
- uint32_t pupdr;\r
- uint32_t odr;\r
- uint32_t afrl;\r
- uint32_t afrh;\r
- uint32_t ascr;\r
- uint32_t lockr;\r
-} gpio_setup_t;\r
-\r
-/**\r
- * @brief Type of STM32 GPIO initialization data.\r
- */\r
-typedef struct {\r
-#if STM32_HAS_GPIOA || defined(__DOXYGEN__)\r
- gpio_setup_t PAData;\r
-#endif\r
-#if STM32_HAS_GPIOB || defined(__DOXYGEN__)\r
- gpio_setup_t PBData;\r
-#endif\r
-#if STM32_HAS_GPIOC || defined(__DOXYGEN__)\r
- gpio_setup_t PCData;\r
-#endif\r
-#if STM32_HAS_GPIOD || defined(__DOXYGEN__)\r
- gpio_setup_t PDData;\r
-#endif\r
-#if STM32_HAS_GPIOE || defined(__DOXYGEN__)\r
- gpio_setup_t PEData;\r
-#endif\r
-#if STM32_HAS_GPIOF || defined(__DOXYGEN__)\r
- gpio_setup_t PFData;\r
-#endif\r
-#if STM32_HAS_GPIOG || defined(__DOXYGEN__)\r
- gpio_setup_t PGData;\r
-#endif\r
-#if STM32_HAS_GPIOH || defined(__DOXYGEN__)\r
- gpio_setup_t PHData;\r
-#endif\r
-#if STM32_HAS_GPIOI || defined(__DOXYGEN__)\r
- gpio_setup_t PIData;\r
-#endif\r
-#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)\r
- gpio_setup_t PJData;\r
-#endif\r
-#if STM32_HAS_GPIOK || defined(__DOXYGEN__)\r
- gpio_setup_t PKData;\r
-#endif\r
-} gpio_config_t;\r
-\r
-/**\r
- * @brief STM32 GPIO static initialization data.\r
- */\r
-static const gpio_config_t gpio_default_config = {\r
-#if STM32_HAS_GPIOA\r
- {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,\r
- VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR,\r
- VAL_GPIOA_LOCKR},\r
-#endif\r
-#if STM32_HAS_GPIOB\r
- {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,\r
- VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR,\r
- VAL_GPIOB_LOCKR},\r
-#endif\r
-#if STM32_HAS_GPIOC\r
- {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,\r
- VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR,\r
- VAL_GPIOC_LOCKR},\r
-#endif\r
-#if STM32_HAS_GPIOD\r
- {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,\r
- VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR,\r
- VAL_GPIOD_LOCKR},\r
-#endif\r
-#if STM32_HAS_GPIOE\r
- {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,\r
- VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR,\r
- VAL_GPIOE_LOCKR},\r
-#endif\r
-#if STM32_HAS_GPIOF\r
- {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,\r
- VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR,\r
- VAL_GPIOF_LOCKR},\r
-#endif\r
-#if STM32_HAS_GPIOG\r
- {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,\r
- VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR,\r
- VAL_GPIOG_LOCKR},\r
-#endif\r
-#if STM32_HAS_GPIOH\r
- {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,\r
- VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR,\r
- VAL_GPIOH_LOCKR},\r
-#endif\r
-#if STM32_HAS_GPIOI\r
- {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,\r
- VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR,\r
- VAL_GPIOI_LOCKR},\r
-#endif\r
-#if STM32_HAS_GPIOJ\r
- {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,\r
- VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR,\r
- VAL_GPIOJ_LOCKR},\r
-#endif\r
-#if STM32_HAS_GPIOK\r
- {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,\r
- VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR,\r
- VAL_GPIOK_LOCKR}\r
-#endif\r
-};\r
-\r
-/*===========================================================================*/\r
-/* Driver local functions. */\r
-/*===========================================================================*/\r
-\r
-static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {\r
-\r
- gpiop->OTYPER = config->otyper;\r
- gpiop->ASCR = config->ascr;\r
- gpiop->OSPEEDR = config->ospeedr;\r
- gpiop->PUPDR = config->pupdr;\r
- gpiop->ODR = config->odr;\r
- gpiop->AFRL = config->afrl;\r
- gpiop->AFRH = config->afrh;\r
- gpiop->MODER = config->moder;\r
- gpiop->LOCKR = config->lockr;\r
-}\r
-\r
-static void stm32_gpio_init(void) {\r
-\r
- /* Enabling GPIO-related clocks, the mask comes from the\r
- registry header file.*/\r
- rccResetAHB2(STM32_GPIO_EN_MASK);\r
- rccEnableAHB2(STM32_GPIO_EN_MASK, true);\r
-\r
- /* Initializing all the defined GPIO ports.*/\r
-#if STM32_HAS_GPIOA\r
- gpio_init(GPIOA, &gpio_default_config.PAData);\r
-#endif\r
-#if STM32_HAS_GPIOB\r
- gpio_init(GPIOB, &gpio_default_config.PBData);\r
-#endif\r
-#if STM32_HAS_GPIOC\r
- gpio_init(GPIOC, &gpio_default_config.PCData);\r
-#endif\r
-#if STM32_HAS_GPIOD\r
- gpio_init(GPIOD, &gpio_default_config.PDData);\r
-#endif\r
-#if STM32_HAS_GPIOE\r
- gpio_init(GPIOE, &gpio_default_config.PEData);\r
-#endif\r
-#if STM32_HAS_GPIOF\r
- gpio_init(GPIOF, &gpio_default_config.PFData);\r
-#endif\r
-#if STM32_HAS_GPIOG\r
- gpio_init(GPIOG, &gpio_default_config.PGData);\r
-#endif\r
-#if STM32_HAS_GPIOH\r
- gpio_init(GPIOH, &gpio_default_config.PHData);\r
-#endif\r
-#if STM32_HAS_GPIOI\r
- gpio_init(GPIOI, &gpio_default_config.PIData);\r
-#endif\r
-#if STM32_HAS_GPIOJ\r
- gpio_init(GPIOJ, &gpio_default_config.PJData);\r
-#endif\r
-#if STM32_HAS_GPIOK\r
- gpio_init(GPIOK, &gpio_default_config.PKData);\r
-#endif\r
-}\r
-\r
-/*===========================================================================*/\r
-/* Driver interrupt handlers. */\r
-/*===========================================================================*/\r
-\r
-/*===========================================================================*/\r
-/* Driver exported functions. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Early initialization code.\r
- * @details GPIO ports and system clocks are initialized before everything\r
- * else.\r
- */\r
-void __early_init(void) {\r
-\r
- stm32_gpio_init();\r
- stm32_clock_init();\r
-}\r
-\r
-#if HAL_USE_SDC || defined(__DOXYGEN__)\r
-/**\r
- * @brief SDC card detection.\r
- */\r
-bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {\r
-\r
- (void)sdcp;\r
- /* CHTODO: Fill the implementation.*/\r
- return true;\r
-}\r
-\r
-/**\r
- * @brief SDC card write protection detection.\r
- */\r
-bool sdc_lld_is_write_protected(SDCDriver *sdcp) {\r
-\r
- (void)sdcp;\r
- /* CHTODO: Fill the implementation.*/\r
- return false;\r
-}\r
-#endif /* HAL_USE_SDC */\r
-\r
-#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)\r
-/**\r
- * @brief MMC_SPI card detection.\r
- */\r
-bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {\r
-\r
- (void)mmcp;\r
- /* CHTODO: Fill the implementation.*/\r
- return true;\r
-}\r
-\r
-/**\r
- * @brief MMC_SPI card write protection detection.\r
- */\r
-bool mmc_lld_is_write_protected(MMCDriver *mmcp) {\r
-\r
- (void)mmcp;\r
- /* CHTODO: Fill the implementation.*/\r
- return false;\r
-}\r
-#endif\r
-\r
-/**\r
- * @brief Board-specific initialization code.\r
- * @note You can add your board-specific code here.\r
- */\r
-void boardInit(void) {\r
-\r
-}\r
+++ /dev/null
-/*\r
- ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio\r
-\r
- Licensed under the Apache License, Version 2.0 (the "License");\r
- you may not use this file except in compliance with the License.\r
- You may obtain a copy of the License at\r
-\r
- http://www.apache.org/licenses/LICENSE-2.0\r
-\r
- Unless required by applicable law or agreed to in writing, software\r
- distributed under the License is distributed on an "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- See the License for the specific language governing permissions and\r
- limitations under the License.\r
-*/\r
-\r
-/*\r
- * This file has been automatically generated using ChibiStudio board\r
- * generator plugin. Do not edit manually.\r
- */\r
-\r
-#ifndef BOARD_H\r
-#define BOARD_H\r
-\r
-/*===========================================================================*/\r
-/* Driver constants. */\r
-/*===========================================================================*/\r
-\r
-/*\r
- * Setup for STMicroelectronics STM32 Nucleo144-H743ZI board.\r
- */\r
-\r
-/*\r
- * Board identifier.\r
- */\r
-#define BOARD_ST_NUCLEO144_H743ZI\r
-#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-H743ZI"\r
-\r
-/*\r
- * Ethernet PHY type.\r
- */\r
-#define BOARD_PHY_ID MII_LAN8742A_ID\r
-#define BOARD_PHY_RMII\r
-\r
-/*\r
- * Board oscillators-related settings.\r
- */\r
-#if !defined(STM32_LSECLK)\r
-#define STM32_LSECLK 32768U\r
-#endif\r
-\r
-#define STM32_LSEDRV (3U << 3U)\r
-\r
-#if !defined(STM32_HSECLK)\r
-#define STM32_HSECLK 8000000U\r
-#endif\r
-\r
-#define STM32_HSE_BYPASS\r
-\r
-/*\r
- * MCU type as defined in the ST header.\r
- */\r
-#define STM32H723xx\r
-\r
-/*\r
- * IO pins assignments.\r
- */\r
-#define GPIOA_PIN0 0U\r
-#define GPIOA_RMII_REF_CLK 1U\r
-#define GPIOA_RMII_MDIO 2U\r
-#define GPIOA_PIN3 3U\r
-#define GPIOA_PIN4 4U\r
-#define GPIOA_PIN5 5U\r
-#define GPIOA_PIN6 6U\r
-#define GPIOA_RMII_CRS_DV 7U\r
-#define GPIOA_USB_SOF 8U\r
-#define GPIOA_MCO1 8U\r
-#define GPIOA_USB_VBUS 9U\r
-#define GPIOA_USB_ID 10U\r
-#define GPIOA_USB_DM 11U\r
-#define GPIOA_USB_DP 12U\r
-#define GPIOA_SWDIO 13U\r
-#define GPIOA_SWCLK 14U\r
-#define GPIOA_T_JTDI 15U\r
-\r
-#define GPIOB_LED1 0U\r
-#define GPIOB_LED_GREEN 0U\r
-#define GPIOB_LED 0U\r
-#define GPIOB_PIN1 1U\r
-#define GPIOB_PIN2 2U\r
-#define GPIOB_SWO 3U\r
-#define GPIOB_PIN4 4U\r
-#define GPIOB_PIN5 5U\r
-#define GPIOB_PIN6 6U\r
-#define GPIOB_PIN7 7U\r
-#define GPIOB_PIN8 8U\r
-#define GPIOB_PIN9 9U\r
-#define GPIOB_PIN10 10U\r
-#define GPIOB_PIN11 11U\r
-#define GPIOB_PIN12 12U\r
-#define GPIOB_RMII_TXD1 13U\r
-#define GPIOB_LED3 14U\r
-#define GPIOB_LED_RED 14U\r
-#define GPIOB_PIN15 15U\r
-\r
-#define GPIOC_PIN0 0U\r
-#define GPIOC_RMII_MDC 1U\r
-#define GPIOC_PIN2 2U\r
-#define GPIOC_PIN3 3U\r
-#define GPIOC_RMII_RXD0 4U\r
-#define GPIOC_RMII_RXD1 5U\r
-#define GPIOC_PIN6 6U\r
-#define GPIOC_PIN7 7U\r
-#define GPIOC_PIN8 8U\r
-#define GPIOC_PIN9 9U\r
-#define GPIOC_PIN10 10U\r
-#define GPIOC_PIN11 11U\r
-#define GPIOC_PIN12 12U\r
-#define GPIOC_BUTTON 13U\r
-#define GPIOC_OSC32_IN 14U\r
-#define GPIOC_OSC32_OUT 15U\r
-\r
-#define GPIOD_PIN0 0U\r
-#define GPIOD_PIN1 1U\r
-#define GPIOD_PIN2 2U\r
-#define GPIOD_PIN3 3U\r
-#define GPIOD_PIN4 4U\r
-#define GPIOD_PIN5 5U\r
-#define GPIOD_PIN6 6U\r
-#define GPIOD_PIN7 7U\r
-#define GPIOD_USART3_RX 8U\r
-#define GPIOD_STLK_RX 8U\r
-#define GPIOD_USART3_TX 9U\r
-#define GPIOD_STLK_TX 9U\r
-#define GPIOD_PIN10 10U\r
-#define GPIOD_PIN11 11U\r
-#define GPIOD_PIN12 12U\r
-#define GPIOD_PIN13 13U\r
-#define GPIOD_PIN14 14U\r
-#define GPIOD_PIN15 15U\r
-\r
-#define GPIOE_PIN0 0U\r
-#define GPIOE_LED2 1U\r
-#define GPIOE_LED_YELLOW 1U\r
-#define GPIOE_PIN2 2U\r
-#define GPIOE_PIN3 3U\r
-#define GPIOE_PIN4 4U\r
-#define GPIOE_PIN5 5U\r
-#define GPIOE_PIN6 6U\r
-#define GPIOE_PIN7 7U\r
-#define GPIOE_PIN8 8U\r
-#define GPIOE_PIN9 9U\r
-#define GPIOE_PIN10 10U\r
-#define GPIOE_PIN11 11U\r
-#define GPIOE_PIN12 12U\r
-#define GPIOE_PIN13 13U\r
-#define GPIOE_PIN14 14U\r
-#define GPIOE_PIN15 15U\r
-\r
-#define GPIOF_PIN0 0U\r
-#define GPIOF_PIN1 1U\r
-#define GPIOF_PIN2 2U\r
-#define GPIOF_PIN3 3U\r
-#define GPIOF_PIN4 4U\r
-#define GPIOF_PIN5 5U\r
-#define GPIOF_PIN6 6U\r
-#define GPIOF_PIN7 7U\r
-#define GPIOF_PIN8 8U\r
-#define GPIOF_PIN9 9U\r
-#define GPIOF_PIN10 10U\r
-#define GPIOF_PIN11 11U\r
-#define GPIOF_PIN12 12U\r
-#define GPIOF_PIN13 13U\r
-#define GPIOF_PIN14 14U\r
-#define GPIOF_PIN15 15U\r
-\r
-#define GPIOG_PIN0 0U\r
-#define GPIOG_PIN1 1U\r
-#define GPIOG_PIN2 2U\r
-#define GPIOG_PIN3 3U\r
-#define GPIOG_PIN4 4U\r
-#define GPIOG_PIN5 5U\r
-#define GPIOG_USB_FS_PWR_EN 6U\r
-#define GPIOG_USB_FS_OVCR 7U\r
-#define GPIOG_PIN8 8U\r
-#define GPIOG_PIN9 9U\r
-#define GPIOG_PIN10 10U\r
-#define GPIOG_RMII_TX_EN 11U\r
-#define GPIOG_PIN12 12U\r
-#define GPIOG_RMII_TXD0 13U\r
-#define GPIOG_PIN14 14U\r
-#define GPIOG_PIN15 15U\r
-\r
-#define GPIOH_OSC_IN 0U\r
-#define GPIOH_OSC_OUT 1U\r
-#define GPIOH_PIN2 2U\r
-#define GPIOH_PIN3 3U\r
-#define GPIOH_PIN4 4U\r
-#define GPIOH_PIN5 5U\r
-#define GPIOH_PIN6 6U\r
-#define GPIOH_PIN7 7U\r
-#define GPIOH_PIN8 8U\r
-#define GPIOH_PIN9 9U\r
-#define GPIOH_PIN10 10U\r
-#define GPIOH_PIN11 11U\r
-#define GPIOH_PIN12 12U\r
-#define GPIOH_PIN13 13U\r
-#define GPIOH_PIN14 14U\r
-#define GPIOH_PIN15 15U\r
-\r
-#define GPIOI_PIN0 0U\r
-#define GPIOI_PIN1 1U\r
-#define GPIOI_PIN2 2U\r
-#define GPIOI_PIN3 3U\r
-#define GPIOI_PIN4 4U\r
-#define GPIOI_PIN5 5U\r
-#define GPIOI_PIN6 6U\r
-#define GPIOI_PIN7 7U\r
-#define GPIOI_PIN8 8U\r
-#define GPIOI_PIN9 9U\r
-#define GPIOI_PIN10 10U\r
-#define GPIOI_PIN11 11U\r
-#define GPIOI_PIN12 12U\r
-#define GPIOI_PIN13 13U\r
-#define GPIOI_PIN14 14U\r
-#define GPIOI_PIN15 15U\r
-\r
-#define GPIOJ_PIN0 0U\r
-#define GPIOJ_PIN1 1U\r
-#define GPIOJ_PIN2 2U\r
-#define GPIOJ_PIN3 3U\r
-#define GPIOJ_PIN4 4U\r
-#define GPIOJ_PIN5 5U\r
-#define GPIOJ_PIN6 6U\r
-#define GPIOJ_PIN7 7U\r
-#define GPIOJ_PIN8 8U\r
-#define GPIOJ_PIN9 9U\r
-#define GPIOJ_PIN10 10U\r
-#define GPIOJ_PIN11 11U\r
-#define GPIOJ_PIN12 12U\r
-#define GPIOJ_PIN13 13U\r
-#define GPIOJ_PIN14 14U\r
-#define GPIOJ_PIN15 15U\r
-\r
-#define GPIOK_PIN0 0U\r
-#define GPIOK_PIN1 1U\r
-#define GPIOK_PIN2 2U\r
-#define GPIOK_PIN3 3U\r
-#define GPIOK_PIN4 4U\r
-#define GPIOK_PIN5 5U\r
-#define GPIOK_PIN6 6U\r
-#define GPIOK_PIN7 7U\r
-#define GPIOK_PIN8 8U\r
-#define GPIOK_PIN9 9U\r
-#define GPIOK_PIN10 10U\r
-#define GPIOK_PIN11 11U\r
-#define GPIOK_PIN12 12U\r
-#define GPIOK_PIN13 13U\r
-#define GPIOK_PIN14 14U\r
-#define GPIOK_PIN15 15U\r
-\r
-/*\r
- * IO lines assignments.\r
- */\r
-#define LINE_RMII_REF_CLK PAL_LINE(GPIOA, 1U)\r
-#define LINE_RMII_MDIO PAL_LINE(GPIOA, 2U)\r
-#define LINE_RMII_CRS_DV PAL_LINE(GPIOA, 7U)\r
-#define LINE_USB_SOF PAL_LINE(GPIOA, 8U)\r
-#define LINE_MCO1 PAL_LINE(GPIOA, 8U)\r
-#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U)\r
-#define LINE_USB_ID PAL_LINE(GPIOA, 10U)\r
-#define LINE_USB_DM PAL_LINE(GPIOA, 11U)\r
-#define LINE_USB_DP PAL_LINE(GPIOA, 12U)\r
-#define LINE_SWDIO PAL_LINE(GPIOA, 13U)\r
-#define LINE_SWCLK PAL_LINE(GPIOA, 14U)\r
-#define LINE_T_JTDI PAL_LINE(GPIOA, 15U)\r
-#define LINE_LED1 PAL_LINE(GPIOB, 0U)\r
-#define LINE_LED_GREEN PAL_LINE(GPIOB, 0U)\r
-#define LINE_LED PAL_LINE(GPIOB, 0U)\r
-#define LINE_SWO PAL_LINE(GPIOB, 3U)\r
-#define LINE_LED2 PAL_LINE(GPIOE, 1U)\r
-#define LINE_LED_YELLOW PAL_LINE(GPIOE, 1U)\r
-#define LINE_RMII_TXD1 PAL_LINE(GPIOB, 13U)\r
-#define LINE_LED3 PAL_LINE(GPIOB, 14U)\r
-#define LINE_LED_RED PAL_LINE(GPIOB, 14U)\r
-#define LINE_RMII_MDC PAL_LINE(GPIOC, 1U)\r
-#define LINE_RMII_RXD0 PAL_LINE(GPIOC, 4U)\r
-#define LINE_RMII_RXD1 PAL_LINE(GPIOC, 5U)\r
-#define LINE_BUTTON PAL_LINE(GPIOC, 13U)\r
-#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)\r
-#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)\r
-#define LINE_USART3_RX PAL_LINE(GPIOD, 8U)\r
-#define LINE_STLK_RX PAL_LINE(GPIOD, 8U)\r
-#define LINE_USART3_TX PAL_LINE(GPIOD, 9U)\r
-#define LINE_STLK_TX PAL_LINE(GPIOD, 9U)\r
-#define LINE_USB_FS_PWR_EN PAL_LINE(GPIOG, 6U)\r
-#define LINE_USB_FS_OVCR PAL_LINE(GPIOG, 7U)\r
-#define LINE_RMII_TX_EN PAL_LINE(GPIOG, 11U)\r
-#define LINE_RMII_TXD0 PAL_LINE(GPIOG, 13U)\r
-#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)\r
-#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)\r
-\r
-/*===========================================================================*/\r
-/* Driver pre-compile time settings. */\r
-/*===========================================================================*/\r
-\r
-/*===========================================================================*/\r
-/* Derived constants and error checks. */\r
-/*===========================================================================*/\r
-\r
-/*===========================================================================*/\r
-/* Driver data structures and types. */\r
-/*===========================================================================*/\r
-\r
-/*===========================================================================*/\r
-/* Driver macros. */\r
-/*===========================================================================*/\r
-\r
-/*\r
- * I/O ports initial setup, this configuration is established soon after reset\r
- * in the initialization code.\r
- * Please refer to the STM32 Reference Manual for details.\r
- */\r
-#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))\r
-#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))\r
-#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))\r
-#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))\r
-#define PIN_ODR_LOW(n) (0U << (n))\r
-#define PIN_ODR_HIGH(n) (1U << (n))\r
-#define PIN_OTYPE_PUSHPULL(n) (0U << (n))\r
-#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))\r
-#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))\r
-#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))\r
-#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))\r
-#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))\r
-#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))\r
-#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))\r
-#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))\r
-#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))\r
-\r
-/*\r
- * GPIOA setup:\r
- *\r
- * PA0 - PIN0 (input pullup).\r
- * PA1 - RMII_REF_CLK (alternate 11).\r
- * PA2 - RMII_MDIO (alternate 11).\r
- * PA3 - PIN3 (input pullup).\r
- * PA4 - PIN4 (input pullup).\r
- * PA5 - PIN5 (input pullup).\r
- * PA6 - PIN6 (input pullup).\r
- * PA7 - RMII_CRS_DV (alternate 11).\r
- * PA8 - USB_SOF MCO1 (alternate 10).\r
- * PA9 - USB_VBUS (analog).\r
- * PA10 - USB_ID (alternate 10).\r
- * PA11 - USB_DM (alternate 10).\r
- * PA12 - USB_DP (alternate 10).\r
- * PA13 - SWDIO (alternate 0).\r
- * PA14 - SWCLK (alternate 0).\r
- * PA15 - T_JTDI (alternate 0).\r
- */\r
-#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \\r
- PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\\r
- PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \\r
- PIN_MODE_INPUT(GPIOA_PIN3) | \\r
- PIN_MODE_INPUT(GPIOA_PIN4) | \\r
- PIN_MODE_INPUT(GPIOA_PIN5) | \\r
- PIN_MODE_INPUT(GPIOA_PIN6) | \\r
- PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) |\\r
- PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \\r
- PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \\r
- PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \\r
- PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \\r
- PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \\r
- PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \\r
- PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \\r
- PIN_MODE_ALTERNATE(GPIOA_T_JTDI))\r
-#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\\r
- PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) |\\r
- PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_T_JTDI))\r
-#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \\r
- PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \\r
- PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \\r
- PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \\r
- PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \\r
- PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \\r
- PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \\r
- PIN_OSPEED_HIGH(GPIOA_RMII_CRS_DV) | \\r
- PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \\r
- PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \\r
- PIN_OSPEED_HIGH(GPIOA_USB_ID) | \\r
- PIN_OSPEED_HIGH(GPIOA_USB_DM) | \\r
- PIN_OSPEED_HIGH(GPIOA_USB_DP) | \\r
- PIN_OSPEED_HIGH(GPIOA_SWDIO) | \\r
- PIN_OSPEED_HIGH(GPIOA_SWCLK) | \\r
- PIN_OSPEED_HIGH(GPIOA_T_JTDI))\r
-#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \\r
- PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\\r
- PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) | \\r
- PIN_PUPDR_PULLUP(GPIOA_PIN3) | \\r
- PIN_PUPDR_PULLUP(GPIOA_PIN4) | \\r
- PIN_PUPDR_PULLUP(GPIOA_PIN5) | \\r
- PIN_PUPDR_PULLUP(GPIOA_PIN6) | \\r
- PIN_PUPDR_PULLUP(GPIOA_RMII_CRS_DV) | \\r
- PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \\r
- PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \\r
- PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \\r
- PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \\r
- PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \\r
- PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \\r
- PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \\r
- PIN_PUPDR_PULLUP(GPIOA_T_JTDI))\r
-#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \\r
- PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \\r
- PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \\r
- PIN_ODR_HIGH(GPIOA_PIN3) | \\r
- PIN_ODR_HIGH(GPIOA_PIN4) | \\r
- PIN_ODR_HIGH(GPIOA_PIN5) | \\r
- PIN_ODR_HIGH(GPIOA_PIN6) | \\r
- PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) | \\r
- PIN_ODR_HIGH(GPIOA_USB_SOF) | \\r
- PIN_ODR_HIGH(GPIOA_USB_VBUS) | \\r
- PIN_ODR_HIGH(GPIOA_USB_ID) | \\r
- PIN_ODR_HIGH(GPIOA_USB_DM) | \\r
- PIN_ODR_HIGH(GPIOA_USB_DP) | \\r
- PIN_ODR_HIGH(GPIOA_SWDIO) | \\r
- PIN_ODR_HIGH(GPIOA_SWCLK) | \\r
- PIN_ODR_HIGH(GPIOA_T_JTDI))\r
-#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \\r
- PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \\r
- PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) | \\r
- PIN_AFIO_AF(GPIOA_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOA_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOA_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOA_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11U))\r
-#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \\r
- PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \\r
- PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \\r
- PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \\r
- PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \\r
- PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \\r
- PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \\r
- PIN_AFIO_AF(GPIOA_T_JTDI, 0U))\r
-\r
-/*\r
- * GPIOB setup:\r
- *\r
- * PB0 - LED1 LED_GREEN LED (output pushpull maximum).\r
- * PB1 - PIN1 (input pullup).\r
- * PB2 - PIN2 (input pullup).\r
- * PB3 - SWO (alternate 0).\r
- * PB4 - PIN4 (input pullup).\r
- * PB5 - PIN5 (input pullup).\r
- * PB6 - PIN6 (input pullup).\r
- * PB7 - PIN7 (input pullup).\r
- * PB8 - PIN8 (input pullup).\r
- * PB9 - PIN9 (input pullup).\r
- * PB10 - PIN10 (input pullup).\r
- * PB11 - PIN11 (input pullup).\r
- * PB12 - PIN12 (input pullup).\r
- * PB13 - RMII_TXD1 (alternate 11).\r
- * PB14 - LED3 LED_RED (output pushpull maximum).\r
- * PB15 - PIN15 (input pullup).\r
- */\r
-#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_LED1) | \\r
- PIN_MODE_INPUT(GPIOB_PIN1) | \\r
- PIN_MODE_INPUT(GPIOB_PIN2) | \\r
- PIN_MODE_ALTERNATE(GPIOB_SWO) | \\r
- PIN_MODE_INPUT(GPIOB_PIN4) | \\r
- PIN_MODE_INPUT(GPIOB_PIN5) | \\r
- PIN_MODE_INPUT(GPIOB_PIN6) | \\r
- PIN_MODE_INPUT(GPIOB_PIN7) | \\r
- PIN_MODE_INPUT(GPIOB_PIN8) | \\r
- PIN_MODE_INPUT(GPIOB_PIN9) | \\r
- PIN_MODE_INPUT(GPIOB_PIN10) | \\r
- PIN_MODE_INPUT(GPIOB_PIN11) | \\r
- PIN_MODE_INPUT(GPIOB_PIN12) | \\r
- PIN_MODE_ALTERNATE(GPIOB_RMII_TXD1) | \\r
- PIN_MODE_OUTPUT(GPIOB_LED3) | \\r
- PIN_MODE_INPUT(GPIOB_PIN15))\r
-#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_LED1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_RMII_TXD1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN15))\r
-#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_LED1) | \\r
- PIN_OSPEED_VERYLOW(GPIOB_PIN1) | \\r
- PIN_OSPEED_VERYLOW(GPIOB_PIN2) | \\r
- PIN_OSPEED_HIGH(GPIOB_SWO) | \\r
- PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \\r
- PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \\r
- PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \\r
- PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \\r
- PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \\r
- PIN_OSPEED_VERYLOW(GPIOB_PIN9) | \\r
- PIN_OSPEED_VERYLOW(GPIOB_PIN10) | \\r
- PIN_OSPEED_VERYLOW(GPIOB_PIN11) | \\r
- PIN_OSPEED_VERYLOW(GPIOB_PIN12) | \\r
- PIN_OSPEED_HIGH(GPIOB_RMII_TXD1) | \\r
- PIN_OSPEED_HIGH(GPIOB_LED3) | \\r
- PIN_OSPEED_VERYLOW(GPIOB_PIN15))\r
-#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_LED1) | \\r
- PIN_PUPDR_PULLUP(GPIOB_PIN1) | \\r
- PIN_PUPDR_PULLUP(GPIOB_PIN2) | \\r
- PIN_PUPDR_PULLUP(GPIOB_SWO) | \\r
- PIN_PUPDR_PULLUP(GPIOB_PIN4) | \\r
- PIN_PUPDR_PULLUP(GPIOB_PIN5) | \\r
- PIN_PUPDR_PULLUP(GPIOB_PIN6) | \\r
- PIN_PUPDR_PULLUP(GPIOB_PIN7) | \\r
- PIN_PUPDR_PULLUP(GPIOB_PIN8) | \\r
- PIN_PUPDR_PULLUP(GPIOB_PIN9) | \\r
- PIN_PUPDR_PULLUP(GPIOB_PIN10) | \\r
- PIN_PUPDR_PULLUP(GPIOB_PIN11) | \\r
- PIN_PUPDR_PULLUP(GPIOB_PIN12) | \\r
- PIN_PUPDR_PULLUP(GPIOB_RMII_TXD1) | \\r
- PIN_PUPDR_FLOATING(GPIOB_LED3) | \\r
- PIN_PUPDR_PULLUP(GPIOB_PIN15))\r
-#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_LED1) | \\r
- PIN_ODR_HIGH(GPIOB_PIN1) | \\r
- PIN_ODR_HIGH(GPIOB_PIN2) | \\r
- PIN_ODR_HIGH(GPIOB_SWO) | \\r
- PIN_ODR_HIGH(GPIOB_PIN4) | \\r
- PIN_ODR_HIGH(GPIOB_PIN5) | \\r
- PIN_ODR_HIGH(GPIOB_PIN6) | \\r
- PIN_ODR_HIGH(GPIOB_PIN7) | \\r
- PIN_ODR_HIGH(GPIOB_PIN8) | \\r
- PIN_ODR_HIGH(GPIOB_PIN9) | \\r
- PIN_ODR_HIGH(GPIOB_PIN10) | \\r
- PIN_ODR_HIGH(GPIOB_PIN11) | \\r
- PIN_ODR_HIGH(GPIOB_PIN12) | \\r
- PIN_ODR_HIGH(GPIOB_RMII_TXD1) | \\r
- PIN_ODR_LOW(GPIOB_LED3) | \\r
- PIN_ODR_HIGH(GPIOB_PIN15))\r
-#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_LED1, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN1, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOB_SWO, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN7, 0U))\r
-#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOB_RMII_TXD1, 11U) | \\r
- PIN_AFIO_AF(GPIOB_LED3, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN15, 0U))\r
-\r
-/*\r
- * GPIOC setup:\r
- *\r
- * PC0 - PIN0 (input pullup).\r
- * PC1 - RMII_MDC (alternate 11).\r
- * PC2 - PIN2 (input pullup).\r
- * PC3 - PIN3 (input pullup).\r
- * PC4 - RMII_RXD0 (alternate 11).\r
- * PC5 - RMII_RXD1 (alternate 11).\r
- * PC6 - PIN6 (input pullup).\r
- * PC7 - PIN7 (input pullup).\r
- * PC8 - PIN8 (input pullup).\r
- * PC9 - PIN9 (input pullup).\r
- * PC10 - PIN10 (input pullup).\r
- * PC11 - PIN11 (input pullup).\r
- * PC12 - PIN12 (input pullup).\r
- * PC13 - BUTTON (input floating).\r
- * PC14 - OSC32_IN (input floating).\r
- * PC15 - OSC32_OUT (input floating).\r
- */\r
-#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \\r
- PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \\r
- PIN_MODE_INPUT(GPIOC_PIN2) | \\r
- PIN_MODE_INPUT(GPIOC_PIN3) | \\r
- PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \\r
- PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \\r
- PIN_MODE_INPUT(GPIOC_PIN6) | \\r
- PIN_MODE_INPUT(GPIOC_PIN7) | \\r
- PIN_MODE_INPUT(GPIOC_PIN8) | \\r
- PIN_MODE_INPUT(GPIOC_PIN9) | \\r
- PIN_MODE_INPUT(GPIOC_PIN10) | \\r
- PIN_MODE_INPUT(GPIOC_PIN11) | \\r
- PIN_MODE_INPUT(GPIOC_PIN12) | \\r
- PIN_MODE_INPUT(GPIOC_BUTTON) | \\r
- PIN_MODE_INPUT(GPIOC_OSC32_IN) | \\r
- PIN_MODE_INPUT(GPIOC_OSC32_OUT))\r
-#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))\r
-#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | \\r
- PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \\r
- PIN_OSPEED_VERYLOW(GPIOC_PIN2) | \\r
- PIN_OSPEED_VERYLOW(GPIOC_PIN3) | \\r
- PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \\r
- PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \\r
- PIN_OSPEED_VERYLOW(GPIOC_PIN6) | \\r
- PIN_OSPEED_VERYLOW(GPIOC_PIN7) | \\r
- PIN_OSPEED_VERYLOW(GPIOC_PIN8) | \\r
- PIN_OSPEED_VERYLOW(GPIOC_PIN9) | \\r
- PIN_OSPEED_VERYLOW(GPIOC_PIN10) | \\r
- PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \\r
- PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \\r
- PIN_OSPEED_HIGH(GPIOC_BUTTON) | \\r
- PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \\r
- PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT))\r
-#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \\r
- PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \\r
- PIN_PUPDR_PULLUP(GPIOC_PIN2) | \\r
- PIN_PUPDR_PULLUP(GPIOC_PIN3) | \\r
- PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \\r
- PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \\r
- PIN_PUPDR_PULLUP(GPIOC_PIN6) | \\r
- PIN_PUPDR_PULLUP(GPIOC_PIN7) | \\r
- PIN_PUPDR_PULLUP(GPIOC_PIN8) | \\r
- PIN_PUPDR_PULLUP(GPIOC_PIN9) | \\r
- PIN_PUPDR_PULLUP(GPIOC_PIN10) | \\r
- PIN_PUPDR_PULLUP(GPIOC_PIN11) | \\r
- PIN_PUPDR_PULLUP(GPIOC_PIN12) | \\r
- PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \\r
- PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \\r
- PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))\r
-#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \\r
- PIN_ODR_HIGH(GPIOC_RMII_MDC) | \\r
- PIN_ODR_HIGH(GPIOC_PIN2) | \\r
- PIN_ODR_HIGH(GPIOC_PIN3) | \\r
- PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \\r
- PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \\r
- PIN_ODR_HIGH(GPIOC_PIN6) | \\r
- PIN_ODR_HIGH(GPIOC_PIN7) | \\r
- PIN_ODR_HIGH(GPIOC_PIN8) | \\r
- PIN_ODR_HIGH(GPIOC_PIN9) | \\r
- PIN_ODR_HIGH(GPIOC_PIN10) | \\r
- PIN_ODR_HIGH(GPIOC_PIN11) | \\r
- PIN_ODR_HIGH(GPIOC_PIN12) | \\r
- PIN_ODR_HIGH(GPIOC_BUTTON) | \\r
- PIN_ODR_HIGH(GPIOC_OSC32_IN) | \\r
- PIN_ODR_HIGH(GPIOC_OSC32_OUT))\r
-#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \\r
- PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) | \\r
- PIN_AFIO_AF(GPIOC_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) | \\r
- PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) | \\r
- PIN_AFIO_AF(GPIOC_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN7, 0U))\r
-#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \\r
- PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \\r
- PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))\r
-\r
-/*\r
- * GPIOD setup:\r
- *\r
- * PD0 - PIN0 (input pullup).\r
- * PD1 - PIN1 (input pullup).\r
- * PD2 - PIN2 (input pullup).\r
- * PD3 - PIN3 (input pullup).\r
- * PD4 - PIN4 (input pullup).\r
- * PD5 - PIN5 (input pullup).\r
- * PD6 - PIN6 (input pullup).\r
- * PD7 - PIN7 (input pullup).\r
- * PD8 - USART3_RX STLK_RX (alternate 7).\r
- * PD9 - USART3_TX STLK_TX (alternate 7).\r
- * PD10 - PIN10 (input pullup).\r
- * PD11 - PIN11 (input pullup).\r
- * PD12 - PIN12 (input pullup).\r
- * PD13 - PIN13 (input pullup).\r
- * PD14 - PIN14 (input pullup).\r
- * PD15 - PIN15 (input pullup).\r
- */\r
-#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \\r
- PIN_MODE_INPUT(GPIOD_PIN1) | \\r
- PIN_MODE_INPUT(GPIOD_PIN2) | \\r
- PIN_MODE_INPUT(GPIOD_PIN3) | \\r
- PIN_MODE_INPUT(GPIOD_PIN4) | \\r
- PIN_MODE_INPUT(GPIOD_PIN5) | \\r
- PIN_MODE_INPUT(GPIOD_PIN6) | \\r
- PIN_MODE_INPUT(GPIOD_PIN7) | \\r
- PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \\r
- PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \\r
- PIN_MODE_INPUT(GPIOD_PIN10) | \\r
- PIN_MODE_INPUT(GPIOD_PIN11) | \\r
- PIN_MODE_INPUT(GPIOD_PIN12) | \\r
- PIN_MODE_INPUT(GPIOD_PIN13) | \\r
- PIN_MODE_INPUT(GPIOD_PIN14) | \\r
- PIN_MODE_INPUT(GPIOD_PIN15))\r
-#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN15))\r
-#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | \\r
- PIN_OSPEED_VERYLOW(GPIOD_PIN1) | \\r
- PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \\r
- PIN_OSPEED_VERYLOW(GPIOD_PIN3) | \\r
- PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \\r
- PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \\r
- PIN_OSPEED_VERYLOW(GPIOD_PIN6) | \\r
- PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \\r
- PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \\r
- PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \\r
- PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \\r
- PIN_OSPEED_VERYLOW(GPIOD_PIN11) | \\r
- PIN_OSPEED_VERYLOW(GPIOD_PIN12) | \\r
- PIN_OSPEED_VERYLOW(GPIOD_PIN13) | \\r
- PIN_OSPEED_VERYLOW(GPIOD_PIN14) | \\r
- PIN_OSPEED_VERYLOW(GPIOD_PIN15))\r
-#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \\r
- PIN_PUPDR_PULLUP(GPIOD_PIN1) | \\r
- PIN_PUPDR_PULLUP(GPIOD_PIN2) | \\r
- PIN_PUPDR_PULLUP(GPIOD_PIN3) | \\r
- PIN_PUPDR_PULLUP(GPIOD_PIN4) | \\r
- PIN_PUPDR_PULLUP(GPIOD_PIN5) | \\r
- PIN_PUPDR_PULLUP(GPIOD_PIN6) | \\r
- PIN_PUPDR_PULLUP(GPIOD_PIN7) | \\r
- PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \\r
- PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \\r
- PIN_PUPDR_PULLUP(GPIOD_PIN10) | \\r
- PIN_PUPDR_PULLUP(GPIOD_PIN11) | \\r
- PIN_PUPDR_PULLUP(GPIOD_PIN12) | \\r
- PIN_PUPDR_PULLUP(GPIOD_PIN13) | \\r
- PIN_PUPDR_PULLUP(GPIOD_PIN14) | \\r
- PIN_PUPDR_PULLUP(GPIOD_PIN15))\r
-#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \\r
- PIN_ODR_HIGH(GPIOD_PIN1) | \\r
- PIN_ODR_HIGH(GPIOD_PIN2) | \\r
- PIN_ODR_HIGH(GPIOD_PIN3) | \\r
- PIN_ODR_HIGH(GPIOD_PIN4) | \\r
- PIN_ODR_HIGH(GPIOD_PIN5) | \\r
- PIN_ODR_HIGH(GPIOD_PIN6) | \\r
- PIN_ODR_HIGH(GPIOD_PIN7) | \\r
- PIN_ODR_HIGH(GPIOD_USART3_RX) | \\r
- PIN_ODR_HIGH(GPIOD_USART3_TX) | \\r
- PIN_ODR_HIGH(GPIOD_PIN10) | \\r
- PIN_ODR_HIGH(GPIOD_PIN11) | \\r
- PIN_ODR_HIGH(GPIOD_PIN12) | \\r
- PIN_ODR_HIGH(GPIOD_PIN13) | \\r
- PIN_ODR_HIGH(GPIOD_PIN14) | \\r
- PIN_ODR_HIGH(GPIOD_PIN15))\r
-#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN1, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN7, 0U))\r
-#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \\r
- PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \\r
- PIN_AFIO_AF(GPIOD_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN13, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN15, 0U))\r
-\r
-/*\r
- * GPIOE setup:\r
- *\r
- * PE0 - PIN0 (input pullup).\r
- * PE1 - PIN1 (input pullup).\r
- * PE2 - PIN2 (input pullup).\r
- * PE3 - PIN3 (input pullup).\r
- * PE4 - PIN4 (input pullup).\r
- * PE5 - PIN5 (input pullup).\r
- * PE6 - PIN6 (input pullup).\r
- * PE7 - PIN7 (input pullup).\r
- * PE8 - PIN8 (input pullup).\r
- * PE9 - PIN9 (input pullup).\r
- * PE10 - PIN10 (input pullup).\r
- * PE11 - PIN11 (input pullup).\r
- * PE12 - PIN12 (input pullup).\r
- * PE13 - PIN13 (input pullup).\r
- * PE14 - PIN14 (input pullup).\r
- * PE15 - PIN15 (input pullup).\r
- */\r
-#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \\r
- PIN_MODE_OUTPUT(GPIOE_LED2) | \\r
- PIN_MODE_INPUT(GPIOE_PIN2) | \\r
- PIN_MODE_INPUT(GPIOE_PIN3) | \\r
- PIN_MODE_INPUT(GPIOE_PIN4) | \\r
- PIN_MODE_INPUT(GPIOE_PIN5) | \\r
- PIN_MODE_INPUT(GPIOE_PIN6) | \\r
- PIN_MODE_INPUT(GPIOE_PIN7) | \\r
- PIN_MODE_INPUT(GPIOE_PIN8) | \\r
- PIN_MODE_INPUT(GPIOE_PIN9) | \\r
- PIN_MODE_INPUT(GPIOE_PIN10) | \\r
- PIN_MODE_INPUT(GPIOE_PIN11) | \\r
- PIN_MODE_INPUT(GPIOE_PIN12) | \\r
- PIN_MODE_INPUT(GPIOE_PIN13) | \\r
- PIN_MODE_INPUT(GPIOE_PIN14) | \\r
- PIN_MODE_INPUT(GPIOE_PIN15))\r
-#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_LED2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN15))\r
-#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | \\r
- PIN_OSPEED_HIGH(GPIOE_LED2) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN7) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN8) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN9) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN10) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN11) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN12) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN13) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN14) | \\r
- PIN_OSPEED_VERYLOW(GPIOE_PIN15))\r
-#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \\r
- PIN_PUPDR_PULLUP(GPIOE_LED2) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN2) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN3) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN4) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN5) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN6) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN7) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN8) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN9) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN10) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN11) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN12) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN13) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN14) | \\r
- PIN_PUPDR_PULLUP(GPIOE_PIN15))\r
-#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \\r
- PIN_ODR_LOW(GPIOE_LED2) | \\r
- PIN_ODR_HIGH(GPIOE_PIN2) | \\r
- PIN_ODR_HIGH(GPIOE_PIN3) | \\r
- PIN_ODR_HIGH(GPIOE_PIN4) | \\r
- PIN_ODR_HIGH(GPIOE_PIN5) | \\r
- PIN_ODR_HIGH(GPIOE_PIN6) | \\r
- PIN_ODR_HIGH(GPIOE_PIN7) | \\r
- PIN_ODR_HIGH(GPIOE_PIN8) | \\r
- PIN_ODR_HIGH(GPIOE_PIN9) | \\r
- PIN_ODR_HIGH(GPIOE_PIN10) | \\r
- PIN_ODR_HIGH(GPIOE_PIN11) | \\r
- PIN_ODR_HIGH(GPIOE_PIN12) | \\r
- PIN_ODR_HIGH(GPIOE_PIN13) | \\r
- PIN_ODR_HIGH(GPIOE_PIN14) | \\r
- PIN_ODR_HIGH(GPIOE_PIN15))\r
-#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \\r
- PIN_AFIO_AF(GPIOE_LED2, 0U)) | \\r
- PIN_AFIO_AF(GPIOE_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN7, 0U)\r
-#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN13, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN15, 0U))\r
-\r
-/*\r
- * GPIOF setup:\r
- *\r
- * PF0 - PIN0 (input pullup).\r
- * PF1 - PIN1 (input pullup).\r
- * PF2 - PIN2 (input pullup).\r
- * PF3 - PIN3 (input pullup).\r
- * PF4 - PIN4 (input pullup).\r
- * PF5 - PIN5 (input pullup).\r
- * PF6 - PIN6 (input pullup).\r
- * PF7 - PIN7 (input pullup).\r
- * PF8 - PIN8 (input pullup).\r
- * PF9 - PIN9 (input pullup).\r
- * PF10 - PIN10 (input pullup).\r
- * PF11 - PIN11 (input pullup).\r
- * PF12 - PIN12 (input pullup).\r
- * PF13 - PIN13 (input pullup).\r
- * PF14 - PIN14 (input pullup).\r
- * PF15 - PIN15 (input pullup).\r
- */\r
-#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \\r
- PIN_MODE_INPUT(GPIOF_PIN1) | \\r
- PIN_MODE_INPUT(GPIOF_PIN2) | \\r
- PIN_MODE_INPUT(GPIOF_PIN3) | \\r
- PIN_MODE_INPUT(GPIOF_PIN4) | \\r
- PIN_MODE_INPUT(GPIOF_PIN5) | \\r
- PIN_MODE_INPUT(GPIOF_PIN6) | \\r
- PIN_MODE_INPUT(GPIOF_PIN7) | \\r
- PIN_MODE_INPUT(GPIOF_PIN8) | \\r
- PIN_MODE_INPUT(GPIOF_PIN9) | \\r
- PIN_MODE_INPUT(GPIOF_PIN10) | \\r
- PIN_MODE_INPUT(GPIOF_PIN11) | \\r
- PIN_MODE_INPUT(GPIOF_PIN12) | \\r
- PIN_MODE_INPUT(GPIOF_PIN13) | \\r
- PIN_MODE_INPUT(GPIOF_PIN14) | \\r
- PIN_MODE_INPUT(GPIOF_PIN15))\r
-#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN15))\r
-#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_PIN0) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN1) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN2) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN3) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN4) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN5) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN7) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN8) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN9) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN10) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN12) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN13) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN14) | \\r
- PIN_OSPEED_VERYLOW(GPIOF_PIN15))\r
-#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN1) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN2) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN3) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN4) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN5) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN6) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN7) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN8) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN9) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN10) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN11) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN12) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN13) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN14) | \\r
- PIN_PUPDR_PULLUP(GPIOF_PIN15))\r
-#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \\r
- PIN_ODR_HIGH(GPIOF_PIN1) | \\r
- PIN_ODR_HIGH(GPIOF_PIN2) | \\r
- PIN_ODR_HIGH(GPIOF_PIN3) | \\r
- PIN_ODR_HIGH(GPIOF_PIN4) | \\r
- PIN_ODR_HIGH(GPIOF_PIN5) | \\r
- PIN_ODR_HIGH(GPIOF_PIN6) | \\r
- PIN_ODR_HIGH(GPIOF_PIN7) | \\r
- PIN_ODR_HIGH(GPIOF_PIN8) | \\r
- PIN_ODR_HIGH(GPIOF_PIN9) | \\r
- PIN_ODR_HIGH(GPIOF_PIN10) | \\r
- PIN_ODR_HIGH(GPIOF_PIN11) | \\r
- PIN_ODR_HIGH(GPIOF_PIN12) | \\r
- PIN_ODR_HIGH(GPIOF_PIN13) | \\r
- PIN_ODR_HIGH(GPIOF_PIN14) | \\r
- PIN_ODR_HIGH(GPIOF_PIN15))\r
-#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN1, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN7, 0U))\r
-#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN13, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN15, 0U))\r
-\r
-/*\r
- * GPIOG setup:\r
- *\r
- * PG0 - PIN0 (input pullup).\r
- * PG1 - PIN1 (input pullup).\r
- * PG2 - PIN2 (input pullup).\r
- * PG3 - PIN3 (input pullup).\r
- * PG4 - PIN4 (input pullup).\r
- * PG5 - PIN5 (input pullup).\r
- * PG6 - USB_FS_PWR_EN (output pushpull minimum).\r
- * PG7 - USB_FS_OVCR (input floating).\r
- * PG8 - PIN8 (input pullup).\r
- * PG9 - PIN9 (input pullup).\r
- * PG10 - PIN10 (input pullup).\r
- * PG11 - RMII_TX_EN (alternate 11).\r
- * PG12 - PIN12 (input pullup).\r
- * PG13 - RMII_TXD0 (alternate 11).\r
- * PG14 - PIN14 (input pullup).\r
- * PG15 - PIN15 (input pullup).\r
- */\r
-#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \\r
- PIN_MODE_INPUT(GPIOG_PIN1) | \\r
- PIN_MODE_INPUT(GPIOG_PIN2) | \\r
- PIN_MODE_INPUT(GPIOG_PIN3) | \\r
- PIN_MODE_INPUT(GPIOG_PIN4) | \\r
- PIN_MODE_INPUT(GPIOG_PIN5) | \\r
- PIN_MODE_OUTPUT(GPIOG_USB_FS_PWR_EN) | \\r
- PIN_MODE_INPUT(GPIOG_USB_FS_OVCR) | \\r
- PIN_MODE_INPUT(GPIOG_PIN8) | \\r
- PIN_MODE_INPUT(GPIOG_PIN9) | \\r
- PIN_MODE_INPUT(GPIOG_PIN10) | \\r
- PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \\r
- PIN_MODE_INPUT(GPIOG_PIN12) | \\r
- PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \\r
- PIN_MODE_INPUT(GPIOG_PIN14) | \\r
- PIN_MODE_INPUT(GPIOG_PIN15))\r
-#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_USB_FS_PWR_EN) |\\r
- PIN_OTYPE_PUSHPULL(GPIOG_USB_FS_OVCR) |\\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN15))\r
-#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_USB_FS_PWR_EN) |\\r
- PIN_OSPEED_VERYLOW(GPIOG_USB_FS_OVCR) |\\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \\r
- PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \\r
- PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN15))\r
-#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \\r
- PIN_PUPDR_PULLUP(GPIOG_PIN1) | \\r
- PIN_PUPDR_PULLUP(GPIOG_PIN2) | \\r
- PIN_PUPDR_PULLUP(GPIOG_PIN3) | \\r
- PIN_PUPDR_PULLUP(GPIOG_PIN4) | \\r
- PIN_PUPDR_PULLUP(GPIOG_PIN5) | \\r
- PIN_PUPDR_FLOATING(GPIOG_USB_FS_PWR_EN) |\\r
- PIN_PUPDR_FLOATING(GPIOG_USB_FS_OVCR) |\\r
- PIN_PUPDR_PULLUP(GPIOG_PIN8) | \\r
- PIN_PUPDR_PULLUP(GPIOG_PIN9) | \\r
- PIN_PUPDR_PULLUP(GPIOG_PIN10) | \\r
- PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \\r
- PIN_PUPDR_PULLUP(GPIOG_PIN12) | \\r
- PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \\r
- PIN_PUPDR_PULLUP(GPIOG_PIN14) | \\r
- PIN_PUPDR_PULLUP(GPIOG_PIN15))\r
-#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \\r
- PIN_ODR_HIGH(GPIOG_PIN1) | \\r
- PIN_ODR_HIGH(GPIOG_PIN2) | \\r
- PIN_ODR_HIGH(GPIOG_PIN3) | \\r
- PIN_ODR_HIGH(GPIOG_PIN4) | \\r
- PIN_ODR_HIGH(GPIOG_PIN5) | \\r
- PIN_ODR_LOW(GPIOG_USB_FS_PWR_EN) | \\r
- PIN_ODR_HIGH(GPIOG_USB_FS_OVCR) | \\r
- PIN_ODR_HIGH(GPIOG_PIN8) | \\r
- PIN_ODR_HIGH(GPIOG_PIN9) | \\r
- PIN_ODR_HIGH(GPIOG_PIN10) | \\r
- PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \\r
- PIN_ODR_HIGH(GPIOG_PIN12) | \\r
- PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \\r
- PIN_ODR_HIGH(GPIOG_PIN14) | \\r
- PIN_ODR_HIGH(GPIOG_PIN15))\r
-#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN1, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOG_USB_FS_PWR_EN, 0U) | \\r
- PIN_AFIO_AF(GPIOG_USB_FS_OVCR, 0U))\r
-#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) | \\r
- PIN_AFIO_AF(GPIOG_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) | \\r
- PIN_AFIO_AF(GPIOG_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN15, 0U))\r
-\r
-/*\r
- * GPIOH setup:\r
- *\r
- * PH0 - OSC_IN (input floating).\r
- * PH1 - OSC_OUT (input floating).\r
- * PH2 - PIN2 (input pullup).\r
- * PH3 - PIN3 (input pullup).\r
- * PH4 - PIN4 (input pullup).\r
- * PH5 - PIN5 (input pullup).\r
- * PH6 - PIN6 (input pullup).\r
- * PH7 - PIN7 (input pullup).\r
- * PH8 - PIN8 (input pullup).\r
- * PH9 - PIN9 (input pullup).\r
- * PH10 - PIN10 (input pullup).\r
- * PH11 - PIN11 (input pullup).\r
- * PH12 - PIN12 (input pullup).\r
- * PH13 - PIN13 (input pullup).\r
- * PH14 - PIN14 (input pullup).\r
- * PH15 - PIN15 (input pullup).\r
- */\r
-#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \\r
- PIN_MODE_INPUT(GPIOH_OSC_OUT) | \\r
- PIN_MODE_INPUT(GPIOH_PIN2) | \\r
- PIN_MODE_INPUT(GPIOH_PIN3) | \\r
- PIN_MODE_INPUT(GPIOH_PIN4) | \\r
- PIN_MODE_INPUT(GPIOH_PIN5) | \\r
- PIN_MODE_INPUT(GPIOH_PIN6) | \\r
- PIN_MODE_INPUT(GPIOH_PIN7) | \\r
- PIN_MODE_INPUT(GPIOH_PIN8) | \\r
- PIN_MODE_INPUT(GPIOH_PIN9) | \\r
- PIN_MODE_INPUT(GPIOH_PIN10) | \\r
- PIN_MODE_INPUT(GPIOH_PIN11) | \\r
- PIN_MODE_INPUT(GPIOH_PIN12) | \\r
- PIN_MODE_INPUT(GPIOH_PIN13) | \\r
- PIN_MODE_INPUT(GPIOH_PIN14) | \\r
- PIN_MODE_INPUT(GPIOH_PIN15))\r
-#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN15))\r
-#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \\r
- PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN15))\r
-#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \\r
- PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN2) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN3) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN4) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN5) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN6) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN7) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN8) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN9) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN10) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN11) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN12) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN13) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN14) | \\r
- PIN_PUPDR_PULLUP(GPIOH_PIN15))\r
-#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \\r
- PIN_ODR_HIGH(GPIOH_OSC_OUT) | \\r
- PIN_ODR_HIGH(GPIOH_PIN2) | \\r
- PIN_ODR_HIGH(GPIOH_PIN3) | \\r
- PIN_ODR_HIGH(GPIOH_PIN4) | \\r
- PIN_ODR_HIGH(GPIOH_PIN5) | \\r
- PIN_ODR_HIGH(GPIOH_PIN6) | \\r
- PIN_ODR_HIGH(GPIOH_PIN7) | \\r
- PIN_ODR_HIGH(GPIOH_PIN8) | \\r
- PIN_ODR_HIGH(GPIOH_PIN9) | \\r
- PIN_ODR_HIGH(GPIOH_PIN10) | \\r
- PIN_ODR_HIGH(GPIOH_PIN11) | \\r
- PIN_ODR_HIGH(GPIOH_PIN12) | \\r
- PIN_ODR_HIGH(GPIOH_PIN13) | \\r
- PIN_ODR_HIGH(GPIOH_PIN14) | \\r
- PIN_ODR_HIGH(GPIOH_PIN15))\r
-#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \\r
- PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN7, 0U))\r
-#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN13, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN15, 0U))\r
-\r
-/*\r
- * GPIOI setup:\r
- *\r
- * PI0 - PIN0 (input pullup).\r
- * PI1 - PIN1 (input pullup).\r
- * PI2 - PIN2 (input pullup).\r
- * PI3 - PIN3 (input pullup).\r
- * PI4 - PIN4 (input pullup).\r
- * PI5 - PIN5 (input pullup).\r
- * PI6 - PIN6 (input pullup).\r
- * PI7 - PIN7 (input pullup).\r
- * PI8 - PIN8 (input pullup).\r
- * PI9 - PIN9 (input pullup).\r
- * PI10 - PIN10 (input pullup).\r
- * PI11 - PIN11 (input pullup).\r
- * PI12 - PIN12 (input pullup).\r
- * PI13 - PIN13 (input pullup).\r
- * PI14 - PIN14 (input pullup).\r
- * PI15 - PIN15 (input pullup).\r
- */\r
-#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \\r
- PIN_MODE_INPUT(GPIOI_PIN1) | \\r
- PIN_MODE_INPUT(GPIOI_PIN2) | \\r
- PIN_MODE_INPUT(GPIOI_PIN3) | \\r
- PIN_MODE_INPUT(GPIOI_PIN4) | \\r
- PIN_MODE_INPUT(GPIOI_PIN5) | \\r
- PIN_MODE_INPUT(GPIOI_PIN6) | \\r
- PIN_MODE_INPUT(GPIOI_PIN7) | \\r
- PIN_MODE_INPUT(GPIOI_PIN8) | \\r
- PIN_MODE_INPUT(GPIOI_PIN9) | \\r
- PIN_MODE_INPUT(GPIOI_PIN10) | \\r
- PIN_MODE_INPUT(GPIOI_PIN11) | \\r
- PIN_MODE_INPUT(GPIOI_PIN12) | \\r
- PIN_MODE_INPUT(GPIOI_PIN13) | \\r
- PIN_MODE_INPUT(GPIOI_PIN14) | \\r
- PIN_MODE_INPUT(GPIOI_PIN15))\r
-#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOI_PIN15))\r
-#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \\r
- PIN_OSPEED_VERYLOW(GPIOI_PIN15))\r
-#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN1) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN2) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN3) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN4) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN5) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN6) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN7) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN8) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN9) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN10) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN11) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN12) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN13) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN14) | \\r
- PIN_PUPDR_PULLUP(GPIOI_PIN15))\r
-#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \\r
- PIN_ODR_HIGH(GPIOI_PIN1) | \\r
- PIN_ODR_HIGH(GPIOI_PIN2) | \\r
- PIN_ODR_HIGH(GPIOI_PIN3) | \\r
- PIN_ODR_HIGH(GPIOI_PIN4) | \\r
- PIN_ODR_HIGH(GPIOI_PIN5) | \\r
- PIN_ODR_HIGH(GPIOI_PIN6) | \\r
- PIN_ODR_HIGH(GPIOI_PIN7) | \\r
- PIN_ODR_HIGH(GPIOI_PIN8) | \\r
- PIN_ODR_HIGH(GPIOI_PIN9) | \\r
- PIN_ODR_HIGH(GPIOI_PIN10) | \\r
- PIN_ODR_HIGH(GPIOI_PIN11) | \\r
- PIN_ODR_HIGH(GPIOI_PIN12) | \\r
- PIN_ODR_HIGH(GPIOI_PIN13) | \\r
- PIN_ODR_HIGH(GPIOI_PIN14) | \\r
- PIN_ODR_HIGH(GPIOI_PIN15))\r
-#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN1, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN7, 0U))\r
-#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN13, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOI_PIN15, 0U))\r
-\r
-/*\r
- * GPIOJ setup:\r
- *\r
- * PJ0 - PIN0 (input pullup).\r
- * PJ1 - PIN1 (input pullup).\r
- * PJ2 - PIN2 (input pullup).\r
- * PJ3 - PIN3 (input pullup).\r
- * PJ4 - PIN4 (input pullup).\r
- * PJ5 - PIN5 (input pullup).\r
- * PJ6 - PIN6 (input pullup).\r
- * PJ7 - PIN7 (input pullup).\r
- * PJ8 - PIN8 (input pullup).\r
- * PJ9 - PIN9 (input pullup).\r
- * PJ10 - PIN10 (input pullup).\r
- * PJ11 - PIN11 (input pullup).\r
- * PJ12 - PIN12 (input pullup).\r
- * PJ13 - PIN13 (input pullup).\r
- * PJ14 - PIN14 (input pullup).\r
- * PJ15 - PIN15 (input pullup).\r
- */\r
-#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN1) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN2) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN3) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN4) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN5) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN6) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN7) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN8) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN9) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN10) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN11) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN12) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN13) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN14) | \\r
- PIN_MODE_INPUT(GPIOJ_PIN15))\r
-#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOJ_PIN15))\r
-#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN1) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN2) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN3) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN4) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN5) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN12) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN13) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN14) | \\r
- PIN_OSPEED_VERYLOW(GPIOJ_PIN15))\r
-#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLUP(GPIOJ_PIN0) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN1) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN2) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN3) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN4) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN5) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN6) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN7) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN8) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN9) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN10) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN11) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN12) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN13) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN14) | \\r
- PIN_PUPDR_PULLUP(GPIOJ_PIN15))\r
-#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN1) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN2) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN3) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN4) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN5) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN6) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN7) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN8) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN9) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN10) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN11) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN12) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN13) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN14) | \\r
- PIN_ODR_HIGH(GPIOJ_PIN15))\r
-#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN7, 0U))\r
-#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOJ_PIN15, 0U))\r
-\r
-/*\r
- * GPIOK setup:\r
- *\r
- * PK0 - PIN0 (input pullup).\r
- * PK1 - PIN1 (input pullup).\r
- * PK2 - PIN2 (input pullup).\r
- * PK3 - PIN3 (input pullup).\r
- * PK4 - PIN4 (input pullup).\r
- * PK5 - PIN5 (input pullup).\r
- * PK6 - PIN6 (input pullup).\r
- * PK7 - PIN7 (input pullup).\r
- * PK8 - PIN8 (input pullup).\r
- * PK9 - PIN9 (input pullup).\r
- * PK10 - PIN10 (input pullup).\r
- * PK11 - PIN11 (input pullup).\r
- * PK12 - PIN12 (input pullup).\r
- * PK13 - PIN13 (input pullup).\r
- * PK14 - PIN14 (input pullup).\r
- * PK15 - PIN15 (input pullup).\r
- */\r
-#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \\r
- PIN_MODE_INPUT(GPIOK_PIN1) | \\r
- PIN_MODE_INPUT(GPIOK_PIN2) | \\r
- PIN_MODE_INPUT(GPIOK_PIN3) | \\r
- PIN_MODE_INPUT(GPIOK_PIN4) | \\r
- PIN_MODE_INPUT(GPIOK_PIN5) | \\r
- PIN_MODE_INPUT(GPIOK_PIN6) | \\r
- PIN_MODE_INPUT(GPIOK_PIN7) | \\r
- PIN_MODE_INPUT(GPIOK_PIN8) | \\r
- PIN_MODE_INPUT(GPIOK_PIN9) | \\r
- PIN_MODE_INPUT(GPIOK_PIN10) | \\r
- PIN_MODE_INPUT(GPIOK_PIN11) | \\r
- PIN_MODE_INPUT(GPIOK_PIN12) | \\r
- PIN_MODE_INPUT(GPIOK_PIN13) | \\r
- PIN_MODE_INPUT(GPIOK_PIN14) | \\r
- PIN_MODE_INPUT(GPIOK_PIN15))\r
-#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOK_PIN15))\r
-#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \\r
- PIN_OSPEED_VERYLOW(GPIOK_PIN15))\r
-#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLUP(GPIOK_PIN0) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN1) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN2) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN3) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN4) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN5) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN6) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN7) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN8) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN9) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN10) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN11) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN12) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN13) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN14) | \\r
- PIN_PUPDR_PULLUP(GPIOK_PIN15))\r
-#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \\r
- PIN_ODR_HIGH(GPIOK_PIN1) | \\r
- PIN_ODR_HIGH(GPIOK_PIN2) | \\r
- PIN_ODR_HIGH(GPIOK_PIN3) | \\r
- PIN_ODR_HIGH(GPIOK_PIN4) | \\r
- PIN_ODR_HIGH(GPIOK_PIN5) | \\r
- PIN_ODR_HIGH(GPIOK_PIN6) | \\r
- PIN_ODR_HIGH(GPIOK_PIN7) | \\r
- PIN_ODR_HIGH(GPIOK_PIN8) | \\r
- PIN_ODR_HIGH(GPIOK_PIN9) | \\r
- PIN_ODR_HIGH(GPIOK_PIN10) | \\r
- PIN_ODR_HIGH(GPIOK_PIN11) | \\r
- PIN_ODR_HIGH(GPIOK_PIN12) | \\r
- PIN_ODR_HIGH(GPIOK_PIN13) | \\r
- PIN_ODR_HIGH(GPIOK_PIN14) | \\r
- PIN_ODR_HIGH(GPIOK_PIN15))\r
-#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN1, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN7, 0U))\r
-#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN13, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOK_PIN15, 0U))\r
-\r
-/*===========================================================================*/\r
-/* External declarations. */\r
-/*===========================================================================*/\r
-\r
-#if !defined(_FROM_ASM_)\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
- void boardInit(void);\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* _FROM_ASM_ */\r
-\r
-#endif /* BOARD_H */\r
+++ /dev/null
-/*\r
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
-\r
- Licensed under the Apache License, Version 2.0 (the "License");\r
- you may not use this file except in compliance with the License.\r
- You may obtain a copy of the License at\r
-\r
- http://www.apache.org/licenses/LICENSE-2.0\r
-\r
- Unless required by applicable law or agreed to in writing, software\r
- distributed under the License is distributed on an "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- See the License for the specific language governing permissions and\r
- limitations under the License.\r
-*/\r
-\r
-/*\r
- * This file has been automatically generated using ChibiStudio board\r
- * generator plugin. Do not edit manually.\r
- */\r
-\r
-#ifndef BOARD_H\r
-#define BOARD_H\r
-\r
-/*===========================================================================*/\r
-/* Driver constants. */\r
-/*===========================================================================*/\r
-\r
-/*\r
- * Setup for STMicroelectronics STM32 Nucleo64-L476RG board.\r
- */\r
-\r
-/*\r
- * Board identifier.\r
- */\r
-#define BOARD_ST_NUCLEO64_L476RG\r
-#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-L476RG"\r
-\r
-/*\r
- * Board oscillators-related settings.\r
- */\r
-#if !defined(STM32_LSECLK)\r
-#define STM32_LSECLK 32768U\r
-#endif\r
-\r
-#define STM32_LSEDRV (3U << 3U)\r
-\r
-#if !defined(STM32_HSECLK)\r
-#define STM32_HSECLK 8000000U\r
-#endif\r
-\r
-#define STM32_HSE_BYPASS\r
-\r
-/*\r
- * Board voltages.\r
- * Required for performance limits calculation.\r
- */\r
-#define STM32_VDD 300U\r
-\r
-/*\r
- * MCU type as defined in the ST header.\r
- */\r
-#define STM32L476xx\r
-\r
-/*\r
- * IO pins assignments.\r
- */\r
-#define GPIOA_ARD_A0 0U\r
-#define GPIOA_ACD12_IN5 0U\r
-#define GPIOA_ARD_A1 1U\r
-#define GPIOA_ACD12_IN6 1U\r
-#define GPIOA_ARD_D1 2U\r
-#define GPIOA_USART2_TX 2U\r
-#define GPIOA_ARD_D0 3U\r
-#define GPIOA_USART2_RX 3U\r
-#define GPIOA_ARD_A2 4U\r
-#define GPIOA_ACD12_IN9 4U\r
-#define GPIOA_ARD_D13 5U\r
-#define GPIOA_LED_GREEN 5U\r
-#define GPIOA_ARD_D12 6U\r
-#define GPIOA_ARD_D11 7U\r
-#define GPIOA_ARD_D7 8U\r
-#define GPIOA_ARD_D8 9U\r
-#define GPIOA_ARD_D2 10U\r
-#define GPIOA_PIN11 11U\r
-#define GPIOA_PIN12 12U\r
-#define GPIOA_SWDIO 13U\r
-#define GPIOA_SWCLK 14U\r
-#define GPIOA_PIN15 15U\r
-\r
-#define GPIOB_ARD_A3 0U\r
-#define GPIOB_ACD12_IN15 0U\r
-#define GPIOB_PIN1 1U\r
-#define GPIOB_PIN2 2U\r
-#define GPIOB_ARD_D3 3U\r
-#define GPIOB_SWO 3U\r
-#define GPIOB_ARD_D5 4U\r
-#define GPIOB_ARD_D4 5U\r
-#define GPIOB_ARD_D10 6U\r
-#define GPIOB_PIN7 7U\r
-#define GPIOB_ARD_D15 8U\r
-#define GPIOB_ARD_D14 9U\r
-#define GPIOB_ARD_D6 10U\r
-#define GPIOB_PIN11 11U\r
-#define GPIOB_PIN12 12U\r
-#define GPIOB_PIN13 13U\r
-#define GPIOB_PIN14 14U\r
-#define GPIOB_PIN15 15U\r
-\r
-#define GPIOC_ARD_A5 0U\r
-#define GPIOC_ACD123_IN1 0U\r
-#define GPIOC_ARD_A4 1U\r
-#define GPIOC_ACD123_IN2 1U\r
-#define GPIOC_PIN2 2U\r
-#define GPIOC_PIN3 3U\r
-#define GPIOC_PIN4 4U\r
-#define GPIOC_PIN5 5U\r
-#define GPIOC_PIN6 6U\r
-#define GPIOC_ARD_D9 7U\r
-#define GPIOC_PIN8 8U\r
-#define GPIOC_PIN9 9U\r
-#define GPIOC_PIN10 10U\r
-#define GPIOC_PIN11 11U\r
-#define GPIOC_PIN12 12U\r
-#define GPIOC_BUTTON 13U\r
-#define GPIOC_OSC32_IN 14U\r
-#define GPIOC_OSC32_OUT 15U\r
-\r
-#define GPIOD_PIN0 0U\r
-#define GPIOD_PIN1 1U\r
-#define GPIOD_PIN2 2U\r
-#define GPIOD_PIN3 3U\r
-#define GPIOD_PIN4 4U\r
-#define GPIOD_PIN5 5U\r
-#define GPIOD_PIN6 6U\r
-#define GPIOD_PIN7 7U\r
-#define GPIOD_PIN8 8U\r
-#define GPIOD_PIN9 9U\r
-#define GPIOD_PIN10 10U\r
-#define GPIOD_PIN11 11U\r
-#define GPIOD_PIN12 12U\r
-#define GPIOD_PIN13 13U\r
-#define GPIOD_PIN14 14U\r
-#define GPIOD_PIN15 15U\r
-\r
-#define GPIOE_PIN0 0U\r
-#define GPIOE_PIN1 1U\r
-#define GPIOE_PIN2 2U\r
-#define GPIOE_PIN3 3U\r
-#define GPIOE_PIN4 4U\r
-#define GPIOE_PIN5 5U\r
-#define GPIOE_PIN6 6U\r
-#define GPIOE_PIN7 7U\r
-#define GPIOE_PIN8 8U\r
-#define GPIOE_PIN9 9U\r
-#define GPIOE_PIN10 10U\r
-#define GPIOE_PIN11 11U\r
-#define GPIOE_PIN12 12U\r
-#define GPIOE_PIN13 13U\r
-#define GPIOE_PIN14 14U\r
-#define GPIOE_PIN15 15U\r
-\r
-#define GPIOF_PIN0 0U\r
-#define GPIOF_PIN1 1U\r
-#define GPIOF_PIN2 2U\r
-#define GPIOF_PIN3 3U\r
-#define GPIOF_PIN4 4U\r
-#define GPIOF_PIN5 5U\r
-#define GPIOF_PIN6 6U\r
-#define GPIOF_PIN7 7U\r
-#define GPIOF_PIN8 8U\r
-#define GPIOF_PIN9 9U\r
-#define GPIOF_PIN10 10U\r
-#define GPIOF_PIN11 11U\r
-#define GPIOF_PIN12 12U\r
-#define GPIOF_PIN13 13U\r
-#define GPIOF_PIN14 14U\r
-#define GPIOF_PIN15 15U\r
-\r
-#define GPIOG_PIN0 0U\r
-#define GPIOG_PIN1 1U\r
-#define GPIOG_PIN2 2U\r
-#define GPIOG_PIN3 3U\r
-#define GPIOG_PIN4 4U\r
-#define GPIOG_PIN5 5U\r
-#define GPIOG_PIN6 6U\r
-#define GPIOG_PIN7 7U\r
-#define GPIOG_PIN8 8U\r
-#define GPIOG_PIN9 9U\r
-#define GPIOG_PIN10 10U\r
-#define GPIOG_PIN11 11U\r
-#define GPIOG_PIN12 12U\r
-#define GPIOG_PIN13 13U\r
-#define GPIOG_PIN14 14U\r
-#define GPIOG_PIN15 15U\r
-\r
-#define GPIOH_OSC_IN 0U\r
-#define GPIOH_OSC_OUT 1U\r
-#define GPIOH_PIN2 2U\r
-#define GPIOH_PIN3 3U\r
-#define GPIOH_PIN4 4U\r
-#define GPIOH_PIN5 5U\r
-#define GPIOH_PIN6 6U\r
-#define GPIOH_PIN7 7U\r
-#define GPIOH_PIN8 8U\r
-#define GPIOH_PIN9 9U\r
-#define GPIOH_PIN10 10U\r
-#define GPIOH_PIN11 11U\r
-#define GPIOH_PIN12 12U\r
-#define GPIOH_PIN13 13U\r
-#define GPIOH_PIN14 14U\r
-#define GPIOH_PIN15 15U\r
-\r
-/*\r
- * IO lines assignments.\r
- */\r
-#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U)\r
-#define LINE_ACD12_IN5 PAL_LINE(GPIOA, 0U)\r
-#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U)\r
-#define LINE_ACD12_IN6 PAL_LINE(GPIOA, 1U)\r
-#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U)\r
-#define LINE_USART2_TX PAL_LINE(GPIOA, 2U)\r
-#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U)\r
-#define LINE_USART2_RX PAL_LINE(GPIOA, 3U)\r
-#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U)\r
-#define LINE_ACD12_IN9 PAL_LINE(GPIOA, 4U)\r
-#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U)\r
-#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U)\r
-#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U)\r
-#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U)\r
-#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U)\r
-#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U)\r
-#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U)\r
-#define LINE_SWDIO PAL_LINE(GPIOA, 13U)\r
-#define LINE_SWCLK PAL_LINE(GPIOA, 14U)\r
-#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U)\r
-#define LINE_ACD12_IN15 PAL_LINE(GPIOB, 0U)\r
-#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U)\r
-#define LINE_SWO PAL_LINE(GPIOB, 3U)\r
-#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U)\r
-#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U)\r
-#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U)\r
-#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U)\r
-#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U)\r
-#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U)\r
-#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U)\r
-#define LINE_ACD123_IN1 PAL_LINE(GPIOC, 0U)\r
-#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U)\r
-#define LINE_ACD123_IN2 PAL_LINE(GPIOC, 1U)\r
-#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U)\r
-#define LINE_BUTTON PAL_LINE(GPIOC, 13U)\r
-#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)\r
-#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)\r
-#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)\r
-#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)\r
-\r
-/*===========================================================================*/\r
-/* Driver pre-compile time settings. */\r
-/*===========================================================================*/\r
-\r
-/*===========================================================================*/\r
-/* Derived constants and error checks. */\r
-/*===========================================================================*/\r
-\r
-/*===========================================================================*/\r
-/* Driver data structures and types. */\r
-/*===========================================================================*/\r
-\r
-/*===========================================================================*/\r
-/* Driver macros. */\r
-/*===========================================================================*/\r
-\r
-/*\r
- * I/O ports initial setup, this configuration is established soon after reset\r
- * in the initialization code.\r
- * Please refer to the STM32 Reference Manual for details.\r
- */\r
-#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))\r
-#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))\r
-#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))\r
-#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))\r
-#define PIN_ODR_LOW(n) (0U << (n))\r
-#define PIN_ODR_HIGH(n) (1U << (n))\r
-#define PIN_OTYPE_PUSHPULL(n) (0U << (n))\r
-#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))\r
-#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))\r
-#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))\r
-#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))\r
-#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))\r
-#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))\r
-#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))\r
-#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))\r
-#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))\r
-#define PIN_ASCR_DISABLED(n) (0U << (n))\r
-#define PIN_ASCR_ENABLED(n) (1U << (n))\r
-#define PIN_LOCKR_DISABLED(n) (0U << (n))\r
-#define PIN_LOCKR_ENABLED(n) (1U << (n))\r
-\r
-/*\r
- * GPIOA setup:\r
- *\r
- * PA0 - ARD_A0 ACD12_IN5 (analog).\r
- * PA1 - ARD_A1 ACD12_IN6 (analog).\r
- * PA2 - ARD_D1 USART2_TX (alternate 7).\r
- * PA3 - ARD_D0 USART2_RX (alternate 7).\r
- * PA4 - ARD_A2 ACD12_IN9 (analog).\r
- * PA5 - ARD_D13 LED_GREEN (output pushpull maximum).\r
- * PA6 - ARD_D12 (analog).\r
- * PA7 - ARD_D11 (analog).\r
- * PA8 - ARD_D7 (analog).\r
- * PA9 - ARD_D8 (analog).\r
- * PA10 - ARD_D2 (analog).\r
- * PA11 - PIN11 (analog).\r
- * PA12 - PIN12 (analog).\r
- * PA13 - SWDIO (alternate 0).\r
- * PA14 - SWCLK (alternate 0).\r
- * PA15 - PIN15 (analog).\r
- */\r
-#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_ARD_A0) | \\r
- PIN_MODE_ANALOG(GPIOA_ARD_A1) | \\r
- PIN_MODE_ALTERNATE(GPIOA_ARD_D1) | \\r
- PIN_MODE_ALTERNATE(GPIOA_ARD_D0) | \\r
- PIN_MODE_ANALOG(GPIOA_ARD_A2) | \\r
- PIN_MODE_OUTPUT(GPIOA_ARD_D13) | \\r
- PIN_MODE_ANALOG(GPIOA_ARD_D12) | \\r
- PIN_MODE_ANALOG(GPIOA_ARD_D11) | \\r
- PIN_MODE_ANALOG(GPIOA_ARD_D7) | \\r
- PIN_MODE_ANALOG(GPIOA_ARD_D8) | \\r
- PIN_MODE_ANALOG(GPIOA_ARD_D2) | \\r
- PIN_MODE_ANALOG(GPIOA_PIN11) | \\r
- PIN_MODE_ANALOG(GPIOA_PIN12) | \\r
- PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \\r
- PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \\r
- PIN_MODE_ANALOG(GPIOA_PIN15))\r
-#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \\r
- PIN_OTYPE_PUSHPULL(GPIOA_PIN15))\r
-#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \\r
- PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \\r
- PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | \\r
- PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | \\r
- PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \\r
- PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \\r
- PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \\r
- PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \\r
- PIN_OSPEED_HIGH(GPIOA_ARD_D7) | \\r
- PIN_OSPEED_HIGH(GPIOA_ARD_D8) | \\r
- PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \\r
- PIN_OSPEED_HIGH(GPIOA_PIN11) | \\r
- PIN_OSPEED_HIGH(GPIOA_PIN12) | \\r
- PIN_OSPEED_HIGH(GPIOA_SWDIO) | \\r
- PIN_OSPEED_HIGH(GPIOA_SWCLK) | \\r
- PIN_OSPEED_HIGH(GPIOA_PIN15))\r
-#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_ARD_A0) | \\r
- PIN_PUPDR_FLOATING(GPIOA_ARD_A1) | \\r
- PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \\r
- PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \\r
- PIN_PUPDR_FLOATING(GPIOA_ARD_A2) | \\r
- PIN_PUPDR_FLOATING(GPIOA_ARD_D13) | \\r
- PIN_PUPDR_FLOATING(GPIOA_ARD_D12) | \\r
- PIN_PUPDR_FLOATING(GPIOA_ARD_D11) | \\r
- PIN_PUPDR_FLOATING(GPIOA_ARD_D7) | \\r
- PIN_PUPDR_FLOATING(GPIOA_ARD_D8) | \\r
- PIN_PUPDR_FLOATING(GPIOA_ARD_D2) | \\r
- PIN_PUPDR_FLOATING(GPIOA_PIN11) | \\r
- PIN_PUPDR_FLOATING(GPIOA_PIN12) | \\r
- PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \\r
- PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \\r
- PIN_PUPDR_FLOATING(GPIOA_PIN15))\r
-#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \\r
- PIN_ODR_HIGH(GPIOA_ARD_A1) | \\r
- PIN_ODR_HIGH(GPIOA_ARD_D1) | \\r
- PIN_ODR_HIGH(GPIOA_ARD_D0) | \\r
- PIN_ODR_HIGH(GPIOA_ARD_A2) | \\r
- PIN_ODR_LOW(GPIOA_ARD_D13) | \\r
- PIN_ODR_HIGH(GPIOA_ARD_D12) | \\r
- PIN_ODR_HIGH(GPIOA_ARD_D11) | \\r
- PIN_ODR_HIGH(GPIOA_ARD_D7) | \\r
- PIN_ODR_HIGH(GPIOA_ARD_D8) | \\r
- PIN_ODR_HIGH(GPIOA_ARD_D2) | \\r
- PIN_ODR_HIGH(GPIOA_PIN11) | \\r
- PIN_ODR_HIGH(GPIOA_PIN12) | \\r
- PIN_ODR_HIGH(GPIOA_SWDIO) | \\r
- PIN_ODR_HIGH(GPIOA_SWCLK) | \\r
- PIN_ODR_HIGH(GPIOA_PIN15))\r
-#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \\r
- PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \\r
- PIN_AFIO_AF(GPIOA_ARD_D1, 7U) | \\r
- PIN_AFIO_AF(GPIOA_ARD_D0, 7U) | \\r
- PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \\r
- PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \\r
- PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \\r
- PIN_AFIO_AF(GPIOA_ARD_D11, 0U))\r
-#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \\r
- PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \\r
- PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \\r
- PIN_AFIO_AF(GPIOA_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOA_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \\r
- PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \\r
- PIN_AFIO_AF(GPIOA_PIN15, 0U))\r
-#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_ARD_A0) | \\r
- PIN_ASCR_DISABLED(GPIOA_ARD_A1) | \\r
- PIN_ASCR_DISABLED(GPIOA_ARD_D1) | \\r
- PIN_ASCR_DISABLED(GPIOA_ARD_D0) | \\r
- PIN_ASCR_DISABLED(GPIOA_ARD_A2) | \\r
- PIN_ASCR_DISABLED(GPIOA_ARD_D13) | \\r
- PIN_ASCR_DISABLED(GPIOA_ARD_D12) | \\r
- PIN_ASCR_DISABLED(GPIOA_ARD_D11) | \\r
- PIN_ASCR_DISABLED(GPIOA_ARD_D7) | \\r
- PIN_ASCR_DISABLED(GPIOA_ARD_D8) | \\r
- PIN_ASCR_DISABLED(GPIOA_ARD_D2) | \\r
- PIN_ASCR_DISABLED(GPIOA_PIN11) | \\r
- PIN_ASCR_DISABLED(GPIOA_PIN12) | \\r
- PIN_ASCR_DISABLED(GPIOA_SWDIO) | \\r
- PIN_ASCR_DISABLED(GPIOA_SWCLK) | \\r
- PIN_ASCR_DISABLED(GPIOA_PIN15))\r
-#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_ARD_A0) | \\r
- PIN_LOCKR_DISABLED(GPIOA_ARD_A1) | \\r
- PIN_LOCKR_DISABLED(GPIOA_ARD_D1) | \\r
- PIN_LOCKR_DISABLED(GPIOA_ARD_D0) | \\r
- PIN_LOCKR_DISABLED(GPIOA_ARD_A2) | \\r
- PIN_LOCKR_DISABLED(GPIOA_ARD_D13) | \\r
- PIN_LOCKR_DISABLED(GPIOA_ARD_D12) | \\r
- PIN_LOCKR_DISABLED(GPIOA_ARD_D11) | \\r
- PIN_LOCKR_DISABLED(GPIOA_ARD_D7) | \\r
- PIN_LOCKR_DISABLED(GPIOA_ARD_D8) | \\r
- PIN_LOCKR_DISABLED(GPIOA_ARD_D2) | \\r
- PIN_LOCKR_DISABLED(GPIOA_PIN11) | \\r
- PIN_LOCKR_DISABLED(GPIOA_PIN12) | \\r
- PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \\r
- PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \\r
- PIN_LOCKR_DISABLED(GPIOA_PIN15))\r
-\r
-/*\r
- * GPIOB setup:\r
- *\r
- * PB0 - ARD_A3 ACD12_IN15 (analog).\r
- * PB1 - PIN1 (analog).\r
- * PB2 - PIN2 (analog).\r
- * PB3 - ARD_D3 SWO (analog).\r
- * PB4 - ARD_D5 (analog).\r
- * PB5 - ARD_D4 (analog).\r
- * PB6 - ARD_D10 (analog).\r
- * PB7 - PIN7 (analog).\r
- * PB8 - ARD_D15 (analog).\r
- * PB9 - ARD_D14 (analog).\r
- * PB10 - ARD_D6 (analog).\r
- * PB11 - PIN11 (analog).\r
- * PB12 - PIN12 (analog).\r
- * PB13 - PIN13 (analog).\r
- * PB14 - PIN14 (analog).\r
- * PB15 - PIN15 (analog).\r
- */\r
-#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_ARD_A3) | \\r
- PIN_MODE_ANALOG(GPIOB_PIN1) | \\r
- PIN_MODE_ANALOG(GPIOB_PIN2) | \\r
- PIN_MODE_ANALOG(GPIOB_ARD_D3) | \\r
- PIN_MODE_ANALOG(GPIOB_ARD_D5) | \\r
- PIN_MODE_ANALOG(GPIOB_ARD_D4) | \\r
- PIN_MODE_ANALOG(GPIOB_ARD_D10) | \\r
- PIN_MODE_ANALOG(GPIOB_PIN7) | \\r
- PIN_MODE_ANALOG(GPIOB_ARD_D15) | \\r
- PIN_MODE_ANALOG(GPIOB_ARD_D14) | \\r
- PIN_MODE_ANALOG(GPIOB_ARD_D6) | \\r
- PIN_MODE_ANALOG(GPIOB_PIN11) | \\r
- PIN_MODE_ANALOG(GPIOB_PIN12) | \\r
- PIN_MODE_ANALOG(GPIOB_PIN13) | \\r
- PIN_MODE_ANALOG(GPIOB_PIN14) | \\r
- PIN_MODE_ANALOG(GPIOB_PIN15))\r
-#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_ARD_D3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOB_PIN15))\r
-#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_A3) | \\r
- PIN_OSPEED_HIGH(GPIOB_PIN1) | \\r
- PIN_OSPEED_HIGH(GPIOB_PIN2) | \\r
- PIN_OSPEED_HIGH(GPIOB_ARD_D3) | \\r
- PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \\r
- PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \\r
- PIN_OSPEED_HIGH(GPIOB_ARD_D10) | \\r
- PIN_OSPEED_HIGH(GPIOB_PIN7) | \\r
- PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \\r
- PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \\r
- PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \\r
- PIN_OSPEED_HIGH(GPIOB_PIN11) | \\r
- PIN_OSPEED_HIGH(GPIOB_PIN12) | \\r
- PIN_OSPEED_HIGH(GPIOB_PIN13) | \\r
- PIN_OSPEED_HIGH(GPIOB_PIN14) | \\r
- PIN_OSPEED_HIGH(GPIOB_PIN15))\r
-#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_ARD_A3) | \\r
- PIN_PUPDR_FLOATING(GPIOB_PIN1) | \\r
- PIN_PUPDR_FLOATING(GPIOB_PIN2) | \\r
- PIN_PUPDR_FLOATING(GPIOB_ARD_D3) | \\r
- PIN_PUPDR_FLOATING(GPIOB_ARD_D5) | \\r
- PIN_PUPDR_FLOATING(GPIOB_ARD_D4) | \\r
- PIN_PUPDR_FLOATING(GPIOB_ARD_D10) | \\r
- PIN_PUPDR_FLOATING(GPIOB_PIN7) | \\r
- PIN_PUPDR_FLOATING(GPIOB_ARD_D15) | \\r
- PIN_PUPDR_FLOATING(GPIOB_ARD_D14) | \\r
- PIN_PUPDR_FLOATING(GPIOB_ARD_D6) | \\r
- PIN_PUPDR_FLOATING(GPIOB_PIN11) | \\r
- PIN_PUPDR_FLOATING(GPIOB_PIN12) | \\r
- PIN_PUPDR_FLOATING(GPIOB_PIN13) | \\r
- PIN_PUPDR_FLOATING(GPIOB_PIN14) | \\r
- PIN_PUPDR_FLOATING(GPIOB_PIN15))\r
-#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_A3) | \\r
- PIN_ODR_HIGH(GPIOB_PIN1) | \\r
- PIN_ODR_HIGH(GPIOB_PIN2) | \\r
- PIN_ODR_HIGH(GPIOB_ARD_D3) | \\r
- PIN_ODR_HIGH(GPIOB_ARD_D5) | \\r
- PIN_ODR_HIGH(GPIOB_ARD_D4) | \\r
- PIN_ODR_HIGH(GPIOB_ARD_D10) | \\r
- PIN_ODR_HIGH(GPIOB_PIN7) | \\r
- PIN_ODR_HIGH(GPIOB_ARD_D15) | \\r
- PIN_ODR_HIGH(GPIOB_ARD_D14) | \\r
- PIN_ODR_HIGH(GPIOB_ARD_D6) | \\r
- PIN_ODR_HIGH(GPIOB_PIN11) | \\r
- PIN_ODR_HIGH(GPIOB_PIN12) | \\r
- PIN_ODR_HIGH(GPIOB_PIN13) | \\r
- PIN_ODR_HIGH(GPIOB_PIN14) | \\r
- PIN_ODR_HIGH(GPIOB_PIN15))\r
-#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN1, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOB_ARD_D3, 0U) | \\r
- PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \\r
- PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \\r
- PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN7, 0U))\r
-#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \\r
- PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \\r
- PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN13, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOB_PIN15, 0U))\r
-#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_ARD_A3) | \\r
- PIN_ASCR_DISABLED(GPIOB_PIN1) | \\r
- PIN_ASCR_DISABLED(GPIOB_PIN2) | \\r
- PIN_ASCR_DISABLED(GPIOB_ARD_D3) | \\r
- PIN_ASCR_DISABLED(GPIOB_ARD_D5) | \\r
- PIN_ASCR_DISABLED(GPIOB_ARD_D4) | \\r
- PIN_ASCR_DISABLED(GPIOB_ARD_D10) | \\r
- PIN_ASCR_DISABLED(GPIOB_PIN7) | \\r
- PIN_ASCR_DISABLED(GPIOB_ARD_D15) | \\r
- PIN_ASCR_DISABLED(GPIOB_ARD_D14) | \\r
- PIN_ASCR_DISABLED(GPIOB_ARD_D6) | \\r
- PIN_ASCR_DISABLED(GPIOB_PIN11) | \\r
- PIN_ASCR_DISABLED(GPIOB_PIN12) | \\r
- PIN_ASCR_DISABLED(GPIOB_PIN13) | \\r
- PIN_ASCR_DISABLED(GPIOB_PIN14) | \\r
- PIN_ASCR_DISABLED(GPIOB_PIN15))\r
-#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_ARD_A3) | \\r
- PIN_LOCKR_DISABLED(GPIOB_PIN1) | \\r
- PIN_LOCKR_DISABLED(GPIOB_PIN2) | \\r
- PIN_LOCKR_DISABLED(GPIOB_ARD_D3) | \\r
- PIN_LOCKR_DISABLED(GPIOB_ARD_D5) | \\r
- PIN_LOCKR_DISABLED(GPIOB_ARD_D4) | \\r
- PIN_LOCKR_DISABLED(GPIOB_ARD_D10) | \\r
- PIN_LOCKR_DISABLED(GPIOB_PIN7) | \\r
- PIN_LOCKR_DISABLED(GPIOB_ARD_D15) | \\r
- PIN_LOCKR_DISABLED(GPIOB_ARD_D14) | \\r
- PIN_LOCKR_DISABLED(GPIOB_ARD_D6) | \\r
- PIN_LOCKR_DISABLED(GPIOB_PIN11) | \\r
- PIN_LOCKR_DISABLED(GPIOB_PIN12) | \\r
- PIN_LOCKR_DISABLED(GPIOB_PIN13) | \\r
- PIN_LOCKR_DISABLED(GPIOB_PIN14) | \\r
- PIN_LOCKR_DISABLED(GPIOB_PIN15))\r
-\r
-/*\r
- * GPIOC setup:\r
- *\r
- * PC0 - ARD_A5 ACD123_IN1 (analog).\r
- * PC1 - ARD_A4 ACD123_IN2 (analog).\r
- * PC2 - PIN2 (analog).\r
- * PC3 - PIN3 (analog).\r
- * PC4 - PIN4 (analog).\r
- * PC5 - PIN5 (analog).\r
- * PC6 - PIN6 (analog).\r
- * PC7 - ARD_D9 (analog).\r
- * PC8 - PIN8 (analog).\r
- * PC9 - PIN9 (analog).\r
- * PC10 - PIN10 (analog).\r
- * PC11 - PIN11 (analog).\r
- * PC12 - PIN12 (analog).\r
- * PC13 - BUTTON (input floating).\r
- * PC14 - OSC32_IN (input floating).\r
- * PC15 - OSC32_OUT (input floating).\r
- */\r
-#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_ARD_A5) | \\r
- PIN_MODE_ANALOG(GPIOC_ARD_A4) | \\r
- PIN_MODE_ANALOG(GPIOC_PIN2) | \\r
- PIN_MODE_ANALOG(GPIOC_PIN3) | \\r
- PIN_MODE_ANALOG(GPIOC_PIN4) | \\r
- PIN_MODE_ANALOG(GPIOC_PIN5) | \\r
- PIN_MODE_ANALOG(GPIOC_PIN6) | \\r
- PIN_MODE_ANALOG(GPIOC_ARD_D9) | \\r
- PIN_MODE_ANALOG(GPIOC_PIN8) | \\r
- PIN_MODE_ANALOG(GPIOC_PIN9) | \\r
- PIN_MODE_ANALOG(GPIOC_PIN10) | \\r
- PIN_MODE_ANALOG(GPIOC_PIN11) | \\r
- PIN_MODE_ANALOG(GPIOC_PIN12) | \\r
- PIN_MODE_INPUT(GPIOC_BUTTON) | \\r
- PIN_MODE_INPUT(GPIOC_OSC32_IN) | \\r
- PIN_MODE_INPUT(GPIOC_OSC32_OUT))\r
-#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_ARD_D9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \\r
- PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))\r
-#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A5) | \\r
- PIN_OSPEED_HIGH(GPIOC_ARD_A4) | \\r
- PIN_OSPEED_HIGH(GPIOC_PIN2) | \\r
- PIN_OSPEED_HIGH(GPIOC_PIN3) | \\r
- PIN_OSPEED_HIGH(GPIOC_PIN4) | \\r
- PIN_OSPEED_HIGH(GPIOC_PIN5) | \\r
- PIN_OSPEED_HIGH(GPIOC_PIN6) | \\r
- PIN_OSPEED_HIGH(GPIOC_ARD_D9) | \\r
- PIN_OSPEED_HIGH(GPIOC_PIN8) | \\r
- PIN_OSPEED_HIGH(GPIOC_PIN9) | \\r
- PIN_OSPEED_HIGH(GPIOC_PIN10) | \\r
- PIN_OSPEED_HIGH(GPIOC_PIN11) | \\r
- PIN_OSPEED_HIGH(GPIOC_PIN12) | \\r
- PIN_OSPEED_HIGH(GPIOC_BUTTON) | \\r
- PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \\r
- PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))\r
-#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ARD_A5) | \\r
- PIN_PUPDR_FLOATING(GPIOC_ARD_A4) | \\r
- PIN_PUPDR_FLOATING(GPIOC_PIN2) | \\r
- PIN_PUPDR_FLOATING(GPIOC_PIN3) | \\r
- PIN_PUPDR_FLOATING(GPIOC_PIN4) | \\r
- PIN_PUPDR_FLOATING(GPIOC_PIN5) | \\r
- PIN_PUPDR_FLOATING(GPIOC_PIN6) | \\r
- PIN_PUPDR_FLOATING(GPIOC_ARD_D9) | \\r
- PIN_PUPDR_FLOATING(GPIOC_PIN8) | \\r
- PIN_PUPDR_FLOATING(GPIOC_PIN9) | \\r
- PIN_PUPDR_FLOATING(GPIOC_PIN10) | \\r
- PIN_PUPDR_FLOATING(GPIOC_PIN11) | \\r
- PIN_PUPDR_FLOATING(GPIOC_PIN12) | \\r
- PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \\r
- PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \\r
- PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))\r
-#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A5) | \\r
- PIN_ODR_HIGH(GPIOC_ARD_A4) | \\r
- PIN_ODR_HIGH(GPIOC_PIN2) | \\r
- PIN_ODR_HIGH(GPIOC_PIN3) | \\r
- PIN_ODR_HIGH(GPIOC_PIN4) | \\r
- PIN_ODR_HIGH(GPIOC_PIN5) | \\r
- PIN_ODR_HIGH(GPIOC_PIN6) | \\r
- PIN_ODR_HIGH(GPIOC_ARD_D9) | \\r
- PIN_ODR_HIGH(GPIOC_PIN8) | \\r
- PIN_ODR_HIGH(GPIOC_PIN9) | \\r
- PIN_ODR_HIGH(GPIOC_PIN10) | \\r
- PIN_ODR_HIGH(GPIOC_PIN11) | \\r
- PIN_ODR_HIGH(GPIOC_PIN12) | \\r
- PIN_ODR_HIGH(GPIOC_BUTTON) | \\r
- PIN_ODR_HIGH(GPIOC_OSC32_IN) | \\r
- PIN_ODR_HIGH(GPIOC_OSC32_OUT))\r
-#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \\r
- PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOC_ARD_D9, 0U))\r
-#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOC_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \\r
- PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \\r
- PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))\r
-#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_ARD_A5) | \\r
- PIN_ASCR_DISABLED(GPIOC_ARD_A4) | \\r
- PIN_ASCR_DISABLED(GPIOC_PIN2) | \\r
- PIN_ASCR_DISABLED(GPIOC_PIN3) | \\r
- PIN_ASCR_DISABLED(GPIOC_PIN4) | \\r
- PIN_ASCR_DISABLED(GPIOC_PIN5) | \\r
- PIN_ASCR_DISABLED(GPIOC_PIN6) | \\r
- PIN_ASCR_DISABLED(GPIOC_ARD_D9) | \\r
- PIN_ASCR_DISABLED(GPIOC_PIN8) | \\r
- PIN_ASCR_DISABLED(GPIOC_PIN9) | \\r
- PIN_ASCR_DISABLED(GPIOC_PIN10) | \\r
- PIN_ASCR_DISABLED(GPIOC_PIN11) | \\r
- PIN_ASCR_DISABLED(GPIOC_PIN12) | \\r
- PIN_ASCR_DISABLED(GPIOC_BUTTON) | \\r
- PIN_ASCR_DISABLED(GPIOC_OSC32_IN) | \\r
- PIN_ASCR_DISABLED(GPIOC_OSC32_OUT))\r
-#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_ARD_A5) | \\r
- PIN_LOCKR_DISABLED(GPIOC_ARD_A4) | \\r
- PIN_LOCKR_DISABLED(GPIOC_PIN2) | \\r
- PIN_LOCKR_DISABLED(GPIOC_PIN3) | \\r
- PIN_LOCKR_DISABLED(GPIOC_PIN4) | \\r
- PIN_LOCKR_DISABLED(GPIOC_PIN5) | \\r
- PIN_LOCKR_DISABLED(GPIOC_PIN6) | \\r
- PIN_LOCKR_DISABLED(GPIOC_ARD_D9) | \\r
- PIN_LOCKR_DISABLED(GPIOC_PIN8) | \\r
- PIN_LOCKR_DISABLED(GPIOC_PIN9) | \\r
- PIN_LOCKR_DISABLED(GPIOC_PIN10) | \\r
- PIN_LOCKR_DISABLED(GPIOC_PIN11) | \\r
- PIN_LOCKR_DISABLED(GPIOC_PIN12) | \\r
- PIN_LOCKR_DISABLED(GPIOC_BUTTON) | \\r
- PIN_LOCKR_DISABLED(GPIOC_OSC32_IN) | \\r
- PIN_LOCKR_DISABLED(GPIOC_OSC32_OUT))\r
-\r
-/*\r
- * GPIOD setup:\r
- *\r
- * PD0 - PIN0 (analog).\r
- * PD1 - PIN1 (analog).\r
- * PD2 - PIN2 (analog).\r
- * PD3 - PIN3 (analog).\r
- * PD4 - PIN4 (analog).\r
- * PD5 - PIN5 (analog).\r
- * PD6 - PIN6 (analog).\r
- * PD7 - PIN7 (analog).\r
- * PD8 - PIN8 (analog).\r
- * PD9 - PIN9 (analog).\r
- * PD10 - PIN10 (analog).\r
- * PD11 - PIN11 (analog).\r
- * PD12 - PIN12 (analog).\r
- * PD13 - PIN13 (analog).\r
- * PD14 - PIN14 (analog).\r
- * PD15 - PIN15 (analog).\r
- */\r
-#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN1) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN2) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN3) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN4) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN5) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN6) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN7) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN8) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN9) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN10) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN11) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN12) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN13) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN14) | \\r
- PIN_MODE_ANALOG(GPIOD_PIN15))\r
-#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOD_PIN15))\r
-#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN1) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN2) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN3) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN4) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN5) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN6) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN7) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN8) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN9) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN10) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN11) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN12) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN13) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN14) | \\r
- PIN_OSPEED_HIGH(GPIOD_PIN15))\r
-#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN1) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN2) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN3) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN4) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN5) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN6) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN7) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN8) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN9) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN10) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN11) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN12) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN13) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN14) | \\r
- PIN_PUPDR_FLOATING(GPIOD_PIN15))\r
-#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \\r
- PIN_ODR_HIGH(GPIOD_PIN1) | \\r
- PIN_ODR_HIGH(GPIOD_PIN2) | \\r
- PIN_ODR_HIGH(GPIOD_PIN3) | \\r
- PIN_ODR_HIGH(GPIOD_PIN4) | \\r
- PIN_ODR_HIGH(GPIOD_PIN5) | \\r
- PIN_ODR_HIGH(GPIOD_PIN6) | \\r
- PIN_ODR_HIGH(GPIOD_PIN7) | \\r
- PIN_ODR_HIGH(GPIOD_PIN8) | \\r
- PIN_ODR_HIGH(GPIOD_PIN9) | \\r
- PIN_ODR_HIGH(GPIOD_PIN10) | \\r
- PIN_ODR_HIGH(GPIOD_PIN11) | \\r
- PIN_ODR_HIGH(GPIOD_PIN12) | \\r
- PIN_ODR_HIGH(GPIOD_PIN13) | \\r
- PIN_ODR_HIGH(GPIOD_PIN14) | \\r
- PIN_ODR_HIGH(GPIOD_PIN15))\r
-#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN1, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN7, 0U))\r
-#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN13, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOD_PIN15, 0U))\r
-#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN1) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN2) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN3) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN4) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN5) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN6) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN7) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN8) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN9) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN10) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN11) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN12) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN13) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN14) | \\r
- PIN_ASCR_DISABLED(GPIOD_PIN15))\r
-#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_PIN0) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN1) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN2) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN3) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN4) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN5) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN6) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN7) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN8) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN9) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN10) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN11) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN12) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN13) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN14) | \\r
- PIN_LOCKR_DISABLED(GPIOD_PIN15))\r
-\r
-/*\r
- * GPIOE setup:\r
- *\r
- * PE0 - PIN0 (analog).\r
- * PE1 - PIN1 (analog).\r
- * PE2 - PIN2 (analog).\r
- * PE3 - PIN3 (analog).\r
- * PE4 - PIN4 (analog).\r
- * PE5 - PIN5 (analog).\r
- * PE6 - PIN6 (analog).\r
- * PE7 - PIN7 (analog).\r
- * PE8 - PIN8 (analog).\r
- * PE9 - PIN9 (analog).\r
- * PE10 - PIN10 (analog).\r
- * PE11 - PIN11 (analog).\r
- * PE12 - PIN12 (analog).\r
- * PE13 - PIN13 (analog).\r
- * PE14 - PIN14 (analog).\r
- * PE15 - PIN15 (analog).\r
- */\r
-#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN1) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN2) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN3) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN4) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN5) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN6) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN7) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN8) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN9) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN10) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN11) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN12) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN13) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN14) | \\r
- PIN_MODE_ANALOG(GPIOE_PIN15))\r
-#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOE_PIN15))\r
-#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN1) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN2) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN3) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN4) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN5) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN6) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN7) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN8) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN9) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN10) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN11) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN12) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN13) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN14) | \\r
- PIN_OSPEED_HIGH(GPIOE_PIN15))\r
-#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN1) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN2) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN3) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN4) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN5) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN6) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN7) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN8) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN9) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN10) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN11) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN12) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN13) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN14) | \\r
- PIN_PUPDR_FLOATING(GPIOE_PIN15))\r
-#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \\r
- PIN_ODR_HIGH(GPIOE_PIN1) | \\r
- PIN_ODR_HIGH(GPIOE_PIN2) | \\r
- PIN_ODR_HIGH(GPIOE_PIN3) | \\r
- PIN_ODR_HIGH(GPIOE_PIN4) | \\r
- PIN_ODR_HIGH(GPIOE_PIN5) | \\r
- PIN_ODR_HIGH(GPIOE_PIN6) | \\r
- PIN_ODR_HIGH(GPIOE_PIN7) | \\r
- PIN_ODR_HIGH(GPIOE_PIN8) | \\r
- PIN_ODR_HIGH(GPIOE_PIN9) | \\r
- PIN_ODR_HIGH(GPIOE_PIN10) | \\r
- PIN_ODR_HIGH(GPIOE_PIN11) | \\r
- PIN_ODR_HIGH(GPIOE_PIN12) | \\r
- PIN_ODR_HIGH(GPIOE_PIN13) | \\r
- PIN_ODR_HIGH(GPIOE_PIN14) | \\r
- PIN_ODR_HIGH(GPIOE_PIN15))\r
-#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN1, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN7, 0U))\r
-#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN13, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOE_PIN15, 0U))\r
-#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN1) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN2) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN3) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN4) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN5) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN6) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN7) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN8) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN9) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN10) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN11) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN12) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN13) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN14) | \\r
- PIN_ASCR_DISABLED(GPIOE_PIN15))\r
-#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_PIN0) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN1) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN2) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN3) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN4) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN5) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN6) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN7) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN8) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN9) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN10) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN11) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN12) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN13) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN14) | \\r
- PIN_LOCKR_DISABLED(GPIOE_PIN15))\r
-\r
-/*\r
- * GPIOF setup:\r
- *\r
- * PF0 - PIN0 (analog).\r
- * PF1 - PIN1 (analog).\r
- * PF2 - PIN2 (analog).\r
- * PF3 - PIN3 (analog).\r
- * PF4 - PIN4 (analog).\r
- * PF5 - PIN5 (analog).\r
- * PF6 - PIN6 (analog).\r
- * PF7 - PIN7 (analog).\r
- * PF8 - PIN8 (analog).\r
- * PF9 - PIN9 (analog).\r
- * PF10 - PIN10 (analog).\r
- * PF11 - PIN11 (analog).\r
- * PF12 - PIN12 (analog).\r
- * PF13 - PIN13 (analog).\r
- * PF14 - PIN14 (analog).\r
- * PF15 - PIN15 (analog).\r
- */\r
-#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN1) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN2) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN3) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN4) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN5) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN6) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN7) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN8) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN9) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN10) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN11) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN12) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN13) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN14) | \\r
- PIN_MODE_ANALOG(GPIOF_PIN15))\r
-#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOF_PIN15))\r
-#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN1) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN2) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN3) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN4) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN5) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN6) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN7) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN8) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN9) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN10) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN11) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN12) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN13) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN14) | \\r
- PIN_OSPEED_HIGH(GPIOF_PIN15))\r
-#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN1) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN2) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN3) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN4) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN5) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN6) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN7) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN8) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN9) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN10) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN11) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN12) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN13) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN14) | \\r
- PIN_PUPDR_FLOATING(GPIOF_PIN15))\r
-#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \\r
- PIN_ODR_HIGH(GPIOF_PIN1) | \\r
- PIN_ODR_HIGH(GPIOF_PIN2) | \\r
- PIN_ODR_HIGH(GPIOF_PIN3) | \\r
- PIN_ODR_HIGH(GPIOF_PIN4) | \\r
- PIN_ODR_HIGH(GPIOF_PIN5) | \\r
- PIN_ODR_HIGH(GPIOF_PIN6) | \\r
- PIN_ODR_HIGH(GPIOF_PIN7) | \\r
- PIN_ODR_HIGH(GPIOF_PIN8) | \\r
- PIN_ODR_HIGH(GPIOF_PIN9) | \\r
- PIN_ODR_HIGH(GPIOF_PIN10) | \\r
- PIN_ODR_HIGH(GPIOF_PIN11) | \\r
- PIN_ODR_HIGH(GPIOF_PIN12) | \\r
- PIN_ODR_HIGH(GPIOF_PIN13) | \\r
- PIN_ODR_HIGH(GPIOF_PIN14) | \\r
- PIN_ODR_HIGH(GPIOF_PIN15))\r
-#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN1, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN7, 0U))\r
-#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN13, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOF_PIN15, 0U))\r
-#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN1) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN2) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN3) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN4) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN5) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN6) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN7) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN8) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN9) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN10) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN11) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN12) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN13) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN14) | \\r
- PIN_ASCR_DISABLED(GPIOF_PIN15))\r
-#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_PIN0) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN1) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN2) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN3) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN4) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN5) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN6) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN7) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN8) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN9) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN10) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN11) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN12) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN13) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN14) | \\r
- PIN_LOCKR_DISABLED(GPIOF_PIN15))\r
-\r
-/*\r
- * GPIOG setup:\r
- *\r
- * PG0 - PIN0 (analog).\r
- * PG1 - PIN1 (analog).\r
- * PG2 - PIN2 (analog).\r
- * PG3 - PIN3 (analog).\r
- * PG4 - PIN4 (analog).\r
- * PG5 - PIN5 (analog).\r
- * PG6 - PIN6 (analog).\r
- * PG7 - PIN7 (analog).\r
- * PG8 - PIN8 (analog).\r
- * PG9 - PIN9 (analog).\r
- * PG10 - PIN10 (analog).\r
- * PG11 - PIN11 (analog).\r
- * PG12 - PIN12 (analog).\r
- * PG13 - PIN13 (analog).\r
- * PG14 - PIN14 (analog).\r
- * PG15 - PIN15 (analog).\r
- */\r
-#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN1) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN2) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN3) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN4) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN5) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN6) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN7) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN8) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN9) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN10) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN11) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN12) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN13) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN14) | \\r
- PIN_MODE_ANALOG(GPIOG_PIN15))\r
-#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOG_PIN15))\r
-#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN6) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN7) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \\r
- PIN_OSPEED_VERYLOW(GPIOG_PIN15))\r
-#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN1) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN2) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN3) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN4) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN5) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN6) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN7) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN8) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN9) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN10) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN11) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN12) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN13) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN14) | \\r
- PIN_PUPDR_FLOATING(GPIOG_PIN15))\r
-#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \\r
- PIN_ODR_HIGH(GPIOG_PIN1) | \\r
- PIN_ODR_HIGH(GPIOG_PIN2) | \\r
- PIN_ODR_HIGH(GPIOG_PIN3) | \\r
- PIN_ODR_HIGH(GPIOG_PIN4) | \\r
- PIN_ODR_HIGH(GPIOG_PIN5) | \\r
- PIN_ODR_HIGH(GPIOG_PIN6) | \\r
- PIN_ODR_HIGH(GPIOG_PIN7) | \\r
- PIN_ODR_HIGH(GPIOG_PIN8) | \\r
- PIN_ODR_HIGH(GPIOG_PIN9) | \\r
- PIN_ODR_HIGH(GPIOG_PIN10) | \\r
- PIN_ODR_HIGH(GPIOG_PIN11) | \\r
- PIN_ODR_HIGH(GPIOG_PIN12) | \\r
- PIN_ODR_HIGH(GPIOG_PIN13) | \\r
- PIN_ODR_HIGH(GPIOG_PIN14) | \\r
- PIN_ODR_HIGH(GPIOG_PIN15))\r
-#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN1, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN7, 0U))\r
-#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN13, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOG_PIN15, 0U))\r
-#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN1) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN2) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN3) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN4) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN5) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN6) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN7) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN8) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN9) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN10) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN11) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN12) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN13) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN14) | \\r
- PIN_ASCR_DISABLED(GPIOG_PIN15))\r
-#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_PIN0) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN1) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN2) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN3) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN4) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN5) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN6) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN7) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN8) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN9) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN10) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN11) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN12) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN13) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN14) | \\r
- PIN_LOCKR_DISABLED(GPIOG_PIN15))\r
-\r
-/*\r
- * GPIOH setup:\r
- *\r
- * PH0 - OSC_IN (input floating).\r
- * PH1 - OSC_OUT (input floating).\r
- * PH2 - PIN2 (analog).\r
- * PH3 - PIN3 (analog).\r
- * PH4 - PIN4 (analog).\r
- * PH5 - PIN5 (analog).\r
- * PH6 - PIN6 (analog).\r
- * PH7 - PIN7 (analog).\r
- * PH8 - PIN8 (analog).\r
- * PH9 - PIN9 (analog).\r
- * PH10 - PIN10 (analog).\r
- * PH11 - PIN11 (analog).\r
- * PH12 - PIN12 (analog).\r
- * PH13 - PIN13 (analog).\r
- * PH14 - PIN14 (analog).\r
- * PH15 - PIN15 (analog).\r
- */\r
-#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \\r
- PIN_MODE_INPUT(GPIOH_OSC_OUT) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN2) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN3) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN4) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN5) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN6) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN7) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN8) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN9) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN10) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN11) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN12) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN13) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN14) | \\r
- PIN_MODE_ANALOG(GPIOH_PIN15))\r
-#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \\r
- PIN_OTYPE_PUSHPULL(GPIOH_PIN15))\r
-#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \\r
- PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \\r
- PIN_OSPEED_VERYLOW(GPIOH_PIN15))\r
-#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \\r
- PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN2) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN3) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN4) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN5) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN6) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN7) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN8) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN9) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN10) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN11) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN12) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN13) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN14) | \\r
- PIN_PUPDR_FLOATING(GPIOH_PIN15))\r
-#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \\r
- PIN_ODR_HIGH(GPIOH_OSC_OUT) | \\r
- PIN_ODR_HIGH(GPIOH_PIN2) | \\r
- PIN_ODR_HIGH(GPIOH_PIN3) | \\r
- PIN_ODR_HIGH(GPIOH_PIN4) | \\r
- PIN_ODR_HIGH(GPIOH_PIN5) | \\r
- PIN_ODR_HIGH(GPIOH_PIN6) | \\r
- PIN_ODR_HIGH(GPIOH_PIN7) | \\r
- PIN_ODR_HIGH(GPIOH_PIN8) | \\r
- PIN_ODR_HIGH(GPIOH_PIN9) | \\r
- PIN_ODR_HIGH(GPIOH_PIN10) | \\r
- PIN_ODR_HIGH(GPIOH_PIN11) | \\r
- PIN_ODR_HIGH(GPIOH_PIN12) | \\r
- PIN_ODR_HIGH(GPIOH_PIN13) | \\r
- PIN_ODR_HIGH(GPIOH_PIN14) | \\r
- PIN_ODR_HIGH(GPIOH_PIN15))\r
-#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \\r
- PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN2, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN3, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN4, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN5, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN6, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN7, 0U))\r
-#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN9, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN10, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN11, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN12, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN13, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN14, 0U) | \\r
- PIN_AFIO_AF(GPIOH_PIN15, 0U))\r
-#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_OSC_IN) | \\r
- PIN_ASCR_DISABLED(GPIOH_OSC_OUT) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN2) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN3) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN4) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN5) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN6) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN7) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN8) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN9) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN10) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN11) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN12) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN13) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN14) | \\r
- PIN_ASCR_DISABLED(GPIOH_PIN15))\r
-#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_OSC_IN) | \\r
- PIN_LOCKR_DISABLED(GPIOH_OSC_OUT) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN2) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN3) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN4) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN5) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN6) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN7) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN8) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN9) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN10) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN11) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN12) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN13) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN14) | \\r
- PIN_LOCKR_DISABLED(GPIOH_PIN15))\r
-\r
-/*===========================================================================*/\r
-/* External declarations. */\r
-/*===========================================================================*/\r
-\r
-#if !defined(_FROM_ASM_)\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
- void boardInit(void);\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* _FROM_ASM_ */\r
-\r
-#endif /* BOARD_H */\r
+++ /dev/null
-/*\r
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
-\r
- Licensed under the Apache License, Version 2.0 (the "License");\r
- you may not use this file except in compliance with the License.\r
- You may obtain a copy of the License at\r
-\r
- http://www.apache.org/licenses/LICENSE-2.0\r
-\r
- Unless required by applicable law or agreed to in writing, software\r
- distributed under the License is distributed on an "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- See the License for the specific language governing permissions and\r
- limitations under the License.\r
-*/\r
-\r
-/**\r
- * @file rt/templates/chconf.h\r
- * @brief Configuration file template.\r
- * @details A copy of this file must be placed in each project directory, it\r
- * contains the application specific kernel settings.\r
- *\r
- * @addtogroup config\r
- * @details Kernel related settings and hooks.\r
- * @{\r
- */\r
-\r
-#ifndef CHCONF_H\r
-#define CHCONF_H\r
-\r
-#define _CHIBIOS_RT_CONF_\r
-#define _CHIBIOS_RT_CONF_VER_6_1_\r
-\r
-/*===========================================================================*/\r
-/**\r
- * @name System timers settings\r
- * @{\r
- */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief System time counter resolution.\r
- * @note Allowed values are 16 or 32 bits.\r
- */\r
-#if !defined(CH_CFG_ST_RESOLUTION)\r
-#define CH_CFG_ST_RESOLUTION 32\r
-#endif\r
-\r
-/**\r
- * @brief System tick frequency.\r
- * @details Frequency of the system timer that drives the system ticks. This\r
- * setting also defines the system tick time unit.\r
- */\r
-#if !defined(CH_CFG_ST_FREQUENCY)\r
-#define CH_CFG_ST_FREQUENCY 10000\r
-#endif\r
-\r
-/**\r
- * @brief Time intervals data size.\r
- * @note Allowed values are 16, 32 or 64 bits.\r
- */\r
-#if !defined(CH_CFG_INTERVALS_SIZE)\r
-#define CH_CFG_INTERVALS_SIZE 32\r
-#endif\r
-\r
-/**\r
- * @brief Time types data size.\r
- * @note Allowed values are 16 or 32 bits.\r
- */\r
-#if !defined(CH_CFG_TIME_TYPES_SIZE)\r
-#define CH_CFG_TIME_TYPES_SIZE 32\r
-#endif\r
-\r
-/**\r
- * @brief Time delta constant for the tick-less mode.\r
- * @note If this value is zero then the system uses the classic\r
- * periodic tick. This value represents the minimum number\r
- * of ticks that is safe to specify in a timeout directive.\r
- * The value one is not valid, timeouts are rounded up to\r
- * this value.\r
- */\r
-#if !defined(CH_CFG_ST_TIMEDELTA)\r
-#define CH_CFG_ST_TIMEDELTA 2\r
-#endif\r
-\r
-/** @} */\r
-\r
-/*===========================================================================*/\r
-/**\r
- * @name Kernel parameters and options\r
- * @{\r
- */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Round robin interval.\r
- * @details This constant is the number of system ticks allowed for the\r
- * threads before preemption occurs. Setting this value to zero\r
- * disables the preemption for threads with equal priority and the\r
- * round robin becomes cooperative. Note that higher priority\r
- * threads can still preempt, the kernel is always preemptive.\r
- * @note Disabling the round robin preemption makes the kernel more compact\r
- * and generally faster.\r
- * @note The round robin preemption is not supported in tickless mode and\r
- * must be set to zero in that case.\r
- */\r
-#if !defined(CH_CFG_TIME_QUANTUM)\r
-#define CH_CFG_TIME_QUANTUM 0\r
-#endif\r
-\r
-/**\r
- * @brief Idle thread automatic spawn suppression.\r
- * @details When this option is activated the function @p chSysInit()\r
- * does not spawn the idle thread. The application @p main()\r
- * function becomes the idle thread and must implement an\r
- * infinite loop.\r
- */\r
-#if !defined(CH_CFG_NO_IDLE_THREAD)\r
-#define CH_CFG_NO_IDLE_THREAD FALSE\r
-#endif\r
-\r
-/** @} */\r
-\r
-/*===========================================================================*/\r
-/**\r
- * @name Performance options\r
- * @{\r
- */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief OS optimization.\r
- * @details If enabled then time efficient rather than space efficient code\r
- * is used when two possible implementations exist.\r
- *\r
- * @note This is not related to the compiler optimization options.\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_OPTIMIZE_SPEED)\r
-#define CH_CFG_OPTIMIZE_SPEED TRUE\r
-#endif\r
-\r
-/** @} */\r
-\r
-/*===========================================================================*/\r
-/**\r
- * @name Subsystem options\r
- * @{\r
- */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Time Measurement APIs.\r
- * @details If enabled then the time measurement APIs are included in\r
- * the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_TM)\r
-#define CH_CFG_USE_TM TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Threads registry APIs.\r
- * @details If enabled then the registry APIs are included in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_REGISTRY)\r
-#define CH_CFG_USE_REGISTRY TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Threads synchronization APIs.\r
- * @details If enabled then the @p chThdWait() function is included in\r
- * the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_WAITEXIT)\r
-#define CH_CFG_USE_WAITEXIT TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Semaphores APIs.\r
- * @details If enabled then the Semaphores APIs are included in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_SEMAPHORES)\r
-#define CH_CFG_USE_SEMAPHORES TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Semaphores queuing mode.\r
- * @details If enabled then the threads are enqueued on semaphores by\r
- * priority rather than in FIFO order.\r
- *\r
- * @note The default is @p FALSE. Enable this if you have special\r
- * requirements.\r
- * @note Requires @p CH_CFG_USE_SEMAPHORES.\r
- */\r
-#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)\r
-#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Mutexes APIs.\r
- * @details If enabled then the mutexes APIs are included in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_MUTEXES)\r
-#define CH_CFG_USE_MUTEXES TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables recursive behavior on mutexes.\r
- * @note Recursive mutexes are heavier and have an increased\r
- * memory footprint.\r
- *\r
- * @note The default is @p FALSE.\r
- * @note Requires @p CH_CFG_USE_MUTEXES.\r
- */\r
-#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)\r
-#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Conditional Variables APIs.\r
- * @details If enabled then the conditional variables APIs are included\r
- * in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- * @note Requires @p CH_CFG_USE_MUTEXES.\r
- */\r
-#if !defined(CH_CFG_USE_CONDVARS)\r
-#define CH_CFG_USE_CONDVARS TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Conditional Variables APIs with timeout.\r
- * @details If enabled then the conditional variables APIs with timeout\r
- * specification are included in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- * @note Requires @p CH_CFG_USE_CONDVARS.\r
- */\r
-#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)\r
-#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Events Flags APIs.\r
- * @details If enabled then the event flags APIs are included in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_EVENTS)\r
-#define CH_CFG_USE_EVENTS TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Events Flags APIs with timeout.\r
- * @details If enabled then the events APIs with timeout specification\r
- * are included in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- * @note Requires @p CH_CFG_USE_EVENTS.\r
- */\r
-#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)\r
-#define CH_CFG_USE_EVENTS_TIMEOUT TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Synchronous Messages APIs.\r
- * @details If enabled then the synchronous messages APIs are included\r
- * in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_MESSAGES)\r
-#define CH_CFG_USE_MESSAGES TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Synchronous Messages queuing mode.\r
- * @details If enabled then messages are served by priority rather than in\r
- * FIFO order.\r
- *\r
- * @note The default is @p FALSE. Enable this if you have special\r
- * requirements.\r
- * @note Requires @p CH_CFG_USE_MESSAGES.\r
- */\r
-#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)\r
-#define CH_CFG_USE_MESSAGES_PRIORITY FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Dynamic Threads APIs.\r
- * @details If enabled then the dynamic threads creation APIs are included\r
- * in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- * @note Requires @p CH_CFG_USE_WAITEXIT.\r
- * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.\r
- */\r
-#if !defined(CH_CFG_USE_DYNAMIC)\r
-#define CH_CFG_USE_DYNAMIC TRUE\r
-#endif\r
-\r
-/** @} */\r
-\r
-/*===========================================================================*/\r
-/**\r
- * @name OSLIB options\r
- * @{\r
- */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Mailboxes APIs.\r
- * @details If enabled then the asynchronous messages (mailboxes) APIs are\r
- * included in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- * @note Requires @p CH_CFG_USE_SEMAPHORES.\r
- */\r
-#if !defined(CH_CFG_USE_MAILBOXES)\r
-#define CH_CFG_USE_MAILBOXES TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Core Memory Manager APIs.\r
- * @details If enabled then the core memory manager APIs are included\r
- * in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_MEMCORE)\r
-#define CH_CFG_USE_MEMCORE TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Managed RAM size.\r
- * @details Size of the RAM area to be managed by the OS. If set to zero\r
- * then the whole available RAM is used. The core memory is made\r
- * available to the heap allocator and/or can be used directly through\r
- * the simplified core memory allocator.\r
- *\r
- * @note In order to let the OS manage the whole RAM the linker script must\r
- * provide the @p __heap_base__ and @p __heap_end__ symbols.\r
- * @note Requires @p CH_CFG_USE_MEMCORE.\r
- */\r
-#if !defined(CH_CFG_MEMCORE_SIZE)\r
-#define CH_CFG_MEMCORE_SIZE 0\r
-#endif\r
-\r
-/**\r
- * @brief Heap Allocator APIs.\r
- * @details If enabled then the memory heap allocator APIs are included\r
- * in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or\r
- * @p CH_CFG_USE_SEMAPHORES.\r
- * @note Mutexes are recommended.\r
- */\r
-#if !defined(CH_CFG_USE_HEAP)\r
-#define CH_CFG_USE_HEAP TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Memory Pools Allocator APIs.\r
- * @details If enabled then the memory pools allocator APIs are included\r
- * in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_MEMPOOLS)\r
-#define CH_CFG_USE_MEMPOOLS TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Objects FIFOs APIs.\r
- * @details If enabled then the objects FIFOs APIs are included\r
- * in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_OBJ_FIFOS)\r
-#define CH_CFG_USE_OBJ_FIFOS TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Pipes APIs.\r
- * @details If enabled then the pipes APIs are included\r
- * in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_PIPES)\r
-#define CH_CFG_USE_PIPES TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Objects Caches APIs.\r
- * @details If enabled then the objects caches APIs are included\r
- * in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_OBJ_CACHES)\r
-#define CH_CFG_USE_OBJ_CACHES TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Delegate threads APIs.\r
- * @details If enabled then the delegate threads APIs are included\r
- * in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_DELEGATES)\r
-#define CH_CFG_USE_DELEGATES TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Jobs Queues APIs.\r
- * @details If enabled then the jobs queues APIs are included\r
- * in the kernel.\r
- *\r
- * @note The default is @p TRUE.\r
- */\r
-#if !defined(CH_CFG_USE_JOBS)\r
-#define CH_CFG_USE_JOBS TRUE\r
-#endif\r
-\r
-/** @} */\r
-\r
-/*===========================================================================*/\r
-/**\r
- * @name Objects factory options\r
- * @{\r
- */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Objects Factory APIs.\r
- * @details If enabled then the objects factory APIs are included in the\r
- * kernel.\r
- *\r
- * @note The default is @p FALSE.\r
- */\r
-#if !defined(CH_CFG_USE_FACTORY)\r
-#define CH_CFG_USE_FACTORY TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Maximum length for object names.\r
- * @details If the specified length is zero then the name is stored by\r
- * pointer but this could have unintended side effects.\r
- */\r
-#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)\r
-#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8\r
-#endif\r
-\r
-/**\r
- * @brief Enables the registry of generic objects.\r
- */\r
-#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)\r
-#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables factory for generic buffers.\r
- */\r
-#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)\r
-#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables factory for semaphores.\r
- */\r
-#if !defined(CH_CFG_FACTORY_SEMAPHORES)\r
-#define CH_CFG_FACTORY_SEMAPHORES TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables factory for mailboxes.\r
- */\r
-#if !defined(CH_CFG_FACTORY_MAILBOXES)\r
-#define CH_CFG_FACTORY_MAILBOXES TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables factory for objects FIFOs.\r
- */\r
-#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)\r
-#define CH_CFG_FACTORY_OBJ_FIFOS TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables factory for Pipes.\r
- */\r
-#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)\r
-#define CH_CFG_FACTORY_PIPES TRUE\r
-#endif\r
-\r
-/** @} */\r
-\r
-/*===========================================================================*/\r
-/**\r
- * @name Debug options\r
- * @{\r
- */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Debug option, kernel statistics.\r
- *\r
- * @note The default is @p FALSE.\r
- */\r
-#if !defined(CH_DBG_STATISTICS)\r
-#define CH_DBG_STATISTICS FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Debug option, system state check.\r
- * @details If enabled the correct call protocol for system APIs is checked\r
- * at runtime.\r
- *\r
- * @note The default is @p FALSE.\r
- */\r
-#if !defined(CH_DBG_SYSTEM_STATE_CHECK)\r
-#define CH_DBG_SYSTEM_STATE_CHECK TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Debug option, parameters checks.\r
- * @details If enabled then the checks on the API functions input\r
- * parameters are activated.\r
- *\r
- * @note The default is @p FALSE.\r
- */\r
-#if !defined(CH_DBG_ENABLE_CHECKS)\r
-#define CH_DBG_ENABLE_CHECKS TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Debug option, consistency checks.\r
- * @details If enabled then all the assertions in the kernel code are\r
- * activated. This includes consistency checks inside the kernel,\r
- * runtime anomalies and port-defined checks.\r
- *\r
- * @note The default is @p FALSE.\r
- */\r
-#if !defined(CH_DBG_ENABLE_ASSERTS)\r
-#define CH_DBG_ENABLE_ASSERTS TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Debug option, trace buffer.\r
- * @details If enabled then the trace buffer is activated.\r
- *\r
- * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.\r
- */\r
-#if !defined(CH_DBG_TRACE_MASK)\r
-#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_NONE\r
-#endif\r
-\r
-/**\r
- * @brief Trace buffer entries.\r
- * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is\r
- * different from @p CH_DBG_TRACE_MASK_DISABLED.\r
- */\r
-#if !defined(CH_DBG_TRACE_BUFFER_SIZE)\r
-#define CH_DBG_TRACE_BUFFER_SIZE 128\r
-#endif\r
-\r
-/**\r
- * @brief Debug option, stack checks.\r
- * @details If enabled then a runtime stack check is performed.\r
- *\r
- * @note The default is @p FALSE.\r
- * @note The stack check is performed in a architecture/port dependent way.\r
- * It may not be implemented or some ports.\r
- * @note The default failure mode is to halt the system with the global\r
- * @p panic_msg variable set to @p NULL.\r
- */\r
-#if !defined(CH_DBG_ENABLE_STACK_CHECK)\r
-#define CH_DBG_ENABLE_STACK_CHECK FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Debug option, stacks initialization.\r
- * @details If enabled then the threads working area is filled with a byte\r
- * value when a thread is created. This can be useful for the\r
- * runtime measurement of the used stack.\r
- *\r
- * @note The default is @p FALSE.\r
- */\r
-#if !defined(CH_DBG_FILL_THREADS)\r
-#define CH_DBG_FILL_THREADS FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Debug option, threads profiling.\r
- * @details If enabled then a field is added to the @p thread_t structure that\r
- * counts the system ticks occurred while executing the thread.\r
- *\r
- * @note The default is @p FALSE.\r
- * @note This debug option is not currently compatible with the\r
- * tickless mode.\r
- */\r
-#if !defined(CH_DBG_THREADS_PROFILING)\r
-#define CH_DBG_THREADS_PROFILING FALSE\r
-#endif\r
-\r
-/** @} */\r
-\r
-/*===========================================================================*/\r
-/**\r
- * @name Kernel hooks\r
- * @{\r
- */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief System structure extension.\r
- * @details User fields added to the end of the @p ch_system_t structure.\r
- */\r
-#define CH_CFG_SYSTEM_EXTRA_FIELDS \\r
- /* Add threads custom fields here.*/\r
-\r
-/**\r
- * @brief System initialization hook.\r
- * @details User initialization code added to the @p chSysInit() function\r
- * just before interrupts are enabled globally.\r
- */\r
-#define CH_CFG_SYSTEM_INIT_HOOK() { \\r
- /* Add threads initialization code here.*/ \\r
-}\r
-\r
-/**\r
- * @brief Threads descriptor structure extension.\r
- * @details User fields added to the end of the @p thread_t structure.\r
- */\r
-#define CH_CFG_THREAD_EXTRA_FIELDS \\r
- /* Add threads custom fields here.*/\r
-\r
-/**\r
- * @brief Threads initialization hook.\r
- * @details User initialization code added to the @p _thread_init() function.\r
- *\r
- * @note It is invoked from within @p _thread_init() and implicitly from all\r
- * the threads creation APIs.\r
- */\r
-#define CH_CFG_THREAD_INIT_HOOK(tp) { \\r
- /* Add threads initialization code here.*/ \\r
-}\r
-\r
-/**\r
- * @brief Threads finalization hook.\r
- * @details User finalization code added to the @p chThdExit() API.\r
- */\r
-#define CH_CFG_THREAD_EXIT_HOOK(tp) { \\r
- /* Add threads finalization code here.*/ \\r
-}\r
-\r
-/**\r
- * @brief Context switch hook.\r
- * @details This hook is invoked just before switching between threads.\r
- */\r
-#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \\r
- /* Context switch code here.*/ \\r
-}\r
-\r
-/**\r
- * @brief ISR enter hook.\r
- */\r
-#define CH_CFG_IRQ_PROLOGUE_HOOK() { \\r
- /* IRQ prologue code here.*/ \\r
-}\r
-\r
-/**\r
- * @brief ISR exit hook.\r
- */\r
-#define CH_CFG_IRQ_EPILOGUE_HOOK() { \\r
- /* IRQ epilogue code here.*/ \\r
-}\r
-\r
-/**\r
- * @brief Idle thread enter hook.\r
- * @note This hook is invoked within a critical zone, no OS functions\r
- * should be invoked from here.\r
- * @note This macro can be used to activate a power saving mode.\r
- */\r
-#define CH_CFG_IDLE_ENTER_HOOK() { \\r
- /* Idle-enter code here.*/ \\r
-}\r
-\r
-/**\r
- * @brief Idle thread leave hook.\r
- * @note This hook is invoked within a critical zone, no OS functions\r
- * should be invoked from here.\r
- * @note This macro can be used to deactivate a power saving mode.\r
- */\r
-#define CH_CFG_IDLE_LEAVE_HOOK() { \\r
- /* Idle-leave code here.*/ \\r
-}\r
-\r
-/**\r
- * @brief Idle Loop hook.\r
- * @details This hook is continuously invoked by the idle thread loop.\r
- */\r
-#define CH_CFG_IDLE_LOOP_HOOK() { \\r
- /* Idle loop code here.*/ \\r
-}\r
-\r
-/**\r
- * @brief System tick event hook.\r
- * @details This hook is invoked in the system tick handler immediately\r
- * after processing the virtual timers queue.\r
- */\r
-#define CH_CFG_SYSTEM_TICK_HOOK() { \\r
- /* System tick event code here.*/ \\r
-}\r
-\r
-/**\r
- * @brief System halt hook.\r
- * @details This hook is invoked in case to a system halting error before\r
- * the system is halted.\r
- */\r
-#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \\r
- /* System halt code here.*/ \\r
-}\r
-\r
-/**\r
- * @brief Trace hook.\r
- * @details This hook is invoked each time a new record is written in the\r
- * trace buffer.\r
- */\r
-#define CH_CFG_TRACE_HOOK(tep) { \\r
- /* Trace code here.*/ \\r
-}\r
-\r
-/** @} */\r
-\r
-/*===========================================================================*/\r
-/* Port-specific settings (override port settings defaulted in chcore.h). */\r
-/*===========================================================================*/\r
-\r
-#endif /* CHCONF_H */\r
-\r
-/** @} */\r
+++ /dev/null
-/*\r
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
-\r
- Licensed under the Apache License, Version 2.0 (the "License");\r
- you may not use this file except in compliance with the License.\r
- You may obtain a copy of the License at\r
-\r
- http://www.apache.org/licenses/LICENSE-2.0\r
-\r
- Unless required by applicable law or agreed to in writing, software\r
- distributed under the License is distributed on an "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- See the License for the specific language governing permissions and\r
- limitations under the License.\r
-*/\r
-\r
-/**\r
- * @file templates/halconf.h\r
- * @brief HAL configuration header.\r
- * @details HAL configuration file, this file allows to enable or disable the\r
- * various device drivers from your application. You may also use\r
- * this file in order to override the device drivers default settings.\r
- *\r
- * @addtogroup HAL_CONF\r
- * @{\r
- */\r
-\r
-#ifndef HALCONF_H\r
-#define HALCONF_H\r
-\r
-#define _CHIBIOS_HAL_CONF_\r
-#define _CHIBIOS_HAL_CONF_VER_7_1_\r
-\r
-#include "mcuconf.h"\r
-\r
-/**\r
- * @brief Enables the PAL subsystem.\r
- */\r
-#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)\r
-#define HAL_USE_PAL TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the ADC subsystem.\r
- */\r
-#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)\r
-#define HAL_USE_ADC TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the CAN subsystem.\r
- */\r
-#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)\r
-#define HAL_USE_CAN FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the cryptographic subsystem.\r
- */\r
-#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)\r
-#define HAL_USE_CRY FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the DAC subsystem.\r
- */\r
-#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)\r
-#define HAL_USE_DAC TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the EFlash subsystem.\r
- */\r
-#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)\r
-#define HAL_USE_EFL FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the GPT subsystem.\r
- */\r
-#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)\r
-#define HAL_USE_GPT TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the I2C subsystem.\r
- */\r
-#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)\r
-#define HAL_USE_I2C FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the I2S subsystem.\r
- */\r
-#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)\r
-#define HAL_USE_I2S FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the ICU subsystem.\r
- */\r
-#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)\r
-#define HAL_USE_ICU FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the MAC subsystem.\r
- */\r
-#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)\r
-#define HAL_USE_MAC FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the MMC_SPI subsystem.\r
- */\r
-#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)\r
-#define HAL_USE_MMC_SPI FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the PWM subsystem.\r
- */\r
-#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)\r
-#define HAL_USE_PWM FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the RTC subsystem.\r
- */\r
-#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)\r
-#define HAL_USE_RTC FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the SDC subsystem.\r
- */\r
-#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)\r
-#define HAL_USE_SDC FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the SERIAL subsystem.\r
- */\r
-#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)\r
-#define HAL_USE_SERIAL FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the SERIAL over USB subsystem.\r
- */\r
-#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)\r
-#define HAL_USE_SERIAL_USB TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the SIO subsystem.\r
- */\r
-#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)\r
-#define HAL_USE_SIO FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the SPI subsystem.\r
- */\r
-#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)\r
-#define HAL_USE_SPI FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the TRNG subsystem.\r
- */\r
-#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)\r
-#define HAL_USE_TRNG FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the UART subsystem.\r
- */\r
-#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)\r
-#define HAL_USE_UART FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the USB subsystem.\r
- */\r
-#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)\r
-#define HAL_USE_USB TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the WDG subsystem.\r
- */\r
-#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)\r
-#define HAL_USE_WDG FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the WSPI subsystem.\r
- */\r
-#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)\r
-#define HAL_USE_WSPI FALSE\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* PAL driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Enables synchronous APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)\r
-#define PAL_USE_CALLBACKS FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables synchronous APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)\r
-#define PAL_USE_WAIT FALSE\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* ADC driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Enables synchronous APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)\r
-#define ADC_USE_WAIT FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
-#define ADC_USE_MUTUAL_EXCLUSION FALSE\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* CAN driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Sleep mode related APIs inclusion switch.\r
- */\r
-#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)\r
-#define CAN_USE_SLEEP_MODE TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enforces the driver to use direct callbacks rather than OSAL events.\r
- */\r
-#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)\r
-#define CAN_ENFORCE_USE_CALLBACKS FALSE\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* CRY driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Enables the SW fall-back of the cryptographic driver.\r
- * @details When enabled, this option, activates a fall-back software\r
- * implementation for algorithms not supported by the underlying\r
- * hardware.\r
- * @note Fall-back implementations may not be present for all algorithms.\r
- */\r
-#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)\r
-#define HAL_CRY_USE_FALLBACK FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Makes the driver forcibly use the fall-back implementations.\r
- */\r
-#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)\r
-#define HAL_CRY_ENFORCE_FALLBACK FALSE\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* DAC driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Enables synchronous APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)\r
-#define DAC_USE_WAIT FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
-#define DAC_USE_MUTUAL_EXCLUSION FALSE\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* I2C driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Enables the mutual exclusion APIs on the I2C bus.\r
- */\r
-#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
-#define I2C_USE_MUTUAL_EXCLUSION TRUE\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* MAC driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Enables the zero-copy API.\r
- */\r
-#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)\r
-#define MAC_USE_ZERO_COPY FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables an event sources for incoming packets.\r
- */\r
-#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)\r
-#define MAC_USE_EVENTS TRUE\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* MMC_SPI driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Delays insertions.\r
- * @details If enabled this options inserts delays into the MMC waiting\r
- * routines releasing some extra CPU time for the threads with\r
- * lower priority, this may slow down the driver a bit however.\r
- * This option is recommended also if the SPI driver does not\r
- * use a DMA channel and heavily loads the CPU.\r
- */\r
-#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)\r
-#define MMC_NICE_WAITING TRUE\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* SDC driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Number of initialization attempts before rejecting the card.\r
- * @note Attempts are performed at 10mS intervals.\r
- */\r
-#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)\r
-#define SDC_INIT_RETRY 100\r
-#endif\r
-\r
-/**\r
- * @brief Include support for MMC cards.\r
- * @note MMC support is not yet implemented so this option must be kept\r
- * at @p FALSE.\r
- */\r
-#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)\r
-#define SDC_MMC_SUPPORT FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Delays insertions.\r
- * @details If enabled this options inserts delays into the MMC waiting\r
- * routines releasing some extra CPU time for the threads with\r
- * lower priority, this may slow down the driver a bit however.\r
- */\r
-#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)\r
-#define SDC_NICE_WAITING TRUE\r
-#endif\r
-\r
-/**\r
- * @brief OCR initialization constant for V20 cards.\r
- */\r
-#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)\r
-#define SDC_INIT_OCR_V20 0x50FF8000U\r
-#endif\r
-\r
-/**\r
- * @brief OCR initialization constant for non-V20 cards.\r
- */\r
-#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)\r
-#define SDC_INIT_OCR 0x80100000U\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* SERIAL driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Default bit rate.\r
- * @details Configuration parameter, this is the baud rate selected for the\r
- * default configuration.\r
- */\r
-#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)\r
-#define SERIAL_DEFAULT_BITRATE 38400\r
-#endif\r
-\r
-/**\r
- * @brief Serial buffers size.\r
- * @details Configuration parameter, you can change the depth of the queue\r
- * buffers depending on the requirements of your application.\r
- * @note The default is 16 bytes for both the transmission and receive\r
- * buffers.\r
- */\r
-#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)\r
-#define SERIAL_BUFFERS_SIZE 16\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* SERIAL_USB driver related setting. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Serial over USB buffers size.\r
- * @details Configuration parameter, the buffer size must be a multiple of\r
- * the USB data endpoint maximum packet size.\r
- * @note The default is 256 bytes for both the transmission and receive\r
- * buffers.\r
- */\r
-#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)\r
-#define SERIAL_USB_BUFFERS_SIZE 256\r
-#endif\r
-\r
-/**\r
- * @brief Serial over USB number of buffers.\r
- * @note The default is 2 buffers.\r
- */\r
-#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)\r
-#define SERIAL_USB_BUFFERS_NUMBER 2\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* SPI driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Enables synchronous APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)\r
-#define SPI_USE_WAIT TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables circular transfers APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)\r
-#define SPI_USE_CIRCULAR FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
-#define SPI_USE_MUTUAL_EXCLUSION TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Handling method for SPI CS line.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)\r
-#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* UART driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Enables synchronous APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)\r
-#define UART_USE_WAIT FALSE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
-#define UART_USE_MUTUAL_EXCLUSION FALSE\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* USB driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Enables synchronous APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)\r
-#define USB_USE_WAIT FALSE\r
-#endif\r
-\r
-/*===========================================================================*/\r
-/* WSPI driver related settings. */\r
-/*===========================================================================*/\r
-\r
-/**\r
- * @brief Enables synchronous APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)\r
-#define WSPI_USE_WAIT TRUE\r
-#endif\r
-\r
-/**\r
- * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.\r
- * @note Disabling this option saves both code and data space.\r
- */\r
-#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
-#define WSPI_USE_MUTUAL_EXCLUSION TRUE\r
-#endif\r
-\r
-#endif /* HALCONF_H */\r
-\r
-/** @} */\r
+++ /dev/null
-#if defined(TARGET_PLATFORM_L4)\r
-#include "mcuconf_l4.h"\r
-#elif defined(TARGET_PLATFORM_H7)\r
-#include "mcuconf_h7.h"\r
-#elif defined(TARGET_PLATFORM_G4)\r
-#include "mcuconf_g4.h"\r
-#endif\r
+++ /dev/null
-/*\r
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
-\r
- Licensed under the Apache License, Version 2.0 (the "License");\r
- you may not use this file except in compliance with the License.\r
- You may obtain a copy of the License at\r
-\r
- http://www.apache.org/licenses/LICENSE-2.0\r
-\r
- Unless required by applicable law or agreed to in writing, software\r
- distributed under the License is distributed on an "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- See the License for the specific language governing permissions and\r
- limitations under the License.\r
-*/\r
-\r
-#ifndef MCUCONF_H\r
-#define MCUCONF_H\r
-\r
-/*\r
- * STM32H7xx drivers configuration.\r
- * The following settings override the default settings present in\r
- * the various device driver implementation headers.\r
- * Note that the settings for each driver only have effect if the whole\r
- * driver is enabled in halconf.h.\r
- *\r
- * IRQ priorities:\r
- * 15...0 Lowest...Highest.\r
- *\r
- * DMA priorities:\r
- * 0...3 Lowest...Highest.\r
- */\r
-\r
-#define STM32H7xx_MCUCONF\r
-#define STM32H723_MCUCONF\r
-#define STM32H725_MCUCONF\r
-//#define STM32H743_MCUCONF\r
-\r
-/*\r
- * General settings.\r
- */\r
-#define STM32_NO_INIT FALSE\r
-#define STM32_TARGET_CORE 1\r
-\r
-/*\r
- * Memory attributes settings.\r
- */\r
-#define STM32_NOCACHE_MPU_REGION MPU_REGION_1\r
-#define STM32_NOCACHE_SRAM1_SRAM2 FALSE\r
-#define STM32_NOCACHE_SRAM3 FALSE\r
-#define STM32_NOCACHE_ALLSRAM TRUE\r
-\r
-/*\r
- * PWR system settings.\r
- * Reading STM32 Reference Manual is required, settings in PWR_CR3 are\r
- * very critical.\r
- * Register constants are taken from the ST header.\r
- */\r
-#define STM32_VOS STM32_VOS_SCALE1\r
-#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)\r
-#define STM32_PWR_CR2 (PWR_CR2_BREN)\r
-#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)\r
-#define STM32_PWR_CPUCR 0\r
-\r
-/*\r
- * Clock tree static settings.\r
- * Reading STM32 Reference Manual is required.\r
- */\r
-#define STM32_HSI_ENABLED TRUE\r
-#define STM32_LSI_ENABLED TRUE\r
-#define STM32_CSI_ENABLED FALSE\r
-#define STM32_HSI48_ENABLED TRUE\r
-#define STM32_HSE_ENABLED FALSE\r
-#define STM32_LSE_ENABLED FALSE\r
-#define STM32_HSIDIV STM32_HSIDIV_DIV8 // HSI = 8MHz\r
-\r
-/*\r
- * PLLs static settings.\r
- * Reading STM32 Reference Manual is required.\r
- */\r
-#define STM32_PLLSRC STM32_PLLSRC_HSI_CK\r
-#define STM32_PLLCFGR_MASK ~0\r
-#define STM32_PLL1_ENABLED TRUE\r
-#define STM32_PLL1_P_ENABLED TRUE\r
-#define STM32_PLL1_Q_ENABLED FALSE\r
-#define STM32_PLL1_R_ENABLED FALSE\r
-#define STM32_PLL1_DIVM_VALUE 4 // 8 / 4 = 2MHz\r
-#define STM32_PLL1_DIVN_VALUE 240 // = 2 * 240\r
-#define STM32_PLL1_FRACN_VALUE 0\r
-#define STM32_PLL1_DIVP_VALUE 1 // = 480MHz\r
-#define STM32_PLL1_DIVQ_VALUE 16\r
-#define STM32_PLL1_DIVR_VALUE 8\r
-#define STM32_PLL2_ENABLED TRUE // PLL2 adjusted by adc.cpp\r
-#define STM32_PLL2_P_ENABLED TRUE\r
-#define STM32_PLL2_Q_ENABLED FALSE\r
-#define STM32_PLL2_R_ENABLED FALSE\r
-#define STM32_PLL2_DIVM_VALUE 4\r
-#define STM32_PLL2_DIVN_VALUE 80\r
-#define STM32_PLL2_FRACN_VALUE 0\r
-#define STM32_PLL2_DIVP_VALUE 20\r
-#define STM32_PLL2_DIVQ_VALUE 8\r
-#define STM32_PLL2_DIVR_VALUE 8\r
-#define STM32_PLL3_ENABLED FALSE\r
-#define STM32_PLL3_P_ENABLED FALSE\r
-#define STM32_PLL3_Q_ENABLED FALSE\r
-#define STM32_PLL3_R_ENABLED FALSE\r
-#define STM32_PLL3_DIVM_VALUE 4\r
-#define STM32_PLL3_DIVN_VALUE 400\r
-#define STM32_PLL3_FRACN_VALUE 0\r
-#define STM32_PLL3_DIVP_VALUE 8\r
-#define STM32_PLL3_DIVQ_VALUE 8\r
-#define STM32_PLL3_DIVR_VALUE 8\r
-\r
-/*\r
- * Core clocks dynamic settings (can be changed at runtime).\r
- * Reading STM32 Reference Manual is required.\r
- */\r
-#define STM32_SW STM32_SW_PLL1_P_CK\r
-#define STM32_RTCSEL STM32_RTCSEL_LSI_CK\r
-#define STM32_D1CPRE STM32_D1CPRE_DIV1\r
-#define STM32_D1HPRE STM32_D1HPRE_DIV2 // /2 = 240MHz\r
-#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2\r
-#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2\r
-#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2\r
-#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2\r
-\r
-/*\r
- * Peripherals clocks static settings.\r
- * Reading STM32 Reference Manual is required.\r
- */\r
-#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK\r
-#define STM32_MCO1PRE_VALUE 4\r
-#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK\r
-#define STM32_MCO2PRE_VALUE 4\r
-#define STM32_TIMPRE_ENABLE TRUE\r
-#define STM32_HRTIMSEL 0\r
-#define STM32_STOPKERWUCK 0\r
-#define STM32_STOPWUCK 0\r
-#define STM32_RTCPRE_VALUE 8\r
-#define STM32_CKPERSEL STM32_CKPERSEL_HSI_CK\r
-#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK\r
-//#define STM32_OCTOSPISEL STM32_OCTOSPISEL_HCLK\r
-//#define STM32_FMCSEL STM32_OCTOSPISEL_HCLK\r
-#define STM32_SWPSEL STM32_SWPSEL_PCLK1\r
-#define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK\r
-#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2\r
-#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK\r
-#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2\r
-#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK\r
-//#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK\r
-#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK\r
-#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1\r
-#define STM32_CECSEL STM32_CECSEL_LSE_CK\r
-#define STM32_USBSEL STM32_USBSEL_HSI48_CK\r
-#define STM32_I2C1235SEL STM32_I2C1235SEL_PCLK1\r
-#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK\r
-#define STM32_USART16910SEL STM32_USART16910SEL_PCLK2\r
-#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1\r
-#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4\r
-#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK\r
-#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK\r
-#define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK\r
-#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4\r
-#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4\r
-#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4\r
-#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4\r
-\r
-/*\r
- * IRQ system settings.\r
- */\r
-#define STM32_IRQ_EXTI0_PRIORITY 6\r
-#define STM32_IRQ_EXTI1_PRIORITY 6\r
-#define STM32_IRQ_EXTI2_PRIORITY 6\r
-#define STM32_IRQ_EXTI3_PRIORITY 6\r
-#define STM32_IRQ_EXTI4_PRIORITY 6\r
-#define STM32_IRQ_EXTI5_9_PRIORITY 6\r
-#define STM32_IRQ_EXTI10_15_PRIORITY 6\r
-#define STM32_IRQ_EXTI16_PRIORITY 6\r
-#define STM32_IRQ_EXTI17_PRIORITY 6\r
-#define STM32_IRQ_EXTI18_PRIORITY 6\r
-#define STM32_IRQ_EXTI19_PRIORITY 6\r
-#define STM32_IRQ_EXTI20_21_PRIORITY 6\r
-\r
-#define STM32_IRQ_FDCAN1_PRIORITY 10\r
-#define STM32_IRQ_FDCAN2_PRIORITY 10\r
-\r
-#define STM32_IRQ_MDMA_PRIORITY 9\r
-\r
-#define STM32_IRQ_QUADSPI1_PRIORITY 10\r
-\r
-#define STM32_IRQ_SDMMC1_PRIORITY 9\r
-#define STM32_IRQ_SDMMC2_PRIORITY 9\r
-\r
-#define STM32_IRQ_TIM1_UP_PRIORITY 7\r
-#define STM32_IRQ_TIM1_CC_PRIORITY 7\r
-#define STM32_IRQ_TIM2_PRIORITY 7\r
-#define STM32_IRQ_TIM3_PRIORITY 7\r
-#define STM32_IRQ_TIM4_PRIORITY 7\r
-#define STM32_IRQ_TIM5_PRIORITY 7\r
-#define STM32_IRQ_TIM6_PRIORITY 7\r
-#define STM32_IRQ_TIM7_PRIORITY 7\r
-#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7\r
-#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7\r
-#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7\r
-#define STM32_IRQ_TIM8_CC_PRIORITY 7\r
-#define STM32_IRQ_TIM15_PRIORITY 7\r
-#define STM32_IRQ_TIM16_PRIORITY 7\r
-#define STM32_IRQ_TIM17_PRIORITY 7\r
-\r
-#define STM32_IRQ_USART1_PRIORITY 12\r
-#define STM32_IRQ_USART2_PRIORITY 12\r
-#define STM32_IRQ_USART3_PRIORITY 12\r
-#define STM32_IRQ_UART4_PRIORITY 12\r
-#define STM32_IRQ_UART5_PRIORITY 12\r
-#define STM32_IRQ_USART6_PRIORITY 12\r
-#define STM32_IRQ_UART7_PRIORITY 12\r
-#define STM32_IRQ_UART8_PRIORITY 12\r
-#define STM32_IRQ_LPUART1_PRIORITY 12\r
-\r
-/*\r
- * ADC driver system settings.\r
- */\r
-#define STM32_ADC_DUAL_MODE FALSE\r
-#define STM32_ADC_COMPACT_SAMPLES FALSE\r
-#define STM32_ADC_USE_ADC12 FALSE\r
-#define STM32_ADC_USE_ADC3 TRUE\r
-#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY\r
-#define STM32_ADC_ADC12_DMA_PRIORITY 2\r
-#define STM32_ADC_ADC3_DMA_PRIORITY 2\r
-#define STM32_ADC_ADC12_IRQ_PRIORITY 5\r
-#define STM32_ADC_ADC3_IRQ_PRIORITY 5\r
-#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4\r
-#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_ADCCK\r
-#define STM32_ADC_ADC3_PRESC (5 << ADC_CCR_PRESC_Pos) // /10\r
-\r
-/*\r
- * CAN driver system settings.\r
- */\r
-#define STM32_CAN_USE_FDCAN1 FALSE\r
-#define STM32_CAN_USE_FDCAN2 FALSE\r
-\r
-/*\r
- * DAC driver system settings.\r
- */\r
-#define STM32_DAC_DUAL_MODE FALSE\r
-#define STM32_DAC_USE_DAC1_CH1 TRUE\r
-#define STM32_DAC_USE_DAC1_CH2 TRUE\r
-#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10\r
-#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10\r
-#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2\r
-#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2\r
-#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-\r
-/*\r
- * GPT driver system settings.\r
- */\r
-#define STM32_GPT_USE_TIM1 FALSE\r
-#define STM32_GPT_USE_TIM2 FALSE\r
-#define STM32_GPT_USE_TIM3 FALSE\r
-#define STM32_GPT_USE_TIM4 FALSE\r
-#define STM32_GPT_USE_TIM5 FALSE\r
-#define STM32_GPT_USE_TIM6 TRUE\r
-#define STM32_GPT_USE_TIM7 FALSE\r
-#define STM32_GPT_USE_TIM8 FALSE\r
-#define STM32_GPT_USE_TIM12 FALSE\r
-#define STM32_GPT_USE_TIM13 FALSE\r
-#define STM32_GPT_USE_TIM14 FALSE\r
-#define STM32_GPT_USE_TIM15 FALSE\r
-#define STM32_GPT_USE_TIM16 FALSE\r
-#define STM32_GPT_USE_TIM17 FALSE\r
-\r
-/*\r
- * I2C driver system settings.\r
- */\r
-#define STM32_I2C_USE_I2C1 FALSE\r
-#define STM32_I2C_USE_I2C2 FALSE\r
-#define STM32_I2C_USE_I2C3 FALSE\r
-#define STM32_I2C_USE_I2C4 FALSE\r
-#define STM32_I2C_BUSY_TIMEOUT 50\r
-#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY\r
-#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY\r
-#define STM32_I2C_I2C1_IRQ_PRIORITY 5\r
-#define STM32_I2C_I2C2_IRQ_PRIORITY 5\r
-#define STM32_I2C_I2C3_IRQ_PRIORITY 5\r
-#define STM32_I2C_I2C4_IRQ_PRIORITY 5\r
-#define STM32_I2C_I2C1_DMA_PRIORITY 3\r
-#define STM32_I2C_I2C2_DMA_PRIORITY 3\r
-#define STM32_I2C_I2C3_DMA_PRIORITY 3\r
-#define STM32_I2C_I2C4_DMA_PRIORITY 3\r
-#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")\r
-\r
-/*\r
- * ICU driver system settings.\r
- */\r
-#define STM32_ICU_USE_TIM1 FALSE\r
-#define STM32_ICU_USE_TIM2 FALSE\r
-#define STM32_ICU_USE_TIM3 FALSE\r
-#define STM32_ICU_USE_TIM4 FALSE\r
-#define STM32_ICU_USE_TIM5 FALSE\r
-#define STM32_ICU_USE_TIM8 FALSE\r
-#define STM32_ICU_USE_TIM12 FALSE\r
-#define STM32_ICU_USE_TIM13 FALSE\r
-#define STM32_ICU_USE_TIM14 FALSE\r
-#define STM32_ICU_USE_TIM15 FALSE\r
-#define STM32_ICU_USE_TIM16 FALSE\r
-#define STM32_ICU_USE_TIM17 FALSE\r
-\r
-/*\r
- * MAC driver system settings.\r
- */\r
-#define STM32_MAC_TRANSMIT_BUFFERS 2\r
-#define STM32_MAC_RECEIVE_BUFFERS 4\r
-#define STM32_MAC_BUFFERS_SIZE 1522\r
-#define STM32_MAC_PHY_TIMEOUT 100\r
-#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE\r
-#define STM32_MAC_ETH1_IRQ_PRIORITY 13\r
-#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0\r
-\r
-/*\r
- * PWM driver system settings.\r
- */\r
-#define STM32_PWM_USE_ADVANCED FALSE\r
-#define STM32_PWM_USE_TIM1 FALSE\r
-#define STM32_PWM_USE_TIM2 FALSE\r
-#define STM32_PWM_USE_TIM3 FALSE\r
-#define STM32_PWM_USE_TIM4 FALSE\r
-#define STM32_PWM_USE_TIM5 FALSE\r
-#define STM32_PWM_USE_TIM8 FALSE\r
-#define STM32_PWM_USE_TIM12 FALSE\r
-#define STM32_PWM_USE_TIM13 FALSE\r
-#define STM32_PWM_USE_TIM14 FALSE\r
-#define STM32_PWM_USE_TIM15 FALSE\r
-#define STM32_PWM_USE_TIM16 FALSE\r
-#define STM32_PWM_USE_TIM17 FALSE\r
-\r
-/*\r
- * RTC driver system settings.\r
- */\r
-#define STM32_RTC_PRESA_VALUE 32\r
-#define STM32_RTC_PRESS_VALUE 1024\r
-#define STM32_RTC_CR_INIT 0\r
-#define STM32_RTC_TAMPCR_INIT 0\r
-\r
-/*\r
- * SDC driver system settings.\r
- */\r
-#define STM32_SDC_USE_SDMMC1 FALSE\r
-#define STM32_SDC_USE_SDMMC2 FALSE\r
-#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE\r
-#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000000\r
-#define STM32_SDC_SDMMC_READ_TIMEOUT 1000000\r
-#define STM32_SDC_SDMMC_CLOCK_DELAY 10\r
-#define STM32_SDC_SDMMC_PWRSAV TRUE\r
-\r
-/*\r
- * SERIAL driver system settings.\r
- */\r
-#define STM32_SERIAL_USE_USART1 FALSE\r
-#define STM32_SERIAL_USE_USART2 FALSE\r
-#define STM32_SERIAL_USE_USART3 FALSE\r
-#define STM32_SERIAL_USE_UART4 FALSE\r
-#define STM32_SERIAL_USE_UART5 FALSE\r
-#define STM32_SERIAL_USE_USART6 FALSE\r
-#define STM32_SERIAL_USE_UART7 FALSE\r
-#define STM32_SERIAL_USE_UART8 FALSE\r
-\r
-/*\r
- * SPI driver system settings.\r
- */\r
-#define STM32_SPI_USE_SPI1 FALSE\r
-#define STM32_SPI_USE_SPI2 FALSE\r
-#define STM32_SPI_USE_SPI3 FALSE\r
-#define STM32_SPI_USE_SPI4 FALSE\r
-#define STM32_SPI_USE_SPI5 FALSE\r
-#define STM32_SPI_USE_SPI6 FALSE\r
-#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY\r
-#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY\r
-#define STM32_SPI_SPI1_DMA_PRIORITY 1\r
-#define STM32_SPI_SPI2_DMA_PRIORITY 1\r
-#define STM32_SPI_SPI3_DMA_PRIORITY 1\r
-#define STM32_SPI_SPI4_DMA_PRIORITY 1\r
-#define STM32_SPI_SPI5_DMA_PRIORITY 1\r
-#define STM32_SPI_SPI6_DMA_PRIORITY 1\r
-#define STM32_SPI_SPI1_IRQ_PRIORITY 10\r
-#define STM32_SPI_SPI2_IRQ_PRIORITY 10\r
-#define STM32_SPI_SPI3_IRQ_PRIORITY 10\r
-#define STM32_SPI_SPI4_IRQ_PRIORITY 10\r
-#define STM32_SPI_SPI5_IRQ_PRIORITY 10\r
-#define STM32_SPI_SPI6_IRQ_PRIORITY 10\r
-#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")\r
-\r
-/*\r
- * ST driver system settings.\r
- */\r
-#define STM32_ST_IRQ_PRIORITY 8\r
-#define STM32_ST_USE_TIMER 2\r
-\r
-/*\r
- * TRNG driver system settings.\r
- */\r
-#define STM32_TRNG_USE_RNG1 FALSE\r
-\r
-/*\r
- * UART driver system settings.\r
- */\r
-#define STM32_UART_USE_USART1 FALSE\r
-#define STM32_UART_USE_USART2 FALSE\r
-#define STM32_UART_USE_USART3 FALSE\r
-#define STM32_UART_USE_UART4 FALSE\r
-#define STM32_UART_USE_UART5 FALSE\r
-#define STM32_UART_USE_USART6 FALSE\r
-#define STM32_UART_USE_UART7 FALSE\r
-#define STM32_UART_USE_UART8 FALSE\r
-#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
-#define STM32_UART_USART1_DMA_PRIORITY 0\r
-#define STM32_UART_USART2_DMA_PRIORITY 0\r
-#define STM32_UART_USART3_DMA_PRIORITY 0\r
-#define STM32_UART_UART4_DMA_PRIORITY 0\r
-#define STM32_UART_UART5_DMA_PRIORITY 0\r
-#define STM32_UART_USART6_DMA_PRIORITY 0\r
-#define STM32_UART_UART7_DMA_PRIORITY 0\r
-#define STM32_UART_UART8_DMA_PRIORITY 0\r
-#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")\r
-\r
-/*\r
- * USB driver system settings.\r
- */\r
-#define STM32_USB_USE_OTG1 FALSE\r
-#define STM32_USB_USE_OTG2 TRUE\r
-#define STM32_USB_OTG1_IRQ_PRIORITY 14\r
-#define STM32_USB_OTG2_IRQ_PRIORITY 14\r
-#define STM32_USB_OTG1_RX_FIFO_SIZE 512\r
-#define STM32_USB_OTG2_RX_FIFO_SIZE 1024\r
-#define STM32_USB_HOST_WAKEUP_DURATION 2\r
-\r
-/*\r
- * WDG driver system settings.\r
- */\r
-#define STM32_WDG_USE_IWDG FALSE\r
-\r
-/*\r
- * WSPI driver system settings.\r
- */\r
-#define STM32_WSPI_USE_QUADSPI1 FALSE\r
-#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1\r
-#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY\r
-#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1\r
-#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")\r
-\r
-#endif /* MCUCONF_H */\r
+++ /dev/null
-/*\r
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
-\r
- Licensed under the Apache License, Version 2.0 (the "License");\r
- you may not use this file except in compliance with the License.\r
- You may obtain a copy of the License at\r
-\r
- http://www.apache.org/licenses/LICENSE-2.0\r
-\r
- Unless required by applicable law or agreed to in writing, software\r
- distributed under the License is distributed on an "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- See the License for the specific language governing permissions and\r
- limitations under the License.\r
-*/\r
-\r
-/*\r
- * STM32L4xx drivers configuration.\r
- * The following settings override the default settings present in\r
- * the various device driver implementation headers.\r
- * Note that the settings for each driver only have effect if the whole\r
- * driver is enabled in halconf.h.\r
- *\r
- * IRQ priorities:\r
- * 15...0 Lowest...Highest.\r
- *\r
- * DMA priorities:\r
- * 0...3 Lowest...Highest.\r
- */\r
-\r
-#ifndef MCUCONF_H\r
-#define MCUCONF_H\r
-\r
-#define STM32L4xx_MCUCONF\r
-#define STM32L476_MCUCONF\r
-//#define STM32L432_MCUCONF\r
-\r
-/*\r
- * HAL driver system settings.\r
- */\r
-#define STM32_NO_INIT FALSE\r
-#define STM32_VOS STM32_VOS_RANGE1\r
-#define STM32_PVD_ENABLE FALSE\r
-#define STM32_PLS STM32_PLS_LEV0\r
-#define STM32_HSI16_ENABLED FALSE\r
-#define STM32_LSI_ENABLED TRUE\r
-#define STM32_HSE_ENABLED FALSE\r
-#define STM32_LSE_ENABLED FALSE\r
-#define STM32_MSIPLL_ENABLED FALSE\r
-#define STM32_MSIRANGE STM32_MSIRANGE_8M\r
-#define STM32_MSISRANGE STM32_MSISRANGE_4M\r
-#define STM32_SW STM32_SW_PLL\r
-#define STM32_PLLSRC STM32_PLLSRC_MSI\r
-#define STM32_PLLM_VALUE 2\r
-#define STM32_PLLN_VALUE 72\r
-#define STM32_PLLP_VALUE 7\r
-#define STM32_PLLQ_VALUE 6\r
-#define STM32_PLLR_VALUE 4\r
-#define STM32_HPRE STM32_HPRE_DIV1\r
-#define STM32_PPRE1 STM32_PPRE1_DIV1\r
-#define STM32_PPRE2 STM32_PPRE2_DIV1\r
-#define STM32_STOPWUCK STM32_STOPWUCK_MSI\r
-#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK\r
-#define STM32_MCOPRE STM32_MCOPRE_DIV1\r
-#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK\r
-#define STM32_PLLSAI1N_VALUE 24\r
-#define STM32_PLLSAI1P_VALUE 7\r
-#define STM32_PLLSAI1Q_VALUE 2\r
-#define STM32_PLLSAI1R_VALUE 4\r
-#define STM32_PLLSAI2N_VALUE 24\r
-#define STM32_PLLSAI2P_VALUE 7\r
-#define STM32_PLLSAI2R_VALUE 8\r
-\r
-/*\r
- * Peripherals clock sources.\r
- */\r
-#define STM32_USART1SEL STM32_USART1SEL_SYSCLK\r
-#define STM32_USART2SEL STM32_USART2SEL_SYSCLK\r
-#define STM32_USART3SEL STM32_USART3SEL_SYSCLK\r
-#define STM32_UART4SEL STM32_UART4SEL_SYSCLK\r
-#define STM32_UART5SEL STM32_UART5SEL_SYSCLK\r
-#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK\r
-#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK\r
-#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK\r
-#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK\r
-#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1\r
-#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1\r
-#define STM32_SAI1SEL STM32_SAI1SEL_OFF\r
-#define STM32_SAI2SEL STM32_SAI2SEL_OFF\r
-#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1\r
-#define STM32_ADCSEL STM32_ADCSEL_PLLSAI2\r
-#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1\r
-#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2\r
-#define STM32_RTCSEL STM32_RTCSEL_LSI\r
-\r
-/*\r
- * IRQ system settings.\r
- */\r
-#define STM32_IRQ_EXTI0_PRIORITY 6\r
-#define STM32_IRQ_EXTI1_PRIORITY 6\r
-#define STM32_IRQ_EXTI2_PRIORITY 6\r
-#define STM32_IRQ_EXTI3_PRIORITY 6\r
-#define STM32_IRQ_EXTI4_PRIORITY 6\r
-#define STM32_IRQ_EXTI5_9_PRIORITY 6\r
-#define STM32_IRQ_EXTI10_15_PRIORITY 6\r
-#define STM32_IRQ_EXTI1635_38_PRIORITY 6\r
-#define STM32_IRQ_EXTI18_PRIORITY 6\r
-#define STM32_IRQ_EXTI19_PRIORITY 6\r
-#define STM32_IRQ_EXTI20_PRIORITY 6\r
-#define STM32_IRQ_EXTI21_22_PRIORITY 15\r
-\r
-#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7\r
-#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7\r
-#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7\r
-#define STM32_IRQ_TIM1_CC_PRIORITY 7\r
-#define STM32_IRQ_TIM2_PRIORITY 7\r
-#define STM32_IRQ_TIM3_PRIORITY 7\r
-#define STM32_IRQ_TIM4_PRIORITY 7\r
-#define STM32_IRQ_TIM5_PRIORITY 7\r
-#define STM32_IRQ_TIM6_PRIORITY 7\r
-#define STM32_IRQ_TIM7_PRIORITY 7\r
-#define STM32_IRQ_TIM8_UP_PRIORITY 7\r
-#define STM32_IRQ_TIM8_CC_PRIORITY 7\r
-\r
-#define STM32_IRQ_USART1_PRIORITY 12\r
-#define STM32_IRQ_USART2_PRIORITY 12\r
-#define STM32_IRQ_USART3_PRIORITY 12\r
-#define STM32_IRQ_UART4_PRIORITY 12\r
-#define STM32_IRQ_UART5_PRIORITY 12\r
-#define STM32_IRQ_LPUART1_PRIORITY 12\r
-\r
-/*\r
- * ADC driver system settings.\r
- */\r
-#define STM32_ADC_DUAL_MODE FALSE\r
-#define STM32_ADC_COMPACT_SAMPLES FALSE\r
-#define STM32_ADC_USE_ADC1 TRUE\r
-#define STM32_ADC_USE_ADC2 FALSE\r
-#define STM32_ADC_USE_ADC3 TRUE\r
-#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)\r
-#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)\r
-#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)\r
-#define STM32_ADC_ADC1_DMA_PRIORITY 2\r
-#define STM32_ADC_ADC2_DMA_PRIORITY 2\r
-#define STM32_ADC_ADC3_DMA_PRIORITY 2\r
-#define STM32_ADC_ADC12_IRQ_PRIORITY 5\r
-#define STM32_ADC_ADC3_IRQ_PRIORITY 5\r
-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5\r
-#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5\r
-#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5\r
-#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_ADCCK\r
-#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV10\r
-\r
-//#define ADC123_PRESC_VALUE 1\r
-\r
-/*\r
- * CAN driver system settings.\r
- */\r
-#define STM32_CAN_USE_CAN1 FALSE\r
-#define STM32_CAN_CAN1_IRQ_PRIORITY 11\r
-\r
-/*\r
- * DAC driver system settings.\r
- */\r
-#define STM32_DAC_DUAL_MODE FALSE\r
-#define STM32_DAC_USE_DAC1_CH1 TRUE\r
-#define STM32_DAC_USE_DAC1_CH2 TRUE\r
-#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10\r
-#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10\r
-#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2\r
-#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2\r
-#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)\r
-#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)\r
-\r
-/*\r
- * GPT driver system settings.\r
- */\r
-#define STM32_GPT_USE_TIM1 FALSE\r
-#define STM32_GPT_USE_TIM2 FALSE\r
-#define STM32_GPT_USE_TIM3 FALSE\r
-#define STM32_GPT_USE_TIM4 FALSE\r
-#define STM32_GPT_USE_TIM5 FALSE\r
-#define STM32_GPT_USE_TIM6 TRUE\r
-#define STM32_GPT_USE_TIM7 TRUE\r
-#define STM32_GPT_USE_TIM8 FALSE\r
-#define STM32_GPT_USE_TIM15 FALSE\r
-#define STM32_GPT_USE_TIM16 FALSE\r
-#define STM32_GPT_USE_TIM17 FALSE\r
-\r
-/*\r
- * I2C driver system settings.\r
- */\r
-#define STM32_I2C_USE_I2C1 FALSE\r
-#define STM32_I2C_USE_I2C2 FALSE\r
-#define STM32_I2C_USE_I2C3 FALSE\r
-#define STM32_I2C_BUSY_TIMEOUT 50\r
-#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)\r
-#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)\r
-#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)\r
-#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)\r
-#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)\r
-#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)\r
-#define STM32_I2C_I2C1_IRQ_PRIORITY 5\r
-#define STM32_I2C_I2C2_IRQ_PRIORITY 5\r
-#define STM32_I2C_I2C3_IRQ_PRIORITY 5\r
-#define STM32_I2C_I2C1_DMA_PRIORITY 3\r
-#define STM32_I2C_I2C2_DMA_PRIORITY 3\r
-#define STM32_I2C_I2C3_DMA_PRIORITY 3\r
-#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")\r
-\r
-/*\r
- * ICU driver system settings.\r
- */\r
-#define STM32_ICU_USE_TIM1 FALSE\r
-#define STM32_ICU_USE_TIM2 FALSE\r
-#define STM32_ICU_USE_TIM3 FALSE\r
-#define STM32_ICU_USE_TIM4 FALSE\r
-#define STM32_ICU_USE_TIM5 FALSE\r
-#define STM32_ICU_USE_TIM8 FALSE\r
-#define STM32_ICU_USE_TIM15 FALSE\r
-#define STM32_ICU_USE_TIM16 FALSE\r
-#define STM32_ICU_USE_TIM17 FALSE\r
-\r
-/*\r
- * PWM driver system settings.\r
- */\r
-#define STM32_PWM_USE_ADVANCED FALSE\r
-#define STM32_PWM_USE_TIM1 FALSE\r
-#define STM32_PWM_USE_TIM2 FALSE\r
-#define STM32_PWM_USE_TIM3 FALSE\r
-#define STM32_PWM_USE_TIM4 FALSE\r
-#define STM32_PWM_USE_TIM5 FALSE\r
-#define STM32_PWM_USE_TIM8 FALSE\r
-#define STM32_PWM_USE_TIM15 FALSE\r
-#define STM32_PWM_USE_TIM16 FALSE\r
-#define STM32_PWM_USE_TIM17 FALSE\r
-\r
-/*\r
- * RTC driver system settings.\r
- */\r
-#define STM32_RTC_PRESA_VALUE 32\r
-#define STM32_RTC_PRESS_VALUE 1024\r
-#define STM32_RTC_CR_INIT 0\r
-#define STM32_RTC_TAMPCR_INIT 0\r
-\r
-/*\r
- * SDC driver system settings.\r
- */\r
-#define STM32_SDC_USE_SDMMC1 FALSE\r
-#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE\r
-#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000\r
-#define STM32_SDC_SDMMC_READ_TIMEOUT 1000\r
-#define STM32_SDC_SDMMC_CLOCK_DELAY 10\r
-#define STM32_SDC_SDMMC1_DMA_PRIORITY 3\r
-#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9\r
-#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)\r
-\r
-/*\r
- * SERIAL driver system settings.\r
- */\r
-#define STM32_SERIAL_USE_USART1 FALSE\r
-#define STM32_SERIAL_USE_USART2 TRUE\r
-#define STM32_SERIAL_USE_USART3 FALSE\r
-#define STM32_SERIAL_USE_UART4 FALSE\r
-#define STM32_SERIAL_USE_UART5 FALSE\r
-#define STM32_SERIAL_USE_LPUART1 FALSE\r
-#define STM32_SERIAL_USART1_PRIORITY 12\r
-#define STM32_SERIAL_USART2_PRIORITY 12\r
-#define STM32_SERIAL_USART3_PRIORITY 12\r
-#define STM32_SERIAL_UART4_PRIORITY 12\r
-#define STM32_SERIAL_UART5_PRIORITY 12\r
-#define STM32_SERIAL_LPUART1_PRIORITY 12\r
-\r
-/*\r
- * SPI driver system settings.\r
- */\r
-#define STM32_SPI_USE_SPI1 FALSE\r
-#define STM32_SPI_USE_SPI2 FALSE\r
-#define STM32_SPI_USE_SPI3 FALSE\r
-#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)\r
-#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)\r
-#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)\r
-#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)\r
-#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)\r
-#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)\r
-#define STM32_SPI_SPI1_DMA_PRIORITY 1\r
-#define STM32_SPI_SPI2_DMA_PRIORITY 1\r
-#define STM32_SPI_SPI3_DMA_PRIORITY 1\r
-#define STM32_SPI_SPI1_IRQ_PRIORITY 10\r
-#define STM32_SPI_SPI2_IRQ_PRIORITY 10\r
-#define STM32_SPI_SPI3_IRQ_PRIORITY 10\r
-#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")\r
-\r
-/*\r
- * ST driver system settings.\r
- */\r
-#define STM32_ST_IRQ_PRIORITY 8\r
-#define STM32_ST_USE_TIMER 2\r
-\r
-/*\r
- * TRNG driver system settings.\r
- */\r
-#define STM32_TRNG_USE_RNG1 FALSE\r
-\r
-/*\r
- * UART driver system settings.\r
- */\r
-#define STM32_UART_USE_USART1 FALSE\r
-#define STM32_UART_USE_USART2 FALSE\r
-#define STM32_UART_USE_USART3 FALSE\r
-#define STM32_UART_USE_UART4 FALSE\r
-#define STM32_UART_USE_UART5 FALSE\r
-#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)\r
-#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)\r
-#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)\r
-#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)\r
-#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)\r
-#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)\r
-#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)\r
-#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)\r
-#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)\r
-#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)\r
-#define STM32_UART_USART1_IRQ_PRIORITY 12\r
-#define STM32_UART_USART2_IRQ_PRIORITY 12\r
-#define STM32_UART_USART3_IRQ_PRIORITY 12\r
-#define STM32_UART_UART4_IRQ_PRIORITY 12\r
-#define STM32_UART_UART5_IRQ_PRIORITY 12\r
-#define STM32_UART_USART1_DMA_PRIORITY 0\r
-#define STM32_UART_USART2_DMA_PRIORITY 0\r
-#define STM32_UART_USART3_DMA_PRIORITY 0\r
-#define STM32_UART_UART4_DMA_PRIORITY 0\r
-#define STM32_UART_UART5_DMA_PRIORITY 0\r
-#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")\r
-\r
-/*\r
- * USB driver system settings.\r
- */\r
-#ifdef STM32L476_MCUCONF\r
-#define STM32_USB_USE_OTG1 TRUE\r
-#define STM32_USB_OTG1_IRQ_PRIORITY 14\r
-#define STM32_USB_OTG1_RX_FIFO_SIZE 512\r
-#else\r
-#define STM32_USB_USE_USB1 TRUE\r
-#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE\r
-#define STM32_USB_USB1_HP_IRQ_PRIORITY 13\r
-#define STM32_USB_USB1_LP_IRQ_PRIORITY 14\r
-#endif // STM32L476_MCUCONF\r
-\r
-/*\r
- * WDG driver system settings.\r
- */\r
-#define STM32_WDG_USE_IWDG FALSE\r
-\r
-/*\r
- * WSPI driver system settings.\r
- */\r
-#define STM32_WSPI_USE_QUADSPI1 FALSE\r
-#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)\r
-\r
-#endif /* MCUCONF_H */\r
--- /dev/null
+# List of all the board related files.\r
+ifeq ($(TARGET_PLATFORM),H7)\r
+ BOARDSRC = ./source/board/board_h7.c\r
+else\r
+ BOARDSRC = ./source/board/board_l4.c\r
+endif\r
+\r
+# Required include directories\r
+ifeq ($(TARGET_PLATFORM),H7)\r
+ BOARDINC = ./source/board/h7\r
+else\r
+ BOARDINC = ./source/board/l4\r
+endif\r
+\r
+# Shared variables\r
+ALLCSRC += $(BOARDSRC)\r
+ALLINC += $(BOARDINC)\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/*\r
+ * This file has been automatically generated using ChibiStudio board\r
+ * generator plugin. Do not edit manually.\r
+ */\r
+\r
+#include "hal.h"\r
+#include "stm32_gpio.h"\r
+\r
+/*===========================================================================*/\r
+/* Driver local definitions. */\r
+/*===========================================================================*/\r
+\r
+/*===========================================================================*/\r
+/* Driver exported variables. */\r
+/*===========================================================================*/\r
+\r
+/*===========================================================================*/\r
+/* Driver local variables and types. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Type of STM32 GPIO port setup.\r
+ */\r
+typedef struct {\r
+ uint32_t moder;\r
+ uint32_t otyper;\r
+ uint32_t ospeedr;\r
+ uint32_t pupdr;\r
+ uint32_t odr;\r
+ uint32_t afrl;\r
+ uint32_t afrh;\r
+} gpio_setup_t;\r
+\r
+/**\r
+ * @brief Type of STM32 GPIO initialization data.\r
+ */\r
+typedef struct {\r
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)\r
+ gpio_setup_t PAData;\r
+#endif\r
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)\r
+ gpio_setup_t PBData;\r
+#endif\r
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)\r
+ gpio_setup_t PCData;\r
+#endif\r
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)\r
+ gpio_setup_t PDData;\r
+#endif\r
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)\r
+ gpio_setup_t PEData;\r
+#endif\r
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)\r
+ gpio_setup_t PFData;\r
+#endif\r
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)\r
+ gpio_setup_t PGData;\r
+#endif\r
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)\r
+ gpio_setup_t PHData;\r
+#endif\r
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)\r
+ gpio_setup_t PIData;\r
+#endif\r
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)\r
+ gpio_setup_t PJData;\r
+#endif\r
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)\r
+ gpio_setup_t PKData;\r
+#endif\r
+} gpio_config_t;\r
+\r
+/**\r
+ * @brief STM32 GPIO static initialization data.\r
+ */\r
+static const gpio_config_t gpio_default_config = {\r
+#if STM32_HAS_GPIOA\r
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,\r
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},\r
+#endif\r
+#if STM32_HAS_GPIOB\r
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,\r
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},\r
+#endif\r
+#if STM32_HAS_GPIOC\r
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,\r
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},\r
+#endif\r
+#if STM32_HAS_GPIOD\r
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,\r
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},\r
+#endif\r
+#if STM32_HAS_GPIOE\r
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,\r
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},\r
+#endif\r
+#if STM32_HAS_GPIOF\r
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,\r
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},\r
+#endif\r
+#if STM32_HAS_GPIOG\r
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,\r
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},\r
+#endif\r
+#if STM32_HAS_GPIOH\r
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,\r
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},\r
+#endif\r
+#if STM32_HAS_GPIOI\r
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,\r
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},\r
+#endif\r
+#if STM32_HAS_GPIOJ\r
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,\r
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},\r
+#endif\r
+#if STM32_HAS_GPIOK\r
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,\r
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}\r
+#endif\r
+};\r
+\r
+/*===========================================================================*/\r
+/* Driver local functions. */\r
+/*===========================================================================*/\r
+\r
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {\r
+\r
+ gpiop->OTYPER = config->otyper;\r
+ gpiop->OSPEEDR = config->ospeedr;\r
+ gpiop->PUPDR = config->pupdr;\r
+ gpiop->ODR = config->odr;\r
+ gpiop->AFRL = config->afrl;\r
+ gpiop->AFRH = config->afrh;\r
+ gpiop->MODER = config->moder;\r
+}\r
+\r
+static void stm32_gpio_init(void) {\r
+\r
+ /* Enabling GPIO-related clocks, the mask comes from the\r
+ registry header file.*/\r
+ rccResetAHB4(STM32_GPIO_EN_MASK);\r
+ rccEnableAHB4(STM32_GPIO_EN_MASK, true);\r
+\r
+ /* Initializing all the defined GPIO ports.*/\r
+#if STM32_HAS_GPIOA\r
+ gpio_init(GPIOA, &gpio_default_config.PAData);\r
+#endif\r
+#if STM32_HAS_GPIOB\r
+ gpio_init(GPIOB, &gpio_default_config.PBData);\r
+#endif\r
+#if STM32_HAS_GPIOC\r
+ gpio_init(GPIOC, &gpio_default_config.PCData);\r
+#endif\r
+#if STM32_HAS_GPIOD\r
+ gpio_init(GPIOD, &gpio_default_config.PDData);\r
+#endif\r
+#if STM32_HAS_GPIOE\r
+ gpio_init(GPIOE, &gpio_default_config.PEData);\r
+#endif\r
+#if STM32_HAS_GPIOF\r
+ gpio_init(GPIOF, &gpio_default_config.PFData);\r
+#endif\r
+#if STM32_HAS_GPIOG\r
+ gpio_init(GPIOG, &gpio_default_config.PGData);\r
+#endif\r
+#if STM32_HAS_GPIOH\r
+ gpio_init(GPIOH, &gpio_default_config.PHData);\r
+#endif\r
+#if STM32_HAS_GPIOI\r
+ gpio_init(GPIOI, &gpio_default_config.PIData);\r
+#endif\r
+#if STM32_HAS_GPIOJ\r
+ gpio_init(GPIOJ, &gpio_default_config.PJData);\r
+#endif\r
+#if STM32_HAS_GPIOK\r
+ gpio_init(GPIOK, &gpio_default_config.PKData);\r
+#endif\r
+}\r
+\r
+/*===========================================================================*/\r
+/* Driver interrupt handlers. */\r
+/*===========================================================================*/\r
+\r
+/*===========================================================================*/\r
+/* Driver exported functions. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Early initialization code.\r
+ * @details GPIO ports and system clocks are initialized before everything\r
+ * else.\r
+ */\r
+void __early_init(void) {\r
+\r
+ stm32_gpio_init();\r
+ stm32_clock_init();\r
+}\r
+\r
+#if HAL_USE_SDC || defined(__DOXYGEN__)\r
+/**\r
+ * @brief SDC card detection.\r
+ */\r
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {\r
+\r
+ (void)sdcp;\r
+ /* CHTODO: Fill the implementation.*/\r
+ return true;\r
+}\r
+\r
+/**\r
+ * @brief SDC card write protection detection.\r
+ */\r
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {\r
+\r
+ (void)sdcp;\r
+ /* CHTODO: Fill the implementation.*/\r
+ return false;\r
+}\r
+#endif /* HAL_USE_SDC */\r
+\r
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)\r
+/**\r
+ * @brief MMC_SPI card detection.\r
+ */\r
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {\r
+\r
+ (void)mmcp;\r
+ /* CHTODO: Fill the implementation.*/\r
+ return true;\r
+}\r
+\r
+/**\r
+ * @brief MMC_SPI card write protection detection.\r
+ */\r
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {\r
+\r
+ (void)mmcp;\r
+ /* CHTODO: Fill the implementation.*/\r
+ return false;\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Board-specific initialization code.\r
+ * @note You can add your board-specific code here.\r
+ */\r
+void boardInit(void) {\r
+\r
+}\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/*\r
+ * This file has been automatically generated using ChibiStudio board\r
+ * generator plugin. Do not edit manually.\r
+ */\r
+\r
+#include "hal.h"\r
+#include "stm32_gpio.h"\r
+\r
+/*===========================================================================*/\r
+/* Driver local definitions. */\r
+/*===========================================================================*/\r
+\r
+/*===========================================================================*/\r
+/* Driver exported variables. */\r
+/*===========================================================================*/\r
+\r
+/*===========================================================================*/\r
+/* Driver local variables and types. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Type of STM32 GPIO port setup.\r
+ */\r
+typedef struct {\r
+ uint32_t moder;\r
+ uint32_t otyper;\r
+ uint32_t ospeedr;\r
+ uint32_t pupdr;\r
+ uint32_t odr;\r
+ uint32_t afrl;\r
+ uint32_t afrh;\r
+ uint32_t ascr;\r
+ uint32_t lockr;\r
+} gpio_setup_t;\r
+\r
+/**\r
+ * @brief Type of STM32 GPIO initialization data.\r
+ */\r
+typedef struct {\r
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)\r
+ gpio_setup_t PAData;\r
+#endif\r
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)\r
+ gpio_setup_t PBData;\r
+#endif\r
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)\r
+ gpio_setup_t PCData;\r
+#endif\r
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)\r
+ gpio_setup_t PDData;\r
+#endif\r
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)\r
+ gpio_setup_t PEData;\r
+#endif\r
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)\r
+ gpio_setup_t PFData;\r
+#endif\r
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)\r
+ gpio_setup_t PGData;\r
+#endif\r
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)\r
+ gpio_setup_t PHData;\r
+#endif\r
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)\r
+ gpio_setup_t PIData;\r
+#endif\r
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)\r
+ gpio_setup_t PJData;\r
+#endif\r
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)\r
+ gpio_setup_t PKData;\r
+#endif\r
+} gpio_config_t;\r
+\r
+/**\r
+ * @brief STM32 GPIO static initialization data.\r
+ */\r
+static const gpio_config_t gpio_default_config = {\r
+#if STM32_HAS_GPIOA\r
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,\r
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR,\r
+ VAL_GPIOA_LOCKR},\r
+#endif\r
+#if STM32_HAS_GPIOB\r
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,\r
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR,\r
+ VAL_GPIOB_LOCKR},\r
+#endif\r
+#if STM32_HAS_GPIOC\r
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,\r
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR,\r
+ VAL_GPIOC_LOCKR},\r
+#endif\r
+#if STM32_HAS_GPIOD\r
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,\r
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR,\r
+ VAL_GPIOD_LOCKR},\r
+#endif\r
+#if STM32_HAS_GPIOE\r
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,\r
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR,\r
+ VAL_GPIOE_LOCKR},\r
+#endif\r
+#if STM32_HAS_GPIOF\r
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,\r
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR,\r
+ VAL_GPIOF_LOCKR},\r
+#endif\r
+#if STM32_HAS_GPIOG\r
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,\r
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR,\r
+ VAL_GPIOG_LOCKR},\r
+#endif\r
+#if STM32_HAS_GPIOH\r
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,\r
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR,\r
+ VAL_GPIOH_LOCKR},\r
+#endif\r
+#if STM32_HAS_GPIOI\r
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,\r
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR,\r
+ VAL_GPIOI_LOCKR},\r
+#endif\r
+#if STM32_HAS_GPIOJ\r
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,\r
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR,\r
+ VAL_GPIOJ_LOCKR},\r
+#endif\r
+#if STM32_HAS_GPIOK\r
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,\r
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR,\r
+ VAL_GPIOK_LOCKR}\r
+#endif\r
+};\r
+\r
+/*===========================================================================*/\r
+/* Driver local functions. */\r
+/*===========================================================================*/\r
+\r
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {\r
+\r
+ gpiop->OTYPER = config->otyper;\r
+ gpiop->ASCR = config->ascr;\r
+ gpiop->OSPEEDR = config->ospeedr;\r
+ gpiop->PUPDR = config->pupdr;\r
+ gpiop->ODR = config->odr;\r
+ gpiop->AFRL = config->afrl;\r
+ gpiop->AFRH = config->afrh;\r
+ gpiop->MODER = config->moder;\r
+ gpiop->LOCKR = config->lockr;\r
+}\r
+\r
+static void stm32_gpio_init(void) {\r
+\r
+ /* Enabling GPIO-related clocks, the mask comes from the\r
+ registry header file.*/\r
+ rccResetAHB2(STM32_GPIO_EN_MASK);\r
+ rccEnableAHB2(STM32_GPIO_EN_MASK, true);\r
+\r
+ /* Initializing all the defined GPIO ports.*/\r
+#if STM32_HAS_GPIOA\r
+ gpio_init(GPIOA, &gpio_default_config.PAData);\r
+#endif\r
+#if STM32_HAS_GPIOB\r
+ gpio_init(GPIOB, &gpio_default_config.PBData);\r
+#endif\r
+#if STM32_HAS_GPIOC\r
+ gpio_init(GPIOC, &gpio_default_config.PCData);\r
+#endif\r
+#if STM32_HAS_GPIOD\r
+ gpio_init(GPIOD, &gpio_default_config.PDData);\r
+#endif\r
+#if STM32_HAS_GPIOE\r
+ gpio_init(GPIOE, &gpio_default_config.PEData);\r
+#endif\r
+#if STM32_HAS_GPIOF\r
+ gpio_init(GPIOF, &gpio_default_config.PFData);\r
+#endif\r
+#if STM32_HAS_GPIOG\r
+ gpio_init(GPIOG, &gpio_default_config.PGData);\r
+#endif\r
+#if STM32_HAS_GPIOH\r
+ gpio_init(GPIOH, &gpio_default_config.PHData);\r
+#endif\r
+#if STM32_HAS_GPIOI\r
+ gpio_init(GPIOI, &gpio_default_config.PIData);\r
+#endif\r
+#if STM32_HAS_GPIOJ\r
+ gpio_init(GPIOJ, &gpio_default_config.PJData);\r
+#endif\r
+#if STM32_HAS_GPIOK\r
+ gpio_init(GPIOK, &gpio_default_config.PKData);\r
+#endif\r
+}\r
+\r
+/*===========================================================================*/\r
+/* Driver interrupt handlers. */\r
+/*===========================================================================*/\r
+\r
+/*===========================================================================*/\r
+/* Driver exported functions. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Early initialization code.\r
+ * @details GPIO ports and system clocks are initialized before everything\r
+ * else.\r
+ */\r
+void __early_init(void) {\r
+\r
+ stm32_gpio_init();\r
+ stm32_clock_init();\r
+}\r
+\r
+#if HAL_USE_SDC || defined(__DOXYGEN__)\r
+/**\r
+ * @brief SDC card detection.\r
+ */\r
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {\r
+\r
+ (void)sdcp;\r
+ /* CHTODO: Fill the implementation.*/\r
+ return true;\r
+}\r
+\r
+/**\r
+ * @brief SDC card write protection detection.\r
+ */\r
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {\r
+\r
+ (void)sdcp;\r
+ /* CHTODO: Fill the implementation.*/\r
+ return false;\r
+}\r
+#endif /* HAL_USE_SDC */\r
+\r
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)\r
+/**\r
+ * @brief MMC_SPI card detection.\r
+ */\r
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {\r
+\r
+ (void)mmcp;\r
+ /* CHTODO: Fill the implementation.*/\r
+ return true;\r
+}\r
+\r
+/**\r
+ * @brief MMC_SPI card write protection detection.\r
+ */\r
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {\r
+\r
+ (void)mmcp;\r
+ /* CHTODO: Fill the implementation.*/\r
+ return false;\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Board-specific initialization code.\r
+ * @note You can add your board-specific code here.\r
+ */\r
+void boardInit(void) {\r
+\r
+}\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/*\r
+ * This file has been automatically generated using ChibiStudio board\r
+ * generator plugin. Do not edit manually.\r
+ */\r
+\r
+#ifndef BOARD_H\r
+#define BOARD_H\r
+\r
+/*===========================================================================*/\r
+/* Driver constants. */\r
+/*===========================================================================*/\r
+\r
+/*\r
+ * Setup for STMicroelectronics STM32 Nucleo144-H743ZI board.\r
+ */\r
+\r
+/*\r
+ * Board identifier.\r
+ */\r
+#define BOARD_ST_NUCLEO144_H743ZI\r
+#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-H743ZI"\r
+\r
+/*\r
+ * Ethernet PHY type.\r
+ */\r
+#define BOARD_PHY_ID MII_LAN8742A_ID\r
+#define BOARD_PHY_RMII\r
+\r
+/*\r
+ * Board oscillators-related settings.\r
+ */\r
+#if !defined(STM32_LSECLK)\r
+#define STM32_LSECLK 32768U\r
+#endif\r
+\r
+#define STM32_LSEDRV (3U << 3U)\r
+\r
+#if !defined(STM32_HSECLK)\r
+#define STM32_HSECLK 8000000U\r
+#endif\r
+\r
+#define STM32_HSE_BYPASS\r
+\r
+/*\r
+ * MCU type as defined in the ST header.\r
+ */\r
+#define STM32H723xx\r
+\r
+/*\r
+ * IO pins assignments.\r
+ */\r
+#define GPIOA_PIN0 0U\r
+#define GPIOA_RMII_REF_CLK 1U\r
+#define GPIOA_RMII_MDIO 2U\r
+#define GPIOA_PIN3 3U\r
+#define GPIOA_PIN4 4U\r
+#define GPIOA_PIN5 5U\r
+#define GPIOA_PIN6 6U\r
+#define GPIOA_RMII_CRS_DV 7U\r
+#define GPIOA_USB_SOF 8U\r
+#define GPIOA_MCO1 8U\r
+#define GPIOA_USB_VBUS 9U\r
+#define GPIOA_USB_ID 10U\r
+#define GPIOA_USB_DM 11U\r
+#define GPIOA_USB_DP 12U\r
+#define GPIOA_SWDIO 13U\r
+#define GPIOA_SWCLK 14U\r
+#define GPIOA_T_JTDI 15U\r
+\r
+#define GPIOB_LED1 0U\r
+#define GPIOB_LED_GREEN 0U\r
+#define GPIOB_LED 0U\r
+#define GPIOB_PIN1 1U\r
+#define GPIOB_PIN2 2U\r
+#define GPIOB_SWO 3U\r
+#define GPIOB_PIN4 4U\r
+#define GPIOB_PIN5 5U\r
+#define GPIOB_PIN6 6U\r
+#define GPIOB_PIN7 7U\r
+#define GPIOB_PIN8 8U\r
+#define GPIOB_PIN9 9U\r
+#define GPIOB_PIN10 10U\r
+#define GPIOB_PIN11 11U\r
+#define GPIOB_PIN12 12U\r
+#define GPIOB_RMII_TXD1 13U\r
+#define GPIOB_LED3 14U\r
+#define GPIOB_LED_RED 14U\r
+#define GPIOB_PIN15 15U\r
+\r
+#define GPIOC_PIN0 0U\r
+#define GPIOC_RMII_MDC 1U\r
+#define GPIOC_PIN2 2U\r
+#define GPIOC_PIN3 3U\r
+#define GPIOC_RMII_RXD0 4U\r
+#define GPIOC_RMII_RXD1 5U\r
+#define GPIOC_PIN6 6U\r
+#define GPIOC_PIN7 7U\r
+#define GPIOC_PIN8 8U\r
+#define GPIOC_PIN9 9U\r
+#define GPIOC_PIN10 10U\r
+#define GPIOC_PIN11 11U\r
+#define GPIOC_PIN12 12U\r
+#define GPIOC_BUTTON 13U\r
+#define GPIOC_OSC32_IN 14U\r
+#define GPIOC_OSC32_OUT 15U\r
+\r
+#define GPIOD_PIN0 0U\r
+#define GPIOD_PIN1 1U\r
+#define GPIOD_PIN2 2U\r
+#define GPIOD_PIN3 3U\r
+#define GPIOD_PIN4 4U\r
+#define GPIOD_PIN5 5U\r
+#define GPIOD_PIN6 6U\r
+#define GPIOD_PIN7 7U\r
+#define GPIOD_USART3_RX 8U\r
+#define GPIOD_STLK_RX 8U\r
+#define GPIOD_USART3_TX 9U\r
+#define GPIOD_STLK_TX 9U\r
+#define GPIOD_PIN10 10U\r
+#define GPIOD_PIN11 11U\r
+#define GPIOD_PIN12 12U\r
+#define GPIOD_PIN13 13U\r
+#define GPIOD_PIN14 14U\r
+#define GPIOD_PIN15 15U\r
+\r
+#define GPIOE_PIN0 0U\r
+#define GPIOE_LED2 1U\r
+#define GPIOE_LED_YELLOW 1U\r
+#define GPIOE_PIN2 2U\r
+#define GPIOE_PIN3 3U\r
+#define GPIOE_PIN4 4U\r
+#define GPIOE_PIN5 5U\r
+#define GPIOE_PIN6 6U\r
+#define GPIOE_PIN7 7U\r
+#define GPIOE_PIN8 8U\r
+#define GPIOE_PIN9 9U\r
+#define GPIOE_PIN10 10U\r
+#define GPIOE_PIN11 11U\r
+#define GPIOE_PIN12 12U\r
+#define GPIOE_PIN13 13U\r
+#define GPIOE_PIN14 14U\r
+#define GPIOE_PIN15 15U\r
+\r
+#define GPIOF_PIN0 0U\r
+#define GPIOF_PIN1 1U\r
+#define GPIOF_PIN2 2U\r
+#define GPIOF_PIN3 3U\r
+#define GPIOF_PIN4 4U\r
+#define GPIOF_PIN5 5U\r
+#define GPIOF_PIN6 6U\r
+#define GPIOF_PIN7 7U\r
+#define GPIOF_PIN8 8U\r
+#define GPIOF_PIN9 9U\r
+#define GPIOF_PIN10 10U\r
+#define GPIOF_PIN11 11U\r
+#define GPIOF_PIN12 12U\r
+#define GPIOF_PIN13 13U\r
+#define GPIOF_PIN14 14U\r
+#define GPIOF_PIN15 15U\r
+\r
+#define GPIOG_PIN0 0U\r
+#define GPIOG_PIN1 1U\r
+#define GPIOG_PIN2 2U\r
+#define GPIOG_PIN3 3U\r
+#define GPIOG_PIN4 4U\r
+#define GPIOG_PIN5 5U\r
+#define GPIOG_USB_FS_PWR_EN 6U\r
+#define GPIOG_USB_FS_OVCR 7U\r
+#define GPIOG_PIN8 8U\r
+#define GPIOG_PIN9 9U\r
+#define GPIOG_PIN10 10U\r
+#define GPIOG_RMII_TX_EN 11U\r
+#define GPIOG_PIN12 12U\r
+#define GPIOG_RMII_TXD0 13U\r
+#define GPIOG_PIN14 14U\r
+#define GPIOG_PIN15 15U\r
+\r
+#define GPIOH_OSC_IN 0U\r
+#define GPIOH_OSC_OUT 1U\r
+#define GPIOH_PIN2 2U\r
+#define GPIOH_PIN3 3U\r
+#define GPIOH_PIN4 4U\r
+#define GPIOH_PIN5 5U\r
+#define GPIOH_PIN6 6U\r
+#define GPIOH_PIN7 7U\r
+#define GPIOH_PIN8 8U\r
+#define GPIOH_PIN9 9U\r
+#define GPIOH_PIN10 10U\r
+#define GPIOH_PIN11 11U\r
+#define GPIOH_PIN12 12U\r
+#define GPIOH_PIN13 13U\r
+#define GPIOH_PIN14 14U\r
+#define GPIOH_PIN15 15U\r
+\r
+#define GPIOI_PIN0 0U\r
+#define GPIOI_PIN1 1U\r
+#define GPIOI_PIN2 2U\r
+#define GPIOI_PIN3 3U\r
+#define GPIOI_PIN4 4U\r
+#define GPIOI_PIN5 5U\r
+#define GPIOI_PIN6 6U\r
+#define GPIOI_PIN7 7U\r
+#define GPIOI_PIN8 8U\r
+#define GPIOI_PIN9 9U\r
+#define GPIOI_PIN10 10U\r
+#define GPIOI_PIN11 11U\r
+#define GPIOI_PIN12 12U\r
+#define GPIOI_PIN13 13U\r
+#define GPIOI_PIN14 14U\r
+#define GPIOI_PIN15 15U\r
+\r
+#define GPIOJ_PIN0 0U\r
+#define GPIOJ_PIN1 1U\r
+#define GPIOJ_PIN2 2U\r
+#define GPIOJ_PIN3 3U\r
+#define GPIOJ_PIN4 4U\r
+#define GPIOJ_PIN5 5U\r
+#define GPIOJ_PIN6 6U\r
+#define GPIOJ_PIN7 7U\r
+#define GPIOJ_PIN8 8U\r
+#define GPIOJ_PIN9 9U\r
+#define GPIOJ_PIN10 10U\r
+#define GPIOJ_PIN11 11U\r
+#define GPIOJ_PIN12 12U\r
+#define GPIOJ_PIN13 13U\r
+#define GPIOJ_PIN14 14U\r
+#define GPIOJ_PIN15 15U\r
+\r
+#define GPIOK_PIN0 0U\r
+#define GPIOK_PIN1 1U\r
+#define GPIOK_PIN2 2U\r
+#define GPIOK_PIN3 3U\r
+#define GPIOK_PIN4 4U\r
+#define GPIOK_PIN5 5U\r
+#define GPIOK_PIN6 6U\r
+#define GPIOK_PIN7 7U\r
+#define GPIOK_PIN8 8U\r
+#define GPIOK_PIN9 9U\r
+#define GPIOK_PIN10 10U\r
+#define GPIOK_PIN11 11U\r
+#define GPIOK_PIN12 12U\r
+#define GPIOK_PIN13 13U\r
+#define GPIOK_PIN14 14U\r
+#define GPIOK_PIN15 15U\r
+\r
+/*\r
+ * IO lines assignments.\r
+ */\r
+#define LINE_RMII_REF_CLK PAL_LINE(GPIOA, 1U)\r
+#define LINE_RMII_MDIO PAL_LINE(GPIOA, 2U)\r
+#define LINE_RMII_CRS_DV PAL_LINE(GPIOA, 7U)\r
+#define LINE_USB_SOF PAL_LINE(GPIOA, 8U)\r
+#define LINE_MCO1 PAL_LINE(GPIOA, 8U)\r
+#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U)\r
+#define LINE_USB_ID PAL_LINE(GPIOA, 10U)\r
+#define LINE_USB_DM PAL_LINE(GPIOA, 11U)\r
+#define LINE_USB_DP PAL_LINE(GPIOA, 12U)\r
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)\r
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)\r
+#define LINE_T_JTDI PAL_LINE(GPIOA, 15U)\r
+#define LINE_LED1 PAL_LINE(GPIOB, 0U)\r
+#define LINE_LED_GREEN PAL_LINE(GPIOB, 0U)\r
+#define LINE_LED PAL_LINE(GPIOB, 0U)\r
+#define LINE_SWO PAL_LINE(GPIOB, 3U)\r
+#define LINE_LED2 PAL_LINE(GPIOE, 1U)\r
+#define LINE_LED_YELLOW PAL_LINE(GPIOE, 1U)\r
+#define LINE_RMII_TXD1 PAL_LINE(GPIOB, 13U)\r
+#define LINE_LED3 PAL_LINE(GPIOB, 14U)\r
+#define LINE_LED_RED PAL_LINE(GPIOB, 14U)\r
+#define LINE_RMII_MDC PAL_LINE(GPIOC, 1U)\r
+#define LINE_RMII_RXD0 PAL_LINE(GPIOC, 4U)\r
+#define LINE_RMII_RXD1 PAL_LINE(GPIOC, 5U)\r
+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)\r
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)\r
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)\r
+#define LINE_USART3_RX PAL_LINE(GPIOD, 8U)\r
+#define LINE_STLK_RX PAL_LINE(GPIOD, 8U)\r
+#define LINE_USART3_TX PAL_LINE(GPIOD, 9U)\r
+#define LINE_STLK_TX PAL_LINE(GPIOD, 9U)\r
+#define LINE_USB_FS_PWR_EN PAL_LINE(GPIOG, 6U)\r
+#define LINE_USB_FS_OVCR PAL_LINE(GPIOG, 7U)\r
+#define LINE_RMII_TX_EN PAL_LINE(GPIOG, 11U)\r
+#define LINE_RMII_TXD0 PAL_LINE(GPIOG, 13U)\r
+#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)\r
+#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)\r
+\r
+/*===========================================================================*/\r
+/* Driver pre-compile time settings. */\r
+/*===========================================================================*/\r
+\r
+/*===========================================================================*/\r
+/* Derived constants and error checks. */\r
+/*===========================================================================*/\r
+\r
+/*===========================================================================*/\r
+/* Driver data structures and types. */\r
+/*===========================================================================*/\r
+\r
+/*===========================================================================*/\r
+/* Driver macros. */\r
+/*===========================================================================*/\r
+\r
+/*\r
+ * I/O ports initial setup, this configuration is established soon after reset\r
+ * in the initialization code.\r
+ * Please refer to the STM32 Reference Manual for details.\r
+ */\r
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))\r
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))\r
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))\r
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))\r
+#define PIN_ODR_LOW(n) (0U << (n))\r
+#define PIN_ODR_HIGH(n) (1U << (n))\r
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))\r
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))\r
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))\r
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))\r
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))\r
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))\r
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))\r
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))\r
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))\r
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))\r
+\r
+/*\r
+ * GPIOA setup:\r
+ *\r
+ * PA0 - PIN0 (input pullup).\r
+ * PA1 - RMII_REF_CLK (alternate 11).\r
+ * PA2 - RMII_MDIO (alternate 11).\r
+ * PA3 - PIN3 (input pullup).\r
+ * PA4 - PIN4 (input pullup).\r
+ * PA5 - PIN5 (input pullup).\r
+ * PA6 - PIN6 (input pullup).\r
+ * PA7 - RMII_CRS_DV (alternate 11).\r
+ * PA8 - USB_SOF MCO1 (alternate 10).\r
+ * PA9 - USB_VBUS (analog).\r
+ * PA10 - USB_ID (alternate 10).\r
+ * PA11 - USB_DM (alternate 10).\r
+ * PA12 - USB_DP (alternate 10).\r
+ * PA13 - SWDIO (alternate 0).\r
+ * PA14 - SWCLK (alternate 0).\r
+ * PA15 - T_JTDI (alternate 0).\r
+ */\r
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \\r
+ PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\\r
+ PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \\r
+ PIN_MODE_INPUT(GPIOA_PIN3) | \\r
+ PIN_MODE_INPUT(GPIOA_PIN4) | \\r
+ PIN_MODE_INPUT(GPIOA_PIN5) | \\r
+ PIN_MODE_INPUT(GPIOA_PIN6) | \\r
+ PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) |\\r
+ PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \\r
+ PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \\r
+ PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \\r
+ PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \\r
+ PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \\r
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \\r
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \\r
+ PIN_MODE_ALTERNATE(GPIOA_T_JTDI))\r
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\\r
+ PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) |\\r
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_T_JTDI))\r
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \\r
+ PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \\r
+ PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \\r
+ PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \\r
+ PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \\r
+ PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \\r
+ PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \\r
+ PIN_OSPEED_HIGH(GPIOA_RMII_CRS_DV) | \\r
+ PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \\r
+ PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \\r
+ PIN_OSPEED_HIGH(GPIOA_USB_ID) | \\r
+ PIN_OSPEED_HIGH(GPIOA_USB_DM) | \\r
+ PIN_OSPEED_HIGH(GPIOA_USB_DP) | \\r
+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \\r
+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \\r
+ PIN_OSPEED_HIGH(GPIOA_T_JTDI))\r
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\\r
+ PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) | \\r
+ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \\r
+ PIN_PUPDR_PULLUP(GPIOA_PIN4) | \\r
+ PIN_PUPDR_PULLUP(GPIOA_PIN5) | \\r
+ PIN_PUPDR_PULLUP(GPIOA_PIN6) | \\r
+ PIN_PUPDR_PULLUP(GPIOA_RMII_CRS_DV) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \\r
+ PIN_PUPDR_PULLUP(GPIOA_T_JTDI))\r
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \\r
+ PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \\r
+ PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \\r
+ PIN_ODR_HIGH(GPIOA_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOA_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOA_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOA_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) | \\r
+ PIN_ODR_HIGH(GPIOA_USB_SOF) | \\r
+ PIN_ODR_HIGH(GPIOA_USB_VBUS) | \\r
+ PIN_ODR_HIGH(GPIOA_USB_ID) | \\r
+ PIN_ODR_HIGH(GPIOA_USB_DM) | \\r
+ PIN_ODR_HIGH(GPIOA_USB_DP) | \\r
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \\r
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \\r
+ PIN_ODR_HIGH(GPIOA_T_JTDI))\r
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \\r
+ PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) | \\r
+ PIN_AFIO_AF(GPIOA_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11U))\r
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \\r
+ PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \\r
+ PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \\r
+ PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \\r
+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_T_JTDI, 0U))\r
+\r
+/*\r
+ * GPIOB setup:\r
+ *\r
+ * PB0 - LED1 LED_GREEN LED (output pushpull maximum).\r
+ * PB1 - PIN1 (input pullup).\r
+ * PB2 - PIN2 (input pullup).\r
+ * PB3 - SWO (alternate 0).\r
+ * PB4 - PIN4 (input pullup).\r
+ * PB5 - PIN5 (input pullup).\r
+ * PB6 - PIN6 (input pullup).\r
+ * PB7 - PIN7 (input pullup).\r
+ * PB8 - PIN8 (input pullup).\r
+ * PB9 - PIN9 (input pullup).\r
+ * PB10 - PIN10 (input pullup).\r
+ * PB11 - PIN11 (input pullup).\r
+ * PB12 - PIN12 (input pullup).\r
+ * PB13 - RMII_TXD1 (alternate 11).\r
+ * PB14 - LED3 LED_RED (output pushpull maximum).\r
+ * PB15 - PIN15 (input pullup).\r
+ */\r
+#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_LED1) | \\r
+ PIN_MODE_INPUT(GPIOB_PIN1) | \\r
+ PIN_MODE_INPUT(GPIOB_PIN2) | \\r
+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \\r
+ PIN_MODE_INPUT(GPIOB_PIN4) | \\r
+ PIN_MODE_INPUT(GPIOB_PIN5) | \\r
+ PIN_MODE_INPUT(GPIOB_PIN6) | \\r
+ PIN_MODE_INPUT(GPIOB_PIN7) | \\r
+ PIN_MODE_INPUT(GPIOB_PIN8) | \\r
+ PIN_MODE_INPUT(GPIOB_PIN9) | \\r
+ PIN_MODE_INPUT(GPIOB_PIN10) | \\r
+ PIN_MODE_INPUT(GPIOB_PIN11) | \\r
+ PIN_MODE_INPUT(GPIOB_PIN12) | \\r
+ PIN_MODE_ALTERNATE(GPIOB_RMII_TXD1) | \\r
+ PIN_MODE_OUTPUT(GPIOB_LED3) | \\r
+ PIN_MODE_INPUT(GPIOB_PIN15))\r
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_LED1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_RMII_TXD1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))\r
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_LED1) | \\r
+ PIN_OSPEED_VERYLOW(GPIOB_PIN1) | \\r
+ PIN_OSPEED_VERYLOW(GPIOB_PIN2) | \\r
+ PIN_OSPEED_HIGH(GPIOB_SWO) | \\r
+ PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \\r
+ PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \\r
+ PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \\r
+ PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \\r
+ PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \\r
+ PIN_OSPEED_VERYLOW(GPIOB_PIN9) | \\r
+ PIN_OSPEED_VERYLOW(GPIOB_PIN10) | \\r
+ PIN_OSPEED_VERYLOW(GPIOB_PIN11) | \\r
+ PIN_OSPEED_VERYLOW(GPIOB_PIN12) | \\r
+ PIN_OSPEED_HIGH(GPIOB_RMII_TXD1) | \\r
+ PIN_OSPEED_HIGH(GPIOB_LED3) | \\r
+ PIN_OSPEED_VERYLOW(GPIOB_PIN15))\r
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_LED1) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_SWO) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_PIN4) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_PIN6) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_PIN9) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_PIN10) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_RMII_TXD1) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_LED3) | \\r
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))\r
+#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_LED1) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN1) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOB_SWO) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOB_RMII_TXD1) | \\r
+ PIN_ODR_LOW(GPIOB_LED3) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN15))\r
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_LED1, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_SWO, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN7, 0U))\r
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_RMII_TXD1, 11U) | \\r
+ PIN_AFIO_AF(GPIOB_LED3, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN15, 0U))\r
+\r
+/*\r
+ * GPIOC setup:\r
+ *\r
+ * PC0 - PIN0 (input pullup).\r
+ * PC1 - RMII_MDC (alternate 11).\r
+ * PC2 - PIN2 (input pullup).\r
+ * PC3 - PIN3 (input pullup).\r
+ * PC4 - RMII_RXD0 (alternate 11).\r
+ * PC5 - RMII_RXD1 (alternate 11).\r
+ * PC6 - PIN6 (input pullup).\r
+ * PC7 - PIN7 (input pullup).\r
+ * PC8 - PIN8 (input pullup).\r
+ * PC9 - PIN9 (input pullup).\r
+ * PC10 - PIN10 (input pullup).\r
+ * PC11 - PIN11 (input pullup).\r
+ * PC12 - PIN12 (input pullup).\r
+ * PC13 - BUTTON (input floating).\r
+ * PC14 - OSC32_IN (input floating).\r
+ * PC15 - OSC32_OUT (input floating).\r
+ */\r
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \\r
+ PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \\r
+ PIN_MODE_INPUT(GPIOC_PIN2) | \\r
+ PIN_MODE_INPUT(GPIOC_PIN3) | \\r
+ PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \\r
+ PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \\r
+ PIN_MODE_INPUT(GPIOC_PIN6) | \\r
+ PIN_MODE_INPUT(GPIOC_PIN7) | \\r
+ PIN_MODE_INPUT(GPIOC_PIN8) | \\r
+ PIN_MODE_INPUT(GPIOC_PIN9) | \\r
+ PIN_MODE_INPUT(GPIOC_PIN10) | \\r
+ PIN_MODE_INPUT(GPIOC_PIN11) | \\r
+ PIN_MODE_INPUT(GPIOC_PIN12) | \\r
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \\r
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \\r
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))\r
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))\r
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | \\r
+ PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \\r
+ PIN_OSPEED_VERYLOW(GPIOC_PIN2) | \\r
+ PIN_OSPEED_VERYLOW(GPIOC_PIN3) | \\r
+ PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \\r
+ PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \\r
+ PIN_OSPEED_VERYLOW(GPIOC_PIN6) | \\r
+ PIN_OSPEED_VERYLOW(GPIOC_PIN7) | \\r
+ PIN_OSPEED_VERYLOW(GPIOC_PIN8) | \\r
+ PIN_OSPEED_VERYLOW(GPIOC_PIN9) | \\r
+ PIN_OSPEED_VERYLOW(GPIOC_PIN10) | \\r
+ PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \\r
+ PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \\r
+ PIN_OSPEED_HIGH(GPIOC_BUTTON) | \\r
+ PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \\r
+ PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT))\r
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \\r
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \\r
+ PIN_PUPDR_PULLUP(GPIOC_PIN3) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \\r
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \\r
+ PIN_PUPDR_PULLUP(GPIOC_PIN7) | \\r
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \\r
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \\r
+ PIN_PUPDR_PULLUP(GPIOC_PIN10) | \\r
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \\r
+ PIN_PUPDR_PULLUP(GPIOC_PIN12) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))\r
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \\r
+ PIN_ODR_HIGH(GPIOC_RMII_MDC) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \\r
+ PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOC_BUTTON) | \\r
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \\r
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))\r
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) | \\r
+ PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN7, 0U))\r
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))\r
+\r
+/*\r
+ * GPIOD setup:\r
+ *\r
+ * PD0 - PIN0 (input pullup).\r
+ * PD1 - PIN1 (input pullup).\r
+ * PD2 - PIN2 (input pullup).\r
+ * PD3 - PIN3 (input pullup).\r
+ * PD4 - PIN4 (input pullup).\r
+ * PD5 - PIN5 (input pullup).\r
+ * PD6 - PIN6 (input pullup).\r
+ * PD7 - PIN7 (input pullup).\r
+ * PD8 - USART3_RX STLK_RX (alternate 7).\r
+ * PD9 - USART3_TX STLK_TX (alternate 7).\r
+ * PD10 - PIN10 (input pullup).\r
+ * PD11 - PIN11 (input pullup).\r
+ * PD12 - PIN12 (input pullup).\r
+ * PD13 - PIN13 (input pullup).\r
+ * PD14 - PIN14 (input pullup).\r
+ * PD15 - PIN15 (input pullup).\r
+ */\r
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \\r
+ PIN_MODE_INPUT(GPIOD_PIN1) | \\r
+ PIN_MODE_INPUT(GPIOD_PIN2) | \\r
+ PIN_MODE_INPUT(GPIOD_PIN3) | \\r
+ PIN_MODE_INPUT(GPIOD_PIN4) | \\r
+ PIN_MODE_INPUT(GPIOD_PIN5) | \\r
+ PIN_MODE_INPUT(GPIOD_PIN6) | \\r
+ PIN_MODE_INPUT(GPIOD_PIN7) | \\r
+ PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \\r
+ PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \\r
+ PIN_MODE_INPUT(GPIOD_PIN10) | \\r
+ PIN_MODE_INPUT(GPIOD_PIN11) | \\r
+ PIN_MODE_INPUT(GPIOD_PIN12) | \\r
+ PIN_MODE_INPUT(GPIOD_PIN13) | \\r
+ PIN_MODE_INPUT(GPIOD_PIN14) | \\r
+ PIN_MODE_INPUT(GPIOD_PIN15))\r
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))\r
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | \\r
+ PIN_OSPEED_VERYLOW(GPIOD_PIN1) | \\r
+ PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \\r
+ PIN_OSPEED_VERYLOW(GPIOD_PIN3) | \\r
+ PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \\r
+ PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \\r
+ PIN_OSPEED_VERYLOW(GPIOD_PIN6) | \\r
+ PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \\r
+ PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \\r
+ PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \\r
+ PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \\r
+ PIN_OSPEED_VERYLOW(GPIOD_PIN11) | \\r
+ PIN_OSPEED_VERYLOW(GPIOD_PIN12) | \\r
+ PIN_OSPEED_VERYLOW(GPIOD_PIN13) | \\r
+ PIN_OSPEED_VERYLOW(GPIOD_PIN14) | \\r
+ PIN_OSPEED_VERYLOW(GPIOD_PIN15))\r
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \\r
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \\r
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \\r
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \\r
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \\r
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \\r
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \\r
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \\r
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \\r
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \\r
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \\r
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \\r
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \\r
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))\r
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN1) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOD_USART3_RX) | \\r
+ PIN_ODR_HIGH(GPIOD_USART3_TX) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN13) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN15))\r
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))\r
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \\r
+ PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))\r
+\r
+/*\r
+ * GPIOE setup:\r
+ *\r
+ * PE0 - PIN0 (input pullup).\r
+ * PE1 - PIN1 (input pullup).\r
+ * PE2 - PIN2 (input pullup).\r
+ * PE3 - PIN3 (input pullup).\r
+ * PE4 - PIN4 (input pullup).\r
+ * PE5 - PIN5 (input pullup).\r
+ * PE6 - PIN6 (input pullup).\r
+ * PE7 - PIN7 (input pullup).\r
+ * PE8 - PIN8 (input pullup).\r
+ * PE9 - PIN9 (input pullup).\r
+ * PE10 - PIN10 (input pullup).\r
+ * PE11 - PIN11 (input pullup).\r
+ * PE12 - PIN12 (input pullup).\r
+ * PE13 - PIN13 (input pullup).\r
+ * PE14 - PIN14 (input pullup).\r
+ * PE15 - PIN15 (input pullup).\r
+ */\r
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \\r
+ PIN_MODE_OUTPUT(GPIOE_LED2) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN2) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN3) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN4) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN5) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN6) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN7) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN8) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN9) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN10) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN11) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN12) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN13) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN14) | \\r
+ PIN_MODE_INPUT(GPIOE_PIN15))\r
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_LED2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))\r
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | \\r
+ PIN_OSPEED_HIGH(GPIOE_LED2) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN7) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN8) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN9) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN10) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN11) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN12) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN13) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN14) | \\r
+ PIN_OSPEED_VERYLOW(GPIOE_PIN15))\r
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_LED2) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN2) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN3) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN4) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN5) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN6) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN7) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN8) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN9) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN10) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN11) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN12) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN13) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN14) | \\r
+ PIN_PUPDR_PULLUP(GPIOE_PIN15))\r
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \\r
+ PIN_ODR_LOW(GPIOE_LED2) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN13) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN15))\r
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_LED2, 0U)) | \\r
+ PIN_AFIO_AF(GPIOE_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN7, 0U)\r
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN13, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN15, 0U))\r
+\r
+/*\r
+ * GPIOF setup:\r
+ *\r
+ * PF0 - PIN0 (input pullup).\r
+ * PF1 - PIN1 (input pullup).\r
+ * PF2 - PIN2 (input pullup).\r
+ * PF3 - PIN3 (input pullup).\r
+ * PF4 - PIN4 (input pullup).\r
+ * PF5 - PIN5 (input pullup).\r
+ * PF6 - PIN6 (input pullup).\r
+ * PF7 - PIN7 (input pullup).\r
+ * PF8 - PIN8 (input pullup).\r
+ * PF9 - PIN9 (input pullup).\r
+ * PF10 - PIN10 (input pullup).\r
+ * PF11 - PIN11 (input pullup).\r
+ * PF12 - PIN12 (input pullup).\r
+ * PF13 - PIN13 (input pullup).\r
+ * PF14 - PIN14 (input pullup).\r
+ * PF15 - PIN15 (input pullup).\r
+ */\r
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN1) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN2) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN3) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN4) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN5) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN6) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN7) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN8) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN9) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN10) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN11) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN12) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN13) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN14) | \\r
+ PIN_MODE_INPUT(GPIOF_PIN15))\r
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))\r
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_PIN0) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN1) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN2) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN3) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN4) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN5) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN7) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN8) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN9) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN10) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN12) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN13) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN14) | \\r
+ PIN_OSPEED_VERYLOW(GPIOF_PIN15))\r
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN1) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN2) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN3) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN4) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN5) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN6) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN7) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN8) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN9) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN10) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN11) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN12) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN13) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN14) | \\r
+ PIN_PUPDR_PULLUP(GPIOF_PIN15))\r
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN1) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN13) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN15))\r
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN1, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN7, 0U))\r
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN13, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN15, 0U))\r
+\r
+/*\r
+ * GPIOG setup:\r
+ *\r
+ * PG0 - PIN0 (input pullup).\r
+ * PG1 - PIN1 (input pullup).\r
+ * PG2 - PIN2 (input pullup).\r
+ * PG3 - PIN3 (input pullup).\r
+ * PG4 - PIN4 (input pullup).\r
+ * PG5 - PIN5 (input pullup).\r
+ * PG6 - USB_FS_PWR_EN (output pushpull minimum).\r
+ * PG7 - USB_FS_OVCR (input floating).\r
+ * PG8 - PIN8 (input pullup).\r
+ * PG9 - PIN9 (input pullup).\r
+ * PG10 - PIN10 (input pullup).\r
+ * PG11 - RMII_TX_EN (alternate 11).\r
+ * PG12 - PIN12 (input pullup).\r
+ * PG13 - RMII_TXD0 (alternate 11).\r
+ * PG14 - PIN14 (input pullup).\r
+ * PG15 - PIN15 (input pullup).\r
+ */\r
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \\r
+ PIN_MODE_INPUT(GPIOG_PIN1) | \\r
+ PIN_MODE_INPUT(GPIOG_PIN2) | \\r
+ PIN_MODE_INPUT(GPIOG_PIN3) | \\r
+ PIN_MODE_INPUT(GPIOG_PIN4) | \\r
+ PIN_MODE_INPUT(GPIOG_PIN5) | \\r
+ PIN_MODE_OUTPUT(GPIOG_USB_FS_PWR_EN) | \\r
+ PIN_MODE_INPUT(GPIOG_USB_FS_OVCR) | \\r
+ PIN_MODE_INPUT(GPIOG_PIN8) | \\r
+ PIN_MODE_INPUT(GPIOG_PIN9) | \\r
+ PIN_MODE_INPUT(GPIOG_PIN10) | \\r
+ PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \\r
+ PIN_MODE_INPUT(GPIOG_PIN12) | \\r
+ PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \\r
+ PIN_MODE_INPUT(GPIOG_PIN14) | \\r
+ PIN_MODE_INPUT(GPIOG_PIN15))\r
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_USB_FS_PWR_EN) |\\r
+ PIN_OTYPE_PUSHPULL(GPIOG_USB_FS_OVCR) |\\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))\r
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_USB_FS_PWR_EN) |\\r
+ PIN_OSPEED_VERYLOW(GPIOG_USB_FS_OVCR) |\\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \\r
+ PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \\r
+ PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN15))\r
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \\r
+ PIN_PUPDR_PULLUP(GPIOG_PIN1) | \\r
+ PIN_PUPDR_PULLUP(GPIOG_PIN2) | \\r
+ PIN_PUPDR_PULLUP(GPIOG_PIN3) | \\r
+ PIN_PUPDR_PULLUP(GPIOG_PIN4) | \\r
+ PIN_PUPDR_PULLUP(GPIOG_PIN5) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_USB_FS_PWR_EN) |\\r
+ PIN_PUPDR_FLOATING(GPIOG_USB_FS_OVCR) |\\r
+ PIN_PUPDR_PULLUP(GPIOG_PIN8) | \\r
+ PIN_PUPDR_PULLUP(GPIOG_PIN9) | \\r
+ PIN_PUPDR_PULLUP(GPIOG_PIN10) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \\r
+ PIN_PUPDR_PULLUP(GPIOG_PIN12) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \\r
+ PIN_PUPDR_PULLUP(GPIOG_PIN14) | \\r
+ PIN_PUPDR_PULLUP(GPIOG_PIN15))\r
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN1) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN5) | \\r
+ PIN_ODR_LOW(GPIOG_USB_FS_PWR_EN) | \\r
+ PIN_ODR_HIGH(GPIOG_USB_FS_OVCR) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN15))\r
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN1, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_USB_FS_PWR_EN, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_USB_FS_OVCR, 0U))\r
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN15, 0U))\r
+\r
+/*\r
+ * GPIOH setup:\r
+ *\r
+ * PH0 - OSC_IN (input floating).\r
+ * PH1 - OSC_OUT (input floating).\r
+ * PH2 - PIN2 (input pullup).\r
+ * PH3 - PIN3 (input pullup).\r
+ * PH4 - PIN4 (input pullup).\r
+ * PH5 - PIN5 (input pullup).\r
+ * PH6 - PIN6 (input pullup).\r
+ * PH7 - PIN7 (input pullup).\r
+ * PH8 - PIN8 (input pullup).\r
+ * PH9 - PIN9 (input pullup).\r
+ * PH10 - PIN10 (input pullup).\r
+ * PH11 - PIN11 (input pullup).\r
+ * PH12 - PIN12 (input pullup).\r
+ * PH13 - PIN13 (input pullup).\r
+ * PH14 - PIN14 (input pullup).\r
+ * PH15 - PIN15 (input pullup).\r
+ */\r
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \\r
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN2) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN3) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN4) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN5) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN6) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN7) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN8) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN9) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN10) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN11) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN12) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN13) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN14) | \\r
+ PIN_MODE_INPUT(GPIOH_PIN15))\r
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))\r
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \\r
+ PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN15))\r
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN2) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN3) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN4) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN5) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN6) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN7) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN8) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN9) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN10) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN11) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN12) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN13) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN14) | \\r
+ PIN_PUPDR_PULLUP(GPIOH_PIN15))\r
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \\r
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN13) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN15))\r
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN7, 0U))\r
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN15, 0U))\r
+\r
+/*\r
+ * GPIOI setup:\r
+ *\r
+ * PI0 - PIN0 (input pullup).\r
+ * PI1 - PIN1 (input pullup).\r
+ * PI2 - PIN2 (input pullup).\r
+ * PI3 - PIN3 (input pullup).\r
+ * PI4 - PIN4 (input pullup).\r
+ * PI5 - PIN5 (input pullup).\r
+ * PI6 - PIN6 (input pullup).\r
+ * PI7 - PIN7 (input pullup).\r
+ * PI8 - PIN8 (input pullup).\r
+ * PI9 - PIN9 (input pullup).\r
+ * PI10 - PIN10 (input pullup).\r
+ * PI11 - PIN11 (input pullup).\r
+ * PI12 - PIN12 (input pullup).\r
+ * PI13 - PIN13 (input pullup).\r
+ * PI14 - PIN14 (input pullup).\r
+ * PI15 - PIN15 (input pullup).\r
+ */\r
+#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN1) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN2) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN3) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN4) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN5) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN6) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN7) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN8) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN9) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN10) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN11) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN12) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN13) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN14) | \\r
+ PIN_MODE_INPUT(GPIOI_PIN15))\r
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))\r
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \\r
+ PIN_OSPEED_VERYLOW(GPIOI_PIN15))\r
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN1) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN2) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN3) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN4) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN5) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN6) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN7) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN8) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN9) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN10) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN11) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN12) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN13) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN14) | \\r
+ PIN_PUPDR_PULLUP(GPIOI_PIN15))\r
+#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN1) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN13) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOI_PIN15))\r
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN1, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN7, 0U))\r
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN13, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOI_PIN15, 0U))\r
+\r
+/*\r
+ * GPIOJ setup:\r
+ *\r
+ * PJ0 - PIN0 (input pullup).\r
+ * PJ1 - PIN1 (input pullup).\r
+ * PJ2 - PIN2 (input pullup).\r
+ * PJ3 - PIN3 (input pullup).\r
+ * PJ4 - PIN4 (input pullup).\r
+ * PJ5 - PIN5 (input pullup).\r
+ * PJ6 - PIN6 (input pullup).\r
+ * PJ7 - PIN7 (input pullup).\r
+ * PJ8 - PIN8 (input pullup).\r
+ * PJ9 - PIN9 (input pullup).\r
+ * PJ10 - PIN10 (input pullup).\r
+ * PJ11 - PIN11 (input pullup).\r
+ * PJ12 - PIN12 (input pullup).\r
+ * PJ13 - PIN13 (input pullup).\r
+ * PJ14 - PIN14 (input pullup).\r
+ * PJ15 - PIN15 (input pullup).\r
+ */\r
+#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN1) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN2) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN3) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN4) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN5) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN6) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN7) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN8) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN9) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN10) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN11) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN12) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN13) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN14) | \\r
+ PIN_MODE_INPUT(GPIOJ_PIN15))\r
+#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN15))\r
+#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN1) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN2) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN3) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN4) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN5) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN12) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN13) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN14) | \\r
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN15))\r
+#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLUP(GPIOJ_PIN0) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN1) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN2) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN3) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN4) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN5) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN6) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN7) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN8) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN9) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN10) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN11) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN12) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN13) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN14) | \\r
+ PIN_PUPDR_PULLUP(GPIOJ_PIN15))\r
+#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN1) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN13) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOJ_PIN15))\r
+#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN7, 0U))\r
+#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOJ_PIN15, 0U))\r
+\r
+/*\r
+ * GPIOK setup:\r
+ *\r
+ * PK0 - PIN0 (input pullup).\r
+ * PK1 - PIN1 (input pullup).\r
+ * PK2 - PIN2 (input pullup).\r
+ * PK3 - PIN3 (input pullup).\r
+ * PK4 - PIN4 (input pullup).\r
+ * PK5 - PIN5 (input pullup).\r
+ * PK6 - PIN6 (input pullup).\r
+ * PK7 - PIN7 (input pullup).\r
+ * PK8 - PIN8 (input pullup).\r
+ * PK9 - PIN9 (input pullup).\r
+ * PK10 - PIN10 (input pullup).\r
+ * PK11 - PIN11 (input pullup).\r
+ * PK12 - PIN12 (input pullup).\r
+ * PK13 - PIN13 (input pullup).\r
+ * PK14 - PIN14 (input pullup).\r
+ * PK15 - PIN15 (input pullup).\r
+ */\r
+#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN1) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN2) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN3) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN4) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN5) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN6) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN7) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN8) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN9) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN10) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN11) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN12) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN13) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN14) | \\r
+ PIN_MODE_INPUT(GPIOK_PIN15))\r
+#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN15))\r
+#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \\r
+ PIN_OSPEED_VERYLOW(GPIOK_PIN15))\r
+#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLUP(GPIOK_PIN0) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN1) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN2) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN3) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN4) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN5) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN6) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN7) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN8) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN9) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN10) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN11) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN12) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN13) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN14) | \\r
+ PIN_PUPDR_PULLUP(GPIOK_PIN15))\r
+#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN1) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN13) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOK_PIN15))\r
+#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN1, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN7, 0U))\r
+#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN13, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOK_PIN15, 0U))\r
+\r
+/*===========================================================================*/\r
+/* External declarations. */\r
+/*===========================================================================*/\r
+\r
+#if !defined(_FROM_ASM_)\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+ void boardInit(void);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* _FROM_ASM_ */\r
+\r
+#endif /* BOARD_H */\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/*\r
+ * This file has been automatically generated using ChibiStudio board\r
+ * generator plugin. Do not edit manually.\r
+ */\r
+\r
+#ifndef BOARD_H\r
+#define BOARD_H\r
+\r
+/*===========================================================================*/\r
+/* Driver constants. */\r
+/*===========================================================================*/\r
+\r
+/*\r
+ * Setup for STMicroelectronics STM32 Nucleo64-L476RG board.\r
+ */\r
+\r
+/*\r
+ * Board identifier.\r
+ */\r
+#define BOARD_ST_NUCLEO64_L476RG\r
+#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-L476RG"\r
+\r
+/*\r
+ * Board oscillators-related settings.\r
+ */\r
+#if !defined(STM32_LSECLK)\r
+#define STM32_LSECLK 32768U\r
+#endif\r
+\r
+#define STM32_LSEDRV (3U << 3U)\r
+\r
+#if !defined(STM32_HSECLK)\r
+#define STM32_HSECLK 8000000U\r
+#endif\r
+\r
+#define STM32_HSE_BYPASS\r
+\r
+/*\r
+ * Board voltages.\r
+ * Required for performance limits calculation.\r
+ */\r
+#define STM32_VDD 300U\r
+\r
+/*\r
+ * MCU type as defined in the ST header.\r
+ */\r
+#define STM32L476xx\r
+\r
+/*\r
+ * IO pins assignments.\r
+ */\r
+#define GPIOA_ARD_A0 0U\r
+#define GPIOA_ACD12_IN5 0U\r
+#define GPIOA_ARD_A1 1U\r
+#define GPIOA_ACD12_IN6 1U\r
+#define GPIOA_ARD_D1 2U\r
+#define GPIOA_USART2_TX 2U\r
+#define GPIOA_ARD_D0 3U\r
+#define GPIOA_USART2_RX 3U\r
+#define GPIOA_ARD_A2 4U\r
+#define GPIOA_ACD12_IN9 4U\r
+#define GPIOA_ARD_D13 5U\r
+#define GPIOA_LED_GREEN 5U\r
+#define GPIOA_ARD_D12 6U\r
+#define GPIOA_ARD_D11 7U\r
+#define GPIOA_ARD_D7 8U\r
+#define GPIOA_ARD_D8 9U\r
+#define GPIOA_ARD_D2 10U\r
+#define GPIOA_PIN11 11U\r
+#define GPIOA_PIN12 12U\r
+#define GPIOA_SWDIO 13U\r
+#define GPIOA_SWCLK 14U\r
+#define GPIOA_PIN15 15U\r
+\r
+#define GPIOB_ARD_A3 0U\r
+#define GPIOB_ACD12_IN15 0U\r
+#define GPIOB_PIN1 1U\r
+#define GPIOB_PIN2 2U\r
+#define GPIOB_ARD_D3 3U\r
+#define GPIOB_SWO 3U\r
+#define GPIOB_ARD_D5 4U\r
+#define GPIOB_ARD_D4 5U\r
+#define GPIOB_ARD_D10 6U\r
+#define GPIOB_PIN7 7U\r
+#define GPIOB_ARD_D15 8U\r
+#define GPIOB_ARD_D14 9U\r
+#define GPIOB_ARD_D6 10U\r
+#define GPIOB_PIN11 11U\r
+#define GPIOB_PIN12 12U\r
+#define GPIOB_PIN13 13U\r
+#define GPIOB_PIN14 14U\r
+#define GPIOB_PIN15 15U\r
+\r
+#define GPIOC_ARD_A5 0U\r
+#define GPIOC_ACD123_IN1 0U\r
+#define GPIOC_ARD_A4 1U\r
+#define GPIOC_ACD123_IN2 1U\r
+#define GPIOC_PIN2 2U\r
+#define GPIOC_PIN3 3U\r
+#define GPIOC_PIN4 4U\r
+#define GPIOC_PIN5 5U\r
+#define GPIOC_PIN6 6U\r
+#define GPIOC_ARD_D9 7U\r
+#define GPIOC_PIN8 8U\r
+#define GPIOC_PIN9 9U\r
+#define GPIOC_PIN10 10U\r
+#define GPIOC_PIN11 11U\r
+#define GPIOC_PIN12 12U\r
+#define GPIOC_BUTTON 13U\r
+#define GPIOC_OSC32_IN 14U\r
+#define GPIOC_OSC32_OUT 15U\r
+\r
+#define GPIOD_PIN0 0U\r
+#define GPIOD_PIN1 1U\r
+#define GPIOD_PIN2 2U\r
+#define GPIOD_PIN3 3U\r
+#define GPIOD_PIN4 4U\r
+#define GPIOD_PIN5 5U\r
+#define GPIOD_PIN6 6U\r
+#define GPIOD_PIN7 7U\r
+#define GPIOD_PIN8 8U\r
+#define GPIOD_PIN9 9U\r
+#define GPIOD_PIN10 10U\r
+#define GPIOD_PIN11 11U\r
+#define GPIOD_PIN12 12U\r
+#define GPIOD_PIN13 13U\r
+#define GPIOD_PIN14 14U\r
+#define GPIOD_PIN15 15U\r
+\r
+#define GPIOE_PIN0 0U\r
+#define GPIOE_PIN1 1U\r
+#define GPIOE_PIN2 2U\r
+#define GPIOE_PIN3 3U\r
+#define GPIOE_PIN4 4U\r
+#define GPIOE_PIN5 5U\r
+#define GPIOE_PIN6 6U\r
+#define GPIOE_PIN7 7U\r
+#define GPIOE_PIN8 8U\r
+#define GPIOE_PIN9 9U\r
+#define GPIOE_PIN10 10U\r
+#define GPIOE_PIN11 11U\r
+#define GPIOE_PIN12 12U\r
+#define GPIOE_PIN13 13U\r
+#define GPIOE_PIN14 14U\r
+#define GPIOE_PIN15 15U\r
+\r
+#define GPIOF_PIN0 0U\r
+#define GPIOF_PIN1 1U\r
+#define GPIOF_PIN2 2U\r
+#define GPIOF_PIN3 3U\r
+#define GPIOF_PIN4 4U\r
+#define GPIOF_PIN5 5U\r
+#define GPIOF_PIN6 6U\r
+#define GPIOF_PIN7 7U\r
+#define GPIOF_PIN8 8U\r
+#define GPIOF_PIN9 9U\r
+#define GPIOF_PIN10 10U\r
+#define GPIOF_PIN11 11U\r
+#define GPIOF_PIN12 12U\r
+#define GPIOF_PIN13 13U\r
+#define GPIOF_PIN14 14U\r
+#define GPIOF_PIN15 15U\r
+\r
+#define GPIOG_PIN0 0U\r
+#define GPIOG_PIN1 1U\r
+#define GPIOG_PIN2 2U\r
+#define GPIOG_PIN3 3U\r
+#define GPIOG_PIN4 4U\r
+#define GPIOG_PIN5 5U\r
+#define GPIOG_PIN6 6U\r
+#define GPIOG_PIN7 7U\r
+#define GPIOG_PIN8 8U\r
+#define GPIOG_PIN9 9U\r
+#define GPIOG_PIN10 10U\r
+#define GPIOG_PIN11 11U\r
+#define GPIOG_PIN12 12U\r
+#define GPIOG_PIN13 13U\r
+#define GPIOG_PIN14 14U\r
+#define GPIOG_PIN15 15U\r
+\r
+#define GPIOH_OSC_IN 0U\r
+#define GPIOH_OSC_OUT 1U\r
+#define GPIOH_PIN2 2U\r
+#define GPIOH_PIN3 3U\r
+#define GPIOH_PIN4 4U\r
+#define GPIOH_PIN5 5U\r
+#define GPIOH_PIN6 6U\r
+#define GPIOH_PIN7 7U\r
+#define GPIOH_PIN8 8U\r
+#define GPIOH_PIN9 9U\r
+#define GPIOH_PIN10 10U\r
+#define GPIOH_PIN11 11U\r
+#define GPIOH_PIN12 12U\r
+#define GPIOH_PIN13 13U\r
+#define GPIOH_PIN14 14U\r
+#define GPIOH_PIN15 15U\r
+\r
+/*\r
+ * IO lines assignments.\r
+ */\r
+#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U)\r
+#define LINE_ACD12_IN5 PAL_LINE(GPIOA, 0U)\r
+#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U)\r
+#define LINE_ACD12_IN6 PAL_LINE(GPIOA, 1U)\r
+#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U)\r
+#define LINE_USART2_TX PAL_LINE(GPIOA, 2U)\r
+#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U)\r
+#define LINE_USART2_RX PAL_LINE(GPIOA, 3U)\r
+#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U)\r
+#define LINE_ACD12_IN9 PAL_LINE(GPIOA, 4U)\r
+#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U)\r
+#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U)\r
+#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U)\r
+#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U)\r
+#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U)\r
+#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U)\r
+#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U)\r
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)\r
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)\r
+#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U)\r
+#define LINE_ACD12_IN15 PAL_LINE(GPIOB, 0U)\r
+#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U)\r
+#define LINE_SWO PAL_LINE(GPIOB, 3U)\r
+#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U)\r
+#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U)\r
+#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U)\r
+#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U)\r
+#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U)\r
+#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U)\r
+#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U)\r
+#define LINE_ACD123_IN1 PAL_LINE(GPIOC, 0U)\r
+#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U)\r
+#define LINE_ACD123_IN2 PAL_LINE(GPIOC, 1U)\r
+#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U)\r
+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)\r
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)\r
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)\r
+#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)\r
+#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)\r
+\r
+/*===========================================================================*/\r
+/* Driver pre-compile time settings. */\r
+/*===========================================================================*/\r
+\r
+/*===========================================================================*/\r
+/* Derived constants and error checks. */\r
+/*===========================================================================*/\r
+\r
+/*===========================================================================*/\r
+/* Driver data structures and types. */\r
+/*===========================================================================*/\r
+\r
+/*===========================================================================*/\r
+/* Driver macros. */\r
+/*===========================================================================*/\r
+\r
+/*\r
+ * I/O ports initial setup, this configuration is established soon after reset\r
+ * in the initialization code.\r
+ * Please refer to the STM32 Reference Manual for details.\r
+ */\r
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))\r
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))\r
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))\r
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))\r
+#define PIN_ODR_LOW(n) (0U << (n))\r
+#define PIN_ODR_HIGH(n) (1U << (n))\r
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))\r
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))\r
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))\r
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))\r
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))\r
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))\r
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))\r
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))\r
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))\r
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))\r
+#define PIN_ASCR_DISABLED(n) (0U << (n))\r
+#define PIN_ASCR_ENABLED(n) (1U << (n))\r
+#define PIN_LOCKR_DISABLED(n) (0U << (n))\r
+#define PIN_LOCKR_ENABLED(n) (1U << (n))\r
+\r
+/*\r
+ * GPIOA setup:\r
+ *\r
+ * PA0 - ARD_A0 ACD12_IN5 (analog).\r
+ * PA1 - ARD_A1 ACD12_IN6 (analog).\r
+ * PA2 - ARD_D1 USART2_TX (alternate 7).\r
+ * PA3 - ARD_D0 USART2_RX (alternate 7).\r
+ * PA4 - ARD_A2 ACD12_IN9 (analog).\r
+ * PA5 - ARD_D13 LED_GREEN (output pushpull maximum).\r
+ * PA6 - ARD_D12 (analog).\r
+ * PA7 - ARD_D11 (analog).\r
+ * PA8 - ARD_D7 (analog).\r
+ * PA9 - ARD_D8 (analog).\r
+ * PA10 - ARD_D2 (analog).\r
+ * PA11 - PIN11 (analog).\r
+ * PA12 - PIN12 (analog).\r
+ * PA13 - SWDIO (alternate 0).\r
+ * PA14 - SWCLK (alternate 0).\r
+ * PA15 - PIN15 (analog).\r
+ */\r
+#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_ARD_A0) | \\r
+ PIN_MODE_ANALOG(GPIOA_ARD_A1) | \\r
+ PIN_MODE_ALTERNATE(GPIOA_ARD_D1) | \\r
+ PIN_MODE_ALTERNATE(GPIOA_ARD_D0) | \\r
+ PIN_MODE_ANALOG(GPIOA_ARD_A2) | \\r
+ PIN_MODE_OUTPUT(GPIOA_ARD_D13) | \\r
+ PIN_MODE_ANALOG(GPIOA_ARD_D12) | \\r
+ PIN_MODE_ANALOG(GPIOA_ARD_D11) | \\r
+ PIN_MODE_ANALOG(GPIOA_ARD_D7) | \\r
+ PIN_MODE_ANALOG(GPIOA_ARD_D8) | \\r
+ PIN_MODE_ANALOG(GPIOA_ARD_D2) | \\r
+ PIN_MODE_ANALOG(GPIOA_PIN11) | \\r
+ PIN_MODE_ANALOG(GPIOA_PIN12) | \\r
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \\r
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \\r
+ PIN_MODE_ANALOG(GPIOA_PIN15))\r
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))\r
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \\r
+ PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \\r
+ PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | \\r
+ PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | \\r
+ PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \\r
+ PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \\r
+ PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \\r
+ PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \\r
+ PIN_OSPEED_HIGH(GPIOA_ARD_D7) | \\r
+ PIN_OSPEED_HIGH(GPIOA_ARD_D8) | \\r
+ PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \\r
+ PIN_OSPEED_HIGH(GPIOA_PIN11) | \\r
+ PIN_OSPEED_HIGH(GPIOA_PIN12) | \\r
+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \\r
+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \\r
+ PIN_OSPEED_HIGH(GPIOA_PIN15))\r
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_ARD_A0) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_ARD_A1) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_ARD_A2) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D13) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D12) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D11) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D7) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D8) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D2) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_PIN11) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_PIN12) | \\r
+ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \\r
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \\r
+ PIN_PUPDR_FLOATING(GPIOA_PIN15))\r
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \\r
+ PIN_ODR_HIGH(GPIOA_ARD_A1) | \\r
+ PIN_ODR_HIGH(GPIOA_ARD_D1) | \\r
+ PIN_ODR_HIGH(GPIOA_ARD_D0) | \\r
+ PIN_ODR_HIGH(GPIOA_ARD_A2) | \\r
+ PIN_ODR_LOW(GPIOA_ARD_D13) | \\r
+ PIN_ODR_HIGH(GPIOA_ARD_D12) | \\r
+ PIN_ODR_HIGH(GPIOA_ARD_D11) | \\r
+ PIN_ODR_HIGH(GPIOA_ARD_D7) | \\r
+ PIN_ODR_HIGH(GPIOA_ARD_D8) | \\r
+ PIN_ODR_HIGH(GPIOA_ARD_D2) | \\r
+ PIN_ODR_HIGH(GPIOA_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOA_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \\r
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \\r
+ PIN_ODR_HIGH(GPIOA_PIN15))\r
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_ARD_D1, 7U) | \\r
+ PIN_AFIO_AF(GPIOA_ARD_D0, 7U) | \\r
+ PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_ARD_D11, 0U))\r
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \\r
+ PIN_AFIO_AF(GPIOA_PIN15, 0U))\r
+#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_ARD_A0) | \\r
+ PIN_ASCR_DISABLED(GPIOA_ARD_A1) | \\r
+ PIN_ASCR_DISABLED(GPIOA_ARD_D1) | \\r
+ PIN_ASCR_DISABLED(GPIOA_ARD_D0) | \\r
+ PIN_ASCR_DISABLED(GPIOA_ARD_A2) | \\r
+ PIN_ASCR_DISABLED(GPIOA_ARD_D13) | \\r
+ PIN_ASCR_DISABLED(GPIOA_ARD_D12) | \\r
+ PIN_ASCR_DISABLED(GPIOA_ARD_D11) | \\r
+ PIN_ASCR_DISABLED(GPIOA_ARD_D7) | \\r
+ PIN_ASCR_DISABLED(GPIOA_ARD_D8) | \\r
+ PIN_ASCR_DISABLED(GPIOA_ARD_D2) | \\r
+ PIN_ASCR_DISABLED(GPIOA_PIN11) | \\r
+ PIN_ASCR_DISABLED(GPIOA_PIN12) | \\r
+ PIN_ASCR_DISABLED(GPIOA_SWDIO) | \\r
+ PIN_ASCR_DISABLED(GPIOA_SWCLK) | \\r
+ PIN_ASCR_DISABLED(GPIOA_PIN15))\r
+#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_ARD_A0) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_ARD_A1) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D1) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D0) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_ARD_A2) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D13) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D12) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D11) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D7) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D8) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D2) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_PIN11) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_PIN12) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \\r
+ PIN_LOCKR_DISABLED(GPIOA_PIN15))\r
+\r
+/*\r
+ * GPIOB setup:\r
+ *\r
+ * PB0 - ARD_A3 ACD12_IN15 (analog).\r
+ * PB1 - PIN1 (analog).\r
+ * PB2 - PIN2 (analog).\r
+ * PB3 - ARD_D3 SWO (analog).\r
+ * PB4 - ARD_D5 (analog).\r
+ * PB5 - ARD_D4 (analog).\r
+ * PB6 - ARD_D10 (analog).\r
+ * PB7 - PIN7 (analog).\r
+ * PB8 - ARD_D15 (analog).\r
+ * PB9 - ARD_D14 (analog).\r
+ * PB10 - ARD_D6 (analog).\r
+ * PB11 - PIN11 (analog).\r
+ * PB12 - PIN12 (analog).\r
+ * PB13 - PIN13 (analog).\r
+ * PB14 - PIN14 (analog).\r
+ * PB15 - PIN15 (analog).\r
+ */\r
+#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_ARD_A3) | \\r
+ PIN_MODE_ANALOG(GPIOB_PIN1) | \\r
+ PIN_MODE_ANALOG(GPIOB_PIN2) | \\r
+ PIN_MODE_ANALOG(GPIOB_ARD_D3) | \\r
+ PIN_MODE_ANALOG(GPIOB_ARD_D5) | \\r
+ PIN_MODE_ANALOG(GPIOB_ARD_D4) | \\r
+ PIN_MODE_ANALOG(GPIOB_ARD_D10) | \\r
+ PIN_MODE_ANALOG(GPIOB_PIN7) | \\r
+ PIN_MODE_ANALOG(GPIOB_ARD_D15) | \\r
+ PIN_MODE_ANALOG(GPIOB_ARD_D14) | \\r
+ PIN_MODE_ANALOG(GPIOB_ARD_D6) | \\r
+ PIN_MODE_ANALOG(GPIOB_PIN11) | \\r
+ PIN_MODE_ANALOG(GPIOB_PIN12) | \\r
+ PIN_MODE_ANALOG(GPIOB_PIN13) | \\r
+ PIN_MODE_ANALOG(GPIOB_PIN14) | \\r
+ PIN_MODE_ANALOG(GPIOB_PIN15))\r
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))\r
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_A3) | \\r
+ PIN_OSPEED_HIGH(GPIOB_PIN1) | \\r
+ PIN_OSPEED_HIGH(GPIOB_PIN2) | \\r
+ PIN_OSPEED_HIGH(GPIOB_ARD_D3) | \\r
+ PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \\r
+ PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \\r
+ PIN_OSPEED_HIGH(GPIOB_ARD_D10) | \\r
+ PIN_OSPEED_HIGH(GPIOB_PIN7) | \\r
+ PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \\r
+ PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \\r
+ PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \\r
+ PIN_OSPEED_HIGH(GPIOB_PIN11) | \\r
+ PIN_OSPEED_HIGH(GPIOB_PIN12) | \\r
+ PIN_OSPEED_HIGH(GPIOB_PIN13) | \\r
+ PIN_OSPEED_HIGH(GPIOB_PIN14) | \\r
+ PIN_OSPEED_HIGH(GPIOB_PIN15))\r
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_ARD_A3) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_PIN1) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_PIN2) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D3) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D5) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D4) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D10) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_PIN7) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D15) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D14) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D6) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_PIN11) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_PIN12) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_PIN13) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_PIN14) | \\r
+ PIN_PUPDR_FLOATING(GPIOB_PIN15))\r
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_A3) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN1) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOB_ARD_D3) | \\r
+ PIN_ODR_HIGH(GPIOB_ARD_D5) | \\r
+ PIN_ODR_HIGH(GPIOB_ARD_D4) | \\r
+ PIN_ODR_HIGH(GPIOB_ARD_D10) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOB_ARD_D15) | \\r
+ PIN_ODR_HIGH(GPIOB_ARD_D14) | \\r
+ PIN_ODR_HIGH(GPIOB_ARD_D6) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN13) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOB_PIN15))\r
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_ARD_D3, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN7, 0U))\r
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN13, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOB_PIN15, 0U))\r
+#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_ARD_A3) | \\r
+ PIN_ASCR_DISABLED(GPIOB_PIN1) | \\r
+ PIN_ASCR_DISABLED(GPIOB_PIN2) | \\r
+ PIN_ASCR_DISABLED(GPIOB_ARD_D3) | \\r
+ PIN_ASCR_DISABLED(GPIOB_ARD_D5) | \\r
+ PIN_ASCR_DISABLED(GPIOB_ARD_D4) | \\r
+ PIN_ASCR_DISABLED(GPIOB_ARD_D10) | \\r
+ PIN_ASCR_DISABLED(GPIOB_PIN7) | \\r
+ PIN_ASCR_DISABLED(GPIOB_ARD_D15) | \\r
+ PIN_ASCR_DISABLED(GPIOB_ARD_D14) | \\r
+ PIN_ASCR_DISABLED(GPIOB_ARD_D6) | \\r
+ PIN_ASCR_DISABLED(GPIOB_PIN11) | \\r
+ PIN_ASCR_DISABLED(GPIOB_PIN12) | \\r
+ PIN_ASCR_DISABLED(GPIOB_PIN13) | \\r
+ PIN_ASCR_DISABLED(GPIOB_PIN14) | \\r
+ PIN_ASCR_DISABLED(GPIOB_PIN15))\r
+#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_ARD_A3) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_PIN1) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_PIN2) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D3) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D5) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D4) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D10) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_PIN7) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D15) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D14) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D6) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_PIN11) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_PIN12) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_PIN13) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_PIN14) | \\r
+ PIN_LOCKR_DISABLED(GPIOB_PIN15))\r
+\r
+/*\r
+ * GPIOC setup:\r
+ *\r
+ * PC0 - ARD_A5 ACD123_IN1 (analog).\r
+ * PC1 - ARD_A4 ACD123_IN2 (analog).\r
+ * PC2 - PIN2 (analog).\r
+ * PC3 - PIN3 (analog).\r
+ * PC4 - PIN4 (analog).\r
+ * PC5 - PIN5 (analog).\r
+ * PC6 - PIN6 (analog).\r
+ * PC7 - ARD_D9 (analog).\r
+ * PC8 - PIN8 (analog).\r
+ * PC9 - PIN9 (analog).\r
+ * PC10 - PIN10 (analog).\r
+ * PC11 - PIN11 (analog).\r
+ * PC12 - PIN12 (analog).\r
+ * PC13 - BUTTON (input floating).\r
+ * PC14 - OSC32_IN (input floating).\r
+ * PC15 - OSC32_OUT (input floating).\r
+ */\r
+#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_ARD_A5) | \\r
+ PIN_MODE_ANALOG(GPIOC_ARD_A4) | \\r
+ PIN_MODE_ANALOG(GPIOC_PIN2) | \\r
+ PIN_MODE_ANALOG(GPIOC_PIN3) | \\r
+ PIN_MODE_ANALOG(GPIOC_PIN4) | \\r
+ PIN_MODE_ANALOG(GPIOC_PIN5) | \\r
+ PIN_MODE_ANALOG(GPIOC_PIN6) | \\r
+ PIN_MODE_ANALOG(GPIOC_ARD_D9) | \\r
+ PIN_MODE_ANALOG(GPIOC_PIN8) | \\r
+ PIN_MODE_ANALOG(GPIOC_PIN9) | \\r
+ PIN_MODE_ANALOG(GPIOC_PIN10) | \\r
+ PIN_MODE_ANALOG(GPIOC_PIN11) | \\r
+ PIN_MODE_ANALOG(GPIOC_PIN12) | \\r
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \\r
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \\r
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))\r
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_D9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))\r
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A5) | \\r
+ PIN_OSPEED_HIGH(GPIOC_ARD_A4) | \\r
+ PIN_OSPEED_HIGH(GPIOC_PIN2) | \\r
+ PIN_OSPEED_HIGH(GPIOC_PIN3) | \\r
+ PIN_OSPEED_HIGH(GPIOC_PIN4) | \\r
+ PIN_OSPEED_HIGH(GPIOC_PIN5) | \\r
+ PIN_OSPEED_HIGH(GPIOC_PIN6) | \\r
+ PIN_OSPEED_HIGH(GPIOC_ARD_D9) | \\r
+ PIN_OSPEED_HIGH(GPIOC_PIN8) | \\r
+ PIN_OSPEED_HIGH(GPIOC_PIN9) | \\r
+ PIN_OSPEED_HIGH(GPIOC_PIN10) | \\r
+ PIN_OSPEED_HIGH(GPIOC_PIN11) | \\r
+ PIN_OSPEED_HIGH(GPIOC_PIN12) | \\r
+ PIN_OSPEED_HIGH(GPIOC_BUTTON) | \\r
+ PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \\r
+ PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))\r
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ARD_A5) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_ARD_A4) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_PIN2) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_PIN3) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_PIN4) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_PIN5) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_PIN6) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_ARD_D9) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_PIN8) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_PIN9) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_PIN10) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_PIN11) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_PIN12) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \\r
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))\r
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A5) | \\r
+ PIN_ODR_HIGH(GPIOC_ARD_A4) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOC_ARD_D9) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOC_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOC_BUTTON) | \\r
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \\r
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))\r
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_ARD_D9, 0U))\r
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \\r
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))\r
+#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_ARD_A5) | \\r
+ PIN_ASCR_DISABLED(GPIOC_ARD_A4) | \\r
+ PIN_ASCR_DISABLED(GPIOC_PIN2) | \\r
+ PIN_ASCR_DISABLED(GPIOC_PIN3) | \\r
+ PIN_ASCR_DISABLED(GPIOC_PIN4) | \\r
+ PIN_ASCR_DISABLED(GPIOC_PIN5) | \\r
+ PIN_ASCR_DISABLED(GPIOC_PIN6) | \\r
+ PIN_ASCR_DISABLED(GPIOC_ARD_D9) | \\r
+ PIN_ASCR_DISABLED(GPIOC_PIN8) | \\r
+ PIN_ASCR_DISABLED(GPIOC_PIN9) | \\r
+ PIN_ASCR_DISABLED(GPIOC_PIN10) | \\r
+ PIN_ASCR_DISABLED(GPIOC_PIN11) | \\r
+ PIN_ASCR_DISABLED(GPIOC_PIN12) | \\r
+ PIN_ASCR_DISABLED(GPIOC_BUTTON) | \\r
+ PIN_ASCR_DISABLED(GPIOC_OSC32_IN) | \\r
+ PIN_ASCR_DISABLED(GPIOC_OSC32_OUT))\r
+#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_ARD_A5) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_ARD_A4) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_PIN2) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_PIN3) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_PIN4) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_PIN5) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_PIN6) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_ARD_D9) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_PIN8) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_PIN9) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_PIN10) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_PIN11) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_PIN12) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_BUTTON) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_OSC32_IN) | \\r
+ PIN_LOCKR_DISABLED(GPIOC_OSC32_OUT))\r
+\r
+/*\r
+ * GPIOD setup:\r
+ *\r
+ * PD0 - PIN0 (analog).\r
+ * PD1 - PIN1 (analog).\r
+ * PD2 - PIN2 (analog).\r
+ * PD3 - PIN3 (analog).\r
+ * PD4 - PIN4 (analog).\r
+ * PD5 - PIN5 (analog).\r
+ * PD6 - PIN6 (analog).\r
+ * PD7 - PIN7 (analog).\r
+ * PD8 - PIN8 (analog).\r
+ * PD9 - PIN9 (analog).\r
+ * PD10 - PIN10 (analog).\r
+ * PD11 - PIN11 (analog).\r
+ * PD12 - PIN12 (analog).\r
+ * PD13 - PIN13 (analog).\r
+ * PD14 - PIN14 (analog).\r
+ * PD15 - PIN15 (analog).\r
+ */\r
+#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN1) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN2) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN3) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN4) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN5) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN6) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN7) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN8) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN9) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN10) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN11) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN12) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN13) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN14) | \\r
+ PIN_MODE_ANALOG(GPIOD_PIN15))\r
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))\r
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN1) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN2) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN3) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN4) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN5) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN6) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN7) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN8) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN9) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN10) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN11) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN12) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN13) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN14) | \\r
+ PIN_OSPEED_HIGH(GPIOD_PIN15))\r
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN1) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN2) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN3) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN4) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN5) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN6) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN7) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN8) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN9) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN10) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN11) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN12) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN13) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN14) | \\r
+ PIN_PUPDR_FLOATING(GPIOD_PIN15))\r
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN1) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN13) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOD_PIN15))\r
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))\r
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))\r
+#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN1) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN2) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN3) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN4) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN5) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN6) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN7) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN8) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN9) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN10) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN11) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN12) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN13) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN14) | \\r
+ PIN_ASCR_DISABLED(GPIOD_PIN15))\r
+#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_PIN0) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN1) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN2) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN3) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN4) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN5) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN6) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN7) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN8) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN9) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN10) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN11) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN12) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN13) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN14) | \\r
+ PIN_LOCKR_DISABLED(GPIOD_PIN15))\r
+\r
+/*\r
+ * GPIOE setup:\r
+ *\r
+ * PE0 - PIN0 (analog).\r
+ * PE1 - PIN1 (analog).\r
+ * PE2 - PIN2 (analog).\r
+ * PE3 - PIN3 (analog).\r
+ * PE4 - PIN4 (analog).\r
+ * PE5 - PIN5 (analog).\r
+ * PE6 - PIN6 (analog).\r
+ * PE7 - PIN7 (analog).\r
+ * PE8 - PIN8 (analog).\r
+ * PE9 - PIN9 (analog).\r
+ * PE10 - PIN10 (analog).\r
+ * PE11 - PIN11 (analog).\r
+ * PE12 - PIN12 (analog).\r
+ * PE13 - PIN13 (analog).\r
+ * PE14 - PIN14 (analog).\r
+ * PE15 - PIN15 (analog).\r
+ */\r
+#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN1) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN2) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN3) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN4) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN5) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN6) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN7) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN8) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN9) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN10) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN11) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN12) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN13) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN14) | \\r
+ PIN_MODE_ANALOG(GPIOE_PIN15))\r
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))\r
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN1) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN2) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN3) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN4) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN5) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN6) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN7) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN8) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN9) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN10) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN11) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN12) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN13) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN14) | \\r
+ PIN_OSPEED_HIGH(GPIOE_PIN15))\r
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN1) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN2) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN3) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN4) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN5) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN6) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN7) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN8) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN9) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN10) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN11) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN12) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN13) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN14) | \\r
+ PIN_PUPDR_FLOATING(GPIOE_PIN15))\r
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN1) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN13) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOE_PIN15))\r
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN1, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN7, 0U))\r
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN13, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOE_PIN15, 0U))\r
+#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN1) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN2) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN3) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN4) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN5) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN6) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN7) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN8) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN9) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN10) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN11) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN12) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN13) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN14) | \\r
+ PIN_ASCR_DISABLED(GPIOE_PIN15))\r
+#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_PIN0) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN1) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN2) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN3) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN4) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN5) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN6) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN7) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN8) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN9) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN10) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN11) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN12) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN13) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN14) | \\r
+ PIN_LOCKR_DISABLED(GPIOE_PIN15))\r
+\r
+/*\r
+ * GPIOF setup:\r
+ *\r
+ * PF0 - PIN0 (analog).\r
+ * PF1 - PIN1 (analog).\r
+ * PF2 - PIN2 (analog).\r
+ * PF3 - PIN3 (analog).\r
+ * PF4 - PIN4 (analog).\r
+ * PF5 - PIN5 (analog).\r
+ * PF6 - PIN6 (analog).\r
+ * PF7 - PIN7 (analog).\r
+ * PF8 - PIN8 (analog).\r
+ * PF9 - PIN9 (analog).\r
+ * PF10 - PIN10 (analog).\r
+ * PF11 - PIN11 (analog).\r
+ * PF12 - PIN12 (analog).\r
+ * PF13 - PIN13 (analog).\r
+ * PF14 - PIN14 (analog).\r
+ * PF15 - PIN15 (analog).\r
+ */\r
+#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN1) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN2) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN3) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN4) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN5) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN6) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN7) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN8) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN9) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN10) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN11) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN12) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN13) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN14) | \\r
+ PIN_MODE_ANALOG(GPIOF_PIN15))\r
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))\r
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN1) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN2) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN3) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN4) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN5) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN6) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN7) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN8) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN9) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN10) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN11) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN12) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN13) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN14) | \\r
+ PIN_OSPEED_HIGH(GPIOF_PIN15))\r
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN1) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \\r
+ PIN_PUPDR_FLOATING(GPIOF_PIN15))\r
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN1) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN13) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOF_PIN15))\r
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN1, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN7, 0U))\r
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN13, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOF_PIN15, 0U))\r
+#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN1) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN2) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN3) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN4) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN5) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN6) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN7) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN8) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN9) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN10) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN11) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN12) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN13) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN14) | \\r
+ PIN_ASCR_DISABLED(GPIOF_PIN15))\r
+#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_PIN0) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN1) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN2) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN3) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN4) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN5) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN6) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN7) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN8) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN9) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN10) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN11) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN12) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN13) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN14) | \\r
+ PIN_LOCKR_DISABLED(GPIOF_PIN15))\r
+\r
+/*\r
+ * GPIOG setup:\r
+ *\r
+ * PG0 - PIN0 (analog).\r
+ * PG1 - PIN1 (analog).\r
+ * PG2 - PIN2 (analog).\r
+ * PG3 - PIN3 (analog).\r
+ * PG4 - PIN4 (analog).\r
+ * PG5 - PIN5 (analog).\r
+ * PG6 - PIN6 (analog).\r
+ * PG7 - PIN7 (analog).\r
+ * PG8 - PIN8 (analog).\r
+ * PG9 - PIN9 (analog).\r
+ * PG10 - PIN10 (analog).\r
+ * PG11 - PIN11 (analog).\r
+ * PG12 - PIN12 (analog).\r
+ * PG13 - PIN13 (analog).\r
+ * PG14 - PIN14 (analog).\r
+ * PG15 - PIN15 (analog).\r
+ */\r
+#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN1) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN2) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN3) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN4) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN5) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN6) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN7) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN8) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN9) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN10) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN11) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN12) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN13) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN14) | \\r
+ PIN_MODE_ANALOG(GPIOG_PIN15))\r
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))\r
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN6) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN7) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \\r
+ PIN_OSPEED_VERYLOW(GPIOG_PIN15))\r
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN1) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN2) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN3) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN4) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN5) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN6) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN7) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN9) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN12) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN13) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN14) | \\r
+ PIN_PUPDR_FLOATING(GPIOG_PIN15))\r
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN1) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN13) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOG_PIN15))\r
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN1, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN7, 0U))\r
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN13, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOG_PIN15, 0U))\r
+#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN1) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN2) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN3) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN4) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN5) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN6) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN7) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN8) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN9) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN10) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN11) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN12) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN13) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN14) | \\r
+ PIN_ASCR_DISABLED(GPIOG_PIN15))\r
+#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_PIN0) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN1) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN2) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN3) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN4) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN5) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN6) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN7) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN8) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN9) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN10) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN11) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN12) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN13) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN14) | \\r
+ PIN_LOCKR_DISABLED(GPIOG_PIN15))\r
+\r
+/*\r
+ * GPIOH setup:\r
+ *\r
+ * PH0 - OSC_IN (input floating).\r
+ * PH1 - OSC_OUT (input floating).\r
+ * PH2 - PIN2 (analog).\r
+ * PH3 - PIN3 (analog).\r
+ * PH4 - PIN4 (analog).\r
+ * PH5 - PIN5 (analog).\r
+ * PH6 - PIN6 (analog).\r
+ * PH7 - PIN7 (analog).\r
+ * PH8 - PIN8 (analog).\r
+ * PH9 - PIN9 (analog).\r
+ * PH10 - PIN10 (analog).\r
+ * PH11 - PIN11 (analog).\r
+ * PH12 - PIN12 (analog).\r
+ * PH13 - PIN13 (analog).\r
+ * PH14 - PIN14 (analog).\r
+ * PH15 - PIN15 (analog).\r
+ */\r
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \\r
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN2) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN3) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN4) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN5) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN6) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN7) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN8) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN9) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN10) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN11) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN12) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN13) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN14) | \\r
+ PIN_MODE_ANALOG(GPIOH_PIN15))\r
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \\r
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))\r
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \\r
+ PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \\r
+ PIN_OSPEED_VERYLOW(GPIOH_PIN15))\r
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN2) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN3) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN4) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN5) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN6) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN7) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN8) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN9) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN10) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN11) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN12) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN13) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN14) | \\r
+ PIN_PUPDR_FLOATING(GPIOH_PIN15))\r
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \\r
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN2) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN3) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN4) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN5) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN6) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN7) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN8) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN9) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN10) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN11) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN12) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN13) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN14) | \\r
+ PIN_ODR_HIGH(GPIOH_PIN15))\r
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN5, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN6, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN7, 0U))\r
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN9, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN10, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN11, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN12, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \\r
+ PIN_AFIO_AF(GPIOH_PIN15, 0U))\r
+#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_OSC_IN) | \\r
+ PIN_ASCR_DISABLED(GPIOH_OSC_OUT) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN2) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN3) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN4) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN5) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN6) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN7) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN8) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN9) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN10) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN11) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN12) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN13) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN14) | \\r
+ PIN_ASCR_DISABLED(GPIOH_PIN15))\r
+#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_OSC_IN) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_OSC_OUT) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN2) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN3) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN4) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN5) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN6) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN7) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN8) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN9) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN10) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN11) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN12) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN13) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN14) | \\r
+ PIN_LOCKR_DISABLED(GPIOH_PIN15))\r
+\r
+/*===========================================================================*/\r
+/* External declarations. */\r
+/*===========================================================================*/\r
+\r
+#if !defined(_FROM_ASM_)\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+ void boardInit(void);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* _FROM_ASM_ */\r
+\r
+#endif /* BOARD_H */\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/**\r
+ * @file rt/templates/chconf.h\r
+ * @brief Configuration file template.\r
+ * @details A copy of this file must be placed in each project directory, it\r
+ * contains the application specific kernel settings.\r
+ *\r
+ * @addtogroup config\r
+ * @details Kernel related settings and hooks.\r
+ * @{\r
+ */\r
+\r
+#ifndef CHCONF_H\r
+#define CHCONF_H\r
+\r
+#define _CHIBIOS_RT_CONF_\r
+#define _CHIBIOS_RT_CONF_VER_6_1_\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name System timers settings\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief System time counter resolution.\r
+ * @note Allowed values are 16 or 32 bits.\r
+ */\r
+#if !defined(CH_CFG_ST_RESOLUTION)\r
+#define CH_CFG_ST_RESOLUTION 32\r
+#endif\r
+\r
+/**\r
+ * @brief System tick frequency.\r
+ * @details Frequency of the system timer that drives the system ticks. This\r
+ * setting also defines the system tick time unit.\r
+ */\r
+#if !defined(CH_CFG_ST_FREQUENCY)\r
+#define CH_CFG_ST_FREQUENCY 10000\r
+#endif\r
+\r
+/**\r
+ * @brief Time intervals data size.\r
+ * @note Allowed values are 16, 32 or 64 bits.\r
+ */\r
+#if !defined(CH_CFG_INTERVALS_SIZE)\r
+#define CH_CFG_INTERVALS_SIZE 32\r
+#endif\r
+\r
+/**\r
+ * @brief Time types data size.\r
+ * @note Allowed values are 16 or 32 bits.\r
+ */\r
+#if !defined(CH_CFG_TIME_TYPES_SIZE)\r
+#define CH_CFG_TIME_TYPES_SIZE 32\r
+#endif\r
+\r
+/**\r
+ * @brief Time delta constant for the tick-less mode.\r
+ * @note If this value is zero then the system uses the classic\r
+ * periodic tick. This value represents the minimum number\r
+ * of ticks that is safe to specify in a timeout directive.\r
+ * The value one is not valid, timeouts are rounded up to\r
+ * this value.\r
+ */\r
+#if !defined(CH_CFG_ST_TIMEDELTA)\r
+#define CH_CFG_ST_TIMEDELTA 2\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Kernel parameters and options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Round robin interval.\r
+ * @details This constant is the number of system ticks allowed for the\r
+ * threads before preemption occurs. Setting this value to zero\r
+ * disables the preemption for threads with equal priority and the\r
+ * round robin becomes cooperative. Note that higher priority\r
+ * threads can still preempt, the kernel is always preemptive.\r
+ * @note Disabling the round robin preemption makes the kernel more compact\r
+ * and generally faster.\r
+ * @note The round robin preemption is not supported in tickless mode and\r
+ * must be set to zero in that case.\r
+ */\r
+#if !defined(CH_CFG_TIME_QUANTUM)\r
+#define CH_CFG_TIME_QUANTUM 0\r
+#endif\r
+\r
+/**\r
+ * @brief Idle thread automatic spawn suppression.\r
+ * @details When this option is activated the function @p chSysInit()\r
+ * does not spawn the idle thread. The application @p main()\r
+ * function becomes the idle thread and must implement an\r
+ * infinite loop.\r
+ */\r
+#if !defined(CH_CFG_NO_IDLE_THREAD)\r
+#define CH_CFG_NO_IDLE_THREAD FALSE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Performance options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief OS optimization.\r
+ * @details If enabled then time efficient rather than space efficient code\r
+ * is used when two possible implementations exist.\r
+ *\r
+ * @note This is not related to the compiler optimization options.\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_OPTIMIZE_SPEED)\r
+#define CH_CFG_OPTIMIZE_SPEED TRUE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Subsystem options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Time Measurement APIs.\r
+ * @details If enabled then the time measurement APIs are included in\r
+ * the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_TM)\r
+#define CH_CFG_USE_TM TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Threads registry APIs.\r
+ * @details If enabled then the registry APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_REGISTRY)\r
+#define CH_CFG_USE_REGISTRY TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Threads synchronization APIs.\r
+ * @details If enabled then the @p chThdWait() function is included in\r
+ * the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_WAITEXIT)\r
+#define CH_CFG_USE_WAITEXIT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Semaphores APIs.\r
+ * @details If enabled then the Semaphores APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_SEMAPHORES)\r
+#define CH_CFG_USE_SEMAPHORES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Semaphores queuing mode.\r
+ * @details If enabled then the threads are enqueued on semaphores by\r
+ * priority rather than in FIFO order.\r
+ *\r
+ * @note The default is @p FALSE. Enable this if you have special\r
+ * requirements.\r
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.\r
+ */\r
+#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)\r
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Mutexes APIs.\r
+ * @details If enabled then the mutexes APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_MUTEXES)\r
+#define CH_CFG_USE_MUTEXES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables recursive behavior on mutexes.\r
+ * @note Recursive mutexes are heavier and have an increased\r
+ * memory footprint.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ * @note Requires @p CH_CFG_USE_MUTEXES.\r
+ */\r
+#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)\r
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Conditional Variables APIs.\r
+ * @details If enabled then the conditional variables APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_MUTEXES.\r
+ */\r
+#if !defined(CH_CFG_USE_CONDVARS)\r
+#define CH_CFG_USE_CONDVARS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Conditional Variables APIs with timeout.\r
+ * @details If enabled then the conditional variables APIs with timeout\r
+ * specification are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_CONDVARS.\r
+ */\r
+#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)\r
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Events Flags APIs.\r
+ * @details If enabled then the event flags APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_EVENTS)\r
+#define CH_CFG_USE_EVENTS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Events Flags APIs with timeout.\r
+ * @details If enabled then the events APIs with timeout specification\r
+ * are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_EVENTS.\r
+ */\r
+#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)\r
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Synchronous Messages APIs.\r
+ * @details If enabled then the synchronous messages APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_MESSAGES)\r
+#define CH_CFG_USE_MESSAGES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Synchronous Messages queuing mode.\r
+ * @details If enabled then messages are served by priority rather than in\r
+ * FIFO order.\r
+ *\r
+ * @note The default is @p FALSE. Enable this if you have special\r
+ * requirements.\r
+ * @note Requires @p CH_CFG_USE_MESSAGES.\r
+ */\r
+#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)\r
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Dynamic Threads APIs.\r
+ * @details If enabled then the dynamic threads creation APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_WAITEXIT.\r
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.\r
+ */\r
+#if !defined(CH_CFG_USE_DYNAMIC)\r
+#define CH_CFG_USE_DYNAMIC TRUE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name OSLIB options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Mailboxes APIs.\r
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are\r
+ * included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.\r
+ */\r
+#if !defined(CH_CFG_USE_MAILBOXES)\r
+#define CH_CFG_USE_MAILBOXES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Core Memory Manager APIs.\r
+ * @details If enabled then the core memory manager APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_MEMCORE)\r
+#define CH_CFG_USE_MEMCORE TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Managed RAM size.\r
+ * @details Size of the RAM area to be managed by the OS. If set to zero\r
+ * then the whole available RAM is used. The core memory is made\r
+ * available to the heap allocator and/or can be used directly through\r
+ * the simplified core memory allocator.\r
+ *\r
+ * @note In order to let the OS manage the whole RAM the linker script must\r
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.\r
+ * @note Requires @p CH_CFG_USE_MEMCORE.\r
+ */\r
+#if !defined(CH_CFG_MEMCORE_SIZE)\r
+#define CH_CFG_MEMCORE_SIZE 0\r
+#endif\r
+\r
+/**\r
+ * @brief Heap Allocator APIs.\r
+ * @details If enabled then the memory heap allocator APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or\r
+ * @p CH_CFG_USE_SEMAPHORES.\r
+ * @note Mutexes are recommended.\r
+ */\r
+#if !defined(CH_CFG_USE_HEAP)\r
+#define CH_CFG_USE_HEAP TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Memory Pools Allocator APIs.\r
+ * @details If enabled then the memory pools allocator APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_MEMPOOLS)\r
+#define CH_CFG_USE_MEMPOOLS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Objects FIFOs APIs.\r
+ * @details If enabled then the objects FIFOs APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_OBJ_FIFOS)\r
+#define CH_CFG_USE_OBJ_FIFOS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Pipes APIs.\r
+ * @details If enabled then the pipes APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_PIPES)\r
+#define CH_CFG_USE_PIPES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Objects Caches APIs.\r
+ * @details If enabled then the objects caches APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_OBJ_CACHES)\r
+#define CH_CFG_USE_OBJ_CACHES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Delegate threads APIs.\r
+ * @details If enabled then the delegate threads APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_DELEGATES)\r
+#define CH_CFG_USE_DELEGATES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Jobs Queues APIs.\r
+ * @details If enabled then the jobs queues APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_CFG_USE_JOBS)\r
+#define CH_CFG_USE_JOBS TRUE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Objects factory options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Objects Factory APIs.\r
+ * @details If enabled then the objects factory APIs are included in the\r
+ * kernel.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_CFG_USE_FACTORY)\r
+#define CH_CFG_USE_FACTORY TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Maximum length for object names.\r
+ * @details If the specified length is zero then the name is stored by\r
+ * pointer but this could have unintended side effects.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)\r
+#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the registry of generic objects.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)\r
+#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables factory for generic buffers.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)\r
+#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables factory for semaphores.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_SEMAPHORES)\r
+#define CH_CFG_FACTORY_SEMAPHORES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables factory for mailboxes.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_MAILBOXES)\r
+#define CH_CFG_FACTORY_MAILBOXES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables factory for objects FIFOs.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)\r
+#define CH_CFG_FACTORY_OBJ_FIFOS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables factory for Pipes.\r
+ */\r
+#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)\r
+#define CH_CFG_FACTORY_PIPES TRUE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Debug options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Debug option, kernel statistics.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_STATISTICS)\r
+#define CH_DBG_STATISTICS FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, system state check.\r
+ * @details If enabled the correct call protocol for system APIs is checked\r
+ * at runtime.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK)\r
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, parameters checks.\r
+ * @details If enabled then the checks on the API functions input\r
+ * parameters are activated.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_ENABLE_CHECKS)\r
+#define CH_DBG_ENABLE_CHECKS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, consistency checks.\r
+ * @details If enabled then all the assertions in the kernel code are\r
+ * activated. This includes consistency checks inside the kernel,\r
+ * runtime anomalies and port-defined checks.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_ENABLE_ASSERTS)\r
+#define CH_DBG_ENABLE_ASSERTS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, trace buffer.\r
+ * @details If enabled then the trace buffer is activated.\r
+ *\r
+ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.\r
+ */\r
+#if !defined(CH_DBG_TRACE_MASK)\r
+#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_NONE\r
+#endif\r
+\r
+/**\r
+ * @brief Trace buffer entries.\r
+ * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is\r
+ * different from @p CH_DBG_TRACE_MASK_DISABLED.\r
+ */\r
+#if !defined(CH_DBG_TRACE_BUFFER_SIZE)\r
+#define CH_DBG_TRACE_BUFFER_SIZE 128\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, stack checks.\r
+ * @details If enabled then a runtime stack check is performed.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ * @note The stack check is performed in a architecture/port dependent way.\r
+ * It may not be implemented or some ports.\r
+ * @note The default failure mode is to halt the system with the global\r
+ * @p panic_msg variable set to @p NULL.\r
+ */\r
+#if !defined(CH_DBG_ENABLE_STACK_CHECK)\r
+#define CH_DBG_ENABLE_STACK_CHECK FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, stacks initialization.\r
+ * @details If enabled then the threads working area is filled with a byte\r
+ * value when a thread is created. This can be useful for the\r
+ * runtime measurement of the used stack.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_FILL_THREADS)\r
+#define CH_DBG_FILL_THREADS FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, threads profiling.\r
+ * @details If enabled then a field is added to the @p thread_t structure that\r
+ * counts the system ticks occurred while executing the thread.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ * @note This debug option is not currently compatible with the\r
+ * tickless mode.\r
+ */\r
+#if !defined(CH_DBG_THREADS_PROFILING)\r
+#define CH_DBG_THREADS_PROFILING FALSE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Kernel hooks\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief System structure extension.\r
+ * @details User fields added to the end of the @p ch_system_t structure.\r
+ */\r
+#define CH_CFG_SYSTEM_EXTRA_FIELDS \\r
+ /* Add threads custom fields here.*/\r
+\r
+/**\r
+ * @brief System initialization hook.\r
+ * @details User initialization code added to the @p chSysInit() function\r
+ * just before interrupts are enabled globally.\r
+ */\r
+#define CH_CFG_SYSTEM_INIT_HOOK() { \\r
+ /* Add threads initialization code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Threads descriptor structure extension.\r
+ * @details User fields added to the end of the @p thread_t structure.\r
+ */\r
+#define CH_CFG_THREAD_EXTRA_FIELDS \\r
+ /* Add threads custom fields here.*/\r
+\r
+/**\r
+ * @brief Threads initialization hook.\r
+ * @details User initialization code added to the @p _thread_init() function.\r
+ *\r
+ * @note It is invoked from within @p _thread_init() and implicitly from all\r
+ * the threads creation APIs.\r
+ */\r
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \\r
+ /* Add threads initialization code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Threads finalization hook.\r
+ * @details User finalization code added to the @p chThdExit() API.\r
+ */\r
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \\r
+ /* Add threads finalization code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Context switch hook.\r
+ * @details This hook is invoked just before switching between threads.\r
+ */\r
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \\r
+ /* Context switch code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief ISR enter hook.\r
+ */\r
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \\r
+ /* IRQ prologue code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief ISR exit hook.\r
+ */\r
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \\r
+ /* IRQ epilogue code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Idle thread enter hook.\r
+ * @note This hook is invoked within a critical zone, no OS functions\r
+ * should be invoked from here.\r
+ * @note This macro can be used to activate a power saving mode.\r
+ */\r
+#define CH_CFG_IDLE_ENTER_HOOK() { \\r
+ /* Idle-enter code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Idle thread leave hook.\r
+ * @note This hook is invoked within a critical zone, no OS functions\r
+ * should be invoked from here.\r
+ * @note This macro can be used to deactivate a power saving mode.\r
+ */\r
+#define CH_CFG_IDLE_LEAVE_HOOK() { \\r
+ /* Idle-leave code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Idle Loop hook.\r
+ * @details This hook is continuously invoked by the idle thread loop.\r
+ */\r
+#define CH_CFG_IDLE_LOOP_HOOK() { \\r
+ /* Idle loop code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief System tick event hook.\r
+ * @details This hook is invoked in the system tick handler immediately\r
+ * after processing the virtual timers queue.\r
+ */\r
+#define CH_CFG_SYSTEM_TICK_HOOK() { \\r
+ /* System tick event code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief System halt hook.\r
+ * @details This hook is invoked in case to a system halting error before\r
+ * the system is halted.\r
+ */\r
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \\r
+ /* System halt code here.*/ \\r
+}\r
+\r
+/**\r
+ * @brief Trace hook.\r
+ * @details This hook is invoked each time a new record is written in the\r
+ * trace buffer.\r
+ */\r
+#define CH_CFG_TRACE_HOOK(tep) { \\r
+ /* Trace code here.*/ \\r
+}\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/* Port-specific settings (override port settings defaulted in chcore.h). */\r
+/*===========================================================================*/\r
+\r
+#endif /* CHCONF_H */\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/**\r
+ * @file templates/halconf.h\r
+ * @brief HAL configuration header.\r
+ * @details HAL configuration file, this file allows to enable or disable the\r
+ * various device drivers from your application. You may also use\r
+ * this file in order to override the device drivers default settings.\r
+ *\r
+ * @addtogroup HAL_CONF\r
+ * @{\r
+ */\r
+\r
+#ifndef HALCONF_H\r
+#define HALCONF_H\r
+\r
+#define _CHIBIOS_HAL_CONF_\r
+#define _CHIBIOS_HAL_CONF_VER_7_1_\r
+\r
+#include "mcuconf.h"\r
+\r
+/**\r
+ * @brief Enables the PAL subsystem.\r
+ */\r
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)\r
+#define HAL_USE_PAL TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the ADC subsystem.\r
+ */\r
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)\r
+#define HAL_USE_ADC TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the CAN subsystem.\r
+ */\r
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)\r
+#define HAL_USE_CAN FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the cryptographic subsystem.\r
+ */\r
+#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)\r
+#define HAL_USE_CRY FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the DAC subsystem.\r
+ */\r
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)\r
+#define HAL_USE_DAC TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the EFlash subsystem.\r
+ */\r
+#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)\r
+#define HAL_USE_EFL FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the GPT subsystem.\r
+ */\r
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)\r
+#define HAL_USE_GPT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the I2C subsystem.\r
+ */\r
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)\r
+#define HAL_USE_I2C FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the I2S subsystem.\r
+ */\r
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)\r
+#define HAL_USE_I2S FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the ICU subsystem.\r
+ */\r
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)\r
+#define HAL_USE_ICU FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the MAC subsystem.\r
+ */\r
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)\r
+#define HAL_USE_MAC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the MMC_SPI subsystem.\r
+ */\r
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)\r
+#define HAL_USE_MMC_SPI FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the PWM subsystem.\r
+ */\r
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)\r
+#define HAL_USE_PWM FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the RTC subsystem.\r
+ */\r
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)\r
+#define HAL_USE_RTC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SDC subsystem.\r
+ */\r
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)\r
+#define HAL_USE_SDC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SERIAL subsystem.\r
+ */\r
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)\r
+#define HAL_USE_SERIAL FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SERIAL over USB subsystem.\r
+ */\r
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)\r
+#define HAL_USE_SERIAL_USB TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SIO subsystem.\r
+ */\r
+#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)\r
+#define HAL_USE_SIO FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SPI subsystem.\r
+ */\r
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)\r
+#define HAL_USE_SPI FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the TRNG subsystem.\r
+ */\r
+#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)\r
+#define HAL_USE_TRNG FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the UART subsystem.\r
+ */\r
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)\r
+#define HAL_USE_UART FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the USB subsystem.\r
+ */\r
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)\r
+#define HAL_USE_USB TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the WDG subsystem.\r
+ */\r
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)\r
+#define HAL_USE_WDG FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the WSPI subsystem.\r
+ */\r
+#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)\r
+#define HAL_USE_WSPI FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* PAL driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)\r
+#define PAL_USE_CALLBACKS FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)\r
+#define PAL_USE_WAIT FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* ADC driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)\r
+#define ADC_USE_WAIT FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define ADC_USE_MUTUAL_EXCLUSION FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* CAN driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Sleep mode related APIs inclusion switch.\r
+ */\r
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)\r
+#define CAN_USE_SLEEP_MODE TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enforces the driver to use direct callbacks rather than OSAL events.\r
+ */\r
+#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)\r
+#define CAN_ENFORCE_USE_CALLBACKS FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* CRY driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables the SW fall-back of the cryptographic driver.\r
+ * @details When enabled, this option, activates a fall-back software\r
+ * implementation for algorithms not supported by the underlying\r
+ * hardware.\r
+ * @note Fall-back implementations may not be present for all algorithms.\r
+ */\r
+#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)\r
+#define HAL_CRY_USE_FALLBACK FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Makes the driver forcibly use the fall-back implementations.\r
+ */\r
+#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)\r
+#define HAL_CRY_ENFORCE_FALLBACK FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* DAC driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)\r
+#define DAC_USE_WAIT FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define DAC_USE_MUTUAL_EXCLUSION FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* I2C driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables the mutual exclusion APIs on the I2C bus.\r
+ */\r
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define I2C_USE_MUTUAL_EXCLUSION TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* MAC driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables the zero-copy API.\r
+ */\r
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)\r
+#define MAC_USE_ZERO_COPY FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables an event sources for incoming packets.\r
+ */\r
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)\r
+#define MAC_USE_EVENTS TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* MMC_SPI driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Delays insertions.\r
+ * @details If enabled this options inserts delays into the MMC waiting\r
+ * routines releasing some extra CPU time for the threads with\r
+ * lower priority, this may slow down the driver a bit however.\r
+ * This option is recommended also if the SPI driver does not\r
+ * use a DMA channel and heavily loads the CPU.\r
+ */\r
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)\r
+#define MMC_NICE_WAITING TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* SDC driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Number of initialization attempts before rejecting the card.\r
+ * @note Attempts are performed at 10mS intervals.\r
+ */\r
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)\r
+#define SDC_INIT_RETRY 100\r
+#endif\r
+\r
+/**\r
+ * @brief Include support for MMC cards.\r
+ * @note MMC support is not yet implemented so this option must be kept\r
+ * at @p FALSE.\r
+ */\r
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)\r
+#define SDC_MMC_SUPPORT FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Delays insertions.\r
+ * @details If enabled this options inserts delays into the MMC waiting\r
+ * routines releasing some extra CPU time for the threads with\r
+ * lower priority, this may slow down the driver a bit however.\r
+ */\r
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)\r
+#define SDC_NICE_WAITING TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief OCR initialization constant for V20 cards.\r
+ */\r
+#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)\r
+#define SDC_INIT_OCR_V20 0x50FF8000U\r
+#endif\r
+\r
+/**\r
+ * @brief OCR initialization constant for non-V20 cards.\r
+ */\r
+#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)\r
+#define SDC_INIT_OCR 0x80100000U\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* SERIAL driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Default bit rate.\r
+ * @details Configuration parameter, this is the baud rate selected for the\r
+ * default configuration.\r
+ */\r
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)\r
+#define SERIAL_DEFAULT_BITRATE 38400\r
+#endif\r
+\r
+/**\r
+ * @brief Serial buffers size.\r
+ * @details Configuration parameter, you can change the depth of the queue\r
+ * buffers depending on the requirements of your application.\r
+ * @note The default is 16 bytes for both the transmission and receive\r
+ * buffers.\r
+ */\r
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)\r
+#define SERIAL_BUFFERS_SIZE 16\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* SERIAL_USB driver related setting. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Serial over USB buffers size.\r
+ * @details Configuration parameter, the buffer size must be a multiple of\r
+ * the USB data endpoint maximum packet size.\r
+ * @note The default is 256 bytes for both the transmission and receive\r
+ * buffers.\r
+ */\r
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)\r
+#define SERIAL_USB_BUFFERS_SIZE 256\r
+#endif\r
+\r
+/**\r
+ * @brief Serial over USB number of buffers.\r
+ * @note The default is 2 buffers.\r
+ */\r
+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)\r
+#define SERIAL_USB_BUFFERS_NUMBER 2\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* SPI driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)\r
+#define SPI_USE_WAIT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables circular transfers APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)\r
+#define SPI_USE_CIRCULAR FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define SPI_USE_MUTUAL_EXCLUSION TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Handling method for SPI CS line.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)\r
+#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* UART driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)\r
+#define UART_USE_WAIT FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define UART_USE_MUTUAL_EXCLUSION FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* USB driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)\r
+#define USB_USE_WAIT FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* WSPI driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)\r
+#define WSPI_USE_WAIT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define WSPI_USE_MUTUAL_EXCLUSION TRUE\r
+#endif\r
+\r
+#endif /* HALCONF_H */\r
+\r
+/** @} */\r
--- /dev/null
+#if defined(TARGET_PLATFORM_L4)\r
+#include "mcuconf_l4.h"\r
+#elif defined(TARGET_PLATFORM_H7)\r
+#include "mcuconf_h7.h"\r
+#elif defined(TARGET_PLATFORM_G4)\r
+#include "mcuconf_g4.h"\r
+#endif\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+#ifndef MCUCONF_H\r
+#define MCUCONF_H\r
+\r
+/*\r
+ * STM32H7xx drivers configuration.\r
+ * The following settings override the default settings present in\r
+ * the various device driver implementation headers.\r
+ * Note that the settings for each driver only have effect if the whole\r
+ * driver is enabled in halconf.h.\r
+ *\r
+ * IRQ priorities:\r
+ * 15...0 Lowest...Highest.\r
+ *\r
+ * DMA priorities:\r
+ * 0...3 Lowest...Highest.\r
+ */\r
+\r
+#define STM32H7xx_MCUCONF\r
+#define STM32H723_MCUCONF\r
+#define STM32H725_MCUCONF\r
+//#define STM32H743_MCUCONF\r
+\r
+/*\r
+ * General settings.\r
+ */\r
+#define STM32_NO_INIT FALSE\r
+#define STM32_TARGET_CORE 1\r
+\r
+/*\r
+ * Memory attributes settings.\r
+ */\r
+#define STM32_NOCACHE_MPU_REGION MPU_REGION_1\r
+#define STM32_NOCACHE_SRAM1_SRAM2 FALSE\r
+#define STM32_NOCACHE_SRAM3 FALSE\r
+#define STM32_NOCACHE_ALLSRAM TRUE\r
+\r
+/*\r
+ * PWR system settings.\r
+ * Reading STM32 Reference Manual is required, settings in PWR_CR3 are\r
+ * very critical.\r
+ * Register constants are taken from the ST header.\r
+ */\r
+#define STM32_VOS STM32_VOS_SCALE1\r
+#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)\r
+#define STM32_PWR_CR2 (PWR_CR2_BREN)\r
+#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)\r
+#define STM32_PWR_CPUCR 0\r
+\r
+/*\r
+ * Clock tree static settings.\r
+ * Reading STM32 Reference Manual is required.\r
+ */\r
+#define STM32_HSI_ENABLED TRUE\r
+#define STM32_LSI_ENABLED TRUE\r
+#define STM32_CSI_ENABLED FALSE\r
+#define STM32_HSI48_ENABLED TRUE\r
+#define STM32_HSE_ENABLED FALSE\r
+#define STM32_LSE_ENABLED FALSE\r
+#define STM32_HSIDIV STM32_HSIDIV_DIV8 // HSI = 8MHz\r
+\r
+/*\r
+ * PLLs static settings.\r
+ * Reading STM32 Reference Manual is required.\r
+ */\r
+#define STM32_PLLSRC STM32_PLLSRC_HSI_CK\r
+#define STM32_PLLCFGR_MASK ~0\r
+#define STM32_PLL1_ENABLED TRUE\r
+#define STM32_PLL1_P_ENABLED TRUE\r
+#define STM32_PLL1_Q_ENABLED FALSE\r
+#define STM32_PLL1_R_ENABLED FALSE\r
+#define STM32_PLL1_DIVM_VALUE 4 // 8 / 4 = 2MHz\r
+#define STM32_PLL1_DIVN_VALUE 240 // = 2 * 240\r
+#define STM32_PLL1_FRACN_VALUE 0\r
+#define STM32_PLL1_DIVP_VALUE 1 // = 480MHz\r
+#define STM32_PLL1_DIVQ_VALUE 16\r
+#define STM32_PLL1_DIVR_VALUE 8\r
+#define STM32_PLL2_ENABLED TRUE // PLL2 adjusted by adc.cpp\r
+#define STM32_PLL2_P_ENABLED TRUE\r
+#define STM32_PLL2_Q_ENABLED FALSE\r
+#define STM32_PLL2_R_ENABLED FALSE\r
+#define STM32_PLL2_DIVM_VALUE 4\r
+#define STM32_PLL2_DIVN_VALUE 80\r
+#define STM32_PLL2_FRACN_VALUE 0\r
+#define STM32_PLL2_DIVP_VALUE 20\r
+#define STM32_PLL2_DIVQ_VALUE 8\r
+#define STM32_PLL2_DIVR_VALUE 8\r
+#define STM32_PLL3_ENABLED FALSE\r
+#define STM32_PLL3_P_ENABLED FALSE\r
+#define STM32_PLL3_Q_ENABLED FALSE\r
+#define STM32_PLL3_R_ENABLED FALSE\r
+#define STM32_PLL3_DIVM_VALUE 4\r
+#define STM32_PLL3_DIVN_VALUE 400\r
+#define STM32_PLL3_FRACN_VALUE 0\r
+#define STM32_PLL3_DIVP_VALUE 8\r
+#define STM32_PLL3_DIVQ_VALUE 8\r
+#define STM32_PLL3_DIVR_VALUE 8\r
+\r
+/*\r
+ * Core clocks dynamic settings (can be changed at runtime).\r
+ * Reading STM32 Reference Manual is required.\r
+ */\r
+#define STM32_SW STM32_SW_PLL1_P_CK\r
+#define STM32_RTCSEL STM32_RTCSEL_LSI_CK\r
+#define STM32_D1CPRE STM32_D1CPRE_DIV1\r
+#define STM32_D1HPRE STM32_D1HPRE_DIV2 // /2 = 240MHz\r
+#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2\r
+#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2\r
+#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2\r
+#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2\r
+\r
+/*\r
+ * Peripherals clocks static settings.\r
+ * Reading STM32 Reference Manual is required.\r
+ */\r
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK\r
+#define STM32_MCO1PRE_VALUE 4\r
+#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK\r
+#define STM32_MCO2PRE_VALUE 4\r
+#define STM32_TIMPRE_ENABLE TRUE\r
+#define STM32_HRTIMSEL 0\r
+#define STM32_STOPKERWUCK 0\r
+#define STM32_STOPWUCK 0\r
+#define STM32_RTCPRE_VALUE 8\r
+#define STM32_CKPERSEL STM32_CKPERSEL_HSI_CK\r
+#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK\r
+//#define STM32_OCTOSPISEL STM32_OCTOSPISEL_HCLK\r
+//#define STM32_FMCSEL STM32_OCTOSPISEL_HCLK\r
+#define STM32_SWPSEL STM32_SWPSEL_PCLK1\r
+#define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK\r
+#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2\r
+#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK\r
+#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2\r
+#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK\r
+//#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK\r
+#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK\r
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1\r
+#define STM32_CECSEL STM32_CECSEL_LSE_CK\r
+#define STM32_USBSEL STM32_USBSEL_HSI48_CK\r
+#define STM32_I2C1235SEL STM32_I2C1235SEL_PCLK1\r
+#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK\r
+#define STM32_USART16910SEL STM32_USART16910SEL_PCLK2\r
+#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1\r
+#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4\r
+#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK\r
+#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK\r
+#define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK\r
+#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4\r
+#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4\r
+#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4\r
+#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4\r
+\r
+/*\r
+ * IRQ system settings.\r
+ */\r
+#define STM32_IRQ_EXTI0_PRIORITY 6\r
+#define STM32_IRQ_EXTI1_PRIORITY 6\r
+#define STM32_IRQ_EXTI2_PRIORITY 6\r
+#define STM32_IRQ_EXTI3_PRIORITY 6\r
+#define STM32_IRQ_EXTI4_PRIORITY 6\r
+#define STM32_IRQ_EXTI5_9_PRIORITY 6\r
+#define STM32_IRQ_EXTI10_15_PRIORITY 6\r
+#define STM32_IRQ_EXTI16_PRIORITY 6\r
+#define STM32_IRQ_EXTI17_PRIORITY 6\r
+#define STM32_IRQ_EXTI18_PRIORITY 6\r
+#define STM32_IRQ_EXTI19_PRIORITY 6\r
+#define STM32_IRQ_EXTI20_21_PRIORITY 6\r
+\r
+#define STM32_IRQ_FDCAN1_PRIORITY 10\r
+#define STM32_IRQ_FDCAN2_PRIORITY 10\r
+\r
+#define STM32_IRQ_MDMA_PRIORITY 9\r
+\r
+#define STM32_IRQ_QUADSPI1_PRIORITY 10\r
+\r
+#define STM32_IRQ_SDMMC1_PRIORITY 9\r
+#define STM32_IRQ_SDMMC2_PRIORITY 9\r
+\r
+#define STM32_IRQ_TIM1_UP_PRIORITY 7\r
+#define STM32_IRQ_TIM1_CC_PRIORITY 7\r
+#define STM32_IRQ_TIM2_PRIORITY 7\r
+#define STM32_IRQ_TIM3_PRIORITY 7\r
+#define STM32_IRQ_TIM4_PRIORITY 7\r
+#define STM32_IRQ_TIM5_PRIORITY 7\r
+#define STM32_IRQ_TIM6_PRIORITY 7\r
+#define STM32_IRQ_TIM7_PRIORITY 7\r
+#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7\r
+#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7\r
+#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7\r
+#define STM32_IRQ_TIM8_CC_PRIORITY 7\r
+#define STM32_IRQ_TIM15_PRIORITY 7\r
+#define STM32_IRQ_TIM16_PRIORITY 7\r
+#define STM32_IRQ_TIM17_PRIORITY 7\r
+\r
+#define STM32_IRQ_USART1_PRIORITY 12\r
+#define STM32_IRQ_USART2_PRIORITY 12\r
+#define STM32_IRQ_USART3_PRIORITY 12\r
+#define STM32_IRQ_UART4_PRIORITY 12\r
+#define STM32_IRQ_UART5_PRIORITY 12\r
+#define STM32_IRQ_USART6_PRIORITY 12\r
+#define STM32_IRQ_UART7_PRIORITY 12\r
+#define STM32_IRQ_UART8_PRIORITY 12\r
+#define STM32_IRQ_LPUART1_PRIORITY 12\r
+\r
+/*\r
+ * ADC driver system settings.\r
+ */\r
+#define STM32_ADC_DUAL_MODE FALSE\r
+#define STM32_ADC_COMPACT_SAMPLES FALSE\r
+#define STM32_ADC_USE_ADC12 FALSE\r
+#define STM32_ADC_USE_ADC3 TRUE\r
+#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY\r
+#define STM32_ADC_ADC12_DMA_PRIORITY 2\r
+#define STM32_ADC_ADC3_DMA_PRIORITY 2\r
+#define STM32_ADC_ADC12_IRQ_PRIORITY 5\r
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5\r
+#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4\r
+#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_ADCCK\r
+#define STM32_ADC_ADC3_PRESC (5 << ADC_CCR_PRESC_Pos) // /10\r
+\r
+/*\r
+ * CAN driver system settings.\r
+ */\r
+#define STM32_CAN_USE_FDCAN1 FALSE\r
+#define STM32_CAN_USE_FDCAN2 FALSE\r
+\r
+/*\r
+ * DAC driver system settings.\r
+ */\r
+#define STM32_DAC_DUAL_MODE FALSE\r
+#define STM32_DAC_USE_DAC1_CH1 TRUE\r
+#define STM32_DAC_USE_DAC1_CH2 TRUE\r
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10\r
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10\r
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2\r
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2\r
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+\r
+/*\r
+ * GPT driver system settings.\r
+ */\r
+#define STM32_GPT_USE_TIM1 FALSE\r
+#define STM32_GPT_USE_TIM2 FALSE\r
+#define STM32_GPT_USE_TIM3 FALSE\r
+#define STM32_GPT_USE_TIM4 FALSE\r
+#define STM32_GPT_USE_TIM5 FALSE\r
+#define STM32_GPT_USE_TIM6 TRUE\r
+#define STM32_GPT_USE_TIM7 FALSE\r
+#define STM32_GPT_USE_TIM8 FALSE\r
+#define STM32_GPT_USE_TIM12 FALSE\r
+#define STM32_GPT_USE_TIM13 FALSE\r
+#define STM32_GPT_USE_TIM14 FALSE\r
+#define STM32_GPT_USE_TIM15 FALSE\r
+#define STM32_GPT_USE_TIM16 FALSE\r
+#define STM32_GPT_USE_TIM17 FALSE\r
+\r
+/*\r
+ * I2C driver system settings.\r
+ */\r
+#define STM32_I2C_USE_I2C1 FALSE\r
+#define STM32_I2C_USE_I2C2 FALSE\r
+#define STM32_I2C_USE_I2C3 FALSE\r
+#define STM32_I2C_USE_I2C4 FALSE\r
+#define STM32_I2C_BUSY_TIMEOUT 50\r
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY\r
+#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY\r
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5\r
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5\r
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5\r
+#define STM32_I2C_I2C4_IRQ_PRIORITY 5\r
+#define STM32_I2C_I2C1_DMA_PRIORITY 3\r
+#define STM32_I2C_I2C2_DMA_PRIORITY 3\r
+#define STM32_I2C_I2C3_DMA_PRIORITY 3\r
+#define STM32_I2C_I2C4_DMA_PRIORITY 3\r
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")\r
+\r
+/*\r
+ * ICU driver system settings.\r
+ */\r
+#define STM32_ICU_USE_TIM1 FALSE\r
+#define STM32_ICU_USE_TIM2 FALSE\r
+#define STM32_ICU_USE_TIM3 FALSE\r
+#define STM32_ICU_USE_TIM4 FALSE\r
+#define STM32_ICU_USE_TIM5 FALSE\r
+#define STM32_ICU_USE_TIM8 FALSE\r
+#define STM32_ICU_USE_TIM12 FALSE\r
+#define STM32_ICU_USE_TIM13 FALSE\r
+#define STM32_ICU_USE_TIM14 FALSE\r
+#define STM32_ICU_USE_TIM15 FALSE\r
+#define STM32_ICU_USE_TIM16 FALSE\r
+#define STM32_ICU_USE_TIM17 FALSE\r
+\r
+/*\r
+ * MAC driver system settings.\r
+ */\r
+#define STM32_MAC_TRANSMIT_BUFFERS 2\r
+#define STM32_MAC_RECEIVE_BUFFERS 4\r
+#define STM32_MAC_BUFFERS_SIZE 1522\r
+#define STM32_MAC_PHY_TIMEOUT 100\r
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE\r
+#define STM32_MAC_ETH1_IRQ_PRIORITY 13\r
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0\r
+\r
+/*\r
+ * PWM driver system settings.\r
+ */\r
+#define STM32_PWM_USE_ADVANCED FALSE\r
+#define STM32_PWM_USE_TIM1 FALSE\r
+#define STM32_PWM_USE_TIM2 FALSE\r
+#define STM32_PWM_USE_TIM3 FALSE\r
+#define STM32_PWM_USE_TIM4 FALSE\r
+#define STM32_PWM_USE_TIM5 FALSE\r
+#define STM32_PWM_USE_TIM8 FALSE\r
+#define STM32_PWM_USE_TIM12 FALSE\r
+#define STM32_PWM_USE_TIM13 FALSE\r
+#define STM32_PWM_USE_TIM14 FALSE\r
+#define STM32_PWM_USE_TIM15 FALSE\r
+#define STM32_PWM_USE_TIM16 FALSE\r
+#define STM32_PWM_USE_TIM17 FALSE\r
+\r
+/*\r
+ * RTC driver system settings.\r
+ */\r
+#define STM32_RTC_PRESA_VALUE 32\r
+#define STM32_RTC_PRESS_VALUE 1024\r
+#define STM32_RTC_CR_INIT 0\r
+#define STM32_RTC_TAMPCR_INIT 0\r
+\r
+/*\r
+ * SDC driver system settings.\r
+ */\r
+#define STM32_SDC_USE_SDMMC1 FALSE\r
+#define STM32_SDC_USE_SDMMC2 FALSE\r
+#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE\r
+#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000000\r
+#define STM32_SDC_SDMMC_READ_TIMEOUT 1000000\r
+#define STM32_SDC_SDMMC_CLOCK_DELAY 10\r
+#define STM32_SDC_SDMMC_PWRSAV TRUE\r
+\r
+/*\r
+ * SERIAL driver system settings.\r
+ */\r
+#define STM32_SERIAL_USE_USART1 FALSE\r
+#define STM32_SERIAL_USE_USART2 FALSE\r
+#define STM32_SERIAL_USE_USART3 FALSE\r
+#define STM32_SERIAL_USE_UART4 FALSE\r
+#define STM32_SERIAL_USE_UART5 FALSE\r
+#define STM32_SERIAL_USE_USART6 FALSE\r
+#define STM32_SERIAL_USE_UART7 FALSE\r
+#define STM32_SERIAL_USE_UART8 FALSE\r
+\r
+/*\r
+ * SPI driver system settings.\r
+ */\r
+#define STM32_SPI_USE_SPI1 FALSE\r
+#define STM32_SPI_USE_SPI2 FALSE\r
+#define STM32_SPI_USE_SPI3 FALSE\r
+#define STM32_SPI_USE_SPI4 FALSE\r
+#define STM32_SPI_USE_SPI5 FALSE\r
+#define STM32_SPI_USE_SPI6 FALSE\r
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY\r
+#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY\r
+#define STM32_SPI_SPI1_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI2_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI3_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI4_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI5_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI6_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10\r
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10\r
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10\r
+#define STM32_SPI_SPI4_IRQ_PRIORITY 10\r
+#define STM32_SPI_SPI5_IRQ_PRIORITY 10\r
+#define STM32_SPI_SPI6_IRQ_PRIORITY 10\r
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")\r
+\r
+/*\r
+ * ST driver system settings.\r
+ */\r
+#define STM32_ST_IRQ_PRIORITY 8\r
+#define STM32_ST_USE_TIMER 2\r
+\r
+/*\r
+ * TRNG driver system settings.\r
+ */\r
+#define STM32_TRNG_USE_RNG1 FALSE\r
+\r
+/*\r
+ * UART driver system settings.\r
+ */\r
+#define STM32_UART_USE_USART1 FALSE\r
+#define STM32_UART_USE_USART2 FALSE\r
+#define STM32_UART_USE_USART3 FALSE\r
+#define STM32_UART_USE_UART4 FALSE\r
+#define STM32_UART_USE_UART5 FALSE\r
+#define STM32_UART_USE_USART6 FALSE\r
+#define STM32_UART_USE_UART7 FALSE\r
+#define STM32_UART_USE_UART8 FALSE\r
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY\r
+#define STM32_UART_USART1_DMA_PRIORITY 0\r
+#define STM32_UART_USART2_DMA_PRIORITY 0\r
+#define STM32_UART_USART3_DMA_PRIORITY 0\r
+#define STM32_UART_UART4_DMA_PRIORITY 0\r
+#define STM32_UART_UART5_DMA_PRIORITY 0\r
+#define STM32_UART_USART6_DMA_PRIORITY 0\r
+#define STM32_UART_UART7_DMA_PRIORITY 0\r
+#define STM32_UART_UART8_DMA_PRIORITY 0\r
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")\r
+\r
+/*\r
+ * USB driver system settings.\r
+ */\r
+#define STM32_USB_USE_OTG1 FALSE\r
+#define STM32_USB_USE_OTG2 TRUE\r
+#define STM32_USB_OTG1_IRQ_PRIORITY 14\r
+#define STM32_USB_OTG2_IRQ_PRIORITY 14\r
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512\r
+#define STM32_USB_OTG2_RX_FIFO_SIZE 1024\r
+#define STM32_USB_HOST_WAKEUP_DURATION 2\r
+\r
+/*\r
+ * WDG driver system settings.\r
+ */\r
+#define STM32_WDG_USE_IWDG FALSE\r
+\r
+/*\r
+ * WSPI driver system settings.\r
+ */\r
+#define STM32_WSPI_USE_QUADSPI1 FALSE\r
+#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1\r
+#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY\r
+#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1\r
+#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")\r
+\r
+#endif /* MCUCONF_H */\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/*\r
+ * STM32L4xx drivers configuration.\r
+ * The following settings override the default settings present in\r
+ * the various device driver implementation headers.\r
+ * Note that the settings for each driver only have effect if the whole\r
+ * driver is enabled in halconf.h.\r
+ *\r
+ * IRQ priorities:\r
+ * 15...0 Lowest...Highest.\r
+ *\r
+ * DMA priorities:\r
+ * 0...3 Lowest...Highest.\r
+ */\r
+\r
+#ifndef MCUCONF_H\r
+#define MCUCONF_H\r
+\r
+#define STM32L4xx_MCUCONF\r
+#define STM32L476_MCUCONF\r
+//#define STM32L432_MCUCONF\r
+\r
+/*\r
+ * HAL driver system settings.\r
+ */\r
+#define STM32_NO_INIT FALSE\r
+#define STM32_VOS STM32_VOS_RANGE1\r
+#define STM32_PVD_ENABLE FALSE\r
+#define STM32_PLS STM32_PLS_LEV0\r
+#define STM32_HSI16_ENABLED FALSE\r
+#define STM32_LSI_ENABLED TRUE\r
+#define STM32_HSE_ENABLED FALSE\r
+#define STM32_LSE_ENABLED FALSE\r
+#define STM32_MSIPLL_ENABLED FALSE\r
+#define STM32_MSIRANGE STM32_MSIRANGE_8M\r
+#define STM32_MSISRANGE STM32_MSISRANGE_4M\r
+#define STM32_SW STM32_SW_PLL\r
+#define STM32_PLLSRC STM32_PLLSRC_MSI\r
+#define STM32_PLLM_VALUE 2\r
+#define STM32_PLLN_VALUE 72\r
+#define STM32_PLLP_VALUE 7\r
+#define STM32_PLLQ_VALUE 6\r
+#define STM32_PLLR_VALUE 4\r
+#define STM32_HPRE STM32_HPRE_DIV1\r
+#define STM32_PPRE1 STM32_PPRE1_DIV1\r
+#define STM32_PPRE2 STM32_PPRE2_DIV1\r
+#define STM32_STOPWUCK STM32_STOPWUCK_MSI\r
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK\r
+#define STM32_MCOPRE STM32_MCOPRE_DIV1\r
+#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK\r
+#define STM32_PLLSAI1N_VALUE 24\r
+#define STM32_PLLSAI1P_VALUE 7\r
+#define STM32_PLLSAI1Q_VALUE 2\r
+#define STM32_PLLSAI1R_VALUE 4\r
+#define STM32_PLLSAI2N_VALUE 24\r
+#define STM32_PLLSAI2P_VALUE 7\r
+#define STM32_PLLSAI2R_VALUE 8\r
+\r
+/*\r
+ * Peripherals clock sources.\r
+ */\r
+#define STM32_USART1SEL STM32_USART1SEL_SYSCLK\r
+#define STM32_USART2SEL STM32_USART2SEL_SYSCLK\r
+#define STM32_USART3SEL STM32_USART3SEL_SYSCLK\r
+#define STM32_UART4SEL STM32_UART4SEL_SYSCLK\r
+#define STM32_UART5SEL STM32_UART5SEL_SYSCLK\r
+#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK\r
+#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK\r
+#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK\r
+#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK\r
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1\r
+#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1\r
+#define STM32_SAI1SEL STM32_SAI1SEL_OFF\r
+#define STM32_SAI2SEL STM32_SAI2SEL_OFF\r
+#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1\r
+#define STM32_ADCSEL STM32_ADCSEL_PLLSAI2\r
+#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1\r
+#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2\r
+#define STM32_RTCSEL STM32_RTCSEL_LSI\r
+\r
+/*\r
+ * IRQ system settings.\r
+ */\r
+#define STM32_IRQ_EXTI0_PRIORITY 6\r
+#define STM32_IRQ_EXTI1_PRIORITY 6\r
+#define STM32_IRQ_EXTI2_PRIORITY 6\r
+#define STM32_IRQ_EXTI3_PRIORITY 6\r
+#define STM32_IRQ_EXTI4_PRIORITY 6\r
+#define STM32_IRQ_EXTI5_9_PRIORITY 6\r
+#define STM32_IRQ_EXTI10_15_PRIORITY 6\r
+#define STM32_IRQ_EXTI1635_38_PRIORITY 6\r
+#define STM32_IRQ_EXTI18_PRIORITY 6\r
+#define STM32_IRQ_EXTI19_PRIORITY 6\r
+#define STM32_IRQ_EXTI20_PRIORITY 6\r
+#define STM32_IRQ_EXTI21_22_PRIORITY 15\r
+\r
+#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7\r
+#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7\r
+#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7\r
+#define STM32_IRQ_TIM1_CC_PRIORITY 7\r
+#define STM32_IRQ_TIM2_PRIORITY 7\r
+#define STM32_IRQ_TIM3_PRIORITY 7\r
+#define STM32_IRQ_TIM4_PRIORITY 7\r
+#define STM32_IRQ_TIM5_PRIORITY 7\r
+#define STM32_IRQ_TIM6_PRIORITY 7\r
+#define STM32_IRQ_TIM7_PRIORITY 7\r
+#define STM32_IRQ_TIM8_UP_PRIORITY 7\r
+#define STM32_IRQ_TIM8_CC_PRIORITY 7\r
+\r
+#define STM32_IRQ_USART1_PRIORITY 12\r
+#define STM32_IRQ_USART2_PRIORITY 12\r
+#define STM32_IRQ_USART3_PRIORITY 12\r
+#define STM32_IRQ_UART4_PRIORITY 12\r
+#define STM32_IRQ_UART5_PRIORITY 12\r
+#define STM32_IRQ_LPUART1_PRIORITY 12\r
+\r
+/*\r
+ * ADC driver system settings.\r
+ */\r
+#define STM32_ADC_DUAL_MODE FALSE\r
+#define STM32_ADC_COMPACT_SAMPLES FALSE\r
+#define STM32_ADC_USE_ADC1 TRUE\r
+#define STM32_ADC_USE_ADC2 FALSE\r
+#define STM32_ADC_USE_ADC3 TRUE\r
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)\r
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)\r
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)\r
+#define STM32_ADC_ADC1_DMA_PRIORITY 2\r
+#define STM32_ADC_ADC2_DMA_PRIORITY 2\r
+#define STM32_ADC_ADC3_DMA_PRIORITY 2\r
+#define STM32_ADC_ADC12_IRQ_PRIORITY 5\r
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5\r
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5\r
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5\r
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5\r
+#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_ADCCK\r
+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV10\r
+\r
+//#define ADC123_PRESC_VALUE 1\r
+\r
+/*\r
+ * CAN driver system settings.\r
+ */\r
+#define STM32_CAN_USE_CAN1 FALSE\r
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11\r
+\r
+/*\r
+ * DAC driver system settings.\r
+ */\r
+#define STM32_DAC_DUAL_MODE FALSE\r
+#define STM32_DAC_USE_DAC1_CH1 TRUE\r
+#define STM32_DAC_USE_DAC1_CH2 TRUE\r
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10\r
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10\r
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2\r
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2\r
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)\r
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)\r
+\r
+/*\r
+ * GPT driver system settings.\r
+ */\r
+#define STM32_GPT_USE_TIM1 FALSE\r
+#define STM32_GPT_USE_TIM2 FALSE\r
+#define STM32_GPT_USE_TIM3 FALSE\r
+#define STM32_GPT_USE_TIM4 FALSE\r
+#define STM32_GPT_USE_TIM5 FALSE\r
+#define STM32_GPT_USE_TIM6 TRUE\r
+#define STM32_GPT_USE_TIM7 TRUE\r
+#define STM32_GPT_USE_TIM8 FALSE\r
+#define STM32_GPT_USE_TIM15 FALSE\r
+#define STM32_GPT_USE_TIM16 FALSE\r
+#define STM32_GPT_USE_TIM17 FALSE\r
+\r
+/*\r
+ * I2C driver system settings.\r
+ */\r
+#define STM32_I2C_USE_I2C1 FALSE\r
+#define STM32_I2C_USE_I2C2 FALSE\r
+#define STM32_I2C_USE_I2C3 FALSE\r
+#define STM32_I2C_BUSY_TIMEOUT 50\r
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)\r
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)\r
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)\r
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)\r
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)\r
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)\r
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5\r
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5\r
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5\r
+#define STM32_I2C_I2C1_DMA_PRIORITY 3\r
+#define STM32_I2C_I2C2_DMA_PRIORITY 3\r
+#define STM32_I2C_I2C3_DMA_PRIORITY 3\r
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")\r
+\r
+/*\r
+ * ICU driver system settings.\r
+ */\r
+#define STM32_ICU_USE_TIM1 FALSE\r
+#define STM32_ICU_USE_TIM2 FALSE\r
+#define STM32_ICU_USE_TIM3 FALSE\r
+#define STM32_ICU_USE_TIM4 FALSE\r
+#define STM32_ICU_USE_TIM5 FALSE\r
+#define STM32_ICU_USE_TIM8 FALSE\r
+#define STM32_ICU_USE_TIM15 FALSE\r
+#define STM32_ICU_USE_TIM16 FALSE\r
+#define STM32_ICU_USE_TIM17 FALSE\r
+\r
+/*\r
+ * PWM driver system settings.\r
+ */\r
+#define STM32_PWM_USE_ADVANCED FALSE\r
+#define STM32_PWM_USE_TIM1 FALSE\r
+#define STM32_PWM_USE_TIM2 FALSE\r
+#define STM32_PWM_USE_TIM3 FALSE\r
+#define STM32_PWM_USE_TIM4 FALSE\r
+#define STM32_PWM_USE_TIM5 FALSE\r
+#define STM32_PWM_USE_TIM8 FALSE\r
+#define STM32_PWM_USE_TIM15 FALSE\r
+#define STM32_PWM_USE_TIM16 FALSE\r
+#define STM32_PWM_USE_TIM17 FALSE\r
+\r
+/*\r
+ * RTC driver system settings.\r
+ */\r
+#define STM32_RTC_PRESA_VALUE 32\r
+#define STM32_RTC_PRESS_VALUE 1024\r
+#define STM32_RTC_CR_INIT 0\r
+#define STM32_RTC_TAMPCR_INIT 0\r
+\r
+/*\r
+ * SDC driver system settings.\r
+ */\r
+#define STM32_SDC_USE_SDMMC1 FALSE\r
+#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE\r
+#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000\r
+#define STM32_SDC_SDMMC_READ_TIMEOUT 1000\r
+#define STM32_SDC_SDMMC_CLOCK_DELAY 10\r
+#define STM32_SDC_SDMMC1_DMA_PRIORITY 3\r
+#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9\r
+#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)\r
+\r
+/*\r
+ * SERIAL driver system settings.\r
+ */\r
+#define STM32_SERIAL_USE_USART1 FALSE\r
+#define STM32_SERIAL_USE_USART2 TRUE\r
+#define STM32_SERIAL_USE_USART3 FALSE\r
+#define STM32_SERIAL_USE_UART4 FALSE\r
+#define STM32_SERIAL_USE_UART5 FALSE\r
+#define STM32_SERIAL_USE_LPUART1 FALSE\r
+#define STM32_SERIAL_USART1_PRIORITY 12\r
+#define STM32_SERIAL_USART2_PRIORITY 12\r
+#define STM32_SERIAL_USART3_PRIORITY 12\r
+#define STM32_SERIAL_UART4_PRIORITY 12\r
+#define STM32_SERIAL_UART5_PRIORITY 12\r
+#define STM32_SERIAL_LPUART1_PRIORITY 12\r
+\r
+/*\r
+ * SPI driver system settings.\r
+ */\r
+#define STM32_SPI_USE_SPI1 FALSE\r
+#define STM32_SPI_USE_SPI2 FALSE\r
+#define STM32_SPI_USE_SPI3 FALSE\r
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)\r
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)\r
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)\r
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)\r
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)\r
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)\r
+#define STM32_SPI_SPI1_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI2_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI3_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10\r
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10\r
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10\r
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")\r
+\r
+/*\r
+ * ST driver system settings.\r
+ */\r
+#define STM32_ST_IRQ_PRIORITY 8\r
+#define STM32_ST_USE_TIMER 2\r
+\r
+/*\r
+ * TRNG driver system settings.\r
+ */\r
+#define STM32_TRNG_USE_RNG1 FALSE\r
+\r
+/*\r
+ * UART driver system settings.\r
+ */\r
+#define STM32_UART_USE_USART1 FALSE\r
+#define STM32_UART_USE_USART2 FALSE\r
+#define STM32_UART_USE_USART3 FALSE\r
+#define STM32_UART_USE_UART4 FALSE\r
+#define STM32_UART_USE_UART5 FALSE\r
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)\r
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)\r
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)\r
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)\r
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)\r
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)\r
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)\r
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)\r
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)\r
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)\r
+#define STM32_UART_USART1_IRQ_PRIORITY 12\r
+#define STM32_UART_USART2_IRQ_PRIORITY 12\r
+#define STM32_UART_USART3_IRQ_PRIORITY 12\r
+#define STM32_UART_UART4_IRQ_PRIORITY 12\r
+#define STM32_UART_UART5_IRQ_PRIORITY 12\r
+#define STM32_UART_USART1_DMA_PRIORITY 0\r
+#define STM32_UART_USART2_DMA_PRIORITY 0\r
+#define STM32_UART_USART3_DMA_PRIORITY 0\r
+#define STM32_UART_UART4_DMA_PRIORITY 0\r
+#define STM32_UART_UART5_DMA_PRIORITY 0\r
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")\r
+\r
+/*\r
+ * USB driver system settings.\r
+ */\r
+#ifdef STM32L476_MCUCONF\r
+#define STM32_USB_USE_OTG1 TRUE\r
+#define STM32_USB_OTG1_IRQ_PRIORITY 14\r
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512\r
+#else\r
+#define STM32_USB_USE_USB1 TRUE\r
+#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE\r
+#define STM32_USB_USB1_HP_IRQ_PRIORITY 13\r
+#define STM32_USB_USB1_LP_IRQ_PRIORITY 14\r
+#endif // STM32L476_MCUCONF\r
+\r
+/*\r
+ * WDG driver system settings.\r
+ */\r
+#define STM32_WDG_USE_IWDG FALSE\r
+\r
+/*\r
+ * WSPI driver system settings.\r
+ */\r
+#define STM32_WSPI_USE_QUADSPI1 FALSE\r
+#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)\r
+\r
+#endif /* MCUCONF_H */\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/*\r
+ * AXI SRAM - BSS, Data, Heap.\r
+ * SRAM1 - SIGGEN.\r
+ * SRAM2 - DAC.\r
+ * SRAM4 - ADC.\r
+ * DTCM-RAM - Process stacks.\r
+ * ITCM-RAM - STMDSP Algorithm.\r
+ * BCKP SRAM - None.\r
+ */\r
+MEMORY\r
+{\r
+ flash0 (rx) : org = 0x08000000, len = 1M /* Flash bank1 + bank2 */\r
+ flash1 (rx) : org = 0x08000000, len = 510K /* Flash bank 1 */\r
+ flashc (rx) : org = 0x0807F800, len = 2K /* Unprivileged firmware */\r
+ flash2 (rx) : org = 0x08080000, len = 512K /* Flash bank 2 */\r
+ flash3 (rx) : org = 0x00000000, len = 0\r
+ flash4 (rx) : org = 0x00000000, len = 0\r
+ flash5 (rx) : org = 0x00000000, len = 0\r
+ flash6 (rx) : org = 0x00000000, len = 0\r
+ flash7 (rx) : org = 0x00000000, len = 0\r
+ ram0 (wx) : org = 0x24000000, len = 320K /* AXI SRAM */\r
+ ram1 (wx) : org = 0x30000000, len = 16K /* AHB SRAM1 */\r
+ ram2 (wx) : org = 0x30004000, len = 16K /* AHB SRAM2 */\r
+ ram3 (wx) : org = 0x38000000, len = 16K /* AHB SRAM4 */\r
+ ram4 (wx) : org = 0x00000000, len = 0\r
+ ramc (wx) : org = 0x20000000, len = 64K /* Unprivileged data */\r
+ ram5 (wx) : org = 0x20010000, len = 64K /* DTCM-RAM */\r
+ ram6 (wx) : org = 0x00000000, len = 64K /* ITCM-RAM */\r
+ ram7 (wx) : org = 0x38800000, len = 4K /* BCKP SRAM */\r
+}\r
+\r
+/* For each data/text section two region are defined, a virtual region\r
+ and a load region (_LMA suffix).*/\r
+\r
+/* Flash region to be used for exception vectors.*/\r
+REGION_ALIAS("VECTORS_FLASH", flash0);\r
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);\r
+\r
+/* Flash region to be used for constructors and destructors.*/\r
+REGION_ALIAS("XTORS_FLASH", flash0);\r
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);\r
+\r
+/* Flash region to be used for code text.*/\r
+REGION_ALIAS("TEXT_FLASH", flash0);\r
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);\r
+\r
+/* Flash region to be used for read only data.*/\r
+REGION_ALIAS("RODATA_FLASH", flash0);\r
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);\r
+\r
+/* Flash region to be used for various.*/\r
+REGION_ALIAS("VARIOUS_FLASH", flash0);\r
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);\r
+\r
+/* Flash region to be used for RAM(n) initialization data.*/\r
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);\r
+\r
+/* RAM region to be used for Main stack. This stack accommodates the processing\r
+ of all exceptions and interrupts.*/\r
+REGION_ALIAS("MAIN_STACK_RAM", ram5);\r
+\r
+/* RAM region to be used for the process stack. This is the stack used by\r
+ the main() function.*/\r
+REGION_ALIAS("PROCESS_STACK_RAM", ram5);\r
+\r
+/* RAM region to be used for data segment.*/\r
+REGION_ALIAS("DATA_RAM", ram0);\r
+REGION_ALIAS("DATA_RAM_LMA", flash0);\r
+\r
+/* RAM region to be used for BSS segment.*/\r
+REGION_ALIAS("BSS_RAM", ram0);\r
+\r
+/* RAM region to be used for the default heap.*/\r
+REGION_ALIAS("HEAP_RAM", ram0);\r
+\r
+/* Stack rules inclusion.*/\r
+INCLUDE rules_stacks.ld\r
+\r
+SECTIONS\r
+{\r
+ .convdata : ALIGN(4)\r
+ {\r
+ *(.convdata)\r
+ . = ALIGN(4);\r
+ } > ramc\r
+\r
+ .stacks : ALIGN(4)\r
+ {\r
+ *(.stacks)\r
+ . = ALIGN(4);\r
+ } > ram5\r
+\r
+ .convcode : ALIGN(4)\r
+ {\r
+ *(.convcode)\r
+ . = ALIGN(4);\r
+ } > flashc\r
+}\r
+\r
+/* Code rules inclusion.*/\r
+INCLUDE rules_code.ld\r
+\r
+/* Data rules inclusion.*/\r
+INCLUDE rules_data.ld\r
+\r
+/* Memory rules inclusion.*/\r
+INCLUDE rules_memory.ld\r
+\r
--- /dev/null
+/*\r
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/*\r
+ * STM32L476xG memory setup.\r
+ * A total of 1MB of flash is available.\r
+ * Firmware uses first 510K, then 2K after is used for unprivileged code.\r
+ * A total of 128K of RAM is available.\r
+ * SRAM2 (32K) is used for ELF binary loading.\r
+ * 32K of SRAM1 is used for system RAM.\r
+ * 48K is used for ADC and DAC buffers.\r
+ * 16K is used for unprivileged data (incl. 8K stack).\r
+ */\r
+MEMORY\r
+{\r
+ flash0 (rx) : org = 0x08000000, len = 510K /* Flash bank 1 (reduced from 1M to 510K) */\r
+ flash1 (rx) : org = 0x00000000, len = 0\r
+ flash2 (rx) : org = 0x00000000, len = 0\r
+ flash3 (rx) : org = 0x00000000, len = 0\r
+ flash4 (rx) : org = 0x00000000, len = 0\r
+ flash5 (rx) : org = 0x00000000, len = 0\r
+ flash6 (rx) : org = 0x00000000, len = 0\r
+ flash7 (rx) : org = 0x00000000, len = 0\r
+ ram0 (wx) : org = 0x20000000, len = 32K /* SRAM (actual total = 96K) */\r
+ ram1 (wx) : org = 0x20008000, len = 48K /* ADC/DAC buffers (16K * 3) */\r
+ ram2 (wx) : org = 0x00000000, len = 0\r
+ ram3 (wx) : org = 0x00000000, len = 0\r
+ ram4 (wx) : org = 0x10000000, len = 32K /* User algorithm */\r
+ ram5 (wx) : org = 0x00000000, len = 0\r
+ ram6 (wx) : org = 0x00000000, len = 0\r
+ ram7 (wx) : org = 0x00000000, len = 0\r
+ flashc (rx) : org = 0x0807F800, len = 2K /* Unprivileged firmware */\r
+ ramc (wx) : org = 0x20014000, len = 16K /* Unprivileged data */\r
+}\r
+\r
+/* For each data/text section two region are defined, a virtual region\r
+ and a load region (_LMA suffix).*/\r
+\r
+/* Flash region to be used for exception vectors.*/\r
+REGION_ALIAS("VECTORS_FLASH", flash0);\r
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);\r
+\r
+/* Flash region to be used for constructors and destructors.*/\r
+REGION_ALIAS("XTORS_FLASH", flash0);\r
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);\r
+\r
+/* Flash region to be used for code text.*/\r
+REGION_ALIAS("TEXT_FLASH", flash0);\r
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);\r
+\r
+/* Flash region to be used for read only data.*/\r
+REGION_ALIAS("RODATA_FLASH", flash0);\r
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);\r
+\r
+/* Flash region to be used for various.*/\r
+REGION_ALIAS("VARIOUS_FLASH", flash0);\r
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);\r
+\r
+/* Flash region to be used for RAM(n) initialization data.*/\r
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);\r
+\r
+/* RAM region to be used for Main stack. This stack accommodates the processing\r
+ of all exceptions and interrupts.*/\r
+REGION_ALIAS("MAIN_STACK_RAM", ram0);\r
+\r
+/* RAM region to be used for the process stack. This is the stack used by\r
+ the main() function.*/\r
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);\r
+\r
+/* RAM region to be used for data segment.*/\r
+REGION_ALIAS("DATA_RAM", ram0);\r
+REGION_ALIAS("DATA_RAM_LMA", flash0);\r
+\r
+/* RAM region to be used for BSS segment.*/\r
+REGION_ALIAS("BSS_RAM", ram0);\r
+\r
+/* RAM region to be used for the default heap.*/\r
+REGION_ALIAS("HEAP_RAM", ram0);\r
+\r
+SECTIONS\r
+{\r
+ .convdata : ALIGN(4)\r
+ {\r
+ *(.convdata)\r
+ . = ALIGN(4);\r
+ } > ramc\r
+\r
+ /*.stacks : ALIGN(4)\r
+ {\r
+ *(.stacks)\r
+ . = ALIGN(4);\r
+ } > ram5*/\r
+\r
+ .convcode : ALIGN(4)\r
+ {\r
+ *(.convcode)\r
+ . = ALIGN(4);\r
+ } > flashc\r
+}\r
+\r
+\r
+/* Generic rules inclusion.*/\r
+INCLUDE rules.ld\r
projects / clyne / stmdsp.git / commitdiff