pendsv, clock lib

diff --git a/Makefile b/Makefile
index 44dd0593fd99635c7dca728d483d2b5d0303dff9..4a7a22cf6d1dc7acd5f4abd567ac5d7325435da2 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -5,6 +5,7 @@ all:
        arm-none-eabi-as $(MCUFLAGS) startup_stm32l476xx.s -c -o out/startup_stm32l476xx.o
        arm-none-eabi-gcc $(CFLAGS) system_stm32l4xx.c -c -o out/system_stm32l4xx.o
        arm-none-eabi-gcc $(CFLAGS) stm32l4xx_it.c -c -o out/stm32l4xx_it.o
+       arm-none-eabi-gcc $(CFLAGS) clock.c -c -o out/clock.o
        arm-none-eabi-gcc $(CFLAGS) main.c -c -o out/main.o
        arm-none-eabi-gcc $(CFLAGS) -T link.ld out/*.o -o out/main.elf
        arm-none-eabi-objcopy -O ihex out/main.elf main.hex

diff --git a/clock.c b/clock.c
new file mode 100644 (file)
index 0000000..8041cb2
--- /dev/null
+++ b/clock.c
@@ -0,0 +1,59 @@
+#include <clock.h>
+#include <stm32l476xx.h>
+
+#define STK_CTRL       *((uint32_t *)0xE000E010)
+#define STK_LOAD       *((uint32_t *)0xE000E014)
+#define STK_VAL                *((uint32_t *)0xE000E018)
+#define STK_CALIB      *((uint32_t *)0xE000E01C)
+
+// ticks since init
+static uint32_t ticks = 0;
+
+void clock_init(void)
+{
+       // turn on HSI (16MHz)
+       RCC->CR |= RCC_CR_HSION;
+       while ((RCC->CR & RCC_CR_HSIRDY) != RCC_CR_HSIRDY);
+
+       // get PLLR to 80MHz (max)
+       // VCO = C * (N/M) -> 16 * (10/1) = 160
+       // SCLK = VCO / R = 160 / 2 = 80 MHz
+       RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC);
+       RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSI;
+       RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLM);
+       RCC->PLLCFGR |= 10 << RCC_PLLCFGR_PLLN_Pos;
+       RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLR);    // /2
+       RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN;             // PLLR on
+
+       // start PLL
+       RCC->CR |= RCC_CR_PLLON;
+       while ((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY);
+
+       // set system clock to PLL
+       RCC->CFGR &= ~(RCC_CFGR_SW);
+       RCC->CFGR |= RCC_CFGR_SW_PLL;
+       while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);
+
+       // SysTick init. 80MHz / 80000 = 1kHz, ms precision
+       STK_LOAD = 80000;
+       STK_CTRL |= 0x07; // no div, interrupt, enable
+}
+
+void delay(uint32_t count)
+{
+       uint32_t target = ticks + count;
+       while (ticks < target);
+}
+
+void PendSV_Handler(void) {
+}
+
+void SysTick_Handler(void)
+{
+       // just keep counting
+       ticks++;
+
+       if (!(ticks % 500))
+               SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; 
+}
+

diff --git a/include/clock.h b/include/clock.h
new file mode 100644 (file)
index 0000000..9d4b17a
--- /dev/null
+++ b/include/clock.h
@@ -0,0 +1,16 @@
+#ifndef CLOCK_H_
+#define CLOCK_H_
+
+#include <stdint.h>
+
+/**
+ * Sets HCLK (system clock) to 80MHz, the maximum.
+ */
+extern void clock_init(void);
+
+/**
+ * Sleeps for given milliseconds.
+ */
+void delay(uint32_t ms);
+
+#endif // CLOCK_H_

diff --git a/include/stm32l476xx.h b/include/stm32l476xx.h
index af8ef5c5ecdab95e7badf16b2039d1f5eabce36f..7c6f9e005ff03fa2b2c41954c17574fa896d48dc 100644 (file)
--- a/include/stm32l476xx.h
+++ b/include/stm32l476xx.h
@@ -18497,6 +18497,30 @@ typedef struct
 #define DFSDM2_IRQHandler              DFSDM1_FLT2_IRQHandler\r
 #define DFSDM3_IRQHandler              DFSDM1_FLT3_IRQHandler\r
 \r
+/*typedef struct {\r
+       uint32_t CPUID;\r
+       uint32_t ICSR;\r
+       uint32_t VTOR;\r
+       uint32_t AIRCR;\r
+       uint32_t SCR;\r
+       uint32_t CCR;\r
+       uint32_t SHPR1;\r
+       uint32_t SHPR2;\r
+       uint32_t SHPR3;\r
+       uint32_t SHCRS;\r
+       uint32_t CFSR;\r
+       uint32_t HFSR;\r
+       uint32_t rsvd;\r
+       uint32_t MMAR;\r
+       uint32_t BFAR;\r
+       uint32_t AFSR;\r
+} __attribute__ ((packed)) SCB_TypeDef;\r
+\r
+#define SCB_ADDR       (0xE000ED00)\r
+#define SCB                    *((SCB_TypeDef *)SCB_ADDR)\r
+\r
+#define SCB_ICSR_PENDSVSET             (1 << 28)*/\r
+\r
 #ifdef __cplusplus\r
 }\r
 #endif /* __cplusplus */\r

diff --git a/main.c b/main.c
index 148f0532709e7155d19dc9897aa1ea795cbc0d18..e640a6bacb5e2fc78b95a005aa1c817e5b8cb063 100644 (file)
--- a/main.c
+++ b/main.c
@@ -1,16 +1,10 @@
-#include "stm32l476xx.h"\r
-\r
-#define STK_CTRL       *((uint32_t *)0xE000E010)\r
-#define STK_LOAD       *((uint32_t *)0xE000E014)\r
-#define STK_VAL                *((uint32_t *)0xE000E018)\r
-#define STK_CALIB      *((uint32_t *)0xE000E01C)\r
-\r
-extern void delay(uint32_t count);\r
+#include <stm32l476xx.h>\r
+#include <clock.h>\r
 \r
 /**\r
  * Accomplishments:\r
  *   - GPIO in/out\r
- *   - got to 40MHz clock\r
+ *   - got to 80MHz clock\r
  */\r
 \r
 void pulse(uint8_t byte);\r
@@ -21,50 +15,23 @@ int main(void)
        FLASH->ACR &= ~(FLASH_ACR_LATENCY);\r
        FLASH->ACR |= FLASH_ACR_LATENCY_2WS;\r
 \r
-       // turn on HSI\r
-       RCC->CR |= RCC_CR_HSION;\r
-       while ((RCC->CR & RCC_CR_HSIRDY) != RCC_CR_HSIRDY);\r
-\r
-       // get PLLR to 80MHz (max)\r
-       // VCO = C * (N/M) -> 16 * (10/1) = 160\r
-       // SCLK = VCO / R = 160 / 4 = 40 MHz\r
-       RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC);  // source HSI, 16MHz\r
-       RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSI;\r
-       RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLM);\r
-       RCC->PLLCFGR |= 10 << RCC_PLLCFGR_PLLN_Pos;\r
-       RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLR);    // /4\r
-       RCC->PLLCFGR |= 1 << RCC_PLLCFGR_PLLR_Pos;\r
-       RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN;             // PLLR on\r
-\r
-       // start PLL\r
-       RCC->CR |= RCC_CR_PLLON;\r
-       while ((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY);\r
-\r
-       // set system clock to PLL\r
-       RCC->CFGR &= ~(RCC_CFGR_SW);\r
-       RCC->CFGR |= RCC_CFGR_SW_PLL;\r
-       while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);\r
-\r
-       // SysTick setup? Assume 4MHz reset clock\r
-       STK_LOAD = 40000;\r
-       STK_CTRL |= 0x07; // AHB, inten, enable\r
+       clock_init();\r
 \r
        RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN;    // A clk enable\r
-       GPIOA->MODER &= ~(GPIO_MODER_MODE5 | GPIO_MODER_MODE0); // A5 -> output, A0 input\r
-       GPIOA->MODER |= GPIO_MODER_MODE5_0;\r
-       GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPD5 | GPIO_PUPDR_PUPD0);\r
-       GPIOA->PUPDR |= GPIO_PUPDR_PUPD5_0 | GPIO_PUPDR_PUPD0_1; // pd for button\r
-\r
-       pulse(*((uint8_t *)0x08080000)); // 0b00100101\r
+       GPIOA->MODER &= ~(GPIO_MODER_MODE5 | GPIO_MODER_MODE6); // A5 -> output, A0 input\r
+       GPIOA->MODER |= GPIO_MODER_MODE5_0 | GPIO_MODER_MODE6_0;\r
+       GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPD5 | GPIO_PUPDR_PUPD6);\r
+       GPIOA->PUPDR |= GPIO_PUPDR_PUPD5_0 | GPIO_PUPDR_PUPD6_0; // pulldown for button (1)\r
+       //if (GPIOA->IDR & 0x01)\r
 \r
-       while (1);/* {\r
+       while (1) {\r
                delay(500);\r
-               //if (GPIOA->IDR & 0x01)\r
-                       GPIOA->BSRR |= 1 << 5;\r
+               GPIOA->BSRR |= 1 << 5;\r
+               GPIOA->BRR |= 1 << 6;\r
                delay(500);\r
-               //else\r
-                       GPIOA->BRR |= 1 << 5;\r
-       }*/\r
+               GPIOA->BSRR |= 1 << 6;\r
+               GPIOA->BRR |= 1 << 5;\r
+       }\r
 }\r
 \r
 void _exit(int code)\r

diff --git a/stm32l4xx_it.c b/stm32l4xx_it.c
index 999bd04380ae25543fdbca32443b53fb701741aa..c3bd859b8f51e970db3e4132851969fae8d15fe4 100644 (file)
--- a/stm32l4xx_it.c
+++ b/stm32l4xx_it.c
@@ -1,13 +1,5 @@
 #include <stdint.h>\r
 \r
-static uint32_t ticks = 0;\r
-\r
-void delay(uint32_t count)\r
-{\r
-       uint32_t target = ticks + count;\r
-       while (ticks < target);\r
-}\r
-\r
 void NMI_Handler(void) {}\r
 \r
 void HardFault_Handler(void)\r
@@ -34,10 +26,3 @@ void SVC_Handler(void) {}
 \r
 void DebugMon_Handler(void) {}\r
 \r
-void PendSV_Handler(void) {}\r
-\r
-void SysTick_Handler(void)\r
-{\r
-  ticks++;\r
-}\r
-\r