--- /dev/null
+.cproject
+.dep
+.project
+bin/*
--- /dev/null
+##############################################################################\r
+# Build global options\r
+# NOTE: Can be overridden externally.\r
+#\r
+include setup.mk\r
+\r
+# Compiler options here.\r
+ifeq ($(USE_OPT),)\r
+ USE_OPT = -std=gnu99 -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -fsingle-precision-constant\r
+endif\r
+\r
+# C specific options here (added to USE_OPT).\r
+ifeq ($(USE_COPT),)\r
+ USE_COPT = \r
+endif\r
+\r
+# C++ specific options here (added to USE_OPT).\r
+ifeq ($(USE_CPPOPT),)\r
+ USE_CPPOPT = -fno-rtti\r
+endif\r
+\r
+# Enable this if you want the linker to remove unused code and data\r
+ifeq ($(USE_LINK_GC),)\r
+ USE_LINK_GC = yes\r
+endif\r
+\r
+# If enabled, this option allows to compile the application in THUMB mode.\r
+ifeq ($(USE_THUMB),)\r
+ USE_THUMB = yes\r
+endif\r
+\r
+# Enable this if you want to see the full log while compiling.\r
+ifeq ($(USE_VERBOSE_COMPILE),)\r
+ USE_VERBOSE_COMPILE = no\r
+endif\r
+\r
+#\r
+# Build global options\r
+##############################################################################\r
+\r
+##############################################################################\r
+# Architecture or project specific options\r
+#\r
+\r
+# Enable this if you really want to use the STM FWLib.\r
+ifeq ($(USE_FWLIB),)\r
+ USE_FWLIB = no\r
+endif\r
+\r
+#\r
+# Architecture or project specific options\r
+##############################################################################\r
+\r
+##############################################################################\r
+# Project, sources and paths\r
+#\r
+\r
+# PROS compatible build directory\r
+ifeq ($(BUILDDIR),)\r
+BUILDDIR = bin\r
+endif\r
+\r
+# Define project name here\r
+ifeq ($(PROJECT),)\r
+PROJECT = output\r
+endif\r
+\r
+# Path to ChibiOS/RT - default assumes making examples\r
+ifeq ($(CHIBIOS),)\r
+CHIBIOS = ../../../../ChibiOS_2.6.2\r
+endif\r
+\r
+# Path to ConVEX root - default assumes making examples\r
+ifeq ($(CONVEX),)\r
+CONVEX = ../..\r
+endif\r
+\r
+# Imported source files and paths\r
+include $(CONVEX)/boards/VEX_STM32_CORTEX/board.mk\r
+include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk\r
+include $(CHIBIOS)/os/hal/hal.mk\r
+include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk\r
+include $(CHIBIOS)/os/kernel/kernel.mk\r
+include $(CONVEX)/fw/vexfw.mk\r
+\r
+# include the optional code\r
+ifeq ($(CONVEX_OPT),yes)\r
+include $(CONVEX)/opt/vexopt.mk\r
+endif\r
+\r
+# Define linker script file here\r
+LDSCRIPT= $(CONVEX)/ld/STM32F103xD.ld\r
+\r
+\r
+# C sources that can be compiled in ARM or THUMB mode depending on the global\r
+# setting.\r
+# replaced standard shell with custom variant\r
+# $(CHIBIOS)/os/various/shell.c \\r
+ \r
+CSRC = $(PORTSRC) \\r
+ $(KERNSRC) \\r
+ $(HALSRC) \\r
+ $(PLATFORMSRC) \\r
+ $(BOARDSRC) \\r
+ $(CHIBIOS)/os/various/evtimer.c \\r
+ $(CHIBIOS)/os/various/syscalls.c \\r
+ $(CHIBIOS)/os/various/chprintf.c \\r
+ $(VEXFWSRC) \\r
+ $(VEXOPTSRC) \\r
+ $(VEXUSERSRC) \\r
+ main.c\r
+\r
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global\r
+# setting.\r
+CPPSRC =\r
+\r
+# C sources to be compiled in ARM mode regardless of the global setting.\r
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler\r
+# option that results in lower performance and larger code size.\r
+ACSRC =\r
+\r
+# C++ sources to be compiled in ARM mode regardless of the global setting.\r
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler\r
+# option that results in lower performance and larger code size.\r
+ACPPSRC =\r
+\r
+# C sources to be compiled in THUMB mode regardless of the global setting.\r
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler\r
+# option that results in lower performance and larger code size.\r
+TCSRC =\r
+\r
+# C sources to be compiled in THUMB mode regardless of the global setting.\r
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler\r
+# option that results in lower performance and larger code size.\r
+TCPPSRC =\r
+\r
+# List ASM source files here\r
+ASMSRC = $(PORTASM)\r
+\r
+INCDIR = $(PORTINC) $(KERNINC) \\r
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) \\r
+ $(CHIBIOS)/os/various $(VEXFWINC) $(VEXOPTINC) $(VEXUSERINC)\r
+\r
+#\r
+# Project, sources and paths\r
+##############################################################################\r
+\r
+##############################################################################\r
+# Compiler settings\r
+#\r
+\r
+MCU = cortex-m3\r
+\r
+#TRGT = arm-elf-\r
+TRGT = arm-none-eabi-\r
+CC = $(TRGT)gcc\r
+CPPC = $(TRGT)g++\r
+# Enable loading with g++ only if you need C++ runtime support.\r
+# NOTE: You can use C++ even without C++ support if you are careful. C++\r
+# runtime support makes code size explode.\r
+LD = $(TRGT)gcc\r
+#LD = $(TRGT)g++\r
+CP = $(TRGT)objcopy\r
+AS = $(TRGT)gcc -x assembler-with-cpp\r
+OD = $(TRGT)objdump\r
+HEX = $(CP) -O ihex\r
+BIN = $(CP) -O binary\r
+\r
+# ARM-specific options here\r
+AOPT = -mfloat-abi=hard -mcpu=cortex-m3 \r
+\r
+# THUMB-specific options here\r
+TOPT = -mthumb -DTHUMB\r
+\r
+# Define C warning options here\r
+CWARN = -Wall -Wextra -Wstrict-prototypes\r
+\r
+# Define C++ warning options here\r
+CPPWARN = -Wall -Wextra\r
+\r
+#\r
+# Compiler settings\r
+##############################################################################\r
+\r
+##############################################################################\r
+# Start of default section\r
+#\r
+\r
+# List all default C defines here, like -D_DEBUG=1\r
+DDEFS =\r
+\r
+# List all default ASM defines here, like -D_DEBUG=1\r
+DADEFS =\r
+\r
+# List all default directories to look for include files here\r
+DINCDIR =\r
+\r
+# List the default directory to look for the libraries here\r
+DLIBDIR = \r
+\r
+# List all default libraries here\r
+DLIBS =\r
+\r
+#\r
+# End of default section\r
+##############################################################################\r
+\r
+##############################################################################\r
+# Start of user section\r
+#\r
+\r
+# List all user C define here, like -D_DEBUG=1\r
+UDEFS =\r
+\r
+# Define ASM defines here\r
+UADEFS =\r
+\r
+# List all user directories here\r
+UINCDIR =\r
+\r
+# List the user directory to look for the libraries here\r
+ULIBDIR =\r
+\r
+# List all user libraries here\r
+ULIBS = -lm\r
+\r
+#\r
+# End of user defines\r
+##############################################################################\r
+\r
+ifeq ($(USE_FWLIB),yes)\r
+ include $(CHIBIOS)/ext/stm32lib/stm32lib.mk\r
+ CSRC += $(STM32SRC)\r
+ INCDIR += $(STM32INC)\r
+ USE_OPT += -DUSE_STDPERIPH_DRIVER\r
+endif\r
+\r
+include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk\r
--- /dev/null
+/*\r
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/**\r
+ * @file templates/chconf.h\r
+ * @brief Configuration file template.\r
+ * @details A copy of this file must be placed in each project directory, it\r
+ * contains the application specific kernel settings.\r
+ *\r
+ * @addtogroup config\r
+ * @details Kernel related settings and hooks.\r
+ * @{\r
+ */\r
+\r
+#ifndef _CHCONF_H_\r
+#define _CHCONF_H_\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Kernel parameters and options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief System tick frequency.\r
+ * @details Frequency of the system timer that drives the system ticks. This\r
+ * setting also defines the system tick time unit.\r
+ */\r
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)\r
+#define CH_FREQUENCY 1000\r
+#endif\r
+\r
+/**\r
+ * @brief Round robin interval.\r
+ * @details This constant is the number of system ticks allowed for the\r
+ * threads before preemption occurs. Setting this value to zero\r
+ * disables the preemption for threads with equal priority and the\r
+ * round robin becomes cooperative. Note that higher priority\r
+ * threads can still preempt, the kernel is always preemptive.\r
+ *\r
+ * @note Disabling the round robin preemption makes the kernel more compact\r
+ * and generally faster.\r
+ */\r
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)\r
+#define CH_TIME_QUANTUM 20\r
+#endif\r
+\r
+/**\r
+ * @brief Managed RAM size.\r
+ * @details Size of the RAM area to be managed by the OS. If set to zero\r
+ * then the whole available RAM is used. The core memory is made\r
+ * available to the heap allocator and/or can be used directly through\r
+ * the simplified core memory allocator.\r
+ *\r
+ * @note In order to let the OS manage the whole RAM the linker script must\r
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.\r
+ * @note Requires @p CH_USE_MEMCORE.\r
+ */\r
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)\r
+#define CH_MEMCORE_SIZE 0\r
+#endif\r
+\r
+/**\r
+ * @brief Idle thread automatic spawn suppression.\r
+ * @details When this option is activated the function @p chSysInit()\r
+ * does not spawn the idle thread automatically. The application has\r
+ * then the responsibility to do one of the following:\r
+ * - Spawn a custom idle thread at priority @p IDLEPRIO.\r
+ * - Change the main() thread priority to @p IDLEPRIO then enter\r
+ * an endless loop. In this scenario the @p main() thread acts as\r
+ * the idle thread.\r
+ * .\r
+ * @note Unless an idle thread is spawned the @p main() thread must not\r
+ * enter a sleep state.\r
+ */\r
+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)\r
+#define CH_NO_IDLE_THREAD FALSE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Performance options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief OS optimization.\r
+ * @details If enabled then time efficient rather than space efficient code\r
+ * is used when two possible implementations exist.\r
+ *\r
+ * @note This is not related to the compiler optimization options.\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)\r
+#define CH_OPTIMIZE_SPEED TRUE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Subsystem options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Threads registry APIs.\r
+ * @details If enabled then the registry APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)\r
+#define CH_USE_REGISTRY TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Threads synchronization APIs.\r
+ * @details If enabled then the @p chThdWait() function is included in\r
+ * the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)\r
+#define CH_USE_WAITEXIT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Semaphores APIs.\r
+ * @details If enabled then the Semaphores APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)\r
+#define CH_USE_SEMAPHORES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Semaphores queuing mode.\r
+ * @details If enabled then the threads are enqueued on semaphores by\r
+ * priority rather than in FIFO order.\r
+ *\r
+ * @note The default is @p FALSE. Enable this if you have special requirements.\r
+ * @note Requires @p CH_USE_SEMAPHORES.\r
+ */\r
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)\r
+#define CH_USE_SEMAPHORES_PRIORITY FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Atomic semaphore API.\r
+ * @details If enabled then the semaphores the @p chSemSignalWait() API\r
+ * is included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_USE_SEMAPHORES.\r
+ */\r
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)\r
+#define CH_USE_SEMSW TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Mutexes APIs.\r
+ * @details If enabled then the mutexes APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)\r
+#define CH_USE_MUTEXES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Conditional Variables APIs.\r
+ * @details If enabled then the conditional variables APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_USE_MUTEXES.\r
+ */\r
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)\r
+#define CH_USE_CONDVARS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Conditional Variables APIs with timeout.\r
+ * @details If enabled then the conditional variables APIs with timeout\r
+ * specification are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_USE_CONDVARS.\r
+ */\r
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)\r
+#define CH_USE_CONDVARS_TIMEOUT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Events Flags APIs.\r
+ * @details If enabled then the event flags APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)\r
+#define CH_USE_EVENTS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Events Flags APIs with timeout.\r
+ * @details If enabled then the events APIs with timeout specification\r
+ * are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_USE_EVENTS.\r
+ */\r
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)\r
+#define CH_USE_EVENTS_TIMEOUT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Synchronous Messages APIs.\r
+ * @details If enabled then the synchronous messages APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)\r
+#define CH_USE_MESSAGES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Synchronous Messages queuing mode.\r
+ * @details If enabled then messages are served by priority rather than in\r
+ * FIFO order.\r
+ *\r
+ * @note The default is @p FALSE. Enable this if you have special requirements.\r
+ * @note Requires @p CH_USE_MESSAGES.\r
+ */\r
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)\r
+#define CH_USE_MESSAGES_PRIORITY FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Mailboxes APIs.\r
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are\r
+ * included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_USE_SEMAPHORES.\r
+ */\r
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)\r
+#define CH_USE_MAILBOXES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief I/O Queues APIs.\r
+ * @details If enabled then the I/O queues APIs are included in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)\r
+#define CH_USE_QUEUES TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Core Memory Manager APIs.\r
+ * @details If enabled then the core memory manager APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)\r
+#define CH_USE_MEMCORE TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Heap Allocator APIs.\r
+ * @details If enabled then the memory heap allocator APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or\r
+ * @p CH_USE_SEMAPHORES.\r
+ * @note Mutexes are recommended.\r
+ */\r
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)\r
+#define CH_USE_HEAP TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief C-runtime allocator.\r
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime\r
+ * @p malloc() and @p free() functions.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ * @note Requires @p CH_USE_HEAP.\r
+ * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the\r
+ * appropriate documentation.\r
+ */\r
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)\r
+#define CH_USE_MALLOC_HEAP FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Memory Pools Allocator APIs.\r
+ * @details If enabled then the memory pools allocator APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ */\r
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)\r
+#define CH_USE_MEMPOOLS TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Dynamic Threads APIs.\r
+ * @details If enabled then the dynamic threads creation APIs are included\r
+ * in the kernel.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note Requires @p CH_USE_WAITEXIT.\r
+ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.\r
+ */\r
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)\r
+#define CH_USE_DYNAMIC TRUE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Debug options\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Debug option, system state check.\r
+ * @details If enabled the correct call protocol for system APIs is checked\r
+ * at runtime.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)\r
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, parameters checks.\r
+ * @details If enabled then the checks on the API functions input\r
+ * parameters are activated.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)\r
+#define CH_DBG_ENABLE_CHECKS FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, consistency checks.\r
+ * @details If enabled then all the assertions in the kernel code are\r
+ * activated. This includes consistency checks inside the kernel,\r
+ * runtime anomalies and port-defined checks.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)\r
+#define CH_DBG_ENABLE_ASSERTS FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, trace buffer.\r
+ * @details If enabled then the context switch circular trace buffer is\r
+ * activated.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)\r
+#define CH_DBG_ENABLE_TRACE FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, stack checks.\r
+ * @details If enabled then a runtime stack check is performed.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ * @note The stack check is performed in a architecture/port dependent way.\r
+ * It may not be implemented or some ports.\r
+ * @note The default failure mode is to halt the system with the global\r
+ * @p panic_msg variable set to @p NULL.\r
+ */\r
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)\r
+#define CH_DBG_ENABLE_STACK_CHECK FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, stacks initialization.\r
+ * @details If enabled then the threads working area is filled with a byte\r
+ * value when a thread is created. This can be useful for the\r
+ * runtime measurement of the used stack.\r
+ *\r
+ * @note The default is @p FALSE.\r
+ */\r
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)\r
+#define CH_DBG_FILL_THREADS FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Debug option, threads profiling.\r
+ * @details If enabled then a field is added to the @p Thread structure that\r
+ * counts the system ticks occurred while executing the thread.\r
+ *\r
+ * @note The default is @p TRUE.\r
+ * @note This debug option is defaulted to TRUE because it is required by\r
+ * some test cases into the test suite.\r
+ */\r
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)\r
+#define CH_DBG_THREADS_PROFILING TRUE\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/**\r
+ * @name Kernel hooks\r
+ * @{\r
+ */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Threads descriptor structure extension.\r
+ * @details User fields added to the end of the @p Thread structure.\r
+ */\r
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)\r
+#define THREAD_EXT_FIELDS \\r
+ /* Add threads custom fields here.*/\r
+#endif\r
+\r
+/**\r
+ * @brief Threads initialization hook.\r
+ * @details User initialization code added to the @p chThdInit() API.\r
+ *\r
+ * @note It is invoked from within @p chThdInit() and implicitly from all\r
+ * the threads creation APIs.\r
+ */\r
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)\r
+#define THREAD_EXT_INIT_HOOK(tp) { \\r
+ /* Add threads initialization code here.*/ \\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Threads finalization hook.\r
+ * @details User finalization code added to the @p chThdExit() API.\r
+ *\r
+ * @note It is inserted into lock zone.\r
+ * @note It is also invoked when the threads simply return in order to\r
+ * terminate.\r
+ */\r
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)\r
+#define THREAD_EXT_EXIT_HOOK(tp) { \\r
+ /* Add threads finalization code here.*/ \\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Context switch hook.\r
+ * @details This hook is invoked just before switching between threads.\r
+ */\r
+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)\r
+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \\r
+ /* System halt code here.*/ \\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Idle Loop hook.\r
+ * @details This hook is continuously invoked by the idle thread loop.\r
+ */\r
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)\r
+#define IDLE_LOOP_HOOK() { \\r
+ /* Idle loop code here.*/ \\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief System tick event hook.\r
+ * @details This hook is invoked in the system tick handler immediately\r
+ * after processing the virtual timers queue.\r
+ */\r
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)\r
+#define SYSTEM_TICK_EVENT_HOOK() { \\r
+ /* System tick event code here.*/ \\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief System halt hook.\r
+ * @details This hook is invoked in case to a system halting error before\r
+ * the system is halted.\r
+ */\r
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)\r
+#define SYSTEM_HALT_HOOK() { \\r
+ /* System halt code here.*/ \\r
+}\r
+#endif\r
+\r
+/** @} */\r
+\r
+/*===========================================================================*/\r
+/* Port-specific settings (override port settings defaulted in chcore.h). */\r
+/*===========================================================================*/\r
+\r
+#endif /* _CHCONF_H_ */\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+/**\r
+ * @file templates/halconf.h\r
+ * @brief HAL configuration header.\r
+ * @details HAL configuration file, this file allows to enable or disable the\r
+ * various device drivers from your application. You may also use\r
+ * this file in order to override the device drivers default settings.\r
+ *\r
+ * @addtogroup HAL_CONF\r
+ * @{\r
+ */\r
+\r
+#ifndef _HALCONF_H_\r
+#define _HALCONF_H_\r
+\r
+#include "mcuconf.h"\r
+\r
+/**\r
+ * @brief Enables the TM subsystem.\r
+ */\r
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)\r
+#define HAL_USE_TM TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the PAL subsystem.\r
+ */\r
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)\r
+#define HAL_USE_PAL TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the ADC subsystem.\r
+ */\r
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)\r
+#define HAL_USE_ADC TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the CAN subsystem.\r
+ */\r
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)\r
+#define HAL_USE_CAN FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the EXT subsystem.\r
+ */\r
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)\r
+#define HAL_USE_EXT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the GPT subsystem.\r
+ */\r
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)\r
+#define HAL_USE_GPT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the I2C subsystem.\r
+ */\r
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)\r
+#define HAL_USE_I2C TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the ICU subsystem.\r
+ */\r
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)\r
+#define HAL_USE_ICU FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the MAC subsystem.\r
+ */\r
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)\r
+#define HAL_USE_MAC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the MMC_SPI subsystem.\r
+ */\r
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)\r
+#define HAL_USE_MMC_SPI FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the PWM subsystem.\r
+ */\r
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)\r
+#define HAL_USE_PWM FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the RTC subsystem.\r
+ */\r
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)\r
+#define HAL_USE_RTC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SDC subsystem.\r
+ */\r
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)\r
+#define HAL_USE_SDC FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SERIAL subsystem.\r
+ */\r
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)\r
+#define HAL_USE_SERIAL TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SERIAL over USB subsystem.\r
+ */\r
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)\r
+#define HAL_USE_SERIAL_USB FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the SPI subsystem.\r
+ */\r
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)\r
+#define HAL_USE_SPI TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the UART subsystem.\r
+ */\r
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)\r
+#define HAL_USE_UART FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the USB subsystem.\r
+ */\r
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)\r
+#define HAL_USE_USB FALSE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* ADC driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)\r
+#define ADC_USE_WAIT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define ADC_USE_MUTUAL_EXCLUSION TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* CAN driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Sleep mode related APIs inclusion switch.\r
+ */\r
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)\r
+#define CAN_USE_SLEEP_MODE TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* I2C driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables the mutual exclusion APIs on the I2C bus.\r
+ */\r
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define I2C_USE_MUTUAL_EXCLUSION TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* MAC driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables an event sources for incoming packets.\r
+ */\r
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)\r
+#define MAC_USE_ZERO_COPY FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables an event sources for incoming packets.\r
+ */\r
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)\r
+#define MAC_USE_EVENTS TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* MMC_SPI driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Block size for MMC transfers.\r
+ */\r
+#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__)\r
+#define MMC_SECTOR_SIZE 512\r
+#endif\r
+\r
+/**\r
+ * @brief Delays insertions.\r
+ * @details If enabled this options inserts delays into the MMC waiting\r
+ * routines releasing some extra CPU time for the threads with\r
+ * lower priority, this may slow down the driver a bit however.\r
+ * This option is recommended also if the SPI driver does not\r
+ * use a DMA channel and heavily loads the CPU.\r
+ */\r
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)\r
+#define MMC_NICE_WAITING TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Number of positive insertion queries before generating the\r
+ * insertion event.\r
+ */\r
+#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__)\r
+#define MMC_POLLING_INTERVAL 10\r
+#endif\r
+\r
+/**\r
+ * @brief Interval, in milliseconds, between insertion queries.\r
+ */\r
+#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__)\r
+#define MMC_POLLING_DELAY 10\r
+#endif\r
+\r
+/**\r
+ * @brief Uses the SPI polled API for small data transfers.\r
+ * @details Polled transfers usually improve performance because it\r
+ * saves two context switches and interrupt servicing. Note\r
+ * that this option has no effect on large transfers which\r
+ * are always performed using DMAs/IRQs.\r
+ */\r
+#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__)\r
+#define MMC_USE_SPI_POLLING TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* SDC driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Number of initialization attempts before rejecting the card.\r
+ * @note Attempts are performed at 10mS intervals.\r
+ */\r
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)\r
+#define SDC_INIT_RETRY 100\r
+#endif\r
+\r
+/**\r
+ * @brief Include support for MMC cards.\r
+ * @note MMC support is not yet implemented so this option must be kept\r
+ * at @p FALSE.\r
+ */\r
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)\r
+#define SDC_MMC_SUPPORT FALSE\r
+#endif\r
+\r
+/**\r
+ * @brief Delays insertions.\r
+ * @details If enabled this options inserts delays into the MMC waiting\r
+ * routines releasing some extra CPU time for the threads with\r
+ * lower priority, this may slow down the driver a bit however.\r
+ */\r
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)\r
+#define SDC_NICE_WAITING TRUE\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* SERIAL driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Default bit rate.\r
+ * @details Configuration parameter, this is the baud rate selected for the\r
+ * default configuration.\r
+ */\r
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)\r
+#define SERIAL_DEFAULT_BITRATE 19200\r
+#endif\r
+\r
+/**\r
+ * @brief Serial buffers size.\r
+ * @details Configuration parameter, you can change the depth of the queue\r
+ * buffers depending on the requirements of your application.\r
+ * @note The default is 64 bytes for both the transmission and receive\r
+ * buffers.\r
+ */\r
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)\r
+#define SERIAL_BUFFERS_SIZE 64\r
+#endif\r
+\r
+/*===========================================================================*/\r
+/* SPI driver related settings. */\r
+/*===========================================================================*/\r
+\r
+/**\r
+ * @brief Enables synchronous APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)\r
+#define SPI_USE_WAIT TRUE\r
+#endif\r
+\r
+/**\r
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.\r
+ * @note Disabling this option saves both code and data space.\r
+ */\r
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)\r
+#define SPI_USE_MUTUAL_EXCLUSION TRUE\r
+#endif\r
+\r
+#endif /* _HALCONF_H_ */\r
+\r
+/** @} */\r
--- /dev/null
+/*-----------------------------------------------------------------------------*/\r
+/* */\r
+/* Copyright (c) James Pearman */\r
+/* 2013 */\r
+/* All Rights Reserved */\r
+/* */\r
+/*-----------------------------------------------------------------------------*/\r
+/* */\r
+/* Module: vexmain.c */\r
+/* Author: James Pearman */\r
+/* Created: 7 May 2013 */\r
+/* */\r
+/* Revisions: */\r
+/* V1.00 04 July 2013 - Initial release */\r
+/* */\r
+/*-----------------------------------------------------------------------------*/\r
+/* */\r
+/* The author is supplying this software for use with the VEX cortex */\r
+/* control system. This file can be freely distributed and teams are */\r
+/* authorized to freely use this program , however, it is requested that */\r
+/* improvements or additions be shared with the Vex community via the vex */\r
+/* forum. Please acknowledge the work of the authors when appropriate. */\r
+/* Thanks. */\r
+/* */\r
+/* Licensed under the Apache License, Version 2.0 (the "License"); */\r
+/* you may not use this file except in compliance with the License. */\r
+/* You may obtain a copy of the License at */\r
+/* */\r
+/* http://www.apache.org/licenses/LICENSE-2.0 */\r
+/* */\r
+/* Unless required by applicable law or agreed to in writing, software */\r
+/* distributed under the License is distributed on an "AS IS" BASIS, */\r
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. */\r
+/* See the License for the specific language governing permissions and */\r
+/* limitations under the License. */\r
+/* */\r
+/* The author can be contacted on the vex forums as jpearman */\r
+/* or electronic mail using jbpearman_at_mac_dot_com */\r
+/* Mentor for team 8888 RoboLancers, Pasadena CA. */\r
+/* */\r
+/*-----------------------------------------------------------------------------*/\r
+\r
+\r
+#include <string.h>\r
+\r
+#include "ch.h"\r
+#include "hal.h"\r
+#include "chprintf.h"\r
+#include "vex.h"\r
+\r
+/*-----------------------------------------------------------------------------*/\r
+/* Command line related. */\r
+/*-----------------------------------------------------------------------------*/\r
+\r
+#define SHELL_WA_SIZE THD_WA_SIZE(512)\r
+\r
+// Shell command\r
+static const ShellCommand commands[] = {\r
+ {"adc", vexAdcDebug },\r
+ {"spi", vexSpiDebug },\r
+ {"motor", vexMotorDebug},\r
+ {"lcd", vexLcdDebug},\r
+ {"enc", vexEncoderDebug},\r
+ {"son", vexSonarDebug},\r
+ {"ime", vexIMEDebug},\r
+ {"test", vexTestDebug},\r
+ {NULL, NULL}\r
+};\r
+\r
+// configuration for the shell\r
+static const ShellConfig shell_cfg1 = {\r
+ (vexStream *)SD_CONSOLE,\r
+ commands\r
+};\r
+\r
+/*-----------------------------------------------------------------------------*/\r
+// Application entry point. */\r
+/*-----------------------------------------------------------------------------*/\r
+\r
+int main(void)\r
+{\r
+ Thread *shelltp = NULL;\r
+ short timeout = 0;\r
+\r
+ // System initializations.\r
+ // - HAL initialization, this also initializes the configured device drivers\r
+ // and performs the board-specific initializations.\r
+ // - Kernel initialization, the main() function becomes a thread and the\r
+ // RTOS is active.\r
+ halInit();\r
+ chSysInit();\r
+\r
+ // Init the serial port associated with the console\r
+ vexConsoleInit();\r
+\r
+ // init VEX\r
+ vexCortexInit();\r
+\r
+ // wait for good spi comms\r
+ while( vexSpiGetOnlineStatus() == 0 )\r
+ {\r
+ // wait for a while\r
+ chThdSleepMilliseconds(100);\r
+ // dump after 5 seconds\r
+ if(timeout++ == 50)\r
+ break;\r
+ }\r
+\r
+ // Shell manager initialization.\r
+ shellInit();\r
+\r
+ // spin in loop monitoring the shell\r
+ while (TRUE)\r
+ {\r
+ if (!shelltp)\r
+ shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);\r
+ else\r
+ if (chThdTerminated(shelltp))\r
+ {\r
+ chThdRelease(shelltp); /* Recovers memory of the previous shell. */\r
+ shelltp = NULL; /* Triggers spawning of a new shell. */\r
+ }\r
+\r
+ chThdSleepMilliseconds(50);\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio\r
+\r
+ Licensed under the Apache License, Version 2.0 (the "License");\r
+ you may not use this file except in compliance with the License.\r
+ You may obtain a copy of the License at\r
+\r
+ http://www.apache.org/licenses/LICENSE-2.0\r
+\r
+ Unless required by applicable law or agreed to in writing, software\r
+ distributed under the License is distributed on an "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ See the License for the specific language governing permissions and\r
+ limitations under the License.\r
+*/\r
+\r
+#define STM32F103_MCUCONF\r
+\r
+/*\r
+ * STM32F1xx drivers configuration.\r
+ * The following settings override the default settings present in\r
+ * the various device driver implementation headers.\r
+ * Note that the settings for each driver only have effect if the whole\r
+ * driver is enabled in halconf.h.\r
+ *\r
+ * IRQ priorities:\r
+ * 15...0 Lowest...Highest.\r
+ *\r
+ * DMA priorities:\r
+ * 0...3 Lowest...Highest.\r
+ */\r
+\r
+/*\r
+ * HAL driver system settings.\r
+ */\r
+#define STM32_NO_INIT FALSE\r
+#define STM32_HSI_ENABLED TRUE\r
+#define STM32_LSI_ENABLED FALSE\r
+#define STM32_HSE_ENABLED TRUE\r
+#define STM32_LSE_ENABLED FALSE\r
+#define STM32_SW STM32_SW_PLL\r
+#define STM32_PLLSRC STM32_PLLSRC_HSE\r
+#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1\r
+#define STM32_PLLMUL_VALUE 9\r
+#define STM32_HPRE STM32_HPRE_DIV1\r
+#define STM32_PPRE1 STM32_PPRE1_DIV2\r
+#define STM32_PPRE2 STM32_PPRE2_DIV1\r
+#define STM32_ADCPRE STM32_ADCPRE_DIV8\r
+#define STM32_USB_CLOCK_REQUIRED TRUE\r
+#define STM32_USBPRE STM32_USBPRE_DIV1P5\r
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK\r
+#define STM32_RTCSEL STM32_RTCSEL_HSEDIV\r
+#define STM32_PVD_ENABLE FALSE\r
+#define STM32_PLS STM32_PLS_LEV0\r
+\r
+/*\r
+ * ADC driver system settings.\r
+ */\r
+#define STM32_ADC_USE_ADC1 TRUE\r
+#define STM32_ADC_ADC1_DMA_PRIORITY 2\r
+#define STM32_ADC_ADC1_IRQ_PRIORITY 5\r
+\r
+/*\r
+ * CAN driver system settings.\r
+ */\r
+#define STM32_CAN_USE_CAN1 TRUE\r
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11\r
+\r
+/*\r
+ * EXT driver system settings.\r
+ */\r
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6\r
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6\r
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6\r
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6\r
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6\r
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6\r
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6\r
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6\r
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 6\r
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6\r
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6\r
+\r
+/*\r
+ * GPT driver system settings.\r
+ */\r
+#define STM32_GPT_USE_TIM1 TRUE\r
+#define STM32_GPT_USE_TIM2 TRUE\r
+#define STM32_GPT_USE_TIM3 FALSE\r
+#define STM32_GPT_USE_TIM4 FALSE\r
+#define STM32_GPT_USE_TIM5 TRUE\r
+#define STM32_GPT_USE_TIM8 FALSE\r
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7\r
+#define STM32_GPT_TIM2_IRQ_PRIORITY 7\r
+#define STM32_GPT_TIM3_IRQ_PRIORITY 7\r
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7\r
+#define STM32_GPT_TIM5_IRQ_PRIORITY 7\r
+#define STM32_GPT_TIM8_IRQ_PRIORITY 7\r
+\r
+/*\r
+ * I2C driver system settings.\r
+ */\r
+#define STM32_I2C_USE_I2C1 TRUE\r
+#define STM32_I2C_USE_I2C2 FALSE\r
+#define STM32_I2C_USE_I2C3 FALSE\r
+#define STM32_I2C_I2C1_IRQ_PRIORITY 10\r
+#define STM32_I2C_I2C2_IRQ_PRIORITY 10\r
+#define STM32_I2C_I2C3_IRQ_PRIORITY 10\r
+#define STM32_I2C_I2C1_DMA_PRIORITY 1\r
+#define STM32_I2C_I2C2_DMA_PRIORITY 1\r
+#define STM32_I2C_I2C3_DMA_PRIORITY 1\r
+#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()\r
+#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()\r
+#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt()\r
+\r
+/*\r
+ * ICU driver system settings.\r
+ */\r
+#define STM32_ICU_USE_TIM1 FALSE\r
+#define STM32_ICU_USE_TIM2 FALSE\r
+#define STM32_ICU_USE_TIM3 FALSE\r
+#define STM32_ICU_USE_TIM4 FALSE\r
+#define STM32_ICU_USE_TIM5 FALSE\r
+#define STM32_ICU_USE_TIM8 FALSE\r
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7\r
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7\r
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7\r
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7\r
+#define STM32_ICU_TIM5_IRQ_PRIORITY 7\r
+#define STM32_ICU_TIM8_IRQ_PRIORITY 7\r
+\r
+/*\r
+ * PWM driver system settings.\r
+ */\r
+#define STM32_PWM_USE_ADVANCED FALSE\r
+#define STM32_PWM_USE_TIM1 FALSE\r
+#define STM32_PWM_USE_TIM2 FALSE\r
+#define STM32_PWM_USE_TIM3 FALSE\r
+#define STM32_PWM_USE_TIM4 FALSE\r
+#define STM32_PWM_USE_TIM5 FALSE\r
+#define STM32_PWM_USE_TIM8 FALSE\r
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7\r
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7\r
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7\r
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7\r
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7\r
+#define STM32_PWM_TIM8_IRQ_PRIORITY 7\r
+\r
+/*\r
+ * RTC driver system settings.\r
+ */\r
+#define STM32_RTC_IRQ_PRIORITY 15\r
+\r
+/*\r
+ * SERIAL driver system settings.\r
+ */\r
+#define STM32_SERIAL_USE_USART1 TRUE\r
+#define STM32_SERIAL_USE_USART2 TRUE\r
+#define STM32_SERIAL_USE_USART3 TRUE\r
+#define STM32_SERIAL_USE_UART4 FALSE\r
+#define STM32_SERIAL_USE_UART5 FALSE\r
+#define STM32_SERIAL_USE_USART6 FALSE\r
+#define STM32_SERIAL_USART1_PRIORITY 12\r
+#define STM32_SERIAL_USART2_PRIORITY 12\r
+#define STM32_SERIAL_USART3_PRIORITY 12\r
+#define STM32_SERIAL_UART4_PRIORITY 12\r
+#define STM32_SERIAL_UART5_PRIORITY 12\r
+#define STM32_SERIAL_USART6_PRIORITY 12\r
+\r
+/*\r
+ * SPI driver system settings.\r
+ */\r
+#define STM32_SPI_USE_SPI1 TRUE\r
+#define STM32_SPI_USE_SPI2 FALSE\r
+#define STM32_SPI_USE_SPI3 FALSE\r
+#define STM32_SPI_SPI1_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI2_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI3_DMA_PRIORITY 1\r
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10\r
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10\r
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10\r
+#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()\r
+\r
+/*\r
+ * UART driver system settings.\r
+ */\r
+#define STM32_UART_USE_USART1 FALSE\r
+#define STM32_UART_USE_USART2 FALSE\r
+#define STM32_UART_USE_USART3 FALSE\r
+#define STM32_UART_USART1_IRQ_PRIORITY 12\r
+#define STM32_UART_USART2_IRQ_PRIORITY 12\r
+#define STM32_UART_USART3_IRQ_PRIORITY 12\r
+#define STM32_UART_USART1_DMA_PRIORITY 0\r
+#define STM32_UART_USART2_DMA_PRIORITY 0\r
+#define STM32_UART_USART3_DMA_PRIORITY 0\r
+#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()\r
+\r
+/*\r
+ * USB driver system settings.\r
+ */\r
+#define STM32_USB_USE_USB1 FALSE\r
+#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE\r
+#define STM32_USB_USB1_HP_IRQ_PRIORITY 6\r
+#define STM32_USB_USB1_LP_IRQ_PRIORITY 14\r
--- /dev/null
+# uncomment these if running from default project location\r
+# Path to ChibiOS\r
+#CHIBIOS = ../ChibiOS_2.6.2\r
+# Path to convex\r
+#CONVEX = ../convex/cortex\r
+\r
+# uncomment to use the optional code like the smart motor library\r
+#CONVEX_OPT = yes\r
+\r
+# User C code files\r
+VEXUSERSRC = vexuser.c\r
+\r
+# Uncomment and add/modify user include files\r
+#VEXUSERINC = myfile.h\r
+\r
--- /dev/null
+#include <stdlib.h>\r
+#include <math.h>\r
+\r
+#define DIGI_CFG_DIGI_OUT(p) { kVexDigital_##p, kVexSensorDigitalOutput, kVexConfigOutput, 0 }\r
+#define DIGI_CFG_DIGI_IN(p) { kVexDigital_##p, kVexSensorDigitalInput, kVexConfigInput, 0 }\r
+\r
+#define MOTOR_CFG_MOT(p, t, r) p, kVexMotor##t, kVexMotor##r\r
+#define MOTOR_CFG_NOIME kVexSensorNone, 0\r
+#define MOTOR_CFG_IME(c) kVexSensorIME, kImeChannel_##c\r
+\r
+#include "ch.h" // needs for all ChibiOS programs\r
+#include "hal.h" // hardware abstraction layer header\r
+#include "vex.h" // vex library header\r
+\r
+// motor ports\r
+#define mDriveFrontLeft kVexMotor_6\r
+#define mDriveFrontRight kVexMotor_9\r
+#define mDriveBackLeft kVexMotor_7\r
+#define mDriveBackRight kVexMotor_8\r
+#define mLiftLowRight kVexMotor_5\r
+#define mLiftHighRight kVexMotor_4\r
+#define mLiftLowLeft kVexMotor_3\r
+#define mLiftHighLeft kVexMotor_2\r
+#define mPickupThingy kVexMotor_10\r
+#define mClawThingy kVexMotor_1\r
+\r
+// Digi IO configuration\r
+static vexDigiCfg dConfig[] = {\r
+};\r
+\r
+static vexMotorCfg mConfig[] = {\r
+ { MOTOR_CFG_MOT(mClawThingy, 393T, Normal), MOTOR_CFG_NOIME },\r
+ { MOTOR_CFG_MOT(mDriveFrontLeft, 393T, Normal), MOTOR_CFG_NOIME },\r
+ { MOTOR_CFG_MOT(mDriveFrontRight, 393T, Reversed), MOTOR_CFG_NOIME },\r
+ { MOTOR_CFG_MOT(mDriveBackLeft, 393T, Reversed), MOTOR_CFG_NOIME },\r
+ { MOTOR_CFG_MOT(mDriveBackRight, 393T, Normal), MOTOR_CFG_NOIME },\r
+ { MOTOR_CFG_MOT(mLiftLowRight, 393T, Normal), MOTOR_CFG_NOIME },\r
+ { MOTOR_CFG_MOT(mLiftHighRight, 393T, Normal), MOTOR_CFG_NOIME },\r
+ { MOTOR_CFG_MOT(mLiftLowLeft, 393T, Normal), MOTOR_CFG_NOIME },\r
+ { MOTOR_CFG_MOT(mLiftHighLeft, 393T, Normal), MOTOR_CFG_NOIME },\r
+ { MOTOR_CFG_MOT(mPickupThingy, 393T, Normal), MOTOR_CFG_NOIME }\r
+};\r
+\r
+void vexUserSetup(void)\r
+{\r
+ vexDigitalConfigure(dConfig, DIG_CONFIG_SIZE(dConfig));\r
+ vexMotorConfigure(mConfig, MOT_CONFIG_SIZE(mConfig));\r
+}\r
+\r
+void vexUserInit(void)\r
+{}\r
+\r
+msg_t vexAutonomous(void* arg)\r
+{\r
+ (void)arg;\r
+\r
+ vexTaskRegister("auton");\r
+\r
+ vexMotorSet(mClawThingy, -127);\r
+ vexMotorSet(mPickupThingy, -64);\r
+ vexSleep(300);\r
+ vexMotorSet(mClawThingy, 0);\r
+ vexMotorSet(mPickupThingy, 0);\r
+\r
+ vexMotorSet(mDriveFrontLeft, 127);\r
+ vexMotorSet(mDriveFrontRight, 127);\r
+ vexMotorSet(mDriveBackLeft, 127);\r
+ vexMotorSet(mDriveBackRight, 127);\r
+ vexSleep(3000);\r
+ vexMotorSet(mDriveFrontLeft, -30);\r
+ vexMotorSet(mDriveFrontRight, -30);\r
+ vexMotorSet(mDriveBackLeft, -30);\r
+ vexMotorSet(mDriveBackRight, -30);\r
+ vexSleep(1000);\r
+ vexMotorSet(mDriveFrontLeft, 0);\r
+ vexMotorSet(mDriveFrontRight, 0);\r
+ vexMotorSet(mDriveBackLeft, 0);\r
+ vexMotorSet(mDriveBackRight, 0);\r
+\r
+ while(1)\r
+ vexSleep(25);\r
+\r
+ return (msg_t)0;\r
+}\r
+\r
+typedef struct {\r
+ int x, y;\r
+} __attribute__ ((packed)) joy_t;\r
+\r
+int doubleButton(int btnp, int btnn, int speed);\r
+\r
+msg_t vexOperator(void* arg)\r
+{\r
+ static joy_t joyLeft, joyRight;\r
+\r
+ (void)arg;\r
+\r
+ vexTaskRegister("operator");\r
+\r
+ while(!chThdShouldTerminate()) {\r
+\r
+ // control update\r
+ joyLeft = (joy_t) {vexControllerGet(Ch4), vexControllerGet(Ch3)};\r
+ joyRight = (joy_t) {vexControllerGet(Ch1), vexControllerGet(Ch2)};\r
+\r
+ // drive motors\r
+ vexMotorSet(mDriveFrontLeft, joyLeft.y + joyLeft.x);\r
+ vexMotorSet(mDriveFrontRight, joyLeft.y - joyLeft.x);\r
+ vexMotorSet(mDriveBackLeft, joyLeft.y + joyLeft.x);\r
+ vexMotorSet(mDriveBackRight, joyLeft.y - joyLeft.x);\r
+\r
+ // lift motors\r
+ vexMotorSet(mLiftLowRight, joyRight.y);\r
+ vexMotorSet(mLiftHighRight, joyRight.y);\r
+ vexMotorSet(mLiftLowLeft, joyRight.y);\r
+ vexMotorSet(mLiftHighLeft, joyRight.y);\r
+\r
+ // lift thingy\r
+ vexMotorSet(mPickupThingy, doubleButton(Btn5U, Btn5D, 64));\r
+\r
+ // claw thingy\r
+ vexMotorSet(mClawThingy, doubleButton(Btn6U, Btn6D, 127));\r
+\r
+ vexSleep(25);\r
+ }\r
+\r
+ return (msg_t)0;\r
+}\r
+\r
+\r
+int doubleButton(int btnp, int btnn, int speed)\r
+{\r
+ return (vexControllerGet(btnp) ? speed : (vexControllerGet(btnn) ? -speed : 0));\r
+}\r
projects / clyne / zephyr-os-alpha.git / commitdiff