exec from ram; process all samples

diff --git a/Core/Src/main.c b/Core/Src/main.c
index 45d16a69184ce1e2045e340d2949ae44139b1912..ed497037b927af220e6ac26f14b64606acc0cb5e 100644 (file)
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -32,7 +32,7 @@ typedef uint32_t sample_t;
 \r
 /* Private define ------------------------------------------------------------*/\r
 /* USER CODE BEGIN PD */\r
-#define SAMPLE_COUNT        (256)   // (Stereo!) Sample count per half-transfer\r
+#define SAMPLE_COUNT        (1024)   // (Stereo!) Sample count per half-transfer\r
 #define SAMPLES_PER_REPORT  (48000) // Report every second given our 48 kHz rate\r
 #define MIC_OFFSET_DB       (  0.f) // Linear offset\r
 #define MIC_SENSITIVITY     (-26.f) // dBFS value expected at MIC_REF_DB\r
@@ -79,7 +79,9 @@ static HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA_Mixed(
     uint8_t *pRxData,\r
     uint16_t TxSize,\r
     uint16_t RxSize);\r
+__RAM_FUNC\r
 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r
+__RAM_FUNC\r
 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r
 /* USER CODE END PFP */\r
 \r
@@ -91,6 +93,14 @@ int __io_putchar(int ch)
     HAL_UART_Transmit(&huart2, &buf, sizeof(buf), HAL_TIMEOUT);\r
     return buf;\r
 }\r
+\r
+__RAM_FUNC\r
+void fvar_init(void)\r
+{\r
+  ln10 = qfp_fln(10.f);\r
+  MIC_REF_AMPL = qfp_fmul(qfp_int2float((1u << (MIC_BITS - 2)) - 1),\r
+    qfp_fpow(10.f, MIC_SENSITIVITY / 20.f));\r
+}\r
 /* USER CODE END 0 */\r
 \r
 /**\r
@@ -101,9 +111,7 @@ int main(void)
 {\r
 \r
   /* USER CODE BEGIN 1 */\r
-  ln10 = qfp_fln(10.f);\r
-  MIC_REF_AMPL = qfp_fmul(qfp_int2float((1u << (MIC_BITS - 1)) - 1),\r
-    qfp_fpow(10.f, MIC_SENSITIVITY / 20.f));\r
+  fvar_init();\r
   /* USER CODE END 1 */\r
 \r
   /* MCU Configuration--------------------------------------------------------*/\r
@@ -160,7 +168,7 @@ void SystemClock_Config(void)
 \r
   /** Configure the main internal regulator output voltage\r
   */\r
-  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE2);\r
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);\r
 \r
   /** Initializes the RCC Oscillators according to the specified parameters\r
   * in the RCC_OscInitTypeDef structure.\r
@@ -180,10 +188,10 @@ void SystemClock_Config(void)
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK\r
                               |RCC_CLOCKTYPE_PCLK1;\r
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;\r
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;\r
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;\r
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;\r
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;\r
 \r
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)\r
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)\r
   {\r
     Error_Handler();\r
   }\r
@@ -323,7 +331,7 @@ static void MX_GPIO_Init(void)
   HAL_GPIO_WritePin(LED_RED_GPIO_Port, LED_RED_Pin, GPIO_PIN_RESET);\r
 \r
   /*Configure GPIO pin Output Level */\r
-  HAL_GPIO_WritePin(IDLE_GPIO_Port, IDLE_Pin, GPIO_PIN_RESET);\r
+  HAL_GPIO_WritePin(IDLE_GPIO_Port, IDLE_Pin, GPIO_PIN_SET);\r
 \r
   /*Configure GPIO pin : LED_GREEN_Pin */\r
   GPIO_InitStruct.Pin = LED_GREEN_Pin;\r
@@ -443,6 +451,43 @@ error :
 \r
 #define BITO (10)\r
 \r
+__RAM_FUNC\r
+__attribute__((naked))\r
+int64_t lmul(int64_t a, int64_t b)\r
+{\r
+    asm(\r
+"      push    {r4, lr}\n"\r
+"      mul     r1, r2\n"\r
+"      mul     r3, r0\n"\r
+"      add     r1, r3\n"\r
+\r
+"      lsr     r3, r0, #16\n"\r
+"      lsr     r4, r2, #16\n"\r
+"      mul     r3, r4\n"\r
+"      add     r1, r3\n"\r
+\r
+"      lsr     r3, r0, #16\n"\r
+"      uxth    r0, r0\n"\r
+"      uxth    r2, r2\n"\r
+"      mul     r3, r2\n"\r
+"      mul     r4, r0\n"\r
+"      mul     r0, r2\n"\r
+\r
+"      mov     r2, #0\n"\r
+"      add     r3, r4\n"\r
+"      adc     r2, r2\n"\r
+"      lsl     r2, #16\n"\r
+"      add     r1, r2\n"\r
+\r
+"      lsl     r2, r3, #16\n"\r
+"      lsr     r3, #16\n"\r
+"      add     r0, r2\n"\r
+"      adc     r1, r3\n"\r
+"      pop     {r4, pc}\n"\r
+    );\r
+}\r
+\r
+__RAM_FUNC\r
 static inline void process(int64_t in_div4)\r
 {\r
     static int64_t z[4] = {0, 0, 0, 0};\r
@@ -458,25 +503,24 @@ static inline void process(int64_t in_div4)
     int64_t out3 = (out2 + z[3]);\r
     z[3] = ((out3 * 0x3f1 /*0.985f*/) >> BITO) - out2;\r
 \r
-    DB_Sum_Squares += (out3 * out3) >> BITO;\r
+    DB_Sum_Squares += lmul(out3, out3) >> BITO;\r
 }\r
 \r
+__RAM_FUNC\r
 static void processSampleBlock(sample_t *sample)\r
 {\r
-  HAL_GPIO_WritePin(IDLE_GPIO_Port, IDLE_Pin, GPIO_PIN_RESET);\r
-\r
-#define STRIDE 2\r
+  IDLE_GPIO_Port->ODR ^= IDLE_Pin;\r
 \r
-  for (int i = 0; i < SAMPLE_COUNT; i += 2 * STRIDE) {\r
+  for (int i = 0; i < SAMPLE_COUNT; i += 2) {\r
     // 18-bit sample comes in as big-endian with right padding.\r
     // Use REVSH to extract 18-bit reading divided by four for process().\r
     int samp;\r
     asm("revsh %0, %1" : "=l" (samp) : "l" (sample[i]));\r
     process(samp);\r
   }\r
-  DB_Count += SAMPLE_COUNT / (2 * STRIDE);\r
+  DB_Count += SAMPLE_COUNT / 2;\r
 \r
-  if (DB_Count >= SAMPLES_PER_REPORT / STRIDE) {\r
+  if (DB_Count >= SAMPLES_PER_REPORT) {\r
     float rms = qfp_fsqrt(qfp_int2float((DB_Sum_Squares >> BITO) / DB_Count));\r
     float db = qfp_fadd(qfp_fmul(qfp_flog10(qfp_fdiv(rms, MIC_REF_AMPL)), 20.f),\r
         MIC_OFFSET_DB + MIC_REF_DB);\r
@@ -486,7 +530,7 @@ static void processSampleBlock(sample_t *sample)
     printf("%d dB\r\n", qfp_float2int(db));\r
   }\r
 \r
-  HAL_GPIO_WritePin(IDLE_GPIO_Port, IDLE_Pin, GPIO_PIN_SET);\r
+  IDLE_GPIO_Port->ODR ^= IDLE_Pin;\r
 }\r
 \r
 void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r

diff --git a/Drivers/qfplib-m0-full-20240105/qfplib-m0-full.h b/Drivers/qfplib-m0-full-20240105/qfplib-m0-full.h
index 0b1f6eb5fc4802445ce59866016f4b3ba6fca462..b3c3a50b002118e00705a852e134206f977df5b5 100644 (file)
--- a/Drivers/qfplib-m0-full-20240105/qfplib-m0-full.h
+++ b/Drivers/qfplib-m0-full-20240105/qfplib-m0-full.h
@@ -24,21 +24,21 @@ Fifth Floor, Boston, MA  02110-1301, USA.
 typedef unsigned           int ui32;
 typedef                    int i32;
 
-extern float  qfp_fadd          (float x,float y);
-extern float  qfp_fsub          (float x,float y);
-extern float  qfp_fmul          (float x,float y);
-extern float  qfp_fdiv          (float x,float y);
-extern int    qfp_fcmp          (float x,float y);
-extern float  qfp_fsqrt         (float x);
-extern i32    qfp_float2int     (float x);
-extern i32    qfp_float2fix     (float x,int f);
-extern ui32   qfp_float2uint    (float x);
-extern ui32   qfp_float2ufix    (float x,int f);
-extern float  qfp_int2float     (i32 x);
-extern float  qfp_fix2float     (i32 x,int f);
-extern float  qfp_uint2float    (ui32 x);
-extern float  qfp_ufix2float    (ui32 x,int f);
-extern float  qfp_fexp          (float x);
-extern float  qfp_fln           (float x);
+__RAM_FUNC extern float  qfp_fadd          (float x,float y);
+__RAM_FUNC extern float  qfp_fsub          (float x,float y);
+__RAM_FUNC extern float  qfp_fmul          (float x,float y);
+__RAM_FUNC extern float  qfp_fdiv          (float x,float y);
+__RAM_FUNC extern int    qfp_fcmp          (float x,float y);
+__RAM_FUNC extern float  qfp_fsqrt         (float x);
+__RAM_FUNC extern i32    qfp_float2int     (float x);
+__RAM_FUNC extern i32    qfp_float2fix     (float x,int f);
+__RAM_FUNC extern ui32   qfp_float2uint    (float x);
+__RAM_FUNC extern ui32   qfp_float2ufix    (float x,int f);
+__RAM_FUNC extern float  qfp_int2float     (i32 x);
+__RAM_FUNC extern float  qfp_fix2float     (i32 x,int f);
+__RAM_FUNC extern float  qfp_uint2float    (ui32 x);
+__RAM_FUNC extern float  qfp_ufix2float    (ui32 x,int f);
+__RAM_FUNC extern float  qfp_fexp          (float x);
+__RAM_FUNC extern float  qfp_fln           (float x);
 
 #endif

diff --git a/Drivers/qfplib-m0-full-20240105/qfplib-m0-full.s b/Drivers/qfplib-m0-full-20240105/qfplib-m0-full.s
index 2ded28d606a38014cdf04af0274d1134262df03c..b08b5c3a5d065f74770a67d56279ae54fbdc7ba2 100644 (file)
--- a/Drivers/qfplib-m0-full-20240105/qfplib-m0-full.s
+++ b/Drivers/qfplib-m0-full-20240105/qfplib-m0-full.s
@@ -16,6 +16,8 @@
 @ write to the Free Software Foundation, Inc., 51 Franklin Street,
 @ Fifth Floor, Boston, MA  02110-1301, USA.
 
+.section .RamFunc
+
 .syntax unified
 .cpu cortex-m0plus
 .thumb

diff --git a/Drivers/qfplib-m0-full-20240105/qfplib-port.h b/Drivers/qfplib-m0-full-20240105/qfplib-port.h
index 4d5781059a102f16514833e88653d2b8861beb58..c411deef83793f799fcf39a29473b9fe5a4eeee8 100644 (file)
--- a/Drivers/qfplib-m0-full-20240105/qfplib-port.h
+++ b/Drivers/qfplib-m0-full-20240105/qfplib-port.h
@@ -1,10 +1,12 @@
 #include "qfplib-m0-full.h"
 
+__RAM_FUNC
 float qfp_fpow(float b, float e)
 {
     return qfp_fexp(qfp_fmul(e, qfp_fln(b)));
 }
 
+__RAM_FUNC
 float qfp_flog10(float x)
 {
     extern float ln10;

diff --git a/Makefile b/Makefile
index b26e4daafef43f1d4faf7376a9ab873770210f85..9fe97c8edbf74d73ba40dfe414dd8eaa4921afb4 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 ##########################################################################################################################\r
-# File automatically-generated by tool: [projectgenerator] version: [4.5.0-RC5] date: [Fri Jan 31 17:56:51 EST 2025] \r
+# File automatically-generated by tool: [projectgenerator] version: [4.5.0-RC5] date: [Sat Feb 01 13:11:42 EST 2025] \r
 ##########################################################################################################################\r
 \r
 # ------------------------------------------------\r

diff --git a/STM32U083xx_RAM.ld b/STM32U083xx_RAM.ld
index dd76c0fe6f92bc178a79c4cbdb6add9019e21b21..4eb873b86513f7df7174b0215b4646d60d30b115 100644 (file)
--- a/STM32U083xx_RAM.ld
+++ b/STM32U083xx_RAM.ld
@@ -44,6 +44,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
 MEMORY\r
 {\r
   RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 32K\r
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 256K\r
 }\r
 \r
 /* Sections */\r
@@ -55,7 +56,8 @@ SECTIONS
     . = ALIGN(4);\r
     KEEP(*(.isr_vector)) /* Startup code */\r
     . = ALIGN(4);\r
-  } >RAM\r
+    *(.text.Reset_Handler)\r
+  } >FLASH\r
 \r
   /* The program code and other data into "RAM" Ram type memory */\r
   .text :\r

diff --git a/microphone.ioc b/microphone.ioc
index 49dc5db3d2abf35b175cc4fa8c9c814f2b8d3dc7..33858813986a61844060d3d8fe863604618d5370 100644 (file)
--- a/microphone.ioc
+++ b/microphone.ioc
@@ -128,10 +128,11 @@ PC2.GPIOParameters=GPIO_Label
 PC2.GPIO_Label=Joystick
 PC2.Locked=true
 PC2.Signal=ADC1_IN2
-PD9.GPIOParameters=GPIO_Speed,GPIO_Label
+PD9.GPIOParameters=GPIO_Speed,PinState,GPIO_Label
 PD9.GPIO_Label=IDLE
 PD9.GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM
 PD9.Locked=true
+PD9.PinState=GPIO_PIN_SET
 PD9.Signal=GPIO_Output
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
@@ -166,24 +167,23 @@ ProjectManager.UAScriptBeforePath=
 ProjectManager.UnderRoot=false
 ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_USART2_UART_Init-USART2-false-HAL-true,0-MX_CORTEX_M0+_Init-CORTEX_M0+-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true
 RCC.ADCFreq_Value=24000000
-RCC.AHBCLKDivider=RCC_SYSCLK_DIV2
-RCC.AHBFreq_Value=12000000
-RCC.APB1CLKDivider=RCC_HCLK_DIV2
+RCC.AHBFreq_Value=24000000
+RCC.APB1CLKDivider=RCC_HCLK_DIV4
 RCC.APBFreq_Value=6000000
 RCC.APBTimFreq_Value=12000000
-RCC.CortexFreq_Value=1500000
+RCC.CortexFreq_Value=3000000
 RCC.Cortex_Div=SYSTICK_CLKSOURCE_HCLK_DIV8
 RCC.DATA_CACHE_ENABLE=1
-RCC.FCLKCortexFreq_Value=12000000
+RCC.FCLKCortexFreq_Value=24000000
 RCC.FamilyName=M
-RCC.HCLKFreq_Value=12000000
+RCC.HCLKFreq_Value=24000000
 RCC.HSE_VALUE=4000000
 RCC.HSI48_VALUE=48000000
 RCC.HSI_VALUE=16000000
 RCC.I2C1Freq_Value=6000000
 RCC.I2C3Freq_Value=6000000
 RCC.INSTRUCTION_CACHE_ENABLE=1
-RCC.IPParameters=ADCFreq_Value,AHBCLKDivider,AHBFreq_Value,APB1CLKDivider,APBFreq_Value,APBTimFreq_Value,CortexFreq_Value,Cortex_Div,DATA_CACHE_ENABLE,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,INSTRUCTION_CACHE_ENABLE,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPUART1Freq_Value,LPUART2Freq_Value,LPUART3Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,MSIClockRangeVal,MSI_VALUE,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIM15Freq_Value,TIM1Freq_Value,USART1Freq_Value,USART2Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VDD_VALUE
+RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1CLKDivider,APBFreq_Value,APBTimFreq_Value,CortexFreq_Value,Cortex_Div,DATA_CACHE_ENABLE,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,INSTRUCTION_CACHE_ENABLE,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPUART1Freq_Value,LPUART2Freq_Value,LPUART3Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,MSIClockRangeVal,MSI_VALUE,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLR,PLLRCLKFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIM15Freq_Value,TIM1Freq_Value,USART1Freq_Value,USART2Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VDD_VALUE
 RCC.LPTIM1Freq_Value=6000000
 RCC.LPTIM2Freq_Value=6000000
 RCC.LPTIM3Freq_Value=6000000
@@ -197,9 +197,11 @@ RCC.MCO1PinFreq_Value=24000000
 RCC.MCO2PinFreq_Value=24000000
 RCC.MSIClockRangeVal=RCC_MSIRANGE_9
 RCC.MSI_VALUE=24000000
-RCC.PLLPoutputFreq_Value=48000000
-RCC.PLLQoutputFreq_Value=48000000
-RCC.PLLRCLKFreq_Value=48000000
+RCC.PLLN=24
+RCC.PLLPoutputFreq_Value=288000000
+RCC.PLLQoutputFreq_Value=288000000
+RCC.PLLR=RCC_PLLR_DIV8
+RCC.PLLRCLKFreq_Value=72000000
 RCC.PLLSourceVirtual=RCC_PLLSOURCE_MSI
 RCC.PWRFreq_Value=24000000
 RCC.RNGFreq_Value=24000000
@@ -211,7 +213,7 @@ RCC.USART1Freq_Value=6000000
 RCC.USART2Freq_Value=6000000
 RCC.USBFreq_Value=24000000
 RCC.VCOInputFreq_Value=24000000
-RCC.VCOOutputFreq_Value=96000000
+RCC.VCOOutputFreq_Value=576000000
 RCC.VDD_VALUE=1.71
 SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2
 SPI1.CalculateBaudRate=3.0 MBits/s