diff --git a/.gitignore b/.gitignore index 0c82925..3b8f372 100644 --- a/.gitignore +++ b/.gitignore @@ -1,8 +1,12 @@ .* *.o *.dat +*.bin +*.lzss alee alee-msp430 alee-standalone libalee.a core.fth.h +msp430/lzss +msp430/msp430fr2476_all.h diff --git a/forth/msp430.fth b/forth/msp430.fth index 8a02158..1b3ab40 100644 --- a/forth/msp430.fth +++ b/forth/msp430.fth @@ -16,864 +16,3 @@ : toggle ( b r reg/wreg -- ) >r over r> execute >r rot r> ^ -rot execute ; -16 base ! - -: ADCCTL0 0700 ; -: ADCCTL0_L 0700 ; -: ADCCTL0_H 0701 ; -: ADCCTL1 0702 ; -: ADCCTL1_L 0702 ; -: ADCCTL1_H 0703 ; -: ADCCTL2 0704 ; -: ADCCTL2_L 0704 ; -: ADCCTL2_H 0705 ; -: ADCLO 0706 ; -: ADCLO_L 0706 ; -: ADCLO_H 0707 ; -: ADCHI 0708 ; -: ADCHI_L 0708 ; -: ADCHI_H 0709 ; -: ADCMCTL0 070A ; -: ADCMCTL0_L 070A ; -: ADCMCTL0_H 070B ; -: ADCMEM0 0712 ; -: ADCMEM0_L 0712 ; -: ADCMEM0_H 0713 ; -: ADCIE 071A ; -: ADCIE_L 071A ; -: ADCIE_H 071B ; -: ADCIFG 071C ; -: ADCIFG_L 071C ; -: ADCIFG_H 071D ; -: ADCIV 071E ; -: ADCIV_L 071E ; -: ADCIV_H 071F ; -: BAKMEM0 0660 ; -: BAKMEM0_L 0660 ; -: BAKMEM0_H 0661 ; -: BAKMEM1 0662 ; -: BAKMEM1_L 0662 ; -: BAKMEM1_H 0663 ; -: BAKMEM2 0664 ; -: BAKMEM2_L 0664 ; -: BAKMEM2_H 0665 ; -: BAKMEM3 0666 ; -: BAKMEM3_L 0666 ; -: BAKMEM3_H 0667 ; -: BAKMEM4 0668 ; -: BAKMEM4_L 0668 ; -: BAKMEM4_H 0669 ; -: BAKMEM5 066A ; -: BAKMEM5_L 066A ; -: BAKMEM5_H 066B ; -: BAKMEM6 066C ; -: BAKMEM6_L 066C ; -: BAKMEM6_H 066D ; -: BAKMEM7 066E ; -: BAKMEM7_L 066E ; -: BAKMEM7_H 066F ; -: BAKMEM8 0670 ; -: BAKMEM8_L 0670 ; -: BAKMEM8_H 0671 ; -: BAKMEM9 0672 ; -: BAKMEM9_L 0672 ; -: BAKMEM9_H 0673 ; -: BAKMEM10 0674 ; -: BAKMEM10_L 0674 ; -: BAKMEM10_H 0675 ; -: BAKMEM11 0676 ; -: BAKMEM11_L 0676 ; -: BAKMEM11_H 0677 ; -: BAKMEM12 0678 ; -: BAKMEM12_L 0678 ; -: BAKMEM12_H 0679 ; -: BAKMEM13 067A ; -: BAKMEM13_L 067A ; -: BAKMEM13_H 067B ; -: BAKMEM14 067C ; -: BAKMEM14_L 067C ; -: BAKMEM14_H 067D ; -: BAKMEM15 067E ; -: BAKMEM15_L 067E ; -: BAKMEM15_H 067F ; -: CRCDI 01C0 ; -: CRCDI_L 01C0 ; -: CRCDI_H 01C1 ; -: CRCDIRB 01C2 ; -: CRCDIRB_L 01C2 ; -: CRCDIRB_H 01C3 ; -: CRCINIRES 01C4 ; -: CRCINIRES_L 01C4 ; -: CRCINIRES_H 01C5 ; -: CRCRESR 01C6 ; -: CRCRESR_L 01C6 ; -: CRCRESR_H 01C7 ; -: CSCTL0 0180 ; -: CSCTL0_L 0180 ; -: CSCTL0_H 0181 ; -: CSCTL1 0182 ; -: CSCTL1_L 0182 ; -: CSCTL1_H 0183 ; -: CSCTL2 0184 ; -: CSCTL2_L 0184 ; -: CSCTL2_H 0185 ; -: CSCTL3 0186 ; -: CSCTL3_L 0186 ; -: CSCTL3_H 0187 ; -: CSCTL4 0188 ; -: CSCTL4_L 0188 ; -: CSCTL4_H 0189 ; -: CSCTL5 018A ; -: CSCTL5_L 018A ; -: CSCTL5_H 018B ; -: CSCTL6 018C ; -: CSCTL6_L 018C ; -: CSCTL6_H 018D ; -: CSCTL7 018E ; -: CSCTL7_L 018E ; -: CSCTL7_H 018F ; -: CSCTL8 0190 ; -: CSCTL8_L 0190 ; -: CSCTL8_H 0191 ; -: PAIN 0200 ; -: PAIN_L 0200 ; -: PAIN_H 0201 ; -: PAOUT 0202 ; -: PAOUT_L 0202 ; -: PAOUT_H 0203 ; -: PADIR 0204 ; -: PADIR_L 0204 ; -: PADIR_H 0205 ; -: PAREN 0206 ; -: PAREN_L 0206 ; -: PAREN_H 0207 ; -: PASEL0 020A ; -: PASEL0_L 020A ; -: PASEL0_H 020B ; -: PASEL1 020C ; -: PASEL1_L 020C ; -: PASEL1_H 020D ; -: P1IV 020E ; -: P1IV_L 020E ; -: P1IV_H 020F ; -: PASELC 0216 ; -: PASELC_L 0216 ; -: PASELC_H 0217 ; -: PAIES 0218 ; -: PAIES_L 0218 ; -: PAIES_H 0219 ; -: PAIE 021A ; -: PAIE_L 021A ; -: PAIE_H 021B ; -: PAIFG 021C ; -: PAIFG_L 021C ; -: PAIFG_H 021D ; -: P2IV 021E ; -: P2IV_L 021E ; -: P2IV_H 021F ; -: PBIN 0220 ; -: PBIN_L 0220 ; -: PBIN_H 0221 ; -: PBOUT 0222 ; -: PBOUT_L 0222 ; -: PBOUT_H 0223 ; -: PBDIR 0224 ; -: PBDIR_L 0224 ; -: PBDIR_H 0225 ; -: PBREN 0226 ; -: PBREN_L 0226 ; -: PBREN_H 0227 ; -: PBSEL0 022A ; -: PBSEL0_L 022A ; -: PBSEL0_H 022B ; -: PBSEL1 022C ; -: PBSEL1_L 022C ; -: PBSEL1_H 022D ; -: P3IV 022E ; -: P3IV_L 022E ; -: P3IV_H 022F ; -: PBSELC 0236 ; -: PBSELC_L 0236 ; -: PBSELC_H 0237 ; -: PBIES 0238 ; -: PBIES_L 0238 ; -: PBIES_H 0239 ; -: PBIE 023A ; -: PBIE_L 023A ; -: PBIE_H 023B ; -: PBIFG 023C ; -: PBIFG_L 023C ; -: PBIFG_H 023D ; -: P4IV 023E ; -: P4IV_L 023E ; -: P4IV_H 023F ; -: PCIN 0240 ; -: PCIN_L 0240 ; -: PCIN_H 0241 ; -: PCOUT 0242 ; -: PCOUT_L 0242 ; -: PCOUT_H 0243 ; -: PCDIR 0244 ; -: PCDIR_L 0244 ; -: PCDIR_H 0245 ; -: PCREN 0246 ; -: PCREN_L 0246 ; -: PCREN_H 0247 ; -: PCSEL0 024A ; -: PCSEL0_L 024A ; -: PCSEL0_H 024B ; -: PCSEL1 024C ; -: PCSEL1_L 024C ; -: PCSEL1_H 024D ; -: P5IV 024E ; -: P5IV_L 024E ; -: P5IV_H 024F ; -: PCSELC 0256 ; -: PCSELC_L 0256 ; -: PCSELC_H 0257 ; -: PCIES 0258 ; -: PCIES_L 0258 ; -: PCIES_H 0259 ; -: PCIE 025A ; -: PCIE_L 025A ; -: PCIE_H 025B ; -: PCIFG 025C ; -: PCIFG_L 025C ; -: PCIFG_H 025D ; -: P6IV 025E ; -: P6IV_L 025E ; -: P6IV_H 025F ; -: PJIN 0320 ; -: PJIN_L 0320 ; -: PJIN_H 0321 ; -: PJOUT 0322 ; -: PJOUT_L 0322 ; -: PJOUT_H 0323 ; -: PJDIR 0324 ; -: PJDIR_L 0324 ; -: PJDIR_H 0325 ; -: PJREN 0326 ; -: PJREN_L 0326 ; -: PJREN_H 0327 ; -: PJSEL0 032A ; -: PJSEL0_L 032A ; -: PJSEL0_H 032B ; -: PJSEL1 032C ; -: PJSEL1_L 032C ; -: PJSEL1_H 032D ; -: PJSELC 0336 ; -: PJSELC_L 0336 ; -: PJSELC_H 0337 ; -: P1IN 0200 ; -: P2IN 0201 ; -: P2OUT 0203 ; -: P1OUT 0202 ; -: P1DIR 0204 ; -: P2DIR 0205 ; -: P1REN 0206 ; -: P2REN 0207 ; -: P1SEL0 020A ; -: P2SEL0 020B ; -: P1SEL1 020C ; -: P2SEL1 020D ; -: P1SELC 0216 ; -: P2SELC 0217 ; -: P1IES 0218 ; -: P2IES 0219 ; -: P1IE 021A ; -: P2IE 021B ; -: P1IFG 021C ; -: P2IFG 021D ; -: P3IN 0220 ; -: P4IN 0221 ; -: P3OUT 0222 ; -: P4OUT 0223 ; -: P3DIR 0224 ; -: P4DIR 0225 ; -: P3REN 0226 ; -: P4REN 0227 ; -: P4SEL0 022B ; -: P3SEL0 022A ; -: P3SEL1 022C ; -: P4SEL1 022D ; -: P3SELC 0236 ; -: P4SELC 0237 ; -: P3IES 0238 ; -: P4IES 0239 ; -: P3IE 023A ; -: P4IE 023B ; -: P3IFG 023C ; -: P4IFG 023D ; -: P5IN 0240 ; -: P6IN 0241 ; -: P5OUT 0242 ; -: P6OUT 0243 ; -: P5DIR 0244 ; -: P6DIR 0245 ; -: P5REN 0246 ; -: P6REN 0247 ; -: P5SEL0 024A ; -: P6SEL0 024B ; -: P5SEL1 024C ; -: P6SEL1 024D ; -: P5SELC 0256 ; -: P6SELC 0257 ; -: P5IES 0258 ; -: P6IES 0259 ; -: P5IE 025A ; -: P6IE 025B ; -: P5IFG 025C ; -: P6IFG 025D ; -: FRCTL0 01A0 ; -: FRCTL0_L 01A0 ; -: FRCTL0_H 01A1 ; -: GCCTL0 01A4 ; -: GCCTL0_L 01A4 ; -: GCCTL0_H 01A5 ; -: GCCTL1 01A6 ; -: GCCTL1_L 01A6 ; -: GCCTL1_H 01A7 ; -: MPY 04C0 ; -: MPY_L 04C0 ; -: MPY_H 04C1 ; -: MPYS 04C2 ; -: MPYS_L 04C2 ; -: MPYS_H 04C3 ; -: MAC 04C4 ; -: MAC_L 04C4 ; -: MAC_H 04C5 ; -: MACS 04C6 ; -: MACS_L 04C6 ; -: MACS_H 04C7 ; -: OP2 04C8 ; -: OP2_L 04C8 ; -: OP2_H 04C9 ; -: RESLO 04CA ; -: RESLO_L 04CA ; -: RESLO_H 04CB ; -: RESHI 04CC ; -: RESHI_L 04CC ; -: RESHI_H 04CD ; -: SUMEXT 04CE ; -: SUMEXT_L 04CE ; -: SUMEXT_H 04CF ; -: MPY32L 04D0 ; -: MPY32L_L 04D0 ; -: MPY32L_H 04D1 ; -: MPY32H 04D2 ; -: MPY32H_L 04D2 ; -: MPY32H_H 04D3 ; -: MPYS32L 04D4 ; -: MPYS32L_L 04D4 ; -: MPYS32L_H 04D5 ; -: MPYS32H 04D6 ; -: MPYS32H_L 04D6 ; -: MPYS32H_H 04D7 ; -: MAC32L 04D8 ; -: MAC32L_L 04D8 ; -: MAC32L_H 04D9 ; -: MAC32H 04DA ; -: MAC32H_L 04DA ; -: MAC32H_H 04DB ; -: MACS32L 04DC ; -: MACS32L_L 04DC ; -: MACS32L_H 04DD ; -: MACS32H 04DE ; -: MACS32H_L 04DE ; -: MACS32H_H 04DF ; -: OP2L 04E0 ; -: OP2L_L 04E0 ; -: OP2L_H 04E1 ; -: OP2H 04E2 ; -: OP2H_L 04E2 ; -: OP2H_H 04E3 ; -: RES0 04E4 ; -: RES0_L 04E4 ; -: RES0_H 04E5 ; -: RES1 04E6 ; -: RES1_L 04E6 ; -: RES1_H 04E7 ; -: RES2 04E8 ; -: RES2_L 04E8 ; -: RES2_H 04E9 ; -: RES3 04EA ; -: RES3_L 04EA ; -: RES3_H 04EB ; -: MPY32CTL0 04EC ; -: MPY32CTL0_L 04EC ; -: MPY32CTL0_H 04ED ; -: PMMCTL0 0120 ; -: PMMCTL0_L 0120 ; -: PMMCTL0_H 0121 ; -: PMMCTL1 0122 ; -: PMMCTL1_L 0122 ; -: PMMCTL1_H 0123 ; -: PMMCTL2 0124 ; -: PMMCTL2_L 0124 ; -: PMMCTL2_H 0125 ; -: PMMIFG 012A ; -: PMMIFG_L 012A ; -: PMMIFG_H 012B ; -: PM5CTL0 0130 ; -: PM5CTL0_L 0130 ; -: PM5CTL0_H 0131 ; -: RTCCTL 0300 ; -: RTCCTL_L 0300 ; -: RTCCTL_H 0301 ; -: RTCIV 0304 ; -: RTCIV_L 0304 ; -: RTCIV_H 0305 ; -: RTCMOD 0308 ; -: RTCMOD_L 0308 ; -: RTCMOD_H 0309 ; -: RTCCNT 030C ; -: RTCCNT_L 030C ; -: RTCCNT_H 030D ; -: SFRIE1 0100 ; -: SFRIE1_L 0100 ; -: SFRIE1_H 0101 ; -: SFRIFG1 0102 ; -: SFRIFG1_L 0102 ; -: SFRIFG1_H 0103 ; -: SFRRPCR 0104 ; -: SFRRPCR_L 0104 ; -: SFRRPCR_H 0105 ; -: SYSCTL 0140 ; -: SYSCTL_L 0140 ; -: SYSCTL_H 0141 ; -: SYSBSLC 0142 ; -: SYSBSLC_L 0142 ; -: SYSBSLC_H 0143 ; -: SYSJMBC 0146 ; -: SYSJMBC_L 0146 ; -: SYSJMBC_H 0147 ; -: SYSJMBI0 0148 ; -: SYSJMBI0_L 0148 ; -: SYSJMBI0_H 0149 ; -: SYSJMBI1 014A ; -: SYSJMBI1_L 014A ; -: SYSJMBI1_H 014B ; -: SYSJMBO0 014C ; -: SYSJMBO0_L 014C ; -: SYSJMBO0_H 014D ; -: SYSJMBO1 014E ; -: SYSJMBO1_L 014E ; -: SYSJMBO1_H 014F ; -: SYSUNIV 015A ; -: SYSUNIV_L 015A ; -: SYSUNIV_H 015B ; -: SYSSNIV 015C ; -: SYSSNIV_L 015C ; -: SYSSNIV_H 015D ; -: SYSRSTIV 015E ; -: SYSRSTIV_L 015E ; -: SYSRSTIV_H 015F ; -: SYSCFG0 0160 ; -: SYSCFG0_L 0160 ; -: SYSCFG0_H 0161 ; -: SYSCFG1 0162 ; -: SYSCFG1_L 0162 ; -: SYSCFG1_H 0163 ; -: SYSCFG2 0164 ; -: SYSCFG2_L 0164 ; -: SYSCFG2_H 0165 ; -: SYSCFG3 0166 ; -: SYSCFG3_L 0166 ; -: SYSCFG3_H 0167 ; -: TA0CTL 0380 ; -: TA0CTL_L 0380 ; -: TA0CTL_H 0381 ; -: TA0CCTL0 0382 ; -: TA0CCTL0_L 0382 ; -: TA0CCTL0_H 0383 ; -: TA0CCTL1 0384 ; -: TA0CCTL1_L 0384 ; -: TA0CCTL1_H 0385 ; -: TA0CCTL2 0386 ; -: TA0CCTL2_L 0386 ; -: TA0CCTL2_H 0387 ; -: TA0R 0390 ; -: TA0R_L 0390 ; -: TA0R_H 0391 ; -: TA0CCR0 0392 ; -: TA0CCR0_L 0392 ; -: TA0CCR0_H 0393 ; -: TA0CCR1 0394 ; -: TA0CCR1_L 0394 ; -: TA0CCR1_H 0395 ; -: TA0CCR2 0396 ; -: TA0CCR2_L 0396 ; -: TA0CCR2_H 0397 ; -: TA0EX0 03A0 ; -: TA0EX0_L 03A0 ; -: TA0EX0_H 03A1 ; -: TA0IV 03AE ; -: TA0IV_L 03AE ; -: TA0IV_H 03AF ; -: TA1CTL 03C0 ; -: TA1CTL_L 03C0 ; -: TA1CTL_H 03C1 ; -: TA1CCTL0 03C2 ; -: TA1CCTL0_L 03C2 ; -: TA1CCTL0_H 03C3 ; -: TA1CCTL1 03C4 ; -: TA1CCTL1_L 03C4 ; -: TA1CCTL1_H 03C5 ; -: TA1CCTL2 03C6 ; -: TA1CCTL2_L 03C6 ; -: TA1CCTL2_H 03C7 ; -: TA1R 03D0 ; -: TA1R_L 03D0 ; -: TA1R_H 03D1 ; -: TA1CCR0 03D2 ; -: TA1CCR0_L 03D2 ; -: TA1CCR0_H 03D3 ; -: TA1CCR1 03D4 ; -: TA1CCR1_L 03D4 ; -: TA1CCR1_H 03D5 ; -: TA1CCR2 03D6 ; -: TA1CCR2_L 03D6 ; -: TA1CCR2_H 03D7 ; -: TA1EX0 03E0 ; -: TA1EX0_L 03E0 ; -: TA1EX0_H 03E1 ; -: TA1IV 03EE ; -: TA1IV_L 03EE ; -: TA1IV_H 03EF ; -: TA2CTL 0400 ; -: TA2CTL_L 0400 ; -: TA2CTL_H 0401 ; -: TA2CCTL0 0402 ; -: TA2CCTL0_L 0402 ; -: TA2CCTL0_H 0403 ; -: TA2CCTL1 0404 ; -: TA2CCTL1_L 0404 ; -: TA2CCTL1_H 0405 ; -: TA2CCTL2 0406 ; -: TA2CCTL2_L 0406 ; -: TA2CCTL2_H 0407 ; -: TA2R 0410 ; -: TA2R_L 0410 ; -: TA2R_H 0411 ; -: TA2CCR0 0412 ; -: TA2CCR0_L 0412 ; -: TA2CCR0_H 0413 ; -: TA2CCR1 0414 ; -: TA2CCR1_L 0414 ; -: TA2CCR1_H 0415 ; -: TA2CCR2 0416 ; -: TA2CCR2_L 0416 ; -: TA2CCR2_H 0417 ; -: TA2EX0 0420 ; -: TA2EX0_L 0420 ; -: TA2EX0_H 0421 ; -: TA2IV 042E ; -: TA2IV_L 042E ; -: TA2IV_H 042F ; -: TA3CTL 0440 ; -: TA3CTL_L 0440 ; -: TA3CTL_H 0441 ; -: TA3CCTL0 0442 ; -: TA3CCTL0_L 0442 ; -: TA3CCTL0_H 0443 ; -: TA3CCTL1 0444 ; -: TA3CCTL1_L 0444 ; -: TA3CCTL1_H 0445 ; -: TA3CCTL2 0446 ; -: TA3CCTL2_L 0446 ; -: TA3CCTL2_H 0447 ; -: TA3R 0450 ; -: TA3R_L 0450 ; -: TA3R_H 0451 ; -: TA3CCR0 0452 ; -: TA3CCR0_L 0452 ; -: TA3CCR0_H 0453 ; -: TA3CCR1 0454 ; -: TA3CCR1_L 0454 ; -: TA3CCR1_H 0455 ; -: TA3CCR2 0456 ; -: TA3CCR2_L 0456 ; -: TA3CCR2_H 0457 ; -: TA3EX0 0460 ; -: TA3EX0_L 0460 ; -: TA3EX0_H 0461 ; -: TA3IV 046E ; -: TA3IV_L 046E ; -: TA3IV_H 046F ; -: TB0CTL 0480 ; -: TB0CTL_L 0480 ; -: TB0CTL_H 0481 ; -: TB0CCTL0 0482 ; -: TB0CCTL0_L 0482 ; -: TB0CCTL0_H 0483 ; -: TB0CCTL1 0484 ; -: TB0CCTL1_L 0484 ; -: TB0CCTL1_H 0485 ; -: TB0CCTL2 0486 ; -: TB0CCTL2_L 0486 ; -: TB0CCTL2_H 0487 ; -: TB0CCTL3 0488 ; -: TB0CCTL3_L 0488 ; -: TB0CCTL3_H 0489 ; -: TB0CCTL4 048A ; -: TB0CCTL4_L 048A ; -: TB0CCTL4_H 048B ; -: TB0CCTL5 048C ; -: TB0CCTL5_L 048C ; -: TB0CCTL5_H 048D ; -: TB0CCTL6 048E ; -: TB0CCTL6_L 048E ; -: TB0CCTL6_H 048F ; -: TB0R 0490 ; -: TB0R_L 0490 ; -: TB0R_H 0491 ; -: TB0CCR0 0492 ; -: TB0CCR0_L 0492 ; -: TB0CCR0_H 0493 ; -: TB0CCR1 0494 ; -: TB0CCR1_L 0494 ; -: TB0CCR1_H 0495 ; -: TB0CCR2 0496 ; -: TB0CCR2_L 0496 ; -: TB0CCR2_H 0497 ; -: TB0CCR3 0498 ; -: TB0CCR3_L 0498 ; -: TB0CCR3_H 0499 ; -: TB0CCR4 049A ; -: TB0CCR4_L 049A ; -: TB0CCR4_H 049B ; -: TB0CCR5 049C ; -: TB0CCR5_L 049C ; -: TB0CCR5_H 049D ; -: TB0CCR6 049E ; -: TB0CCR6_L 049E ; -: TB0CCR6_H 049F ; -: TB0EX0 04A0 ; -: TB0EX0_L 04A0 ; -: TB0EX0_H 04A1 ; -: TB0IV 04AE ; -: TB0IV_L 04AE ; -: TB0IV_H 04AF ; -: WDTCTL 01CC ; -: WDTCTL_L 01CC ; -: WDTCTL_H 01CD ; -: CP0CTL0 08E0 ; -: CP0CTL0_L 08E0 ; -: CP0CTL0_H 08E1 ; -: CP0CTL1 08E2 ; -: CP0CTL1_L 08E2 ; -: CP0CTL1_H 08E3 ; -: CP0INT 08E6 ; -: CP0INT_L 08E6 ; -: CP0INT_H 08E7 ; -: CP0IV 08E8 ; -: CP0IV_L 08E8 ; -: CP0IV_H 08E9 ; -: CP0DACCTL 08F0 ; -: CP0DACCTL_L 08F0 ; -: CP0DACCTL_H 08F1 ; -: CP0DACDATA 08F2 ; -: CP0DACDATA_L 08F2 ; -: CP0DACDATA_H 08F3 ; -: UCA0CTLW0 0500 ; -: UCA0CTLW0_L 0500 ; -: UCA0CTLW0_H 0501 ; -: UCA0CTLW1 0502 ; -: UCA0CTLW1_L 0502 ; -: UCA0CTLW1_H 0503 ; -: UCA0BRW 0506 ; -: UCA0BRW_L 0506 ; -: UCA0BRW_H 0507 ; -: UCA0MCTLW 0508 ; -: UCA0MCTLW_L 0508 ; -: UCA0MCTLW_H 0509 ; -: UCA0STATW 050A ; -: UCA0STATW_L 050A ; -: UCA0STATW_H 050B ; -: UCA0RXBUF 050C ; -: UCA0RXBUF_L 050C ; -: UCA0RXBUF_H 050D ; -: UCA0TXBUF 050E ; -: UCA0TXBUF_L 050E ; -: UCA0TXBUF_H 050F ; -: UCA0ABCTL 0510 ; -: UCA0ABCTL_L 0510 ; -: UCA0ABCTL_H 0511 ; -: UCA0IRCTL 0512 ; -: UCA0IRCTL_L 0512 ; -: UCA0IRCTL_H 0513 ; -: UCA0IE 051A ; -: UCA0IE_L 051A ; -: UCA0IE_H 051B ; -: UCA0IFG 051C ; -: UCA0IFG_L 051C ; -: UCA0IFG_H 051D ; -: UCA0IV 051E ; -: UCA0IV_L 051E ; -: UCA0IV_H 051F ; -: UCA1CTLW0 0520 ; -: UCA1CTLW0_L 0520 ; -: UCA1CTLW0_H 0521 ; -: UCA1CTLW1 0522 ; -: UCA1CTLW1_L 0522 ; -: UCA1CTLW1_H 0523 ; -: UCA1BRW 0526 ; -: UCA1BRW_L 0526 ; -: UCA1BRW_H 0527 ; -: UCA1MCTLW 0528 ; -: UCA1MCTLW_L 0528 ; -: UCA1MCTLW_H 0529 ; -: UCA1STATW 052A ; -: UCA1STATW_L 052A ; -: UCA1STATW_H 052B ; -: UCA1RXBUF 052C ; -: UCA1RXBUF_L 052C ; -: UCA1RXBUF_H 052D ; -: UCA1TXBUF 052E ; -: UCA1TXBUF_L 052E ; -: UCA1TXBUF_H 052F ; -: UCA1ABCTL 0530 ; -: UCA1ABCTL_L 0530 ; -: UCA1ABCTL_H 0531 ; -: UCA1IRCTL 0532 ; -: UCA1IRCTL_L 0532 ; -: UCA1IRCTL_H 0533 ; -: UCA1IE 053A ; -: UCA1IE_L 053A ; -: UCA1IE_H 053B ; -: UCA1IFG 053C ; -: UCA1IFG_L 053C ; -: UCA1IFG_H 053D ; -: UCA1IV 053E ; -: UCA1IV_L 053E ; -: UCA1IV_H 053F ; -: UCB0CTLW0 0540 ; -: UCB0CTLW0_L 0540 ; -: UCB0CTLW0_H 0541 ; -: UCB0CTLW1 0542 ; -: UCB0CTLW1_L 0542 ; -: UCB0CTLW1_H 0543 ; -: UCB0BRW 0546 ; -: UCB0BRW_L 0546 ; -: UCB0BRW_H 0547 ; -: UCB0STATW 0548 ; -: UCB0STATW_L 0548 ; -: UCB0STATW_H 0549 ; -: UCB0TBCNT 054A ; -: UCB0TBCNT_L 054A ; -: UCB0TBCNT_H 054B ; -: UCB0RXBUF 054C ; -: UCB0RXBUF_L 054C ; -: UCB0RXBUF_H 054D ; -: UCB0TXBUF 054E ; -: UCB0TXBUF_L 054E ; -: UCB0TXBUF_H 054F ; -: UCB0I2COA0 0554 ; -: UCB0I2COA0_L 0554 ; -: UCB0I2COA0_H 0555 ; -: UCB0I2COA1 0556 ; -: UCB0I2COA1_L 0556 ; -: UCB0I2COA1_H 0557 ; -: UCB0I2COA2 0558 ; -: UCB0I2COA2_L 0558 ; -: UCB0I2COA2_H 0559 ; -: UCB0I2COA3 055A ; -: UCB0I2COA3_L 055A ; -: UCB0I2COA3_H 055B ; -: UCB0ADDRX 055C ; -: UCB0ADDRX_L 055C ; -: UCB0ADDRX_H 055D ; -: UCB0ADDMASK 055E ; -: UCB0ADDMASK_L 055E ; -: UCB0ADDMASK_H 055F ; -: UCB0I2CSA 0560 ; -: UCB0I2CSA_L 0560 ; -: UCB0I2CSA_H 0561 ; -: UCB0IE 056A ; -: UCB0IE_L 056A ; -: UCB0IE_H 056B ; -: UCB0IFG 056C ; -: UCB0IFG_L 056C ; -: UCB0IFG_H 056D ; -: UCB0IV 056E ; -: UCB0IV_L 056E ; -: UCB0IV_H 056F ; -: UCB1CTLW0 0580 ; -: UCB1CTLW0_L 0580 ; -: UCB1CTLW0_H 0581 ; -: UCB1CTLW1 0582 ; -: UCB1CTLW1_L 0582 ; -: UCB1CTLW1_H 0583 ; -: UCB1BRW 0586 ; -: UCB1BRW_L 0586 ; -: UCB1BRW_H 0587 ; -: UCB1STATW 0588 ; -: UCB1STATW_L 0588 ; -: UCB1STATW_H 0589 ; -: UCB1TBCNT 058A ; -: UCB1TBCNT_L 058A ; -: UCB1TBCNT_H 058B ; -: UCB1RXBUF 058C ; -: UCB1RXBUF_L 058C ; -: UCB1RXBUF_H 058D ; -: UCB1TXBUF 058E ; -: UCB1TXBUF_L 058E ; -: UCB1TXBUF_H 058F ; -: UCB1I2COA0 0594 ; -: UCB1I2COA0_L 0594 ; -: UCB1I2COA0_H 0595 ; -: UCB1I2COA1 0596 ; -: UCB1I2COA1_L 0596 ; -: UCB1I2COA1_H 0597 ; -: UCB1I2COA2 0598 ; -: UCB1I2COA2_L 0598 ; -: UCB1I2COA2_H 0599 ; -: UCB1I2COA3 059A ; -: UCB1I2COA3_L 059A ; -: UCB1I2COA3_H 059B ; -: UCB1ADDRX 059C ; -: UCB1ADDRX_L 059C ; -: UCB1ADDRX_H 059D ; -: UCB1ADDMASK 059E ; -: UCB1ADDMASK_L 059E ; -: UCB1ADDMASK_H 059F ; -: UCB1I2CSA 05A0 ; -: UCB1I2CSA_L 05A0 ; -: UCB1I2CSA_H 05A1 ; -: UCB1IE 05AA ; -: UCB1IE_L 05AA ; -: UCB1IE_H 05AB ; -: UCB1IFG 05AC ; -: UCB1IFG_L 05AC ; -: UCB1IFG_H 05AD ; -: UCB1IV 05AE ; -: UCB1IV_L 05AE ; -: UCB1IV_H 05AF ; - -decimal - -: ECOMP0_VECTOR 0 ; -: PORT6_VECTOR 1 ; -: PORT5_VECTOR 2 ; -: PORT4_VECTOR 3 ; -: PORT3_VECTOR 4 ; -: PORT2_VECTOR 5 ; -: PORT1_VECTOR 6 ; -: ADC_VECTOR 7 ; -: EUSCI_B1_VECTOR 8 ; -: EUSCI_B0_VECTOR 9 ; -: EUSCI_A1_VECTOR 10 ; -: EUSCI_A0_VECTOR 11 ; -: WDT_VECTOR 12 ; -: RTC_VECTOR 13 ; -: TIMER0_B1_VECTOR 14 ; -: TIMER0_B0_VECTOR 15 ; -: TIMER3_A1_VECTOR 16 ; -: TIMER3_A0_VECTOR 17 ; -: TIMER2_A1_VECTOR 18 ; -: TIMER2_A0_VECTOR 19 ; -: TIMER1_A1_VECTOR 20 ; -: TIMER1_A0_VECTOR 21 ; -: TIMER0_A1_VECTOR 22 ; -: TIMER0_A0_VECTOR 23 ; - diff --git a/msp430/Makefile b/msp430/Makefile new file mode 100644 index 0000000..8b91764 --- /dev/null +++ b/msp430/Makefile @@ -0,0 +1,12 @@ +dict: lzss + cat msp430fr2476_symbols.ld | grep "^PROVIDE.*" | sed -e "s/^PROVIDE(//" -e "s/[ ][ ]*//" -e "s/=.0x/\\\\x/" -e "s/..);/\\\\x&/" -e "s/);//" > msp430fr2476_symbols.dat + grep -E "^#define \w+\s+\([0-9].*$$" msp430fr2476.h | sed -e "s/).*$$/)/" -e "s/^#define //" -e "s/[ ][ ]*//" -e "s/(0x/\\\\x/" -e "s/..)/\\\\x&/" -e "s/)//" -e "s/(/\\\\x/" -e "s/\\\\x\\\\/\\\\x00\\\\/" > msp430fr2476.dat + cat msp430fr2476_symbols.dat msp430fr2476.dat | tr '\n' '\373' | tr -d '\r' > msp430fr2476_all.dat + @echo "printf ... > msp430fr2476_all.bin" + @printf "$(shell cat msp430fr2476_all.dat)" > msp430fr2476_all.bin + ./lzss e msp430fr2476_all.bin msp430fr2476_all.lzss + ls -l msp430fr2476_all.lzss + xxd -i msp430fr2476_all.lzss > msp430fr2476_all.h + +lzss: lzss.c + diff --git a/msp430/alee-msp430.cpp b/msp430/alee-msp430.cpp index 14ccfd0..c4cd955 100644 --- a/msp430/alee-msp430.cpp +++ b/msp430/alee-msp430.cpp @@ -18,13 +18,17 @@ #include "alee.hpp" #include "libalee/ctype.hpp" +#include "lzss.h" +static const +#include "msp430fr2476_all.h" +#include #include #include "splitmemdictrw.hpp" alignas(sizeof(Cell)) -__attribute__((section(".text"))) +__attribute__((section(".lodict"))) #include "core.fth.h" static char strbuf[80]; @@ -33,6 +37,7 @@ static void readchar(State& state); static void serput(int c); static void serputs(const char *s); static void printint(DoubleCell n, char *buf); +static Error findword(State&, Word); static void initGPIO(); static void initClock(); @@ -40,7 +45,7 @@ static void initUART(); static void Software_Trim(); #define MCLK_FREQ_MHZ (8) // MCLK = 8MHz -//__attribute__((section(".upper.bss"))) +//__attribute__((section(".hidict"))) //static uint8_t hidict[16384]; static Addr isr_list[24] = {}; @@ -56,6 +61,7 @@ int main() (void)alee_dat_len; State state (dict, readchar); + Parser::customParse = findword; serputs("alee forth\n\r"); @@ -156,7 +162,7 @@ void user_sys(State& state) serput(state.pop()); break; case 10: - { auto index = state.pop(); + { auto index = state.pop() - 20; isr_list[index] = state.pop(); } break; case 11: @@ -184,6 +190,49 @@ void user_sys(State& state) } } +#define LZSS_MAGIC_SEPARATOR (0xFB) + +static char lzword[32]; +static int lzwlen; +static char lzbuf[32]; +static char *lzptr; + +Error findword(State& state, Word word) +{ + char *ptr = lzword; + for (auto it = word.begin(&state.dict); it != word.end(&state.dict); ++it) { + *ptr = *it; + if (islower(*ptr)) + *ptr -= 32; + ++ptr; + } + lzwlen = (int)(ptr - lzword); + + lzptr = lzbuf; + lzssinit(msp430fr2476_all_lzss, msp430fr2476_all_lzss_len); + + auto ret = decode([](int c) { + if (c != LZSS_MAGIC_SEPARATOR) { + *lzptr++ = (char)c; + } else { + if (lzwlen == lzptr - lzbuf - 2 && strncmp(lzword, lzbuf, lzptr - lzbuf - 2) == 0) { + lzwlen = (*(lzptr - 2) << 8) | *(lzptr - 1); + return 1; + } else { + lzptr = lzbuf; + } + } + return 0; + }); + + if (ret == EOF) { + return Error::noword; + } else { + Parser::processLiteral(state, (Cell)lzwlen); + return Error::none; + } +} + void initGPIO() { // Unnecessary, but done by TI example @@ -201,9 +250,6 @@ void initGPIO() P3DIR &= ~BIT4; P3REN |= BIT4; P3OUT |= BIT4; P2DIR &= ~BIT3; P2REN |= BIT3; P2OUT |= BIT3; - // XT1 pins (P2.0 and P2.1) - //P2SEL1 |= BIT0 | BIT1; - // Allow GPIO configurations to be applied PM5CTL0 &= ~LOCKLPM5; @@ -224,19 +270,6 @@ void initClock() CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz // default DCODIV as MCLK and SMCLK source - -// // ACLK to XT1 -// do -// { -// CSCTL7 &= ~(XT1OFFG | DCOFFG); // Clear XT1 and DCO fault flag -// SFRIFG1 &= ~OFIFG; -// }while (SFRIFG1 & OFIFG); // Test oscillator fault flag -// -// CSCTL4 = SELMS__DCOCLKDIV | SELA__XT1CLK; // set ACLK = XT1CLK = 32768Hz -// // DCOCLK = MCLK and SMCLK source -// -// // Now that osc is running enable fault interrupt -// SFRIE1 |= OFIE; } void initUART() diff --git a/msp430/lzss.c b/msp430/lzss.c new file mode 100644 index 0000000..9b64d38 --- /dev/null +++ b/msp430/lzss.c @@ -0,0 +1,181 @@ +/* LZSS encoder-decoder (Haruhiko Okumura; public domain) */ + +#include +#include + +#define EI 8 /* typically 10..13 */ +#define EJ 3 /* typically 4..5 */ +#define P 1 /* If match length <= P then output one character */ +#define N (1 << EI) /* buffer size */ +#define F ((1 << EJ) + 1) /* lookahead buffer size */ + +int bit_buffer = 0, bit_mask = 128; +unsigned long codecount = 0, textcount = 0; +unsigned char buffer[N * 2]; +FILE *infile, *outfile; + +void error(void) +{ + printf("Output error\n"); exit(1); +} + +void putbit1(void) +{ + bit_buffer |= bit_mask; + if ((bit_mask >>= 1) == 0) { + if (fputc(bit_buffer, outfile) == EOF) error(); + bit_buffer = 0; bit_mask = 128; codecount++; + } +} + +void putbit0(void) +{ + if ((bit_mask >>= 1) == 0) { + if (fputc(bit_buffer, outfile) == EOF) error(); + bit_buffer = 0; bit_mask = 128; codecount++; + } +} + +void flush_bit_buffer(void) +{ + if (bit_mask != 128) { + if (fputc(bit_buffer, outfile) == EOF) error(); + codecount++; + } +} + +void output1(int c) +{ + int mask; + + putbit1(); + mask = 256; + while (mask >>= 1) { + if (c & mask) putbit1(); + else putbit0(); + } +} + +void output2(int x, int y) +{ + int mask; + + putbit0(); + mask = N; + while (mask >>= 1) { + if (x & mask) putbit1(); + else putbit0(); + } + mask = (1 << EJ); + while (mask >>= 1) { + if (y & mask) putbit1(); + else putbit0(); + } +} + +void encode(void) +{ + int i, j, f1, x, y, r, s, bufferend, c; + + for (i = 0; i < N - F; i++) buffer[i] = ' '; + for (i = N - F; i < N * 2; i++) { + if ((c = fgetc(infile)) == EOF) break; + buffer[i] = c; textcount++; + } + bufferend = i; r = N - F; s = 0; + while (r < bufferend) { + f1 = (F <= bufferend - r) ? F : bufferend - r; + x = 0; y = 1; c = buffer[r]; + for (i = r - 1; i >= s; i--) + if (buffer[i] == c) { + for (j = 1; j < f1; j++) + if (buffer[i + j] != buffer[r + j]) break; + if (j > y) { + x = i; y = j; + } + } + if (y <= P) { y = 1; output1(c); } + else output2(x & (N - 1), y - 2); + r += y; s += y; + if (r >= N * 2 - F) { + for (i = 0; i < N; i++) buffer[i] = buffer[i + N]; + bufferend -= N; r -= N; s -= N; + while (bufferend < N * 2) { + if ((c = fgetc(infile)) == EOF) break; + buffer[bufferend++] = c; textcount++; + } + } + } + flush_bit_buffer(); + printf("text: %ld bytes\n", textcount); + printf("code: %ld bytes (%ld%%)\n", + codecount, (codecount * 100) / textcount); +} + +int getbit(int n) /* get n bits */ +{ + int i, x; + static int buf, mask = 0; + + x = 0; + for (i = 0; i < n; i++) { + if (mask == 0) { + if ((buf = fgetc(infile)) == EOF) return EOF; + mask = 128; + } + x <<= 1; + if (buf & mask) x++; + mask >>= 1; + } + return x; +} + +void decode(void) +{ + int i, j, k, r, c; + + for (i = 0; i < N - F; i++) buffer[i] = ' '; + r = N - F; + while ((c = getbit(1)) != EOF) { + if (c) { + if ((c = getbit(8)) == EOF) break; + fputc(c, outfile); + buffer[r++] = c; r &= (N - 1); + } else { + if ((i = getbit(EI)) == EOF) break; + if ((j = getbit(EJ)) == EOF) break; + for (k = 0; k <= j + 1; k++) { + c = buffer[(i + k) & (N - 1)]; + fputc(c, outfile); + buffer[r++] = c; r &= (N - 1); + } + } + } +} + +int main(int argc, char *argv[]) +{ + int enc; + char *s; + + if (argc != 4) { + printf("Usage: lzss e/d infile outfile\n\te = encode\td = decode\n"); + return 1; + } + s = argv[1]; + if (s[1] == 0 && (*s == 'd' || *s == 'D' || *s == 'e' || *s == 'E')) + enc = (*s == 'e' || *s == 'E'); + else { + printf("? %s\n", s); return 1; + } + if ((infile = fopen(argv[2], "rb")) == NULL) { + printf("? %s\n", argv[2]); return 1; + } + if ((outfile = fopen(argv[3], "wb")) == NULL) { + printf("? %s\n", argv[3]); return 1; + } + if (enc) encode(); else decode(); + fclose(infile); fclose(outfile); + return 0; +} + diff --git a/msp430/lzss.h b/msp430/lzss.h new file mode 100644 index 0000000..5753ba9 --- /dev/null +++ b/msp430/lzss.h @@ -0,0 +1,74 @@ +/* LZSS encoder-decoder (Haruhiko Okumura; public domain) */ +/* Modified by Clyne Sullivan to focus on streamed decompression. */ + +#ifndef EOF +#define EOF (-1) +#endif + +#define EI 8 /* typically 10..13 */ +#define EJ 3 /* typically 4..5 */ +#define N (1 << EI) /* buffer size */ +#define F ((1 << EJ) + 1) /* lookahead buffer size */ + +static unsigned char buffer[N * 2]; +static const unsigned char *inbuffer; +static unsigned int insize, inidx; +static int buf, mask; + +/* Prepares decode() to decompress the given data. */ +void lzssinit(const unsigned char *inb, unsigned int ins) +{ + inbuffer = inb; + insize = ins; + inidx = 0; + buf = 0; + mask = 0; +} + +int getbit(int n) /* get n bits */ +{ + int i, x; + + x = 0; + for (i = 0; i < n; i++) { + if (mask == 0) { + if (inidx >= insize) + return EOF; + buf = inbuffer[inidx++]; + mask = 128; + } + x <<= 1; + if (buf & mask) x++; + mask >>= 1; + } + return x; +} + +/* handleoutput() receives each decompressed byte, return zero if want more. */ +int decode(int (*handleoutput)(int)) +{ + int i, j, k, r, c, ret; + + for (i = 0; i < N - F; i++) buffer[i] = ' '; + r = N - F; + while ((c = getbit(1)) != EOF) { + if (c) { + if ((c = getbit(8)) == EOF) break; + if ((ret = handleoutput(c))) + return ret; + buffer[r++] =(unsigned char) c; r &= (N - 1); + } else { + if ((i = getbit(EI)) == EOF) break; + if ((j = getbit(EJ)) == EOF) break; + for (k = 0; k <= j + 1; k++) { + c = buffer[(i + k) & (N - 1)]; + if ((ret = handleoutput(c))) + return ret; + buffer[r++] = (unsigned char)c; r &= (N - 1); + } + } + } + + return EOF; +} + diff --git a/msp430/msp430fr2476.h b/msp430/msp430fr2476.h new file mode 100644 index 0000000..33c8ee8 --- /dev/null +++ b/msp430/msp430fr2476.h @@ -0,0 +1,4301 @@ +//***************************************************************************** +// +// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//**************************************************************************** + +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430 microcontroller. +* +* This file supports assembler and C development for +* MSP430FR2476 devices. +* +********************************************************************/ + +#ifndef __MSP430FR2476 +#define __MSP430FR2476 + +#define __MSP430_HEADER_VERSION__ 1212 + +#define __MSP430_HAS_MSP430XV2_CPU__ /* CPU type */ +#define __MSP430FR2XX_4XX_FAMILY__ + +#include "in430.h" + +#define __MSP430_TI_HEADERS__ + +#ifndef __AUTOGENERATED__ +#define __AUTOGENERATED__ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001) +#define BIT1 (0x0002) +#define BIT2 (0x0004) +#define BIT3 (0x0008) +#define BIT4 (0x0010) +#define BIT5 (0x0020) +#define BIT6 (0x0040) +#define BIT7 (0x0080) +#define BIT8 (0x0100) +#define BIT9 (0x0200) +#define BITA (0x0400) +#define BITB (0x0800) +#define BITC (0x1000) +#define BITD (0x2000) +#define BITE (0x4000) +#define BITF (0x8000) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001) +#define Z (0x0002) +#define N (0x0004) +#define V (0x0100) +#define GIE (0x0008) +#define CPUOFF (0x0010) +#define OSCOFF (0x0020) +#define SCG0 (0x0040) +#define SCG1 (0x0080) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#ifndef __STDC__ /* Begin #defines for assembler */ +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) +/* End #defines for assembler */ + +#else /* Begin #defines for C */ +#define LPM0_bits (CPUOFF) +#define LPM1_bits (SCG0+CPUOFF) +#define LPM2_bits (SCG1+CPUOFF) +#define LPM3_bits (SCG1+SCG0+CPUOFF) +#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) + +#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ +#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ +#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ +#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ +#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ +#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ +#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ +#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ +#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ +#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#endif /* End #defines for C */ + +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ + + +/***************************************************************************** + ADC Registers +*****************************************************************************/ + +#define __MSP430_HAS_ADC__ /* Definition to show that module is available */ +#define __MSP430_BASEADDRESS_ADC__ 0x0700 +#define ADC_BASE __MSP430_BASEADDRESS_ADC__ + +sfr_w(ADCCTL0); /* ADC Control 0 */ +sfr_b(ADCCTL0_L); +sfr_b(ADCCTL0_H); +sfr_w(ADCCTL1); /* ADC Control 1 */ +sfr_b(ADCCTL1_L); +sfr_b(ADCCTL1_H); +sfr_w(ADCCTL2); /* ADC Control 2 */ +sfr_b(ADCCTL2_L); +sfr_b(ADCCTL2_H); +sfr_w(ADCLO); /* ADC Window Comparator Low Threshold Register */ +sfr_b(ADCLO_L); +sfr_b(ADCLO_H); +sfr_w(ADCHI); /* ADC Window Comparator High Threshold Register */ +sfr_b(ADCHI_L); +sfr_b(ADCHI_H); +sfr_w(ADCMCTL0); /* ADC Conversion Memory Control Register */ +sfr_b(ADCMCTL0_L); +sfr_b(ADCMCTL0_H); +sfr_w(ADCMEM0); /* ADC Conversion Memory Register */ +sfr_b(ADCMEM0_L); +sfr_b(ADCMEM0_H); +sfr_w(ADCIE); /* ADC Interrupt Enable 0 */ +sfr_b(ADCIE_L); +sfr_b(ADCIE_H); +sfr_w(ADCIFG); /* ADC Interrupt Flag */ +sfr_b(ADCIFG_L); +sfr_b(ADCIFG_H); +sfr_w(ADCIV); /* ADC Interrupt Vector */ +sfr_b(ADCIV_L); +sfr_b(ADCIV_H); + +/* ADC Register Offsets */ +#define OFS_ADCCTL0 (0x0000) +#define OFS_ADCCTL1 (0x0002) +#define OFS_ADCCTL2 (0x0004) +#define OFS_ADCLO (0x0006) +#define OFS_ADCHI (0x0008) +#define OFS_ADCMCTL0 (0x000A) +#define OFS_ADCMEM0 (0x0012) +#define OFS_ADCIE (0x001A) +#define OFS_ADCIFG (0x001C) +#define OFS_ADCIV (0x001E) + +/* ADC Control Bits */ + +/* ADCCTL0 Control Bits */ +#define ADCSC (0x0001) /* start conversion */ +#define ADCSC_0 (0x0000) /* No sample-and-conversion-start */ +#define ADCSC_1 (0x0001) /* Start sample-and-conversion */ +#define ADCENC (0x0002) /* enable conversion */ +#define ADCENC_0 (0x0000) /* ADC disabled */ +#define ADCENC_1 (0x0002) /* ADC enabled */ +#define ADCON (0x0010) /* ADC on */ +#define ADCON_0 (0x0000) /* ADC off */ +#define ADCON_1 (0x0010) /* ADC on */ +#define ADCMSC (0x0080) /* sample-and-hold time. */ +#define ADCMSC_0 (0x0000) /* The sampling timer requires a rising edge of the SHI signal to + trigger each sample-and-convert. */ +#define ADCMSC_1 (0x0080) /* The incidence of a positive(or for devices first rising edge + of the) SHI signal triggers the sampling timer, but further + sample-and-conversions are performed automatically as soon as + the prior conversion is completed. */ +#define ADCSHT (0x0f00) /* sample-and-hold time. */ +#define ADCSHT0 (0x0100) /* sample-and-hold time. */ +#define ADCSHT1 (0x0200) /* sample-and-hold time. */ +#define ADCSHT2 (0x0400) /* sample-and-hold time. */ +#define ADCSHT3 (0x0800) /* sample-and-hold time. */ +#define ADCSHT_0 (0x0000) /* 4 ADCCLK cycles */ +#define ADCSHT_1 (0x0100) /* 8 ADCCLK cycles */ +#define ADCSHT_2 (0x0200) /* 16 ADCCLK cycles */ +#define ADCSHT_3 (0x0300) /* 32 ADCCLK cycles */ +#define ADCSHT_4 (0x0400) /* 64 ADCCLK cycles */ +#define ADCSHT_5 (0x0500) /* 96 ADCCLK cycles */ +#define ADCSHT_6 (0x0600) /* 128 ADCCLK cycles */ +#define ADCSHT_7 (0x0700) /* 192 ADCCLK cycles */ +#define ADCSHT_8 (0x0800) /* 256 ADCCLK cycles */ +#define ADCSHT_9 (0x0900) /* 384 ADCCLK cycles */ +#define ADCSHT_10 (0x0a00) /* 512 ADCCLK cycles */ +#define ADCSHT_11 (0x0b00) /* 768 ADCCLK cycles */ +#define ADCSHT_12 (0x0c00) /* 1024 ADCCLK cycles */ +#define ADCSHT_13 (0x0d00) /* 1024 ADCCLK cycles */ +#define ADCSHT_14 (0x0e00) /* 1024 ADCCLK cycles */ +#define ADCSHT_15 (0x0f00) /* 1024 ADCCLK cycles */ + +/* ADCCTL1 Control Bits */ +#define ADCBUSY (0x0001) /* ADC busy */ +#define ADCBUSY_0 (0x0000) /* No operation is active. */ +#define ADCBUSY_1 (0x0001) /* A sequence, sample, or conversion is active. */ +#define ADCCONSEQ (0x0006) /* conversion sequence mode select */ +#define ADCCONSEQ0 (0x0002) /* conversion sequence mode select */ +#define ADCCONSEQ1 (0x0004) /* conversion sequence mode select */ +#define ADCCONSEQ_0 (0x0000) /* Single-channel, single-conversion */ +#define ADCCONSEQ_1 (0x0002) /* Sequence-of-channels */ +#define ADCCONSEQ_2 (0x0004) /* Repeat-single-channel */ +#define ADCCONSEQ_3 (0x0006) /* Repeat-sequence-of-channels */ +#define ADCSSEL (0x0018) /* clock source select */ +#define ADCSSEL0 (0x0008) /* clock source select */ +#define ADCSSEL1 (0x0010) /* clock source select */ +#define ADCSSEL_0 (0x0000) /* ADCOSC (MODOSC) */ +#define ADCSSEL_1 (0x0008) /* ACLK */ +#define ADCSSEL_2 (0x0010) /* MCLK */ +#define ADCSSEL_3 (0x0018) /* SMCLK */ +#define ADCDIV (0x00e0) /* clock divider */ +#define ADCDIV0 (0x0020) /* clock divider */ +#define ADCDIV1 (0x0040) /* clock divider */ +#define ADCDIV2 (0x0080) /* clock divider */ +#define ADCDIV_0 (0x0000) /* /1 */ +#define ADCDIV_1 (0x0020) /* /2 */ +#define ADCDIV_2 (0x0040) /* /3 */ +#define ADCDIV_3 (0x0060) /* /4 */ +#define ADCDIV_4 (0x0080) /* /5 */ +#define ADCDIV_5 (0x00a0) /* /6 */ +#define ADCDIV_6 (0x00c0) /* /7 */ +#define ADCDIV_7 (0x00e0) /* /8 */ +#define ADCISSH (0x0100) /* invert signal sample-and-hold */ +#define ADCISSH_0 (0x0000) /* The sample-input signal is not inverted. */ +#define ADCISSH_1 (0x0100) /* The sample-input signal is inverted. */ +#define ADCSHP (0x0200) /* sample-and-hold pulse-mode select */ +#define ADCSHP_0 (0x0000) /* SAMPCON signal is sourced from the sample-input signal. */ +#define ADCSHP_1 (0x0200) /* SAMPCON signal is sourced from the sampling timer. */ +#define ADCSHS (0x0c00) /* sample-and-hold source select */ +#define ADCSHS0 (0x0400) /* sample-and-hold source select */ +#define ADCSHS1 (0x0800) /* sample-and-hold source select */ +#define ADCSHS_0 (0x0000) /* ADCSC bit */ +#define ADCSHS_1 (0x0400) /* see the device-specific data sheet for source */ +#define ADCSHS_2 (0x0800) /* see the device-specific data sheet for source */ +#define ADCSHS_3 (0x0c00) /* see the device-specific data sheet for source */ + +/* ADCCTL2 Control Bits */ +#define ADCDF (0x0008) /* data read-back format */ +#define ADCDF_0 (0x0000) /* Binary unsigned. Theoretically the analog input voltage V(REF) + results in 0000h, the analog input voltage +V(REF) results in + 03FFh. */ +#define ADCDF_1 (0x0008) /* Signed binary (2s complement), left aligned. Theoretically the + analog input voltage V(REF) results in 8000h, the analog input + voltage +V(REF) results in 7FC0h. */ +#define ADCRES (0x0030) /* resolution */ +#define ADCRES0 (0x0010) /* resolution */ +#define ADCRES1 (0x0020) /* resolution */ +#define ADCRES_0 (0x0000) /* 8 bit */ +#define ADCRES_1 (0x0010) /* 10 bit */ +#define ADCRES_2 (0x0020) /* 12 bit */ +#define ADCRES_3 (0x0030) /* Reserved */ +#define ADCSR (0x0004) /* ADC sampling rate. */ +#define ADCPDIV (0x0300) /* */ +#define ADCPDIV0 (0x0100) /* */ +#define ADCPDIV1 (0x0200) /* */ +#define ADCPDIV_0 (0x0000) /* Predivide by 1 */ +#define ADCPDIV_1 (0x0100) /* Predivide by 4 */ +#define ADCPDIV_2 (0x0200) /* Predivide by 64 */ +#define ADCPDIV_3 (0x0300) /* Reserved */ +#define ADCPDIV__1 (0x0000) /* Predivide by 1 */ +#define ADCPDIV__4 (0x0100) /* Predivide by 4 */ +#define ADCPDIV__64 (0x0200) /* Predivide by 64 */ + +/* ADCMCTL0 Control Bits */ +#define ADCINCH (0x000f) /* Input channel select */ +#define ADCINCH0 (0x0001) /* Input channel select */ +#define ADCINCH1 (0x0002) /* Input channel select */ +#define ADCINCH2 (0x0004) /* Input channel select */ +#define ADCINCH3 (0x0008) /* Input channel select */ +#define ADCINCH_0 (0x0000) /* A0 - see device-specific data sheet */ +#define ADCINCH_1 (0x0001) /* A1 - see device-specific data sheet */ +#define ADCINCH_2 (0x0002) /* A2 - see device-specific data sheet */ +#define ADCINCH_3 (0x0003) /* A3 - see device-specific data sheet */ +#define ADCINCH_4 (0x0004) /* A4 - see device-specific data sheet */ +#define ADCINCH_5 (0x0005) /* A5 - see device-specific data sheet */ +#define ADCINCH_6 (0x0006) /* A2 - see device-specific data sheet */ +#define ADCINCH_7 (0x0007) /* A7 - see device-specific data sheet */ +#define ADCINCH_8 (0x0008) /* A8 - see device-specific data sheet */ +#define ADCINCH_9 (0x0009) /* A9 - see device-specific data sheet */ +#define ADCINCH_10 (0x000a) /* A10 - see device-specific data sheet */ +#define ADCINCH_11 (0x000b) /* A11 - see device-specific data sheet */ +#define ADCINCH_12 (0x000c) /* A12 - see device-specific data sheet */ +#define ADCINCH_13 (0x000d) /* A13 - see device-specific data sheet */ +#define ADCINCH_14 (0x000e) /* A14 - see device-specific data sheet */ +#define ADCINCH_15 (0x000f) /* A15 - see device-specific data sheet */ +#define ADCSREF (0x0070) /* */ +#define ADCSREF0 (0x0010) /* */ +#define ADCSREF1 (0x0020) /* */ +#define ADCSREF2 (0x0040) /* */ +#define ADCSREF_0 (0x0000) /* 000b = V(R+) = AVCC and V(R-) = AVSS */ +#define ADCSREF_1 (0x0010) /* 001b = V(R+) = VREF and V(R-) = AVSS */ +#define ADCSREF_2 (0x0020) /* 010b = V(R+) = VEREF+ buffered and V(R-) = AVSS */ +#define ADCSREF_3 (0x0030) /* 011b =V(R+) = VEREF+ and V(R-) = AVSS */ +#define ADCSREF_4 (0x0040) /* 100b = V(R+) = AVCC and V(R-) = VEREF- */ +#define ADCSREF_5 (0x0050) /* 101b = V(R+) = VREF and V(R-) = VEREF- */ +#define ADCSREF_6 (0x0060) /* 110b = V(R+) = VEREF+ buffered and V(R-) = VEREF- */ +#define ADCSREF_7 (0x0070) /* 111b = V(R+) = VEREF+ and V(R-) = VEREF- */ +#define EXPCHEN (0x0100) /* */ +#define EXPCHEN_0 (0x0000) /* ADC channel expanded disable */ +#define EXPCHEN_1 (0x0100) /* ADC channel expanded enable */ + +/* ADCMEM0 Control Bits */ +#define CONVERSION_RESULTS (0xffff) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS0 (0x0001) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS1 (0x0002) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS2 (0x0004) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS3 (0x0008) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS4 (0x0010) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS5 (0x0020) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS6 (0x0040) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS7 (0x0080) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS8 (0x0100) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS9 (0x0200) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS10 (0x0400) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS11 (0x0800) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS12 (0x1000) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS13 (0x2000) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS14 (0x4000) /* Conversion Results/Reset Value is undefined */ +#define CONVERSION_RESULTS15 (0x8000) /* Conversion Results/Reset Value is undefined */ + +/* ADCIE Control Bits */ +#define ADCIE0 (0x0001) /* */ +#define ADCIE0_0 (0x0000) /* 0b = Interrupt disabled */ +#define ADCIE0_1 (0x0001) /* 1b = Interrupt enabled */ +#define ADCINIE (0x0002) /* */ +#define ADCINIE_0 (0x0000) /* 0b = Inside of window interrupt disabled */ +#define ADCINIE_1 (0x0002) /* 1b = Inside of window interrupt enabled */ +#define ADCLOIE (0x0004) /* */ +#define ADCLOIE_0 (0x0000) /* 0b = Below lower threshold interrupt disabled */ +#define ADCLOIE_1 (0x0004) /* 1b = Below lower threshold interrupt enabled */ +#define ADCHIIE (0x0008) /* */ +#define ADCHIIE_0 (0x0000) /* 0b = Above upper threshold interrupt disabled */ +#define ADCHIIE_1 (0x0008) /* 1b = Above upper threshold interrupt enabled */ +#define ADCOVIE (0x0010) /* */ +#define ADCOVIE_0 (0x0000) /* 0b = Overflow interrupt disabled */ +#define ADCOVIE_1 (0x0010) /* 1b = Overflow interrupt enabled */ +#define ADCTOVIE (0x0020) /* */ +#define ADCTOVIE_0 (0x0000) /* 0b = Conversion time overflow interrupt disabled */ +#define ADCTOVIE_1 (0x0020) /* 1b = Conversion time overflow interrupt enabled */ + +/* ADCIFG Control Bits */ +#define ADCIFG0 (0x0001) /* ADCMEM0 interrupt flag */ +#define ADCIFG0_0 (0x0000) /* No interrupt pending */ +#define ADCIFG0_1 (0x0001) /* Interrupt pending */ +#define ADCINIFG (0x0002) /* */ +#define ADCINIFG_0 (0x0000) /* No interrupt pending */ +#define ADCINIFG_1 (0x0002) /* Interrupt pending */ +#define ADCLOIFG (0x0004) /* */ +#define ADCLOIFG_0 (0x0000) /* No interrupt pending */ +#define ADCLOIFG_1 (0x0004) /* Interrupt pending */ +#define ADCHIIFG (0x0008) /* */ +#define ADCHIIFG_0 (0x0000) /* No interrupt pending */ +#define ADCHIIFG_1 (0x0008) /* Interrupt pending */ +#define ADCOVIFG (0x0010) /* */ +#define ADCOVIFG_0 (0x0000) /* No interrupt pending */ +#define ADCOVIFG_1 (0x0010) /* Interrupt pending */ +#define ADCTOVIFG (0x0020) /* */ +#define ADCTOVIFG_1 (0x0020) /* Interrupt pending */ + +/* ADCIV Control Bits */ +#define ADCIV0 (0x0001) /* interrupt vector value */ +#define ADCIV1 (0x0002) /* interrupt vector value */ +#define ADCIV2 (0x0004) /* interrupt vector value */ +#define ADCIV3 (0x0008) /* interrupt vector value */ +#define ADCIV4 (0x0010) /* interrupt vector value */ +#define ADCIV5 (0x0020) /* interrupt vector value */ +#define ADCIV6 (0x0040) /* interrupt vector value */ +#define ADCIV7 (0x0080) /* interrupt vector value */ +#define ADCIV8 (0x0100) /* interrupt vector value */ +#define ADCIV9 (0x0200) /* interrupt vector value */ +#define ADCIV10 (0x0400) /* interrupt vector value */ +#define ADCIV11 (0x0800) /* interrupt vector value */ +#define ADCIV12 (0x1000) /* interrupt vector value */ +#define ADCIV13 (0x2000) /* interrupt vector value */ +#define ADCIV14 (0x4000) /* interrupt vector value */ +#define ADCIV15 (0x8000) /* interrupt vector value */ +#define ADCIV_0 (0x0000) /* No interrupt pending */ +#define ADCIV_2 (0x0002) /* Interrupt Source: ADCMEM0 overflow; Interrupt Flag: ADCOVIFG; + Interrupt Priority: Highest */ +#define ADCIV_4 (0x0004) /* Interrupt Source: Conversion time overflow; Interrupt Flag: + ADCTOVIFG */ +#define ADCIV_6 (0x0006) /* Interrupt Source: ADCHI Interrupt flag; Interrupt Flag: + ADCHIIFG */ +#define ADCIV_8 (0x0008) /* Interrupt Source: ADCLO Interrupt flag; Interrupt Flag: + ADCLOIFG */ +#define ADCIV_10 (0x000a) /* nterrupt Source: ADCIN Interrupt flag; Interrupt Flag: + ADCINIFG */ +#define ADCIV_12 (0x000c) /* Interrupt Source: ADC memory Interrupt flag; Interrupt Flag: + ADCIFG0; Interrupt Priority: Lowest */ +#define ADCIV__NONE (0x0000) /* No interrupt pending */ +#define ADCIV__ADCOVIFG (0x0002) /* Interrupt Source: ADCMEM0 overflow; Interrupt Flag: ADCOVIFG; + Interrupt Priority: Highest */ +#define ADCIV__ADCTOVIFG (0x0004) /* Interrupt Source: Conversion time overflow; Interrupt Flag: + ADCTOVIFG */ +#define ADCIV__ADCHIIFG (0x0006) /* Interrupt Source: ADCHI Interrupt flag; Interrupt Flag: + ADCHIIFG */ +#define ADCIV__ADCLOIFG (0x0008) /* Interrupt Source: ADCLO Interrupt flag; Interrupt Flag: + ADCLOIFG */ +#define ADCIV__ADCINIFG (0x000a) /* nterrupt Source: ADCIN Interrupt flag; Interrupt Flag: + ADCINIFG */ +#define ADCIV__ADCIFG0 (0x000c) /* Interrupt Source: ADC memory Interrupt flag; Interrupt Flag: + ADCIFG0; Interrupt Priority: Lowest */ + + +/***************************************************************************** + BKMEM Registers +*****************************************************************************/ + +#define __MSP430_HAS_BKMEM__ /* Definition to show that module is available */ +#define __MSP430_BASEADDRESS_BKMEM__ 0x0660 +#define BKMEM_BASE __MSP430_BASEADDRESS_BKMEM__ + +sfr_w(BAKMEM0); /* Backup Memory registers. Backup Memory 0. */ +sfr_b(BAKMEM0_L); +sfr_b(BAKMEM0_H); +sfr_w(BAKMEM1); /* Backup Memory 1. */ +sfr_b(BAKMEM1_L); +sfr_b(BAKMEM1_H); +sfr_w(BAKMEM2); /* Backup Memory 2. */ +sfr_b(BAKMEM2_L); +sfr_b(BAKMEM2_H); +sfr_w(BAKMEM3); /* Backup Memory 3. */ +sfr_b(BAKMEM3_L); +sfr_b(BAKMEM3_H); +sfr_w(BAKMEM4); /* Backup Memory 4. */ +sfr_b(BAKMEM4_L); +sfr_b(BAKMEM4_H); +sfr_w(BAKMEM5); /* Backup Memory 5. */ +sfr_b(BAKMEM5_L); +sfr_b(BAKMEM5_H); +sfr_w(BAKMEM6); /* Backup Memory 6. */ +sfr_b(BAKMEM6_L); +sfr_b(BAKMEM6_H); +sfr_w(BAKMEM7); /* Backup Memory 7. */ +sfr_b(BAKMEM7_L); +sfr_b(BAKMEM7_H); +sfr_w(BAKMEM8); /* Backup Memory 8. */ +sfr_b(BAKMEM8_L); +sfr_b(BAKMEM8_H); +sfr_w(BAKMEM9); /* Backup Memory 9. */ +sfr_b(BAKMEM9_L); +sfr_b(BAKMEM9_H); +sfr_w(BAKMEM10); /* Backup Memory registers. Backup Memory 10. */ +sfr_b(BAKMEM10_L); +sfr_b(BAKMEM10_H); +sfr_w(BAKMEM11); /* Backup Memory 11. */ +sfr_b(BAKMEM11_L); +sfr_b(BAKMEM11_H); +sfr_w(BAKMEM12); /* Backup Memory 12. */ +sfr_b(BAKMEM12_L); +sfr_b(BAKMEM12_H); +sfr_w(BAKMEM13); /* Backup Memory 13. */ +sfr_b(BAKMEM13_L); +sfr_b(BAKMEM13_H); +sfr_w(BAKMEM14); /* Backup Memory 14. */ +sfr_b(BAKMEM14_L); +sfr_b(BAKMEM14_H); +sfr_w(BAKMEM15); /* Backup Memory 15. */ +sfr_b(BAKMEM15_L); +sfr_b(BAKMEM15_H); + +/* BKMEM Register Offsets */ +#define OFS_BAKMEM0 (0x0000) +#define OFS_BAKMEM1 (0x0002) +#define OFS_BAKMEM2 (0x0004) +#define OFS_BAKMEM3 (0x0006) +#define OFS_BAKMEM4 (0x0008) +#define OFS_BAKMEM5 (0x000A) +#define OFS_BAKMEM6 (0x000C) +#define OFS_BAKMEM7 (0x000E) +#define OFS_BAKMEM8 (0x0010) +#define OFS_BAKMEM9 (0x0012) +#define OFS_BAKMEM10 (0x0014) +#define OFS_BAKMEM11 (0x0016) +#define OFS_BAKMEM12 (0x0018) +#define OFS_BAKMEM13 (0x001A) +#define OFS_BAKMEM14 (0x001C) +#define OFS_BAKMEM15 (0x001E) + +/* No control bits available or already defined for another module */ + +/***************************************************************************** + CRC Registers +*****************************************************************************/ + +#define __MSP430_HAS_CRC__ /* Definition to show that module is available */ +#define __MSP430_BASEADDRESS_CRC__ 0x01C0 +#define CRC_BASE __MSP430_BASEADDRESS_CRC__ + +sfr_w(CRCDI); /* CRC Data In */ +sfr_b(CRCDI_L); +sfr_b(CRCDI_H); +sfr_w(CRCDIRB); /* CRC Data In Reverse Byte */ +sfr_b(CRCDIRB_L); +sfr_b(CRCDIRB_H); +sfr_w(CRCINIRES); /* CRC Initialization and Result */ +sfr_b(CRCINIRES_L); +sfr_b(CRCINIRES_H); +sfr_w(CRCRESR); /* CRC Result Reverse */ +sfr_b(CRCRESR_L); +sfr_b(CRCRESR_H); + +/* CRC Register Offsets */ +#define OFS_CRCDI (0x0000) +#define OFS_CRCDIRB (0x0002) +#define OFS_CRCINIRES (0x0004) +#define OFS_CRCRESR (0x0006) + +/* No control bits available or already defined for another module */ + +/***************************************************************************** + CS Registers +*****************************************************************************/ + +#define __MSP430_HAS_CS__ /* Definition to show that module is available */ +#define __MSP430_BASEADDRESS_CS__ 0x0180 +#define CS_BASE __MSP430_BASEADDRESS_CS__ + +sfr_w(CSCTL0); /* Clock System Control 0 */ +sfr_b(CSCTL0_L); +sfr_b(CSCTL0_H); +sfr_w(CSCTL1); /* Clock System Control 1 */ +sfr_b(CSCTL1_L); +sfr_b(CSCTL1_H); +sfr_w(CSCTL2); /* Clock System Control 2 */ +sfr_b(CSCTL2_L); +sfr_b(CSCTL2_H); +sfr_w(CSCTL3); /* Clock System Control 3 */ +sfr_b(CSCTL3_L); +sfr_b(CSCTL3_H); +sfr_w(CSCTL4); /* Clock System Control 4 */ +sfr_b(CSCTL4_L); +sfr_b(CSCTL4_H); +sfr_w(CSCTL5); /* Clock System Control 5 */ +sfr_b(CSCTL5_L); +sfr_b(CSCTL5_H); +sfr_w(CSCTL6); /* Clock System Control 6 */ +sfr_b(CSCTL6_L); +sfr_b(CSCTL6_H); +sfr_w(CSCTL7); /* Clock System Control Register 7 */ +sfr_b(CSCTL7_L); +sfr_b(CSCTL7_H); +sfr_w(CSCTL8); /* Clock System Control Register 8 */ +sfr_b(CSCTL8_L); +sfr_b(CSCTL8_H); + +/* CS Register Offsets */ +#define OFS_CSCTL0 (0x0000) +#define OFS_CSCTL1 (0x0002) +#define OFS_CSCTL2 (0x0004) +#define OFS_CSCTL3 (0x0006) +#define OFS_CSCTL4 (0x0008) +#define OFS_CSCTL5 (0x000A) +#define OFS_CSCTL6 (0x000C) +#define OFS_CSCTL7 (0x000E) +#define OFS_CSCTL8 (0x0010) + +/* CS Control Bits */ + +/* CSCTL0 Control Bits */ +#define DCO (0x01ff) /* */ +#define DCO0 (0x0001) /* */ +#define DCO1 (0x0002) /* */ +#define DCO2 (0x0004) /* */ +#define DCO3 (0x0008) /* */ +#define DCO4 (0x0010) /* */ +#define DCO5 (0x0020) /* */ +#define DCO6 (0x0040) /* */ +#define DCO7 (0x0080) /* */ +#define DCO8 (0x0100) /* */ +#define MOD (0x3e00) /* */ +#define MOD0 (0x0200) /* */ +#define MOD1 (0x0400) /* */ +#define MOD2 (0x0800) /* */ +#define MOD3 (0x1000) /* */ +#define MOD4 (0x2000) /* */ + +/* CSCTL1 Control Bits */ +#define DISMOD (0x0001) /* */ +#define DISMOD_0 (0x0000) /* Modulation enabled */ +#define DISMOD_1 (0x0001) /* Modulation disabled */ +#define DCORSEL (0x000e) /* */ +#define DCORSEL0 (0x0002) /* */ +#define DCORSEL1 (0x0004) /* */ +#define DCORSEL2 (0x0008) /* */ +#define DCORSEL_0 (0x0000) /* 1 MHz */ +#define DCORSEL_1 (0x0002) /* 2 MHz */ +#define DCORSEL_2 (0x0004) /* 4 MHz */ +#define DCORSEL_3 (0x0006) /* 8 MHz */ +#define DCORSEL_4 (0x0008) /* 12 MHz */ +#define DCORSEL_5 (0x000a) /* 16 MHz */ +#define DCORSEL_6 (0x000c) /* 20 MHz(Only avaliable in 24MHz clock system) */ +#define DCORSEL_7 (0x000e) /* 24 MHz(Only avaliable in 24MHz clock system) */ +#define DCOFTRIM (0x0070) /* */ +#define DCOFTRIM0 (0x0010) /* */ +#define DCOFTRIM1 (0x0020) /* */ +#define DCOFTRIM2 (0x0040) /* */ +#define DCOFTRIMEN (0x0080) /* */ +#define DCOFTRIMEN_0 (0x0000) /* Disable frequency trim */ +#define DCOFTRIMEN_1 (0x0080) /* Enable frequency trim */ + +/* CSCTL2 Control Bits */ +#define FLLN (0x03ff) /* */ +#define FLLN0 (0x0001) /* */ +#define FLLN1 (0x0002) /* */ +#define FLLN2 (0x0004) /* */ +#define FLLN3 (0x0008) /* */ +#define FLLN4 (0x0010) /* */ +#define FLLN5 (0x0020) /* */ +#define FLLN6 (0x0040) /* */ +#define FLLN7 (0x0080) /* */ +#define FLLN8 (0x0100) /* */ +#define FLLN9 (0x0200) /* */ +#define FLLD (0x7000) /* */ +#define FLLD0 (0x1000) /* */ +#define FLLD1 (0x2000) /* */ +#define FLLD2 (0x4000) /* */ +#define FLLD_0 (0x0000) /* fDCOCLK / 1 */ +#define FLLD_1 (0x1000) /* fDCOCLK / 2 */ +#define FLLD_2 (0x2000) /* fDCOCLK / 4 */ +#define FLLD_3 (0x3000) /* fDCOCLK / 8 */ +#define FLLD_4 (0x4000) /* fDCOCLK / 16 */ +#define FLLD_5 (0x5000) /* fDCOCLK / 32 */ +#define FLLD_6 (0x6000) /* fDCOCLK / 40(Only avaliable in 24MHz clock system) */ +#define FLLD_7 (0x7000) /* fDCOCLK / 48(Only avaliable in 24MHz clock system) */ +#define FLLD__1 (0x0000) /* fDCOCLK / 1 */ +#define FLLD__2 (0x1000) /* fDCOCLK / 2 */ +#define FLLD__4 (0x2000) /* fDCOCLK / 4 */ +#define FLLD__8 (0x3000) /* fDCOCLK / 8 */ +#define FLLD__16 (0x4000) /* fDCOCLK / 16 */ +#define FLLD__32 (0x5000) /* fDCOCLK / 32 */ + +/* CSCTL3 Control Bits */ +#define FLLREFDIV (0x0007) /* */ +#define FLLREFDIV0 (0x0001) /* */ +#define FLLREFDIV1 (0x0002) /* */ +#define FLLREFDIV2 (0x0004) /* */ +#define FLLREFDIV_0 (0x0000) /* fFLLREFCLK / 1 */ +#define FLLREFDIV_1 (0x0001) /* fFLLREFCLK / 32 */ +#define FLLREFDIV_2 (0x0002) /* fFLLREFCLK / 64 */ +#define FLLREFDIV_3 (0x0003) /* fFLLREFCLK / 128 */ +#define FLLREFDIV_4 (0x0004) /* fFLLREFCLK / 256 */ +#define FLLREFDIV_5 (0x0005) /* fFLLREFCLK / 512 */ +#define FLLREFDIV_6 (0x0006) /* fFLLREFCLK / 640 (only available in 24MHz clock system) */ +#define FLLREFDIV_7 (0x0007) /* fFLLREFCLK / 768(only available in 24MHz clock system) */ +#define FLLREFDIV__1 (0x0000) /* fFLLREFCLK / 1 */ +#define FLLREFDIV__32 (0x0001) /* fFLLREFCLK / 32 */ +#define FLLREFDIV__64 (0x0002) /* fFLLREFCLK / 64 */ +#define FLLREFDIV__128 (0x0003) /* fFLLREFCLK / 128 */ +#define FLLREFDIV__256 (0x0004) /* fFLLREFCLK / 256 */ +#define FLLREFDIV__512 (0x0005) /* fFLLREFCLK / 512 */ +#define SELREF (0x0030) /* */ +#define SELREF0 (0x0010) /* */ +#define SELREF1 (0x0020) /* */ +#define SELREF_0 (0x0000) /* XT1CLK */ +#define SELREF_1 (0x0010) /* REFOCLK */ +#define SELREF_2 (0x0020) /* served for future use */ +#define SELREF_3 (0x0030) /* served for future use */ +#define SELREF__XT1CLK (0x0000) /* XT1CLK */ +#define SELREF__REFOCLK (0x0010) /* REFOCLK */ +#define REFOLP (0x0080) /* */ +#define REFOLP_0 (0x0000) /* REFO Low Power Disabled (High Power Mode) */ +#define REFOLP_1 (0x0080) /* REFO Low Power Enabled */ + +/* CSCTL4 Control Bits */ +#define SELMS (0x0007) /* */ +#define SELMS0 (0x0001) /* */ +#define SELMS1 (0x0002) /* */ +#define SELMS2 (0x0004) /* */ +#define SELMS_0 (0x0000) /* DCOCLKDIV */ +#define SELMS_1 (0x0001) /* REFOCLK */ +#define SELMS_2 (0x0002) /* XT1CLK */ +#define SELMS_3 (0x0003) /* VLOCLK */ +#define SELMS_4 (0x0004) /* Reserved for future use */ +#define SELMS_5 (0x0005) /* Reserved for future use */ +#define SELMS_6 (0x0006) /* Reserved for future use */ +#define SELMS_7 (0x0007) /* Reserved for future use */ +#define SELMS__DCOCLKDIV (0x0000) /* DCOCLKDIV */ +#define SELMS__REFOCLK (0x0001) /* REFOCLK */ +#define SELMS__XT1CLK (0x0002) /* XT1CLK */ +#define SELMS__VLOCLK (0x0003) /* VLOCLK */ +#define SELA (0x0300) /* */ +#define SELA0 (0x0100) /* */ +#define SELA1 (0x0200) /* */ +#define SELA_0 (0x0000) /* XT1CLK with divider (must be no more than 40 kHz) */ +#define SELA_1 (0x0100) /* REFO (internal 32-kHz clock source) */ +#define SELA_2 (0x0200) /* VLO (internal 10-kHz clock source) */ +#define SELA_3 (0x0300) /* Reserved */ +#define SELA__XT1CLK (0x0000) /* XT1CLK with divider (must be no more than 40 kHz) */ +#define SELA__REFOCLK (0x0100) /* REFO (internal 32-kHz clock source) */ +#define SELA__VLOCLK (0x0200) /* VLO (internal 10-kHz clock source) */ +#define SELA__RESERVED (0x0300) /* Reserved */ + +/* CSCTL5 Control Bits */ +#define DIVM (0x0007) /* */ +#define DIVM0 (0x0001) /* */ +#define DIVM1 (0x0002) /* */ +#define DIVM2 (0x0004) /* */ +#define DIVM_0 (0x0000) /* /1 */ +#define DIVM_1 (0x0001) /* /2 */ +#define DIVM_2 (0x0002) /* /4 */ +#define DIVM_3 (0x0003) /* /8 */ +#define DIVM_4 (0x0004) /* /16 */ +#define DIVM_5 (0x0005) /* /32 */ +#define DIVM_6 (0x0006) /* /64 */ +#define DIVM_7 (0x0007) /* /128 */ +#define DIVM__1 (0x0000) /* /1 */ +#define DIVM__2 (0x0001) /* /2 */ +#define DIVM__4 (0x0002) /* /4 */ +#define DIVM__8 (0x0003) /* /8 */ +#define DIVM__16 (0x0004) /* /16 */ +#define DIVM__32 (0x0005) /* /32 */ +#define DIVM__64 (0x0006) /* /64 */ +#define DIVM__128 (0x0007) /* /128 */ +#define DIVS (0x0030) /* */ +#define DIVS0 (0x0010) /* */ +#define DIVS1 (0x0020) /* */ +#define DIVS_0 (0x0000) /* /1 */ +#define DIVS_1 (0x0010) /* /2 */ +#define DIVS_2 (0x0020) /* /4 */ +#define DIVS_3 (0x0030) /* /8 */ +#define DIVS__1 (0x0000) /* /1 */ +#define DIVS__2 (0x0010) /* /2 */ +#define DIVS__4 (0x0020) /* /4 */ +#define DIVS__8 (0x0030) /* /8 */ +#define SMCLKOFF (0x0100) /* */ +#define SMCLKOFF_0 (0x0000) /* SMCLK on */ +#define SMCLKOFF_1 (0x0100) /* SMCLK off */ +#define VLOAUTOOFF (0x1000) /* */ +#define VLOAUTOOFF_0 (0x0000) /* VLO always on */ +#define VLOAUTOOFF_1 (0x1000) /* VLO automatically turned off if not used(default) */ + +/* CSCTL6 Control Bits */ +#define XT1AUTOOFF (0x0001) /* */ +#define XT1AUTOOFF_0 (0x0000) /* XT1 is on if XT1 is selected by the port selection and XT1 is + not in bypass mode of operation. */ +#define XT1AUTOOFF_1 (0x0001) /* XT1 is off if it is not used as a source for ACLK, MCLK, or + SMCLK or is not used as a reference source required for FLL + operation. */ +#define XT1AGCOFF (0x0002) /* */ +#define XT1AGCOFF_0 (0x0000) /* AGC on */ +#define XT1AGCOFF_1 (0x0002) /* AGC off */ +#define XT1HFFREQ (0x000c) /* */ +#define XT1HFFREQ0 (0x0004) /* */ +#define XT1HFFREQ1 (0x0008) /* */ +#define XT1HFFREQ_0 (0x0000) /* 1 to 4 MHz */ +#define XT1HFFREQ_1 (0x0004) /* >4 MHz to 6 MHz */ +#define XT1HFFREQ_2 (0x0008) /* >6 MHz to 16 MHz */ +#define XT1HFFREQ_3 (0x000c) /* >16 MHz to 24 MHz */ +#define XT1BYPASS (0x0010) /* */ +#define XT1BYPASS_0 (0x0000) /* XT1 source internally */ +#define XT1BYPASS_1 (0x0010) /* XT1 sources externally from pin */ +#define XTS (0x0020) /* */ +#define XTS_0 (0x0000) /* Low-frequency mode. */ +#define XTS_1 (0x0020) /* High-frequency mode. */ +#define XT1DRIVE (0x00c0) /* */ +#define XT1DRIVE0 (0x0040) /* */ +#define XT1DRIVE1 (0x0080) /* */ +#define XT1DRIVE_0 (0x0000) /* Lowest drive strength and current consumption */ +#define XT1DRIVE_1 (0x0040) /* Lower drive strength and current consumption */ +#define XT1DRIVE_2 (0x0080) /* Higher drive strength and current consumption */ +#define XT1DRIVE_3 (0x00c0) /* Highest drive strength and current consumption */ +#define DIVA (0x0f00) /* */ +#define DIVA0 (0x0100) /* */ +#define DIVA1 (0x0200) /* */ +#define DIVA2 (0x0400) /* */ +#define DIVA3 (0x0800) /* */ +#define DIVA_0 (0x0000) /* /1 */ +#define DIVA_1 (0x0100) /* /16 */ +#define DIVA_2 (0x0200) /* /32 */ +#define DIVA_3 (0x0300) /* /64 */ +#define DIVA_4 (0x0400) /* /128 */ +#define DIVA_5 (0x0500) /* /256 */ +#define DIVA_6 (0x0600) /* /384 */ +#define DIVA_7 (0x0700) /* /512 */ +#define DIVA_8 (0x0800) /* /768(Only available in 24MHz clock system, 24 MHz preference) */ +#define DIVA_9 (0x0900) /* /1024(Only available in 24MHz clock system, 24 MHz preference) */ +#define DIVA_10 (0x0a00) /* /108(Only available in 24MHz clock system, 24 MHz preference) */ +#define DIVA_11 (0x0b00) /* 338(Only available in 24MHz clock system, 24 MHz preference) */ +#define DIVA_12 (0x0c00) /* 414(Only available in 24MHz clock system, 24 MHz preference) */ +#define DIVA_13 (0x0d00) /* 640(Only available in 24MHz clock system, 24 MHz preference) */ +#define DIVA_14 (0x0e00) /* Reserved */ +#define DIVA_15 (0x0f00) /* Reserved */ +#define DIVA__1 (0x0000) /* /1 */ +#define DIVA__16 (0x0100) /* /16 */ +#define DIVA__32 (0x0200) /* /32 */ +#define DIVA__64 (0x0300) /* /64 */ +#define DIVA__128 (0x0400) /* /128 */ +#define DIVA__256 (0x0500) /* /256 */ +#define DIVA__384 (0x0600) /* /384 */ +#define DIVA__512 (0x0700) /* /512 */ +#define DIVA__768 (0x0800) /* /768(Only available in 24MHz clock system, 24 MHz preference) */ +#define DIVA__1024 (0x0900) /* /1024(Only available in 24MHz clock system, 24 MHz preference) */ +#define DIVA__108 (0x0a00) /* /108(Only available in 24MHz clock system, 24 MHz preference) */ +#define DIVA__338 (0x0b00) /* 338(Only available in 24MHz clock system, 24 MHz preference) */ +#define DIVA__414 (0x0c00) /* 414(Only available in 24MHz clock system, 24 MHz preference) */ +#define DIVA__640 (0x0d00) /* 640(Only available in 24MHz clock system, 24 MHz preference) */ +#define XT1FAULTOFF (0x2000) /* */ +#define XT1FAULTOFF_0 (0x0000) /* Enabling XT1 fault to switch ACLK to REFO */ +#define XT1FAULTOFF_1 (0x2000) /* Disabling XT1 fault to switch ACLK to REFO */ + +/* CSCTL7 Control Bits */ +#define REFOREADY (0x0004) /* */ +#define REFOREADY_0 (0x0000) /* REFO unstable */ +#define REFOREADY_1 (0x0004) /* REFO ready to go */ +#define DCOFFG (0x0001) /* */ +#define DCOFFG_0 (0x0000) /* No fault condition occurred after the last reset. */ +#define DCOFFG_1 (0x0001) /* DCO fault. A DCO fault occurred after the last reset. */ +#define XT1OFFG (0x0002) /* */ +#define XT1OFFG_0 (0x0000) /* No fault condition occurred after the last reset. */ +#define XT1OFFG_1 (0x0002) /* XT1 fault. An XT1 fault occurred after the last reset. */ +#define FLLULIFG (0x0010) /* */ +#define FLLULIFG_0 (0x0000) /* FLLUNLOCK bits not equal to 10b */ +#define FLLULIFG_1 (0x0010) /* FLLUNLOCK bits equal to 10b */ +#define ENSTFCNT1 (0x0040) /* */ +#define ENSTFCNT1_0 (0x0000) /* Startup fault counter disabled. Counter is cleared.. */ +#define ENSTFCNT1_1 (0x0040) /* Startup fault counter enabled. */ +#define FLLUNLOCK (0x0300) /* */ +#define FLLUNLOCK0 (0x0100) /* */ +#define FLLUNLOCK1 (0x0200) /* */ +#define FLLUNLOCK_0 (0x0000) /* FLL is locked. No unlock condition currently active. */ +#define FLLUNLOCK_1 (0x0100) /* DCOCLK is currently too slow. */ +#define FLLUNLOCK_2 (0x0200) /* DCOCLK is currently too fast. */ +#define FLLUNLOCK_3 (0x0300) /* DCOERROR. DCO out of range. */ +#define FLLUNLOCKHIS (0x0c00) /* */ +#define FLLUNLOCKHIS0 (0x0400) /* */ +#define FLLUNLOCKHIS1 (0x0800) /* */ +#define FLLUNLOCKHIS_0 (0x0000) /* FLL is locked. No unlock situation has been detected since the + last reset of these bits. */ +#define FLLUNLOCKHIS_1 (0x0400) /* DCOCLK has been too slow since the bits were cleared. */ +#define FLLUNLOCKHIS_2 (0x0800) /* DCOCLK has been too fast since the bits were cleared. */ +#define FLLUNLOCKHIS_3 (0x0c00) /* DCOCLK has been both too fast and too slow since the bits were + cleared. */ +#define FLLULPUC (0x1000) /* */ +#define FLLWARNEN (0x2000) /* */ +#define FLLWARNEN_0 (0x0000) /* FLLUNLOCKHIS status cannot set OFIFG. */ +#define FLLWARNEN_1 (0x2000) /* FLLUNLOCKHIS status can set OFIFG. */ + +/* CSCTL8 Control Bits */ +#define ACLKREQEN (0x0001) /* */ +#define ACLKREQEN_0 (0x0000) /* ACLK conditional requests are disabled. */ +#define ACLKREQEN_1 (0x0001) /* ACLK conditional requests are enabled. */ +#define MCLKREQEN (0x0002) /* */ +#define MCLKREQEN_0 (0x0000) /* MCLK conditional requests are disabled. */ +#define MCLKREQEN_1 (0x0002) /* MCLK conditional requests are enabled. */ +#define SMCLKREQEN (0x0004) /* */ +#define SMCLKREQEN_0 (0x0000) /* SMCLK conditional requests are disabled. */ +#define SMCLKREQEN_1 (0x0004) /* SMCLK conditional requests are enabled. */ +#define MODOSCREQEN (0x0008) /* */ +#define MODOSCREQEN_0 (0x0000) /* MODOSC conditional requests are disabled. */ +#define MODOSCREQEN_1 (0x0008) /* MODOSC conditional requests are enabled. */ + + +/***************************************************************************** + DIO Registers +*****************************************************************************/ + +#define __MSP430_HAS_DIO__ 6 /* Definition to show that module is available */ +#define __MSP430_BASEADDRESS_DIO__ 0x0200 +#define DIO_BASE __MSP430_BASEADDRESS_DIO__ +#define __MSP430_HAS_PORTA_R__ /* Definition to show that port is available */ +#define __MSP430_BASEADDRESS_PORTA_R__ 0x200 +#define PA_BASE __MSP430_BASEADDRESS_PORTA_R__ +#define __MSP430_HAS_PORTB_R__ /* Definition to show that port is available */ +#define __MSP430_BASEADDRESS_PORTB_R__ 0x220 +#define PB_BASE __MSP430_BASEADDRESS_PORTB_R__ +#define __MSP430_HAS_PORTC_R__ /* Definition to show that port is available */ +#define __MSP430_BASEADDRESS_PORTC_R__ 0x240 +#define PC_BASE __MSP430_BASEADDRESS_PORTC_R__ +#define __MSP430_HAS_PORTJ_R__ /* Definition to show that port is available */ +#define __MSP430_BASEADDRESS_PORTJ_R__ 0x320 +#define PJ_BASE __MSP430_BASEADDRESS_PORTJ_R__ +#define __MSP430_HAS_PORT1_R__ /* Definition to show that port is available */ +#define __MSP430_BASEADDRESS_PORT1_R__ 0x200 +#define P1_BASE __MSP430_BASEADDRESS_PORT1_R__ +#define __MSP430_HAS_PORT2_R__ /* Definition to show that port is available */ +#define __MSP430_BASEADDRESS_PORT2_R__ 0x200 +#define P2_BASE __MSP430_BASEADDRESS_PORT2_R__ +#define __MSP430_HAS_PORT3_R__ /* Definition to show that port is available */ +#define __MSP430_BASEADDRESS_PORT3_R__ 0x220 +#define P3_BASE __MSP430_BASEADDRESS_PORT3_R__ +#define __MSP430_HAS_PORT4_R__ /* Definition to show that port is available */ +#define __MSP430_BASEADDRESS_PORT4_R__ 0x220 +#define P4_BASE __MSP430_BASEADDRESS_PORT4_R__ +#define __MSP430_HAS_PORT5_R__ /* Definition to show that port is available */ +#define __MSP430_BASEADDRESS_PORT5_R__ 0x240 +#define P5_BASE __MSP430_BASEADDRESS_PORT5_R__ +#define __MSP430_HAS_PORT6_R__ /* Definition to show that port is available */ +#define __MSP430_BASEADDRESS_PORT6_R__ 0x240 +#define P6_BASE __MSP430_BASEADDRESS_PORT6_R__ +#define __MSP430_HAS_PASEL0__ /* Define for DriverLib */ +#define __MSP430_HAS_PASEL1__ /* Define for DriverLib */ +#define __MSP430_HAS_PBSEL0__ /* Define for DriverLib */ +#define __MSP430_HAS_PBSEL1__ /* Define for DriverLib */ +#define __MSP430_HAS_PCSEL0__ /* Define for DriverLib */ +#define __MSP430_HAS_PCSEL1__ /* Define for DriverLib */ +#define __MSP430_HAS_PJSEL0__ /* Define for DriverLib */ +#define __MSP430_HAS_PJSEL1__ /* Define for DriverLib */ +#define __MSP430_HAS_P1SEL0__ /* Define for DriverLib */ +#define __MSP430_HAS_P2SEL0__ /* Define for DriverLib */ +#define __MSP430_HAS_P1SEL1__ /* Define for DriverLib */ +#define __MSP430_HAS_P2SEL1__ /* Define for DriverLib */ +#define __MSP430_HAS_P4SEL0__ /* Define for DriverLib */ +#define __MSP430_HAS_P3SEL0__ /* Define for DriverLib */ +#define __MSP430_HAS_P3SEL1__ /* Define for DriverLib */ +#define __MSP430_HAS_P4SEL1__ /* Define for DriverLib */ +#define __MSP430_HAS_P5SEL0__ /* Define for DriverLib */ +#define __MSP430_HAS_P6SEL0__ /* Define for DriverLib */ +#define __MSP430_HAS_P5SEL1__ /* Define for DriverLib */ +#define __MSP430_HAS_P6SEL1__ /* Define for DriverLib */ + +sfr_w(PAIN); /* Port A Input */ +sfr_b(PAIN_L); +sfr_b(PAIN_H); +sfr_w(PAOUT); /* Port A Output */ +sfr_b(PAOUT_L); +sfr_b(PAOUT_H); +sfr_w(PADIR); /* Port A Direction */ +sfr_b(PADIR_L); +sfr_b(PADIR_H); +sfr_w(PAREN); /* Port A Resistor Enable */ +sfr_b(PAREN_L); +sfr_b(PAREN_H); +sfr_w(PASEL0); /* Port A Select 0 */ +sfr_b(PASEL0_L); +sfr_b(PASEL0_H); +sfr_w(PASEL1); /* Port A Select 1 */ +sfr_b(PASEL1_L); +sfr_b(PASEL1_H); +sfr_w(P1IV); /* Port 1 Interrupt Vector Register */ +sfr_b(P1IV_L); +sfr_b(P1IV_H); +sfr_w(PASELC); /* Port A Complement Select */ +sfr_b(PASELC_L); +sfr_b(PASELC_H); +sfr_w(PAIES); /* Port A Interrupt Edge Select */ +sfr_b(PAIES_L); +sfr_b(PAIES_H); +sfr_w(PAIE); /* Port A Interrupt Enable */ +sfr_b(PAIE_L); +sfr_b(PAIE_H); +sfr_w(PAIFG); /* Port A Interrupt Flag */ +sfr_b(PAIFG_L); +sfr_b(PAIFG_H); +sfr_w(P2IV); /* Port 2 Interrupt Vector Register */ +sfr_b(P2IV_L); +sfr_b(P2IV_H); +sfr_w(PBIN); /* Port B Input */ +sfr_b(PBIN_L); +sfr_b(PBIN_H); +sfr_w(PBOUT); /* Port B Output */ +sfr_b(PBOUT_L); +sfr_b(PBOUT_H); +sfr_w(PBDIR); /* Port B Direction */ +sfr_b(PBDIR_L); +sfr_b(PBDIR_H); +sfr_w(PBREN); /* Port B Resistor Enable */ +sfr_b(PBREN_L); +sfr_b(PBREN_H); +sfr_w(PBSEL0); /* Port B Select 0 */ +sfr_b(PBSEL0_L); +sfr_b(PBSEL0_H); +sfr_w(PBSEL1); /* Port B Select 1 */ +sfr_b(PBSEL1_L); +sfr_b(PBSEL1_H); +sfr_w(P3IV); /* Port 3 Interrupt Vector Register */ +sfr_b(P3IV_L); +sfr_b(P3IV_H); +sfr_w(PBSELC); /* Port B Complement Select */ +sfr_b(PBSELC_L); +sfr_b(PBSELC_H); +sfr_w(PBIES); /* Port B Interrupt Edge Select */ +sfr_b(PBIES_L); +sfr_b(PBIES_H); +sfr_w(PBIE); /* Port B Interrupt Enable */ +sfr_b(PBIE_L); +sfr_b(PBIE_H); +sfr_w(PBIFG); /* Port B Interrupt Flag */ +sfr_b(PBIFG_L); +sfr_b(PBIFG_H); +sfr_w(P4IV); /* Port 4 Interrupt Vector Register */ +sfr_b(P4IV_L); +sfr_b(P4IV_H); +sfr_w(PCIN); /* Port C Input */ +sfr_b(PCIN_L); +sfr_b(PCIN_H); +sfr_w(PCOUT); /* Port C Output */ +sfr_b(PCOUT_L); +sfr_b(PCOUT_H); +sfr_w(PCDIR); /* Port C Direction */ +sfr_b(PCDIR_L); +sfr_b(PCDIR_H); +sfr_w(PCREN); /* Port C Resistor Enable */ +sfr_b(PCREN_L); +sfr_b(PCREN_H); +sfr_w(PCSEL0); /* Port C Select 0 */ +sfr_b(PCSEL0_L); +sfr_b(PCSEL0_H); +sfr_w(PCSEL1); /* Port C Select 1 */ +sfr_b(PCSEL1_L); +sfr_b(PCSEL1_H); +sfr_w(P5IV); /* Port 5 Interrupt Vector Register */ +sfr_b(P5IV_L); +sfr_b(P5IV_H); +sfr_w(PCSELC); /* Port C Complement Select */ +sfr_b(PCSELC_L); +sfr_b(PCSELC_H); +sfr_w(PCIES); /* Port C Interrupt Edge Select */ +sfr_b(PCIES_L); +sfr_b(PCIES_H); +sfr_w(PCIE); /* Port C Interrupt Enable */ +sfr_b(PCIE_L); +sfr_b(PCIE_H); +sfr_w(PCIFG); /* Port C Interrupt Flag */ +sfr_b(PCIFG_L); +sfr_b(PCIFG_H); +sfr_w(P6IV); /* Port 6 Interrupt Vector Register */ +sfr_b(P6IV_L); +sfr_b(P6IV_H); +sfr_w(PJIN); /* Port J Input */ +sfr_b(PJIN_L); +sfr_b(PJIN_H); +sfr_w(PJOUT); /* Port J Output */ +sfr_b(PJOUT_L); +sfr_b(PJOUT_H); +sfr_w(PJDIR); /* Port J Direction */ +sfr_b(PJDIR_L); +sfr_b(PJDIR_H); +sfr_w(PJREN); /* Port J Resistor Enable */ +sfr_b(PJREN_L); +sfr_b(PJREN_H); +sfr_w(PJSEL0); /* Port J Select 0 */ +sfr_b(PJSEL0_L); +sfr_b(PJSEL0_H); +sfr_w(PJSEL1); /* Port J Select 1 */ +sfr_b(PJSEL1_L); +sfr_b(PJSEL1_H); +sfr_w(PJSELC); /* Port J Complement Select */ +sfr_b(PJSELC_L); +sfr_b(PJSELC_H); +sfr_b(P1IN); /* Port 1 Input */ + +sfr_b(P2IN); /* Port 2 Input */ + +sfr_b(P2OUT); /* Port 2 Output */ + +sfr_b(P1OUT); /* Port 1 Output */ + +sfr_b(P1DIR); /* Port 1 Direction */ + +sfr_b(P2DIR); /* Port 2 Direction */ + +sfr_b(P1REN); /* Port 1 Resistor Enable */ + +sfr_b(P2REN); /* Port 2 Resistor Enable */ + +sfr_b(P1SEL0); /* Port 1 Select 0 */ + +sfr_b(P2SEL0); /* Port 2 Select 0 */ + +sfr_b(P1SEL1); /* Port 1 Select 1 */ + +sfr_b(P2SEL1); /* Port 2 Select 1 */ + +sfr_b(P1SELC); /* Port 1 Complement Select */ + +sfr_b(P2SELC); /* Port 2 Complement Select */ + +sfr_b(P1IES); /* Port 1 Interrupt Edge Select */ + +sfr_b(P2IES); /* Port 2 Interrupt Edge Select */ + +sfr_b(P1IE); /* Port 1 Interrupt Enable */ + +sfr_b(P2IE); /* Port 2 Interrupt Enable */ + +sfr_b(P1IFG); /* Port 1 Interrupt Flag */ + +sfr_b(P2IFG); /* Port 2 Interrupt Flag */ + +sfr_b(P3IN); /* Port 3 Input */ + +sfr_b(P4IN); /* Port 4 Input */ + +sfr_b(P3OUT); /* Port 3 Output */ + +sfr_b(P4OUT); /* Port 4 Output */ + +sfr_b(P3DIR); /* Port 3 Direction */ + +sfr_b(P4DIR); /* Port 4 Direction */ + +sfr_b(P3REN); /* Port 3 Resistor Enable */ + +sfr_b(P4REN); /* Port 4 Resistor Enable */ + +sfr_b(P4SEL0); /* Port 4 Select 0 */ + +sfr_b(P3SEL0); /* Port 3 Select 0 */ + +sfr_b(P3SEL1); /* Port 3 Select 1 */ + +sfr_b(P4SEL1); /* Port 4 Select 1 */ + +sfr_b(P3SELC); /* Port 3 Complement Select */ + +sfr_b(P4SELC); /* Port 4 Complement Select */ + +sfr_b(P3IES); /* Port 3 Interrupt Edge Select */ + +sfr_b(P4IES); /* Port 4 Interrupt Edge Select */ + +sfr_b(P3IE); /* Port 3 Interrupt Enable */ + +sfr_b(P4IE); /* Port 4 Interrupt Enable */ + +sfr_b(P3IFG); /* Port 3 Interrupt Flag */ + +sfr_b(P4IFG); /* Port 4 Interrupt Flag */ + +sfr_b(P5IN); /* Port 5 Input */ + +sfr_b(P6IN); /* Port 6 Input */ + +sfr_b(P5OUT); /* Port 5 Output */ + +sfr_b(P6OUT); /* Port 6 Output */ + +sfr_b(P5DIR); /* Port 5 Direction */ + +sfr_b(P6DIR); /* Port 6 Direction */ + +sfr_b(P5REN); /* Port 5 Resistor Enable */ + +sfr_b(P6REN); /* Port 6 Resistor Enable */ + +sfr_b(P5SEL0); /* Port 5 Select 0 */ + +sfr_b(P6SEL0); /* Port 6 Select 0 */ + +sfr_b(P5SEL1); /* Port 5 Select 1 */ + +sfr_b(P6SEL1); /* Port 6 Select 1 */ + +sfr_b(P5SELC); /* Port 5 Complement Select */ + +sfr_b(P6SELC); /* Port 6 Complement Select */ + +sfr_b(P5IES); /* Port 5 Interrupt Edge Select */ + +sfr_b(P6IES); /* Port 6 Interrupt Edge Select */ + +sfr_b(P5IE); /* Port 5 Interrupt Enable */ + +sfr_b(P6IE); /* Port 6 Interrupt Enable */ + +sfr_b(P5IFG); /* Port 5 Interrupt Flag */ + +sfr_b(P6IFG); /* Port 6 Interrupt Flag */ + + +/* DIO Register Offsets */ +#define OFS_PAIN (0x0000) +#define OFS_PAOUT (0x0002) +#define OFS_PADIR (0x0004) +#define OFS_PAREN (0x0006) +#define OFS_PASEL0 (0x000A) +#define OFS_PASEL1 (0x000C) +#define OFS_P1IV (0x000E) +#define OFS_PASELC (0x0016) +#define OFS_PAIES (0x0018) +#define OFS_PAIE (0x001A) +#define OFS_PAIFG (0x001C) +#define OFS_P2IV (0x001E) +#define OFS_PBIN (0x0000) +#define OFS_PBOUT (0x0002) +#define OFS_PBDIR (0x0004) +#define OFS_PBREN (0x0006) +#define OFS_PBSEL0 (0x000A) +#define OFS_PBSEL1 (0x000C) +#define OFS_P3IV (0x000E) +#define OFS_PBSELC (0x0016) +#define OFS_PBIES (0x0018) +#define OFS_PBIE (0x001A) +#define OFS_PBIFG (0x001C) +#define OFS_P4IV (0x001E) +#define OFS_PCIN (0x0000) +#define OFS_PCOUT (0x0002) +#define OFS_PCDIR (0x0004) +#define OFS_PCREN (0x0006) +#define OFS_PCSEL0 (0x000A) +#define OFS_PCSEL1 (0x000C) +#define OFS_P5IV (0x000E) +#define OFS_PCSELC (0x0016) +#define OFS_PCIES (0x0018) +#define OFS_PCIE (0x001A) +#define OFS_PCIFG (0x001C) +#define OFS_P6IV (0x001E) +#define OFS_PJIN (0x0000) +#define OFS_PJOUT (0x0002) +#define OFS_PJDIR (0x0004) +#define OFS_PJREN (0x0006) +#define OFS_PJSEL0 (0x000A) +#define OFS_PJSEL1 (0x000C) +#define OFS_PJSELC (0x0016) +#define OFS_P1IN (0x0000) +#define OFS_P2IN (0x0001) +#define OFS_P2OUT (0x0003) +#define OFS_P1OUT (0x0002) +#define OFS_P1DIR (0x0004) +#define OFS_P2DIR (0x0005) +#define OFS_P1REN (0x0006) +#define OFS_P2REN (0x0007) +#define OFS_P1SEL0 (0x000A) +#define OFS_P2SEL0 (0x000B) +#define OFS_P1SEL1 (0x000C) +#define OFS_P2SEL1 (0x000D) +#define OFS_P1SELC (0x0016) +#define OFS_P2SELC (0x0017) +#define OFS_P1IES (0x0018) +#define OFS_P2IES (0x0019) +#define OFS_P1IE (0x001A) +#define OFS_P2IE (0x001B) +#define OFS_P1IFG (0x001C) +#define OFS_P2IFG (0x001D) +#define OFS_P3IN (0x0000) +#define OFS_P4IN (0x0001) +#define OFS_P3OUT (0x0002) +#define OFS_P4OUT (0x0003) +#define OFS_P3DIR (0x0004) +#define OFS_P4DIR (0x0005) +#define OFS_P3REN (0x0006) +#define OFS_P4REN (0x0007) +#define OFS_P4SEL0 (0x000B) +#define OFS_P3SEL0 (0x000A) +#define OFS_P3SEL1 (0x000C) +#define OFS_P4SEL1 (0x000D) +#define OFS_P3SELC (0x0016) +#define OFS_P4SELC (0x0017) +#define OFS_P3IES (0x0018) +#define OFS_P4IES (0x0019) +#define OFS_P3IE (0x001A) +#define OFS_P4IE (0x001B) +#define OFS_P3IFG (0x001C) +#define OFS_P4IFG (0x001D) +#define OFS_P5IN (0x0000) +#define OFS_P6IN (0x0001) +#define OFS_P5OUT (0x0002) +#define OFS_P6OUT (0x0003) +#define OFS_P5DIR (0x0004) +#define OFS_P6DIR (0x0005) +#define OFS_P5REN (0x0006) +#define OFS_P6REN (0x0007) +#define OFS_P5SEL0 (0x000A) +#define OFS_P6SEL0 (0x000B) +#define OFS_P5SEL1 (0x000C) +#define OFS_P6SEL1 (0x000D) +#define OFS_P5SELC (0x0016) +#define OFS_P6SELC (0x0017) +#define OFS_P5IES (0x0018) +#define OFS_P6IES (0x0019) +#define OFS_P5IE (0x001A) +#define OFS_P6IE (0x001B) +#define OFS_P5IFG (0x001C) +#define OFS_P6IFG (0x001D) + +/***************************************************************************** + FRCTL Registers +*****************************************************************************/ + +#define __MSP430_HAS_FRCTL__ /* Definition to show that module is available */ +#define __MSP430_BASEADDRESS_FRCTL__ 0x01A0 +#define FRCTL_BASE __MSP430_BASEADDRESS_FRCTL__ + +sfr_w(FRCTL0); /* FRAM Controller Control Register 0 */ +sfr_b(FRCTL0_L); +sfr_b(FRCTL0_H); +sfr_w(GCCTL0); /* General Control Register 0 */ +sfr_b(GCCTL0_L); +sfr_b(GCCTL0_H); +sfr_w(GCCTL1); /* General Control Register 1 */ +sfr_b(GCCTL1_L); +sfr_b(GCCTL1_H); + +/* FRCTL Register Offsets */ +#define OFS_FRCTL0 (0x0000) +#define OFS_GCCTL0 (0x0004) +#define OFS_GCCTL1 (0x0006) + +/* FRCTL Control Bits */ + +/* FRCTL0 Control Bits */ +#define NWAITS (0x0070) /* Wait state numbers */ +#define NWAITS0 (0x0010) /* Wait state numbers */ +#define NWAITS1 (0x0020) /* Wait state numbers */ +#define NWAITS2 (0x0040) /* Wait state numbers */ +#define NWAITS_0 (0x0000) /* FRAM wait states: 0 */ +#define NWAITS_1 (0x0010) /* FRAM wait states: 1 */ +#define NWAITS_2 (0x0020) /* FRAM wait states: 2 */ +#define NWAITS_3 (0x0030) /* FRAM wait states: 3 */ +#define NWAITS_4 (0x0040) /* FRAM wait states: 4 */ +#define NWAITS_5 (0x0050) /* FRAM wait states: 5 */ +#define NWAITS_6 (0x0060) /* FRAM wait states: 6 */ +#define NWAITS_7 (0x0070) /* FRAM wait states: 7 */ +#define FRCTLPW (0xa500) /* FRCTLPW password */ +#define FRCTLPW0 (0x0100) /* FRCTLPW password */ +#define FRCTLPW1 (0x0200) /* FRCTLPW password */ +#define FRCTLPW2 (0x0400) /* FRCTLPW password */ +#define FRCTLPW3 (0x0800) /* FRCTLPW password */ +#define FRCTLPW4 (0x1000) /* FRCTLPW password */ +#define FRCTLPW5 (0x2000) /* FRCTLPW password */ +#define FRCTLPW6 (0x4000) /* FRCTLPW password */ +#define FRCTLPW7 (0x8000) /* FRCTLPW password */ + +/* GCCTL0 Control Bits */ +#define UBDRSTEN (0x0080) /* Enable Power Up Clear (PUC) reset for the uncorrectable bit + error detection flag (UBDIFG) */ +#define UBDRSTEN_0 (0x0000) /* PUC not initiated on uncorrectable bit error detection flag. */ +#define UBDRSTEN_1 (0x0080) /* PUC initiated on uncorrectable bit error detection flag. + Generates vector in SYSRSTIV. Clear the UBDIE bit. */ +#define UBDIE (0x0040) /* Enable NMI event for the uncorrectable bit error detection + flag (UBDIFG) */ +#define UBDIE_0 (0x0000) /* Disable NMI for the uncorrectable bit error detection flag + (UBDIFG). */ +#define UBDIE_1 (0x0040) /* Enable NMI for the uncorrectable bit error detection flag + (UBDIFG). Generates vector in SYSSNIV. Clear the UBDRSTEN bit. */ +#define CBDIE (0x0020) /* Enable NMI event for the correctable bit error detection flag + (CBDIFG) */ +#define CBDIE_0 (0x0000) /* Disable NMI for the correctable bit error detection flag + (CBDIFG). */ +#define CBDIE_1 (0x0020) /* Disable NMI for the correctable bit error detection flag + (CBDIFG). Generates vector in SYSSNIV. */ +#define FRPWR (0x0004) /* FRAM Memory Power Control Request */ +#define FRPWR_0 (0x0000) /* Enable INACTIVE mode. */ +#define FRPWR_1 (0x0004) /* Enable ACTIVE mode. */ +#define FRLPMPWR (0x0002) /* Enables FRAM auto power up after LPM */ +#define FRLPMPWR_0 (0x0000) /* FRAM startup is delayed to the first FRAM access after exit + from LPM */ +#define FRLPMPWR_1 (0x0002) /* FRAM is powered up immediately on exit from LPM */ + +/* GCCTL1 Control Bits */ +#define ACCTEIFG (0x0008) /* Access time error flag */ +#define ACCTEIFG_0 (0x0000) /* No interrupt pending. */ +#define ACCTEIFG_1 (0x0008) /* Interrupt pending. Can be cleared by writing '0' or by reading + SYSSNIV when it is the highest pending interrupt. */ +#define UBDIFG (0x0004) /* FRAM uncorrectable bit error detection flag */ +#define UBDIFG_0 (0x0000) /* No interrupt pending. */ +#define UBDIFG_1 (0x0004) /* Interrupt pending. Can be cleared by writing '0' or by reading + SYSSNIV when it is the highest pending interrupt. */ +#define CBDIFG (0x0002) /* FRAM correctable bit error detection flag */ +#define CBDIFG_0 (0x0000) /* No interrupt is pending */ +#define CBDIFG_1 (0x0002) /* Interrupt pending. Can be cleared by writing '0' or by reading + SYSSNIV if it is the highest pending interrupt. */ + + +/***************************************************************************** + MPY32 Registers +*****************************************************************************/ + +#define __MSP430_HAS_MPY32__ /* Definition to show that module is available */ +#define __MSP430_BASEADDRESS_MPY32__ 0x04C0 +#define MPY32_BASE __MSP430_BASEADDRESS_MPY32__ + +sfr_w(MPY); /* 16-bit operand one multiply */ +sfr_b(MPY_L); +sfr_b(MPY_H); +sfr_w(MPYS); /* 16-bit operand one signed multiply */ +sfr_b(MPYS_L); +sfr_b(MPYS_H); +sfr_w(MAC); /* 16-bit operand one multiply accumulate */ +sfr_b(MAC_L); +sfr_b(MAC_H); +sfr_w(MACS); /* 16-bit operand one signed multiply accumulate */ +sfr_b(MACS_L); +sfr_b(MACS_H); +sfr_w(OP2); /* 16-bit operand two */ +sfr_b(OP2_L); +sfr_b(OP2_H); +sfr_w(RESLO); /* 16x16-bit result low word */ +sfr_b(RESLO_L); +sfr_b(RESLO_H); +sfr_w(RESHI); /* 16x16-bit result high word */ +sfr_b(RESHI_L); +sfr_b(RESHI_H); +sfr_w(SUMEXT); /* 16x16-bit sum extension register */ +sfr_b(SUMEXT_L); +sfr_b(SUMEXT_H); +sfr_w(MPY32L); /* 32-bit operand 1 multiply low word */ +sfr_b(MPY32L_L); +sfr_b(MPY32L_H); +sfr_w(MPY32H); /* 32-bit operand 1 multiply high word */ +sfr_b(MPY32H_L); +sfr_b(MPY32H_H); +sfr_w(MPYS32L); /* 32-bit operand 1 signed multiply low word */ +sfr_b(MPYS32L_L); +sfr_b(MPYS32L_H); +sfr_w(MPYS32H); /* 32-bit operand 1 signed multiply high word */ +sfr_b(MPYS32H_L); +sfr_b(MPYS32H_H); +sfr_w(MAC32L); /* 32-bit operand 1 multiply accumulate low word */ +sfr_b(MAC32L_L); +sfr_b(MAC32L_H); +sfr_w(MAC32H); /* 32-bit operand 1 multiply accumulate high word */ +sfr_b(MAC32H_L); +sfr_b(MAC32H_H); +sfr_w(MACS32L); /* 32-bit operand 1 signed multiply accumulate low word */ +sfr_b(MACS32L_L); +sfr_b(MACS32L_H); +sfr_w(MACS32H); /* 32-bit operand 1 signed multiply accumulate high word */ +sfr_b(MACS32H_L); +sfr_b(MACS32H_H); +sfr_w(OP2L); /* 32-bit operand 2 low word */ +sfr_b(OP2L_L); +sfr_b(OP2L_H); +sfr_w(OP2H); /* 32-bit operand 2 high word */ +sfr_b(OP2H_L); +sfr_b(OP2H_H); +sfr_w(RES0); /* 32x32-bit result 0 least significant word */ +sfr_b(RES0_L); +sfr_b(RES0_H); +sfr_w(RES1); /* 32x32-bit result 1 */ +sfr_b(RES1_L); +sfr_b(RES1_H); +sfr_w(RES2); /* 32x32-bit result 2 */ +sfr_b(RES2_L); +sfr_b(RES2_H); +sfr_w(RES3); /* 32x32-bit result 3 most significant word */ +sfr_b(RES3_L); +sfr_b(RES3_H); +sfr_w(MPY32CTL0); /* MPY32 control register 0 */ +sfr_b(MPY32CTL0_L); +sfr_b(MPY32CTL0_H); + +/* MPY32 Register Offsets */ +#define OFS_MPY (0x0000) +#define OFS_MPYS (0x0002) +#define OFS_MAC (0x0004) +#define OFS_MACS (0x0006) +#define OFS_OP2 (0x0008) +#define OFS_RESLO (0x000A) +#define OFS_RESHI (0x000C) +#define OFS_SUMEXT (0x000E) +#define OFS_MPY32L (0x0010) +#define OFS_MPY32H (0x0012) +#define OFS_MPYS32L (0x0014) +#define OFS_MPYS32H (0x0016) +#define OFS_MAC32L (0x0018) +#define OFS_MAC32H (0x001A) +#define OFS_MACS32L (0x001C) +#define OFS_MACS32H (0x001E) +#define OFS_OP2L (0x0020) +#define OFS_OP2H (0x0022) +#define OFS_RES0 (0x0024) +#define OFS_RES1 (0x0026) +#define OFS_RES2 (0x0028) +#define OFS_RES3 (0x002A) +#define OFS_MPY32CTL0 (0x002C) + +/* MPY32 Control Bits */ + +/* MACS32H Control Bits */ +#define MACS32H0 (0x0100) /* 32-bit operand 1 signed multiply accumulate high word */ +#define MACS32H1 (0x0200) /* 32-bit operand 1 signed multiply accumulate high word */ +#define MACS32H2 (0x0400) /* 32-bit operand 1 signed multiply accumulate high word */ +#define MACS32H3 (0x0800) /* 32-bit operand 1 signed multiply accumulate high word */ +#define MACS32H4 (0x1000) /* 32-bit operand 1 signed multiply accumulate high word */ +#define MACS32H5 (0x2000) /* 32-bit operand 1 signed multiply accumulate high word */ +#define MACS32H6 (0x4000) /* 32-bit operand 1 signed multiply accumulate high word */ +#define MACS32H7 (0x8000) /* 32-bit operand 1 signed multiply accumulate high word */ + +/* MPY32CTL0 Control Bits */ +#define MPYDLY32 (0x0200) /* Delayed write mode. */ +#define MPYDLY32_0 (0x0000) /* Writes are delayed until 64-bit result (RES0 to RES3) is + available. */ +#define MPYDLY32_1 (0x0200) /* Writes are delayed until 32-bit result (RES0 to RES1) is + available. 8 MPYDLYWRTEN */ +#define MPYDLYWRTEN (0x0100) /* Delayed write enable. */ +#define MPYDLYWRTEN_0 (0x0000) /* Writes are not delayed. */ +#define MPYDLYWRTEN_1 (0x0100) /* Writes are delayed. */ +#define MPYOP2_32 (0x0080) /* Multiplier bit width of operand 2 */ +#define MPYOP2_32_0 (0x0000) /* 16 bits. */ +#define MPYOP2_32_1 (0x0080) /* 32 bits. */ +#define MPYOP2_32__16 (0x0000) /* 16 bits. */ +#define MPYOP2_32__32 (0x0080) /* 32 bits. */ +#define MPYOP1_32 (0x0040) /* Multiplier bit width of operand 1 */ +#define MPYOP1_32_0 (0x0000) /* 16 bits. */ +#define MPYOP1_32_1 (0x0040) /* 32 bits. */ +#define MPYOP1_32__16 (0x0000) /* 16 bits. */ +#define MPYOP1_32__32 (0x0040) /* 32 bits. */ +#define MPYM (0x0030) /* Multiplier mode */ +#define MPYM0 (0x0010) /* Multiplier mode */ +#define MPYM1 (0x0020) /* Multiplier mode */ +#define MPYM_0 (0x0000) /* MPY Multiply */ +#define MPYM_1 (0x0010) /* MPYS Signed multiply */ +#define MPYM_2 (0x0020) /* MAC Multiply accumulate */ +#define MPYM_3 (0x0030) /* MACS Signed multiply accumulate */ +#define MPYM__MPY (0x0000) /* MPY Multiply */ +#define MPYM__MPYS (0x0010) /* MPYS Signed multiply */ +#define MPYM__MAC (0x0020) /* MAC Multiply accumulate */ +#define MPYM__MACS (0x0030) /* MACS Signed multiply accumulate */ +#define MPYSAT (0x0008) /* Saturation mode */ +#define MPYSAT_0 (0x0000) /* Saturation mode disabled. */ +#define MPYSAT_1 (0x0008) /* Saturation mode enabled. */ +#define MPYSAT__DISABLE (0x0000) /* Saturation mode disabled. */ +#define MPYSAT__ENABLE (0x0008) /* Saturation mode enabled. */ +#define MPYFRAC (0x0004) /* Fractional mode. */ +#define MPYFRAC_0 (0x0000) /* Fractional mode disabled. */ +#define MPYFRAC_1 (0x0004) /* Fractional mode enabled. */ +#define MPYFRAC__DISABLE (0x0000) /* Fractional mode disabled. */ +#define MPYFRAC__ENABLE (0x0004) /* Fractional mode enabled. */ +#define MPYC (0x0001) /* Carry of the multiplier */ +#define MPYC_0 (0x0000) /* No carry for result. */ +#define MPYC_1 (0x0001) /* Result has a carry. */ + + +/***************************************************************************** + PMM Registers +*****************************************************************************/ + +#define __MSP430_HAS_PMM__ /* Definition to show that module is available */ +#define __MSP430_BASEADDRESS_PMM__ 0x0120 +#define PMM_BASE __MSP430_BASEADDRESS_PMM__ + +sfr_w(PMMCTL0); /* Power Management Module control register 0 */ +sfr_b(PMMCTL0_L); +sfr_b(PMMCTL0_H); +sfr_w(PMMCTL1); /* Power Management Module Control Register 1. Allows manual + overwrite of predictive LDO settings. */ +sfr_b(PMMCTL1_L); +sfr_b(PMMCTL1_H); +sfr_w(PMMCTL2); /* Power Management Module Control Register 2 */ +sfr_b(PMMCTL2_L); +sfr_b(PMMCTL2_H); +sfr_w(PMMIFG); /* PMM interrupt flag register */ +sfr_b(PMMIFG_L); +sfr_b(PMMIFG_H); +sfr_w(PM5CTL0); /* Power mode 5 control register 0 */ +sfr_b(PM5CTL0_L); +sfr_b(PM5CTL0_H); + +/* PMM Register Offsets */ +#define OFS_PMMCTL0 (0x0000) +#define OFS_PMMCTL1 (0x0002) +#define OFS_PMMCTL2 (0x0004) +#define OFS_PMMIFG (0x000A) +#define OFS_PM5CTL0 (0x0010) + +/* PMM Control Bits */ + +/* PMMCTL0 Control Bits */ +#define PMMSWBOR (0x0004) /* Software brownout reset. */ +#define PMMSWBOR_0 (0x0000) /* Normal operation */ +#define PMMSWBOR_1 (0x0004) /* Set to 1 to trigger a BOR */ +#define PMMSWPOR (0x0008) /* Software POR. */ +#define PMMSWPOR_0 (0x0000) /* Normal operation */ +#define PMMSWPOR_1 (0x0008) /* Set to 1 to trigger a POR */ +#define PMMREGOFF (0x0010) /* Regulator off */ +#define PMMREGOFF_0 (0x0000) /* Regulator remains on when going into LPM3 or LPM4 */ +#define PMMREGOFF_1 (0x0010) /* Regulator is turned off when going to LPM3 or LPM4. System + enters LPM3.5 or LPM4.5, respectively. */ +#define SVSHE (0x0040) /* High-side SVS enable. */ +#define SVSHE_0 (0x0000) /* High-side SVS (SVSH) is disabled in LPM2, LPM3, LPM4, LPM3.5, + and LPM4.5. SVSH is always enabled in active mode, LPM0, and + LPM1. */ +#define SVSHE_1 (0x0040) /* SVSH is always enabled. */ +#define PMMPW (0xa500) /* PMM password. */ +#define PMMPW0 (0x0100) /* PMM password. */ +#define PMMPW1 (0x0200) /* PMM password. */ +#define PMMPW2 (0x0400) /* PMM password. */ +#define PMMPW3 (0x0800) /* PMM password. */ +#define PMMPW4 (0x1000) /* PMM password. */ +#define PMMPW5 (0x2000) /* PMM password. */ +#define PMMPW6 (0x4000) /* PMM password. */ +#define PMMPW7 (0x8000) /* PMM password. */ + +/* PMMCTL2 Control Bits */ +#define INTREFEN (0x0001) /* */ +#define INTREFEN_0 (0x0000) /* Disable internal reference */ +#define INTREFEN_1 (0x0001) /* Enable internal reference */ +#define EXTREFEN (0x0002) /* */ +#define EXTREFEN_0 (0x0000) /* Disable external reference output */ +#define EXTREFEN_1 (0x0002) /* Enable internal reference output */ +#define PWRMODE (0xc000) /* */ +#define PWRMODE0 (0x4000) /* */ +#define PWRMODE1 (0x8000) /* */ +#define TSENSOREN (0x0008) /* */ +#define TSENSOREN_0 (0x0000) /* Disable temperature sensor */ +#define TSENSOREN_1 (0x0008) /* Enable temperature sensor */ +#define REFGENACT (0x0100) /* */ +#define REFGENACT_0 (0x0000) /* Reference generator not active */ +#define REFGENACT_1 (0x0100) /* Reference generator active */ +#define REFBGACT (0x0200) /* */ +#define REFBGACT_0 (0x0000) /* Reference bandgap buffer not active */ +#define REFBGACT_1 (0x0200) /* Reference bandgap buffer active */ +#define BGMODE (0x0800) /* */ +#define BGMODE_0 (0x0000) /* Static mode (higher precision) */ +#define BGMODE_1 (0x0800) /* Sampled mode (lower power consumption) */ +#define REFGENRDY (0x1000) /* */ +#define REFGENRDY_0 (0x0000) /* Reference voltage output is not ready to be used. */ +#define REFGENRDY_1 (0x1000) /* Reference voltage output is ready to be used */ +#define REFBGRDY (0x2000) /* */ +#define REFBGRDY_0 (0x0000) /* Buffered bandgap voltage is not ready to be used */ +#define REFBGRDY_1 (0x2000) /* Buffered bandgap voltage is ready to be used */ +#define REFVSEL (0x0030) /* */ +#define REFVSEL0 (0x0010) /* */ +#define REFVSEL1 (0x0020) /* */ +#define REFVSEL_0 (0x0000) /* 00b = 1.5V */ +#define REFVSEL_1 (0x0010) /* 01b = 2.0V */ +#define REFVSEL_2 (0x0020) /* 10b = 2.5V */ +#define REFVSEL_3 (0x0030) /* 11b = Reserved */ +#define REFGEN (0x0040) /* */ +#define REFGEN_0 (0x0000) /* No trigger */ +#define REFGEN_1 (0x0040) /* Generation of the reference voltage is started by writing 1 or + by a hardware trigger */ +#define REFBGEN (0x0080) /* */ +#define REFBG_0 (0x0000) /* No trigger */ +#define REFBG_1 (0x0080) /* Generation of the bandgap voltage is started by writing 1 or + by a hardware trigger */ + +/* PMMIFG Control Bits */ +#define PMMBORIFG (0x0100) /* PMM software brownout reset interrupt flag. */ +#define PMMBORIFG_0 (0x0000) /* Reset not due to PMMSWBOR */ +#define PMMBORIFG_1 (0x0100) /* Reset due to PMMSWBOR */ +#define PMMRSTIFG (0x0200) /* PMM reset pin interrupt flag. */ +#define PMMRSTIFG_0 (0x0000) /* Reset not due to reset pin */ +#define PMMRSTIFG_1 (0x0200) /* Reset due to reset pin */ +#define PMMPORIFG (0x0400) /* PMM software POR interrupt flag. */ +#define PMMPORIFG_0 (0x0000) /* Reset not due to PMMSWPOR */ +#define PMMPORIFG_1 (0x0400) /* Reset due to PMMSWPOR */ +#define SPWRIFG (0x0800) /* */ +#define SVSHIFG (0x2000) /* High-side SVS interrupt flag. */ +#define SVSHIFG_0 (0x0000) /* Reset not due to SVSH */ +#define SVSHIFG_1 (0x2000) /* Reset due to SVSH */ +#define PMMLPM5IFG (0x8000) /* LPMx.5 flag. */ +#define PMMLPM5IFG_0 (0x0000) /* Reset not due to wake-up from LPMx.5 */ +#define PMMLPM5IFG_1 (0x8000) /* Reset due to wake-up from LPMx.5 */ +#define PMMSPSIFG (0x0001) /* */ +#define PPWRIFG (0x1000) /* */ + +/* PM5CTL0 Control Bits */ +#define LOCKLPM5 (0x0001) /* LPMx.5 Lock Bit */ +#define LOCKLPM5_0 (0x0000) /* LPMx.5 configuration is not locked and defaults to its reset + condition. */ +#define LOCKLPM5_1 (0x0001) /* LPMx.5 configuration remains locked. Pin state is held during + LPMx.5 entry and exit. */ +#define LPM5SW (0x0010) /* */ +#define LPM5SW_0 (0x0000) /* LPMx.5 switch disconnected */ +#define LPM5SW_1 (0x0010) /* LPMx.5 switch connected */ +#define LPM5SM (0x0020) /* */ +#define LPM5SM_0 (0x0000) /* Automatic mode for LPM3.5 switch that the switch is fully + handled by the circuitry during mode switch. */ +#define LPM5SM_1 (0x0020) /* Manual mode for LPM3.5 switch that the switch is specified by + LPM5SW bit setting in software. */ + + +/***************************************************************************** + RTC Registers +*****************************************************************************/ + +#define __MSP430_HAS_RTC__ /* Definition to show that module is available */ +#define __MSP430_BASEADDRESS_RTC__ 0x0300 +#define RTC_BASE __MSP430_BASEADDRESS_RTC__ + +sfr_w(RTCCTL); /* RTCCTL0 Register */ +sfr_b(RTCCTL_L); +sfr_b(RTCCTL_H); +sfr_w(RTCIV); /* Real-Time Clock Interrupt Vector Register */ +sfr_b(RTCIV_L); +sfr_b(RTCIV_H); +sfr_w(RTCMOD); /* RTC Counter Modulo Register */ +sfr_b(RTCMOD_L); +sfr_b(RTCMOD_H); +sfr_w(RTCCNT); /* RTC Counter Register */ +sfr_b(RTCCNT_L); +sfr_b(RTCCNT_H); + +/* RTC Register Offsets */ +#define OFS_RTCCTL (0x0000) +#define OFS_RTCIV (0x0004) +#define OFS_RTCMOD (0x0008) +#define OFS_RTCCNT (0x000C) + +/* RTC Control Bits */ + +/* RTCCTL Control Bits */ +#define RTCIFG (0x0001) /* */ +#define RTCIFG_0 (0x0000) /* No interrupt pending */ +#define RTCIFG_1 (0x0001) /* Interrupt pending */ +#define RTCIE (0x0002) /* */ +#define RTCIE_0 (0x0000) /* Interrupt disabled */ +#define RTCIE_1 (0x0002) /* Interrupt enabled */ +#define RTCSR (0x0040) /* */ +#define RTCSR_0 (0x0000) /* Write 0 has no effect */ +#define RTCSR_1 (0x0040) /* Write 1 to this bit clears the counter value and reloads the + shadow register value from the modulo register at the next + tick of the selected source clock. No overflow event or + interrupt is generated. */ +#define RTCPS (0x0700) /* */ +#define RTCPS0 (0x0100) /* */ +#define RTCPS1 (0x0200) /* */ +#define RTCPS2 (0x0400) /* */ +#define RTCPS_0 (0x0000) /* /1 */ +#define RTCPS_1 (0x0100) /* /10 */ +#define RTCPS_2 (0x0200) /* /100 */ +#define RTCPS_3 (0x0300) /* /1000 */ +#define RTCPS_4 (0x0400) /* /16 */ +#define RTCPS_5 (0x0500) /* /64 */ +#define RTCPS_6 (0x0600) /* /256 */ +#define RTCPS_7 (0x0700) /* /1024 */ +#define RTCPS__1 (0x0000) /* /1 */ +#define RTCPS__10 (0x0100) /* /10 */ +#define RTCPS__100 (0x0200) /* /100 */ +#define RTCPS__1000 (0x0300) /* /1000 */ +#define RTCPS__16 (0x0400) /* /16 */ +#define RTCPS__64 (0x0500) /* /64 */ +#define RTCPS__256 (0x0600) /* /256 */ +#define RTCPS__1024 (0x0700) /* /1024 */ +#define RTCSS (0x3000) /* */ +#define RTCSS0 (0x1000) /* */ +#define RTCSS1 (0x2000) /* */ +#define RTCSS_0 (0x0000) /* Disabled */ +#define RTCSS_1 (0x1000) /* SMCLK */ +#define RTCSS_2 (0x2000) /* XT1CLK */ +#define RTCSS_3 (0x3000) /* VLOCLK */ +#define RTCSS__DISABLED (0x0000) /* Disabled */ +#define RTCSS__SMCLK (0x1000) /* SMCLK */ +#define RTCSS__XT1CLK (0x2000) /* XT1CLK */ +#define RTCSS__VLOCLK (0x3000) /* VLOCLK */ + +/* RTCIV Control Bits */ +#define RTCIV0 (0x0001) /* Real-time clock interrupt vector value */ +#define RTCIV1 (0x0002) /* Real-time clock interrupt vector value */ +#define RTCIV2 (0x0004) /* Real-time clock interrupt vector value */ +#define RTCIV3 (0x0008) /* Real-time clock interrupt vector value */ +#define RTCIV4 (0x0010) /* Real-time clock interrupt vector value */ +#define RTCIV5 (0x0020) /* Real-time clock interrupt vector value */ +#define RTCIV6 (0x0040) /* Real-time clock interrupt vector value */ +#define RTCIV7 (0x0080) /* Real-time clock interrupt vector value */ +#define RTCIV8 (0x0100) /* Real-time clock interrupt vector value */ +#define RTCIV9 (0x0200) /* Real-time clock interrupt vector value */ +#define RTCIV10 (0x0400) /* Real-time clock interrupt vector value */ +#define RTCIV11 (0x0800) /* Real-time clock interrupt vector value */ +#define RTCIV12 (0x1000) /* Real-time clock interrupt vector value */ +#define RTCIV13 (0x2000) /* Real-time clock interrupt vector value */ +#define RTCIV14 (0x4000) /* Real-time clock interrupt vector value */ +#define RTCIV15 (0x8000) /* Real-time clock interrupt vector value */ +#define RTCIV_0 (0x0000) /* No interrupt pending */ +#define RTCIV_2 (0x0002) /* upt Source: RTC Counter Overflow; Interrupt Flag: RTCIFG */ +#define RTCIV__NONE (0x0000) /* No interrupt pending */ +#define RTCIV__RTCIFG (0x0002) /* upt Source: RTC Counter Overflow; Interrupt Flag: RTCIFG */ + + +/***************************************************************************** + SFR Registers +*****************************************************************************/ + +#define __MSP430_HAS_SFR__ /* Definition to show that module is available */ +#define __MSP430_BASEADDRESS_SFR__ 0x0100 +#define SFR_BASE __MSP430_BASEADDRESS_SFR__ + +sfr_w(SFRIE1); /* Interrupt Enable */ +sfr_b(SFRIE1_L); +sfr_b(SFRIE1_H); +sfr_w(SFRIFG1); /* Interrupt Flag */ +sfr_b(SFRIFG1_L); +sfr_b(SFRIFG1_H); +sfr_w(SFRRPCR); /* Reset Pin Control */ +sfr_b(SFRRPCR_L); +sfr_b(SFRRPCR_H); + +/* SFR Register Offsets */ +#define OFS_SFRIE1 (0x0000) +#define OFS_SFRIFG1 (0x0002) +#define OFS_SFRRPCR (0x0004) + +/* SFR Control Bits */ + +/* SFRIE1 Control Bits */ +#define WDTIE (0x0001) /* Watchdog timer interrupt enable */ +#define WDTIE_0 (0x0000) /* Interrupts disabled */ +#define WDTIE_1 (0x0001) /* Interrupts enabled */ +#define WDTIE__DISABLE (0x0000) /* Interrupts disabled */ +#define WDTIE__ENABLE (0x0001) /* Interrupts enabled */ +#define OFIE (0x0002) /* Oscillator fault interrupt enable */ +#define OFIE_0 (0x0000) /* Interrupts disabled */ +#define OFIE_1 (0x0002) /* Interrupts enabled */ +#define OFIE__DISABLE (0x0000) /* Interrupts disabled */ +#define OFIE__ENABLE (0x0002) /* Interrupts enabled */ +#define VMAIE (0x0008) /* Vacant memory access interrupt enable */ +#define VMAIE_0 (0x0000) /* Interrupts disabled */ +#define VMAIE_1 (0x0008) /* Interrupts enabled */ +#define VMAIE__DISABLE (0x0000) /* Interrupts disabled */ +#define VMAIE__ENABLE (0x0008) /* Interrupts enabled */ +#define NMIIE (0x0010) /* NMI pin interrupt enable */ +#define NMIIE_0 (0x0000) /* Interrupts disabled */ +#define NMIIE_1 (0x0010) /* Interrupts enabled */ +#define NMIIE__DISABLE (0x0000) /* Interrupts disabled */ +#define NMIIE__ENABLE (0x0010) /* Interrupts enabled */ +#define JMBINIE (0x0040) /* JTAG mailbox input interrupt enable */ +#define JMBINIE_0 (0x0000) /* Interrupts disabled */ +#define JMBINIE_1 (0x0040) /* Interrupts enabled */ +#define JMBINIE__DISABLE (0x0000) /* Interrupts disabled */ +#define JMBINIE__ENABLE (0x0040) /* Interrupts enabled */ +#define JMBOUTIE (0x0080) /* JTAG mailbox output interrupt enable */ +#define JMBOUTIE_0 (0x0000) /* Interrupts disabled */ +#define JMBOUTIE_1 (0x0080) /* Interrupts enabled */ +#define JMBOUTIE__DISABLE (0x0000) /* Interrupts disabled */ +#define JMBOUTIE__ENABLE (0x0080) /* Interrupts enabled */ + +/* SFRIFG1 Control Bits */ +#define OFIFG (0x0002) /* Oscillator fault interrupt flag */ +#define OFIFG_0 (0x0000) /* No interrupt pending */ +#define OFIFG_1 (0x0002) /* Interrupt pending */ +#define VMAIFG (0x0008) /* Vacant memory access interrupt flag */ +#define VMAIFG_0 (0x0000) /* No interrupt pending */ +#define VMAIFG_1 (0x0008) /* Interrupt pending */ +#define NMIIFG (0x0010) /* NMI pin interrupt flag */ +#define NMIIFG_0 (0x0000) /* No interrupt pending */ +#define NMIIFG_1 (0x0010) /* Interrupt pending */ +#define WDTIFG (0x0001) /* Watchdog timer interrupt flag */ +#define WDTIFG_0 (0x0000) /* No interrupt pending */ +#define WDTIFG_1 (0x0001) /* Interrupt pending */ +#define JMBINIFG (0x0040) /* JTAG mailbox input interrupt flag */ +#define JMBINIFG_0 (0x0000) /* No interrupt pending. When in 16-bit mode (JMBMODE = 0), this + bit is cleared automatically when JMBI0 is read by the CPU. + When in 32-bit mode (JMBMODE = 1), this bit is cleared + automatically when both JMBI0 and JMBI1 have been read by the + CPU. This bit is also cleared when the associated vector in + SYSUNIV has been read */ +#define JMBINIFG_1 (0x0040) /* Interrupt pending. A message is waiting in the JMBIN + registers. In 16-bit mode (JMBMODE = 0) when JMBI0 has been + written by the JTAG module. In 32-bit mode (JMBMODE = 1) when + JMBI0 and JMBI1 have been written by the JTAG module. */ +#define JMBOUTIFG (0x0080) /* JTAG mailbox output interrupt flag */ +#define JMBOUTIFG_0 (0x0000) /* No interrupt pending. When in 16-bit mode (JMBMODE = 0), this + bit is cleared automatically when JMBO0 has been written with + a new message to the JTAG module by the CPU. When in 32-bit + mode (JMBMODE = 1), this bit is cleared automatically when + both JMBO0 and JMBO1 have been written with new messages to + the JTAG module by the CPU. This bit is also cleared when the + associated vector in SYSUNIV has been read. */ +#define JMBOUTIFG_1 (0x0080) /* Interrupt pending. JMBO registers are ready for new messages. + In 16-bit mode (JMBMODE = 0), JMBO0 has been received by the + JTAG module and is ready for a new message from the CPU. In + 32-bit mode (JMBMODE = 1), JMBO0 and JMBO1 have been received + by the JTAG module and are ready for new messages from the + CPU. */ + +/* SFRRPCR Control Bits */ +#define SYSNMI (0x0001) /* NMI select */ +#define SYSNMI_0 (0x0000) /* Reset function */ +#define SYSNMI_1 (0x0001) /* NMI function */ +#define SYSNMI__RESET (0x0000) /* Reset function */ +#define SYSNMI__NMI (0x0001) /* NMI function */ +#define SYSNMIIES (0x0002) /* NMI edge select */ +#define SYSNMIIES_0 (0x0000) /* NMI on rising edge */ +#define SYSNMIIES_1 (0x0002) /* NMI on falling edge */ +#define SYSNMIIES__RISING (0x0000) /* NMI on rising edge */ +#define SYSNMIIES__FALLING (0x0002) /* NMI on falling edge */ +#define SYSRSTUP (0x0004) /* Reset resistor pin pullup or pulldown */ +#define SYSRSTUP_0 (0x0000) /* Pulldown is selected */ +#define SYSRSTUP_1 (0x0004) /* Pullup is selected */ +#define SYSRSTUP__PULLDOWN (0x0000) /* Pulldown is selected */ +#define SYSRSTUP__PULLUP (0x0004) /* Pullup is selected */ +#define SYSRSTRE (0x0008) /* Reset pin resistor enable */ +#define SYSRSTRE_0 (0x0000) /* Pullup or pulldown resistor at the RST/NMI pin is disabled */ +#define SYSRSTRE_1 (0x0008) /* Pullup or pulldown resistor at the RST/NMI pin is enabled */ +#define SYSRSTRE__DISABLE (0x0000) /* Pullup or pulldown resistor at the RST/NMI pin is disabled */ +#define SYSRSTRE__ENABLE (0x0008) /* Pullup or pulldown resistor at the RST/NMI pin is enabled */ +#define SYSFLTE (0x0010) /* Reset pin filter enable */ +#define SYSFLTE_0 (0x0000) /* Digital filter on reset pin is disabled */ +#define SYSFLTE_1 (0x0010) /* Digital filter on reset pin is enabled */ +#define SYSFLTE__DISABLED (0x0000) /* Digital filter on reset pin is disabled */ +#define SYSFLTE__ENABLED (0x0010) /* Digital filter on reset pin is enabled */ + + +/***************************************************************************** + SYS Registers +*****************************************************************************/ + +#define __MSP430_HAS_SYS__ /* Definition to show that module is available */ +#define __MSP430_BASEADDRESS_SYS__ 0x0140 +#define SYS_BASE __MSP430_BASEADDRESS_SYS__ + +sfr_w(SYSCTL); /* System Control */ +sfr_b(SYSCTL_L); +sfr_b(SYSCTL_H); +sfr_w(SYSBSLC); /* Bootloader Configuration */ +sfr_b(SYSBSLC_L); +sfr_b(SYSBSLC_H); +sfr_w(SYSJMBC); /* JTAG Mailbox Control */ +sfr_b(SYSJMBC_L); +sfr_b(SYSJMBC_H); +sfr_w(SYSJMBI0); /* JTAG Mailbox Input 0 */ +sfr_b(SYSJMBI0_L); +sfr_b(SYSJMBI0_H); +sfr_w(SYSJMBI1); /* JTAG Mailbox Input 1 */ +sfr_b(SYSJMBI1_L); +sfr_b(SYSJMBI1_H); +sfr_w(SYSJMBO0); /* JTAG Mailbox Output 0 */ +sfr_b(SYSJMBO0_L); +sfr_b(SYSJMBO0_H); +sfr_w(SYSJMBO1); /* JTAG Mailbox Output 1 */ +sfr_b(SYSJMBO1_L); +sfr_b(SYSJMBO1_H); +sfr_w(SYSUNIV); /* User NMI Vector Generator */ +sfr_b(SYSUNIV_L); +sfr_b(SYSUNIV_H); +sfr_w(SYSSNIV); /* System NMI Vector Generator */ +sfr_b(SYSSNIV_L); +sfr_b(SYSSNIV_H); +sfr_w(SYSRSTIV); /* Reset Vector Generator */ +sfr_b(SYSRSTIV_L); +sfr_b(SYSRSTIV_H); +sfr_w(SYSCFG0); /* System Configuration 0 */ +sfr_b(SYSCFG0_L); +sfr_b(SYSCFG0_H); +sfr_w(SYSCFG1); /* System Configuration 1 */ +sfr_b(SYSCFG1_L); +sfr_b(SYSCFG1_H); +sfr_w(SYSCFG2); /* System Configuration 2 */ +sfr_b(SYSCFG2_L); +sfr_b(SYSCFG2_H); +sfr_w(SYSCFG3); /* System Configuration 3 */ +sfr_b(SYSCFG3_L); +sfr_b(SYSCFG3_H); + +/* SYS Register Offsets */ +#define OFS_SYSCTL (0x0000) +#define OFS_SYSBSLC (0x0002) +#define OFS_SYSJMBC (0x0006) +#define OFS_SYSJMBI0 (0x0008) +#define OFS_SYSJMBI1 (0x000A) +#define OFS_SYSJMBO0 (0x000C) +#define OFS_SYSJMBO1 (0x000E) +#define OFS_SYSUNIV (0x001A) +#define OFS_SYSSNIV (0x001C) +#define OFS_SYSRSTIV (0x001E) +#define OFS_SYSCFG0 (0x0020) +#define OFS_SYSCFG1 (0x0022) +#define OFS_SYSCFG2 (0x0024) +#define OFS_SYSCFG3 (0x0026) + +/* SYS Control Bits */ + +/* SYSCTL Control Bits */ +#define SYSRIVECT (0x0001) /* RAM-based interrupt vectors */ +#define SYSRIVECT_0 (0x0000) /* Interrupt vectors generated with end address TOP of lower 64K + FRAM FFFFh */ +#define SYSRIVECT_1 (0x0001) /* Interrupt vectors generated with end address TOP of RAM, when + RAM available */ +#define SYSRIVECT__FRAM (0x0000) /* Interrupt vectors generated with end address TOP of lower 64K + FRAM FFFFh */ +#define SYSRIVECT__RAM (0x0001) /* Interrupt vectors generated with end address TOP of RAM, when + RAM available */ +#define SYSPMMPE (0x0004) /* PMM access protect */ +#define SYSPMMPE_0 (0x0000) /* Access from anywhere in memory */ +#define SYSPMMPE_1 (0x0004) /* Access only from the BSL segments */ +#define SYSPMMPE__DIS (0x0000) /* Access from anywhere in memory */ +#define SYSPMMPE__EN (0x0004) /* Access only from the BSL segments */ +#define SYSBSLIND (0x0010) /* BSL entry indication */ +#define SYSBSLIND_0 (0x0000) /* No BSL entry sequence detected */ +#define SYSBSLIND_1 (0x0010) /* BSL entry sequence detected */ +#define SYSBSLIND__CLR (0x0000) /* No BSL entry sequence detected */ +#define SYSBSLIND__SET (0x0010) /* BSL entry sequence detected */ +#define SYSJTAGPIN (0x0020) /* Dedicated JTAG pins enable */ +#define SYSJTAGPIN_0 (0x0000) /* Shared JTAG pins (JTAG mode selectable using SBW sequence) */ +#define SYSJTAGPIN_1 (0x0020) /* Dedicated JTAG pins (explicit 4-wire JTAG mode selection) */ +#define SYSJTAGPIN__SHARED (0x0000) /* Shared JTAG pins (JTAG mode selectable using SBW sequence) */ +#define SYSJTAGPIN__DEDICATED (0x0020) /* Dedicated JTAG pins (explicit 4-wire JTAG mode selection) */ + +/* SYSBSLC Control Bits */ +#define SYSBSLR (0x0004) /* */ +#define SYSBSLR_0 (0x0000) /* No RAM assigned to BSL area */ +#define SYSBSLR_1 (0x0004) /* Lowest 16 bytes of RAM assigned to BSL */ +#define SYSBSLR__NORAM (0x0000) /* No RAM assigned to BSL area */ +#define SYSBSLR__RAM (0x0004) /* Lowest 16 bytes of RAM assigned to BSL */ +#define SYSBSLOFF (0x4000) /* */ +#define SYSBSLOFF_0 (0x0000) /* BSL memory is addressed when this area is read. */ +#define SYSBSLOFF_1 (0x4000) /* BSL memory behaves like vacant memory. Reads cause 3FFFh to be + read. Fetches cause JMP $ to be executed. */ +#define SYSBSLOFF__ON (0x0000) /* BSL memory is addressed when this area is read. */ +#define SYSBSLOFF__OFF (0x4000) /* BSL memory behaves like vacant memory. Reads cause 3FFFh to be + read. Fetches cause JMP $ to be executed. */ +#define SYSBSLPE (0x8000) /* */ +#define SYSBSLPE_0 (0x0000) /* Area not protected. Read, program, and erase of BSL memory is + possible. */ +#define SYSBSLPE_1 (0x8000) /* Area protected */ +#define SYSBSLPE__NOTPROT (0x0000) /* Area not protected. Read, program, and erase of BSL memory is + possible. */ +#define SYSBSLPE__PROT (0x8000) /* Area protected */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG (0x0001) /* Incoming JTAG Mailbox 0 flag */ +#define JMBIN0FG_0 (0x0000) /* JMBI0 has no new data */ +#define JMBIN0FG_1 (0x0001) /* JMBI0 has new data available */ +#define JMBIN0FG__NODAT (0x0000) /* JMBI0 has no new data */ +#define JMBIN0FG__NEWDAT (0x0001) /* JMBI0 has new data available */ +#define JMBIN1FG (0x0002) /* Incoming JTAG Mailbox 1 flag */ +#define JMBIN1FG_0 (0x0000) /* JMBI1 has no new data */ +#define JMBIN1FG_1 (0x0002) /* JMBI1 has new data available */ +#define JMBIN1FG__NODAT (0x0000) /* JMBI1 has no new data */ +#define JMBIN1FG__NEWDAT (0x0002) /* JMBI1 has new data available */ +#define JMBOUT0FG (0x0004) /* Outgoing JTAG Mailbox 0 flag */ +#define JMBOUT0FG_0 (0x0000) /* JMBO0 is not ready to receive new data */ +#define JMBOUT0FG_1 (0x0004) /* JMBO0 is ready to receive new data */ +#define JMBOUT0FG__BUSY (0x0000) /* JMBO0 is not ready to receive new data */ +#define JMBOUT0FG__READY (0x0004) /* JMBO0 is ready to receive new data */ +#define JMBOUT1FG (0x0008) /* Outgoing JTAG Mailbox 1 flag */ +#define JMBOUT1FG_0 (0x0000) /* JMBO1 is not ready to receive new data */ +#define JMBOUT1FG_1 (0x0008) /* JMBO1 is ready to receive new data */ +#define JMBOUT1FG__BUSY (0x0000) /* JMBO1 is not ready to receive new data */ +#define JMBOUT1FG__READY (0x0008) /* JMBO1 is ready to receive new data */ +#define JMBMODE (0x0010) /* Operation mode of JMB */ +#define JMBMODE_0 (0x0000) /* 16-bit transfers using JMBO0 and JMBI0 only */ +#define JMBMODE_1 (0x0010) /* 32-bit transfers using JMBO0 with JMBO1 and JMBI0 with JMBI1 */ +#define JMBMODE__16BIT (0x0000) /* 16-bit transfers using JMBO0 and JMBI0 only */ +#define JMBMODE__32BIT (0x0010) /* 32-bit transfers using JMBO0 with JMBO1 and JMBI0 with JMBI1 */ +#define JMBCLR0OFF (0x0040) /* Incoming JTAG Mailbox 0 flag auto-clear disable */ +#define JMBCLR0OFF_0 (0x0000) /* JMBIN0FG cleared on read of JMB0IN register */ +#define JMBCLR0OFF_1 (0x0040) /* JMBIN0FG cleared by software */ +#define JMBCLR0OFF__CLRORD (0x0000) /* JMBIN0FG cleared on read of JMB0IN register */ +#define JMBCLR0OFF__CLRBSW (0x0040) /* JMBIN0FG cleared by software */ +#define JMBCLR1OFF (0x0080) /* Incoming JTAG Mailbox 1 flag auto-clear disable */ +#define JMBCLR1OFF_0 (0x0000) /* JMBIN1FG cleared on read of JMB1IN register */ +#define JMBCLR1OFF_1 (0x0080) /* JMBIN1FG cleared by software */ +#define JMBCLR1OFF__CLRORD (0x0000) /* JMBIN1FG cleared on read of JMB1IN register */ +#define JMBCLR1OFF__CLRBSW (0x0080) /* JMBIN1FG cleared by software */ + +/* SYSJMBI0 Control Bits */ +#define MSGLO (0x00ff) /* JTAG mailbox incoming message low byte */ +#define MSGLO0 (0x0001) /* JTAG mailbox incoming message low byte */ +#define MSGLO1 (0x0002) /* JTAG mailbox incoming message low byte */ +#define MSGLO2 (0x0004) /* JTAG mailbox incoming message low byte */ +#define MSGLO3 (0x0008) /* JTAG mailbox incoming message low byte */ +#define MSGLO4 (0x0010) /* JTAG mailbox incoming message low byte */ +#define MSGLO5 (0x0020) /* JTAG mailbox incoming message low byte */ +#define MSGLO6 (0x0040) /* JTAG mailbox incoming message low byte */ +#define MSGLO7 (0x0080) /* JTAG mailbox incoming message low byte */ +#define MSGHI (0xff00) /* JTAG mailbox incoming message high byte */ +#define MSGHI0 (0x0100) /* JTAG mailbox incoming message high byte */ +#define MSGHI1 (0x0200) /* JTAG mailbox incoming message high byte */ +#define MSGHI2 (0x0400) /* JTAG mailbox incoming message high byte */ +#define MSGHI3 (0x0800) /* JTAG mailbox incoming message high byte */ +#define MSGHI4 (0x1000) /* JTAG mailbox incoming message high byte */ +#define MSGHI5 (0x2000) /* JTAG mailbox incoming message high byte */ +#define MSGHI6 (0x4000) /* JTAG mailbox incoming message high byte */ +#define MSGHI7 (0x8000) /* JTAG mailbox incoming message high byte */ + +/* SYSUNIV Control Bits */ +#define SYSUNIV0 (0x0001) /* User NMI vector */ +#define SYSUNIV1 (0x0002) /* User NMI vector */ +#define SYSUNIV2 (0x0004) /* User NMI vector */ +#define SYSUNIV3 (0x0008) /* User NMI vector */ +#define SYSUNIV4 (0x0010) /* User NMI vector */ +#define SYSUNIV5 (0x0020) /* User NMI vector */ +#define SYSUNIV6 (0x0040) /* User NMI vector */ +#define SYSUNIV7 (0x0080) /* User NMI vector */ +#define SYSUNIV8 (0x0100) /* User NMI vector */ +#define SYSUNIV9 (0x0200) /* User NMI vector */ +#define SYSUNIV10 (0x0400) /* User NMI vector */ +#define SYSUNIV11 (0x0800) /* User NMI vector */ +#define SYSUNIV12 (0x1000) /* User NMI vector */ +#define SYSUNIV13 (0x2000) /* User NMI vector */ +#define SYSUNIV14 (0x4000) /* User NMI vector */ +#define SYSUNIV15 (0x8000) /* User NMI vector */ +#define SYSUNIV_0 (0x0000) /* No interrupt pending */ +#define SYSUNIV_2 (0x0002) /* NMIFG NMI pin or SVSH event */ +#define SYSUNIV_4 (0x0004) /* OFIFG oscillator fault */ +#define SYSUNIV__NONE (0x0000) /* No interrupt pending */ +#define SYSUNIV__NMIIFG (0x0002) /* NMIFG NMI pin or SVSH event */ +#define SYSUNIV__OFIFG (0x0004) /* OFIFG oscillator fault */ + +/* SYSSNIV Control Bits */ +#define SYSSNIV0 (0x0001) /* System NMI vector */ +#define SYSSNIV1 (0x0002) /* System NMI vector */ +#define SYSSNIV2 (0x0004) /* System NMI vector */ +#define SYSSNIV3 (0x0008) /* System NMI vector */ +#define SYSSNIV4 (0x0010) /* System NMI vector */ +#define SYSSNIV5 (0x0020) /* System NMI vector */ +#define SYSSNIV6 (0x0040) /* System NMI vector */ +#define SYSSNIV7 (0x0080) /* System NMI vector */ +#define SYSSNIV8 (0x0100) /* System NMI vector */ +#define SYSSNIV9 (0x0200) /* System NMI vector */ +#define SYSSNIV10 (0x0400) /* System NMI vector */ +#define SYSSNIV11 (0x0800) /* System NMI vector */ +#define SYSSNIV12 (0x1000) /* System NMI vector */ +#define SYSSNIV13 (0x2000) /* System NMI vector */ +#define SYSSNIV14 (0x4000) /* System NMI vector */ +#define SYSSNIV15 (0x8000) /* System NMI vector */ +#define SYSSNIV_0 (0x0000) /* No interrupt pending */ +#define SYSSNIV_2 (0x0002) /* SVS low-power reset entry */ +#define SYSSNIV_4 (0x0004) /* Uncorrectable FRAM bit error detection */ +#define SYSSNIV_6 (0x0006) /* Reserved */ +#define SYSSNIV_8 (0x0008) /* Reserved */ +#define SYSSNIV_10 (0x000a) /* Reserved */ +#define SYSSNIV_12 (0x000c) /* Reserved */ +#define SYSSNIV_14 (0x000e) /* Reserved */ +#define SYSSNIV_16 (0x0010) /* Reserved */ +#define SYSSNIV_18 (0x0012) /* VMAIFG Vacant memory access */ +#define SYSSNIV_20 (0x0014) /* JMBINIFG JTAG mailbox input */ +#define SYSSNIV_22 (0x0016) /* JMBOUTIFG JTAG mailbox output */ +#define SYSSNIV_24 (0x0018) /* Correctable FRAM bit error detection */ +#define SYSSNIV__NONE (0x0000) /* No interrupt pending */ +#define SYSSNIV__SVSLIFG (0x0002) /* SVS low-power reset entry */ +#define SYSSNIV__UBDIFG (0x0004) /* Uncorrectable FRAM bit error detection */ +#define SYSSNIV__VMAIFG (0x0012) /* VMAIFG Vacant memory access */ +#define SYSSNIV__JMBINIFG (0x0014) /* JMBINIFG JTAG mailbox input */ +#define SYSSNIV__JMBOUTIFG (0x0016) /* JMBOUTIFG JTAG mailbox output */ +#define SYSSNIV__CBDIFG (0x0018) /* Correctable FRAM bit error detection */ + +/* SYSRSTIV Control Bits */ +#define SYSRSTIV0 (0x0001) /* Reset interrupt vector */ +#define SYSRSTIV1 (0x0002) /* Reset interrupt vector */ +#define SYSRSTIV2 (0x0004) /* Reset interrupt vector */ +#define SYSRSTIV3 (0x0008) /* Reset interrupt vector */ +#define SYSRSTIV4 (0x0010) /* Reset interrupt vector */ +#define SYSRSTIV5 (0x0020) /* Reset interrupt vector */ +#define SYSRSTIV6 (0x0040) /* Reset interrupt vector */ +#define SYSRSTIV7 (0x0080) /* Reset interrupt vector */ +#define SYSRSTIV8 (0x0100) /* Reset interrupt vector */ +#define SYSRSTIV9 (0x0200) /* Reset interrupt vector */ +#define SYSRSTIV10 (0x0400) /* Reset interrupt vector */ +#define SYSRSTIV11 (0x0800) /* Reset interrupt vector */ +#define SYSRSTIV12 (0x1000) /* Reset interrupt vector */ +#define SYSRSTIV13 (0x2000) /* Reset interrupt vector */ +#define SYSRSTIV14 (0x4000) /* Reset interrupt vector */ +#define SYSRSTIV15 (0x8000) /* Reset interrupt vector */ +#define SYSRSTIV_0 (0x0000) /* No interrupt pending */ +#define SYSRSTIV_2 (0x0002) /* Brownout */ +#define SYSRSTIV_4 (0x0004) /* RSTIFG RST/NMI */ +#define SYSRSTIV_6 (0x0006) /* PMMSWBOR software BOR */ +#define SYSRSTIV_8 (0x0008) /* LPMx.5 wakeup */ +#define SYSRSTIV_10 (0x000a) /* Security violation */ +#define SYSRSTIV_12 (0x000c) /* Reserved */ +#define SYSRSTIV_14 (0x000e) /* SVSHIFG SVSH event */ +#define SYSRSTIV_16 (0x0010) /* Reserved */ +#define SYSRSTIV_18 (0x0012) /* Reserved */ +#define SYSRSTIV_20 (0x0014) /* PMMSWPOR software POR */ +#define SYSRSTIV_22 (0x0016) /* WDTIFG watchdog timeout */ +#define SYSRSTIV_24 (0x0018) /* WDTPW watchdog password violation */ +#define SYSRSTIV_26 (0x001a) /* FRCTLPW password violation */ +#define SYSRSTIV_28 (0x001c) /* Uncorrectable FRAM bit error detection */ +#define SYSRSTIV_30 (0x001e) /* Peripheral area fetch */ +#define SYSRSTIV_32 (0x0020) /* PMM password violation */ +#define SYSRSTIV_34 (0x0022) /* Reserved */ +#define SYSRSTIV_36 (0x0024) /* FLL unlock (PUC) */ +#define SYSRSTIV__NONE (0x0000) /* No interrupt pending */ +#define SYSRSTIV__BOR (0x0002) /* Brownout */ +#define SYSRSTIV__RSTNMI (0x0004) /* RSTIFG RST/NMI */ +#define SYSRSTIV__PMMSWBOR (0x0006) /* PMMSWBOR software BOR */ +#define SYSRSTIV__LPM5WU (0x0008) /* LPMx.5 wakeup */ +#define SYSRSTIV__SECYV (0x000a) /* Security violation */ +#define SYSRSTIV__SVSHIFG (0x000e) /* SVSHIFG SVSH event */ +#define SYSRSTIV__PMMSWPOR (0x0014) /* PMMSWPOR software POR */ +#define SYSRSTIV__WDTIFG (0x0016) /* WDTIFG watchdog timeout */ +#define SYSRSTIV__WDTPW (0x0018) /* WDTPW watchdog password violation */ +#define SYSRSTIV__FRCTLPW (0x001a) /* FRCTLPW password violation */ +#define SYSRSTIV__UBDIFG (0x001c) /* Uncorrectable FRAM bit error detection */ +#define SYSRSTIV__PERF (0x001e) /* Peripheral area fetch */ +#define SYSRSTIV__PMMPW (0x0020) /* PMM password violation */ +#define SYSRSTIV__FLLUL (0x0024) /* FLL unlock (PUC) */ + +/* SYSCFG0 Control Bits */ +#define PFWP (0x0001) /* */ +#define PFWP_0 (0x0000) /* Program FRAM write enable */ +#define PFWP_1 (0x0001) /* Program FRAM write protected (not writable) */ +#define PFWP__WEN (0x0000) /* Program FRAM write enable */ +#define PFWP__WPROT (0x0001) /* Program FRAM write protected (not writable) */ +#define FRWPPW (0xa500) /* FRWPPW password. */ +#define FRWPPW0 (0x0100) /* FRWPPW password. */ +#define FRWPPW1 (0x0200) /* FRWPPW password. */ +#define FRWPPW2 (0x0400) /* FRWPPW password. */ +#define FRWPPW3 (0x0800) /* FRWPPW password. */ +#define FRWPPW4 (0x1000) /* FRWPPW password. */ +#define FRWPPW5 (0x2000) /* FRWPPW password. */ +#define FRWPPW6 (0x4000) /* FRWPPW password. */ +#define FRWPPW7 (0x8000) /* FRWPPW password. */ +#define DFWP (0x0002) /* */ +#define DFWP_0 (0x0000) /* Data FRAM write enable */ +#define DFWP_1 (0x0002) /* Data FRAM write protected (not writable) */ +#define DFWP__WEN (0x0000) /* Data FRAM write enable */ +#define DFWP__WPROT (0x0002) /* Data FRAM write protected (not writable) */ +#define FRWPOA (0x00fc) /* */ +#define FRWPOA0 (0x0004) /* */ +#define FRWPOA1 (0x0008) /* */ +#define FRWPOA2 (0x0010) /* */ +#define FRWPOA3 (0x0020) /* */ +#define FRWPOA4 (0x0040) /* */ +#define FRWPOA5 (0x0080) /* */ + +/* SYSCFG1 Control Bits */ +#define IREN (0x0001) /* */ +#define IREN_0 (0x0000) /* Infrared function disabled */ +#define IREN_1 (0x0001) /* Infrared function enabled */ +#define IREN__DIS (0x0000) /* Infrared function disabled */ +#define IREN__EN (0x0001) /* Infrared function enabled */ +#define IRPSEL (0x0002) /* */ +#define IRPSEL_0 (0x0000) /* Normal polarity */ +#define IRPSEL_1 (0x0002) /* Inverted polarity */ +#define IRPSEL__NORM (0x0000) /* Normal polarity */ +#define IRPSEL__INV (0x0002) /* Inverted polarity */ +#define IRMSEL (0x0004) /* */ +#define IRMSEL_0 (0x0000) /* ASK mode */ +#define IRMSEL_1 (0x0004) /* FSK mode */ +#define IRMSEL__ASK (0x0000) /* ASK mode */ +#define IRMSEL__FSK (0x0004) /* FSK mode */ +#define IRDSSEL (0x0008) /* */ +#define IRDSSEL_0 (0x0000) /* From hardware peripherals upon device configuration */ +#define IRDSSEL_1 (0x0008) /* From IRDATA bit */ +#define IRDSSEL__HW (0x0000) /* From hardware peripherals upon device configuration */ +#define IRDSSEL__IRDATA (0x0008) /* From IRDATA bit */ +#define IRDATA (0x0010) /* */ +#define IRDATA_0 (0x0000) /* Infrared data logic 0 */ +#define IRDATA_1 (0x0010) /* Infrared data logic 1 */ +#define IRDATA__LOW (0x0000) /* Infrared data logic 0 */ +#define IRDATA__HIGH (0x0010) /* Infrared data logic 1 */ +#define SYNCSEL (0x00c0) /* */ +#define SYNCSEL0 (0x0040) /* */ +#define SYNCSEL1 (0x0080) /* */ +#define SYNCSEL_0 (0x0000) /* External source is selected */ +#define SYNCSEL_1 (0x0040) /* ADC as the source is selected */ +#define SYNCSEL_2 (0x0080) /* Comparator as the source is selected */ +#define SYNCSEL_3 (0x00c0) /* Reserved */ + +/* SYSCFG2 Control Bits */ +#define RTCCKSEL (0x0400) /* */ +#define RTCCKSEL_0 (0x0000) /* SMCLK is selected */ +#define RTCCKSEL_1 (0x0400) /* ACLK is selected */ +#define USCIB0RMP (0x0800) /* */ +#define USCIB0RMP_0 (0x0000) /* Default function. See the device-specific data sheet for + details. */ +#define USCIB0RMP_1 (0x0800) /* Remapped function. See the device-specific data sheet for + details. */ +#define TB0TRGSEL (0x8000) /* */ +#define TB0TRGSEL_0 (0x0000) /* Internal source is selected */ +#define TB0TRGSEL_1 (0x8000) /* External source is selected */ + +/* SYSCFG3 Control Bits */ +#define USCIA0RMP (0x0001) /* */ +#define USCIA0RMP_0 (0x0000) /* Default function. See the device-specific data sheet for + details. */ +#define USCIA0RMP_1 (0x0001) /* Remapped function. See the device-specific data sheet for + details. */ +#define TA2RMP (0x0004) /* */ +#define TA2RMP_0 (0x0000) /* Default function. See the device-specific data sheet for + details. */ +#define TA2RMP_1 (0x0004) /* Remapped function. See the device-specific data sheet for + details. */ +#define TA3RMP (0x0008) /* */ +#define TA3RMP_0 (0x0000) /* Default function. See the device-specific data sheet for + details. */ +#define TA3RMP_1 (0x0008) /* Remapped function. See the device-specific data sheet for + details. */ +#define USCIB1RMP (0x0010) /* */ +#define USCIB1RMP_0 (0x0000) /* Default function. See the device-specific data sheet for + details. */ +#define USCIB1RMP_1 (0x0010) /* Remapped function. See the device-specific data sheet for + details. */ + + +/***************************************************************************** + TA0 Registers +*****************************************************************************/ + +#define __MSP430_HAS_TA0__ 3 /* Definition to show that module is available */ +#ifndef __MSP430_HAS_TAx__ +#define __MSP430_HAS_TAx__ +#endif +#define __MSP430_BASEADDRESS_TA0__ 0x0380 +#define TA0_BASE __MSP430_BASEADDRESS_TA0__ + +sfr_w(TA0CTL); /* TimerAx Control Register */ +sfr_b(TA0CTL_L); +sfr_b(TA0CTL_H); +sfr_w(TA0CCTL0); /* Timer_A Capture/Compare Control Register */ +sfr_b(TA0CCTL0_L); +sfr_b(TA0CCTL0_H); +sfr_w(TA0CCTL1); /* Timer_A Capture/Compare Control Register */ +sfr_b(TA0CCTL1_L); +sfr_b(TA0CCTL1_H); +sfr_w(TA0CCTL2); /* Timer_A Capture/Compare Control Register */ +sfr_b(TA0CCTL2_L); +sfr_b(TA0CCTL2_H); +sfr_w(TA0R); /* TimerA register */ +sfr_b(TA0R_L); +sfr_b(TA0R_H); +sfr_w(TA0CCR0); /* Timer_A Capture/Compare Register */ +sfr_b(TA0CCR0_L); +sfr_b(TA0CCR0_H); +sfr_w(TA0CCR1); /* Timer_A Capture/Compare Register */ +sfr_b(TA0CCR1_L); +sfr_b(TA0CCR1_H); +sfr_w(TA0CCR2); /* Timer_A Capture/Compare Register */ +sfr_b(TA0CCR2_L); +sfr_b(TA0CCR2_H); +sfr_w(TA0EX0); /* TimerAx Expansion 0 Register */ +sfr_b(TA0EX0_L); +sfr_b(TA0EX0_H); +sfr_w(TA0IV); /* TimerAx Interrupt Vector Register */ +sfr_b(TA0IV_L); +sfr_b(TA0IV_H); + +/* TA0 Register Offsets */ +#define OFS_TA0CTL (0x0000) +#define OFS_TA0CCTL0 (0x0002) +#define OFS_TA0CCTL1 (0x0004) +#define OFS_TA0CCTL2 (0x0006) +#define OFS_TA0R (0x0010) +#define OFS_TA0CCR0 (0x0012) +#define OFS_TA0CCR1 (0x0014) +#define OFS_TA0CCR2 (0x0016) +#define OFS_TA0EX0 (0x0020) +#define OFS_TA0IV (0x002E) + +/* TA0 Control Bits */ + +/* TA0CTL Control Bits */ +#define TAIFG (0x0001) /* TimerA interrupt flag */ +#define TAIFG_0 (0x0000) /* No interrupt pending */ +#define TAIFG_1 (0x0001) /* Interrupt pending */ +#define TAIE (0x0002) /* TimerA interrupt enable */ +#define TAIE_0 (0x0000) /* Interrupt disabled */ +#define TAIE_1 (0x0002) /* Interrupt enabled */ +#define TACLR (0x0004) /* TimerA clear */ +#define MC (0x0030) /* Mode control */ +#define MC0 (0x0010) /* Mode control */ +#define MC1 (0x0020) /* Mode control */ +#define MC_0 (0x0000) /* Stop mode: Timer is halted */ +#define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */ +#define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */ +#define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ +#define MC__STOP (0x0000) /* Stop mode: Timer is halted */ +#define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */ +#define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */ +#define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ +#define ID (0x00c0) /* Input divider */ +#define ID0 (0x0040) /* Input divider */ +#define ID1 (0x0080) /* Input divider */ +#define ID_0 (0x0000) /* /1 */ +#define ID_1 (0x0040) /* /2 */ +#define ID_2 (0x0080) /* /4 */ +#define ID_3 (0x00c0) /* /8 */ +#define ID__1 (0x0000) /* /1 */ +#define ID__2 (0x0040) /* /2 */ +#define ID__4 (0x0080) /* /4 */ +#define ID__8 (0x00c0) /* /8 */ +#define TASSEL (0x0300) /* TimerA clock source select */ +#define TASSEL0 (0x0100) /* TimerA clock source select */ +#define TASSEL1 (0x0200) /* TimerA clock source select */ +#define TASSEL_0 (0x0000) /* TAxCLK */ +#define TASSEL_1 (0x0100) /* ACLK */ +#define TASSEL_2 (0x0200) /* SMCLK */ +#define TASSEL_3 (0x0300) /* INCLK */ +#define TASSEL__TACLK (0x0000) /* TAxCLK */ +#define TASSEL__ACLK (0x0100) /* ACLK */ +#define TASSEL__SMCLK (0x0200) /* SMCLK */ +#define TASSEL__INCLK (0x0300) /* INCLK */ + +/* TA0CCTL Control Bits */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ +#define CCIFG_0 (0x0000) /* No interrupt pending */ +#define CCIFG_1 (0x0001) /* Interrupt pending */ +#define COV (0x0002) /* Capture overflow */ +#define COV_0 (0x0000) /* No capture overflow occurred */ +#define COV_1 (0x0002) /* Capture overflow occurred */ +#define OUT (0x0004) /* Output */ +#define OUT_0 (0x0000) /* Output low */ +#define OUT_1 (0x0004) /* Output high */ +#define OUT__LOW (0x0000) /* Output low */ +#define OUT__HIGH (0x0004) /* Output high */ +#define CCI (0x0008) /* Capture/compare input */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCIE_0 (0x0000) /* Interrupt disabled */ +#define CCIE_1 (0x0010) /* Interrupt enabled */ +#define OUTMOD (0x00e0) /* Output mode */ +#define OUTMOD0 (0x0020) /* Output mode */ +#define OUTMOD1 (0x0040) /* Output mode */ +#define OUTMOD2 (0x0080) /* Output mode */ +#define OUTMOD_0 (0x0000) /* OUT bit value */ +#define OUTMOD_1 (0x0020) /* Set */ +#define OUTMOD_2 (0x0040) /* Toggle/reset */ +#define OUTMOD_3 (0x0060) /* Set/reset */ +#define OUTMOD_4 (0x0080) /* Toggle */ +#define OUTMOD_5 (0x00a0) /* Reset */ +#define OUTMOD_6 (0x00c0) /* Toggle/set */ +#define OUTMOD_7 (0x00e0) /* Reset/set */ +#define CAP (0x0100) /* Capture mode */ +#define CAP_0 (0x0000) /* Compare mode */ +#define CAP_1 (0x0100) /* Capture mode */ +#define CAP__COMPARE (0x0000) /* Compare mode */ +#define CAP__CAPTURE (0x0100) /* Capture mode */ +#define SCCI (0x0400) /* Synchronized capture/compare input */ +#define SCS (0x0800) /* Synchronize capture source */ +#define SCS_0 (0x0000) /* Asynchronous capture */ +#define SCS_1 (0x0800) /* Synchronous capture */ +#define SCS__ASYNC (0x0000) /* Asynchronous capture */ +#define SCS__SYNC (0x0800) /* Synchronous capture */ +#define CCIS (0x3000) /* Capture/compare input select */ +#define CCIS0 (0x1000) /* Capture/compare input select */ +#define CCIS1 (0x2000) /* Capture/compare input select */ +#define CCIS_0 (0x0000) /* CCIxA */ +#define CCIS_1 (0x1000) /* CCIxB */ +#define CCIS_2 (0x2000) /* GND */ +#define CCIS_3 (0x3000) /* VCC */ +#define CCIS__CCIA (0x0000) /* CCIxA */ +#define CCIS__CCIB (0x1000) /* CCIxB */ +#define CCIS__GND (0x2000) /* GND */ +#define CCIS__VCC (0x3000) /* VCC */ +#define CM (0xc000) /* Capture mode */ +#define CM0 (0x4000) /* Capture mode */ +#define CM1 (0x8000) /* Capture mode */ +#define CM_0 (0x0000) /* No capture */ +#define CM_1 (0x4000) /* Capture on rising edge */ +#define CM_2 (0x8000) /* Capture on falling edge */ +#define CM_3 (0xc000) /* Capture on both rising and falling edges */ +#define CM__NONE (0x0000) /* No capture */ +#define CM__RISING (0x4000) /* Capture on rising edge */ +#define CM__FALLING (0x8000) /* Capture on falling edge */ +#define CM__BOTH (0xc000) /* Capture on both rising and falling edges */ + +/* TA0EX0 Control Bits */ +#define TAIDEX (0x0007) /* Input divider expansion */ +#define TAIDEX0 (0x0001) /* Input divider expansion */ +#define TAIDEX1 (0x0002) /* Input divider expansion */ +#define TAIDEX2 (0x0004) /* Input divider expansion */ +#define TAIDEX_0 (0x0000) /* Divide by 1 */ +#define TAIDEX_1 (0x0001) /* Divide by 2 */ +#define TAIDEX_2 (0x0002) /* Divide by 3 */ +#define TAIDEX_3 (0x0003) /* Divide by 4 */ +#define TAIDEX_4 (0x0004) /* Divide by 5 */ +#define TAIDEX_5 (0x0005) /* Divide by 6 */ +#define TAIDEX_6 (0x0006) /* Divide by 7 */ +#define TAIDEX_7 (0x0007) /* Divide by 8 */ +#define TAIDEX__1 (0x0000) /* Divide by 1 */ +#define TAIDEX__2 (0x0001) /* Divide by 2 */ +#define TAIDEX__3 (0x0002) /* Divide by 3 */ +#define TAIDEX__4 (0x0003) /* Divide by 4 */ +#define TAIDEX__5 (0x0004) /* Divide by 5 */ +#define TAIDEX__6 (0x0005) /* Divide by 6 */ +#define TAIDEX__7 (0x0006) /* Divide by 7 */ +#define TAIDEX__8 (0x0007) /* Divide by 8 */ + +/* TA0IV Control Bits */ +#define TAIV (0xffff) /* TimerA interrupt vector value */ +#define TAIV0 (0x0001) /* TimerA interrupt vector value */ +#define TAIV1 (0x0002) /* TimerA interrupt vector value */ +#define TAIV2 (0x0004) /* TimerA interrupt vector value */ +#define TAIV3 (0x0008) /* TimerA interrupt vector value */ +#define TAIV4 (0x0010) /* TimerA interrupt vector value */ +#define TAIV5 (0x0020) /* TimerA interrupt vector value */ +#define TAIV6 (0x0040) /* TimerA interrupt vector value */ +#define TAIV7 (0x0080) /* TimerA interrupt vector value */ +#define TAIV8 (0x0100) /* TimerA interrupt vector value */ +#define TAIV9 (0x0200) /* TimerA interrupt vector value */ +#define TAIV10 (0x0400) /* TimerA interrupt vector value */ +#define TAIV11 (0x0800) /* TimerA interrupt vector value */ +#define TAIV12 (0x1000) /* TimerA interrupt vector value */ +#define TAIV13 (0x2000) /* TimerA interrupt vector value */ +#define TAIV14 (0x4000) /* TimerA interrupt vector value */ +#define TAIV15 (0x8000) /* TimerA interrupt vector value */ +#define TAIV_0 (0x0000) /* No interrupt pending */ +#define TAIV_2 (0x0002) /* Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 + CCIFG; Interrupt Priority: Highest */ +#define TAIV_4 (0x0004) /* Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 + CCIFG */ +#define TAIV_6 (0x0006) /* Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 + CCIFG */ +#define TAIV_8 (0x0008) /* Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 + CCIFG */ +#define TAIV_10 (0x000a) /* Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 + CCIFG */ +#define TAIV_12 (0x000c) /* Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 + CCIFG */ +#define TAIV_14 (0x000e) /* Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL + TAIFG; Interrupt Priority: Lowest */ +#define TAIV__NONE (0x0000) /* No interrupt pending */ +#define TAIV__TACCR1 (0x0002) /* Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 + CCIFG; Interrupt Priority: Highest */ +#define TAIV__TACCR2 (0x0004) /* Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 + CCIFG */ +#define TAIV__TACCR3 (0x0006) /* Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 + CCIFG */ +#define TAIV__TACCR4 (0x0008) /* Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 + CCIFG */ +#define TAIV__TACCR5 (0x000a) /* Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 + CCIFG */ +#define TAIV__TACCR6 (0x000c) /* Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 + CCIFG */ +#define TAIV__TAIFG (0x000e) /* Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL + TAIFG; Interrupt Priority: Lowest */ + + +/***************************************************************************** + TA1 Registers +*****************************************************************************/ + +#define __MSP430_HAS_TA1__ 3 /* Definition to show that module is available */ +#ifndef __MSP430_HAS_TAx__ +#define __MSP430_HAS_TAx__ +#endif +#define __MSP430_BASEADDRESS_TA1__ 0x03C0 +#define TA1_BASE __MSP430_BASEADDRESS_TA1__ + +sfr_w(TA1CTL); /* TimerAx Control Register */ +sfr_b(TA1CTL_L); +sfr_b(TA1CTL_H); +sfr_w(TA1CCTL0); /* Timer_A Capture/Compare Control Register */ +sfr_b(TA1CCTL0_L); +sfr_b(TA1CCTL0_H); +sfr_w(TA1CCTL1); /* Timer_A Capture/Compare Control Register */ +sfr_b(TA1CCTL1_L); +sfr_b(TA1CCTL1_H); +sfr_w(TA1CCTL2); /* Timer_A Capture/Compare Control Register */ +sfr_b(TA1CCTL2_L); +sfr_b(TA1CCTL2_H); +sfr_w(TA1R); /* TimerA register */ +sfr_b(TA1R_L); +sfr_b(TA1R_H); +sfr_w(TA1CCR0); /* Timer_A Capture/Compare Register */ +sfr_b(TA1CCR0_L); +sfr_b(TA1CCR0_H); +sfr_w(TA1CCR1); /* Timer_A Capture/Compare Register */ +sfr_b(TA1CCR1_L); +sfr_b(TA1CCR1_H); +sfr_w(TA1CCR2); /* Timer_A Capture/Compare Register */ +sfr_b(TA1CCR2_L); +sfr_b(TA1CCR2_H); +sfr_w(TA1EX0); /* TimerAx Expansion 0 Register */ +sfr_b(TA1EX0_L); +sfr_b(TA1EX0_H); +sfr_w(TA1IV); /* TimerAx Interrupt Vector Register */ +sfr_b(TA1IV_L); +sfr_b(TA1IV_H); + +/* TA1 Register Offsets */ +#define OFS_TA1CTL (0x0000) +#define OFS_TA1CCTL0 (0x0002) +#define OFS_TA1CCTL1 (0x0004) +#define OFS_TA1CCTL2 (0x0006) +#define OFS_TA1R (0x0010) +#define OFS_TA1CCR0 (0x0012) +#define OFS_TA1CCR1 (0x0014) +#define OFS_TA1CCR2 (0x0016) +#define OFS_TA1EX0 (0x0020) +#define OFS_TA1IV (0x002E) + +/* No control bits available or already defined for another module */ + +/***************************************************************************** + TA2 Registers +*****************************************************************************/ + +#define __MSP430_HAS_TA2__ 3 /* Definition to show that module is available */ +#ifndef __MSP430_HAS_TAx__ +#define __MSP430_HAS_TAx__ +#endif +#define __MSP430_BASEADDRESS_TA2__ 0x0400 +#define TA2_BASE __MSP430_BASEADDRESS_TA2__ + +sfr_w(TA2CTL); /* TimerAx Control Register */ +sfr_b(TA2CTL_L); +sfr_b(TA2CTL_H); +sfr_w(TA2CCTL0); /* Timer_A Capture/Compare Control Register */ +sfr_b(TA2CCTL0_L); +sfr_b(TA2CCTL0_H); +sfr_w(TA2CCTL1); /* Timer_A Capture/Compare Control Register */ +sfr_b(TA2CCTL1_L); +sfr_b(TA2CCTL1_H); +sfr_w(TA2CCTL2); /* Timer_A Capture/Compare Control Register */ +sfr_b(TA2CCTL2_L); +sfr_b(TA2CCTL2_H); +sfr_w(TA2R); /* TimerA register */ +sfr_b(TA2R_L); +sfr_b(TA2R_H); +sfr_w(TA2CCR0); /* Timer_A Capture/Compare Register */ +sfr_b(TA2CCR0_L); +sfr_b(TA2CCR0_H); +sfr_w(TA2CCR1); /* Timer_A Capture/Compare Register */ +sfr_b(TA2CCR1_L); +sfr_b(TA2CCR1_H); +sfr_w(TA2CCR2); /* Timer_A Capture/Compare Register */ +sfr_b(TA2CCR2_L); +sfr_b(TA2CCR2_H); +sfr_w(TA2EX0); /* TimerAx Expansion 0 Register */ +sfr_b(TA2EX0_L); +sfr_b(TA2EX0_H); +sfr_w(TA2IV); /* TimerAx Interrupt Vector Register */ +sfr_b(TA2IV_L); +sfr_b(TA2IV_H); + +/* TA2 Register Offsets */ +#define OFS_TA2CTL (0x0000) +#define OFS_TA2CCTL0 (0x0002) +#define OFS_TA2CCTL1 (0x0004) +#define OFS_TA2CCTL2 (0x0006) +#define OFS_TA2R (0x0010) +#define OFS_TA2CCR0 (0x0012) +#define OFS_TA2CCR1 (0x0014) +#define OFS_TA2CCR2 (0x0016) +#define OFS_TA2EX0 (0x0020) +#define OFS_TA2IV (0x002E) + +/* No control bits available or already defined for another module */ + +/***************************************************************************** + TA3 Registers +*****************************************************************************/ + +#define __MSP430_HAS_TA3__ 3 /* Definition to show that module is available */ +#ifndef __MSP430_HAS_TAx__ +#define __MSP430_HAS_TAx__ +#endif +#define __MSP430_BASEADDRESS_TA3__ 0x0440 +#define TA3_BASE __MSP430_BASEADDRESS_TA3__ + +sfr_w(TA3CTL); /* TimerAx Control Register */ +sfr_b(TA3CTL_L); +sfr_b(TA3CTL_H); +sfr_w(TA3CCTL0); /* Timer_A Capture/Compare Control Register */ +sfr_b(TA3CCTL0_L); +sfr_b(TA3CCTL0_H); +sfr_w(TA3CCTL1); /* Timer_A Capture/Compare Control Register */ +sfr_b(TA3CCTL1_L); +sfr_b(TA3CCTL1_H); +sfr_w(TA3CCTL2); /* Timer_A Capture/Compare Control Register */ +sfr_b(TA3CCTL2_L); +sfr_b(TA3CCTL2_H); +sfr_w(TA3R); /* TimerA register */ +sfr_b(TA3R_L); +sfr_b(TA3R_H); +sfr_w(TA3CCR0); /* Timer_A Capture/Compare Register */ +sfr_b(TA3CCR0_L); +sfr_b(TA3CCR0_H); +sfr_w(TA3CCR1); /* Timer_A Capture/Compare Register */ +sfr_b(TA3CCR1_L); +sfr_b(TA3CCR1_H); +sfr_w(TA3CCR2); /* Timer_A Capture/Compare Register */ +sfr_b(TA3CCR2_L); +sfr_b(TA3CCR2_H); +sfr_w(TA3EX0); /* TimerAx Expansion 0 Register */ +sfr_b(TA3EX0_L); +sfr_b(TA3EX0_H); +sfr_w(TA3IV); /* TimerAx Interrupt Vector Register */ +sfr_b(TA3IV_L); +sfr_b(TA3IV_H); + +/* TA3 Register Offsets */ +#define OFS_TA3CTL (0x0000) +#define OFS_TA3CCTL0 (0x0002) +#define OFS_TA3CCTL1 (0x0004) +#define OFS_TA3CCTL2 (0x0006) +#define OFS_TA3R (0x0010) +#define OFS_TA3CCR0 (0x0012) +#define OFS_TA3CCR1 (0x0014) +#define OFS_TA3CCR2 (0x0016) +#define OFS_TA3EX0 (0x0020) +#define OFS_TA3IV (0x002E) + +/* No control bits available or already defined for another module */ + +/***************************************************************************** + TB0 Registers +*****************************************************************************/ + +#define __MSP430_HAS_TB0__ 7 /* Definition to show that module is available */ +#ifndef __MSP430_HAS_TBx__ +#define __MSP430_HAS_TBx__ +#endif +#define __MSP430_BASEADDRESS_TB0__ 0x0480 +#define TB0_BASE __MSP430_BASEADDRESS_TB0__ + +sfr_w(TB0CTL); /* Timer_B Control Register */ +sfr_b(TB0CTL_L); +sfr_b(TB0CTL_H); +sfr_w(TB0CCTL0); /* Timer_B Capture/Compare Control Register */ +sfr_b(TB0CCTL0_L); +sfr_b(TB0CCTL0_H); +sfr_w(TB0CCTL1); /* Timer_B Capture/Compare Control Register */ +sfr_b(TB0CCTL1_L); +sfr_b(TB0CCTL1_H); +sfr_w(TB0CCTL2); /* Timer_B Capture/Compare Control Register */ +sfr_b(TB0CCTL2_L); +sfr_b(TB0CCTL2_H); +sfr_w(TB0CCTL3); /* Timer_B Capture/Compare Control Register */ +sfr_b(TB0CCTL3_L); +sfr_b(TB0CCTL3_H); +sfr_w(TB0CCTL4); /* Timer_B Capture/Compare Control Register */ +sfr_b(TB0CCTL4_L); +sfr_b(TB0CCTL4_H); +sfr_w(TB0CCTL5); /* Timer_B Capture/Compare Control Register */ +sfr_b(TB0CCTL5_L); +sfr_b(TB0CCTL5_H); +sfr_w(TB0CCTL6); /* Timer_B Capture/Compare Control Register */ +sfr_b(TB0CCTL6_L); +sfr_b(TB0CCTL6_H); +sfr_w(TB0R); /* Timer_B count register */ +sfr_b(TB0R_L); +sfr_b(TB0R_H); +sfr_w(TB0CCR0); /* Timer_B Capture/Compare Register */ +sfr_b(TB0CCR0_L); +sfr_b(TB0CCR0_H); +sfr_w(TB0CCR1); /* Timer_B Capture/Compare Register */ +sfr_b(TB0CCR1_L); +sfr_b(TB0CCR1_H); +sfr_w(TB0CCR2); /* Timer_B Capture/Compare Register */ +sfr_b(TB0CCR2_L); +sfr_b(TB0CCR2_H); +sfr_w(TB0CCR3); /* Timer_B Capture/Compare Register */ +sfr_b(TB0CCR3_L); +sfr_b(TB0CCR3_H); +sfr_w(TB0CCR4); /* Timer_B Capture/Compare Register */ +sfr_b(TB0CCR4_L); +sfr_b(TB0CCR4_H); +sfr_w(TB0CCR5); /* Timer_B Capture/Compare Register */ +sfr_b(TB0CCR5_L); +sfr_b(TB0CCR5_H); +sfr_w(TB0CCR6); /* Timer_B Capture/Compare Register */ +sfr_b(TB0CCR6_L); +sfr_b(TB0CCR6_H); +sfr_w(TB0EX0); /* Timer_Bx Expansion Register 0 */ +sfr_b(TB0EX0_L); +sfr_b(TB0EX0_H); +sfr_w(TB0IV); /* Timer_Bx Interrupt Vector Register */ +sfr_b(TB0IV_L); +sfr_b(TB0IV_H); + +/* TB0 Register Offsets */ +#define OFS_TB0CTL (0x0000) +#define OFS_TB0CCTL0 (0x0002) +#define OFS_TB0CCTL1 (0x0004) +#define OFS_TB0CCTL2 (0x0006) +#define OFS_TB0CCTL3 (0x0008) +#define OFS_TB0CCTL4 (0x000A) +#define OFS_TB0CCTL5 (0x000C) +#define OFS_TB0CCTL6 (0x000E) +#define OFS_TB0R (0x0010) +#define OFS_TB0CCR0 (0x0012) +#define OFS_TB0CCR1 (0x0014) +#define OFS_TB0CCR2 (0x0016) +#define OFS_TB0CCR3 (0x0018) +#define OFS_TB0CCR4 (0x001A) +#define OFS_TB0CCR5 (0x001C) +#define OFS_TB0CCR6 (0x001E) +#define OFS_TB0EX0 (0x0020) +#define OFS_TB0IV (0x002E) + +/* TB0 Control Bits */ + +/* TB0CTL Control Bits */ +#define TBIFG (0x0001) /* TimerB interrupt flag */ +#define TBIFG_0 (0x0000) /* No interrupt pending */ +#define TBIFG_1 (0x0001) /* Interrupt pending */ +#define TBIE (0x0002) /* TimerB interrupt enable */ +#define TBIE_0 (0x0000) /* Interrupt disabled */ +#define TBIE_1 (0x0002) /* Interrupt enabled */ +#define TBCLR (0x0004) /* TimerB clear */ +#define TBSSEL (0x0300) /* TimerB clock source select */ +#define TBSSEL0 (0x0100) /* TimerB clock source select */ +#define TBSSEL1 (0x0200) /* TimerB clock source select */ +#define TBSSEL_0 (0x0000) /* TBxCLK */ +#define TBSSEL_1 (0x0100) /* ACLK */ +#define TBSSEL_2 (0x0200) /* SMCLK */ +#define TBSSEL_3 (0x0300) /* INCLK */ +#define TBSSEL__TBCLK (0x0000) /* TBxCLK */ +#define TBSSEL__ACLK (0x0100) /* ACLK */ +#define TBSSEL__SMCLK (0x0200) /* SMCLK */ +#define TBSSEL__INCLK (0x0300) /* INCLK */ +#define CNTL (0x1800) /* Counter length */ +#define CNTL0 (0x0800) /* Counter length */ +#define CNTL1 (0x1000) /* Counter length */ +#define CNTL_0 (0x0000) /* 16-bit, TBxR(max) = 0FFFFh */ +#define CNTL_1 (0x0800) /* 12-bit, TBxR(max) = 0FFFh */ +#define CNTL_2 (0x1000) /* 10-bit, TBxR(max) = 03FFh */ +#define CNTL_3 (0x1800) /* 8-bit, TBxR(max) = 0FFh */ +#define CNTL__16 (0x0000) /* 16-bit, TBxR(max) = 0FFFFh */ +#define CNTL__12 (0x0800) /* 12-bit, TBxR(max) = 0FFFh */ +#define CNTL__10 (0x1000) /* 10-bit, TBxR(max) = 03FFh */ +#define CNTL__8 (0x1800) /* 8-bit, TBxR(max) = 0FFh */ +#define TBCLGRP (0x6000) /* TBxCLn group */ +#define TBCLGRP0 (0x2000) /* TBxCLn group */ +#define TBCLGRP1 (0x4000) /* TBxCLn group */ +#define TBCLGRP_0 (0x0000) /* Each TBxCLn latch loads independently */ +#define TBCLGRP_1 (0x2000) /* TBxCL1+TBxCL2 (TBxCCR1 CLLD bits control the update); + TBxCL3+TBxCL4 (TBxCCR3 CLLD bits control the update); + TBxCL5+TBxCL6 (TBxCCR5 CLLD bits control the update); TBxCL0 + independent */ +#define TBCLGRP_2 (0x4000) /* TBxCL1+TBxCL2+TBxCL3 (TBxCCR1 CLLD bits control the update); + TBxCL4+TBxCL5+TBxCL6 (TBxCCR4 CLLD bits control the update); + TBxCL0 independent */ +#define TBCLGRP_3 (0x6000) /* TBxCL0+TBxCL1+TBxCL2+TBxCL3+TBxCL4+TBxCL5+TBxCL6 (TBxCCR1 CLLD + bits control the update) */ + +/* TB0CCTL Control Bits */ +#define CLLD (0x0600) /* Compare latch load */ +#define CLLD0 (0x0200) /* Compare latch load */ +#define CLLD1 (0x0400) /* Compare latch load */ +#define CLLD_0 (0x0000) /* TBxCLn loads on write to TBxCCRn */ +#define CLLD_1 (0x0200) /* TBxCLn loads when TBxR counts to 0 */ +#define CLLD_2 (0x0400) /* TBxCLn loads when TBxR counts to 0 (up or continuous mode). + TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down + mode). */ +#define CLLD_3 (0x0600) /* TBxCLn loads when TBxR counts to TBxCLn */ + +/* TB0EX0 Control Bits */ +#define TBIDEX (0x0007) /* Input divider expansion */ +#define TBIDEX0 (0x0001) /* Input divider expansion */ +#define TBIDEX1 (0x0002) /* Input divider expansion */ +#define TBIDEX2 (0x0004) /* Input divider expansion */ +#define TBIDEX_0 (0x0000) /* Divide by 1 */ +#define TBIDEX_1 (0x0001) /* Divide by 2 */ +#define TBIDEX_2 (0x0002) /* Divide by 3 */ +#define TBIDEX_3 (0x0003) /* Divide by 4 */ +#define TBIDEX_4 (0x0004) /* Divide by 5 */ +#define TBIDEX_5 (0x0005) /* Divide by 6 */ +#define TBIDEX_6 (0x0006) /* Divide by 7 */ +#define TBIDEX_7 (0x0007) /* Divide by 8 */ +#define TBIDEX__1 (0x0000) /* Divide by 1 */ +#define TBIDEX__2 (0x0001) /* Divide by 2 */ +#define TBIDEX__3 (0x0002) /* Divide by 3 */ +#define TBIDEX__4 (0x0003) /* Divide by 4 */ +#define TBIDEX__5 (0x0004) /* Divide by 5 */ +#define TBIDEX__6 (0x0005) /* Divide by 6 */ +#define TBIDEX__7 (0x0006) /* Divide by 7 */ +#define TBIDEX__8 (0x0007) /* Divide by 8 */ + +/* TB0IV Control Bits */ +#define TBIV (0xffff) /* Timer_B interrupt vector value */ +#define TBIV0 (0x0001) /* Timer_B interrupt vector value */ +#define TBIV1 (0x0002) /* Timer_B interrupt vector value */ +#define TBIV2 (0x0004) /* Timer_B interrupt vector value */ +#define TBIV3 (0x0008) /* Timer_B interrupt vector value */ +#define TBIV4 (0x0010) /* Timer_B interrupt vector value */ +#define TBIV5 (0x0020) /* Timer_B interrupt vector value */ +#define TBIV6 (0x0040) /* Timer_B interrupt vector value */ +#define TBIV7 (0x0080) /* Timer_B interrupt vector value */ +#define TBIV8 (0x0100) /* Timer_B interrupt vector value */ +#define TBIV9 (0x0200) /* Timer_B interrupt vector value */ +#define TBIV10 (0x0400) /* Timer_B interrupt vector value */ +#define TBIV11 (0x0800) /* Timer_B interrupt vector value */ +#define TBIV12 (0x1000) /* Timer_B interrupt vector value */ +#define TBIV13 (0x2000) /* Timer_B interrupt vector value */ +#define TBIV14 (0x4000) /* Timer_B interrupt vector value */ +#define TBIV15 (0x8000) /* Timer_B interrupt vector value */ +#define TBIV_0 (0x0000) /* No interrupt pending */ +#define TBIV_2 (0x0002) /* Interrupt Source: Capture/compare 1; Interrupt Flag: TBxCCR1 + CCIFG; Interrupt Priority: Highest */ +#define TBIV_4 (0x0004) /* Interrupt Source: Capture/compare 2; Interrupt Flag: TBxCCR2 + CCIFG */ +#define TBIV_6 (0x0006) /* Interrupt Source: Capture/compare 3; Interrupt Flag: TBxCCR3 + CCIFG */ +#define TBIV_8 (0x0008) /* Interrupt Source: Capture/compare 4; Interrupt Flag: TBxCCR4 + CCIFG */ +#define TBIV_10 (0x000a) /* Interrupt Source: Capture/compare 5; Interrupt Flag: TBxCCR5 + CCIFG */ +#define TBIV_12 (0x000c) /* Interrupt Source: Capture/compare 6; Interrupt Flag: TBxCCR6 + CCIFG */ +#define TBIV_14 (0x000e) /* Interrupt Source: Timer overflow; Interrupt Flag: TBxCTL + TBIFG; Interrupt Priority: Lowest */ +#define TBIV__NONE (0x0000) /* No interrupt pending */ +#define TBIV__TBCCR1 (0x0002) /* Interrupt Source: Capture/compare 1; Interrupt Flag: TBxCCR1 + CCIFG; Interrupt Priority: Highest */ +#define TBIV__TBCCR2 (0x0004) /* Interrupt Source: Capture/compare 2; Interrupt Flag: TBxCCR2 + CCIFG */ +#define TBIV__TBCCR3 (0x0006) /* Interrupt Source: Capture/compare 3; Interrupt Flag: TBxCCR3 + CCIFG */ +#define TBIV__TBCCR4 (0x0008) /* Interrupt Source: Capture/compare 4; Interrupt Flag: TBxCCR4 + CCIFG */ +#define TBIV__TBCCR5 (0x000a) /* Interrupt Source: Capture/compare 5; Interrupt Flag: TBxCCR5 + CCIFG */ +#define TBIV__TBCCR6 (0x000c) /* Interrupt Source: Capture/compare 6; Interrupt Flag: TBxCCR6 + CCIFG */ +#define TBIV__TBIFG (0x000e) /* Interrupt Source: Timer overflow; Interrupt Flag: TBxCTL + TBIFG; Interrupt Priority: Lowest */ + + +/***************************************************************************** + WDT_A Registers +*****************************************************************************/ + +#define __MSP430_HAS_WDT_A__ /* Definition to show that module is available */ +#define __MSP430_BASEADDRESS_WDT_A__ 0x01CC +#define WDT_A_BASE __MSP430_BASEADDRESS_WDT_A__ + +sfr_w(WDTCTL); /* Watchdog Timer Control Register */ +sfr_b(WDTCTL_L); +sfr_b(WDTCTL_H); + +/* WDT_A Register Offsets */ +#define OFS_WDTCTL (0x0000) + +/* WDT_A Control Bits */ + +/* WDTCTL Control Bits */ +#define WDTIS (0x0007) /* Watchdog timer interval select */ +#define WDTIS0 (0x0001) /* Watchdog timer interval select */ +#define WDTIS1 (0x0002) /* Watchdog timer interval select */ +#define WDTIS2 (0x0004) /* Watchdog timer interval select */ +#define WDTIS_0 (0x0000) /* Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ +#define WDTIS_1 (0x0001) /* Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ +#define WDTIS_2 (0x0002) /* Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ +#define WDTIS_3 (0x0003) /* Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ +#define WDTIS_4 (0x0004) /* Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ +#define WDTIS_5 (0x0005) /* Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ +#define WDTIS_6 (0x0006) /* Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ +#define WDTIS_7 (0x0007) /* Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ +#define WDTIS__2G (0x0000) /* Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ +#define WDTIS__128M (0x0001) /* Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ +#define WDTIS__8192K (0x0002) /* Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ +#define WDTIS__512K (0x0003) /* Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ +#define WDTIS__32K (0x0004) /* Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ +#define WDTIS__8192 (0x0005) /* Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ +#define WDTIS__512 (0x0006) /* Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ +#define WDTIS__64 (0x0007) /* Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ +#define WDTCNTCL (0x0008) /* Watchdog timer counter clear */ +#define WDTCNTCL_0 (0x0000) /* No action */ +#define WDTCNTCL_1 (0x0008) /* WDTCNT = 0000h */ +#define WDTTMSEL (0x0010) /* Watchdog timer mode select */ +#define WDTTMSEL_0 (0x0000) /* Watchdog mode */ +#define WDTTMSEL_1 (0x0010) /* Interval timer mode */ +#define WDTSSEL (0x0060) /* Watchdog timer clock source select */ +#define WDTSSEL0 (0x0020) /* Watchdog timer clock source select */ +#define WDTSSEL1 (0x0040) /* Watchdog timer clock source select */ +#define WDTSSEL_0 (0x0000) /* SMCLK */ +#define WDTSSEL_1 (0x0020) /* ACLK */ +#define WDTSSEL_2 (0x0040) /* VLOCLK */ +#define WDTSSEL_3 (0x0060) /* BCLK */ +#define WDTSSEL__SMCLK (0x0000) /* SMCLK */ +#define WDTSSEL__ACLK (0x0020) /* ACLK */ +#define WDTSSEL__VLOCLK (0x0040) /* VLOCLK */ +#define WDTSSEL__BCLK (0x0060) /* BCLK */ +#define WDTHOLD (0x0080) /* Watchdog timer hold */ +#define WDTHOLD_0 (0x0000) /* Watchdog timer is not stopped */ +#define WDTHOLD_1 (0x0080) /* Watchdog timer is stopped */ +#define WDTHOLD__UNHOLD (0x0000) /* Watchdog timer is not stopped */ +#define WDTHOLD__HOLD (0x0080) /* Watchdog timer is stopped */ +#define WDTPW (0x5a00) /* Watchdog timer password */ +#define WDTPW0 (0x0100) /* Watchdog timer password */ +#define WDTPW1 (0x0200) /* Watchdog timer password */ +#define WDTPW2 (0x0400) /* Watchdog timer password */ +#define WDTPW3 (0x0800) /* Watchdog timer password */ +#define WDTPW4 (0x1000) /* Watchdog timer password */ +#define WDTPW5 (0x2000) /* Watchdog timer password */ +#define WDTPW6 (0x4000) /* Watchdog timer password */ +#define WDTPW7 (0x8000) /* Watchdog timer password */ + + +/***************************************************************************** + eCOMP0 Registers +*****************************************************************************/ + +#define __MSP430_HAS_ECOMP0__ /* Definition to show that module is available */ +#ifndef __MSP430_HAS_ECOMPx__ +#define __MSP430_HAS_ECOMPx__ +#endif +#define __MSP430_BASEADDRESS_ECOMP0__ 0x08E0 +#define ECOMP0_BASE __MSP430_BASEADDRESS_ECOMP0__ + +sfr_w(CP0CTL0); /* Comparator Control Register 0 */ +sfr_b(CP0CTL0_L); +sfr_b(CP0CTL0_H); +sfr_w(CP0CTL1); /* Comparator Control Register 1 */ +sfr_b(CP0CTL1_L); +sfr_b(CP0CTL1_H); +sfr_w(CP0INT); /* Comparator Interrupt Control Register */ +sfr_b(CP0INT_L); +sfr_b(CP0INT_H); +sfr_w(CP0IV); /* Comparator Interrupt Vector Word Register */ +sfr_b(CP0IV_L); +sfr_b(CP0IV_H); +sfr_w(CP0DACCTL); /* 6-bit Comparator built-in DAC Control Register */ +sfr_b(CP0DACCTL_L); +sfr_b(CP0DACCTL_H); +sfr_w(CP0DACDATA); /* 6-bit Comparator built-in DAC Data Register */ +sfr_b(CP0DACDATA_L); +sfr_b(CP0DACDATA_H); + +/* eCOMP0 Register Offsets */ +#define OFS_CP0CTL0 (0x0000) +#define OFS_CP0CTL1 (0x0002) +#define OFS_CP0INT (0x0006) +#define OFS_CP0IV (0x0008) +#define OFS_CP0DACCTL (0x0010) +#define OFS_CP0DACDATA (0x0012) + +/* eCOMP0 Control Bits */ + +/* CP0CTL0 Control Bits */ +#define CPPEN (0x0010) /* Channel input enable for the V+ terminal */ +#define CPPEN_0 (0x0000) /* Selected analog input channel for V+ terminal is disabled. */ +#define CPPEN_1 (0x0010) /* Selected analog input channel for V+ terminal is enabled. */ +#define CPNSEL (0x0700) /* Channel input selected for the - terminal */ +#define CPNSEL0 (0x0100) /* Channel input selected for the - terminal */ +#define CPNSEL1 (0x0200) /* Channel input selected for the - terminal */ +#define CPNSEL2 (0x0400) /* Channel input selected for the - terminal */ +#define CPNSEL_0 (0x0000) /* select external input source */ +#define CPNSEL_1 (0x0100) /* select external input source */ +#define CPNSEL_2 (0x0200) /* select external input source */ +#define CPNSEL_3 (0x0300) /* select external input source */ +#define CPNSEL_4 (0x0400) /* device specific, please refer to device data sheet for details */ +#define CPNSEL_5 (0x0500) /* device specific, please refer to device data sheet for details */ +#define CPNSEL_6 (0x0600) /* 6-bit DAC */ +#define CPNSEL_7 (0x0700) /* Reserved */ +#define CPNEN (0x1000) /* Channel input enable for the - terminal */ +#define CPNEN_0 (0x0000) /* Selected analog input channel for V- terminal is disabled. */ +#define CPNEN_1 (0x1000) /* Selected analog input channel for V- terminal is enabled. */ +#define CPPSEL (0x0007) /* Channel input selected for the V+ terminal */ +#define CPPSEL0 (0x0001) /* Channel input selected for the V+ terminal */ +#define CPPSEL1 (0x0002) /* Channel input selected for the V+ terminal */ +#define CPPSEL2 (0x0004) /* Channel input selected for the V+ terminal */ +#define CPPSEL_0 (0x0000) /* select external input source */ +#define CPPSEL_1 (0x0001) /* select external input source */ +#define CPPSEL_2 (0x0002) /* select external input source */ +#define CPPSEL_3 (0x0003) /* select external input source */ +#define CPPSEL_4 (0x0004) /* device specific, please refer to device data sheet for details */ +#define CPPSEL_5 (0x0005) /* device specific, please refer to device data sheet for details */ +#define CPPSEL_6 (0x0006) /* 6-bit DAC */ +#define CPPSEL_7 (0x0007) /* Reserved */ + +/* CP0CTL1 Control Bits */ +#define CPOUT (0x0001) /* Comparator output value */ +#define CPINV (0x0002) /* Comparator output polarity */ +#define CPINV_0 (0x0000) /* Comparator output is non-inverted */ +#define CPINV_1 (0x0002) /* Comparator output is inverted */ +#define CPIES (0x0010) /* Interrupt edge select for CEIIFG and CEIFG */ +#define CPIES_0 (0x0000) /* Rising edge for CPIFG, falling edge for CPIIFG */ +#define CPIES_1 (0x0010) /* Falling edge for CPIFG, rising edge for CPIIFG */ +#define CPFLT (0x0020) /* */ +#define CPFLT_0 (0x0000) /* Comparator output is not filtered */ +#define CPFLT_1 (0x0020) /* Comparator output is filtered */ +#define CPFLTDLY (0x00c0) /* */ +#define CPFLTDLY0 (0x0040) /* */ +#define CPFLTDLY1 (0x0080) /* */ +#define CPFLTDLY_0 (0x0000) /* Typical filter delay of 450ns */ +#define CPFLTDLY_1 (0x0040) /* Typical filter delay of 900ns */ +#define CPFLTDLY_2 (0x0080) /* Typical filter delay of 1800ns */ +#define CPFLTDLY_3 (0x00c0) /* Typical filter delay of 3600ns */ +#define CPMSEL (0x0100) /* */ +#define CPMSEL_0 (0x0000) /* High-power & High speed mode (500nA) */ +#define CPMSEL_1 (0x0100) /* Low-power & Low speed mode (10nA) */ +#define CPEN (0x0200) /* */ +#define CPEN_0 (0x0000) /* Comparator is disabled */ +#define CPEN_1 (0x0200) /* Comparator is enabled */ +#define CPHSEL (0x0c00) /* */ +#define CPHSEL0 (0x0400) /* */ +#define CPHSEL1 (0x0800) /* */ +#define CPHSEL_0 (0x0000) /* disable */ +#define CPHSEL_1 (0x0400) /* 10mV */ +#define CPHSEL_2 (0x0800) /* 20mV */ +#define CPHSEL_3 (0x0c00) /* 30mV */ +#define CPIE (0x4000) /* */ +#define CPIE_0 (0x0000) /* Interrupt output is disabled */ +#define CPIE_1 (0x4000) /* Interrupt output is enabled */ +#define CPIIE (0x8000) /* */ +#define CPIIE_0 (0x0000) /* Interrupt inverted output is disabled */ +#define CPIIE_1 (0x8000) /* Interrupt inverted output is enabled */ + +/* CP0INT Control Bits */ +#define CPIFG (0x0001) /* Comparator output interrupt flag */ +#define CPIFG_0 (0x0000) /* No interrupt pending. */ +#define CPIFG_1 (0x0001) /* Output interrupt pending. */ +#define CPIIFG (0x0002) /* Comparator output inverted interrupt flag */ +#define CPIIFG_0 (0x0000) /* No interrupt pending. */ +#define CPIIFG_1 (0x0002) /* Output interrupt pending. */ + +/* CP0IV Control Bits */ +#define CPIV (0xffff) /* Comparator interrupt vector word register */ +#define CPIV0 (0x0001) /* Comparator interrupt vector word register */ +#define CPIV1 (0x0002) /* Comparator interrupt vector word register */ +#define CPIV2 (0x0004) /* Comparator interrupt vector word register */ +#define CPIV3 (0x0008) /* Comparator interrupt vector word register */ +#define CPIV4 (0x0010) /* Comparator interrupt vector word register */ +#define CPIV5 (0x0020) /* Comparator interrupt vector word register */ +#define CPIV6 (0x0040) /* Comparator interrupt vector word register */ +#define CPIV7 (0x0080) /* Comparator interrupt vector word register */ +#define CPIV8 (0x0100) /* Comparator interrupt vector word register */ +#define CPIV9 (0x0200) /* Comparator interrupt vector word register */ +#define CPIV10 (0x0400) /* Comparator interrupt vector word register */ +#define CPIV11 (0x0800) /* Comparator interrupt vector word register */ +#define CPIV12 (0x1000) /* Comparator interrupt vector word register */ +#define CPIV13 (0x2000) /* Comparator interrupt vector word register */ +#define CPIV14 (0x4000) /* Comparator interrupt vector word register */ +#define CPIV15 (0x8000) /* Comparator interrupt vector word register */ +#define CPIV_0 (0x0000) /* No interrupt pending */ +#define CEIV_2 (0x0002) /* CPIFG */ +#define CPIV_4 (0x0004) /* CPIIFG */ +#define CPIV__NONE (0x0000) /* No interrupt pending */ +#define CPIV__CPIFG (0x0002) /* CPIFG */ +#define CPIV__CPIIFG (0x0004) /* CPIIFG */ + +/* CP0DACCTL Control Bits */ +#define CPDACSW (0x0001) /* */ +#define CPDACSW_0 (0x0000) /* CPDACBUF1 selected */ +#define CPDACSW_1 (0x0001) /* CPDACBUF2 selected */ +#define CPDACBUFS (0x0002) /* */ +#define CPDACBUFS_0 (0x0000) /* Comparator output is selected as the buffer control source */ +#define CPDACBUFS_1 (0x0002) /* CPDACSW bit is selected as the buffer control source */ +#define CPDACREFS (0x0004) /* */ +#define CPDACREFS_0 (0x0000) /* VDD selected */ +#define CPDACREFS_1 (0x0004) /* on-chip VREF selected */ +#define CPDACEN (0x0080) /* */ +#define CPDACEN_0 (0x0000) /* DAC output is disabled. */ +#define CPDACEN_1 (0x0080) /* DAC output is enabled. */ + +/* CP0DACDATA Control Bits */ +#define CPDACBUF1 (0x003f) /* */ +#define CPDACBUF10 (0x0001) /* */ +#define CPDACBUF11 (0x0002) /* */ +#define CPDACBUF12 (0x0004) /* */ +#define CPDACBUF13 (0x0008) /* */ +#define CPDACBUF14 (0x0010) /* */ +#define CPDACBUF15 (0x0020) /* */ +#define CPDACBUF1_0 (0x0000) /* 0v */ +#define CPDACBUF1_1 (0x0001) /* selected reference voltage * 1/64 */ +#define CPDACBUF1_2 (0x0002) /* selected reference voltage * 2/64 */ +#define CPDACBUF1_3 (0x0003) /* selected reference voltage * 3/64 */ +#define CPDACBUF1_4 (0x0004) /* selected reference voltage * 4/64 */ +#define CPDACBUF1_5 (0x0005) /* selected reference voltage * 5/64 */ +#define CPDACBUF1_6 (0x0006) /* selected reference voltage * 6/64 */ +#define CPDACBUF1_7 (0x0007) /* selected reference voltage * 7/64 */ +#define CPDACBUF1_8 (0x0008) /* selected reference voltage * 8/64 */ +#define CPDACBUF1_9 (0x0009) /* selected reference voltage *9/64 */ +#define CPDACBUF1_10 (0x000a) /* selected reference voltage * 10/64 */ +#define CPDACBUF1_11 (0x000b) /* selected reference voltage * 11/64 */ +#define CPDACBUF1_12 (0x000c) /* selected reference voltage * 12/64 */ +#define CPDACBUF1_13 (0x000d) /* selected reference voltage * 13/64 */ +#define CPDACBUF1_14 (0x000e) /* selected reference voltage * 14/64 */ +#define CPDACBUF1_15 (0x000f) /* selected reference voltage * 15/64 */ +#define CPDACBUF1_16 (0x0010) /* selected reference voltage * 16/64 */ +#define CPDACBUF1_17 (0x0011) /* selected reference voltage * 17/64 */ +#define CPDACBUF1_18 (0x0012) /* selected reference voltage * 18/64 */ +#define CPDACBUF1_19 (0x0013) /* selected reference voltage * 19/64 */ +#define CPDACBUF1_20 (0x0014) /* selected reference voltage * 20/64 */ +#define CPDACBUF1_21 (0x0015) /* selected reference voltage * 21/64 */ +#define CPDACBUF1_22 (0x0016) /* selected reference voltage * 22/64 */ +#define CPDACBUF1_23 (0x0017) /* selected reference voltage * 23/64 */ +#define CPDACBUF1_24 (0x0018) /* selected reference voltage * 24/64 */ +#define CPDACBUF1_25 (0x0019) /* selected reference voltage * 25/64 */ +#define CPDACBUF1_26 (0x001a) /* selected reference voltage * 26/64 */ +#define CPDACBUF1_27 (0x001b) /* selected reference voltage * 27/64 */ +#define CPDACBUF1_28 (0x001c) /* selected reference voltage * 28/64 */ +#define CPDACBUF1_29 (0x001d) /* selected reference voltage * 29/64 */ +#define CPDACBUF1_30 (0x001e) /* selected reference voltage * 30/64 */ +#define CPDACBUF1_31 (0x001f) /* selected reference voltage * 31/64 */ +#define CPDACBUF1_32 (0x0020) /* selected reference voltage * 32/64 */ +#define CPDACBUF1_33 (0x0021) /* selected reference voltage * 33/64 */ +#define CPDACBUF1_34 (0x0022) /* selected reference voltage * 34/64 */ +#define CPDACBUF1_35 (0x0023) /* selected reference voltage * 35/64 */ +#define CPDACBUF1_36 (0x0024) /* selected reference voltage * 36/64 */ +#define CPDACBUF1_37 (0x0025) /* selected reference voltage * 37/64 */ +#define CPDACBUF1_38 (0x0026) /* selected reference voltage * 38/64 */ +#define CPDACBUF1_39 (0x0027) /* selected reference voltage * 39/64 */ +#define CPDACBUF1_40 (0x0028) /* selected reference voltage * 40/64 */ +#define CPDACBUF1_41 (0x0029) /* selected reference voltage * 41/64 */ +#define CPDACBUF1_42 (0x002a) /* selected reference voltage * 42/64 */ +#define CPDACBUF1_43 (0x002b) /* selected reference voltage * 43/64 */ +#define CPDACBUF1_44 (0x002c) /* selected reference voltage * 44/64 */ +#define CPDACBUF1_45 (0x002d) /* selected reference voltage * 45/64 */ +#define CPDACBUF1_46 (0x002e) /* selected reference voltage * 46/64 */ +#define CPDACBUF1_47 (0x002f) /* selected reference voltage * 47/64 */ +#define CPDACBUF1_48 (0x0030) /* selected reference voltage * 48/64 */ +#define CPDACBUF1_49 (0x0031) /* selected reference voltage * 49/64 */ +#define CPDACBUF1_50 (0x0032) /* selected reference voltage * 50/64 */ +#define CPDACBUF1_51 (0x0033) /* selected reference voltage * 51/64 */ +#define CPDACBUF1_52 (0x0034) /* selected reference voltage * 52/64 */ +#define CPDACBUF1_53 (0x0035) /* selected reference voltage * 53/64 */ +#define CPDACBUF1_54 (0x0036) /* selected reference voltage * 54/64 */ +#define CPDACBUF1_55 (0x0037) /* selected reference voltage * 55/64 */ +#define CPDACBUF1_56 (0x0038) /* selected reference voltage * 56/64 */ +#define CPDACBUF1_57 (0x0039) /* selected reference voltage * 57/64 */ +#define CPDACBUF1_58 (0x003a) /* selected reference voltage * 58/64 */ +#define CPDACBUF1_59 (0x003b) /* selected reference voltage * 59/64 */ +#define CPDACBUF1_60 (0x003c) /* selected reference voltage * 60/64 */ +#define CPDACBUF1_61 (0x003d) /* selected reference voltage * 61/64 */ +#define CPDACBUF1_62 (0x003e) /* selected reference voltage * 62/64 */ +#define CPDACBUF1_63 (0x003f) /* selected reference voltage * 63/64 */ +#define CPDACBUF2 (0x3f00) /* */ +#define CPDACBUF20 (0x0100) /* */ +#define CPDACBUF21 (0x0200) /* */ +#define CPDACBUF22 (0x0400) /* */ +#define CPDACBUF23 (0x0800) /* */ +#define CPDACBUF24 (0x1000) /* */ +#define CPDACBUF25 (0x2000) /* */ +#define CPDACBUF2_0 (0x0000) /* 0v */ +#define CPDACBUF2_1 (0x0100) /* selected reference voltage * 1/64 */ +#define CPDACBUF2_2 (0x0200) /* selected reference voltage * 2/64 */ +#define CPDACBUF2_3 (0x0300) /* selected reference voltage * 3/64 */ +#define CPDACBUF2_4 (0x0400) /* selected reference voltage * 4/64 */ +#define CPDACBUF2_5 (0x0500) /* selected reference voltage * 5/64 */ +#define CPDACBUF2_6 (0x0600) /* selected reference voltage * 6/64 */ +#define CPDACBUF2_7 (0x0700) /* selected reference voltage * 7/64 */ +#define CPDACBUF2_8 (0x0800) /* selected reference voltage * 8/64 */ +#define CPDACBUF2_9 (0x0900) /* selected reference voltage * 9/64 */ +#define CPDACBUF2_10 (0x0a00) /* selected reference voltage * 10/64 */ +#define CPDACBUF2_11 (0x0b00) /* selected reference voltage * 11/64 */ +#define CPDACBUF2_12 (0x0c00) /* selected reference voltage * 12/64 */ +#define CPDACBUF2_13 (0x0d00) /* selected reference voltage * 13/64 */ +#define CPDACBUF2_14 (0x0e00) /* selected reference voltage * 14/64 */ +#define CPDACBUF2_15 (0x0f00) /* selected reference voltage * 15/64 */ +#define CPDACBUF2_16 (0x1000) /* selected reference voltage * 16/64 */ +#define CPDACBUF2_17 (0x1100) /* selected reference voltage * 17/64 */ +#define CPDACBUF2_18 (0x1200) /* selected reference voltage * 18/64 */ +#define CPDACBUF2_19 (0x1300) /* selected reference voltage * 19/64 */ +#define CPDACBUF2_20 (0x1400) /* selected reference voltage * 20/64 */ +#define CPDACBUF2_21 (0x1500) /* selected reference voltage * 21/64 */ +#define CPDACBUF2_22 (0x1600) /* selected reference voltage * 22/64 */ +#define CPDACBUF2_23 (0x1700) /* selected reference voltage * 23/64 */ +#define CPDACBUF2_24 (0x1800) /* selected reference voltage * 24/64 */ +#define CPDACBUF2_25 (0x1900) /* selected reference voltage * 25/64 */ +#define CPDACBUF2_26 (0x1a00) /* selected reference voltage * 26/64 */ +#define CPDACBUF2_27 (0x1b00) /* selected reference voltage * 27/64 */ +#define CPDACBUF2_28 (0x1c00) /* selected reference voltage * 28/64 */ +#define CPDACBUF2_29 (0x1d00) /* selected reference voltage * 29/64 */ +#define CPDACBUF2_30 (0x1e00) /* selected reference voltage * 30/64 */ +#define CPDACBUF2_31 (0x1f00) /* selected reference voltage * 31/64 */ +#define CPDACBUF2_32 (0x2000) /* selected reference voltage * 32/64 */ +#define CPDACBUF2_33 (0x2100) /* selected reference voltage * 33/64 */ +#define CPDACBUF2_34 (0x2200) /* selected reference voltage * 34/64 */ +#define CPDACBUF2_35 (0x2300) /* selected reference voltage * 35/64 */ +#define CPDACBUF2_36 (0x2400) /* selected reference voltage * 36/64 */ +#define CPDACBUF2_37 (0x2500) /* selected reference voltage * 37/64 */ +#define CPDACBUF2_38 (0x2600) /* selected reference voltage * 38/64 */ +#define CPDACBUF2_39 (0x2700) /* selected reference voltage * 39/64 */ +#define CPDACBUF2_40 (0x2800) /* selected reference voltage * 40/64 */ +#define CPDACBUF2_41 (0x2900) /* selected reference voltage * 41/64 */ +#define CPDACBUF2_42 (0x2a00) /* selected reference voltage * 42/64 */ +#define CPDACBUF2_43 (0x2b00) /* selected reference voltage * 43/64 */ +#define CPDACBUF2_44 (0x2c00) /* selected reference voltage * 44/64 */ +#define CPDACBUF2_45 (0x2d00) /* selected reference voltage * 45/64 */ +#define CPDACBUF2_46 (0x2e00) /* selected reference voltage * 46/64 */ +#define CPDACBUF2_47 (0x2f00) /* selected reference voltage * 47/64 */ +#define CPDACBUF2_48 (0x3000) /* selected reference voltage * 48/64 */ +#define CPDACBUF2_49 (0x3100) /* selected reference voltage * 49/64 */ +#define CPDACBUF2_50 (0x3200) /* selected reference voltage * 50/64 */ +#define CPDACBUF2_51 (0x3300) /* selected reference voltage * 51/64 */ +#define CPDACBUF2_52 (0x3400) /* selected reference voltage * 52/64 */ +#define CPDACBUF2_53 (0x3500) /* selected reference voltage * 53/64 */ +#define CPDACBUF2_54 (0x3600) /* selected reference voltage * 54/64 */ +#define CPDACBUF2_55 (0x3700) /* selected reference voltage * 55/64 */ +#define CPDACBUF2_56 (0x3800) /* selected reference voltage * 56/64 */ +#define CPDACBUF2_57 (0x3900) /* selected reference voltage * 57/64 */ +#define CPDACBUF2_58 (0x3a00) /* selected reference voltage * 58/64 */ +#define CPDACBUF2_59 (0x3b00) /* selected reference voltage * 59/64 */ +#define CPDACBUF2_60 (0x3c00) /* selected reference voltage * 60/64 */ +#define CPDACBUF2_61 (0x3d00) /* selected reference voltage * 61/64 */ +#define CPDACBUF2_62 (0x3e00) /* selected reference voltage * 62/64 */ +#define CPDACBUF2_63 (0x3f00) /* selected reference voltage * 63/64 */ + + +/***************************************************************************** + eUSCI_A0 Registers +*****************************************************************************/ + +#define __MSP430_HAS_EUSCI_A0__ /* Definition to show that module is available */ +#ifndef __MSP430_HAS_EUSCI_Ax__ +#define __MSP430_HAS_EUSCI_Ax__ +#endif +#define __MSP430_BASEADDRESS_EUSCI_A0__ 0x0500 +#define EUSCI_A0_BASE __MSP430_BASEADDRESS_EUSCI_A0__ + +sfr_w(UCA0CTLW0); /* eUSCI_Ax Control Word Register 0 */ +sfr_b(UCA0CTLW0_L); +sfr_b(UCA0CTLW0_H); +sfr_w(UCA0CTLW1); /* eUSCI_Ax Control Word Register 1 */ +sfr_b(UCA0CTLW1_L); +sfr_b(UCA0CTLW1_H); +sfr_w(UCA0BRW); /* eUSCI_Ax Baud Rate Control Word Register */ +sfr_b(UCA0BRW_L); +sfr_b(UCA0BRW_H); +sfr_w(UCA0MCTLW); /* eUSCI_Ax Modulation Control Word Register */ +sfr_b(UCA0MCTLW_L); +sfr_b(UCA0MCTLW_H); +sfr_w(UCA0STATW); /* eUSCI_Ax Status Register */ +sfr_b(UCA0STATW_L); +sfr_b(UCA0STATW_H); +sfr_w(UCA0RXBUF); /* eUSCI_Ax Receive Buffer Register */ +sfr_b(UCA0RXBUF_L); +sfr_b(UCA0RXBUF_H); +sfr_w(UCA0TXBUF); /* eUSCI_Ax Transmit Buffer Register */ +sfr_b(UCA0TXBUF_L); +sfr_b(UCA0TXBUF_H); +sfr_w(UCA0ABCTL); /* eUSCI_Ax Auto Baud Rate Control Register */ +sfr_b(UCA0ABCTL_L); +sfr_b(UCA0ABCTL_H); +sfr_w(UCA0IRCTL); /* eUSCI_Ax IrDA Control Word Register */ +sfr_b(UCA0IRCTL_L); +sfr_b(UCA0IRCTL_H); +sfr_w(UCA0IE); /* eUSCI_Ax Interrupt Enable Register */ +sfr_b(UCA0IE_L); +sfr_b(UCA0IE_H); +sfr_w(UCA0IFG); /* eUSCI_Ax Interrupt Flag Register */ +sfr_b(UCA0IFG_L); +sfr_b(UCA0IFG_H); +sfr_w(UCA0IV); /* eUSCI_Ax Interrupt Vector Register */ +sfr_b(UCA0IV_L); +sfr_b(UCA0IV_H); + +/* eUSCI_A0 Register Offsets */ +#define OFS_UCA0CTLW0 (0x0000) +#define OFS_UCA0CTLW1 (0x0002) +#define OFS_UCA0BRW (0x0006) +#define OFS_UCA0MCTLW (0x0008) +#define OFS_UCA0STATW (0x000A) +#define OFS_UCA0RXBUF (0x000C) +#define OFS_UCA0TXBUF (0x000E) +#define OFS_UCA0ABCTL (0x0010) +#define OFS_UCA0IRCTL (0x0012) +#define OFS_UCA0IE (0x001A) +#define OFS_UCA0IFG (0x001C) +#define OFS_UCA0IV (0x001E) + +/* eUSCI_A0 Control Bits */ + +/* UCA0CTLW0 Control Bits */ +#define UCSWRST (0x0001) /* Software reset enable */ +#define UCSWRST_0 (0x0000) /* Disabled. eUSCI_A reset released for operation */ +#define UCSWRST_1 (0x0001) /* Enabled. eUSCI_A logic held in reset state */ +#define UCSWRST__DISABLE (0x0000) /* Disabled. eUSCI_A reset released for operation */ +#define UCSWRST__ENABLE (0x0001) /* Enabled. eUSCI_A logic held in reset state */ +#define UCTXBRK (0x0002) /* Transmit break */ +#define UCTXBRK_0 (0x0000) /* Next frame transmitted is not a break */ +#define UCTXBRK_1 (0x0002) /* Next frame transmitted is a break or a break/synch */ +#define UCTXADDR (0x0004) /* Transmit address */ +#define UCTXADDR_0 (0x0000) /* Next frame transmitted is data */ +#define UCTXADDR_1 (0x0004) /* Next frame transmitted is an address */ +#define UCDORM (0x0008) /* Dormant */ +#define UCDORM_0 (0x0000) /* Not dormant. All received characters set UCRXIFG. */ +#define UCDORM_1 (0x0008) /* Dormant. Only characters that are preceded by an idle-line or + with address bit set UCRXIFG. In UART mode with automatic + baud-rate detection, only the combination of a break and synch + field sets UCRXIFG. */ +#define UCBRKIE (0x0010) /* Receive break character interrupt enable */ +#define UCBRKIE_0 (0x0000) /* Received break characters do not set UCRXIFG */ +#define UCBRKIE_1 (0x0010) /* Received break characters set UCRXIFG */ +#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */ +#define UCRXEIE_0 (0x0000) /* Erroneous characters rejected and UCRXIFG is not set */ +#define UCRXEIE_1 (0x0020) /* Erroneous characters received set UCRXIFG */ +#define UCSSEL (0x00c0) /* eUSCI_A clock source select */ +#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */ +#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */ +#define UCSSEL_0 (0x0000) /* UCLK */ +#define UCSSEL_1 (0x0040) /* ACLK */ +#define UCSSEL_2 (0x0080) /* SMCLK */ +#define UCSSEL_3 (0x00c0) /* SMCLK */ +#define UCSSEL__UCLK (0x0000) /* UCLK */ +#define UCSSEL__ACLK (0x0040) /* ACLK */ +#define UCSSEL__SMCLK (0x0080) /* SMCLK */ +#define UCSYNC (0x0100) /* Synchronous mode enable */ +#define UCSYNC_0 (0x0000) /* Asynchronous mode */ +#define UCSYNC_1 (0x0100) /* Synchronous mode */ +#define UCSYNC__ASYNC (0x0000) /* Asynchronous mode */ +#define UCSYNC__SYNC (0x0100) /* Synchronous mode */ +#define UCMODE (0x0600) /* eUSCI_A mode */ +#define UCMODE0 (0x0200) /* eUSCI_A mode */ +#define UCMODE1 (0x0400) /* eUSCI_A mode */ +#define UCMODE_0 (0x0000) /* UART mode */ +#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */ +#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */ +#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */ +#define UCSPB (0x0800) /* Stop bit select */ +#define UCSPB_0 (0x0000) /* One stop bit */ +#define UCSPB_1 (0x0800) /* Two stop bits */ +#define UC7BIT (0x1000) /* Character length */ +#define UC7BIT_0 (0x0000) /* 8-bit data */ +#define UC7BIT_1 (0x1000) /* 7-bit data */ +#define UC7BIT__8BIT (0x0000) /* 8-bit data */ +#define UC7BIT__7BIT (0x1000) /* 7-bit data */ +#define UCMSB (0x2000) /* MSB first select */ +#define UCMSB_0 (0x0000) /* LSB first */ +#define UCMSB_1 (0x2000) /* MSB first */ +#define UCPAR (0x4000) /* Parity select */ +#define UCPAR_0 (0x0000) /* Odd parity */ +#define UCPAR_1 (0x4000) /* Even parity */ +#define UCPAR__ODD (0x0000) /* Odd parity */ +#define UCPAR__EVEN (0x4000) /* Even parity */ +#define UCPEN (0x8000) /* Parity enable */ +#define UCPEN_0 (0x0000) /* Parity disabled */ +#define UCPEN_1 (0x8000) /* Parity enabled. Parity bit is generated (UCAxTXD) and expected + (UCAxRXD). In address-bit multiprocessor mode, the address bit + is included in the parity calculation. */ + +/* UCA0CTLW0_SPI Control Bits */ +#define UCSTEM (0x0002) /* STE mode select in master mode. */ +#define UCSTEM_0 (0x0000) /* STE pin is used to prevent conflicts with other masters */ +#define UCSTEM_1 (0x0002) /* STE pin is used to generate the enable signal for a 4-wire + slave */ +#define UCMST (0x0800) /* Master mode select */ +#define UCMST_0 (0x0000) /* Slave mode */ +#define UCMST_1 (0x0800) /* Master mode */ +#define UCMST__SLAVE (0x0000) /* Slave mode */ +#define UCMST__MASTER (0x0800) /* Master mode */ +#define UCCKPL (0x4000) /* Clock polarity select */ +#define UCCKPL_0 (0x0000) /* The inactive state is low */ +#define UCCKPL_1 (0x4000) /* The inactive state is high */ +#define UCCKPL__LOW (0x0000) /* The inactive state is low */ +#define UCCKPL__HIGH (0x4000) /* The inactive state is high */ +#define UCCKPH (0x8000) /* Clock phase select */ +#define UCCKPH_0 (0x0000) /* Data is changed on the first UCLK edge and captured on the + following edge. */ +#define UCCKPH_1 (0x8000) /* Data is captured on the first UCLK edge and changed on the + following edge. */ + +/* UCA0CTLW1 Control Bits */ +#define UCGLIT (0x0003) /* Deglitch time */ +#define UCGLIT0 (0x0001) /* Deglitch time */ +#define UCGLIT1 (0x0002) /* Deglitch time */ +#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */ +#define UCGLIT_1 (0x0001) /* Approximately 50 ns */ +#define UCGLIT_2 (0x0002) /* Approximately 100 ns */ +#define UCGLIT_3 (0x0003) /* Approximately 200 ns */ + +/* UCA0BRW Control Bits */ +#define UCBR (0xffff) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR0 (0x0001) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR1 (0x0002) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR2 (0x0004) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR3 (0x0008) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR4 (0x0010) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR5 (0x0020) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR6 (0x0040) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR7 (0x0080) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR8 (0x0100) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR9 (0x0200) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR10 (0x0400) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR11 (0x0800) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR12 (0x1000) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR13 (0x2000) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR14 (0x4000) /* Clock prescaler setting of the Baud rate generator */ +#define UCBR15 (0x8000) /* Clock prescaler setting of the Baud rate generator */ + +/* UCA0MCTLW Control Bits */ +#define UCOS16 (0x0001) /* Oversampling mode enabled */ +#define UCOS16_0 (0x0000) /* Disabled */ +#define UCOS16_1 (0x0001) /* Enabled */ +#define UCBRF (0x00f0) /* First modulation stage select */ +#define UCBRF0 (0x0010) /* First modulation stage select */ +#define UCBRF1 (0x0020) /* First modulation stage select */ +#define UCBRF2 (0x0040) /* First modulation stage select */ +#define UCBRF3 (0x0080) /* First modulation stage select */ +#define UCBRS (0xff00) /* Second modulation stage select */ +#define UCBRS0 (0x0100) /* Second modulation stage select */ +#define UCBRS1 (0x0200) /* Second modulation stage select */ +#define UCBRS2 (0x0400) /* Second modulation stage select */ +#define UCBRS3 (0x0800) /* Second modulation stage select */ +#define UCBRS4 (0x1000) /* Second modulation stage select */ +#define UCBRS5 (0x2000) /* Second modulation stage select */ +#define UCBRS6 (0x4000) /* Second modulation stage select */ +#define UCBRS7 (0x8000) /* Second modulation stage select */ + +/* UCA0STATW Control Bits */ +#define UCBUSY (0x0001) /* eUSCI_A busy */ +#define UCBUSY_0 (0x0000) /* eUSCI_A inactive */ +#define UCBUSY_1 (0x0001) /* eUSCI_A transmitting or receiving */ +#define UCBUSY__IDLE (0x0000) /* eUSCI_A inactive */ +#define UCBUSY__BUSY (0x0001) /* eUSCI_A transmitting or receiving */ +#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */ +#define UCADDR_UCIDLE_0 (0x0000) /* UCADDR: Received character is data. UCIDLE: No idle line + detected */ +#define UCADDR_UCIDLE_1 (0x0002) /* UCADDR: Received character is an address. UCIDLE: Idle line + detected */ +#define UCRXERR (0x0004) /* Receive error flag */ +#define UCRXERR_0 (0x0000) /* No receive errors detected */ +#define UCRXERR_1 (0x0004) /* Receive error detected */ +#define UCBRK (0x0008) /* Break detect flag */ +#define UCBRK_0 (0x0000) /* No break condition */ +#define UCBRK_1 (0x0008) /* Break condition occurred */ +#define UCPE (0x0010) /* */ +#define UCPE_0 (0x0000) /* No error */ +#define UCPE_1 (0x0010) /* Character received with parity error */ +#define UCOE (0x0020) /* Overrun error flag */ +#define UCOE_0 (0x0000) /* No error */ +#define UCOE_1 (0x0020) /* Overrun error occurred */ +#define UCFE (0x0040) /* Framing error flag */ +#define UCFE_0 (0x0000) /* No error */ +#define UCFE_1 (0x0040) /* Character received with low stop bit */ +#define UCLISTEN (0x0080) /* Listen enable */ +#define UCLISTEN_0 (0x0000) /* Disabled */ +#define UCLISTEN_1 (0x0080) /* Enabled. UCAxTXD is internally fed back to the receiver */ + +/* UCA0RXBUF Control Bits */ +#define UCRXBUF (0x00ff) /* Receive data buffer */ +#define UCRXBUF0 (0x0001) /* Receive data buffer */ +#define UCRXBUF1 (0x0002) /* Receive data buffer */ +#define UCRXBUF2 (0x0004) /* Receive data buffer */ +#define UCRXBUF3 (0x0008) /* Receive data buffer */ +#define UCRXBUF4 (0x0010) /* Receive data buffer */ +#define UCRXBUF5 (0x0020) /* Receive data buffer */ +#define UCRXBUF6 (0x0040) /* Receive data buffer */ +#define UCRXBUF7 (0x0080) /* Receive data buffer */ + +/* UCA0TXBUF Control Bits */ +#define UCTXBUF (0x00ff) /* Transmit data buffer */ +#define UCTXBUF0 (0x0001) /* Transmit data buffer */ +#define UCTXBUF1 (0x0002) /* Transmit data buffer */ +#define UCTXBUF2 (0x0004) /* Transmit data buffer */ +#define UCTXBUF3 (0x0008) /* Transmit data buffer */ +#define UCTXBUF4 (0x0010) /* Transmit data buffer */ +#define UCTXBUF5 (0x0020) /* Transmit data buffer */ +#define UCTXBUF6 (0x0040) /* Transmit data buffer */ +#define UCTXBUF7 (0x0080) /* Transmit data buffer */ + +/* UCA0ABCTL Control Bits */ +#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */ +#define UCABDEN_0 (0x0000) /* Baud-rate detection disabled. Length of break and synch field + is not measured. */ +#define UCABDEN_1 (0x0001) /* Baud-rate detection enabled. Length of break and synch field + is measured and baud-rate settings are changed accordingly. */ +#define UCBTOE (0x0004) /* Break time out error */ +#define UCBTOE_0 (0x0000) /* No error */ +#define UCBTOE_1 (0x0004) /* Length of break field exceeded 22 bit times */ +#define UCSTOE (0x0008) /* Synch field time out error */ +#define UCSTOE_0 (0x0000) /* No error */ +#define UCSTOE_1 (0x0008) /* Length of synch field exceeded measurable time */ +#define UCDELIM (0x0030) /* Break/synch delimiter length */ +#define UCDELIM0 (0x0010) /* Break/synch delimiter length */ +#define UCDELIM1 (0x0020) /* Break/synch delimiter length */ +#define UCDELIM_0 (0x0000) /* 1 bit time */ +#define UCDELIM_1 (0x0010) /* 2 bit times */ +#define UCDELIM_2 (0x0020) /* 3 bit times */ +#define UCDELIM_3 (0x0030) /* 4 bit times */ + +/* UCA0IRCTL Control Bits */ +#define UCIREN (0x0001) /* IrDA encoder/decoder enable */ +#define UCIREN_0 (0x0000) /* IrDA encoder/decoder disabled */ +#define UCIREN_1 (0x0001) /* IrDA encoder/decoder enabled */ +#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */ +#define UCIRTXCLK_0 (0x0000) /* BRCLK */ +#define UCIRTXCLK_1 (0x0002) /* BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. */ +#define UCIRTXPL (0x00fc) /* Transmit pulse length */ +#define UCIRTXPL0 (0x0004) /* Transmit pulse length */ +#define UCIRTXPL1 (0x0008) /* Transmit pulse length */ +#define UCIRTXPL2 (0x0010) /* Transmit pulse length */ +#define UCIRTXPL3 (0x0020) /* Transmit pulse length */ +#define UCIRTXPL4 (0x0040) /* Transmit pulse length */ +#define UCIRTXPL5 (0x0080) /* Transmit pulse length */ +#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */ +#define UCIRRXFE_0 (0x0000) /* Receive filter disabled */ +#define UCIRRXFE_1 (0x0100) /* Receive filter enabled */ +#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */ +#define UCIRRXPL_0 (0x0000) /* IrDA transceiver delivers a high pulse when a light pulse is + seen */ +#define UCIRRXPL_1 (0x0200) /* IrDA transceiver delivers a low pulse when a light pulse is + seen */ +#define UCIRRXPL__HIGH (0x0000) /* IrDA transceiver delivers a high pulse when a light pulse is + seen */ +#define UCIRRXPL__LOW (0x0200) /* IrDA transceiver delivers a low pulse when a light pulse is + seen */ +#define UCIRRXFL (0xfc00) /* Receive filter length */ +#define UCIRRXFL0 (0x0400) /* Receive filter length */ +#define UCIRRXFL1 (0x0800) /* Receive filter length */ +#define UCIRRXFL2 (0x1000) /* Receive filter length */ +#define UCIRRXFL3 (0x2000) /* Receive filter length */ +#define UCIRRXFL4 (0x4000) /* Receive filter length */ +#define UCIRRXFL5 (0x8000) /* Receive filter length */ + +/* UCA0IE Control Bits */ +#define UCRXIE (0x0001) /* Receive interrupt enable */ +#define UCRXIE_0 (0x0000) /* Interrupt disabled */ +#define UCRXIE_1 (0x0001) /* Interrupt enabled */ +#define UCTXIE (0x0002) /* Transmit interrupt enable */ +#define UCTXIE_0 (0x0000) /* Interrupt disabled */ +#define UCTXIE_1 (0x0002) /* Interrupt enabled */ +#define UCSTTIE (0x0004) /* Start bit interrupt enable */ +#define UCSTTIE_0 (0x0000) /* Interrupt disabled */ +#define UCSTTIE_1 (0x0004) /* Interrupt enabled */ +#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */ +#define UCTXCPTIE_0 (0x0000) /* Interrupt disabled */ +#define UCTXCPTIE_1 (0x0008) /* Interrupt enabled */ + +/* UCA0IFG Control Bits */ +#define UCRXIFG (0x0001) /* Receive interrupt flag */ +#define UCRXIFG_0 (0x0000) /* No interrupt pending */ +#define UCRXIFG_1 (0x0001) /* Interrupt pending */ +#define UCTXIFG (0x0002) /* Transmit interrupt flag */ +#define UCTXIFG_0 (0x0000) /* No interrupt pending */ +#define UCTXIFG_1 (0x0002) /* Interrupt pending */ +#define UCSTTIFG (0x0004) /* Start bit interrupt flag */ +#define UCSTTIFG_0 (0x0000) /* No interrupt pending */ +#define UCSTTIFG_1 (0x0004) /* Interrupt pending */ +#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */ +#define UCTXCPTIFG_0 (0x0000) /* No interrupt pending */ +#define UCTXCPTIFG_1 (0x0008) /* Interrupt pending */ + +/* UCA0IV Control Bits */ +#define UCIV (0xffff) /* eUSCI_A interrupt vector value */ +#define UCIV0 (0x0001) /* eUSCI_A interrupt vector value */ +#define UCIV1 (0x0002) /* eUSCI_A interrupt vector value */ +#define UCIV2 (0x0004) /* eUSCI_A interrupt vector value */ +#define UCIV3 (0x0008) /* eUSCI_A interrupt vector value */ +#define UCIV4 (0x0010) /* eUSCI_A interrupt vector value */ +#define UCIV5 (0x0020) /* eUSCI_A interrupt vector value */ +#define UCIV6 (0x0040) /* eUSCI_A interrupt vector value */ +#define UCIV7 (0x0080) /* eUSCI_A interrupt vector value */ +#define UCIV8 (0x0100) /* eUSCI_A interrupt vector value */ +#define UCIV9 (0x0200) /* eUSCI_A interrupt vector value */ +#define UCIV10 (0x0400) /* eUSCI_A interrupt vector value */ +#define UCIV11 (0x0800) /* eUSCI_A interrupt vector value */ +#define UCIV12 (0x1000) /* eUSCI_A interrupt vector value */ +#define UCIV13 (0x2000) /* eUSCI_A interrupt vector value */ +#define UCIV14 (0x4000) /* eUSCI_A interrupt vector value */ +#define UCIV15 (0x8000) /* eUSCI_A interrupt vector value */ +#define UCIV_0 (0x0000) /* No interrupt pending */ +#define UCIV_2 (0x0002) /* Interrupt Source: Receive buffer full; Interrupt Flag: + UCRXIFG; Interrupt Priority: Highest */ +#define UCIV_4 (0x0004) /* Interrupt Source: Transmit buffer empty; Interrupt Flag: + UCTXIFG */ +#define UCIV_6 (0x0006) /* Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG */ +#define UCIV_8 (0x0008) /* Interrupt Source: Transmit complete; Interrupt Flag: + UCTXCPTIFG; Interrupt Priority: Lowest */ +#define UCIV__NONE (0x0000) /* No interrupt pending */ +#define UCIV__UCRXIFG (0x0002) /* Interrupt Source: Receive buffer full; Interrupt Flag: + UCRXIFG; Interrupt Priority: Highest */ +#define UCIV__UCTXIFG (0x0004) /* Interrupt Source: Transmit buffer empty; Interrupt Flag: + UCTXIFG */ +#define UCIV__UCSTTIFG (0x0006) /* Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG */ +#define UCIV__UCTXCPTIFG (0x0008) /* Interrupt Source: Transmit complete; Interrupt Flag: + UCTXCPTIFG; Interrupt Priority: Lowest */ + + +/***************************************************************************** + eUSCI_A1 Registers +*****************************************************************************/ + +#define __MSP430_HAS_EUSCI_A1__ /* Definition to show that module is available */ +#ifndef __MSP430_HAS_EUSCI_Ax__ +#define __MSP430_HAS_EUSCI_Ax__ +#endif +#define __MSP430_BASEADDRESS_EUSCI_A1__ 0x0520 +#define EUSCI_A1_BASE __MSP430_BASEADDRESS_EUSCI_A1__ + +sfr_w(UCA1CTLW0); /* eUSCI_Ax Control Word Register 0 */ +sfr_b(UCA1CTLW0_L); +sfr_b(UCA1CTLW0_H); +sfr_w(UCA1CTLW1); /* eUSCI_Ax Control Word Register 1 */ +sfr_b(UCA1CTLW1_L); +sfr_b(UCA1CTLW1_H); +sfr_w(UCA1BRW); /* eUSCI_Ax Baud Rate Control Word Register */ +sfr_b(UCA1BRW_L); +sfr_b(UCA1BRW_H); +sfr_w(UCA1MCTLW); /* eUSCI_Ax Modulation Control Word Register */ +sfr_b(UCA1MCTLW_L); +sfr_b(UCA1MCTLW_H); +sfr_w(UCA1STATW); /* eUSCI_Ax Status Register */ +sfr_b(UCA1STATW_L); +sfr_b(UCA1STATW_H); +sfr_w(UCA1RXBUF); /* eUSCI_Ax Receive Buffer Register */ +sfr_b(UCA1RXBUF_L); +sfr_b(UCA1RXBUF_H); +sfr_w(UCA1TXBUF); /* eUSCI_Ax Transmit Buffer Register */ +sfr_b(UCA1TXBUF_L); +sfr_b(UCA1TXBUF_H); +sfr_w(UCA1ABCTL); /* eUSCI_Ax Auto Baud Rate Control Register */ +sfr_b(UCA1ABCTL_L); +sfr_b(UCA1ABCTL_H); +sfr_w(UCA1IRCTL); /* eUSCI_Ax IrDA Control Word Register */ +sfr_b(UCA1IRCTL_L); +sfr_b(UCA1IRCTL_H); +sfr_w(UCA1IE); /* eUSCI_Ax Interrupt Enable Register */ +sfr_b(UCA1IE_L); +sfr_b(UCA1IE_H); +sfr_w(UCA1IFG); /* eUSCI_Ax Interrupt Flag Register */ +sfr_b(UCA1IFG_L); +sfr_b(UCA1IFG_H); +sfr_w(UCA1IV); /* eUSCI_Ax Interrupt Vector Register */ +sfr_b(UCA1IV_L); +sfr_b(UCA1IV_H); + +/* eUSCI_A1 Register Offsets */ +#define OFS_UCA1CTLW0 (0x0000) +#define OFS_UCA1CTLW1 (0x0002) +#define OFS_UCA1BRW (0x0006) +#define OFS_UCA1MCTLW (0x0008) +#define OFS_UCA1STATW (0x000A) +#define OFS_UCA1RXBUF (0x000C) +#define OFS_UCA1TXBUF (0x000E) +#define OFS_UCA1ABCTL (0x0010) +#define OFS_UCA1IRCTL (0x0012) +#define OFS_UCA1IE (0x001A) +#define OFS_UCA1IFG (0x001C) +#define OFS_UCA1IV (0x001E) + +/* No control bits available or already defined for another module */ + +/***************************************************************************** + eUSCI_B0 Registers +*****************************************************************************/ + +#define __MSP430_HAS_EUSCI_B0__ /* Definition to show that module is available */ +#ifndef __MSP430_HAS_EUSCI_Bx__ +#define __MSP430_HAS_EUSCI_Bx__ +#endif +#define __MSP430_BASEADDRESS_EUSCI_B0__ 0x0540 +#define EUSCI_B0_BASE __MSP430_BASEADDRESS_EUSCI_B0__ + +sfr_w(UCB0CTLW0); /* eUSCI_Bx Control Word Register 0 */ +sfr_b(UCB0CTLW0_L); +sfr_b(UCB0CTLW0_H); +sfr_w(UCB0CTLW1); /* eUSCI_Bx Control Word Register 1 */ +sfr_b(UCB0CTLW1_L); +sfr_b(UCB0CTLW1_H); +sfr_w(UCB0BRW); /* eUSCI_Bx Baud Rate Control Word Register */ +sfr_b(UCB0BRW_L); +sfr_b(UCB0BRW_H); +sfr_w(UCB0STATW); /* eUSCI_Bx Status Register */ +sfr_b(UCB0STATW_L); +sfr_b(UCB0STATW_H); +sfr_w(UCB0TBCNT); /* eUSCI_Bx Byte Counter Threshold Register */ +sfr_b(UCB0TBCNT_L); +sfr_b(UCB0TBCNT_H); +sfr_w(UCB0RXBUF); /* eUSCI_Bx Receive Buffer Register */ +sfr_b(UCB0RXBUF_L); +sfr_b(UCB0RXBUF_H); +sfr_w(UCB0TXBUF); /* eUSCI_Bx Transmit Buffer Register */ +sfr_b(UCB0TXBUF_L); +sfr_b(UCB0TXBUF_H); +sfr_w(UCB0I2COA0); /* eUSCI_Bx I2C Own Address 0 Register */ +sfr_b(UCB0I2COA0_L); +sfr_b(UCB0I2COA0_H); +sfr_w(UCB0I2COA1); /* eUSCI_Bx I2C Own Address 1 Register */ +sfr_b(UCB0I2COA1_L); +sfr_b(UCB0I2COA1_H); +sfr_w(UCB0I2COA2); /* eUSCI_Bx I2C Own Address 2 Register */ +sfr_b(UCB0I2COA2_L); +sfr_b(UCB0I2COA2_H); +sfr_w(UCB0I2COA3); /* eUSCI_Bx I2C Own Address 3 Register */ +sfr_b(UCB0I2COA3_L); +sfr_b(UCB0I2COA3_H); +sfr_w(UCB0ADDRX); /* eUSCI_Bx I2C Received Address Register */ +sfr_b(UCB0ADDRX_L); +sfr_b(UCB0ADDRX_H); +sfr_w(UCB0ADDMASK); /* eUSCI_Bx I2C Address Mask Register */ +sfr_b(UCB0ADDMASK_L); +sfr_b(UCB0ADDMASK_H); +sfr_w(UCB0I2CSA); /* eUSCI_Bx I2C Slave Address Register */ +sfr_b(UCB0I2CSA_L); +sfr_b(UCB0I2CSA_H); +sfr_w(UCB0IE); /* eUSCI_Bx Interrupt Enable Register */ +sfr_b(UCB0IE_L); +sfr_b(UCB0IE_H); +sfr_w(UCB0IFG); /* eUSCI_Bx Interrupt Flag Register */ +sfr_b(UCB0IFG_L); +sfr_b(UCB0IFG_H); +sfr_w(UCB0IV); /* eUSCI_Bx Interrupt Vector Register */ +sfr_b(UCB0IV_L); +sfr_b(UCB0IV_H); + +/* eUSCI_B0 Register Offsets */ +#define OFS_UCB0CTLW0 (0x0000) +#define OFS_UCB0CTLW1 (0x0002) +#define OFS_UCB0BRW (0x0006) +#define OFS_UCB0STATW (0x0008) +#define OFS_UCB0TBCNT (0x000A) +#define OFS_UCB0RXBUF (0x000C) +#define OFS_UCB0TXBUF (0x000E) +#define OFS_UCB0I2COA0 (0x0014) +#define OFS_UCB0I2COA1 (0x0016) +#define OFS_UCB0I2COA2 (0x0018) +#define OFS_UCB0I2COA3 (0x001A) +#define OFS_UCB0ADDRX (0x001C) +#define OFS_UCB0ADDMASK (0x001E) +#define OFS_UCB0I2CSA (0x0020) +#define OFS_UCB0IE (0x002A) +#define OFS_UCB0IFG (0x002C) +#define OFS_UCB0IV (0x002E) + +/* eUSCI_B0 Control Bits */ + +/* UCB0CTLW0 Control Bits */ +#define UCTXSTT (0x0002) /* Transmit START condition in master mode */ +#define UCTXSTT_0 (0x0000) /* Do not generate START condition */ +#define UCTXSTT_1 (0x0002) /* Generate START condition */ +#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */ +#define UCTXSTP_0 (0x0000) /* No STOP generated */ +#define UCTXSTP_1 (0x0004) /* Generate STOP */ +#define UCTXNACK (0x0008) /* Transmit a NACK */ +#define UCTXNACK_0 (0x0000) /* Acknowledge normally */ +#define UCTXNACK_1 (0x0008) /* Generate NACK */ +#define UCTR (0x0010) /* Transmitter/receiver */ +#define UCTR_0 (0x0000) /* Receiver */ +#define UCTR_1 (0x0010) /* Transmitter */ +#define UCTR__RX (0x0000) /* Receiver */ +#define UCTR__TX (0x0010) /* Transmitter */ +#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */ +#define UCTXACK_0 (0x0000) /* Do not acknowledge the slave address */ +#define UCTXACK_1 (0x0020) /* Acknowledge the slave address */ +#define UCSSEL__UCLKI (0x0000) /* UCLKI */ +#define UCMM (0x2000) /* Multi-master environment select */ +#define UCMM_0 (0x0000) /* Single master environment. There is no other master in the + system. The address compare unit is disabled. */ +#define UCMM_1 (0x2000) /* Multi-master environment */ +#define UCMM__SINGLE (0x0000) /* Single master environment. There is no other master in the + system. The address compare unit is disabled. */ +#define UCMM__MULTI (0x2000) /* Multi-master environment */ +#define UCSLA10 (0x4000) /* Slave addressing mode select */ +#define UCSLA10_0 (0x0000) /* Address slave with 7-bit address */ +#define UCSLA10_1 (0x4000) /* Address slave with 10-bit address */ +#define UCSLA10__7BIT (0x0000) /* Address slave with 7-bit address */ +#define UCSLA10__10BIT (0x4000) /* Address slave with 10-bit address */ +#define UCA10 (0x8000) /* Own addressing mode select */ +#define UCA10_0 (0x0000) /* Own address is a 7-bit address */ +#define UCA10_1 (0x8000) /* Own address is a 10-bit address */ + +/* UCB0CTLW1 Control Bits */ +#define UCASTP (0x000c) /* Automatic STOP condition generation */ +#define UCASTP0 (0x0004) /* Automatic STOP condition generation */ +#define UCASTP1 (0x0008) /* Automatic STOP condition generation */ +#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated + after the user sets the UCTXSTP bit. The value in UCBxTBCNT is + a don't care. */ +#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold + defined in UCBxTBCNT */ +#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte + counter value reached UCBxTBCNT. UCBCNTIFG is set with the + byte counter reaching the threshold */ +#define UCASTP_3 (0x000c) /* Reserved */ +#define UCSWACK (0x0010) /* SW or HW ACK control */ +#define UCSWACK_0 (0x0000) /* The address acknowledge of the slave is controlled by the + eUSCI_B module */ +#define UCSWACK_1 (0x0010) /* The user needs to trigger the sending of the address ACK by + issuing UCTXACK */ +#define UCSTPNACK (0x0020) /* ACK all master bytes */ +#define UCSTPNACK_0 (0x0000) /* Send a non-acknowledge before the STOP condition as a master + receiver (conform to I2C standard) */ +#define UCSTPNACK_1 (0x0020) /* All bytes are acknowledged by the eUSCI_B when configured as + master receiver */ +#define UCCLTO (0x00c0) /* Clock low timeout select */ +#define UCCLTO0 (0x0040) /* Clock low timeout select */ +#define UCCLTO1 (0x0080) /* Clock low timeout select */ +#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */ +#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */ +#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */ +#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */ +#define UCETXINT (0x0100) /* Early UCTXIFG0 */ +#define UCETXINT_0 (0x0000) /* UCTXIFGx is set after an address match with UCxI2COAx and the + direction bit indicating slave transmit */ +#define UCETXINT_1 (0x0100) /* UCTXIFG0 is set for each START condition */ + +/* UCB0STATW Control Bits */ +#define UCBBUSY (0x0010) /* Bus busy */ +#define UCBBUSY_0 (0x0000) /* Bus inactive */ +#define UCBBUSY_1 (0x0010) /* Bus busy */ +#define UCBBUSY__IDLE (0x0000) /* Bus inactive */ +#define UCBBUSY__BUSY (0x0010) /* Bus busy */ +#define UCGC (0x0020) /* General call address received */ +#define UCGC_0 (0x0000) /* No general call address received */ +#define UCGC_1 (0x0020) /* General call address received */ +#define UCSCLLOW (0x0040) /* SCL low */ +#define UCSCLLOW_0 (0x0000) /* SCL is not held low */ +#define UCSCLLOW_1 (0x0040) /* SCL is held low */ +#define UCBCNT (0xff00) /* Hardware byte counter value */ +#define UCBCNT0 (0x0100) /* Hardware byte counter value */ +#define UCBCNT1 (0x0200) /* Hardware byte counter value */ +#define UCBCNT2 (0x0400) /* Hardware byte counter value */ +#define UCBCNT3 (0x0800) /* Hardware byte counter value */ +#define UCBCNT4 (0x1000) /* Hardware byte counter value */ +#define UCBCNT5 (0x2000) /* Hardware byte counter value */ +#define UCBCNT6 (0x4000) /* Hardware byte counter value */ +#define UCBCNT7 (0x8000) /* Hardware byte counter value */ + +/* UCB0TBCNT Control Bits */ +#define UCTBCNT (0x00ff) /* Byte counter threshold value */ +#define UCTBCNT0 (0x0001) /* Byte counter threshold value */ +#define UCTBCNT1 (0x0002) /* Byte counter threshold value */ +#define UCTBCNT2 (0x0004) /* Byte counter threshold value */ +#define UCTBCNT3 (0x0008) /* Byte counter threshold value */ +#define UCTBCNT4 (0x0010) /* Byte counter threshold value */ +#define UCTBCNT5 (0x0020) /* Byte counter threshold value */ +#define UCTBCNT6 (0x0040) /* Byte counter threshold value */ +#define UCTBCNT7 (0x0080) /* Byte counter threshold value */ + +/* UCB0I2COA0 Control Bits */ +#define I2COA0 (0x03ff) /* I2C own address */ +#define I2COA00 (0x0001) /* I2C own address */ +#define I2COA01 (0x0002) /* I2C own address */ +#define I2COA02 (0x0004) /* I2C own address */ +#define I2COA03 (0x0008) /* I2C own address */ +#define I2COA04 (0x0010) /* I2C own address */ +#define I2COA05 (0x0020) /* I2C own address */ +#define I2COA06 (0x0040) /* I2C own address */ +#define I2COA07 (0x0080) /* I2C own address */ +#define I2COA08 (0x0100) /* I2C own address */ +#define I2COA09 (0x0200) /* I2C own address */ +#define UCOAEN (0x0400) /* Own Address enable register */ +#define UCOAEN_0 (0x0000) /* The slave address defined in I2COA0 is disabled */ +#define UCOAEN_1 (0x0400) /* The slave address defined in I2COA0 is enabled */ +#define UCOAEN__DISABLE (0x0000) /* The slave address defined in I2COA0 is disabled */ +#define UCOAEN__ENABLE (0x0400) /* The slave address defined in I2COA0 is enabled */ +#define UCGCEN (0x8000) /* General call response enable */ +#define UCGCEN_0 (0x0000) /* Do not respond to a general call */ +#define UCGCEN_1 (0x8000) /* Respond to a general call */ + +/* UCB0I2COA1 Control Bits */ +#define I2COA1 (0x03ff) /* I2C own address */ +#define I2COA10 (0x0001) /* I2C own address */ +#define I2COA11 (0x0002) /* I2C own address */ +#define I2COA12 (0x0004) /* I2C own address */ +#define I2COA13 (0x0008) /* I2C own address */ +#define I2COA14 (0x0010) /* I2C own address */ +#define I2COA15 (0x0020) /* I2C own address */ +#define I2COA16 (0x0040) /* I2C own address */ +#define I2COA17 (0x0080) /* I2C own address */ +#define I2COA18 (0x0100) /* I2C own address */ +#define I2COA19 (0x0200) /* I2C own address */ + +/* UCB0I2COA2 Control Bits */ +#define I2COA2 (0x03ff) /* I2C own address */ +#define I2COA20 (0x0001) /* I2C own address */ +#define I2COA21 (0x0002) /* I2C own address */ +#define I2COA22 (0x0004) /* I2C own address */ +#define I2COA23 (0x0008) /* I2C own address */ +#define I2COA24 (0x0010) /* I2C own address */ +#define I2COA25 (0x0020) /* I2C own address */ +#define I2COA26 (0x0040) /* I2C own address */ +#define I2COA27 (0x0080) /* I2C own address */ +#define I2COA28 (0x0100) /* I2C own address */ +#define I2COA29 (0x0200) /* I2C own address */ + +/* UCB0I2COA3 Control Bits */ +#define I2COA3 (0x03ff) /* I2C own address */ +#define I2COA30 (0x0001) /* I2C own address */ +#define I2COA31 (0x0002) /* I2C own address */ +#define I2COA32 (0x0004) /* I2C own address */ +#define I2COA33 (0x0008) /* I2C own address */ +#define I2COA34 (0x0010) /* I2C own address */ +#define I2COA35 (0x0020) /* I2C own address */ +#define I2COA36 (0x0040) /* I2C own address */ +#define I2COA37 (0x0080) /* I2C own address */ +#define I2COA38 (0x0100) /* I2C own address */ +#define I2COA39 (0x0200) /* I2C own address */ + +/* UCB0ADDRX Control Bits */ +#define ADDRX (0x03ff) /* Received Address Register */ +#define ADDRX0 (0x0001) /* Received Address Register */ +#define ADDRX1 (0x0002) /* Received Address Register */ +#define ADDRX2 (0x0004) /* Received Address Register */ +#define ADDRX3 (0x0008) /* Received Address Register */ +#define ADDRX4 (0x0010) /* Received Address Register */ +#define ADDRX5 (0x0020) /* Received Address Register */ +#define ADDRX6 (0x0040) /* Received Address Register */ +#define ADDRX7 (0x0080) /* Received Address Register */ +#define ADDRX8 (0x0100) /* Received Address Register */ +#define ADDRX9 (0x0200) /* Received Address Register */ + +/* UCB0ADDMASK Control Bits */ +#define ADDMASK (0x03ff) /* */ +#define ADDMASK0 (0x0001) /* */ +#define ADDMASK1 (0x0002) /* */ +#define ADDMASK2 (0x0004) /* */ +#define ADDMASK3 (0x0008) /* */ +#define ADDMASK4 (0x0010) /* */ +#define ADDMASK5 (0x0020) /* */ +#define ADDMASK6 (0x0040) /* */ +#define ADDMASK7 (0x0080) /* */ +#define ADDMASK8 (0x0100) /* */ +#define ADDMASK9 (0x0200) /* */ + +/* UCB0I2CSA Control Bits */ +#define I2CSA (0x03ff) /* I2C slave address */ +#define I2CSA0 (0x0001) /* I2C slave address */ +#define I2CSA1 (0x0002) /* I2C slave address */ +#define I2CSA2 (0x0004) /* I2C slave address */ +#define I2CSA3 (0x0008) /* I2C slave address */ +#define I2CSA4 (0x0010) /* I2C slave address */ +#define I2CSA5 (0x0020) /* I2C slave address */ +#define I2CSA6 (0x0040) /* I2C slave address */ +#define I2CSA7 (0x0080) /* I2C slave address */ +#define I2CSA8 (0x0100) /* I2C slave address */ +#define I2CSA9 (0x0200) /* I2C slave address */ + +/* UCB0IE Control Bits */ +#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */ +#define UCRXIE0_0 (0x0000) /* Interrupt disabled */ +#define UCRXIE0_1 (0x0001) /* Interrupt enabled */ +#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */ +#define UCTXIE0_0 (0x0000) /* Interrupt disabled */ +#define UCTXIE0_1 (0x0002) /* Interrupt enabled */ +#define UCSTPIE (0x0008) /* STOP condition interrupt enable */ +#define UCSTPIE_0 (0x0000) /* Interrupt disabled */ +#define UCSTPIE_1 (0x0008) /* Interrupt enabled */ +#define UCALIE (0x0010) /* Arbitration lost interrupt enable */ +#define UCALIE_0 (0x0000) /* Interrupt disabled */ +#define UCALIE_1 (0x0010) /* Interrupt enabled */ +#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */ +#define UCNACKIE_0 (0x0000) /* Interrupt disabled */ +#define UCNACKIE_1 (0x0020) /* Interrupt enabled */ +#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */ +#define UCBCNTIE_0 (0x0000) /* Interrupt disabled */ +#define UCBCNTIE_1 (0x0040) /* Interrupt enabled */ +#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */ +#define UCCLTOIE_0 (0x0000) /* Interrupt disabled */ +#define UCCLTOIE_1 (0x0080) /* Interrupt enabled */ +#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */ +#define UCRXIE1_0 (0x0000) /* Interrupt disabled */ +#define UCRXIE1_1 (0x0100) /* Interrupt enabled */ +#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */ +#define UCTXIE1_0 (0x0000) /* Interrupt disabled */ +#define UCTXIE1_1 (0x0200) /* Interrupt enabled */ +#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */ +#define UCRXIE2_0 (0x0000) /* Interrupt disabled */ +#define UCRXIE2_1 (0x0400) /* Interrupt enabled */ +#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */ +#define UCTXIE2_0 (0x0000) /* Interrupt disabled */ +#define UCTXIE2_1 (0x0800) /* Interrupt enabled */ +#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */ +#define UCRXIE3_0 (0x0000) /* Interrupt disabled */ +#define UCRXIE3_1 (0x1000) /* Interrupt enabled */ +#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */ +#define UCTXIE3_0 (0x0000) /* Interrupt disabled */ +#define UCTXIE3_1 (0x2000) /* Interrupt enabled */ +#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */ +#define UCBIT9IE_0 (0x0000) /* Interrupt disabled */ +#define UCBIT9IE_1 (0x4000) /* Interrupt enabled */ + +/* UCB0IFG Control Bits */ +#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */ +#define UCRXIFG0_0 (0x0000) /* No interrupt pending */ +#define UCRXIFG0_1 (0x0001) /* Interrupt pending */ +#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */ +#define UCTXIFG0_0 (0x0000) /* No interrupt pending */ +#define UCTXIFG0_1 (0x0002) /* Interrupt pending */ +#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */ +#define UCSTPIFG_0 (0x0000) /* No interrupt pending */ +#define UCSTPIFG_1 (0x0008) /* Interrupt pending */ +#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */ +#define UCALIFG_0 (0x0000) /* No interrupt pending */ +#define UCALIFG_1 (0x0010) /* Interrupt pending */ +#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */ +#define UCNACKIFG_0 (0x0000) /* No interrupt pending */ +#define UCNACKIFG_1 (0x0020) /* Interrupt pending */ +#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */ +#define UCBCNTIFG_0 (0x0000) /* No interrupt pending */ +#define UCBCNTIFG_1 (0x0040) /* Interrupt pending */ +#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */ +#define UCCLTOIFG_0 (0x0000) /* No interrupt pending */ +#define UCCLTOIFG_1 (0x0080) /* Interrupt pending */ +#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */ +#define UCRXIFG1_0 (0x0000) /* No interrupt pending */ +#define UCRXIFG1_1 (0x0100) /* Interrupt pending */ +#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */ +#define UCTXIFG1_0 (0x0000) /* No interrupt pending */ +#define UCTXIFG1_1 (0x0200) /* Interrupt pending */ +#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */ +#define UCRXIFG2_0 (0x0000) /* No interrupt pending */ +#define UCRXIFG2_1 (0x0400) /* Interrupt pending */ +#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */ +#define UCTXIFG2_0 (0x0000) /* No interrupt pending */ +#define UCTXIFG2_1 (0x0800) /* Interrupt pending */ +#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */ +#define UCRXIFG3_0 (0x0000) /* No interrupt pending */ +#define UCRXIFG3_1 (0x1000) /* Interrupt pending */ +#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */ +#define UCTXIFG3_0 (0x0000) /* No interrupt pending */ +#define UCTXIFG3_1 (0x2000) /* Interrupt pending */ +#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */ +#define UCBIT9IFG_0 (0x0000) /* No interrupt pending */ +#define UCBIT9IFG_1 (0x4000) /* Interrupt pending */ + +#define UCIV__UCALIFG (0x0002) /* Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; + Interrupt Priority: Highest */ +#define UCIV__UCNACKIFG (0x0004) /* Interrupt Source: Not acknowledgment; Interrupt Flag: + UCNACKIFG */ +#define UCIV__UCSTPIFG (0x0008) /* Interrupt Source: Stop condition received; Interrupt Flag: + UCSTPIFG */ +#define UCIV__UCRXIFG3 (0x000a) /* Interrupt Source: Slave 3 Data received; Interrupt Flag: + UCRXIFG3 */ +#define UCIV__UCTXIFG3 (0x000c) /* Interrupt Source: Slave 3 Transmit buffer empty; Interrupt + Flag: UCTXIFG3 */ +#define UCIV__UCRXIFG2 (0x000e) /* Interrupt Source: Slave 2 Data received; Interrupt Flag: + UCRXIFG2 */ +#define UCIV__UCTXIFG2 (0x0010) /* Interrupt Source: Slave 2 Transmit buffer empty; Interrupt + Flag: UCTXIFG2 */ +#define UCIV__UCRXIFG1 (0x0012) /* Interrupt Source: Slave 1 Data received; Interrupt Flag: + UCRXIFG1 */ +#define UCIV__UCTXIFG1 (0x0014) /* Interrupt Source: Slave 1 Transmit buffer empty; Interrupt + Flag: UCTXIFG1 */ +#define UCIV__UCRXIFG0 (0x0016) /* Interrupt Source: Data received; Interrupt Flag: UCRXIFG0 */ +#define UCIV__UCTXIFG0 (0x0018) /* Interrupt Source: Transmit buffer empty; Interrupt Flag: + UCTXIFG0 */ +#define UCIV__UCBCNTIFG (0x001a) /* Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG */ +#define UCIV__UCCLTOIFG (0x001c) /* Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG */ +#define UCIV__UCBIT9IFG (0x001e) /* Interrupt Source: Nineth bit position; Interrupt Flag: + UCBIT9IFG; Priority: Lowest */ + + +/***************************************************************************** + eUSCI_B1 Registers +*****************************************************************************/ + +#define __MSP430_HAS_EUSCI_B1__ /* Definition to show that module is available */ +#ifndef __MSP430_HAS_EUSCI_Bx__ +#define __MSP430_HAS_EUSCI_Bx__ +#endif +#define __MSP430_BASEADDRESS_EUSCI_B1__ 0x0580 +#define EUSCI_B1_BASE __MSP430_BASEADDRESS_EUSCI_B1__ + +sfr_w(UCB1CTLW0); /* eUSCI_Bx Control Word Register 0 */ +sfr_b(UCB1CTLW0_L); +sfr_b(UCB1CTLW0_H); +sfr_w(UCB1CTLW1); /* eUSCI_Bx Control Word Register 1 */ +sfr_b(UCB1CTLW1_L); +sfr_b(UCB1CTLW1_H); +sfr_w(UCB1BRW); /* eUSCI_Bx Baud Rate Control Word Register */ +sfr_b(UCB1BRW_L); +sfr_b(UCB1BRW_H); +sfr_w(UCB1STATW); /* eUSCI_Bx Status Register */ +sfr_b(UCB1STATW_L); +sfr_b(UCB1STATW_H); +sfr_w(UCB1TBCNT); /* eUSCI_Bx Byte Counter Threshold Register */ +sfr_b(UCB1TBCNT_L); +sfr_b(UCB1TBCNT_H); +sfr_w(UCB1RXBUF); /* eUSCI_Bx Receive Buffer Register */ +sfr_b(UCB1RXBUF_L); +sfr_b(UCB1RXBUF_H); +sfr_w(UCB1TXBUF); /* eUSCI_Bx Transmit Buffer Register */ +sfr_b(UCB1TXBUF_L); +sfr_b(UCB1TXBUF_H); +sfr_w(UCB1I2COA0); /* eUSCI_Bx I2C Own Address 0 Register */ +sfr_b(UCB1I2COA0_L); +sfr_b(UCB1I2COA0_H); +sfr_w(UCB1I2COA1); /* eUSCI_Bx I2C Own Address 1 Register */ +sfr_b(UCB1I2COA1_L); +sfr_b(UCB1I2COA1_H); +sfr_w(UCB1I2COA2); /* eUSCI_Bx I2C Own Address 2 Register */ +sfr_b(UCB1I2COA2_L); +sfr_b(UCB1I2COA2_H); +sfr_w(UCB1I2COA3); /* eUSCI_Bx I2C Own Address 3 Register */ +sfr_b(UCB1I2COA3_L); +sfr_b(UCB1I2COA3_H); +sfr_w(UCB1ADDRX); /* eUSCI_Bx I2C Received Address Register */ +sfr_b(UCB1ADDRX_L); +sfr_b(UCB1ADDRX_H); +sfr_w(UCB1ADDMASK); /* eUSCI_Bx I2C Address Mask Register */ +sfr_b(UCB1ADDMASK_L); +sfr_b(UCB1ADDMASK_H); +sfr_w(UCB1I2CSA); /* eUSCI_Bx I2C Slave Address Register */ +sfr_b(UCB1I2CSA_L); +sfr_b(UCB1I2CSA_H); +sfr_w(UCB1IE); /* eUSCI_Bx Interrupt Enable Register */ +sfr_b(UCB1IE_L); +sfr_b(UCB1IE_H); +sfr_w(UCB1IFG); /* eUSCI_Bx Interrupt Flag Register */ +sfr_b(UCB1IFG_L); +sfr_b(UCB1IFG_H); +sfr_w(UCB1IV); /* eUSCI_Bx Interrupt Vector Register */ +sfr_b(UCB1IV_L); +sfr_b(UCB1IV_H); + +/* eUSCI_B1 Register Offsets */ +#define OFS_UCB1CTLW0 (0x0000) +#define OFS_UCB1CTLW1 (0x0002) +#define OFS_UCB1BRW (0x0006) +#define OFS_UCB1STATW (0x0008) +#define OFS_UCB1TBCNT (0x000A) +#define OFS_UCB1RXBUF (0x000C) +#define OFS_UCB1TXBUF (0x000E) +#define OFS_UCB1I2COA0 (0x0014) +#define OFS_UCB1I2COA1 (0x0016) +#define OFS_UCB1I2COA2 (0x0018) +#define OFS_UCB1I2COA3 (0x001A) +#define OFS_UCB1ADDRX (0x001C) +#define OFS_UCB1ADDMASK (0x001E) +#define OFS_UCB1I2CSA (0x0020) +#define OFS_UCB1IE (0x002A) +#define OFS_UCB1IFG (0x002C) +#define OFS_UCB1IV (0x002E) + +/* No control bits available or already defined for another module */ + +/************************************************************ +* TLV Descriptors +************************************************************/ + +#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */ + +#define TLV_CRC_LENGTH (0x1A01) /* CRC length of the TLV structure */ +#define TLV_CRC_VALUE (0x1A02) /* CRC value of the TLV structure */ +#define TLV_START (0x1A08) /* Start Address of the TLV structure */ +#define TLV_END (0x1AFF) /* End Address of the TLV structure */ +#define TLV_CRC_START (0x1A04) /* Start Address of the CRC protected structure */ +#define TLV_CRC_END (0x1A77) /* End Address of the TLV protected structure */ + +#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */ +#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */ +#define TLV_Reserved3 (0x03) /* Reserved for future use */ +#define TLV_Reserved4 (0x04) /* Reserved for future use */ +#define TLV_BLANK (0x05) /* Blank descriptor */ +#define TLV_Reserved6 (0x06) /* Reserved for future use */ +#define TLV_Reserved7 (0x07) /* Reserved for future use */ +#define TLV_DIERECORD (0x08) /* Unique Die Record */ +#define TLV_ADCCAL (0x11) /* ADC calibration */ +#define TLV_ADC12CAL (0x11) /* ADC12 calibration */ +#define TLV_ADC10CAL (0x13) /* ADC10 calibration */ +#define TLV_REFCAL (0x12) /* REF calibration */ +#define TLV_TAGEXT (0xFE) /* Tag extender */ +#define TLV_TAGEND (0xFF) /* Tag End of Table */ + +/************************************************************ +* Interrupt Vectors (offset from 0xFF80 + 0x10 for Password) +************************************************************/ + +#define ECOMP0_VECTOR (20) /* 0xFFCA */ +#define PORT6_VECTOR (21) /* 0xFFCC */ +#define PORT5_VECTOR (22) /* 0xFFCE */ +#define PORT4_VECTOR (23) /* 0xFFD0 */ +#define PORT3_VECTOR (24) /* 0xFFD2 */ +#define PORT2_VECTOR (25) /* 0xFFD4 */ +#define PORT1_VECTOR (26) /* 0xFFD6 */ +#define ADC_VECTOR (27) /* 0xFFD8 */ +#define EUSCI_B1_VECTOR (28) /* 0xFFDA */ +#define EUSCI_B0_VECTOR (29) /* 0xFFDC */ +#define EUSCI_A1_VECTOR (30) /* 0xFFDE */ +#define EUSCI_A0_VECTOR (31) /* 0xFFE0 */ +#define WDT_VECTOR (32) /* 0xFFE2 */ +#define RTC_VECTOR (33) /* 0xFFE4 */ +#define TIMER0_B1_VECTOR (34) /* 0xFFE6 */ +#define TIMER0_B0_VECTOR (35) /* 0xFFE8 */ +#define TIMER3_A1_VECTOR (36) /* 0xFFEA */ +#define TIMER3_A0_VECTOR (37) /* 0xFFEC */ +#define TIMER2_A1_VECTOR (38) /* 0xFFEE */ +#define TIMER2_A0_VECTOR (39) /* 0xFFF0 */ +#define TIMER1_A1_VECTOR (40) /* 0xFFF2 */ +#define TIMER1_A0_VECTOR (41) /* 0xFFF4 */ +#define TIMER0_A1_VECTOR (42) /* 0xFFF6 */ +#define TIMER0_A0_VECTOR (43) /* 0xFFF8 */ +#define UNMI_VECTOR (44) /* 0xFFFA */ +#define SYSNMI_VECTOR (45) /* 0xFFFC */ +#define RESET_VECTOR ("reset") /* 0xFFFE Reset (Highest Priority) */ + + +/************************************************************ +* Memory Boundary Definitions +************************************************************/ + +#define TINYRAM_START 0x0006 +#define TINYRAM_LENGTH 0x001A +#define BSL0_START 0x1000 +#define BSL0_LENGTH 0x0800 +#define INFO_START 0x1800 +#define INFO_LENGTH 0x0200 +#define TLVMEM_START 0x1A00 +#define TLVMEM_LENGTH 0x0200 +#define BOOTCODE_START 0x1C00 +#define BOOTCODE_LENGTH 0x0400 +#define RAM_START 0x2000 +#define RAM_LENGTH 0x2000 +#define FRAM_START 0x8000 +#define FRAM_LENGTH 0x10000 +#define ROMLIB_START 0xC0000 +#define ROMLIB_LENGTH 0x4000 +#define BSL1_START 0xFFC00 +#define BSL1_LENGTH 0x0400 + +/************************************************************ +* End of Modules +************************************************************/ + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#ifndef EXCLUDE_LEGACY +#include "legacy.h" +#endif + +#endif /* #ifndef __MSP430FR2476 */ + + diff --git a/msp430/msp430fr2476.ld b/msp430/msp430fr2476.ld index 62004bd..fce197c 100644 --- a/msp430/msp430fr2476.ld +++ b/msp430/msp430fr2476.ld @@ -46,7 +46,8 @@ MEMORY { BSL1 : ORIGIN = 0xFFC00, LENGTH = 0x0400 /* END=0xFFFFF, size 1024 */ RAM : ORIGIN = 0x2000, LENGTH = 0x2000 /* END=0x3FFF, size 8192 */ INFOMEM : ORIGIN = 0x1800, LENGTH = 0x0200 /* END=0x19FF, size 512 */ - FRAM (rx) : ORIGIN = 0x8000, LENGTH = 0x7F80 /* END=0xFF7F, size 32640 */ + FRAM (rx) : ORIGIN = 0x8000, LENGTH = 0x6600 /* END=0xAFFF, size 9216 */ + LOFRAM (rxw) : ORIGIN = 0xE600, LENGTH = 0x1980 /* END=0xFF7F, size 23424 */ HIFRAM (rxw) : ORIGIN = 0x00010000, LENGTH = 0x00007FFF JTAGSIGNATURE : ORIGIN = 0xFF80, LENGTH = 0x0004 BSLSIGNATURE : ORIGIN = 0xFF84, LENGTH = 0x0004 @@ -341,6 +342,18 @@ SECTIONS *(.lower.text.* .lower.text) } > FRAM + .lodict : + { + . = ALIGN(2); + *(.lodict) + } > LOFRAM + + .hidict : + { + . = ALIGN(2); + *(.hidict) + } > HIFRAM + .text : { PROVIDE (_start = .); diff --git a/msp430/msp430fr2476_symbols.ld b/msp430/msp430fr2476_symbols.ld new file mode 100644 index 0000000..512dc01 --- /dev/null +++ b/msp430/msp430fr2476_symbols.ld @@ -0,0 +1,1045 @@ +/* ============================================================================ */ +/* Copyright (c) 2021, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports MSP430FR2476 devices. */ + +/* 1.212 */ + +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ + + +/***************************************************************************** + ADC +*****************************************************************************/ +PROVIDE(ADCCTL0 = 0x0700); +PROVIDE(ADCCTL0_L = 0x0700); +PROVIDE(ADCCTL0_H = 0x0701); +PROVIDE(ADCCTL1 = 0x0702); +PROVIDE(ADCCTL1_L = 0x0702); +PROVIDE(ADCCTL1_H = 0x0703); +PROVIDE(ADCCTL2 = 0x0704); +PROVIDE(ADCCTL2_L = 0x0704); +PROVIDE(ADCCTL2_H = 0x0705); +PROVIDE(ADCLO = 0x0706); +PROVIDE(ADCLO_L = 0x0706); +PROVIDE(ADCLO_H = 0x0707); +PROVIDE(ADCHI = 0x0708); +PROVIDE(ADCHI_L = 0x0708); +PROVIDE(ADCHI_H = 0x0709); +PROVIDE(ADCMCTL0 = 0x070A); +PROVIDE(ADCMCTL0_L = 0x070A); +PROVIDE(ADCMCTL0_H = 0x070B); +PROVIDE(ADCMEM0 = 0x0712); +PROVIDE(ADCMEM0_L = 0x0712); +PROVIDE(ADCMEM0_H = 0x0713); +PROVIDE(ADCIE = 0x071A); +PROVIDE(ADCIE_L = 0x071A); +PROVIDE(ADCIE_H = 0x071B); +PROVIDE(ADCIFG = 0x071C); +PROVIDE(ADCIFG_L = 0x071C); +PROVIDE(ADCIFG_H = 0x071D); +PROVIDE(ADCIV = 0x071E); +PROVIDE(ADCIV_L = 0x071E); +PROVIDE(ADCIV_H = 0x071F); + + +/***************************************************************************** + BKMEM +*****************************************************************************/ +PROVIDE(BAKMEM0 = 0x0660); +PROVIDE(BAKMEM0_L = 0x0660); +PROVIDE(BAKMEM0_H = 0x0661); +PROVIDE(BAKMEM1 = 0x0662); +PROVIDE(BAKMEM1_L = 0x0662); +PROVIDE(BAKMEM1_H = 0x0663); +PROVIDE(BAKMEM2 = 0x0664); +PROVIDE(BAKMEM2_L = 0x0664); +PROVIDE(BAKMEM2_H = 0x0665); +PROVIDE(BAKMEM3 = 0x0666); +PROVIDE(BAKMEM3_L = 0x0666); +PROVIDE(BAKMEM3_H = 0x0667); +PROVIDE(BAKMEM4 = 0x0668); +PROVIDE(BAKMEM4_L = 0x0668); +PROVIDE(BAKMEM4_H = 0x0669); +PROVIDE(BAKMEM5 = 0x066A); +PROVIDE(BAKMEM5_L = 0x066A); +PROVIDE(BAKMEM5_H = 0x066B); +PROVIDE(BAKMEM6 = 0x066C); +PROVIDE(BAKMEM6_L = 0x066C); +PROVIDE(BAKMEM6_H = 0x066D); +PROVIDE(BAKMEM7 = 0x066E); +PROVIDE(BAKMEM7_L = 0x066E); +PROVIDE(BAKMEM7_H = 0x066F); +PROVIDE(BAKMEM8 = 0x0670); +PROVIDE(BAKMEM8_L = 0x0670); +PROVIDE(BAKMEM8_H = 0x0671); +PROVIDE(BAKMEM9 = 0x0672); +PROVIDE(BAKMEM9_L = 0x0672); +PROVIDE(BAKMEM9_H = 0x0673); +PROVIDE(BAKMEM10 = 0x0674); +PROVIDE(BAKMEM10_L = 0x0674); +PROVIDE(BAKMEM10_H = 0x0675); +PROVIDE(BAKMEM11 = 0x0676); +PROVIDE(BAKMEM11_L = 0x0676); +PROVIDE(BAKMEM11_H = 0x0677); +PROVIDE(BAKMEM12 = 0x0678); +PROVIDE(BAKMEM12_L = 0x0678); +PROVIDE(BAKMEM12_H = 0x0679); +PROVIDE(BAKMEM13 = 0x067A); +PROVIDE(BAKMEM13_L = 0x067A); +PROVIDE(BAKMEM13_H = 0x067B); +PROVIDE(BAKMEM14 = 0x067C); +PROVIDE(BAKMEM14_L = 0x067C); +PROVIDE(BAKMEM14_H = 0x067D); +PROVIDE(BAKMEM15 = 0x067E); +PROVIDE(BAKMEM15_L = 0x067E); +PROVIDE(BAKMEM15_H = 0x067F); + + +/***************************************************************************** + CRC +*****************************************************************************/ +PROVIDE(CRCDI = 0x01C0); +PROVIDE(CRCDI_L = 0x01C0); +PROVIDE(CRCDI_H = 0x01C1); +PROVIDE(CRCDIRB = 0x01C2); +PROVIDE(CRCDIRB_L = 0x01C2); +PROVIDE(CRCDIRB_H = 0x01C3); +PROVIDE(CRCINIRES = 0x01C4); +PROVIDE(CRCINIRES_L = 0x01C4); +PROVIDE(CRCINIRES_H = 0x01C5); +PROVIDE(CRCRESR = 0x01C6); +PROVIDE(CRCRESR_L = 0x01C6); +PROVIDE(CRCRESR_H = 0x01C7); + + +/***************************************************************************** + CS +*****************************************************************************/ +PROVIDE(CSCTL0 = 0x0180); +PROVIDE(CSCTL0_L = 0x0180); +PROVIDE(CSCTL0_H = 0x0181); +PROVIDE(CSCTL1 = 0x0182); +PROVIDE(CSCTL1_L = 0x0182); +PROVIDE(CSCTL1_H = 0x0183); +PROVIDE(CSCTL2 = 0x0184); +PROVIDE(CSCTL2_L = 0x0184); +PROVIDE(CSCTL2_H = 0x0185); +PROVIDE(CSCTL3 = 0x0186); +PROVIDE(CSCTL3_L = 0x0186); +PROVIDE(CSCTL3_H = 0x0187); +PROVIDE(CSCTL4 = 0x0188); +PROVIDE(CSCTL4_L = 0x0188); +PROVIDE(CSCTL4_H = 0x0189); +PROVIDE(CSCTL5 = 0x018A); +PROVIDE(CSCTL5_L = 0x018A); +PROVIDE(CSCTL5_H = 0x018B); +PROVIDE(CSCTL6 = 0x018C); +PROVIDE(CSCTL6_L = 0x018C); +PROVIDE(CSCTL6_H = 0x018D); +PROVIDE(CSCTL7 = 0x018E); +PROVIDE(CSCTL7_L = 0x018E); +PROVIDE(CSCTL7_H = 0x018F); +PROVIDE(CSCTL8 = 0x0190); +PROVIDE(CSCTL8_L = 0x0190); +PROVIDE(CSCTL8_H = 0x0191); + + +/***************************************************************************** + DIO +*****************************************************************************/ +PROVIDE(PAIN = 0x0200); +PROVIDE(PAIN_L = 0x0200); +PROVIDE(PAIN_H = 0x0201); +PROVIDE(PAOUT = 0x0202); +PROVIDE(PAOUT_L = 0x0202); +PROVIDE(PAOUT_H = 0x0203); +PROVIDE(PADIR = 0x0204); +PROVIDE(PADIR_L = 0x0204); +PROVIDE(PADIR_H = 0x0205); +PROVIDE(PAREN = 0x0206); +PROVIDE(PAREN_L = 0x0206); +PROVIDE(PAREN_H = 0x0207); +PROVIDE(PASEL0 = 0x020A); +PROVIDE(PASEL0_L = 0x020A); +PROVIDE(PASEL0_H = 0x020B); +PROVIDE(PASEL1 = 0x020C); +PROVIDE(PASEL1_L = 0x020C); +PROVIDE(PASEL1_H = 0x020D); +PROVIDE(P1IV = 0x020E); +PROVIDE(P1IV_L = 0x020E); +PROVIDE(P1IV_H = 0x020F); +PROVIDE(PASELC = 0x0216); +PROVIDE(PASELC_L = 0x0216); +PROVIDE(PASELC_H = 0x0217); +PROVIDE(PAIES = 0x0218); +PROVIDE(PAIES_L = 0x0218); +PROVIDE(PAIES_H = 0x0219); +PROVIDE(PAIE = 0x021A); +PROVIDE(PAIE_L = 0x021A); +PROVIDE(PAIE_H = 0x021B); +PROVIDE(PAIFG = 0x021C); +PROVIDE(PAIFG_L = 0x021C); +PROVIDE(PAIFG_H = 0x021D); +PROVIDE(P2IV = 0x021E); +PROVIDE(P2IV_L = 0x021E); +PROVIDE(P2IV_H = 0x021F); +PROVIDE(PBIN = 0x0220); +PROVIDE(PBIN_L = 0x0220); +PROVIDE(PBIN_H = 0x0221); +PROVIDE(PBOUT = 0x0222); +PROVIDE(PBOUT_L = 0x0222); +PROVIDE(PBOUT_H = 0x0223); +PROVIDE(PBDIR = 0x0224); +PROVIDE(PBDIR_L = 0x0224); +PROVIDE(PBDIR_H = 0x0225); +PROVIDE(PBREN = 0x0226); +PROVIDE(PBREN_L = 0x0226); +PROVIDE(PBREN_H = 0x0227); +PROVIDE(PBSEL0 = 0x022A); +PROVIDE(PBSEL0_L = 0x022A); +PROVIDE(PBSEL0_H = 0x022B); +PROVIDE(PBSEL1 = 0x022C); +PROVIDE(PBSEL1_L = 0x022C); +PROVIDE(PBSEL1_H = 0x022D); +PROVIDE(P3IV = 0x022E); +PROVIDE(P3IV_L = 0x022E); +PROVIDE(P3IV_H = 0x022F); +PROVIDE(PBSELC = 0x0236); +PROVIDE(PBSELC_L = 0x0236); +PROVIDE(PBSELC_H = 0x0237); +PROVIDE(PBIES = 0x0238); +PROVIDE(PBIES_L = 0x0238); +PROVIDE(PBIES_H = 0x0239); +PROVIDE(PBIE = 0x023A); +PROVIDE(PBIE_L = 0x023A); +PROVIDE(PBIE_H = 0x023B); +PROVIDE(PBIFG = 0x023C); +PROVIDE(PBIFG_L = 0x023C); +PROVIDE(PBIFG_H = 0x023D); +PROVIDE(P4IV = 0x023E); +PROVIDE(P4IV_L = 0x023E); +PROVIDE(P4IV_H = 0x023F); +PROVIDE(PCIN = 0x0240); +PROVIDE(PCIN_L = 0x0240); +PROVIDE(PCIN_H = 0x0241); +PROVIDE(PCOUT = 0x0242); +PROVIDE(PCOUT_L = 0x0242); +PROVIDE(PCOUT_H = 0x0243); +PROVIDE(PCDIR = 0x0244); +PROVIDE(PCDIR_L = 0x0244); +PROVIDE(PCDIR_H = 0x0245); +PROVIDE(PCREN = 0x0246); +PROVIDE(PCREN_L = 0x0246); +PROVIDE(PCREN_H = 0x0247); +PROVIDE(PCSEL0 = 0x024A); +PROVIDE(PCSEL0_L = 0x024A); +PROVIDE(PCSEL0_H = 0x024B); +PROVIDE(PCSEL1 = 0x024C); +PROVIDE(PCSEL1_L = 0x024C); +PROVIDE(PCSEL1_H = 0x024D); +PROVIDE(P5IV = 0x024E); +PROVIDE(P5IV_L = 0x024E); +PROVIDE(P5IV_H = 0x024F); +PROVIDE(PCSELC = 0x0256); +PROVIDE(PCSELC_L = 0x0256); +PROVIDE(PCSELC_H = 0x0257); +PROVIDE(PCIES = 0x0258); +PROVIDE(PCIES_L = 0x0258); +PROVIDE(PCIES_H = 0x0259); +PROVIDE(PCIE = 0x025A); +PROVIDE(PCIE_L = 0x025A); +PROVIDE(PCIE_H = 0x025B); +PROVIDE(PCIFG = 0x025C); +PROVIDE(PCIFG_L = 0x025C); +PROVIDE(PCIFG_H = 0x025D); +PROVIDE(P6IV = 0x025E); +PROVIDE(P6IV_L = 0x025E); +PROVIDE(P6IV_H = 0x025F); +PROVIDE(PJIN = 0x0320); +PROVIDE(PJIN_L = 0x0320); +PROVIDE(PJIN_H = 0x0321); +PROVIDE(PJOUT = 0x0322); +PROVIDE(PJOUT_L = 0x0322); +PROVIDE(PJOUT_H = 0x0323); +PROVIDE(PJDIR = 0x0324); +PROVIDE(PJDIR_L = 0x0324); +PROVIDE(PJDIR_H = 0x0325); +PROVIDE(PJREN = 0x0326); +PROVIDE(PJREN_L = 0x0326); +PROVIDE(PJREN_H = 0x0327); +PROVIDE(PJSEL0 = 0x032A); +PROVIDE(PJSEL0_L = 0x032A); +PROVIDE(PJSEL0_H = 0x032B); +PROVIDE(PJSEL1 = 0x032C); +PROVIDE(PJSEL1_L = 0x032C); +PROVIDE(PJSEL1_H = 0x032D); +PROVIDE(PJSELC = 0x0336); +PROVIDE(PJSELC_L = 0x0336); +PROVIDE(PJSELC_H = 0x0337); +PROVIDE(P1IN = 0x0200); + +PROVIDE(P2IN = 0x0201); + +PROVIDE(P2OUT = 0x0203); + +PROVIDE(P1OUT = 0x0202); + +PROVIDE(P1DIR = 0x0204); + +PROVIDE(P2DIR = 0x0205); + +PROVIDE(P1REN = 0x0206); + +PROVIDE(P2REN = 0x0207); + +PROVIDE(P1SEL0 = 0x020A); + +PROVIDE(P2SEL0 = 0x020B); + +PROVIDE(P1SEL1 = 0x020C); + +PROVIDE(P2SEL1 = 0x020D); + +PROVIDE(P1SELC = 0x0216); + +PROVIDE(P2SELC = 0x0217); + +PROVIDE(P1IES = 0x0218); + +PROVIDE(P2IES = 0x0219); + +PROVIDE(P1IE = 0x021A); + +PROVIDE(P2IE = 0x021B); + +PROVIDE(P1IFG = 0x021C); + +PROVIDE(P2IFG = 0x021D); + +PROVIDE(P3IN = 0x0220); + +PROVIDE(P4IN = 0x0221); + +PROVIDE(P3OUT = 0x0222); + +PROVIDE(P4OUT = 0x0223); + +PROVIDE(P3DIR = 0x0224); + +PROVIDE(P4DIR = 0x0225); + +PROVIDE(P3REN = 0x0226); + +PROVIDE(P4REN = 0x0227); + +PROVIDE(P4SEL0 = 0x022B); + +PROVIDE(P3SEL0 = 0x022A); + +PROVIDE(P3SEL1 = 0x022C); + +PROVIDE(P4SEL1 = 0x022D); + +PROVIDE(P3SELC = 0x0236); + +PROVIDE(P4SELC = 0x0237); + +PROVIDE(P3IES = 0x0238); + +PROVIDE(P4IES = 0x0239); + +PROVIDE(P3IE = 0x023A); + +PROVIDE(P4IE = 0x023B); + +PROVIDE(P3IFG = 0x023C); + +PROVIDE(P4IFG = 0x023D); + +PROVIDE(P5IN = 0x0240); + +PROVIDE(P6IN = 0x0241); + +PROVIDE(P5OUT = 0x0242); + +PROVIDE(P6OUT = 0x0243); + +PROVIDE(P5DIR = 0x0244); + +PROVIDE(P6DIR = 0x0245); + +PROVIDE(P5REN = 0x0246); + +PROVIDE(P6REN = 0x0247); + +PROVIDE(P5SEL0 = 0x024A); + +PROVIDE(P6SEL0 = 0x024B); + +PROVIDE(P5SEL1 = 0x024C); + +PROVIDE(P6SEL1 = 0x024D); + +PROVIDE(P5SELC = 0x0256); + +PROVIDE(P6SELC = 0x0257); + +PROVIDE(P5IES = 0x0258); + +PROVIDE(P6IES = 0x0259); + +PROVIDE(P5IE = 0x025A); + +PROVIDE(P6IE = 0x025B); + +PROVIDE(P5IFG = 0x025C); + +PROVIDE(P6IFG = 0x025D); + + + +/***************************************************************************** + FRCTL +*****************************************************************************/ +PROVIDE(FRCTL0 = 0x01A0); +PROVIDE(FRCTL0_L = 0x01A0); +PROVIDE(FRCTL0_H = 0x01A1); +PROVIDE(GCCTL0 = 0x01A4); +PROVIDE(GCCTL0_L = 0x01A4); +PROVIDE(GCCTL0_H = 0x01A5); +PROVIDE(GCCTL1 = 0x01A6); +PROVIDE(GCCTL1_L = 0x01A6); +PROVIDE(GCCTL1_H = 0x01A7); + + +/***************************************************************************** + MPY32 +*****************************************************************************/ +PROVIDE(MPY = 0x04C0); +PROVIDE(MPY_L = 0x04C0); +PROVIDE(MPY_H = 0x04C1); +PROVIDE(MPYS = 0x04C2); +PROVIDE(MPYS_L = 0x04C2); +PROVIDE(MPYS_H = 0x04C3); +PROVIDE(MAC = 0x04C4); +PROVIDE(MAC_L = 0x04C4); +PROVIDE(MAC_H = 0x04C5); +PROVIDE(MACS = 0x04C6); +PROVIDE(MACS_L = 0x04C6); +PROVIDE(MACS_H = 0x04C7); +PROVIDE(OP2 = 0x04C8); +PROVIDE(OP2_L = 0x04C8); +PROVIDE(OP2_H = 0x04C9); +PROVIDE(RESLO = 0x04CA); +PROVIDE(RESLO_L = 0x04CA); +PROVIDE(RESLO_H = 0x04CB); +PROVIDE(RESHI = 0x04CC); +PROVIDE(RESHI_L = 0x04CC); +PROVIDE(RESHI_H = 0x04CD); +PROVIDE(SUMEXT = 0x04CE); +PROVIDE(SUMEXT_L = 0x04CE); +PROVIDE(SUMEXT_H = 0x04CF); +PROVIDE(MPY32L = 0x04D0); +PROVIDE(MPY32L_L = 0x04D0); +PROVIDE(MPY32L_H = 0x04D1); +PROVIDE(MPY32H = 0x04D2); +PROVIDE(MPY32H_L = 0x04D2); +PROVIDE(MPY32H_H = 0x04D3); +PROVIDE(MPYS32L = 0x04D4); +PROVIDE(MPYS32L_L = 0x04D4); +PROVIDE(MPYS32L_H = 0x04D5); +PROVIDE(MPYS32H = 0x04D6); +PROVIDE(MPYS32H_L = 0x04D6); +PROVIDE(MPYS32H_H = 0x04D7); +PROVIDE(MAC32L = 0x04D8); +PROVIDE(MAC32L_L = 0x04D8); +PROVIDE(MAC32L_H = 0x04D9); +PROVIDE(MAC32H = 0x04DA); +PROVIDE(MAC32H_L = 0x04DA); +PROVIDE(MAC32H_H = 0x04DB); +PROVIDE(MACS32L = 0x04DC); +PROVIDE(MACS32L_L = 0x04DC); +PROVIDE(MACS32L_H = 0x04DD); +PROVIDE(MACS32H = 0x04DE); +PROVIDE(MACS32H_L = 0x04DE); +PROVIDE(MACS32H_H = 0x04DF); +PROVIDE(OP2L = 0x04E0); +PROVIDE(OP2L_L = 0x04E0); +PROVIDE(OP2L_H = 0x04E1); +PROVIDE(OP2H = 0x04E2); +PROVIDE(OP2H_L = 0x04E2); +PROVIDE(OP2H_H = 0x04E3); +PROVIDE(RES0 = 0x04E4); +PROVIDE(RES0_L = 0x04E4); +PROVIDE(RES0_H = 0x04E5); +PROVIDE(RES1 = 0x04E6); +PROVIDE(RES1_L = 0x04E6); +PROVIDE(RES1_H = 0x04E7); +PROVIDE(RES2 = 0x04E8); +PROVIDE(RES2_L = 0x04E8); +PROVIDE(RES2_H = 0x04E9); +PROVIDE(RES3 = 0x04EA); +PROVIDE(RES3_L = 0x04EA); +PROVIDE(RES3_H = 0x04EB); +PROVIDE(MPY32CTL0 = 0x04EC); +PROVIDE(MPY32CTL0_L = 0x04EC); +PROVIDE(MPY32CTL0_H = 0x04ED); + + +/***************************************************************************** + PMM +*****************************************************************************/ +PROVIDE(PMMCTL0 = 0x0120); +PROVIDE(PMMCTL0_L = 0x0120); +PROVIDE(PMMCTL0_H = 0x0121); +PROVIDE(PMMCTL1 = 0x0122); +PROVIDE(PMMCTL1_L = 0x0122); +PROVIDE(PMMCTL1_H = 0x0123); +PROVIDE(PMMCTL2 = 0x0124); +PROVIDE(PMMCTL2_L = 0x0124); +PROVIDE(PMMCTL2_H = 0x0125); +PROVIDE(PMMIFG = 0x012A); +PROVIDE(PMMIFG_L = 0x012A); +PROVIDE(PMMIFG_H = 0x012B); +PROVIDE(PM5CTL0 = 0x0130); +PROVIDE(PM5CTL0_L = 0x0130); +PROVIDE(PM5CTL0_H = 0x0131); + + +/***************************************************************************** + RTC +*****************************************************************************/ +PROVIDE(RTCCTL = 0x0300); +PROVIDE(RTCCTL_L = 0x0300); +PROVIDE(RTCCTL_H = 0x0301); +PROVIDE(RTCIV = 0x0304); +PROVIDE(RTCIV_L = 0x0304); +PROVIDE(RTCIV_H = 0x0305); +PROVIDE(RTCMOD = 0x0308); +PROVIDE(RTCMOD_L = 0x0308); +PROVIDE(RTCMOD_H = 0x0309); +PROVIDE(RTCCNT = 0x030C); +PROVIDE(RTCCNT_L = 0x030C); +PROVIDE(RTCCNT_H = 0x030D); + + +/***************************************************************************** + SFR +*****************************************************************************/ +PROVIDE(SFRIE1 = 0x0100); +PROVIDE(SFRIE1_L = 0x0100); +PROVIDE(SFRIE1_H = 0x0101); +PROVIDE(SFRIFG1 = 0x0102); +PROVIDE(SFRIFG1_L = 0x0102); +PROVIDE(SFRIFG1_H = 0x0103); +PROVIDE(SFRRPCR = 0x0104); +PROVIDE(SFRRPCR_L = 0x0104); +PROVIDE(SFRRPCR_H = 0x0105); + + +/***************************************************************************** + SYS +*****************************************************************************/ +PROVIDE(SYSCTL = 0x0140); +PROVIDE(SYSCTL_L = 0x0140); +PROVIDE(SYSCTL_H = 0x0141); +PROVIDE(SYSBSLC = 0x0142); +PROVIDE(SYSBSLC_L = 0x0142); +PROVIDE(SYSBSLC_H = 0x0143); +PROVIDE(SYSJMBC = 0x0146); +PROVIDE(SYSJMBC_L = 0x0146); +PROVIDE(SYSJMBC_H = 0x0147); +PROVIDE(SYSJMBI0 = 0x0148); +PROVIDE(SYSJMBI0_L = 0x0148); +PROVIDE(SYSJMBI0_H = 0x0149); +PROVIDE(SYSJMBI1 = 0x014A); +PROVIDE(SYSJMBI1_L = 0x014A); +PROVIDE(SYSJMBI1_H = 0x014B); +PROVIDE(SYSJMBO0 = 0x014C); +PROVIDE(SYSJMBO0_L = 0x014C); +PROVIDE(SYSJMBO0_H = 0x014D); +PROVIDE(SYSJMBO1 = 0x014E); +PROVIDE(SYSJMBO1_L = 0x014E); +PROVIDE(SYSJMBO1_H = 0x014F); +PROVIDE(SYSUNIV = 0x015A); +PROVIDE(SYSUNIV_L = 0x015A); +PROVIDE(SYSUNIV_H = 0x015B); +PROVIDE(SYSSNIV = 0x015C); +PROVIDE(SYSSNIV_L = 0x015C); +PROVIDE(SYSSNIV_H = 0x015D); +PROVIDE(SYSRSTIV = 0x015E); +PROVIDE(SYSRSTIV_L = 0x015E); +PROVIDE(SYSRSTIV_H = 0x015F); +PROVIDE(SYSCFG0 = 0x0160); +PROVIDE(SYSCFG0_L = 0x0160); +PROVIDE(SYSCFG0_H = 0x0161); +PROVIDE(SYSCFG1 = 0x0162); +PROVIDE(SYSCFG1_L = 0x0162); +PROVIDE(SYSCFG1_H = 0x0163); +PROVIDE(SYSCFG2 = 0x0164); +PROVIDE(SYSCFG2_L = 0x0164); +PROVIDE(SYSCFG2_H = 0x0165); +PROVIDE(SYSCFG3 = 0x0166); +PROVIDE(SYSCFG3_L = 0x0166); +PROVIDE(SYSCFG3_H = 0x0167); + + +/***************************************************************************** + TA0 +*****************************************************************************/ +PROVIDE(TA0CTL = 0x0380); +PROVIDE(TA0CTL_L = 0x0380); +PROVIDE(TA0CTL_H = 0x0381); +PROVIDE(TA0CCTL0 = 0x0382); +PROVIDE(TA0CCTL0_L = 0x0382); +PROVIDE(TA0CCTL0_H = 0x0383); +PROVIDE(TA0CCTL1 = 0x0384); +PROVIDE(TA0CCTL1_L = 0x0384); +PROVIDE(TA0CCTL1_H = 0x0385); +PROVIDE(TA0CCTL2 = 0x0386); +PROVIDE(TA0CCTL2_L = 0x0386); +PROVIDE(TA0CCTL2_H = 0x0387); +PROVIDE(TA0R = 0x0390); +PROVIDE(TA0R_L = 0x0390); +PROVIDE(TA0R_H = 0x0391); +PROVIDE(TA0CCR0 = 0x0392); +PROVIDE(TA0CCR0_L = 0x0392); +PROVIDE(TA0CCR0_H = 0x0393); +PROVIDE(TA0CCR1 = 0x0394); +PROVIDE(TA0CCR1_L = 0x0394); +PROVIDE(TA0CCR1_H = 0x0395); +PROVIDE(TA0CCR2 = 0x0396); +PROVIDE(TA0CCR2_L = 0x0396); +PROVIDE(TA0CCR2_H = 0x0397); +PROVIDE(TA0EX0 = 0x03A0); +PROVIDE(TA0EX0_L = 0x03A0); +PROVIDE(TA0EX0_H = 0x03A1); +PROVIDE(TA0IV = 0x03AE); +PROVIDE(TA0IV_L = 0x03AE); +PROVIDE(TA0IV_H = 0x03AF); + + +/***************************************************************************** + TA1 +*****************************************************************************/ +PROVIDE(TA1CTL = 0x03C0); +PROVIDE(TA1CTL_L = 0x03C0); +PROVIDE(TA1CTL_H = 0x03C1); +PROVIDE(TA1CCTL0 = 0x03C2); +PROVIDE(TA1CCTL0_L = 0x03C2); +PROVIDE(TA1CCTL0_H = 0x03C3); +PROVIDE(TA1CCTL1 = 0x03C4); +PROVIDE(TA1CCTL1_L = 0x03C4); +PROVIDE(TA1CCTL1_H = 0x03C5); +PROVIDE(TA1CCTL2 = 0x03C6); +PROVIDE(TA1CCTL2_L = 0x03C6); +PROVIDE(TA1CCTL2_H = 0x03C7); +PROVIDE(TA1R = 0x03D0); +PROVIDE(TA1R_L = 0x03D0); +PROVIDE(TA1R_H = 0x03D1); +PROVIDE(TA1CCR0 = 0x03D2); +PROVIDE(TA1CCR0_L = 0x03D2); +PROVIDE(TA1CCR0_H = 0x03D3); +PROVIDE(TA1CCR1 = 0x03D4); +PROVIDE(TA1CCR1_L = 0x03D4); +PROVIDE(TA1CCR1_H = 0x03D5); +PROVIDE(TA1CCR2 = 0x03D6); +PROVIDE(TA1CCR2_L = 0x03D6); +PROVIDE(TA1CCR2_H = 0x03D7); +PROVIDE(TA1EX0 = 0x03E0); +PROVIDE(TA1EX0_L = 0x03E0); +PROVIDE(TA1EX0_H = 0x03E1); +PROVIDE(TA1IV = 0x03EE); +PROVIDE(TA1IV_L = 0x03EE); +PROVIDE(TA1IV_H = 0x03EF); + + +/***************************************************************************** + TA2 +*****************************************************************************/ +PROVIDE(TA2CTL = 0x0400); +PROVIDE(TA2CTL_L = 0x0400); +PROVIDE(TA2CTL_H = 0x0401); +PROVIDE(TA2CCTL0 = 0x0402); +PROVIDE(TA2CCTL0_L = 0x0402); +PROVIDE(TA2CCTL0_H = 0x0403); +PROVIDE(TA2CCTL1 = 0x0404); +PROVIDE(TA2CCTL1_L = 0x0404); +PROVIDE(TA2CCTL1_H = 0x0405); +PROVIDE(TA2CCTL2 = 0x0406); +PROVIDE(TA2CCTL2_L = 0x0406); +PROVIDE(TA2CCTL2_H = 0x0407); +PROVIDE(TA2R = 0x0410); +PROVIDE(TA2R_L = 0x0410); +PROVIDE(TA2R_H = 0x0411); +PROVIDE(TA2CCR0 = 0x0412); +PROVIDE(TA2CCR0_L = 0x0412); +PROVIDE(TA2CCR0_H = 0x0413); +PROVIDE(TA2CCR1 = 0x0414); +PROVIDE(TA2CCR1_L = 0x0414); +PROVIDE(TA2CCR1_H = 0x0415); +PROVIDE(TA2CCR2 = 0x0416); +PROVIDE(TA2CCR2_L = 0x0416); +PROVIDE(TA2CCR2_H = 0x0417); +PROVIDE(TA2EX0 = 0x0420); +PROVIDE(TA2EX0_L = 0x0420); +PROVIDE(TA2EX0_H = 0x0421); +PROVIDE(TA2IV = 0x042E); +PROVIDE(TA2IV_L = 0x042E); +PROVIDE(TA2IV_H = 0x042F); + + +/***************************************************************************** + TA3 +*****************************************************************************/ +PROVIDE(TA3CTL = 0x0440); +PROVIDE(TA3CTL_L = 0x0440); +PROVIDE(TA3CTL_H = 0x0441); +PROVIDE(TA3CCTL0 = 0x0442); +PROVIDE(TA3CCTL0_L = 0x0442); +PROVIDE(TA3CCTL0_H = 0x0443); +PROVIDE(TA3CCTL1 = 0x0444); +PROVIDE(TA3CCTL1_L = 0x0444); +PROVIDE(TA3CCTL1_H = 0x0445); +PROVIDE(TA3CCTL2 = 0x0446); +PROVIDE(TA3CCTL2_L = 0x0446); +PROVIDE(TA3CCTL2_H = 0x0447); +PROVIDE(TA3R = 0x0450); +PROVIDE(TA3R_L = 0x0450); +PROVIDE(TA3R_H = 0x0451); +PROVIDE(TA3CCR0 = 0x0452); +PROVIDE(TA3CCR0_L = 0x0452); +PROVIDE(TA3CCR0_H = 0x0453); +PROVIDE(TA3CCR1 = 0x0454); +PROVIDE(TA3CCR1_L = 0x0454); +PROVIDE(TA3CCR1_H = 0x0455); +PROVIDE(TA3CCR2 = 0x0456); +PROVIDE(TA3CCR2_L = 0x0456); +PROVIDE(TA3CCR2_H = 0x0457); +PROVIDE(TA3EX0 = 0x0460); +PROVIDE(TA3EX0_L = 0x0460); +PROVIDE(TA3EX0_H = 0x0461); +PROVIDE(TA3IV = 0x046E); +PROVIDE(TA3IV_L = 0x046E); +PROVIDE(TA3IV_H = 0x046F); + + +/***************************************************************************** + TB0 +*****************************************************************************/ +PROVIDE(TB0CTL = 0x0480); +PROVIDE(TB0CTL_L = 0x0480); +PROVIDE(TB0CTL_H = 0x0481); +PROVIDE(TB0CCTL0 = 0x0482); +PROVIDE(TB0CCTL0_L = 0x0482); +PROVIDE(TB0CCTL0_H = 0x0483); +PROVIDE(TB0CCTL1 = 0x0484); +PROVIDE(TB0CCTL1_L = 0x0484); +PROVIDE(TB0CCTL1_H = 0x0485); +PROVIDE(TB0CCTL2 = 0x0486); +PROVIDE(TB0CCTL2_L = 0x0486); +PROVIDE(TB0CCTL2_H = 0x0487); +PROVIDE(TB0CCTL3 = 0x0488); +PROVIDE(TB0CCTL3_L = 0x0488); +PROVIDE(TB0CCTL3_H = 0x0489); +PROVIDE(TB0CCTL4 = 0x048A); +PROVIDE(TB0CCTL4_L = 0x048A); +PROVIDE(TB0CCTL4_H = 0x048B); +PROVIDE(TB0CCTL5 = 0x048C); +PROVIDE(TB0CCTL5_L = 0x048C); +PROVIDE(TB0CCTL5_H = 0x048D); +PROVIDE(TB0CCTL6 = 0x048E); +PROVIDE(TB0CCTL6_L = 0x048E); +PROVIDE(TB0CCTL6_H = 0x048F); +PROVIDE(TB0R = 0x0490); +PROVIDE(TB0R_L = 0x0490); +PROVIDE(TB0R_H = 0x0491); +PROVIDE(TB0CCR0 = 0x0492); +PROVIDE(TB0CCR0_L = 0x0492); +PROVIDE(TB0CCR0_H = 0x0493); +PROVIDE(TB0CCR1 = 0x0494); +PROVIDE(TB0CCR1_L = 0x0494); +PROVIDE(TB0CCR1_H = 0x0495); +PROVIDE(TB0CCR2 = 0x0496); +PROVIDE(TB0CCR2_L = 0x0496); +PROVIDE(TB0CCR2_H = 0x0497); +PROVIDE(TB0CCR3 = 0x0498); +PROVIDE(TB0CCR3_L = 0x0498); +PROVIDE(TB0CCR3_H = 0x0499); +PROVIDE(TB0CCR4 = 0x049A); +PROVIDE(TB0CCR4_L = 0x049A); +PROVIDE(TB0CCR4_H = 0x049B); +PROVIDE(TB0CCR5 = 0x049C); +PROVIDE(TB0CCR5_L = 0x049C); +PROVIDE(TB0CCR5_H = 0x049D); +PROVIDE(TB0CCR6 = 0x049E); +PROVIDE(TB0CCR6_L = 0x049E); +PROVIDE(TB0CCR6_H = 0x049F); +PROVIDE(TB0EX0 = 0x04A0); +PROVIDE(TB0EX0_L = 0x04A0); +PROVIDE(TB0EX0_H = 0x04A1); +PROVIDE(TB0IV = 0x04AE); +PROVIDE(TB0IV_L = 0x04AE); +PROVIDE(TB0IV_H = 0x04AF); + + +/***************************************************************************** + WDT_A +*****************************************************************************/ +PROVIDE(WDTCTL = 0x01CC); +PROVIDE(WDTCTL_L = 0x01CC); +PROVIDE(WDTCTL_H = 0x01CD); + + +/***************************************************************************** + eCOMP0 +*****************************************************************************/ +PROVIDE(CP0CTL0 = 0x08E0); +PROVIDE(CP0CTL0_L = 0x08E0); +PROVIDE(CP0CTL0_H = 0x08E1); +PROVIDE(CP0CTL1 = 0x08E2); +PROVIDE(CP0CTL1_L = 0x08E2); +PROVIDE(CP0CTL1_H = 0x08E3); +PROVIDE(CP0INT = 0x08E6); +PROVIDE(CP0INT_L = 0x08E6); +PROVIDE(CP0INT_H = 0x08E7); +PROVIDE(CP0IV = 0x08E8); +PROVIDE(CP0IV_L = 0x08E8); +PROVIDE(CP0IV_H = 0x08E9); +PROVIDE(CP0DACCTL = 0x08F0); +PROVIDE(CP0DACCTL_L = 0x08F0); +PROVIDE(CP0DACCTL_H = 0x08F1); +PROVIDE(CP0DACDATA = 0x08F2); +PROVIDE(CP0DACDATA_L = 0x08F2); +PROVIDE(CP0DACDATA_H = 0x08F3); + + +/***************************************************************************** + eUSCI_A0 +*****************************************************************************/ +PROVIDE(UCA0CTLW0 = 0x0500); +PROVIDE(UCA0CTLW0_L = 0x0500); +PROVIDE(UCA0CTLW0_H = 0x0501); +PROVIDE(UCA0CTLW1 = 0x0502); +PROVIDE(UCA0CTLW1_L = 0x0502); +PROVIDE(UCA0CTLW1_H = 0x0503); +PROVIDE(UCA0BRW = 0x0506); +PROVIDE(UCA0BRW_L = 0x0506); +PROVIDE(UCA0BRW_H = 0x0507); +PROVIDE(UCA0MCTLW = 0x0508); +PROVIDE(UCA0MCTLW_L = 0x0508); +PROVIDE(UCA0MCTLW_H = 0x0509); +PROVIDE(UCA0STATW = 0x050A); +PROVIDE(UCA0STATW_L = 0x050A); +PROVIDE(UCA0STATW_H = 0x050B); +PROVIDE(UCA0RXBUF = 0x050C); +PROVIDE(UCA0RXBUF_L = 0x050C); +PROVIDE(UCA0RXBUF_H = 0x050D); +PROVIDE(UCA0TXBUF = 0x050E); +PROVIDE(UCA0TXBUF_L = 0x050E); +PROVIDE(UCA0TXBUF_H = 0x050F); +PROVIDE(UCA0ABCTL = 0x0510); +PROVIDE(UCA0ABCTL_L = 0x0510); +PROVIDE(UCA0ABCTL_H = 0x0511); +PROVIDE(UCA0IRCTL = 0x0512); +PROVIDE(UCA0IRCTL_L = 0x0512); +PROVIDE(UCA0IRCTL_H = 0x0513); +PROVIDE(UCA0IE = 0x051A); +PROVIDE(UCA0IE_L = 0x051A); +PROVIDE(UCA0IE_H = 0x051B); +PROVIDE(UCA0IFG = 0x051C); +PROVIDE(UCA0IFG_L = 0x051C); +PROVIDE(UCA0IFG_H = 0x051D); +PROVIDE(UCA0IV = 0x051E); +PROVIDE(UCA0IV_L = 0x051E); +PROVIDE(UCA0IV_H = 0x051F); + + +/***************************************************************************** + eUSCI_A1 +*****************************************************************************/ +PROVIDE(UCA1CTLW0 = 0x0520); +PROVIDE(UCA1CTLW0_L = 0x0520); +PROVIDE(UCA1CTLW0_H = 0x0521); +PROVIDE(UCA1CTLW1 = 0x0522); +PROVIDE(UCA1CTLW1_L = 0x0522); +PROVIDE(UCA1CTLW1_H = 0x0523); +PROVIDE(UCA1BRW = 0x0526); +PROVIDE(UCA1BRW_L = 0x0526); +PROVIDE(UCA1BRW_H = 0x0527); +PROVIDE(UCA1MCTLW = 0x0528); +PROVIDE(UCA1MCTLW_L = 0x0528); +PROVIDE(UCA1MCTLW_H = 0x0529); +PROVIDE(UCA1STATW = 0x052A); +PROVIDE(UCA1STATW_L = 0x052A); +PROVIDE(UCA1STATW_H = 0x052B); +PROVIDE(UCA1RXBUF = 0x052C); +PROVIDE(UCA1RXBUF_L = 0x052C); +PROVIDE(UCA1RXBUF_H = 0x052D); +PROVIDE(UCA1TXBUF = 0x052E); +PROVIDE(UCA1TXBUF_L = 0x052E); +PROVIDE(UCA1TXBUF_H = 0x052F); +PROVIDE(UCA1ABCTL = 0x0530); +PROVIDE(UCA1ABCTL_L = 0x0530); +PROVIDE(UCA1ABCTL_H = 0x0531); +PROVIDE(UCA1IRCTL = 0x0532); +PROVIDE(UCA1IRCTL_L = 0x0532); +PROVIDE(UCA1IRCTL_H = 0x0533); +PROVIDE(UCA1IE = 0x053A); +PROVIDE(UCA1IE_L = 0x053A); +PROVIDE(UCA1IE_H = 0x053B); +PROVIDE(UCA1IFG = 0x053C); +PROVIDE(UCA1IFG_L = 0x053C); +PROVIDE(UCA1IFG_H = 0x053D); +PROVIDE(UCA1IV = 0x053E); +PROVIDE(UCA1IV_L = 0x053E); +PROVIDE(UCA1IV_H = 0x053F); + + +/***************************************************************************** + eUSCI_B0 +*****************************************************************************/ +PROVIDE(UCB0CTLW0 = 0x0540); +PROVIDE(UCB0CTLW0_L = 0x0540); +PROVIDE(UCB0CTLW0_H = 0x0541); +PROVIDE(UCB0CTLW1 = 0x0542); +PROVIDE(UCB0CTLW1_L = 0x0542); +PROVIDE(UCB0CTLW1_H = 0x0543); +PROVIDE(UCB0BRW = 0x0546); +PROVIDE(UCB0BRW_L = 0x0546); +PROVIDE(UCB0BRW_H = 0x0547); +PROVIDE(UCB0STATW = 0x0548); +PROVIDE(UCB0STATW_L = 0x0548); +PROVIDE(UCB0STATW_H = 0x0549); +PROVIDE(UCB0TBCNT = 0x054A); +PROVIDE(UCB0TBCNT_L = 0x054A); +PROVIDE(UCB0TBCNT_H = 0x054B); +PROVIDE(UCB0RXBUF = 0x054C); +PROVIDE(UCB0RXBUF_L = 0x054C); +PROVIDE(UCB0RXBUF_H = 0x054D); +PROVIDE(UCB0TXBUF = 0x054E); +PROVIDE(UCB0TXBUF_L = 0x054E); +PROVIDE(UCB0TXBUF_H = 0x054F); +PROVIDE(UCB0I2COA0 = 0x0554); +PROVIDE(UCB0I2COA0_L = 0x0554); +PROVIDE(UCB0I2COA0_H = 0x0555); +PROVIDE(UCB0I2COA1 = 0x0556); +PROVIDE(UCB0I2COA1_L = 0x0556); +PROVIDE(UCB0I2COA1_H = 0x0557); +PROVIDE(UCB0I2COA2 = 0x0558); +PROVIDE(UCB0I2COA2_L = 0x0558); +PROVIDE(UCB0I2COA2_H = 0x0559); +PROVIDE(UCB0I2COA3 = 0x055A); +PROVIDE(UCB0I2COA3_L = 0x055A); +PROVIDE(UCB0I2COA3_H = 0x055B); +PROVIDE(UCB0ADDRX = 0x055C); +PROVIDE(UCB0ADDRX_L = 0x055C); +PROVIDE(UCB0ADDRX_H = 0x055D); +PROVIDE(UCB0ADDMASK = 0x055E); +PROVIDE(UCB0ADDMASK_L = 0x055E); +PROVIDE(UCB0ADDMASK_H = 0x055F); +PROVIDE(UCB0I2CSA = 0x0560); +PROVIDE(UCB0I2CSA_L = 0x0560); +PROVIDE(UCB0I2CSA_H = 0x0561); +PROVIDE(UCB0IE = 0x056A); +PROVIDE(UCB0IE_L = 0x056A); +PROVIDE(UCB0IE_H = 0x056B); +PROVIDE(UCB0IFG = 0x056C); +PROVIDE(UCB0IFG_L = 0x056C); +PROVIDE(UCB0IFG_H = 0x056D); +PROVIDE(UCB0IV = 0x056E); +PROVIDE(UCB0IV_L = 0x056E); +PROVIDE(UCB0IV_H = 0x056F); + + +/***************************************************************************** + eUSCI_B1 +*****************************************************************************/ +PROVIDE(UCB1CTLW0 = 0x0580); +PROVIDE(UCB1CTLW0_L = 0x0580); +PROVIDE(UCB1CTLW0_H = 0x0581); +PROVIDE(UCB1CTLW1 = 0x0582); +PROVIDE(UCB1CTLW1_L = 0x0582); +PROVIDE(UCB1CTLW1_H = 0x0583); +PROVIDE(UCB1BRW = 0x0586); +PROVIDE(UCB1BRW_L = 0x0586); +PROVIDE(UCB1BRW_H = 0x0587); +PROVIDE(UCB1STATW = 0x0588); +PROVIDE(UCB1STATW_L = 0x0588); +PROVIDE(UCB1STATW_H = 0x0589); +PROVIDE(UCB1TBCNT = 0x058A); +PROVIDE(UCB1TBCNT_L = 0x058A); +PROVIDE(UCB1TBCNT_H = 0x058B); +PROVIDE(UCB1RXBUF = 0x058C); +PROVIDE(UCB1RXBUF_L = 0x058C); +PROVIDE(UCB1RXBUF_H = 0x058D); +PROVIDE(UCB1TXBUF = 0x058E); +PROVIDE(UCB1TXBUF_L = 0x058E); +PROVIDE(UCB1TXBUF_H = 0x058F); +PROVIDE(UCB1I2COA0 = 0x0594); +PROVIDE(UCB1I2COA0_L = 0x0594); +PROVIDE(UCB1I2COA0_H = 0x0595); +PROVIDE(UCB1I2COA1 = 0x0596); +PROVIDE(UCB1I2COA1_L = 0x0596); +PROVIDE(UCB1I2COA1_H = 0x0597); +PROVIDE(UCB1I2COA2 = 0x0598); +PROVIDE(UCB1I2COA2_L = 0x0598); +PROVIDE(UCB1I2COA2_H = 0x0599); +PROVIDE(UCB1I2COA3 = 0x059A); +PROVIDE(UCB1I2COA3_L = 0x059A); +PROVIDE(UCB1I2COA3_H = 0x059B); +PROVIDE(UCB1ADDRX = 0x059C); +PROVIDE(UCB1ADDRX_L = 0x059C); +PROVIDE(UCB1ADDRX_H = 0x059D); +PROVIDE(UCB1ADDMASK = 0x059E); +PROVIDE(UCB1ADDMASK_L = 0x059E); +PROVIDE(UCB1ADDMASK_H = 0x059F); +PROVIDE(UCB1I2CSA = 0x05A0); +PROVIDE(UCB1I2CSA_L = 0x05A0); +PROVIDE(UCB1I2CSA_H = 0x05A1); +PROVIDE(UCB1IE = 0x05AA); +PROVIDE(UCB1IE_L = 0x05AA); +PROVIDE(UCB1IE_H = 0x05AB); +PROVIDE(UCB1IFG = 0x05AC); +PROVIDE(UCB1IFG_L = 0x05AC); +PROVIDE(UCB1IFG_H = 0x05AD); +PROVIDE(UCB1IV = 0x05AE); +PROVIDE(UCB1IV_L = 0x05AE); +PROVIDE(UCB1IV_H = 0x05AF); + +/************************************************************ +* End of Modules +************************************************************/ +