diff --git a/Makefile b/Makefile index e54b3fb..beaea6b 100644 --- a/Makefile +++ b/Makefile @@ -12,10 +12,10 @@ all: alee msp430: CXX := msp430-elf-g++ msp430: AR := msp430-elf-gcc-ar -msp430: CXXFLAGS += -I. -msp430: CXXFLAGS += -Os -mmcu=msp430g2553 -ffunction-sections -fdata-sections -msp430: CXXFLAGS += -DMEMDICTSIZE=128 -flto -fno-asynchronous-unwind-tables -fno-threadsafe-statics -fno-stack-protector -msp430: LDFLAGS += -L/usr/msp430-elf/usr/include -Tmsp430/msp430g2553.ld -Wl,-gc-sections +msp430: CXXFLAGS += -I. -I/usr/msp430-elf/usr/include +msp430: CXXFLAGS += -Os -mmcu=msp430fr2476 -ffunction-sections -fdata-sections +msp430: CXXFLAGS += -DMEMDICTSIZE=1024 -flto -fno-asynchronous-unwind-tables -fno-threadsafe-statics -fno-stack-protector +msp430: LDFLAGS += -L/usr/msp430-elf/usr/include -Tmsp430/msp430fr2476.ld -Wl,-gc-sections msp430: clean-lib msp430/alee-msp430 msp430-prep: STANDALONE += forth/msp430.fth diff --git a/forth/msp430.fth b/forth/msp430.fth index 1497e04..9ba88bf 100644 --- a/forth/msp430.fth +++ b/forth/msp430.fth @@ -7,104 +7,836 @@ 16 base ! -: ie1 0000 ; -: ifg1 0002 ; -: ie2 0001 ; -: ifg2 0003 ; -: adc10dtc0 0048 ; -: adc10dtc1 0049 ; -: adc10ae0 004a ; -: adc10ctl0 01b0 ; -: adc10ctl1 01b2 ; -: adc10mem 01b4 ; -: adc10sa 01bc ; -: dcoctl 0056 ; -: bcsctl1 0057 ; -: bcsctl2 0058 ; -: bcsctl3 0053 ; -: cactl1 0059 ; -: cactl2 005a ; -: capd 005b ; -: fctl1 0128 ; -: fctl2 012a ; -: fctl3 012c ; -: p1in 0020 ; -: p1out 0021 ; -: p1dir 0022 ; -: p1ifg 0023 ; -: p1ies 0024 ; -: p1ie 0025 ; -: p1sel 0026 ; -: p1sel2 0041 ; -: p1ren 0027 ; -: p2in 0028 ; -: p2out 0029 ; -: p2dir 002a ; -: p2ifg 002b ; -: p2ies 002c ; -: p2ie 002d ; -: p2sel 002e ; -: p2sel2 0042 ; -: p2ren 002f ; -: p3in 0018 ; -: p3out 0019 ; -: p3dir 001a ; -: p3sel 001b ; -: p3sel2 0043 ; -: p3ren 0010 ; -: ta0iv 012e ; -: ta0ctl 0160 ; -: ta0cctl0 0162 ; -: ta0cctl1 0164 ; -: ta0cctl2 0166 ; -: ta0r 0170 ; -: ta0ccr0 0172 ; -: ta0ccr1 0174 ; -: ta0ccr2 0176 ; -: ta1iv 011e ; -: ta1ctl 0180 ; -: ta1cctl0 0182 ; -: ta1cctl1 0184 ; -: ta1cctl2 0186 ; -: ta1r 0190 ; -: ta1ccr0 0192 ; -: ta1ccr1 0194 ; -: ta1ccr2 0196 ; -: uca0ctl0 0060 ; -: uca0ctl1 0061 ; -: uca0br0 0062 ; -: uca0br1 0063 ; -: uca0mctl 0064 ; -: uca0stat 0065 ; -: uca0rxbuf 0066 ; -: uca0txbuf 0067 ; -: uca0abctl 005d ; -: uca0irtctl 005e ; -: uca0irrctl 005f ; -: ucb0ctl0 0068 ; -: ucb0ctl1 0069 ; -: ucb0br0 006a ; -: ucb0br1 006b ; -: ucb0i2cie 006c ; -: ucb0stat 006d ; -: ucb0rxbuf 006e ; -: ucb0txbuf 006f ; -: ucb0i2coa 0118 ; -: ucb0i2csa 011a ; -: wdtctl 0120 ; -: caldco_16mhz 10f8 ; -: calbc1_16mhz 10f9 ; -: caldco_12mhz 10fa ; -: calbc1_12mhz 10fb ; -: caldco_8mhz 10fc ; -: calbc1_8mhz 10fd ; -: caldco_1mhz 10fe ; -: calbc1_1mhz 10ff ; -: tlv_checksum 10c0 ; -: tlv_dco_30_tag 10f6 ; -: tlv_dco_30_len 10f7 ; -: tlv_adc10_1_tag 10da ; -: tlv_adc10_1_len 10db ; +: ADCCTL0 0700 ; +: ADCCTL0_L 0700 ; +: ADCCTL0_H 0701 ; +: ADCCTL1 0702 ; +: ADCCTL1_L 0702 ; +: ADCCTL1_H 0703 ; +: ADCCTL2 0704 ; +: ADCCTL2_L 0704 ; +: ADCCTL2_H 0705 ; +: ADCLO 0706 ; +: ADCLO_L 0706 ; +: ADCLO_H 0707 ; +: ADCHI 0708 ; +: ADCHI_L 0708 ; +: ADCHI_H 0709 ; +: ADCMCTL0 070A ; +: ADCMCTL0_L 070A ; +: ADCMCTL0_H 070B ; +: ADCMEM0 0712 ; +: ADCMEM0_L 0712 ; +: ADCMEM0_H 0713 ; +: ADCIE 071A ; +: ADCIE_L 071A ; +: ADCIE_H 071B ; +: ADCIFG 071C ; +: ADCIFG_L 071C ; +: ADCIFG_H 071D ; +: ADCIV 071E ; +: ADCIV_L 071E ; +: ADCIV_H 071F ; +: BAKMEM0 0660 ; +: BAKMEM0_L 0660 ; +: BAKMEM0_H 0661 ; +: BAKMEM1 0662 ; +: BAKMEM1_L 0662 ; +: BAKMEM1_H 0663 ; +: BAKMEM2 0664 ; +: BAKMEM2_L 0664 ; +: BAKMEM2_H 0665 ; +: BAKMEM3 0666 ; +: BAKMEM3_L 0666 ; +: BAKMEM3_H 0667 ; +: BAKMEM4 0668 ; +: BAKMEM4_L 0668 ; +: BAKMEM4_H 0669 ; +: BAKMEM5 066A ; +: BAKMEM5_L 066A ; +: BAKMEM5_H 066B ; +: BAKMEM6 066C ; +: BAKMEM6_L 066C ; +: BAKMEM6_H 066D ; +: BAKMEM7 066E ; +: BAKMEM7_L 066E ; +: BAKMEM7_H 066F ; +: BAKMEM8 0670 ; +: BAKMEM8_L 0670 ; +: BAKMEM8_H 0671 ; +: BAKMEM9 0672 ; +: BAKMEM9_L 0672 ; +: BAKMEM9_H 0673 ; +: BAKMEM10 0674 ; +: BAKMEM10_L 0674 ; +: BAKMEM10_H 0675 ; +: BAKMEM11 0676 ; +: BAKMEM11_L 0676 ; +: BAKMEM11_H 0677 ; +: BAKMEM12 0678 ; +: BAKMEM12_L 0678 ; +: BAKMEM12_H 0679 ; +: BAKMEM13 067A ; +: BAKMEM13_L 067A ; +: BAKMEM13_H 067B ; +: BAKMEM14 067C ; +: BAKMEM14_L 067C ; +: BAKMEM14_H 067D ; +: BAKMEM15 067E ; +: BAKMEM15_L 067E ; +: BAKMEM15_H 067F ; +: CRCDI 01C0 ; +: CRCDI_L 01C0 ; +: CRCDI_H 01C1 ; +: CRCDIRB 01C2 ; +: CRCDIRB_L 01C2 ; +: CRCDIRB_H 01C3 ; +: CRCINIRES 01C4 ; +: CRCINIRES_L 01C4 ; +: CRCINIRES_H 01C5 ; +: CRCRESR 01C6 ; +: CRCRESR_L 01C6 ; +: CRCRESR_H 01C7 ; +: CSCTL0 0180 ; +: CSCTL0_L 0180 ; +: CSCTL0_H 0181 ; +: CSCTL1 0182 ; +: CSCTL1_L 0182 ; +: CSCTL1_H 0183 ; +: CSCTL2 0184 ; +: CSCTL2_L 0184 ; +: CSCTL2_H 0185 ; +: CSCTL3 0186 ; +: CSCTL3_L 0186 ; +: CSCTL3_H 0187 ; +: CSCTL4 0188 ; +: CSCTL4_L 0188 ; +: CSCTL4_H 0189 ; +: CSCTL5 018A ; +: CSCTL5_L 018A ; +: CSCTL5_H 018B ; +: CSCTL6 018C ; +: CSCTL6_L 018C ; +: CSCTL6_H 018D ; +: CSCTL7 018E ; +: CSCTL7_L 018E ; +: CSCTL7_H 018F ; +: CSCTL8 0190 ; +: CSCTL8_L 0190 ; +: CSCTL8_H 0191 ; +: PAIN 0200 ; +: PAIN_L 0200 ; +: PAIN_H 0201 ; +: PAOUT 0202 ; +: PAOUT_L 0202 ; +: PAOUT_H 0203 ; +: PADIR 0204 ; +: PADIR_L 0204 ; +: PADIR_H 0205 ; +: PAREN 0206 ; +: PAREN_L 0206 ; +: PAREN_H 0207 ; +: PASEL0 020A ; +: PASEL0_L 020A ; +: PASEL0_H 020B ; +: PASEL1 020C ; +: PASEL1_L 020C ; +: PASEL1_H 020D ; +: P1IV 020E ; +: P1IV_L 020E ; +: P1IV_H 020F ; +: PASELC 0216 ; +: PASELC_L 0216 ; +: PASELC_H 0217 ; +: PAIES 0218 ; +: PAIES_L 0218 ; +: PAIES_H 0219 ; +: PAIE 021A ; +: PAIE_L 021A ; +: PAIE_H 021B ; +: PAIFG 021C ; +: PAIFG_L 021C ; +: PAIFG_H 021D ; +: P2IV 021E ; +: P2IV_L 021E ; +: P2IV_H 021F ; +: PBIN 0220 ; +: PBIN_L 0220 ; +: PBIN_H 0221 ; +: PBOUT 0222 ; +: PBOUT_L 0222 ; +: PBOUT_H 0223 ; +: PBDIR 0224 ; +: PBDIR_L 0224 ; +: PBDIR_H 0225 ; +: PBREN 0226 ; +: PBREN_L 0226 ; +: PBREN_H 0227 ; +: PBSEL0 022A ; +: PBSEL0_L 022A ; +: PBSEL0_H 022B ; +: PBSEL1 022C ; +: PBSEL1_L 022C ; +: PBSEL1_H 022D ; +: P3IV 022E ; +: P3IV_L 022E ; +: P3IV_H 022F ; +: PBSELC 0236 ; +: PBSELC_L 0236 ; +: PBSELC_H 0237 ; +: PBIES 0238 ; +: PBIES_L 0238 ; +: PBIES_H 0239 ; +: PBIE 023A ; +: PBIE_L 023A ; +: PBIE_H 023B ; +: PBIFG 023C ; +: PBIFG_L 023C ; +: PBIFG_H 023D ; +: P4IV 023E ; +: P4IV_L 023E ; +: P4IV_H 023F ; +: PCIN 0240 ; +: PCIN_L 0240 ; +: PCIN_H 0241 ; +: PCOUT 0242 ; +: PCOUT_L 0242 ; +: PCOUT_H 0243 ; +: PCDIR 0244 ; +: PCDIR_L 0244 ; +: PCDIR_H 0245 ; +: PCREN 0246 ; +: PCREN_L 0246 ; +: PCREN_H 0247 ; +: PCSEL0 024A ; +: PCSEL0_L 024A ; +: PCSEL0_H 024B ; +: PCSEL1 024C ; +: PCSEL1_L 024C ; +: PCSEL1_H 024D ; +: P5IV 024E ; +: P5IV_L 024E ; +: P5IV_H 024F ; +: PCSELC 0256 ; +: PCSELC_L 0256 ; +: PCSELC_H 0257 ; +: PCIES 0258 ; +: PCIES_L 0258 ; +: PCIES_H 0259 ; +: PCIE 025A ; +: PCIE_L 025A ; +: PCIE_H 025B ; +: PCIFG 025C ; +: PCIFG_L 025C ; +: PCIFG_H 025D ; +: P6IV 025E ; +: P6IV_L 025E ; +: P6IV_H 025F ; +: PJIN 0320 ; +: PJIN_L 0320 ; +: PJIN_H 0321 ; +: PJOUT 0322 ; +: PJOUT_L 0322 ; +: PJOUT_H 0323 ; +: PJDIR 0324 ; +: PJDIR_L 0324 ; +: PJDIR_H 0325 ; +: PJREN 0326 ; +: PJREN_L 0326 ; +: PJREN_H 0327 ; +: PJSEL0 032A ; +: PJSEL0_L 032A ; +: PJSEL0_H 032B ; +: PJSEL1 032C ; +: PJSEL1_L 032C ; +: PJSEL1_H 032D ; +: PJSELC 0336 ; +: PJSELC_L 0336 ; +: PJSELC_H 0337 ; +: P1IN 0200 ; +: P2IN 0201 ; +: P2OUT 0203 ; +: P1OUT 0202 ; +: P1DIR 0204 ; +: P2DIR 0205 ; +: P1REN 0206 ; +: P2REN 0207 ; +: P1SEL0 020A ; +: P2SEL0 020B ; +: P1SEL1 020C ; +: P2SEL1 020D ; +: P1SELC 0216 ; +: P2SELC 0217 ; +: P1IES 0218 ; +: P2IES 0219 ; +: P1IE 021A ; +: P2IE 021B ; +: P1IFG 021C ; +: P2IFG 021D ; +: P3IN 0220 ; +: P4IN 0221 ; +: P3OUT 0222 ; +: P4OUT 0223 ; +: P3DIR 0224 ; +: P4DIR 0225 ; +: P3REN 0226 ; +: P4REN 0227 ; +: P4SEL0 022B ; +: P3SEL0 022A ; +: P3SEL1 022C ; +: P4SEL1 022D ; +: P3SELC 0236 ; +: P4SELC 0237 ; +: P3IES 0238 ; +: P4IES 0239 ; +: P3IE 023A ; +: P4IE 023B ; +: P3IFG 023C ; +: P4IFG 023D ; +: P5IN 0240 ; +: P6IN 0241 ; +: P5OUT 0242 ; +: P6OUT 0243 ; +: P5DIR 0244 ; +: P6DIR 0245 ; +: P5REN 0246 ; +: P6REN 0247 ; +: P5SEL0 024A ; +: P6SEL0 024B ; +: P5SEL1 024C ; +: P6SEL1 024D ; +: P5SELC 0256 ; +: P6SELC 0257 ; +: P5IES 0258 ; +: P6IES 0259 ; +: P5IE 025A ; +: P6IE 025B ; +: P5IFG 025C ; +: P6IFG 025D ; +: FRCTL0 01A0 ; +: FRCTL0_L 01A0 ; +: FRCTL0_H 01A1 ; +: GCCTL0 01A4 ; +: GCCTL0_L 01A4 ; +: GCCTL0_H 01A5 ; +: GCCTL1 01A6 ; +: GCCTL1_L 01A6 ; +: GCCTL1_H 01A7 ; +: MPY 04C0 ; +: MPY_L 04C0 ; +: MPY_H 04C1 ; +: MPYS 04C2 ; +: MPYS_L 04C2 ; +: MPYS_H 04C3 ; +: MAC 04C4 ; +: MAC_L 04C4 ; +: MAC_H 04C5 ; +: MACS 04C6 ; +: MACS_L 04C6 ; +: MACS_H 04C7 ; +: OP2 04C8 ; +: OP2_L 04C8 ; +: OP2_H 04C9 ; +: RESLO 04CA ; +: RESLO_L 04CA ; +: RESLO_H 04CB ; +: RESHI 04CC ; +: RESHI_L 04CC ; +: RESHI_H 04CD ; +: SUMEXT 04CE ; +: SUMEXT_L 04CE ; +: SUMEXT_H 04CF ; +: MPY32L 04D0 ; +: MPY32L_L 04D0 ; +: MPY32L_H 04D1 ; +: MPY32H 04D2 ; +: MPY32H_L 04D2 ; +: MPY32H_H 04D3 ; +: MPYS32L 04D4 ; +: MPYS32L_L 04D4 ; +: MPYS32L_H 04D5 ; +: MPYS32H 04D6 ; +: MPYS32H_L 04D6 ; +: MPYS32H_H 04D7 ; +: MAC32L 04D8 ; +: MAC32L_L 04D8 ; +: MAC32L_H 04D9 ; +: MAC32H 04DA ; +: MAC32H_L 04DA ; +: MAC32H_H 04DB ; +: MACS32L 04DC ; +: MACS32L_L 04DC ; +: MACS32L_H 04DD ; +: MACS32H 04DE ; +: MACS32H_L 04DE ; +: MACS32H_H 04DF ; +: OP2L 04E0 ; +: OP2L_L 04E0 ; +: OP2L_H 04E1 ; +: OP2H 04E2 ; +: OP2H_L 04E2 ; +: OP2H_H 04E3 ; +: RES0 04E4 ; +: RES0_L 04E4 ; +: RES0_H 04E5 ; +: RES1 04E6 ; +: RES1_L 04E6 ; +: RES1_H 04E7 ; +: RES2 04E8 ; +: RES2_L 04E8 ; +: RES2_H 04E9 ; +: RES3 04EA ; +: RES3_L 04EA ; +: RES3_H 04EB ; +: MPY32CTL0 04EC ; +: MPY32CTL0_L 04EC ; +: MPY32CTL0_H 04ED ; +: PMMCTL0 0120 ; +: PMMCTL0_L 0120 ; +: PMMCTL0_H 0121 ; +: PMMCTL1 0122 ; +: PMMCTL1_L 0122 ; +: PMMCTL1_H 0123 ; +: PMMCTL2 0124 ; +: PMMCTL2_L 0124 ; +: PMMCTL2_H 0125 ; +: PMMIFG 012A ; +: PMMIFG_L 012A ; +: PMMIFG_H 012B ; +: PM5CTL0 0130 ; +: PM5CTL0_L 0130 ; +: PM5CTL0_H 0131 ; +: RTCCTL 0300 ; +: RTCCTL_L 0300 ; +: RTCCTL_H 0301 ; +: RTCIV 0304 ; +: RTCIV_L 0304 ; +: RTCIV_H 0305 ; +: RTCMOD 0308 ; +: RTCMOD_L 0308 ; +: RTCMOD_H 0309 ; +: RTCCNT 030C ; +: RTCCNT_L 030C ; +: RTCCNT_H 030D ; +: SFRIE1 0100 ; +: SFRIE1_L 0100 ; +: SFRIE1_H 0101 ; +: SFRIFG1 0102 ; +: SFRIFG1_L 0102 ; +: SFRIFG1_H 0103 ; +: SFRRPCR 0104 ; +: SFRRPCR_L 0104 ; +: SFRRPCR_H 0105 ; +: SYSCTL 0140 ; +: SYSCTL_L 0140 ; +: SYSCTL_H 0141 ; +: SYSBSLC 0142 ; +: SYSBSLC_L 0142 ; +: SYSBSLC_H 0143 ; +: SYSJMBC 0146 ; +: SYSJMBC_L 0146 ; +: SYSJMBC_H 0147 ; +: SYSJMBI0 0148 ; +: SYSJMBI0_L 0148 ; +: SYSJMBI0_H 0149 ; +: SYSJMBI1 014A ; +: SYSJMBI1_L 014A ; +: SYSJMBI1_H 014B ; +: SYSJMBO0 014C ; +: SYSJMBO0_L 014C ; +: SYSJMBO0_H 014D ; +: SYSJMBO1 014E ; +: SYSJMBO1_L 014E ; +: SYSJMBO1_H 014F ; +: SYSUNIV 015A ; +: SYSUNIV_L 015A ; +: SYSUNIV_H 015B ; +: SYSSNIV 015C ; +: SYSSNIV_L 015C ; +: SYSSNIV_H 015D ; +: SYSRSTIV 015E ; +: SYSRSTIV_L 015E ; +: SYSRSTIV_H 015F ; +: SYSCFG0 0160 ; +: SYSCFG0_L 0160 ; +: SYSCFG0_H 0161 ; +: SYSCFG1 0162 ; +: SYSCFG1_L 0162 ; +: SYSCFG1_H 0163 ; +: SYSCFG2 0164 ; +: SYSCFG2_L 0164 ; +: SYSCFG2_H 0165 ; +: SYSCFG3 0166 ; +: SYSCFG3_L 0166 ; +: SYSCFG3_H 0167 ; +: TA0CTL 0380 ; +: TA0CTL_L 0380 ; +: TA0CTL_H 0381 ; +: TA0CCTL0 0382 ; +: TA0CCTL0_L 0382 ; +: TA0CCTL0_H 0383 ; +: TA0CCTL1 0384 ; +: TA0CCTL1_L 0384 ; +: TA0CCTL1_H 0385 ; +: TA0CCTL2 0386 ; +: TA0CCTL2_L 0386 ; +: TA0CCTL2_H 0387 ; +: TA0R 0390 ; +: TA0R_L 0390 ; +: TA0R_H 0391 ; +: TA0CCR0 0392 ; +: TA0CCR0_L 0392 ; +: TA0CCR0_H 0393 ; +: TA0CCR1 0394 ; +: TA0CCR1_L 0394 ; +: TA0CCR1_H 0395 ; +: TA0CCR2 0396 ; +: TA0CCR2_L 0396 ; +: TA0CCR2_H 0397 ; +: TA0EX0 03A0 ; +: TA0EX0_L 03A0 ; +: TA0EX0_H 03A1 ; +: TA0IV 03AE ; +: TA0IV_L 03AE ; +: TA0IV_H 03AF ; +: TA1CTL 03C0 ; +: TA1CTL_L 03C0 ; +: TA1CTL_H 03C1 ; +: TA1CCTL0 03C2 ; +: TA1CCTL0_L 03C2 ; +: TA1CCTL0_H 03C3 ; +: TA1CCTL1 03C4 ; +: TA1CCTL1_L 03C4 ; +: TA1CCTL1_H 03C5 ; +: TA1CCTL2 03C6 ; +: TA1CCTL2_L 03C6 ; +: TA1CCTL2_H 03C7 ; +: TA1R 03D0 ; +: TA1R_L 03D0 ; +: TA1R_H 03D1 ; +: TA1CCR0 03D2 ; +: TA1CCR0_L 03D2 ; +: TA1CCR0_H 03D3 ; +: TA1CCR1 03D4 ; +: TA1CCR1_L 03D4 ; +: TA1CCR1_H 03D5 ; +: TA1CCR2 03D6 ; +: TA1CCR2_L 03D6 ; +: TA1CCR2_H 03D7 ; +: TA1EX0 03E0 ; +: TA1EX0_L 03E0 ; +: TA1EX0_H 03E1 ; +: TA1IV 03EE ; +: TA1IV_L 03EE ; +: TA1IV_H 03EF ; +: TA2CTL 0400 ; +: TA2CTL_L 0400 ; +: TA2CTL_H 0401 ; +: TA2CCTL0 0402 ; +: TA2CCTL0_L 0402 ; +: TA2CCTL0_H 0403 ; +: TA2CCTL1 0404 ; +: TA2CCTL1_L 0404 ; +: TA2CCTL1_H 0405 ; +: TA2CCTL2 0406 ; +: TA2CCTL2_L 0406 ; +: TA2CCTL2_H 0407 ; +: TA2R 0410 ; +: TA2R_L 0410 ; +: TA2R_H 0411 ; +: TA2CCR0 0412 ; +: TA2CCR0_L 0412 ; +: TA2CCR0_H 0413 ; +: TA2CCR1 0414 ; +: TA2CCR1_L 0414 ; +: TA2CCR1_H 0415 ; +: TA2CCR2 0416 ; +: TA2CCR2_L 0416 ; +: TA2CCR2_H 0417 ; +: TA2EX0 0420 ; +: TA2EX0_L 0420 ; +: TA2EX0_H 0421 ; +: TA2IV 042E ; +: TA2IV_L 042E ; +: TA2IV_H 042F ; +: TA3CTL 0440 ; +: TA3CTL_L 0440 ; +: TA3CTL_H 0441 ; +: TA3CCTL0 0442 ; +: TA3CCTL0_L 0442 ; +: TA3CCTL0_H 0443 ; +: TA3CCTL1 0444 ; +: TA3CCTL1_L 0444 ; +: TA3CCTL1_H 0445 ; +: TA3CCTL2 0446 ; +: TA3CCTL2_L 0446 ; +: TA3CCTL2_H 0447 ; +: TA3R 0450 ; +: TA3R_L 0450 ; +: TA3R_H 0451 ; +: TA3CCR0 0452 ; +: TA3CCR0_L 0452 ; +: TA3CCR0_H 0453 ; +: TA3CCR1 0454 ; +: TA3CCR1_L 0454 ; +: TA3CCR1_H 0455 ; +: TA3CCR2 0456 ; +: TA3CCR2_L 0456 ; +: TA3CCR2_H 0457 ; +: TA3EX0 0460 ; +: TA3EX0_L 0460 ; +: TA3EX0_H 0461 ; +: TA3IV 046E ; +: TA3IV_L 046E ; +: TA3IV_H 046F ; +: TB0CTL 0480 ; +: TB0CTL_L 0480 ; +: TB0CTL_H 0481 ; +: TB0CCTL0 0482 ; +: TB0CCTL0_L 0482 ; +: TB0CCTL0_H 0483 ; +: TB0CCTL1 0484 ; +: TB0CCTL1_L 0484 ; +: TB0CCTL1_H 0485 ; +: TB0CCTL2 0486 ; +: TB0CCTL2_L 0486 ; +: TB0CCTL2_H 0487 ; +: TB0CCTL3 0488 ; +: TB0CCTL3_L 0488 ; +: TB0CCTL3_H 0489 ; +: TB0CCTL4 048A ; +: TB0CCTL4_L 048A ; +: TB0CCTL4_H 048B ; +: TB0CCTL5 048C ; +: TB0CCTL5_L 048C ; +: TB0CCTL5_H 048D ; +: TB0CCTL6 048E ; +: TB0CCTL6_L 048E ; +: TB0CCTL6_H 048F ; +: TB0R 0490 ; +: TB0R_L 0490 ; +: TB0R_H 0491 ; +: TB0CCR0 0492 ; +: TB0CCR0_L 0492 ; +: TB0CCR0_H 0493 ; +: TB0CCR1 0494 ; +: TB0CCR1_L 0494 ; +: TB0CCR1_H 0495 ; +: TB0CCR2 0496 ; +: TB0CCR2_L 0496 ; +: TB0CCR2_H 0497 ; +: TB0CCR3 0498 ; +: TB0CCR3_L 0498 ; +: TB0CCR3_H 0499 ; +: TB0CCR4 049A ; +: TB0CCR4_L 049A ; +: TB0CCR4_H 049B ; +: TB0CCR5 049C ; +: TB0CCR5_L 049C ; +: TB0CCR5_H 049D ; +: TB0CCR6 049E ; +: TB0CCR6_L 049E ; +: TB0CCR6_H 049F ; +: TB0EX0 04A0 ; +: TB0EX0_L 04A0 ; +: TB0EX0_H 04A1 ; +: TB0IV 04AE ; +: TB0IV_L 04AE ; +: TB0IV_H 04AF ; +: WDTCTL 01CC ; +: WDTCTL_L 01CC ; +: WDTCTL_H 01CD ; +: CP0CTL0 08E0 ; +: CP0CTL0_L 08E0 ; +: CP0CTL0_H 08E1 ; +: CP0CTL1 08E2 ; +: CP0CTL1_L 08E2 ; +: CP0CTL1_H 08E3 ; +: CP0INT 08E6 ; +: CP0INT_L 08E6 ; +: CP0INT_H 08E7 ; +: CP0IV 08E8 ; +: CP0IV_L 08E8 ; +: CP0IV_H 08E9 ; +: CP0DACCTL 08F0 ; +: CP0DACCTL_L 08F0 ; +: CP0DACCTL_H 08F1 ; +: CP0DACDATA 08F2 ; +: CP0DACDATA_L 08F2 ; +: CP0DACDATA_H 08F3 ; +: UCA0CTLW0 0500 ; +: UCA0CTLW0_L 0500 ; +: UCA0CTLW0_H 0501 ; +: UCA0CTLW1 0502 ; +: UCA0CTLW1_L 0502 ; +: UCA0CTLW1_H 0503 ; +: UCA0BRW 0506 ; +: UCA0BRW_L 0506 ; +: UCA0BRW_H 0507 ; +: UCA0MCTLW 0508 ; +: UCA0MCTLW_L 0508 ; +: UCA0MCTLW_H 0509 ; +: UCA0STATW 050A ; +: UCA0STATW_L 050A ; +: UCA0STATW_H 050B ; +: UCA0RXBUF 050C ; +: UCA0RXBUF_L 050C ; +: UCA0RXBUF_H 050D ; +: UCA0TXBUF 050E ; +: UCA0TXBUF_L 050E ; +: UCA0TXBUF_H 050F ; +: UCA0ABCTL 0510 ; +: UCA0ABCTL_L 0510 ; +: UCA0ABCTL_H 0511 ; +: UCA0IRCTL 0512 ; +: UCA0IRCTL_L 0512 ; +: UCA0IRCTL_H 0513 ; +: UCA0IE 051A ; +: UCA0IE_L 051A ; +: UCA0IE_H 051B ; +: UCA0IFG 051C ; +: UCA0IFG_L 051C ; +: UCA0IFG_H 051D ; +: UCA0IV 051E ; +: UCA0IV_L 051E ; +: UCA0IV_H 051F ; +: UCA1CTLW0 0520 ; +: UCA1CTLW0_L 0520 ; +: UCA1CTLW0_H 0521 ; +: UCA1CTLW1 0522 ; +: UCA1CTLW1_L 0522 ; +: UCA1CTLW1_H 0523 ; +: UCA1BRW 0526 ; +: UCA1BRW_L 0526 ; +: UCA1BRW_H 0527 ; +: UCA1MCTLW 0528 ; +: UCA1MCTLW_L 0528 ; +: UCA1MCTLW_H 0529 ; +: UCA1STATW 052A ; +: UCA1STATW_L 052A ; +: UCA1STATW_H 052B ; +: UCA1RXBUF 052C ; +: UCA1RXBUF_L 052C ; +: UCA1RXBUF_H 052D ; +: UCA1TXBUF 052E ; +: UCA1TXBUF_L 052E ; +: UCA1TXBUF_H 052F ; +: UCA1ABCTL 0530 ; +: UCA1ABCTL_L 0530 ; +: UCA1ABCTL_H 0531 ; +: UCA1IRCTL 0532 ; +: UCA1IRCTL_L 0532 ; +: UCA1IRCTL_H 0533 ; +: UCA1IE 053A ; +: UCA1IE_L 053A ; +: UCA1IE_H 053B ; +: UCA1IFG 053C ; +: UCA1IFG_L 053C ; +: UCA1IFG_H 053D ; +: UCA1IV 053E ; +: UCA1IV_L 053E ; +: UCA1IV_H 053F ; +: UCB0CTLW0 0540 ; +: UCB0CTLW0_L 0540 ; +: UCB0CTLW0_H 0541 ; +: UCB0CTLW1 0542 ; +: UCB0CTLW1_L 0542 ; +: UCB0CTLW1_H 0543 ; +: UCB0BRW 0546 ; +: UCB0BRW_L 0546 ; +: UCB0BRW_H 0547 ; +: UCB0STATW 0548 ; +: UCB0STATW_L 0548 ; +: UCB0STATW_H 0549 ; +: UCB0TBCNT 054A ; +: UCB0TBCNT_L 054A ; +: UCB0TBCNT_H 054B ; +: UCB0RXBUF 054C ; +: UCB0RXBUF_L 054C ; +: UCB0RXBUF_H 054D ; +: UCB0TXBUF 054E ; +: UCB0TXBUF_L 054E ; +: UCB0TXBUF_H 054F ; +: UCB0I2COA0 0554 ; +: UCB0I2COA0_L 0554 ; +: UCB0I2COA0_H 0555 ; +: UCB0I2COA1 0556 ; +: UCB0I2COA1_L 0556 ; +: UCB0I2COA1_H 0557 ; +: UCB0I2COA2 0558 ; +: UCB0I2COA2_L 0558 ; +: UCB0I2COA2_H 0559 ; +: UCB0I2COA3 055A ; +: UCB0I2COA3_L 055A ; +: UCB0I2COA3_H 055B ; +: UCB0ADDRX 055C ; +: UCB0ADDRX_L 055C ; +: UCB0ADDRX_H 055D ; +: UCB0ADDMASK 055E ; +: UCB0ADDMASK_L 055E ; +: UCB0ADDMASK_H 055F ; +: UCB0I2CSA 0560 ; +: UCB0I2CSA_L 0560 ; +: UCB0I2CSA_H 0561 ; +: UCB0IE 056A ; +: UCB0IE_L 056A ; +: UCB0IE_H 056B ; +: UCB0IFG 056C ; +: UCB0IFG_L 056C ; +: UCB0IFG_H 056D ; +: UCB0IV 056E ; +: UCB0IV_L 056E ; +: UCB0IV_H 056F ; +: UCB1CTLW0 0580 ; +: UCB1CTLW0_L 0580 ; +: UCB1CTLW0_H 0581 ; +: UCB1CTLW1 0582 ; +: UCB1CTLW1_L 0582 ; +: UCB1CTLW1_H 0583 ; +: UCB1BRW 0586 ; +: UCB1BRW_L 0586 ; +: UCB1BRW_H 0587 ; +: UCB1STATW 0588 ; +: UCB1STATW_L 0588 ; +: UCB1STATW_H 0589 ; +: UCB1TBCNT 058A ; +: UCB1TBCNT_L 058A ; +: UCB1TBCNT_H 058B ; +: UCB1RXBUF 058C ; +: UCB1RXBUF_L 058C ; +: UCB1RXBUF_H 058D ; +: UCB1TXBUF 058E ; +: UCB1TXBUF_L 058E ; +: UCB1TXBUF_H 058F ; +: UCB1I2COA0 0594 ; +: UCB1I2COA0_L 0594 ; +: UCB1I2COA0_H 0595 ; +: UCB1I2COA1 0596 ; +: UCB1I2COA1_L 0596 ; +: UCB1I2COA1_H 0597 ; +: UCB1I2COA2 0598 ; +: UCB1I2COA2_L 0598 ; +: UCB1I2COA2_H 0599 ; +: UCB1I2COA3 059A ; +: UCB1I2COA3_L 059A ; +: UCB1I2COA3_H 059B ; +: UCB1ADDRX 059C ; +: UCB1ADDRX_L 059C ; +: UCB1ADDRX_H 059D ; +: UCB1ADDMASK 059E ; +: UCB1ADDMASK_L 059E ; +: UCB1ADDMASK_H 059F ; +: UCB1I2CSA 05A0 ; +: UCB1I2CSA_L 05A0 ; +: UCB1I2CSA_H 05A1 ; +: UCB1IE 05AA ; +: UCB1IE_L 05AA ; +: UCB1IE_H 05AB ; +: UCB1IFG 05AC ; +: UCB1IFG_L 05AC ; +: UCB1IFG_H 05AD ; +: UCB1IV 05AE ; +: UCB1IV_L 05AE ; +: UCB1IV_H 05AF ; decimal - diff --git a/msp430/alee-msp430.cpp b/msp430/alee-msp430.cpp index 4bb82ef..fba9c6f 100644 --- a/msp430/alee-msp430.cpp +++ b/msp430/alee-msp430.cpp @@ -32,24 +32,18 @@ static void serput(int c); static void serputs(const char *s); static void printint(DoubleCell n, char *buf); +static void initGPIO(); +static void initClock(); +static void initUART(); +static void Software_Trim(); +#define MCLK_FREQ_MHZ (8) // MCLK = 8MHz + int main() { WDTCTL = WDTPW | WDTHOLD; - DCOCTL = 0; - BCSCTL1 = CALBC1_16MHZ; - DCOCTL = CALDCO_16MHZ; - - P1SEL |= BIT1 | BIT2; - P1SEL2 |= BIT1 | BIT2; - - UCA0CTL1 = UCSWRST; - UCA0CTL1 |= UCSSEL_2; - UCA0BR0 = 139; - UCA0BR1 = 0; - UCA0MCTL = UCBRS0; - UCA0CTL1 &= (uint8_t)~UCSWRST; - - __enable_interrupt(); + initGPIO(); + initClock(); + initUART(); static SplitMemDict dict (alee_dat); State state (dict, readchar); @@ -58,8 +52,8 @@ int main() auto ptr = strbuf; while (1) { - if (IFG2 & UCA0RXIFG) { - char c = UCA0RXBUF; + if (UCA0IFG & UCRXIFG) { + auto c = static_cast(UCA0RXBUF); serput(c); if (c == '\r') { @@ -95,13 +89,13 @@ int main() } } -static void readchar(State& state) +void readchar(State& state) { auto idx = state.dict.read(Dictionary::Input); Addr addr = Dictionary::Input + sizeof(Cell) + idx; - while (!(IFG2 & UCA0RXIFG)); - auto c = UCA0RXBUF; + while (!(UCA0IFG & UCRXIFG)); + auto c = static_cast(UCA0RXBUF); if (isupper(c)) c += 32; state.dict.writebyte(addr, c ? c : ' '); @@ -109,8 +103,8 @@ static void readchar(State& state) void serput(int c) { - while (!(IFG2 & UCA0TXIFG)); - UCA0TXBUF = (char)c; + while (!(UCA0IFG & UCTXIFG)); + UCA0TXBUF = static_cast(c); } void serputs(const char *s) @@ -128,7 +122,7 @@ void printint(DoubleCell n, char *buf) n = -n; do { - *ptr++ = (char)(n % 10) + '0'; + *ptr++ = static_cast((n % 10) + '0'); } while ((n /= 10)); if (neg) @@ -164,6 +158,128 @@ void user_sys(State& state) } } -extern "C" int atexit(void (*)()) { return 0; } -void operator delete(void *) {} -void operator delete(void *, std::size_t) {} +void initGPIO() +{ + // Unnecessary, but done by TI example + P1DIR = 0xFF; P2DIR = 0xFF; + P1REN = 0xFF; P2REN = 0xFF; + P1OUT = 0x00; P2OUT = 0x00; + + // Set LED pins to outputs + P6DIR |= BIT0 | BIT1 | BIT2; + P6OUT |= BIT0 | BIT1 | BIT2; + P5DIR |= BIT5 | BIT6 | BIT7; + P5OUT |= BIT5 | BIT6 | BIT7; + + // Allow GPIO configurations to be applied + PM5CTL0 &= ~LOCKLPM5; + + // Safety measure, prevent unwarranted interrupts + P5IFG = 0; + P6IFG = 0; +} + +void initClock() +{ + __bis_SR_register(SCG0); // disable FLL + CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source + CSCTL1 = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_3;// DCOFTRIM=3, DCO Range = 8MHz + CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz + __delay_cycles(3); + __bic_SR_register(SCG0); // enable FLL + Software_Trim(); // Software Trim to get the best DCOFTRIM value + + CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz + // default DCODIV as MCLK and SMCLK source +} + +void initUART() +{ + // Configure UART pins + P5SEL0 |= BIT1 | BIT2; // set 2-UART pin as second function + SYSCFG3|=USCIA0RMP; //Set the remapping source + // Configure UART + UCA0CTLW0 |= UCSWRST; + UCA0CTLW0 |= UCSSEL__SMCLK; + + // Baud Rate calculation + // 8000000/(16*9600) = 52.083 + // Fractional portion = 0.083 + // User's Guide Table 17-4: UCBRSx = 0x49 + // UCBRFx = int ( (52.083-52)*16) = 1 + UCA0BR0 = 52; // 8000000/16/9600 + UCA0BR1 = 0x00; + UCA0MCTLW = 0x4900 | UCOS16 | UCBRF_1; + + UCA0CTLW0 &= ~UCSWRST; // Initialize eUSCI +} + +void Software_Trim() +{ + unsigned int oldDcoTap = 0xffff; + unsigned int newDcoTap = 0xffff; + unsigned int newDcoDelta = 0xffff; + unsigned int bestDcoDelta = 0xffff; + unsigned int csCtl0Copy = 0; + unsigned int csCtl1Copy = 0; + unsigned int csCtl0Read = 0; + unsigned int csCtl1Read = 0; + unsigned int dcoFreqTrim = 3; + unsigned char endLoop = 0; + + do + { + CSCTL0 = 0x100; // DCO Tap = 256 + do + { + CSCTL7 &= ~DCOFFG; // Clear DCO fault flag + }while (CSCTL7 & DCOFFG); // Test DCO fault flag + + __delay_cycles((unsigned int)3000 * MCLK_FREQ_MHZ);// Wait FLL lock status (FLLUNLOCK) to be stable + // Suggest to wait 24 cycles of divided FLL reference clock + while((CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)) && ((CSCTL7 & DCOFFG) == 0)); + + csCtl0Read = CSCTL0; // Read CSCTL0 + csCtl1Read = CSCTL1; // Read CSCTL1 + + oldDcoTap = newDcoTap; // Record DCOTAP value of last time + newDcoTap = csCtl0Read & 0x01ff; // Get DCOTAP value of this time + dcoFreqTrim = (csCtl1Read & 0x0070)>>4;// Get DCOFTRIM value + + if(newDcoTap < 256) // DCOTAP < 256 + { + newDcoDelta = 256 - newDcoTap; // Delta value between DCPTAP and 256 + if((oldDcoTap != 0xffff) && (oldDcoTap >= 256)) // DCOTAP cross 256 + endLoop = 1; // Stop while loop + else + { + dcoFreqTrim--; + CSCTL1 = (csCtl1Read & (~DCOFTRIM)) | (dcoFreqTrim<<4); + } + } + else // DCOTAP >= 256 + { + newDcoDelta = newDcoTap - 256; // Delta value between DCPTAP and 256 + if(oldDcoTap < 256) // DCOTAP cross 256 + endLoop = 1; // Stop while loop + else + { + dcoFreqTrim++; + CSCTL1 = (csCtl1Read & (~DCOFTRIM)) | (dcoFreqTrim<<4); + } + } + + if(newDcoDelta < bestDcoDelta) // Record DCOTAP closest to 256 + { + csCtl0Copy = csCtl0Read; + csCtl1Copy = csCtl1Read; + bestDcoDelta = newDcoDelta; + } + + }while(endLoop == 0); // Poll until endLoop == 1 + + CSCTL0 = csCtl0Copy; // Reload locked DCOTAP + CSCTL1 = csCtl1Copy; // Reload locked DCOFTRIM + while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked +} + diff --git a/msp430/msp430fr2476.ld b/msp430/msp430fr2476.ld new file mode 100644 index 0000000..011683b --- /dev/null +++ b/msp430/msp430fr2476.ld @@ -0,0 +1,463 @@ +/* ============================================================================ */ +/* Copyright (c) 2021, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports MSP430FR2476 devices. */ +/* Version: 1.212 */ +/* Default linker script, for normal executables */ + +OUTPUT_ARCH(msp430) +ENTRY(_start) + +MEMORY { + TINYRAM : ORIGIN = 0x0006, LENGTH = 0x001A /* END=0x001F, size 26 */ + BSL0 : ORIGIN = 0x1000, LENGTH = 0x0800 /* END=0x17FF, size 2048 */ + TLVMEM : ORIGIN = 0x1A00, LENGTH = 0x0200 /* END=0x1BFF, size 512 */ + BOOTCODE : ORIGIN = 0x1C00, LENGTH = 0x0400 /* END=0x1FFF, size 1024 */ + ROMLIB : ORIGIN = 0xC0000, LENGTH = 0x4000 /* END=0xC3FFF, size 16384 */ + BSL1 : ORIGIN = 0xFFC00, LENGTH = 0x0400 /* END=0xFFFFF, size 1024 */ + RAM : ORIGIN = 0x2000, LENGTH = 0x2000 /* END=0x3FFF, size 8192 */ + INFOMEM : ORIGIN = 0x1800, LENGTH = 0x0200 /* END=0x19FF, size 512 */ + FRAM (rx) : ORIGIN = 0x8000, LENGTH = 0x7F80 /* END=0xFF7F, size 32640 */ + HIFRAM (rxw) : ORIGIN = 0x00010000, LENGTH = 0x00007FFF + JTAGSIGNATURE : ORIGIN = 0xFF80, LENGTH = 0x0004 + BSLSIGNATURE : ORIGIN = 0xFF84, LENGTH = 0x0004 + BSLCONFIGURATIONSIGNATURE : ORIGIN = 0xFF88, LENGTH = 0x0002 + BSLCONFIGURATION : ORIGIN = 0xFF8A, LENGTH = 0x0002 + BSLI2CADDRESS : ORIGIN = 0xFFA0, LENGTH = 0x0002 + VECT0 : ORIGIN = 0xFFA2, LENGTH = 0x0002 + VECT1 : ORIGIN = 0xFFA4, LENGTH = 0x0002 + VECT2 : ORIGIN = 0xFFA6, LENGTH = 0x0002 + VECT3 : ORIGIN = 0xFFA8, LENGTH = 0x0002 + VECT4 : ORIGIN = 0xFFAA, LENGTH = 0x0002 + VECT5 : ORIGIN = 0xFFAC, LENGTH = 0x0002 + VECT6 : ORIGIN = 0xFFAE, LENGTH = 0x0002 + VECT7 : ORIGIN = 0xFFB0, LENGTH = 0x0002 + VECT8 : ORIGIN = 0xFFB2, LENGTH = 0x0002 + VECT9 : ORIGIN = 0xFFB4, LENGTH = 0x0002 + VECT10 : ORIGIN = 0xFFB6, LENGTH = 0x0002 + VECT11 : ORIGIN = 0xFFB8, LENGTH = 0x0002 + VECT12 : ORIGIN = 0xFFBA, LENGTH = 0x0002 + VECT13 : ORIGIN = 0xFFBC, LENGTH = 0x0002 + VECT14 : ORIGIN = 0xFFBE, LENGTH = 0x0002 + VECT15 : ORIGIN = 0xFFC0, LENGTH = 0x0002 + VECT16 : ORIGIN = 0xFFC2, LENGTH = 0x0002 + VECT17 : ORIGIN = 0xFFC4, LENGTH = 0x0002 + VECT18 : ORIGIN = 0xFFC6, LENGTH = 0x0002 + VECT19 : ORIGIN = 0xFFC8, LENGTH = 0x0002 + VECT20 : ORIGIN = 0xFFCA, LENGTH = 0x0002 + VECT21 : ORIGIN = 0xFFCC, LENGTH = 0x0002 + VECT22 : ORIGIN = 0xFFCE, LENGTH = 0x0002 + VECT23 : ORIGIN = 0xFFD0, LENGTH = 0x0002 + VECT24 : ORIGIN = 0xFFD2, LENGTH = 0x0002 + VECT25 : ORIGIN = 0xFFD4, LENGTH = 0x0002 + VECT26 : ORIGIN = 0xFFD6, LENGTH = 0x0002 + VECT27 : ORIGIN = 0xFFD8, LENGTH = 0x0002 + VECT28 : ORIGIN = 0xFFDA, LENGTH = 0x0002 + VECT29 : ORIGIN = 0xFFDC, LENGTH = 0x0002 + VECT30 : ORIGIN = 0xFFDE, LENGTH = 0x0002 + VECT31 : ORIGIN = 0xFFE0, LENGTH = 0x0002 + VECT32 : ORIGIN = 0xFFE2, LENGTH = 0x0002 + VECT33 : ORIGIN = 0xFFE4, LENGTH = 0x0002 + VECT34 : ORIGIN = 0xFFE6, LENGTH = 0x0002 + VECT35 : ORIGIN = 0xFFE8, LENGTH = 0x0002 + VECT36 : ORIGIN = 0xFFEA, LENGTH = 0x0002 + VECT37 : ORIGIN = 0xFFEC, LENGTH = 0x0002 + VECT38 : ORIGIN = 0xFFEE, LENGTH = 0x0002 + VECT39 : ORIGIN = 0xFFF0, LENGTH = 0x0002 + VECT40 : ORIGIN = 0xFFF2, LENGTH = 0x0002 + VECT41 : ORIGIN = 0xFFF4, LENGTH = 0x0002 + VECT42 : ORIGIN = 0xFFF6, LENGTH = 0x0002 + VECT43 : ORIGIN = 0xFFF8, LENGTH = 0x0002 + VECT44 : ORIGIN = 0xFFFA, LENGTH = 0x0002 + VECT45 : ORIGIN = 0xFFFC, LENGTH = 0x0002 + RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002 +} + +SECTIONS +{ + .jtagsignature : {} > JTAGSIGNATURE + .bslsignature : {} > BSLSIGNATURE + .bslconfigsignature : {} > BSLCONFIGURATIONSIGNATURE + .bslconfig : {} > BSLCONFIGURATION + .bsli2caddress : {} > BSLI2CADDRESS + + __interrupt_vector_0 : { KEEP (*(__interrupt_vector_0 )) } > VECT0 + __interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) } > VECT1 + __interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) } > VECT2 + __interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) } > VECT3 + __interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) } > VECT4 + __interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) } > VECT5 + __interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) } > VECT6 + __interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) } > VECT7 + __interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) } > VECT8 + __interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) } > VECT9 + __interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) } > VECT10 + __interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) } > VECT11 + __interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) } > VECT12 + __interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) } > VECT13 + __interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) } > VECT14 + __interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) } > VECT15 + __interrupt_vector_16 : { KEEP (*(__interrupt_vector_16)) } > VECT16 + __interrupt_vector_17 : { KEEP (*(__interrupt_vector_17)) } > VECT17 + __interrupt_vector_18 : { KEEP (*(__interrupt_vector_18)) } > VECT18 + __interrupt_vector_19 : { KEEP (*(__interrupt_vector_19)) } > VECT19 + __interrupt_vector_20 : { KEEP (*(__interrupt_vector_20)) KEEP (*(__interrupt_vector_ecomp0)) } > VECT20 + __interrupt_vector_21 : { KEEP (*(__interrupt_vector_21)) KEEP (*(__interrupt_vector_port6)) } > VECT21 + __interrupt_vector_22 : { KEEP (*(__interrupt_vector_22)) KEEP (*(__interrupt_vector_port5)) } > VECT22 + __interrupt_vector_23 : { KEEP (*(__interrupt_vector_23)) KEEP (*(__interrupt_vector_port4)) } > VECT23 + __interrupt_vector_24 : { KEEP (*(__interrupt_vector_24)) KEEP (*(__interrupt_vector_port3)) } > VECT24 + __interrupt_vector_25 : { KEEP (*(__interrupt_vector_25)) KEEP (*(__interrupt_vector_port2)) } > VECT25 + __interrupt_vector_26 : { KEEP (*(__interrupt_vector_26)) KEEP (*(__interrupt_vector_port1)) } > VECT26 + __interrupt_vector_27 : { KEEP (*(__interrupt_vector_27)) KEEP (*(__interrupt_vector_adc)) } > VECT27 + __interrupt_vector_28 : { KEEP (*(__interrupt_vector_28)) KEEP (*(__interrupt_vector_eusci_b1)) } > VECT28 + __interrupt_vector_29 : { KEEP (*(__interrupt_vector_29)) KEEP (*(__interrupt_vector_eusci_b0)) } > VECT29 + __interrupt_vector_30 : { KEEP (*(__interrupt_vector_30)) KEEP (*(__interrupt_vector_eusci_a1)) } > VECT30 + __interrupt_vector_31 : { KEEP (*(__interrupt_vector_31)) KEEP (*(__interrupt_vector_eusci_a0)) } > VECT31 + __interrupt_vector_32 : { KEEP (*(__interrupt_vector_32)) KEEP (*(__interrupt_vector_wdt)) } > VECT32 + __interrupt_vector_33 : { KEEP (*(__interrupt_vector_33)) KEEP (*(__interrupt_vector_rtc)) } > VECT33 + __interrupt_vector_34 : { KEEP (*(__interrupt_vector_34)) KEEP (*(__interrupt_vector_timer0_b1)) } > VECT34 + __interrupt_vector_35 : { KEEP (*(__interrupt_vector_35)) KEEP (*(__interrupt_vector_timer0_b0)) } > VECT35 + __interrupt_vector_36 : { KEEP (*(__interrupt_vector_36)) KEEP (*(__interrupt_vector_timer3_a1)) } > VECT36 + __interrupt_vector_37 : { KEEP (*(__interrupt_vector_37)) KEEP (*(__interrupt_vector_timer3_a0)) } > VECT37 + __interrupt_vector_38 : { KEEP (*(__interrupt_vector_38)) KEEP (*(__interrupt_vector_timer2_a1)) } > VECT38 + __interrupt_vector_39 : { KEEP (*(__interrupt_vector_39)) KEEP (*(__interrupt_vector_timer2_a0)) } > VECT39 + __interrupt_vector_40 : { KEEP (*(__interrupt_vector_40)) KEEP (*(__interrupt_vector_timer1_a1)) } > VECT40 + __interrupt_vector_41 : { KEEP (*(__interrupt_vector_41)) KEEP (*(__interrupt_vector_timer1_a0)) } > VECT41 + __interrupt_vector_42 : { KEEP (*(__interrupt_vector_42)) KEEP (*(__interrupt_vector_timer0_a1)) } > VECT42 + __interrupt_vector_43 : { KEEP (*(__interrupt_vector_43)) KEEP (*(__interrupt_vector_timer0_a0)) } > VECT43 + __interrupt_vector_44 : { KEEP (*(__interrupt_vector_44)) KEEP (*(__interrupt_vector_unmi)) } > VECT44 + __interrupt_vector_45 : { KEEP (*(__interrupt_vector_45)) KEEP (*(__interrupt_vector_sysnmi)) } > VECT45 + __reset_vector : + { + KEEP (*(__interrupt_vector_46)) + KEEP (*(__interrupt_vector_reset)) + KEEP (*(.resetvec)) + } > RESETVEC + + .lower.rodata : + { + . = ALIGN(2); + *(.lower.rodata.* .lower.rodata) + } > FRAM + + .rodata : + { + . = ALIGN(2); + *(.plt) + *(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*) + *(.rodata1) + KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) + } > FRAM + + /* Note: This is a separate .rodata section for sections which are + read only but which older linkers treat as read-write. + This prevents older linkers from marking the entire .rodata + section as read-write. */ + .rodata2 : + { + . = ALIGN(2); + PROVIDE (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + . = ALIGN(2); + PROVIDE (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE (__init_array_end = .); + . = ALIGN(2); + PROVIDE (__fini_array_start = .); + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE (__fini_array_end = .); + . = ALIGN(2); + *(.eh_frame_hdr) + KEEP (*(.eh_frame)) + + /* gcc uses crtbegin.o to find the start of the constructors, so + we make sure it is first. Because this is a wildcard, it + doesn't matter if the user does not actually link against + crtbegin.o; the linker won't look for a file to match a + wildcard. The wildcard also means that it doesn't matter which + directory crtbegin.o is in. */ + KEEP (*crtbegin*.o(.ctors)) + + /* We don't want to include the .ctor section from the crtend.o + file until after the sorted ctors. The .ctor section from + the crtend file contains the end of ctors marker and it must + be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } > FRAM + + .upper.rodata : + { + *(.upper.rodata.* .upper.rodata) + } > HIFRAM + + /* This section contains data that is initialised during load + but not on application reset. */ + .persistent : + { + . = ALIGN(2); + PROVIDE (__persistent_start = .); + *(.persistent) + . = ALIGN(2); + PROVIDE (__persistent_end = .); + } > FRAM + + .tinyram : {} > TINYRAM + + .lower.data : + { + . = ALIGN(2); + PROVIDE (__datastart = .); + *(.lower.data.* .lower.data) + } > RAM AT> FRAM + + .data : + { + . = ALIGN(2); + + KEEP (*(.jcr)) + *(.data.rel.ro.local) *(.data.rel.ro*) + *(.dynamic) + + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + *(.data1) + *(.got.plt) *(.got) + + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + . = ALIGN(2); + *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1) + + . = ALIGN(2); + + _edata = .; + PROVIDE (edata = .); + PROVIDE (__dataend = .); + } > RAM AT> FRAM + + /* Note that crt0 assumes this is a multiple of two; all the + start/stop symbols are also assumed word-aligned. */ + PROVIDE(__romdatastart = LOADADDR(.lower.data)); + PROVIDE (__romdatacopysize = SIZEOF(.lower.data) + SIZEOF(.data)); + + .upper.data : + { + __upper_data_init = LOADADDR (.upper.data); + /* Status word. */ + SHORT(1); + __high_datastart = .; + *(.upper.data.* .upper.data) + __high_dataend = .; + } > HIFRAM AT> FRAM + + __rom_highdatacopysize = SIZEOF(.upper.data) - 2; + __rom_highdatastart = LOADADDR(.upper.data) + 2; + + .lower.bss : + { + . = ALIGN(2); + PROVIDE (__bssstart = .); + *(.lower.bss.* .lower.bss) + } > RAM + + .bss : + { + . = ALIGN(2); + *(.dynbss) + *(.sbss .sbss.*) + *(.bss .bss.* .gnu.linkonce.b.*) + . = ALIGN(2); + *(COMMON) + PROVIDE (__bssend = .); + } > RAM + PROVIDE (__bsssize = SIZEOF(.lower.bss) + SIZEOF(.bss)); + + .upper.bss : + { + . = ALIGN(2); + __high_bssstart = .; + *(.upper.bss.* .upper.bss) + . = ALIGN(2); + __high_bssend = .; + } > HIFRAM + __high_bsssize = SIZEOF(.upper.bss); + + /* This section contains data that is not initialised during load + or application reset. */ + .noinit (NOLOAD) : + { + . = ALIGN(2); + PROVIDE (__noinit_start = .); + *(.noinit) + . = ALIGN(2); + PROVIDE (__noinit_end = .); + } > RAM + + /* We create this section so that "end" will always be in the + RAM region (matching .stack below), even if the .bss + section is empty. */ + .heap (NOLOAD) : + { + . = ALIGN(2); + __heap_start__ = .; + _end = __heap_start__; + PROVIDE (end = .); + KEEP (*(.heap)) + _end = .; + PROVIDE (end = .); + /* This word is here so that the section is not empty, and thus + not discarded by the linker. The actual value does not matter + and is ignored. */ + LONG(0); + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > RAM + /* WARNING: Do not place anything in RAM here. + The heap section must be the last section in RAM and the stack + section must be placed at the very end of the RAM region. */ + + .stack (ORIGIN (RAM) + LENGTH(RAM)) : + { + PROVIDE (__stack = .); + *(.stack) + } + + .lower.text : + { + . = ALIGN(2); + *(.lower.text.* .lower.text) + } > FRAM + + .text : + { + PROVIDE (_start = .); + + . = ALIGN(2); + KEEP (*(SORT(.crt_*))) + + . = ALIGN(2); + KEEP (*(.lowtext)) + + . = ALIGN(2); + *(.text .stub .text.* .gnu.linkonce.t.* .text:*) + + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.interp .hash .dynsym .dynstr .gnu.version*) + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + . = ALIGN(2); + KEEP (*(.init)) + KEEP (*(.fini)) + KEEP (*(.tm_clone_table)) + } > FRAM + + .upper.text : + { + . = ALIGN(2); + *(.upper.text.* .upper.text) + } > HIFRAM + + .info (NOLOAD) : {} > INFOMEM /* MSP430 INFO FLASH MEMORY SEGMENTS */ + + /* The rest are all not normally part of the runtime image. */ + + .MSP430.attributes 0 : + { + KEEP (*(.MSP430.attributes)) + KEEP (*(.gnu.attributes)) + KEEP (*(__TI_build_attributes)) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1. */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions. */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2. */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2. */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions. */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF Extension. */ + .debug_macro 0 : { *(.debug_macro) } + + /DISCARD/ : { *(.note.GNU-stack) } +} + + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +INCLUDE msp430fr2476_symbols.ld + diff --git a/msp430/msp430g2553.ld b/msp430/msp430g2553.ld deleted file mode 100644 index 0845667..0000000 --- a/msp430/msp430g2553.ld +++ /dev/null @@ -1,315 +0,0 @@ -/* ============================================================================ */ -/* Copyright (c) 2021, Texas Instruments Incorporated */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* */ -/* * Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* */ -/* * Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in the */ -/* documentation and/or other materials provided with the distribution. */ -/* */ -/* * Neither the name of Texas Instruments Incorporated nor the names of */ -/* its contributors may be used to endorse or promote products derived */ -/* from this software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ -/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ -/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ -/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ -/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ -/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ -/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ -/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ============================================================================ */ - -/* This file supports MSP430G2553 devices. */ -/* Version: 1.212 */ -/* Default linker script, for normal executables */ - -OUTPUT_ARCH(msp430) -ENTRY(_start) - -MEMORY { - SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */ - RAM : ORIGIN = 0x0200, LENGTH = 0x0200 /* END=0x03FF, size 512 */ - INFOMEM : ORIGIN = 0x1000, LENGTH = 0x0100 /* END=0x10FF, size 256 as 4 64-byte segments */ - INFOA : ORIGIN = 0x10C0, LENGTH = 0x0040 /* END=0x10FF, size 64 */ - INFOB : ORIGIN = 0x1080, LENGTH = 0x0040 /* END=0x10BF, size 64 */ - INFOC : ORIGIN = 0x1040, LENGTH = 0x0040 /* END=0x107F, size 64 */ - INFOD : ORIGIN = 0x1000, LENGTH = 0x0040 /* END=0x103F, size 64 */ - ROM (rx) : ORIGIN = 0xC000, LENGTH = 0x3FDE /* END=0xFFDD, size 16350 */ - BSLSIGNATURE : ORIGIN = 0xFFDE, LENGTH = 0x0002 - VECT1 : ORIGIN = 0xFFE0, LENGTH = 0x0002 - VECT2 : ORIGIN = 0xFFE2, LENGTH = 0x0002 - VECT3 : ORIGIN = 0xFFE4, LENGTH = 0x0002 - VECT4 : ORIGIN = 0xFFE6, LENGTH = 0x0002 - VECT5 : ORIGIN = 0xFFE8, LENGTH = 0x0002 - VECT6 : ORIGIN = 0xFFEA, LENGTH = 0x0002 - VECT7 : ORIGIN = 0xFFEC, LENGTH = 0x0002 - VECT8 : ORIGIN = 0xFFEE, LENGTH = 0x0002 - VECT9 : ORIGIN = 0xFFF0, LENGTH = 0x0002 - VECT10 : ORIGIN = 0xFFF2, LENGTH = 0x0002 - VECT11 : ORIGIN = 0xFFF4, LENGTH = 0x0002 - VECT12 : ORIGIN = 0xFFF6, LENGTH = 0x0002 - VECT13 : ORIGIN = 0xFFF8, LENGTH = 0x0002 - VECT14 : ORIGIN = 0xFFFA, LENGTH = 0x0002 - VECT15 : ORIGIN = 0xFFFC, LENGTH = 0x0002 - RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002 -} - -SECTIONS -{ - .bslsignature : {} > BSLSIGNATURE - __interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) KEEP (*(__interrupt_vector_trapint)) } > VECT1 - __interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) } > VECT2 - __interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) KEEP (*(__interrupt_vector_port1)) } > VECT3 - __interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) KEEP (*(__interrupt_vector_port2)) } > VECT4 - __interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) } > VECT5 - __interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) KEEP (*(__interrupt_vector_adc10)) } > VECT6 - __interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) KEEP (*(__interrupt_vector_usciab0tx)) } > VECT7 - __interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) KEEP (*(__interrupt_vector_usciab0rx)) } > VECT8 - __interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) KEEP (*(__interrupt_vector_timer0_a1)) } > VECT9 - __interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) KEEP (*(__interrupt_vector_timer0_a0)) } > VECT10 - __interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) KEEP (*(__interrupt_vector_wdt)) } > VECT11 - __interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) KEEP (*(__interrupt_vector_comparatora)) } > VECT12 - __interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) KEEP (*(__interrupt_vector_timer1_a1)) } > VECT13 - __interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) KEEP (*(__interrupt_vector_timer1_a0)) } > VECT14 - __interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) KEEP (*(__interrupt_vector_nmi)) } > VECT15 - __reset_vector : - { - KEEP (*(__interrupt_vector_16)) - KEEP (*(__interrupt_vector_reset)) - KEEP (*(.resetvec)) - } > RESETVEC - - .rodata : - { - . = ALIGN(2); - *(.plt) - *(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*) - *(.rodata1) - KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) - } > ROM - - /* Note: This is a separate .rodata section for sections which are - read only but which older linkers treat as read-write. - This prevents older linkers from marking the entire .rodata - section as read-write. */ - .rodata2 : - { - . = ALIGN(2); - PROVIDE (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - . = ALIGN(2); - PROVIDE (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE (__init_array_end = .); - . = ALIGN(2); - PROVIDE (__fini_array_start = .); - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE (__fini_array_end = .); - /* . = ALIGN(2); - *(.eh_frame_hdr) - KEEP (*(.eh_frame)) */ - - /* gcc uses crtbegin.o to find the start of the constructors, so - we make sure it is first. Because this is a wildcard, it - doesn't matter if the user does not actually link against - crtbegin.o; the linker won't look for a file to match a - wildcard. The wildcard also means that it doesn't matter which - directory crtbegin.o is in. */ - KEEP (*crtbegin*.o(.ctors)) - - /* We don't want to include the .ctor section from the crtend.o - file until after the sorted ctors. The .ctor section from - the crtend file contains the end of ctors marker and it must - be last */ - KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - - KEEP (*crtbegin*.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } > ROM - - .text : - { - . = ALIGN(2); - PROVIDE (_start = .); - KEEP (*(SORT(.crt_*))) - *(.lowtext .text .stub .text.* .gnu.linkonce.t.* .text:*) - KEEP (*(.text.*personality*)) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.interp .hash .dynsym .dynstr .gnu.version*) - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - . = ALIGN(2); - KEEP (*(.init)) - KEEP (*(.fini)) - KEEP (*(.tm_clone_table)) - } > ROM - - .data : - { - . = ALIGN(2); - PROVIDE (__datastart = .); - - KEEP (*(.jcr)) - *(.data.rel.ro.local) *(.data.rel.ro*) - *(.dynamic) - - *(.data .data.* .gnu.linkonce.d.*) - KEEP (*(.gnu.linkonce.d.*personality*)) - SORT(CONSTRUCTORS) - *(.data1) - *(.got.plt) *(.got) - - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - . = ALIGN(2); - *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1) - - . = ALIGN(2); - _edata = .; - PROVIDE (edata = .); - PROVIDE (__dataend = .); - } > RAM AT>ROM - - /* Note that crt0 assumes this is a multiple of two; all the - start/stop symbols are also assumed word-aligned. */ - PROVIDE(__romdatastart = LOADADDR(.data)); - PROVIDE (__romdatacopysize = SIZEOF(.data)); - - .bss : - { - . = ALIGN(2); - PROVIDE (__bssstart = .); - *(.dynbss) - *(.sbss .sbss.*) - *(.bss .bss.* .gnu.linkonce.b.*) - . = ALIGN(2); - *(COMMON) - PROVIDE (__bssend = .); - } > RAM - PROVIDE (__bsssize = SIZEOF(.bss)); - - /* This section contains data that is not initialised during load - or application reset. */ - .noinit (NOLOAD) : - { - . = ALIGN(2); - PROVIDE (__noinit_start = .); - *(.noinit) - . = ALIGN(2); - PROVIDE (__noinit_end = .); - end = .; - } > RAM - - /* We create this section so that "end" will always be in the - RAM region (matching .stack below), even if the .bss - section is empty. */ - .heap (NOLOAD) : - { - . = ALIGN(2); - __heap_start__ = .; - _end = __heap_start__; - PROVIDE (end = .); - KEEP (*(.heap)) - _end = .; - PROVIDE (end = .); - /* This word is here so that the section is not empty, and thus - not discarded by the linker. The actual value does not matter - and is ignored. */ - LONG(0); - __heap_end__ = .; - __HeapLimit = __heap_end__; - } > RAM - /* WARNING: Do not place anything in RAM here. - The heap section must be the last section in RAM and the stack - section must be placed at the very end of the RAM region. */ - - .stack (ORIGIN (RAM) + LENGTH(RAM)) : - { - PROVIDE (__stack = .); - *(.stack) - } - - .infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */ - .infoB : {} > INFOB - .infoC : {} > INFOC - .infoD : {} > INFOD - - /* The rest are all not normally part of the runtime image. */ - - .MSP430.attributes 0 : - { - KEEP (*(.MSP430.attributes)) - KEEP (*(.gnu.attributes)) - KEEP (*(__TI_build_attributes)) - } - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1. */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions. */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2. */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2. */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions. */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* DWARF 3 */ - .debug_pubtypes 0 : { *(.debug_pubtypes) } - .debug_ranges 0 : { *(.debug_ranges) } - /* DWARF Extension. */ - .debug_macro 0 : { *(.debug_macro) } - - /DISCARD/ : { *(.note.GNU-stack) } -} - - -/****************************************************************************/ -/* Include peripherals memory map */ -/****************************************************************************/ - -INCLUDE msp430g2553_symbols.ld -