diff options
| author | Clyne Sullivan <clyne@bitgloo.com> | 2023-11-03 09:09:39 -0400 |
|---|---|---|
| committer | Clyne Sullivan <clyne@bitgloo.com> | 2023-11-03 09:09:39 -0400 |
| commit | e175ab21b36e93ed17cd065a4afe2fa284791781 (patch) | |
| tree | b50f94a9a2bb3e2d3c86d0e8dc551a2ec7388666 /forth/msp430.fth | |
| parent | 974f49ca165f8d90f8f8565ae4d71beb402b2d3a (diff) | |
interrupt support; better reg words
Diffstat (limited to 'forth/msp430.fth')
| -rw-r--r-- | forth/msp430.fth | 46 |
1 files changed, 41 insertions, 5 deletions
diff --git a/forth/msp430.fth b/forth/msp430.fth index 9fb041f..8a02158 100644 --- a/forth/msp430.fth +++ b/forth/msp430.fth @@ -1,9 +1,20 @@ -: r! 3 sys ; -: r@ 4 sys ; +: vector! 10 sys ; +: reg! 11 sys ; +: reg@ 12 sys ; +: 2reg! 13 sys ; +: 2reg@ 14 sys ; +: sr+ 15 sys ; +: sr- 16 sys ; -: rset dup r@ rot | swap r! ; -: rclr dup r@ rot invert & swap r! ; -: rtgl dup r@ rot ^ swap r! ; +: reg [ ' reg@ ' reg! ] literal literal ; +: 2reg [ ' 2reg@ ' 2reg! ] literal literal ; + +: set ( b r reg/wreg -- ) + >r over r> execute >r rot r> | -rot execute ; +: clear ( b r reg/wreg -- ) + >r over r> execute >r rot invert r> & -rot execute ; +: toggle ( b r reg/wreg -- ) + >r over r> execute >r rot r> ^ -rot execute ; 16 base ! @@ -841,3 +852,28 @@ decimal +: ECOMP0_VECTOR 0 ; +: PORT6_VECTOR 1 ; +: PORT5_VECTOR 2 ; +: PORT4_VECTOR 3 ; +: PORT3_VECTOR 4 ; +: PORT2_VECTOR 5 ; +: PORT1_VECTOR 6 ; +: ADC_VECTOR 7 ; +: EUSCI_B1_VECTOR 8 ; +: EUSCI_B0_VECTOR 9 ; +: EUSCI_A1_VECTOR 10 ; +: EUSCI_A0_VECTOR 11 ; +: WDT_VECTOR 12 ; +: RTC_VECTOR 13 ; +: TIMER0_B1_VECTOR 14 ; +: TIMER0_B0_VECTOR 15 ; +: TIMER3_A1_VECTOR 16 ; +: TIMER3_A0_VECTOR 17 ; +: TIMER2_A1_VECTOR 18 ; +: TIMER2_A0_VECTOR 19 ; +: TIMER1_A1_VECTOR 20 ; +: TIMER1_A0_VECTOR 21 ; +: TIMER0_A1_VECTOR 22 ; +: TIMER0_A0_VECTOR 23 ; + |