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-rw-r--r--msp430/alee-msp430.cpp149
1 files changed, 95 insertions, 54 deletions
diff --git a/msp430/alee-msp430.cpp b/msp430/alee-msp430.cpp
index b983900..51f63f8 100644
--- a/msp430/alee-msp430.cpp
+++ b/msp430/alee-msp430.cpp
@@ -16,50 +16,63 @@
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
-#include "alee.hpp"
-#include "libalee/ctype.hpp"
+#include "libalee/alee.hpp"
#include "lzss.h"
static const
#include "msp430fr2476_all.h"
-#include <cstring>
#include <msp430.h>
#include "splitmemdictrw.hpp"
-alignas(sizeof(Cell))
-__attribute__((section(".lodict")))
-#include "core.fth.h"
-
static char strbuf[80];
static void readchar(State& state);
static void serput(int c);
static void serputs(const char *s);
-static void printint(DoubleCell n, char *buf);
+static void printint(DoubleCell n, char *buf, int base);
+
static Error findword(State&, Word);
static void initGPIO();
static void initClock();
static void initUART();
static void Software_Trim();
-#define MCLK_FREQ_MHZ (8) // MCLK = 8MHz
+#define MCLK_FREQ_MHZ (16)
+
+static void alee_main();
-//__attribute__((section(".hidict")))
-//static uint8_t hidict[16384];
+#define ALEE_RODICTSIZE (9088)
+__attribute__((section(".lodict")))
+#include "core.fth.h"
-static bool inISR = false;
+static bool exitLpm;
static Addr isr_list[24] = {};
-static SplitMemDictRW<sizeof(alee_dat), 16384> dict (alee_dat, 0x10000);
+
+using DictType = SplitMemDictRW<ALEE_RODICTSIZE, 32767>;
+extern char __dict[sizeof(DictType)];
+static auto& dict = *(new (__dict) DictType (alee_dat, 0x10000));
int main()
{
WDTCTL = WDTPW | WDTHOLD;
+
+ extern char __libaleebegin;
+ extern char __libaleeend;
+ extern char __libaleedst;
+ std::copy(&__libaleebegin, &__libaleeend, &__libaleedst);
+
initGPIO();
initClock();
initUART();
SYSCFG0 = FRWPPW;
+ alee_main();
+}
+
+LIBALEE_SECTION
+void alee_main()
+{
(void)alee_dat_len;
State state (dict, readchar);
Parser::customParse = findword;
@@ -105,6 +118,7 @@ int main()
}
}
+LIBALEE_SECTION
void readchar(State& state)
{
auto idx = state.dict.read(Dictionary::Input);
@@ -117,20 +131,25 @@ void readchar(State& state)
state.dict.writebyte(addr, c ? c : ' ');
}
+LIBALEE_SECTION
void serput(int c)
{
while (!(UCA0IFG & UCTXIFG));
UCA0TXBUF = static_cast<char>(c);
}
+LIBALEE_SECTION
void serputs(const char *s)
{
while (*s)
serput(*s++);
}
-void printint(DoubleCell n, char *buf)
+LIBALEE_SECTION
+void printint(DoubleCell n, char *buf, int base)
{
+ static const char digit[] = "0123456789ABCDEF";
+
char *ptr = buf;
bool neg = n < 0;
@@ -138,8 +157,8 @@ void printint(DoubleCell n, char *buf)
n = -n;
do {
- *ptr++ = static_cast<char>((n % 10) + '0');
- } while ((n /= 10));
+ *ptr++ = digit[n % base];
+ } while ((n /= base));
if (neg)
serput('-');
@@ -150,11 +169,12 @@ void printint(DoubleCell n, char *buf)
serput(' ');
}
+LIBALEE_SECTION
void user_sys(State& state)
{
switch (state.pop()) {
case 0: // .
- printint(state.pop(), strbuf);
+ printint(state.pop(), strbuf, state.dict.read(Dictionary::Base));
break;
case 1: // unused
state.push(static_cast<Addr>(state.dict.capacity() - state.dict.here()));
@@ -181,16 +201,18 @@ void user_sys(State& state)
state.push(*reinterpret_cast<uint16_t *>(state.pop()));
break;
case 15:
- if (!inISR)
- _bis_SR_register(state.pop());
- else
- _bis_SR_register_on_exit(state.pop());
+ _bis_SR_register(state.pop());
break;
case 16:
- if (!inISR)
- _bic_SR_register(state.pop());
- else
- _bic_SR_register_on_exit(state.pop());
+ _bic_SR_register(state.pop());
+ break;
+ case 17:
+ exitLpm |= true;
+ break;
+ case 50:
+ Parser::customParse = nullptr;
+ extern char _etext;
+ state.push((Addr)&_etext);
break;
default:
break;
@@ -199,14 +221,14 @@ void user_sys(State& state)
#define LZSS_MAGIC_SEPARATOR (0xFB)
-static char lzword[32];
+static uint8_t lzword[32];
static int lzwlen;
-static char lzbuf[32];
-static char *lzptr;
+static uint8_t lzbuf[32];
+static uint8_t *lzptr;
Error findword(State& state, Word word)
{
- char *ptr = lzword;
+ uint8_t *ptr = lzword;
for (auto it = word.begin(&state.dict); it != word.end(&state.dict); ++it) {
*ptr = *it;
if (islower(*ptr))
@@ -220,9 +242,9 @@ Error findword(State& state, Word word)
auto ret = decode([](int c) {
if (c != LZSS_MAGIC_SEPARATOR) {
- *lzptr++ = (char)c;
+ *lzptr++ = (uint8_t)c;
} else {
- if (lzwlen == lzptr - lzbuf - 2 && strncmp(lzword, lzbuf, lzptr - lzbuf - 2) == 0) {
+ if (lzwlen == lzptr - lzbuf - 2 && std::equal(lzbuf, lzptr - 2, lzword)) {
lzwlen = (*(lzptr - 2) << 8) | *(lzptr - 1);
return 1;
} else {
@@ -267,35 +289,47 @@ void initGPIO()
void initClock()
{
- __bis_SR_register(SCG0); // disable FLL
- CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source
- CSCTL1 = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_3;// DCOFTRIM=3, DCO Range = 8MHz
- CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz
+ static_assert(MCLK_FREQ_MHZ == 16);
+
+ // Configure one FRAM waitstate as required by the device datasheet for MCLK
+ // operation beyond 8MHz _before_ configuring the clock system.
+ FRCTL0 = FRCTLPW | NWAITS_1;
+
+ P2SEL0 |= BIT0 | BIT1; // P2.0~P2.1: crystal pins
+ do
+ {
+ CSCTL7 &= ~(XT1OFFG | DCOFFG); // Clear XT1 and DCO fault flag
+ SFRIFG1 &= ~OFIFG;
+ } while (SFRIFG1 & OFIFG); // Test oscillator fault flag
+
+ __bis_SR_register(SCG0); // disable FLL
+ CSCTL3 |= SELREF__XT1CLK; // Set XT1 as FLL reference source
+ CSCTL1 = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_5;// DCOFTRIM=5, DCO Range = 16MHz
+ CSCTL2 = FLLD_0 + 487; // DCOCLKDIV = 16MHz
__delay_cycles(3);
- __bic_SR_register(SCG0); // enable FLL
- Software_Trim(); // Software Trim to get the best DCOFTRIM value
+ __bic_SR_register(SCG0); // enable FLL
+ Software_Trim(); // Software Trim to get the best DCOFTRIM value
+
+ CSCTL4 = SELMS__DCOCLKDIV | SELA__XT1CLK; // set XT1 (~32768Hz) as ACLK source, ACLK = 32768Hz
+ // default DCOCLKDIV as MCLK and SMCLK source
- CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
- // default DCODIV as MCLK and SMCLK source
}
void initUART()
{
// Configure UART pins
- P5SEL0 |= BIT1 | BIT2; // set 2-UART pin as second function
- SYSCFG3|=USCIA0RMP; //Set the remapping source
- // Configure UART
+ P5SEL0 |= BIT1 | BIT2;
+ SYSCFG3 |= USCIA0RMP; // Set the remapping source
+
UCA0CTLW0 |= UCSWRST;
- UCA0CTLW0 |= UCSSEL__SMCLK;
+ UCA0CTLW0 |= UCSSEL__SMCLK; // 16 MHz
// Baud Rate calculation
- // 8000000/(16*9600) = 52.083
- // Fractional portion = 0.083
- // User's Guide Table 17-4: UCBRSx = 0x49
- // UCBRFx = int ( (52.083-52)*16) = 1
- UCA0BR0 = 52; // 8000000/16/9600
- UCA0BR1 = 0x00;
- UCA0MCTLW = 0x4900 | UCOS16 | UCBRF_1;
+ // N = 16MHz / 115200 = 138.888
+ // OS16 = 1, UCBRx = INT(N/16) = 8(.6806)
+ // UCBRFx = INT( ((N/16) - UCBRx) * 16) = 10(.8896)
+ UCA0BRW = 8;
+ UCA0MCTLW = 0xD600 | 0x00A0 | UCOS16;
UCA0CTLW0 &= ~UCSWRST; // Initialize eUSCI
}
@@ -369,21 +403,25 @@ void Software_Trim()
while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked
}
-void alee_isr_handle(unsigned index)
+bool alee_isr_handle(unsigned index)
{
const Addr isr = isr_list[index];
if (isr != 0) {
State isrstate (dict, readchar);
- inISR = true;
+ exitLpm = false;
isrstate.execute(isr);
- inISR = false;
+ return exitLpm;
}
+
+ return false;
}
#define DEFINE_ISR(VVV, III) \
__attribute__((interrupt(VVV))) \
- void VVV##_ISR() { alee_isr_handle(III); }
+ void VVV##_ISR() { \
+ if (alee_isr_handle(III)) \
+ _low_power_mode_off_on_exit(); }
DEFINE_ISR(ECOMP0_VECTOR, 0)
DEFINE_ISR(PORT6_VECTOR, 1)
@@ -410,3 +448,6 @@ DEFINE_ISR(TIMER1_A0_VECTOR, 21)
DEFINE_ISR(TIMER0_A1_VECTOR, 22)
DEFINE_ISR(TIMER0_A0_VECTOR, 23)
+// Override newlib's free to save hundreds of bytes
+extern "C" void free(void *) {}
+
generated by cgit v1.2.3 (git 2.39.1) at 2025-04-05 09:56:07 +0000