From 12fa2716dbc3ea80c833411b12fe403421cebb00 Mon Sep 17 00:00:00 2001 From: Clyne Sullivan Date: Thu, 25 Jan 2018 11:00:18 -0500 Subject: hardware float support --- src/system_stm32l4xx.c | 44 -------------------------------------------- 1 file changed, 44 deletions(-) delete mode 100644 src/system_stm32l4xx.c (limited to 'src/system_stm32l4xx.c') diff --git a/src/system_stm32l4xx.c b/src/system_stm32l4xx.c deleted file mode 100644 index 4c22bfe..0000000 --- a/src/system_stm32l4xx.c +++ /dev/null @@ -1,44 +0,0 @@ -#include "stm32l476xx.h" - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000U; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= 0xEAF6FFFFU; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000U; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000U; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -- cgit v1.2.3