From b8585da5c8f8a1889de3309b5ae1186fc720ddd9 Mon Sep 17 00:00:00 2001
From: Clyne Sullivan <clyne@bitgloo.com>
Date: Mon, 3 Apr 2023 13:28:10 -0400
Subject: [PATCH] add upload target; fix indentation

---
 00-80mhz/main.c | 86 ++++++++++++++++++++++++-------------------------
 common/rules.mk | 20 +++++++++---
 2 files changed, 58 insertions(+), 48 deletions(-)

diff --git a/00-80mhz/main.c b/00-80mhz/main.c
index b343bf7..a69aceb 100644
--- a/00-80mhz/main.c
+++ b/00-80mhz/main.c
@@ -2,48 +2,48 @@
 
 int main(void)
 {
-        // Disable interrupts
-	asm("cpsid i");
-
-	// Running at 80MHz requires configuring flash wait-states:
-	FLASH->ACR = (FLASH->ACR & ~(FLASH_ACR_LATENCY)) | FLASH_ACR_LATENCY_4WS;
-
-        // Configure the PLL to output 80MHz:
-        //  1. MSI clock is 4MHz at reset, use MSI as source for PLL
-        //  2. Set PLLN multiplier to 40: 4MHz * 40 = 160MHz
-        //  3. PLLM divider is set to zero, no division there
-        //  4. Set PLLR system clock divider to zero = division by two
-        //     160MHz / 2 = 80MHz
-        RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_MSI |
-                       (40 << RCC_PLLCFGR_PLLN_Pos) |
-                       (0 << RCC_PLLCFGR_PLLR_Pos) |
-                       RCC_PLLCFGR_PLLREN;
-
-        // Enable the PLL
-	RCC->CR |= RCC_CR_PLLON;
-	while ((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY);
-
-        // Set the system clock to use PLL
-        // Also clear the HPRE divider to be safe 
-	RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_HPRE_Msk | RCC_CFGR_SW_Msk)) |
-	            RCC_CFGR_SW_PLL;
-	while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);
-
-        // The processor is now running at 80MHz!
-
-        // Enable MCO to output the system clock over PA8
-        RCC->CFGR &= ~(RCC_CFGR_MCOPRE_Msk);
-        RCC->CFGR |= 2 << RCC_CFGR_MCOSEL_Pos;
-
-        // Configure PA8 for alternate function zero (MCO)
-        RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
-        GPIOA->MODER &= ~(GPIO_MODER_MODE8_Msk);
-        GPIOA->MODER |= 2 << GPIO_MODER_MODE8_Pos;
-        GPIOA->AFR[1] &= ~(GPIO_AFRH_AFSEL8_Msk);
-
-        // Using a volatile assembly instruction ensures that this loop is not
-        // optimized away by the compiler.
-	while (1)
-            asm volatile("nop");
+    // Disable interrupts
+    asm("cpsid i");
+
+    // Running at 80MHz requires configuring flash wait-states:
+    FLASH->ACR = (FLASH->ACR & ~(FLASH_ACR_LATENCY)) | FLASH_ACR_LATENCY_4WS;
+
+    // Configure the PLL to output 80MHz:
+    //  1. MSI clock is 4MHz at reset, use MSI as source for PLL
+    //  2. Set PLLN multiplier to 40: 4MHz * 40 = 160MHz
+    //  3. PLLM divider is set to zero, no division there
+    //  4. Set PLLR system clock divider to zero = division by two
+    //     160MHz / 2 = 80MHz
+    RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_MSI |
+                   (40 << RCC_PLLCFGR_PLLN_Pos) |
+                   (0 << RCC_PLLCFGR_PLLR_Pos) |
+                   RCC_PLLCFGR_PLLREN;
+
+    // Enable the PLL
+    RCC->CR |= RCC_CR_PLLON;
+    while ((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY);
+
+    // Set the system clock to use PLL
+    // Also clear the HPRE divider to be safe
+    RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_HPRE_Msk | RCC_CFGR_SW_Msk)) |
+                RCC_CFGR_SW_PLL;
+    while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);
+
+    // The processor is now running at 80MHz!
+
+    // Enable MCO to output the system clock over PA8
+    RCC->CFGR &= ~(RCC_CFGR_MCOPRE_Msk);
+    RCC->CFGR |= 2 << RCC_CFGR_MCOSEL_Pos;
+
+    // Configure PA8 for alternate function zero (MCO)
+    RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
+    GPIOA->MODER &= ~(GPIO_MODER_MODE8_Msk);
+    GPIOA->MODER |= 2 << GPIO_MODER_MODE8_Pos;
+    GPIOA->AFR[1] &= ~(GPIO_AFRH_AFSEL8_Msk);
+
+    // Using a volatile assembly instruction ensures that this loop is not
+    // optimized away by the compiler.
+    while (1)
+        asm volatile("nop");
 }
 
diff --git a/common/rules.mk b/common/rules.mk
index 9a7494c..8eda63a 100644
--- a/common/rules.mk
+++ b/common/rules.mk
@@ -1,7 +1,9 @@
-CC := arm-none-eabi-gcc
 AS := arm-none-eabi-as
+CC := arm-none-eabi-gcc
+OBJCOPY := arm-none-eabi-objcopy
 
 OUTFILE := main.out
+HEXFILE := $(subst .out,.hex,$(OUTFILE))
 
 MCUFLAGS := -mthumb -mcpu=cortex-m4 #-mfloat-abi=hard -mfpu=fpv4-sp-d16
 AFLAGS = $(MCUFLAGS) 
@@ -16,23 +18,31 @@ CFILES += $(wildcard $(COMMON_DIR)/*.c) \
 
 OFILES := $(patsubst %.c, %.o, $(patsubst %.s, %.o, $(CFILES)))
 
-.PHONY: all clean
+.PHONY: all upload clean
 
 all: $(OUTFILE)
 
+upload: $(HEXFILE)
+	@openocd -f interface/stlink.cfg -f target/stm32l4x.cfg \
+	         -c "program $(HEXFILE) verify reset exit"
+
 clean:
 	@echo "  CLEAN"
 	@rm -f $(OUTFILE) $(OFILES)
 
+$(HEXFILE): $(OUTFILE)
+	@echo "  OBJCOPY " $@
+	@$(OBJCOPY) -O ihex $< $@
+
 $(OUTFILE): $(OFILES)
-	@echo "  CC     " $@
+	@echo "  CC      " $@
 	@$(CC) $(CFLAGS) $(LDFLAGS) $(OFILES) -o $@
 
 %.o: %.c
-	@echo "  CC     " $<
+	@echo "  CC      " $<
 	@$(CC) $(CFLAGS) -c $< -o $@
 
 %.o: %.s
-	@echo "  AS     " $<
+	@echo "  AS      " $<
 	@$(AS) $(AFLAGS) -c $< -o $@