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authorClyne Sullivan <clyne@bitgloo.com>2021-09-17 07:26:50 -0400
committerClyne Sullivan <clyne@bitgloo.com>2021-09-17 07:26:50 -0400
commitc61598fe95bb188ca28f1710dd8a42907bb797cb (patch)
tree42be7889b8e873775ef656ddae98cb2e6b5e4b3e /cfg/mcuconf.h
parent6790246c3c731e88094161a594c9c70a3f7903f4 (diff)
use rtc for timing
Diffstat (limited to 'cfg/mcuconf.h')
-rw-r--r--cfg/mcuconf.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/cfg/mcuconf.h b/cfg/mcuconf.h
index 217d13f..96e9080 100644
--- a/cfg/mcuconf.h
+++ b/cfg/mcuconf.h
@@ -44,22 +44,22 @@
#define STM32_PLS STM32_PLS_LEV4
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI16_DIVIDER_ENABLED FALSE
-#define STM32_LSI_ENABLED FALSE
+#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_ADC_CLOCK_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_SW STM32_SW_MSI
-#define STM32_PLLSRC STM32_PLLSRC_HSI16
-#define STM32_PLLMUL_VALUE 3
-#define STM32_PLLDIV_VALUE 4
+#define STM32_PLLSRC STM32_PLLSRC_NONE
+#define STM32_PLLMUL_VALUE 1
+#define STM32_PLLDIV_VALUE 8
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
-#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
-#define STM32_RTCPRE STM32_RTCPRE_DIV2
+#define STM32_RTCSEL STM32_RTCSEL_LSI // ~37kHz
+#define STM32_RTCPRE STM32_RTCPRE_DIV2 // HSE only!
#define STM32_USART2SEL STM32_USART2SEL_APB
#define STM32_LPUART1SEL STM32_LPUART1SEL_APB
#define STM32_I2C1SEL STM32_I2C1SEL_APB