From c61598fe95bb188ca28f1710dd8a42907bb797cb Mon Sep 17 00:00:00 2001 From: Clyne Sullivan Date: Fri, 17 Sep 2021 07:26:50 -0400 Subject: use rtc for timing --- cfg/chconf.h | 14 +++++++------- cfg/halconf.h | 2 +- cfg/mcuconf.h | 12 ++++++------ 3 files changed, 14 insertions(+), 14 deletions(-) (limited to 'cfg') diff --git a/cfg/chconf.h b/cfg/chconf.h index dc2ccc1..25d444a 100644 --- a/cfg/chconf.h +++ b/cfg/chconf.h @@ -451,11 +451,11 @@ * @note This macro can be used to activate a power saving mode. */ #define CH_CFG_IDLE_ENTER_HOOK() { \ - RCC->ICSCR = (RCC->ICSCR & ~RCC_ICSCR_MSIRANGE_Msk); \ - while (!(RCC->CR & RCC_CR_MSIRDY)); \ - PWR->CR &= ~PWR_CR_LPRUN; \ - PWR->CR |= PWR_CR_LPRUN; \ } +// RCC->ICSCR = (RCC->ICSCR & ~RCC_ICSCR_MSIRANGE_Msk); +// while (!(RCC->CR & RCC_CR_MSIRDY)); +// PWR->CR &= ~PWR_CR_LPRUN; +// PWR->CR |= PWR_CR_LPRUN; /** * @brief Idle thread leave hook. @@ -464,10 +464,10 @@ * @note This macro can be used to deactivate a power saving mode. */ #define CH_CFG_IDLE_LEAVE_HOOK() { \ - RCC->ICSCR |= 6 << RCC_ICSCR_MSIRANGE_Pos; \ - while (!(RCC->CR & RCC_CR_MSIRDY)); \ - PWR->CR &= ~PWR_CR_LPRUN; \ } +// RCC->ICSCR |= 6 << RCC_ICSCR_MSIRANGE_Pos; +// while (!(RCC->CR & RCC_CR_MSIRDY)); +// PWR->CR &= ~PWR_CR_LPRUN; /** * @brief System halt hook. diff --git a/cfg/halconf.h b/cfg/halconf.h index 5cdb5e0..6688b95 100644 --- a/cfg/halconf.h +++ b/cfg/halconf.h @@ -128,7 +128,7 @@ * @brief Enables the RTC subsystem. */ #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE +#define HAL_USE_RTC TRUE #endif /** diff --git a/cfg/mcuconf.h b/cfg/mcuconf.h index 217d13f..96e9080 100644 --- a/cfg/mcuconf.h +++ b/cfg/mcuconf.h @@ -44,22 +44,22 @@ #define STM32_PLS STM32_PLS_LEV4 #define STM32_HSI16_ENABLED TRUE #define STM32_HSI16_DIVIDER_ENABLED FALSE -#define STM32_LSI_ENABLED FALSE +#define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED FALSE #define STM32_LSE_ENABLED FALSE #define STM32_ADC_CLOCK_ENABLED TRUE #define STM32_MSIRANGE STM32_MSIRANGE_4M #define STM32_SW STM32_SW_MSI -#define STM32_PLLSRC STM32_PLLSRC_HSI16 -#define STM32_PLLMUL_VALUE 3 -#define STM32_PLLDIV_VALUE 4 +#define STM32_PLLSRC STM32_PLLSRC_NONE +#define STM32_PLLMUL_VALUE 1 +#define STM32_PLLDIV_VALUE 8 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV1 #define STM32_PPRE2 STM32_PPRE2_DIV1 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOPRE STM32_MCOPRE_DIV1 -#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK -#define STM32_RTCPRE STM32_RTCPRE_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI // ~37kHz +#define STM32_RTCPRE STM32_RTCPRE_DIV2 // HSE only! #define STM32_USART2SEL STM32_USART2SEL_APB #define STM32_LPUART1SEL STM32_LPUART1SEL_APB #define STM32_I2C1SEL STM32_I2C1SEL_APB -- cgit v1.2.3