upload initial port

4 files changed, 487 insertions, 0 deletions

diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/boot.S b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/boot.S
new file mode 100644
index 0000000..04f297c
--- /dev/null
+++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/boot.S
@@ -0,0 +1,192 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    SPC563Mxx/boot.s

+ * @brief   SPC563Mxx boot-related code.

+ *

+ * @addtogroup PPC_BOOT

+ * @{

+ */

+

+#include "boot.h"

+

+#if defined(__HIGHTEC__)

+#define se_bge bge

+#endif

+

+#if !defined(__DOXYGEN__)

+

+        /* BAM record.*/

+        .section    .boot, "ax"

+

+#if BOOT_USE_VLE

+        .long       0x015A0000

+#else

+        .long       0x005A0000

+#endif

+        .long       _reset_address

+

+        .align      2

+        .globl      _reset_address

+        .type       _reset_address, @function

+_reset_address:

+#if BOOT_PERFORM_CORE_INIT

+        e_bl        _coreinit

+#endif

+        e_bl        _ivinit

+

+#if BOOT_RELOCATE_IN_RAM

+        /*

+         * Image relocation in RAM.

+         */

+        e_lis       r4, __ram_reloc_start__@h

+        e_or2i      r4, __ram_reloc_start__@l

+        e_lis       r5, __ram_reloc_dest__@h

+        e_or2i      r5, __ram_reloc_dest__@l

+        e_lis       r6, __ram_reloc_end__@h

+        e_or2i      r6, r6, __ram_reloc_end__@l

+.relloop:

+        se_cmpl     r4, r6

+        se_bge      .relend

+        se_lwz      r7, 0(r4)

+        se_addi     r4, 4

+        se_stw      r7, 0(r5)

+        se_addi     r5, 4

+        se_b        .relloop

+.relend:

+        e_lis       r3, _boot_address@h

+        e_or2i      r3, _boot_address@l

+        mtctr       r3

+        se_bctrl

+#else

+        e_b         _boot_address

+#endif

+

+#if BOOT_PERFORM_CORE_INIT

+        .align      2

+_coreinit:

+        /*

+         * RAM clearing, this device requires a write to all RAM location in

+         * order to initialize the ECC detection hardware, this is going to

+         * slow down the startup but there is no way around.

+         */

+        xor         r0, r0, r0

+        xor         r1, r1, r1

+        xor         r2, r2, r2

+        xor         r3, r3, r3

+        xor         r4, r4, r4

+        xor         r5, r5, r5

+        xor         r6, r6, r6

+        xor         r7, r7, r7

+        xor         r8, r8, r8

+        xor         r9, r9, r9

+        xor         r10, r10, r10

+        xor         r11, r11, r11

+        xor         r12, r12, r12

+        xor         r13, r13, r13

+        xor         r14, r14, r14

+        xor         r15, r15, r15

+        xor         r16, r16, r16

+        xor         r17, r17, r17

+        xor         r18, r18, r18

+        xor         r19, r19, r19

+        xor         r20, r20, r20

+        xor         r21, r21, r21

+        xor         r22, r22, r22

+        xor         r23, r23, r23

+        xor         r24, r24, r24

+        xor         r25, r25, r25

+        xor         r26, r26, r26

+        xor         r27, r27, r27

+        xor         r28, r28, r28

+        xor         r29, r29, r29

+        xor         r30, r30, r30

+        xor         r31, r31, r31

+        e_lis       r4, __ram_start__@h

+        e_or2i      r4, __ram_start__@l

+        e_lis       r5, __ram_end__@h

+        e_or2i      r5, __ram_end__@l

+.cleareccloop:

+        se_cmpl     r4, r5

+        se_bge      .cleareccend

+        e_stmw      r16, 0(r4)

+        e_addi      r4, r4, 64

+        se_b        .cleareccloop

+.cleareccend:

+

+        /*

+         * Branch prediction enabled.

+         */

+        e_li        r3, BOOT_BUCSR_DEFAULT

+        mtspr       1013, r3       /* BUCSR */

+

+        se_blr

+#endif /* BOOT_PERFORM_CORE_INIT */

+

+        /*

+         * Exception vectors initialization.

+         */

+_ivinit:

+        /* MSR initialization.*/

+        e_lis       r3, BOOT_MSR_DEFAULT@h

+        e_or2i      r3, BOOT_MSR_DEFAULT@l

+        mtMSR       r3

+

+        /* IVPR initialization.*/

+        e_lis       r3, __ivpr_base__@h

+        e_or2i      r3, __ivpr_base__@l

+        mtIVPR      r3

+

+        /* IVORs initialization.*/

+        e_lis       r3, _unhandled_exception@h

+        e_or2i      r3, _unhandled_exception@l

+

+        mtspr       400, r3        /* IVOR0-15 */

+        mtspr       401, r3

+        mtspr       402, r3

+        mtspr       403, r3

+        mtspr       404, r3

+        mtspr       405, r3

+        mtspr       406, r3

+        mtspr       407, r3

+        mtspr       408, r3

+        mtspr       409, r3

+        mtspr       410, r3

+        mtspr       411, r3

+        mtspr       412, r3

+        mtspr       413, r3

+        mtspr       414, r3

+        mtspr       415, r3

+        mtspr       528, r3        /* IVOR32-34 */

+        mtspr       529, r3

+        mtspr       530, r3

+

+        se_blr

+

+        .section    .handlers, "ax"

+

+        /*

+         * Unhandled exceptions handler.

+         */

+        .weak       _unhandled_exception

+        .type       _unhandled_exception, @function

+_unhandled_exception:

+        se_b        _unhandled_exception

+

+#endif /* !defined(__DOXYGEN__) */

+

+/** @} */

diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/boot.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/boot.h
new file mode 100644
index 0000000..f9168f5
--- /dev/null
+++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/boot.h
@@ -0,0 +1,119 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    boot.h

+ * @brief   Boot parameters for the SPC563Mxx.

+ * @{

+ */

+

+#ifndef BOOT_H

+#define BOOT_H

+

+/*===========================================================================*/

+/* Module constants.                                                         */

+/*===========================================================================*/

+

+/**

+ * @name    BUCSR registers definitions

+ * @{

+ */

+#define BUCSR_BPEN              0x00000001

+#define BUCSR_BALLOC_BFI        0x00000200

+/** @} */

+

+/**

+ * @name   MSR register definitions

+ * @{

+ */

+#define MSR_UCLE                0x04000000

+#define MSR_SPE                 0x02000000

+#define MSR_WE                  0x00040000

+#define MSR_CE                  0x00020000

+#define MSR_EE                  0x00008000

+#define MSR_PR                  0x00004000

+#define MSR_FP                  0x00002000

+#define MSR_ME                  0x00001000

+#define MSR_FE0                 0x00000800

+#define MSR_DE                  0x00000200

+#define MSR_FE1                 0x00000100

+#define MSR_IS                  0x00000020

+#define MSR_DS                  0x00000010

+#define MSR_RI                  0x00000002

+/** @} */

+

+/*===========================================================================*/

+/* Module pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/*

+ * BUCSR default settings.

+ */

+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)

+#define BOOT_BUCSR_DEFAULT      (BUCSR_BPEN | BUCSR_BALLOC_BFI)

+#endif

+

+/*

+ * MSR default settings.

+ */

+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)

+#define BOOT_MSR_DEFAULT        (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)

+#endif

+

+/*

+ * Boot default settings.

+ */

+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)

+#define BOOT_PERFORM_CORE_INIT  1

+#endif

+

+/*

+ * VLE mode default settings.

+ */

+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)

+#define BOOT_USE_VLE            1

+#endif

+

+/*

+ * RAM relocation flag.

+ */

+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)

+#define BOOT_RELOCATE_IN_RAM    0

+#endif

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Module data structures and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Module macros.                                                            */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Module inline functions.                                                  */

+/*===========================================================================*/

+

+#endif /* BOOT_H */

+

+/** @} */

diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/intc.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/intc.h
new file mode 100644
index 0000000..c60b31c
--- /dev/null
+++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/intc.h
@@ -0,0 +1,93 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    SPC563Mxx/intc.h

+ * @brief   SPC563Mxx INTC module header.

+ *

+ * @addtogroup INTC

+ * @{

+ */

+

+#ifndef INTC_H

+#define INTC_H

+

+/*===========================================================================*/

+/* Module constants.                                                         */

+/*===========================================================================*/

+

+/**

+ * @name    INTC addresses

+ * @{

+ */

+#define INTC_BASE           0xFFF48000

+#define INTC_IACKR_ADDR     (INTC_BASE + 0x10)

+#define INTC_EOIR_ADDR      (INTC_BASE + 0x18)

+/** @} */

+

+/**

+ * @brief   INTC priority levels.

+ */

+#define INTC_PRIORITY_LEVELS 16U

+

+/*===========================================================================*/

+/* Module pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Module data structures and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Module macros.                                                            */

+/*===========================================================================*/

+

+/**

+ * @name    INTC-related macros

+ * @{

+ */

+#define INTC_BCR            (*((volatile uint32_t *)(INTC_BASE + 0)))

+#define INTC_CPR(n)         (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))

+#define INTC_IACKR(n)       (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))

+#define INTC_EOIR(n)        (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))

+#define INTC_PSR(n)         (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))

+/** @} */

+

+/**

+ * @brief   Core selection macros for PSR register.

+ */

+#define INTC_PSR_CORE0      0x00

+

+/**

+ * @brief   PSR register content helper

+ */

+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Module inline functions.                                                  */

+/*===========================================================================*/

+

+#endif /* INTC_H */

+

+/** @} */

diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/ppcparams.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/ppcparams.h
new file mode 100644
index 0000000..705e3fc
--- /dev/null
+++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/ppcparams.h
@@ -0,0 +1,83 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    SPC563Mxx/ppcparams.h

+ * @brief   PowerPC parameters for the SPC563Mxx.

+ *

+ * @defgroup PPC_SPC563Mxx SPC563Mxx Specific Parameters

+ * @ingroup PPC_SPECIFIC

+ * @details This file contains the PowerPC specific parameters for the

+ *          SPC563Mxx platform.

+ * @{

+ */

+

+#ifndef PPCPARAMS_H

+#define PPCPARAMS_H

+

+/**

+ * @brief   Family identification macro.

+ */

+#define PPC_SPC563Mxx

+

+/**

+ * @brief   PPC core model.

+ */

+#define PPC_VARIANT                 PPC_VARIANT_e200z3

+

+/**

+ * @brief   Number of cores.

+ */

+#define PPC_CORE_NUMBER             1

+

+/**

+ * @brief   Number of writable bits in IVPR register.

+ */

+#define PPC_IVPR_BITS               16

+

+/**

+ * @brief   IVORx registers support.

+ */

+#define PPC_SUPPORTS_IVORS          TRUE

+

+/**

+ * @brief   Book E instruction set support.

+ */

+#define PPC_SUPPORTS_BOOKE          TRUE

+

+/**

+ * @brief   VLE instruction set support.

+ */

+#define PPC_SUPPORTS_VLE            TRUE

+

+/**

+ * @brief   Supports VLS Load/Store Multiple Volatile instructions.

+ */

+#define PPC_SUPPORTS_VLE_MULTI      TRUE

+

+/**

+ * @brief   Supports the decrementer timer.

+ */

+#define PPC_SUPPORTS_DECREMENTER    TRUE

+

+/**

+ * @brief   Number of interrupt sources.

+ */

+#define PPC_NUM_VECTORS             360

+

+#endif /* PPCPARAMS_H */

+

+/** @} */