diff options
| author | Clyne Sullivan <clyne@bitgloo.com> | 2020-11-08 18:31:02 -0500 |
|---|---|---|
| committer | Clyne Sullivan <clyne@bitgloo.com> | 2020-11-08 18:31:02 -0500 |
| commit | e12639c46f0be29461803ffa1790d6f69c16d280 (patch) | |
| tree | 5195f6ce497d702cef57bd752a9ec5c054855a87 /cfg | |
| parent | f3e4d176d5922a13ce2615895cea1e197175984a (diff) | |
fixed sample rate setting
Diffstat (limited to 'cfg')
| -rw-r--r-- | cfg/chconf.h | 4 | ||||
| -rw-r--r-- | cfg/mcuconf.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/cfg/chconf.h b/cfg/chconf.h index 04570c1..faa8600 100644 --- a/cfg/chconf.h +++ b/cfg/chconf.h @@ -544,7 +544,7 @@ * @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS)
-#define CH_DBG_ENABLE_CHECKS FALSE
+#define CH_DBG_ENABLE_CHECKS TRUE
#endif
/**
@@ -556,7 +556,7 @@ * @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS)
-#define CH_DBG_ENABLE_ASSERTS FALSE
+#define CH_DBG_ENABLE_ASSERTS TRUE
#endif
/**
diff --git a/cfg/mcuconf.h b/cfg/mcuconf.h index 929e049..caad802 100644 --- a/cfg/mcuconf.h +++ b/cfg/mcuconf.h @@ -69,7 +69,7 @@ #define STM32_PLLSAI1R_VALUE 4
#define STM32_PLLSAI2N_VALUE 24
#define STM32_PLLSAI2P_VALUE 7
-#define STM32_PLLSAI2R_VALUE 2
+#define STM32_PLLSAI2R_VALUE 8
/*
* Peripherals clock sources.
@@ -88,7 +88,7 @@ #define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
-#define STM32_ADCSEL STM32_ADCSEL_PLLSAI1
+#define STM32_ADCSEL STM32_ADCSEL_PLLSAI2
#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
|