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authorClyne Sullivan <clyne@bitgloo.com>2021-03-10 19:42:18 -0500
committerClyne Sullivan <clyne@bitgloo.com>2021-03-10 19:42:18 -0500
commit1a7d45b9130251119874df8b15424ec41306d8f2 (patch)
tree6eadd9d6ef2f6ff3e4cf1854088deb8f882a0542 /source/sclock.cpp
parenteeeb04fa1a202c68279d4b4ee0a1e3ff34c62c7f (diff)
support H7 and L4; use second ADC for input
Diffstat (limited to 'source/sclock.cpp')
-rw-r--r--source/sclock.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/source/sclock.cpp b/source/sclock.cpp
index 795274d..198c684 100644
--- a/source/sclock.cpp
+++ b/source/sclock.cpp
@@ -5,19 +5,27 @@ unsigned int SClock::m_div = 1;
unsigned int SClock::m_runcount = 0;
const GPTConfig SClock::m_timer_config = {
+#if defined(TARGET_PLATFORM_H7)
.frequency = 4800000,
+#else
+ .frequency = 36000000,
+#endif
.callback = nullptr,
.cr2 = TIM_CR2_MMS_1, /* TRGO */
.dier = 0
};
const std::array<unsigned int, 6> SClock::m_rate_divs = {{
+#if defined(TARGET_PLATFORM_H7)
/* 8k */ 600,
/* 16k */ 300,
/* 20k */ 240,
/* 32k */ 150,
/* 48k */ 100,
/* 96k */ 50
+#else
+ 4500, 2250, 1800, 1125, 750, 375
+#endif
}};
void SClock::begin()