diff options
Diffstat (limited to 'ChibiOS_20.3.2/os/common/startup')
223 files changed, 34300 insertions, 0 deletions
diff --git a/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/crt0.S b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/crt0.S new file mode 100644 index 0000000..d496e28 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/crt0.S @@ -0,0 +1,123 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file crt0.S
+ * @brief Generic ARM startup file.
+ *
+ * @addtogroup ARM_GCC_STARTUP
+ * @{
+ */
+
+#if !defined(__DOXYGEN__)
+
+ .set MODE_USR, 0x10
+ .set MODE_FIQ, 0x11
+ .set MODE_IRQ, 0x12
+ .set MODE_SVC, 0x13
+ .set MODE_ABT, 0x17
+ .set MODE_UND, 0x1B
+ .set MODE_SYS, 0x1F
+
+ .set I_BIT, 0x80
+ .set F_BIT, 0x40
+
+ .text
+ .code 32
+ .balign 4
+
+/*
+ * Reset handler.
+ */
+ .global Reset_Handler
+Reset_Handler:
+ /*
+ * Stack pointers initialization.
+ */
+ ldr r0, =__stacks_end__
+ /* Undefined */
+ msr CPSR_c, #MODE_UND | I_BIT | F_BIT
+ mov sp, r0
+ ldr r1, =__und_stack_size__
+ sub r0, r0, r1
+ /* Abort */
+ msr CPSR_c, #MODE_ABT | I_BIT | F_BIT
+ mov sp, r0
+ ldr r1, =__abt_stack_size__
+ sub r0, r0, r1
+ /* FIQ */
+ msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
+ mov sp, r0
+ ldr r1, =__fiq_stack_size__
+ sub r0, r0, r1
+ /* IRQ */
+ msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT
+ mov sp, r0
+ ldr r1, =__irq_stack_size__
+ sub r0, r0, r1
+ /* Supervisor */
+ msr CPSR_c, #MODE_SVC | I_BIT | F_BIT
+ mov sp, r0
+ ldr r1, =__svc_stack_size__
+ sub r0, r0, r1
+ /* System */
+ msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
+ mov sp, r0
+// ldr r1, =__sys_stack_size__
+// sub r0, r0, r1
+ /*
+ * Early initialization.
+ */
+ bl __early_init
+
+ /*
+ * Data initialization.
+ * NOTE: It assumes that the DATA size is a multiple of 4.
+ */
+ ldr r1, =__textdata_base__
+ ldr r2, =__data_base__
+ ldr r3, =__data_end__
+dataloop:
+ cmp r2, r3
+ ldrlo r0, [r1], #4
+ strlo r0, [r2], #4
+ blo dataloop
+ /*
+ * BSS initialization.
+ * NOTE: It assumes that the BSS size is a multiple of 4.
+ */
+ mov r0, #0
+ ldr r1, =__bss_base__
+ ldr r2, =__bss_end__
+bssloop:
+ cmp r1, r2
+ strlo r0, [r1], #4
+ blo bssloop
+ /*
+ * Late initialization.
+ */
+ bl __core_init
+ bl __late_init
+
+ /*
+ * Main program invocation.
+ */
+ bl main
+ b __default_exit
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/crt1.c b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/crt1.c new file mode 100644 index 0000000..846bc1f --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/crt1.c @@ -0,0 +1,84 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/compilers/GCC/crt1.c
+ * @brief Startup stub functions.
+ *
+ * @addtogroup ARMCMx_GCC_STARTUP
+ * @{
+ */
+
+#include <stdbool.h>
+
+/**
+ * @brief Architecture-dependent core initialization.
+ * @details This hook is invoked immediately after the stack initialization
+ * and before the DATA and BSS segments initialization.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __core_init(void) {}
+
+/**
+ * @brief Early initialization.
+ * @details This hook is invoked immediately after the stack initialization
+ * and before the DATA and BSS segments initialization. The
+ * default behavior is to do nothing.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __early_init(void) {}
+/*lint -restore*/
+
+/**
+ * @brief Late initialization.
+ * @details This hook is invoked after the DATA and BSS segments
+ * initialization and before any static constructor. The
+ * default behavior is to do nothing.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __late_init(void) {}
+/*lint -restore*/
+
+/**
+ * @brief Default @p main() function exit handler.
+ * @details This handler is invoked or the @p main() function exit. The
+ * default behavior is to enter an infinite loop.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((noreturn, weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __default_exit(void) {
+/*lint -restore*/
+
+ while (true) {
+ }
+}
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/ld/LPC2148.ld b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/ld/LPC2148.ld new file mode 100644 index 0000000..335e216 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/ld/LPC2148.ld @@ -0,0 +1,43 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * LPC2148 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 512k - 12k
+ ram0 : org = 0x40000200, len = 32k - 0x200 - 288
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* RAM region to be used for stacks. This stack accommodates the processing
+ of all exceptions and interrupts*/
+REGION_ALIAS("STACKS_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/ld/rules.ld b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/ld/rules.ld new file mode 100644 index 0000000..79d5634 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/ld/rules.ld @@ -0,0 +1,237 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__;
+
+__ram0_base__ = ORIGIN(ram0);
+__ram0_size__ = LENGTH(ram0);
+__ram0_end__ = __ram0_base__ + __ram0_size__;
+__ram1_base__ = ORIGIN(ram1);
+__ram1_size__ = LENGTH(ram1);
+__ram1_end__ = __ram1_base__ + __ram1_size__;
+__ram2_base__ = ORIGIN(ram2);
+__ram2_size__ = LENGTH(ram2);
+__ram2_end__ = __ram2_base__ + __ram2_size__;
+__ram3_base__ = ORIGIN(ram3);
+__ram3_size__ = LENGTH(ram3);
+__ram3_end__ = __ram3_base__ + __ram3_size__;
+__ram4_base__ = ORIGIN(ram4);
+__ram4_size__ = LENGTH(ram4);
+__ram4_end__ = __ram4_base__ + __ram4_size__;
+__ram5_base__ = ORIGIN(ram5);
+__ram5_size__ = LENGTH(ram5);
+__ram5_end__ = __ram5_base__ + __ram5_size__;
+__ram6_base__ = ORIGIN(ram6);
+__ram6_size__ = LENGTH(ram6);
+__ram6_end__ = __ram6_base__ + __ram6_size__;
+__ram7_base__ = ORIGIN(ram7);
+__ram7_size__ = LENGTH(ram7);
+__ram7_end__ = __ram7_base__ + __ram7_size__;
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ . = 0;
+ _text = .;
+
+ startup : ALIGN(16)
+ {
+ KEEP(*(.vectors))
+ KEEP(*(.boot))
+ } > flash
+
+ constructors : ALIGN(4)
+ {
+ PROVIDE(__init_array_base__ = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE(__init_array_end__ = .);
+ } > flash
+
+ destructors : ALIGN(4)
+ {
+ PROVIDE(__fini_array_base__ = .);
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ PROVIDE(__fini_array_end__ = .);
+ } > flash
+
+ .text : ALIGN_WITH_INPUT
+ {
+ __text_base__ = .;
+ *(.text)
+ *(.text.*)
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ __text_end__ = .;
+ } > flash
+
+ .rodata : ALIGN(4)
+ {
+ __rodata_base__ = .;
+ *(.rodata)
+ *(.rodata.*)
+ . = ALIGN(4);
+ __rodata_end__ = .;
+ } > flash
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ .ARM.exidx : {
+ __exidx_base__ = .;
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end__ = .;
+ __exidx_end = .;
+ } > flash
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > flash
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > flash
+
+ .textalign : ONLY_IF_RO
+ {
+ . = ALIGN(8);
+ } > flash
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .stacks (NOLOAD) :
+ {
+ . = ALIGN(8);
+ __stacks_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __stacks_total_size__;
+ . = ALIGN(8);
+ __stacks_end__ = .;
+ } > STACKS_RAM
+
+ .data : ALIGN(4)
+ {
+ . = ALIGN(4);
+ PROVIDE(_data = .);
+ __textdata_base__ = LOADADDR(.data);
+ __data_base__ = .;
+ *(.data)
+ *(.data.*)
+ *(.ramtext)
+ . = ALIGN(4);
+ PROVIDE(_edata = .);
+ __data_end__ = .;
+ } > DATA_RAM AT > flash
+
+ .bss (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ __bss_base__ = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ . = ALIGN(4);
+ __bss_end__ = .;
+ PROVIDE(end = .);
+ } > BSS_RAM
+
+ .ram0 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ *(.ram0)
+ *(.ram0.*)
+ . = ALIGN(4);
+ __ram0_free__ = .;
+ } > ram0
+
+ .ram1 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ *(.ram1)
+ *(.ram1.*)
+ . = ALIGN(4);
+ __ram1_free__ = .;
+ } > ram1
+
+ .ram2 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ *(.ram2)
+ *(.ram2.*)
+ . = ALIGN(4);
+ __ram2_free__ = .;
+ } > ram2
+
+ .ram3 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ *(.ram3)
+ *(.ram3.*)
+ . = ALIGN(4);
+ __ram3_free__ = .;
+ } > ram3
+
+ .ram4 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ *(.ram4)
+ *(.ram4.*)
+ . = ALIGN(4);
+ __ram4_free__ = .;
+ } > ram4
+
+ .ram5 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ *(.ram5)
+ *(.ram5.*)
+ . = ALIGN(4);
+ __ram5_free__ = .;
+ } > ram5
+
+ .ram6 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ *(.ram6)
+ *(.ram6.*)
+ . = ALIGN(4);
+ __ram6_free__ = .;
+ } > ram6
+
+ .ram7 (NOLOAD) : ALIGN(4)
+ {
+ . = ALIGN(4);
+ *(.ram7)
+ *(.ram7.*)
+ . = ALIGN(4);
+ __ram7_free__ = .;
+ } > ram7
+}
+
+/* Heap default boundaries, it is defaulted to be the non-used part
+ of ram0 region.*/
+__heap_base__ = __ram0_free__;
+__heap_end__ = __ram0_end__;
diff --git a/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/mk/startup_lpc214x.mk b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/mk/startup_lpc214x.mk new file mode 100644 index 0000000..6ba1593 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/mk/startup_lpc214x.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS generic LPC214x file.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARM/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARM/compilers/GCC/vectors.S \
+ $(CHIBIOS)/os/common/startup/ARM/compilers/GCC/crt0.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ ${CHIBIOS}/os/common/startup/ARM/devices/LPC214x
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/ARM/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/rules.mk b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/rules.mk new file mode 100644 index 0000000..a7c7883 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/rules.mk @@ -0,0 +1,352 @@ +# ARM Cortex-Mx common makefile scripts and rules.
+
+##############################################################################
+# Processing options coming from the upper Makefile.
+#
+
+# Compiler options
+OPT = $(USE_OPT)
+COPT = $(USE_COPT)
+CPPOPT = $(USE_CPPOPT)
+
+# Garbage collection
+ifeq ($(USE_LINK_GC),yes)
+ OPT += -ffunction-sections -fdata-sections -fno-common
+ LDOPT := ,--gc-sections
+else
+ LDOPT :=
+endif
+
+# Linker extra options
+ifneq ($(USE_LDOPT),)
+ LDOPT := $(LDOPT),$(USE_LDOPT)
+endif
+
+# Link time optimizations
+ifeq ($(USE_LTO),yes)
+ OPT += -flto
+endif
+
+# Undefined state stack size
+ifeq ($(USE_UND_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__und_stack_size__=8
+else
+ LDOPT := $(LDOPT),--defsym=__und_stack_size__=$(USE_UND_STACKSIZE)
+endif
+
+# Abort stack size
+ifeq ($(USE_ABT_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__abt_stack_size__=8
+else
+ LDOPT := $(LDOPT),--defsym=__abt_stack_size__=$(USE_ABT_STACKSIZE)
+endif
+
+# FIQ stack size
+ifeq ($(USE_FIQ_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__fiq_stack_size__=64
+else
+ LDOPT := $(LDOPT),--defsym=__fiq_stack_size__=$(USE_FIQ_STACKSIZE)
+endif
+
+# IRQ stack size
+ifeq ($(USE_IRQ_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__irq_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__irq_stack_size__=$(USE_IRQ_STACKSIZE)
+endif
+
+# Supervisor stack size
+ifeq ($(USE_SUPERVISOR_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__svc_stack_size__=8
+else
+ LDOPT := $(LDOPT),--defsym=__svc_stack_size__=$(USE_SUPERVISOR_STACKSIZE)
+endif
+
+# System stack size
+ifeq ($(USE_SYSTEM_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__sys_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__sys_stack_size__=$(USE_SYSTEM_STACKSIZE)
+endif
+
+# Output directory and files
+ifeq ($(BUILDDIR),)
+ BUILDDIR = build
+endif
+ifeq ($(BUILDDIR),.)
+ BUILDDIR = build
+endif
+
+# Dependencies directory
+ifeq ($(DEPDIR),)
+ DEPDIR = .dep
+endif
+ifeq ($(DEPDIR),.)
+ DEPDIR = .dep
+endif
+
+OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
+ $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp \
+ $(BUILDDIR)/$(PROJECT).list
+
+# Source files groups and paths
+ifeq ($(USE_THUMB),yes)
+ TCSRC += $(CSRC)
+ TCPPSRC += $(CPPSRC)
+else
+ ACSRC += $(CSRC)
+ ACPPSRC += $(CPPSRC)
+endif
+ASRC = $(ACSRC) $(ACPPSRC)
+TSRC = $(TCSRC) $(TCPPSRC)
+SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
+
+# Various directories
+OBJDIR = $(BUILDDIR)/obj
+LSTDIR = $(BUILDDIR)/lst
+
+# Object files groups
+ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o)))
+#ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o)))
+ACPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(patsubst %.cpp, %.o, $(filter %.cpp, $(TCPPSRC)))))
+ACCOBJS := $(addprefix $(OBJDIR)/, $(notdir $(patsubst %.cc, %.o, $(filter %.cc, $(TCPPSRC)))))
+TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
+#TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
+TCPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(patsubst %.cpp, %.o, $(filter %.cpp, $(TCPPSRC)))))
+TCCOBJS := $(addprefix $(OBJDIR)/, $(notdir $(patsubst %.cc, %.o, $(filter %.cc, $(TCPPSRC)))))
+ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
+ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+#OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
+OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(ACCOBJS) $(TCPPOBJS) $(TCOBJS)
+
+# Paths
+IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
+LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+
+# Macros
+DEFS = $(DDEFS) $(UDEFS)
+ADEFS = $(DADEFS) $(UADEFS)
+
+# Libs
+LIBS = $(DLIBS) $(ULIBS)
+
+# Various settings
+MCFLAGS = -mcpu=$(MCU)
+ODFLAGS = -x --syms
+ASFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+ASXFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
+CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
+CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
+LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH)/ld,--script=$(LDSCRIPT)$(LDOPT)
+
+# Thumb interwork enabled only if needed because it kills performance.
+ifneq ($(strip $(TSRC)),)
+ CFLAGS += -DTHUMB_PRESENT
+ CPPFLAGS += -DTHUMB_PRESENT
+ ASFLAGS += -DTHUMB_PRESENT
+ ASXFLAGS += -DTHUMB_PRESENT
+ ifneq ($(strip $(ASRC)),)
+ # Mixed ARM and THUMB mode.
+ CFLAGS += -mthumb-interwork
+ CPPFLAGS += -mthumb-interwork
+ ASFLAGS += -mthumb-interwork
+ ASXFLAGS += -mthumb-interwork
+ LDFLAGS += -mthumb-interwork
+ else
+ # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly.
+ CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
+ CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
+ ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
+ ASXFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
+ LDFLAGS += -mno-thumb-interwork -mthumb
+ endif
+else
+ # Pure ARM mode
+ CFLAGS += -mno-thumb-interwork
+ CPPFLAGS += -mno-thumb-interwork
+ ASFLAGS += -mno-thumb-interwork
+ ASXFLAGS += -mno-thumb-interwork
+ LDFLAGS += -mno-thumb-interwork
+endif
+
+# Generate dependency information
+ASFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+ASXFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+CFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+CPPFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+
+# Paths where to search for sources
+VPATH = $(SRCPATHS)
+
+#
+# Makefile rules
+#
+
+all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK
+
+PRE_MAKE_ALL_RULE_HOOK:
+
+POST_MAKE_ALL_RULE_HOOK:
+
+$(OBJS): | PRE_MAKE_ALL_RULE_HOOK $(BUILDDIR) $(OBJDIR) $(LSTDIR) $(DEPDIR)
+
+$(BUILDDIR):
+ifneq ($(USE_VERBOSE_COMPILE),yes)
+ @echo Compiler Options
+ @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
+ @echo
+endif
+ @mkdir -p $(BUILDDIR)
+
+$(OBJDIR):
+ @mkdir -p $(OBJDIR)
+
+$(LSTDIR):
+ @mkdir -p $(LSTDIR)
+
+$(DEPDIR):
+ @mkdir -p $(DEPDIR)
+
+$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ACCOBJS) : $(OBJDIR)/%.o : %.cc $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCCOBJS) : $(OBJDIR)/%.o : %.cc $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ACOBJS) : $(OBJDIR)/%.o : %.c $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCOBJS) : $(OBJDIR)/%.o : %.c $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMOBJS) : $(OBJDIR)/%.o : %.s $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(BUILDDIR)/$(PROJECT).elf: $(OBJS) $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+else
+ @echo Linking $@
+ @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+endif
+
+%.hex: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(HEX) $< $@
+else
+ @echo Creating $@
+ @$(HEX) $< $@
+endif
+
+%.bin: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(BIN) $< $@
+else
+ @echo Creating $@
+ @$(BIN) $< $@
+endif
+
+%.dmp: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(OD) $(ODFLAGS) $< > $@
+ $(SZ) $<
+else
+ @echo Creating $@
+ @$(OD) $(ODFLAGS) $< > $@
+ @echo
+ @$(SZ) $<
+endif
+
+%.list: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(OD) -S $< > $@
+else
+ @echo Creating $@
+ @$(OD) -S $< > $@
+ @echo
+ @echo Done
+endif
+
+lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a
+
+$(BUILDDIR)/lib$(PROJECT).a: $(OBJS)
+ @$(AR) -r $@ $^
+ @echo
+ @echo Done
+
+clean: CLEAN_RULE_HOOK
+ @echo Cleaning
+ @echo - $(DEPDIR)
+ @-rm -fR $(DEPDIR)/* $(BUILDDIR)/* 2>/dev/null
+ @-if [ -d "$(DEPDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(DEPDIR)) 2>/dev/null; fi
+ @echo - $(BUILDDIR)
+ @-if [ -d "$(BUILDDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(BUILDDIR)) 2>/dev/null; fi
+ @echo
+ @echo Done
+
+CLEAN_RULE_HOOK:
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(wildcard $(DEPDIR)/*)
+
+# *** EOF ***
diff --git a/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/vectors.S b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/vectors.S new file mode 100644 index 0000000..3d8950c --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARM/compilers/GCC/vectors.S @@ -0,0 +1,104 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARM/compilers/GCC/vectors.s
+ * @brief Interrupt vectors for ARM devices.
+ *
+ * @defgroup ARM_VECTORS ARM Exception Vectors
+ * @{
+ */
+
+#if defined(__DOXYGEN__)
+/**
+ * @brief Unhandled exceptions handler.
+ * @details Any undefined exception vector points to this function by default.
+ * This function simply stops the system into an infinite loop.
+ * @note The default implementation is a weak symbol, the application
+ * can override the default implementation.
+ *
+ * @notapi
+ */
+void _unhandled_exception(void) {}
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ .section .vectors, "ax"
+ .code 32
+ .balign 4
+
+/*
+ * System entry points.
+ */
+ .global _start
+_start:
+ ldr pc, _reset
+ ldr pc, _undefined
+ ldr pc, _swi
+ ldr pc, _prefetch
+ ldr pc, _abort
+ nop
+ ldr pc, _irq
+ ldr pc, _fiq
+
+_reset:
+ .word Boot_Handler
+_undefined:
+ .word Und_Handler
+_swi:
+ .word Swi_Handler
+_prefetch:
+ .word Prefetch_Handler
+_abort:
+ .word Abort_Handler
+_fiq:
+ .word Fiq_Handler
+_irq:
+ .word Irq_Handler
+
+/*
+ * Default exceptions handlers. The handlers are declared weak in order to be
+ * replaced by the real handling code. Everything is defaulted to an infinite
+ * loop.
+ */
+ .weak Reset_Handler
+Reset_Handler:
+ .weak Und_Handler
+Und_Handler:
+ .weak Swi_Handler
+Swi_Handler:
+ .weak Prefetch_Handler
+Prefetch_Handler:
+ .weak Abort_Handler
+Abort_Handler:
+ .weak Fiq_Handler
+Fiq_Handler:
+ .weak Irq_Handler
+Irq_Handler:
+ .weak _unhandled_exception
+_unhandled_exception:
+ b _unhandled_exception
+/*
+ * Default boot handler. Jump to Reset_Handler.
+ */
+ .section .boot, "ax"
+ .weak Boot_Handler
+Boot_Handler:
+ b Reset_Handler
+#endif
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARM/devices/LPC214x/armparams.h b/ChibiOS_20.3.2/os/common/startup/ARM/devices/LPC214x/armparams.h new file mode 100644 index 0000000..eebec84 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARM/devices/LPC214x/armparams.h @@ -0,0 +1,62 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file LPC214x/armparams.h
+ * @brief ARM parameters for the LPC214x.
+ *
+ * @defgroup ARM_LPC214x LPC214x Specific Parameters
+ * @ingroup ARM_SPECIFIC
+ * @details This file contains the ARM specific parameters for the
+ * LPC214x platform.
+ * @{
+ */
+
+#ifndef ARMPARAMS_H
+#define ARMPARAMS_H
+
+/**
+ * @brief ARM core model.
+ */
+#define ARM_CORE ARM_CORE_ARM7TDMI
+
+/**
+ * @brief Thumb-capable.
+ */
+#define ARM_SUPPORTS_THUMB 1
+
+/**
+ * @brief Thumb2-capable.
+ */
+#define ARM_SUPPORTS_THUMB2 0
+
+/**
+ * @brief Implementation of the wait-for-interrupt state enter.
+ */
+#define ARM_WFI_IMPL (PCON = 1)
+
+#if !defined(_FROM_ASM_) || defined(__DOXYGEN__)
+/**
+ * @brief Address of the IRQ vector register in the interrupt controller.
+ */
+#define ARM_IRQ_VECTOR_REG 0xFFFFF030U
+#else
+#define ARM_IRQ_VECTOR_REG 0xFFFFF030
+#endif
+
+#endif /* ARMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARM/devices/LPC214x/lpc214x.h b/ChibiOS_20.3.2/os/common/startup/ARM/devices/LPC214x/lpc214x.h new file mode 100644 index 0000000..f310c55 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARM/devices/LPC214x/lpc214x.h @@ -0,0 +1,523 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file lpc214x.h
+ * @brief LPC214x register definitions.
+ */
+
+#ifndef LPC214X_H
+#define LPC214X_H
+
+typedef volatile uint8_t IOREG8;
+typedef volatile uint16_t IOREG16;
+typedef volatile uint32_t IOREG32;
+
+/*
+ * System.
+ */
+#define MEMMAP (*((IOREG32 *)0xE01FC040))
+#define PCON (*((IOREG32 *)0xE01FC0C0))
+#define PCONP (*((IOREG32 *)0xE01FC0C4))
+#define VPBDIV (*((IOREG32 *)0xE01FC100))
+#define EXTINT (*((IOREG32 *)0xE01FC140))
+#define INTWAKE (*((IOREG32 *)0xE01FC144))
+#define EXTMODE (*((IOREG32 *)0xE01FC148))
+#define EXTPOLAR (*((IOREG32 *)0xE01FC14C))
+#define RSID (*((IOREG32 *)0xE01FC180))
+#define CSPR (*((IOREG32 *)0xE01FC184))
+#define SCS (*((IOREG32 *)0xE01FC1A0))
+
+#define VPD_D4 0
+#define VPD_D1 1
+#define VPD_D2 2
+#define VPD_RESERVED 3
+
+#define PCTIM0 (1 << 1)
+#define PCTIM1 (1 << 2)
+#define PCUART0 (1 << 3)
+#define PCUART1 (1 << 4)
+#define PCPWM0 (1 << 5)
+#define PCI2C0 (1 << 7)
+#define PCSPI0 (1 << 8)
+#define PCRTC (1 << 9)
+#define PCSPI1 (1 << 10)
+#define PCAD0 (1 << 12)
+#define PCI2C1 (1 << 19)
+#define PCAD1 (1 << 20)
+#define PCUSB (1 << 31)
+#define PCALL (PCTIM0 | PCTIM1 | PCUART0 | PCUART1 | \
+ PCPWM0 | PCI2C0 | PCSPI0 | PCRTC | PCSPI1 | \
+ PCAD0 | PCI2C1 | PCAD1 | PCUSB)
+
+#define EINT0 1
+#define EINT1 2
+#define EINT2 4
+#define EINT3 8
+
+#define EXTWAKE0 1
+#define EXTWAKE1 2
+#define EXTWAKE2 4
+#define EXTWAKE3 8
+#define USBWAKE 0x20
+#define BODWAKE 0x4000
+#define RTCWAKE 0x8000
+
+#define EXTMODE0 1
+#define EXTMODE1 2
+#define EXTMODE2 4
+#define EXTMODE3 8
+
+#define EXTPOLAR0 1
+#define EXTPOLAR1 2
+#define EXTPOLAR2 4
+#define EXTPOLAR3 8
+
+typedef struct {
+ IOREG32 PLL_CON;
+ IOREG32 PLL_CFG;
+ IOREG32 PLL_STAT;
+ IOREG32 PLL_FEED;
+} PLL;
+
+#define PLL0Base ((PLL *)0xE01FC080)
+#define PLL1Base ((PLL *)0xE01FC0A0)
+#define PLL0CON (PLL0Base->PLL_CON)
+#define PLL0CFG (PLL0Base->PLL_CFG)
+#define PLL0STAT (PLL0Base->PLL_STAT)
+#define PLL0FEED (PLL0Base->PLL_FEED)
+#define PLL1CON (PLL1Base->PLL_CON)
+#define PLL1CFG (PLL1Base->PLL_CFG)
+#define PLL1STAT (PLL1Base->PLL_STAT)
+#define PLL1FEED (PLL1Base->PLL_FEED)
+
+/*
+ * Pins.
+ */
+typedef struct {
+ IOREG32 PS_SEL0;
+ IOREG32 PS_SEL1;
+ IOREG32 _dummy[3];
+ IOREG32 PS_SEL2;
+} PS;
+
+#define PSBase ((PS *)0xE002C000)
+#define PINSEL0 (PSBase->PS_SEL0)
+#define PINSEL1 (PSBase->PS_SEL1)
+#define PINSEL2 (PSBase->PS_SEL2)
+
+/*
+ * VIC
+ */
+#define SOURCE_WDT 0
+#define SOURCE_ARMCore0 2
+#define SOURCE_ARMCore1 3
+#define SOURCE_Timer0 4
+#define SOURCE_Timer1 5
+#define SOURCE_UART0 6
+#define SOURCE_UART1 7
+#define SOURCE_PWM0 8
+#define SOURCE_I2C0 9
+#define SOURCE_SPI0 10
+#define SOURCE_SPI1 11
+#define SOURCE_PLL 12
+#define SOURCE_RTC 13
+#define SOURCE_EINT0 14
+#define SOURCE_EINT1 15
+#define SOURCE_EINT2 16
+#define SOURCE_EINT3 17
+#define SOURCE_ADC0 18
+#define SOURCE_I2C1 19
+#define SOURCE_BOD 20
+#define SOURCE_ADC1 21
+#define SOURCE_USB 22
+
+#define INTMASK(n) (1 << (n))
+#define ALLINTMASK (INTMASK(SOURCE_WDT) | INTMASK(SOURCE_ARMCore0) | \
+ INTMASK(SOURCE_ARMCore1) | INTMASK(SOURCE_Timer0) | \
+ INTMASK(SOURCE_Timer1) | INTMASK(SOURCE_UART0) | \
+ INTMASK(SOURCE_UART1) | INTMASK(SOURCE_PWM0) | \
+ INTMASK(SOURCE_I2C0) | INTMASK(SOURCE_SPI0) | \
+ INTMASK(SOURCE_SPI1) | INTMASK(SOURCE_PLL) | \
+ INTMASK(SOURCE_RTC) | INTMASK(SOURCE_EINT0) | \
+ INTMASK(SOURCE_EINT1) | INTMASK(SOURCE_EINT2) | \
+ INTMASK(SOURCE_EINT3) | INTMASK(SOURCE_ADC0) | \
+ INTMASK(SOURCE_I2C1) | INTMASK(SOURCE_BOD) | \
+ INTMASK(SOURCE_ADC1) | INTMASK(SOURCE_USB))
+
+typedef struct {
+ IOREG32 VIC_IRQStatus;
+ IOREG32 VIC_FIQStatus;
+ IOREG32 VIC_RawIntr;
+ IOREG32 VIC_IntSelect;
+ IOREG32 VIC_IntEnable;
+ IOREG32 VIC_IntEnClear;
+ IOREG32 VIC_SoftInt;
+ IOREG32 VIC_SoftIntClear;
+ IOREG32 VIC_Protection;
+ IOREG32 unused1[3];
+ IOREG32 VIC_VectAddr;
+ IOREG32 VIC_DefVectAddr;
+ IOREG32 unused2[50];
+ IOREG32 VIC_VectAddrs[16];
+ IOREG32 unused3[48];
+ IOREG32 VIC_VectCntls[16];
+} VIC;
+
+#define VICBase ((VIC *)0xFFFFF000)
+#define VICVectorsBase ((IOREG32 *)0xFFFFF100)
+#define VICControlsBase ((IOREG32 *)0xFFFFF200)
+
+#define VICIRQStatus (VICBase->VIC_IRQStatus)
+#define VICFIQStatus (VICBase->VIC_FIQStatus)
+#define VICRawIntr (VICBase->VIC_RawIntr)
+#define VICIntSelect (VICBase->VIC_IntSelect)
+#define VICIntEnable (VICBase->VIC_IntEnable)
+#define VICIntEnClear (VICBase->VIC_IntEnClear)
+#define VICSoftInt (VICBase->VIC_SoftInt)
+#define VICSoftIntClear (VICBase->VIC_SoftIntClear)
+#define VICProtection (VICBase->VIC_Protection)
+#define VICVectAddr (VICBase->VIC_VectAddr)
+#define VICDefVectAddr (VICBase->VIC_DefVectAddr)
+
+#define VICVectAddrs(n) (VICBase->VIC_VectAddrs[n])
+#define VICVectCntls(n) (VICBase->VIC_VectCntls[n])
+
+/*
+ * MAM.
+ */
+typedef struct {
+ IOREG32 MAM_Control;
+ IOREG32 MAM_Timing;
+} MAM;
+
+#define MAMBase ((MAM *)0xE01FC000)
+#define MAMCR (MAMBase->MAM_Control)
+#define MAMTIM (MAMBase->MAM_Timing)
+
+/*
+ * GPIO - FIO.
+ */
+typedef struct {
+ IOREG32 IO_PIN;
+ IOREG32 IO_SET;
+ IOREG32 IO_DIR;
+ IOREG32 IO_CLR;
+} GPIO;
+
+#define GPIO0Base ((GPIO *)0xE0028000)
+#define IO0PIN (GPIO0Base->IO_PIN)
+#define IO0SET (GPIO0Base->IO_SET)
+#define IO0DIR (GPIO0Base->IO_DIR)
+#define IO0CLR (GPIO0Base->IO_CLR)
+
+#define GPIO1Base ((GPIO *)0xE0028010)
+#define IO1PIN (GPIO1Base->IO_PIN)
+#define IO1SET (GPIO1Base->IO_SET)
+#define IO1DIR (GPIO1Base->IO_DIR)
+#define IO1CLR (GPIO1Base->IO_CLR)
+
+typedef struct {
+ IOREG32 FIO_DIR;
+ IOREG32 unused1;
+ IOREG32 unused2;
+ IOREG32 unused3;
+ IOREG32 FIO_MASK;
+ IOREG32 FIO_PIN;
+ IOREG32 FIO_SET;
+ IOREG32 FIO_CLR;
+} FIO;
+
+#define FIO0Base ((FIO *)0x3FFFC000)
+#define FIO0DIR (FIO0Base->FIO_DIR)
+#define FIO0MASK (FIO0Base->FIO_MASK)
+#define FIO0PIN (FIO0Base->FIO_PIN)
+#define FIO0SET (FIO0Base->FIO_SET)
+#define FIO0CLR (FIO0Base->FIO_CLR)
+
+#define FIO1Base ((FIO *)0x3FFFC020)
+#define FIO1DIR (FIO1Base->FIO_DIR)
+#define FIO1MASK (FIO1Base->FIO_MASK)
+#define FIO1PIN (FIO1Base->FIO_PIN)
+#define FIO1SET (FIO1Base->FIO_SET)
+#define FIO1CLR (FIO1Base->FIO_CLR)
+
+/*
+ * UART.
+ */
+typedef struct {
+ union {
+ IOREG32 UART_RBR;
+ IOREG32 UART_THR;
+ IOREG32 UART_DLL;
+ };
+ union {
+ IOREG32 UART_IER;
+ IOREG32 UART_DLM;
+ };
+ union {
+ IOREG32 UART_IIR;
+ IOREG32 UART_FCR;
+ };
+ IOREG32 UART_LCR;
+ IOREG32 UART_MCR;
+ IOREG32 UART_LSR;
+ IOREG32 unused18;
+ IOREG32 UART_SCR;
+ IOREG32 UART_ACR;
+ IOREG32 unused24;
+ IOREG32 UART_FDR;
+ IOREG32 unused2C;
+ IOREG32 UART_TER;
+} UART;
+
+#define U0Base ((UART *)0xE000C000)
+#define U0RBR (U0Base->UART_RBR)
+#define U0THR (U0Base->UART_THR)
+#define U0DLL (U0Base->UART_DLL)
+#define U0IER (U0Base->UART_IER)
+#define U0DLM (U0Base->UART_DLM)
+#define U0IIR (U0Base->UART_IIR)
+#define U0FCR (U0Base->UART_FCR)
+#define U0LCR (U0Base->UART_LCR)
+#define U0LSR (U0Base->UART_LSR)
+#define U0SCR (U0Base->UART_SCR)
+#define U0ACR (U0Base->UART_ACR)
+#define U0FDR (U0Base->UART_FDR)
+#define U0TER (U0Base->UART_TER)
+
+#define U1Base ((UART *)0xE0010000)
+#define U1RBR (U1Base->UART_RBR)
+#define U1THR (U1Base->UART_THR)
+#define U1DLL (U1Base->UART_DLL)
+#define U1IER (U1Base->UART_IER)
+#define U1DLM (U1Base->UART_DLM)
+#define U1IIR (U1Base->UART_IIR)
+#define U1FCR (U1Base->UART_FCR)
+#define U1MCR (U1Base->UART_MCR)
+#define U1LCR (U1Base->UART_LCR)
+#define U1LSR (U1Base->UART_LSR)
+#define U1SCR (U1Base->UART_SCR)
+#define U1ACR (U1Base->UART_ACR)
+#define U1FDR (U1Base->UART_FDR)
+#define U1TER (U1Base->UART_TER)
+
+#define IIR_SRC_MASK 0x0F
+#define IIR_SRC_NONE 0x01
+#define IIR_SRC_TX 0x02
+#define IIR_SRC_RX 0x04
+#define IIR_SRC_ERROR 0x06
+#define IIR_SRC_TIMEOUT 0x0C
+
+#define IER_RBR 1
+#define IER_THRE 2
+#define IER_STATUS 4
+
+#define IIR_INT_PENDING 1
+
+#define LCR_WL5 0
+#define LCR_WL6 1
+#define LCR_WL7 2
+#define LCR_WL8 3
+#define LCR_STOP1 0
+#define LCR_STOP2 4
+#define LCR_NOPARITY 0
+#define LCR_PARITYODD 0x08
+#define LCR_PARITYEVEN 0x18
+#define LCR_PARITYONE 0x28
+#define LCR_PARITYZERO 0x38
+#define LCR_BREAK_ON 0x40
+#define LCR_DLAB 0x80
+
+#define FCR_ENABLE 1
+#define FCR_RXRESET 2
+#define FCR_TXRESET 4
+#define FCR_TRIGGER0 0
+#define FCR_TRIGGER1 0x40
+#define FCR_TRIGGER2 0x80
+#define FCR_TRIGGER3 0xC0
+
+#define LSR_RBR_FULL 1
+#define LSR_OVERRUN 2
+#define LSR_PARITY 4
+#define LSR_FRAMING 8
+#define LSR_BREAK 0x10
+#define LSR_THRE 0x20
+#define LSR_TEMT 0x40
+#define LSR_RXFE 0x80
+
+#define TER_ENABLE 0x80
+
+/*
+ * SSP.
+ */
+typedef struct {
+ IOREG32 SSP_CR0;
+ IOREG32 SSP_CR1;
+ IOREG32 SSP_DR;
+ IOREG32 SSP_SR;
+ IOREG32 SSP_CPSR;
+ IOREG32 SSP_IMSC;
+ IOREG32 SSP_RIS;
+ IOREG32 SSP_MIS;
+ IOREG32 SSP_ICR;
+} SSP;
+
+#define SSPBase ((SSP *)0xE0068000)
+#define SSPCR0 (SSPBase->SSP_CR0)
+#define SSPCR1 (SSPBase->SSP_CR1)
+#define SSPDR (SSPBase->SSP_DR)
+#define SSPSR (SSPBase->SSP_SR)
+#define SSPCPSR (SSPBase->SSP_CPSR)
+#define SSPIMSC (SSPBase->SSP_IMSC)
+#define SSPRIS (SSPBase->SSP_RIS)
+#define SSPMIS (SSPBase->SSP_MIS)
+#define SSPICR (SSPBase->SSP_ICR)
+
+#define CR0_DSSMASK 0x0F
+#define CR0_DSS4BIT 3
+#define CR0_DSS5BIT 4
+#define CR0_DSS6BIT 5
+#define CR0_DSS7BIT 6
+#define CR0_DSS8BIT 7
+#define CR0_DSS9BIT 8
+#define CR0_DSS10BIT 9
+#define CR0_DSS11BIT 0xA
+#define CR0_DSS12BIT 0xB
+#define CR0_DSS13BIT 0xC
+#define CR0_DSS14BIT 0xD
+#define CR0_DSS15BIT 0xE
+#define CR0_DSS16BIT 0xF
+#define CR0_FRFSPI 0
+#define CR0_FRFSSI 0x10
+#define CR0_FRFMW 0x20
+#define CR0_CPOL 0x40
+#define CR0_CPHA 0x80
+#define CR0_CLOCKRATE(n) ((n) << 8)
+
+#define CR1_LBM 1
+#define CR1_SSE 2
+#define CR1_MS 4
+#define CR1_SOD 8
+
+#define SR_TFE 1
+#define SR_TNF 2
+#define SR_RNE 4
+#define SR_RFF 8
+#define SR_BSY 0x10
+
+#define IMSC_ROR 1
+#define IMSC_RT 2
+#define IMSC_RX 4
+#define IMSC_TX 8
+
+#define RIS_ROR 1
+#define RIS_RT 2
+#define RIS_RX 4
+#define RIS_TX 8
+
+#define MIS_ROR 1
+#define MIS_RT 2
+#define MIS_RX 4
+#define MIS_TX 8
+
+#define ICR_ROR 1
+#define ICR_RT 2
+
+/*
+ * Timers/Counters.
+ */
+typedef struct {
+ IOREG32 TC_IR;
+ IOREG32 TC_TCR;
+ IOREG32 TC_TC;
+ IOREG32 TC_PR;
+ IOREG32 TC_PC;
+ IOREG32 TC_MCR;
+ IOREG32 TC_MR0;
+ IOREG32 TC_MR1;
+ IOREG32 TC_MR2;
+ IOREG32 TC_MR3;
+ IOREG32 TC_CCR;
+ IOREG32 TC_CR0;
+ IOREG32 TC_CR1;
+ IOREG32 TC_CR2;
+ IOREG32 TC_CR3;
+ IOREG32 TC_EMR;
+ IOREG32 TC_CTCR;
+} TC;
+
+#define T0Base ((TC *)0xE0004000)
+#define T0IR (T0Base->TC_IR)
+#define T0TCR (T0Base->TC_TCR)
+#define T0TC (T0Base->TC_TC)
+#define T0PR (T0Base->TC_PR)
+#define T0PC (T0Base->TC_PC)
+#define T0MCR (T0Base->TC_MCR)
+#define T0MR0 (T0Base->TC_MR0)
+#define T0MR1 (T0Base->TC_MR1)
+#define T0MR2 (T0Base->TC_MR2)
+#define T0MR3 (T0Base->TC_MR3)
+#define T0CCR (T0Base->TC_CCR)
+#define T0CR0 (T0Base->TC_CR0)
+#define T0CR1 (T0Base->TC_CR1)
+#define T0CR2 (T0Base->TC_CR2)
+#define T0CR3 (T0Base->TC_CR3)
+#define T0EMR (T0Base->TC_EMR)
+#define T0CTCR (T0Base->TC_CTCR)
+
+#define T1Base ((TC *)0xE0008000)
+#define T1IR (T1Base->TC_IR)
+#define T1TCR (T1Base->TC_TCR)
+#define T1TC (T1Base->TC_TC)
+#define T1PR (T1Base->TC_PR)
+#define T1PC (T1Base->TC_PC)
+#define T1MCR (T1Base->TC_MCR)
+#define T1MR0 (T1Base->TC_MR0)
+#define T1MR1 (T1Base->TC_MR1)
+#define T1MR2 (T1Base->TC_MR2)
+#define T1MR3 (T1Base->TC_MR3)
+#define T1CCR (T1Base->TC_CCR)
+#define T1CR0 (T1Base->TC_CR0)
+#define T1CR1 (T1Base->TC_CR1)
+#define T1CR2 (T1Base->TC_CR2)
+#define T1CR3 (T1Base->TC_CR3)
+#define T1EMR (T1Base->TC_EMR)
+#define T1CTCR (T1Base->TC_CTCR)
+
+/*
+ * Watchdog.
+ */
+typedef struct {
+ IOREG32 WD_MOD;
+ IOREG32 WD_TC;
+ IOREG32 WD_FEED;
+ IOREG32 WD_TV;
+} WD;
+
+#define WDBase ((WD *)0xE0000000)
+#define WDMOD (WDBase->WD_MOD)
+#define WDTC (WDBase->WD_TC)
+#define WDFEED (WDBase->WD_FEED)
+#define WDTV (WDBase->WD_TV)
+
+/*
+ * DAC.
+ */
+#define DACR (*((IOREG32 *)0xE006C000))
+
+#endif /* LPC214X_H */
+
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/crt0.S b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/crt0.S new file mode 100644 index 0000000..dcb0e42 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/crt0.S @@ -0,0 +1,190 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file crt0.S
+ * @brief Generic ARMv7-M sandbox startup file for ChibiOS.
+ *
+ * @addtogroup ARMCMx_GCC_STARTUP_V7M_SB
+ * @{
+ */
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
+#define CRT0_STACKS_FILL_PATTERN 0x55555555
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
+#define CRT0_INIT_STACKS TRUE
+#endif
+
+/**
+ * @brief DATA segment initialization switch.
+ */
+#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
+#define CRT0_INIT_DATA TRUE
+#endif
+
+/**
+ * @brief BSS segment initialization switch.
+ */
+#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
+#define CRT0_INIT_BSS TRUE
+#endif
+
+/**
+ * @brief Constructors invocation switch.
+ */
+#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_CONSTRUCTORS TRUE
+#endif
+
+/**
+ * @brief Destructors invocation switch.
+ */
+#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_DESTRUCTORS TRUE
+#endif
+
+/*===========================================================================*/
+/* Code section. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+
+ .syntax unified
+ .cpu cortex-m3
+
+ .thumb
+
+ .section .sandbox, "ax"
+ .align 4
+ .globl _sandbox
+_sandbox: .long 0xFE9154C0
+ .long 0x0C4519EF
+ .long 16
+ .long 0
+ b _crt0_entry
+
+ .text
+/*
+ * CRT0 entry point.
+ */
+ .align 2
+ .thumb_func
+ .global _crt0_entry
+_crt0_entry:
+
+ /* PSP stack pointers initialization.*/
+ ldr r0, =__user_psp_end__
+ msr PSP, r0
+
+#if CRT0_INIT_STACKS == TRUE
+ /* User process Stack initialization. Note, it assumes that the
+ stack size is a multiple of 4 so the linker file must
+ ensure this.*/
+ ldr r0, =CRT0_STACKS_FILL_PATTERN
+ ldr r1, =__user_psp_base__
+ ldr r2, =__user_psp_end__
+upsloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo upsloop
+#endif /* CRT0_INIT_STACKS == TRUE */
+
+#if CRT0_INIT_DATA == TRUE
+ /* Data initialization. Note, it assumes that the DATA size
+ is a multiple of 4 so the linker file must ensure this.*/
+ ldr r1, =__textdata_base__
+ ldr r2, =__data_base__
+ ldr r3, =__data_end__
+dloop:
+ cmp r2, r3
+ ittt lo
+ ldrlo r0, [r1], #4
+ strlo r0, [r2], #4
+ blo dloop
+#endif /* CRT0_INIT_DATA == TRUE */
+
+#if CRT0_INIT_BSS == TRUE
+ /* BSS initialization. Note, it assumes that the DATA size
+ is a multiple of 4 so the linker file must ensure this.*/
+ movs r0, #0
+ ldr r1, =__bss_base__
+ ldr r2, =__bss_end__
+bloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo bloop
+#endif /* CRT0_INIT_BSS == TRUE */
+
+#if CRT0_CALL_CONSTRUCTORS == TRUE
+ /* Constructors invocation.*/
+ ldr r4, =__init_array_base__
+ ldr r5, =__init_array_end__
+initloop:
+ cmp r4, r5
+ bge endinitloop
+ ldr r1, [r4], #4
+ blx r1
+ b initloop
+endinitloop:
+#endif /* CRT0_CALL_CONSTRUCTORS == TRUE */
+
+ /* Main program invocation, r0 contains the returned value.*/
+ bl main
+
+#if CRT0_CALL_DESTRUCTORS == TRUE
+ /* Destructors invocation.*/
+ ldr r4, =__fini_array_base__
+ ldr r5, =__fini_array_end__
+finiloop:
+ cmp r4, r5
+ bge endfiniloop
+ ldr r1, [r4], #4
+ blx r1
+ b finiloop
+endfiniloop:
+#endif /* CRT0_CALL_DESTRUCTORS == TRUE */
+
+.exitloop: b .exitloop
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules.ld new file mode 100644 index 0000000..8ca9a47 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules.ld @@ -0,0 +1,11 @@ +/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
+
+/* Memory rules inclusion.*/
+INCLUDE rules_memory.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules_code.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules_code.ld new file mode 100644 index 0000000..6568410 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules_code.ld @@ -0,0 +1,80 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+ENTRY(_crt0_entry)
+
+SECTIONS
+{
+ .sandbox : ALIGN(16)
+ {
+ KEEP(*(.sandbox))
+ } > CODE_SPACE
+
+ .xtors : ALIGN(4)
+ {
+ __init_array_base__ = .;
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ __init_array_end__ = .;
+ __fini_array_base__ = .;
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ __fini_array_end__ = .;
+ } > CODE_SPACE
+
+ .text : ALIGN_WITH_INPUT
+ {
+ __text_base__ = .;
+ *(.text)
+ *(.text.*)
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ __text_end__ = .;
+ } > CODE_SPACE
+
+ .rodata : ALIGN(4)
+ {
+ __rodata_base__ = .;
+ *(.rodata)
+ *(.rodata.*)
+ . = ALIGN(4);
+ __rodata_end__ = .;
+ } > CODE_SPACE
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > CODE_SPACE
+
+ .ARM.exidx : {
+ __exidx_base__ = .;
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end__ = .;
+ __exidx_end = .;
+ } > CODE_SPACE
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > CODE_SPACE
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > CODE_SPACE
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules_data.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules_data.ld new file mode 100644 index 0000000..6d474ea --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules_data.ld @@ -0,0 +1,43 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+SECTIONS
+{
+ .data : ALIGN(4)
+ {
+ PROVIDE(_textdata = LOADADDR(.data));
+ PROVIDE(_data = .);
+ __textdata_base__ = LOADADDR(.data);
+ __data_base__ = .;
+ *(.data)
+ *(.data.*)
+ *(.ramtext)
+ . = ALIGN(4);
+ PROVIDE(_edata = .);
+ __data_end__ = .;
+ } > DATA_SPACE
+
+ .bss (NOLOAD) : ALIGN(4)
+ {
+ __bss_base__ = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ PROVIDE(end = .);
+ } > DATA_SPACE
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules_memory.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules_memory.ld new file mode 100644 index 0000000..8cf4585 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules_memory.ld @@ -0,0 +1,27 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +SECTIONS +{ + /* The default heap uses the (statically) unused part of a RAM section.*/ + .heap (NOLOAD) : + { + . = ALIGN(8); + __heap_base__ = .; + . = ORIGIN(DATA_SPACE) + LENGTH(DATA_SPACE); + __heap_end__ = .; + } > DATA_SPACE +} diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules_stacks.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules_stacks.ld new file mode 100644 index 0000000..a377ffe --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/ld/rules_stacks.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+SECTIONS
+{
+ .upsp (NOLOAD) :
+ {
+ . = ALIGN(8);
+ __user_psp_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __user_psp_end__ = .;
+ } > DATA_SPACE
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/mk/startup.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/mk/startup.mk new file mode 100644 index 0000000..22e67cd --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx-SB/compilers/GCC/mk/startup.mk @@ -0,0 +1,14 @@ +# List of the ChibiOS generic sandbox startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx-SB/compilers/GCC/crt0.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx-SB/compilers/GCC
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx-SB/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S new file mode 100644 index 0000000..4adb573 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S @@ -0,0 +1,288 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file crt0_v6m.S
+ * @brief Generic ARMv6-M (Cortex-M0/M1) startup file for ChibiOS.
+ *
+ * @addtogroup ARMCMx_GCC_STARTUP_V6M
+ * @{
+ */
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#define CONTROL_MODE_PRIVILEGED 0
+#define CONTROL_MODE_UNPRIVILEGED 1
+#define CONTROL_USE_MSP 0
+#define CONTROL_USE_PSP 2
+
+#define SCB_VTOR 0xE000ED08
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enforces initialization of MSP.
+ * @note This is required if the boot process is not reliable for whatever
+ * reason (bad ROMs, bad bootloaders, bad debuggers=.
+ */
+#if !defined(CRT0_FORCE_MSP_INIT) || defined(__DOXYGEN__)
+#define CRT0_FORCE_MSP_INIT TRUE
+#endif
+
+/**
+ * @brief VTOR special register initialization.
+ * @details VTOR is initialized to point to the vectors table.
+ * @note This option can only be enabled on Cortex-M0+ cores.
+ */
+#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
+#define CRT0_VTOR_INIT FALSE
+#endif
+
+/**
+ * @brief Control special register initialization value.
+ * @details The system is setup to run in privileged mode using the PSP
+ * stack (dual stack mode).
+ */
+#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
+#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \
+ CONTROL_MODE_PRIVILEGED)
+#endif
+
+/**
+ * @brief Core initialization switch.
+ */
+#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
+#define CRT0_INIT_CORE TRUE
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
+#define CRT0_STACKS_FILL_PATTERN 0x55555555
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
+#define CRT0_INIT_STACKS TRUE
+#endif
+
+/**
+ * @brief DATA segment initialization switch.
+ */
+#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
+#define CRT0_INIT_DATA TRUE
+#endif
+
+/**
+ * @brief BSS segment initialization switch.
+ */
+#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
+#define CRT0_INIT_BSS TRUE
+#endif
+
+/**
+ * @brief RAM areas initialization switch.
+ */
+#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__)
+#define CRT0_INIT_RAM_AREAS TRUE
+#endif
+
+/**
+ * @brief Constructors invocation switch.
+ */
+#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_CONSTRUCTORS TRUE
+#endif
+
+/**
+ * @brief Destructors invocation switch.
+ */
+#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_DESTRUCTORS TRUE
+#endif
+
+/*===========================================================================*/
+/* Code section. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+
+ .cpu cortex-m0
+ .fpu softvfp
+ .syntax unified
+ .thumb
+ .text
+
+/*
+ * CRT0 entry point.
+ */
+ .align 2
+ .thumb_func
+ .global _crt0_entry
+_crt0_entry:
+ /* Interrupts are globally masked initially.*/
+ cpsid i
+
+#if CRT0_FORCE_MSP_INIT == TRUE
+ /* MSP stack pointers initialization.*/
+ ldr r0, =__main_stack_end__
+ msr MSP, r0
+#endif
+
+ /* PSP stack pointers initialization.*/
+ ldr r0, =__process_stack_end__
+ msr PSP, r0
+
+ /* CPU mode initialization as configured.*/
+ movs r0, #CRT0_CONTROL_INIT
+ msr CONTROL, r0
+ isb
+
+#if CRT0_VTOR_INIT == TRUE
+ ldr r0, =_vectors
+ ldr r1, =SCB_VTOR
+ str r0, [r1]
+#endif
+
+#if CRT0_INIT_CORE == TRUE
+ /* Core initialization.*/
+ bl __core_init
+#endif
+
+ /* Early initialization..*/
+ bl __early_init
+
+#if CRT0_INIT_STACKS == TRUE
+ ldr r0, =CRT0_STACKS_FILL_PATTERN
+ /* Main Stack initialization. Note, it assumes that the
+ stack size is a multiple of 4 so the linker file must
+ ensure this.*/
+ ldr r1, =__main_stack_base__
+ ldr r2, =__main_stack_end__
+msloop:
+ cmp r1, r2
+ bge endmsloop
+ str r0, [r1]
+ adds r1, #4
+ b msloop
+endmsloop:
+ /* Process Stack initialization. Note, it assumes that the
+ stack size is a multiple of 4 so the linker file must
+ ensure this.*/
+ ldr r1, =__process_stack_base__
+ ldr r2, =__process_stack_end__
+psloop:
+ cmp r1, r2
+ bge endpsloop
+ str r0, [r1]
+ adds r1, #4
+ b psloop
+endpsloop:
+#endif
+
+#if CRT0_INIT_DATA == TRUE
+ /* Data initialization. Note, it assumes that the DATA size
+ is a multiple of 4 so the linker file must ensure this.*/
+ ldr r1, =__textdata_base__
+ ldr r2, =__data_base__
+ ldr r3, =__data_end__
+dloop:
+ cmp r2, r3
+ bge enddloop
+ ldr r0, [r1]
+ str r0, [r2]
+ adds r1, #4
+ adds r2, #4
+ b dloop
+enddloop:
+#endif
+
+#if CRT0_INIT_BSS == TRUE
+ /* BSS initialization. Note, it assumes that the DATA size
+ is a multiple of 4 so the linker file must ensure this.*/
+ movs r0, #0
+ ldr r1, =__bss_base__
+ ldr r2, =__bss_end__
+bloop:
+ cmp r1, r2
+ bge endbloop
+ str r0, [r1]
+ adds r1, #4
+ b bloop
+endbloop:
+#endif
+
+#if CRT0_INIT_RAM_AREAS == TRUE
+ /* RAM areas initialization.*/
+ bl __init_ram_areas
+#endif
+
+ /* Late initialization..*/
+ bl __late_init
+
+#if CRT0_CALL_CONSTRUCTORS == TRUE
+ /* Constructors invocation.*/
+ ldr r4, =__init_array_base__
+ ldr r5, =__init_array_end__
+initloop:
+ cmp r4, r5
+ bge endinitloop
+ ldr r1, [r4]
+ blx r1
+ adds r4, #4
+ b initloop
+endinitloop:
+#endif
+
+ /* Main program invocation, r0 contains the returned value.*/
+ bl main
+
+#if CRT0_CALL_DESTRUCTORS == TRUE
+ /* Destructors invocation.*/
+ ldr r4, =__fini_array_base__
+ ldr r5, =__fini_array_end__
+finiloop:
+ cmp r4, r5
+ bge endfiniloop
+ ldr r1, [r4]
+ blx r1
+ adds r4, #4
+ b finiloop
+endfiniloop:
+#endif
+
+ /* Branching to the defined exit handler.*/
+ ldr r1, =__default_exit
+ bx r1
+
+#endif
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S new file mode 100644 index 0000000..4ce96d6 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S @@ -0,0 +1,350 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file crt0_v7m.S
+ * @brief Generic ARMv7-M (Cortex-M3/M4/M7) startup file for ChibiOS.
+ *
+ * @addtogroup ARMCMx_GCC_STARTUP_V7M
+ * @{
+ */
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#define CONTROL_MODE_PRIVILEGED 0
+#define CONTROL_MODE_UNPRIVILEGED 1
+#define CONTROL_USE_MSP 0
+#define CONTROL_USE_PSP 2
+#define CONTROL_FPCA 4
+
+#define FPCCR_ASPEN (1 << 31)
+#define FPCCR_LSPEN (1 << 30)
+
+#define SCB_VTOR 0xE000ED08
+#define SCB_CPACR 0xE000ED88
+#define SCB_FPCCR 0xE000EF34
+#define SCB_FPDSCR 0xE000EF3C
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enforces initialization of MSP.
+ * @note This is required if the boot process is not reliable for whatever
+ * reason (bad ROMs, bad bootloaders, bad debuggers=.
+ */
+#if !defined(CRT0_FORCE_MSP_INIT) || defined(__DOXYGEN__)
+#define CRT0_FORCE_MSP_INIT TRUE
+#endif
+
+/**
+ * @brief VTOR special register initialization.
+ * @details VTOR is initialized to point to the vectors table.
+ */
+#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
+#define CRT0_VTOR_INIT TRUE
+#endif
+
+/**
+ * @brief FPU initialization switch.
+ */
+#if !defined(CRT0_INIT_FPU) || defined(__DOXYGEN__)
+#if defined(CORTEX_USE_FPU) || defined(__DOXYGEN__)
+#define CRT0_INIT_FPU CORTEX_USE_FPU
+#else
+#define CRT0_INIT_FPU FALSE
+#endif
+#endif
+
+/**
+ * @brief Control special register initialization value.
+ * @details The system is setup to run in privileged mode using the PSP
+ * stack (dual stack mode).
+ */
+#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
+#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \
+ CONTROL_MODE_PRIVILEGED)
+#endif
+
+/**
+ * @brief Core initialization switch.
+ */
+#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
+#define CRT0_INIT_CORE TRUE
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
+#define CRT0_STACKS_FILL_PATTERN 0x55555555
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
+#define CRT0_INIT_STACKS TRUE
+#endif
+
+/**
+ * @brief DATA segment initialization switch.
+ */
+#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
+#define CRT0_INIT_DATA TRUE
+#endif
+
+/**
+ * @brief BSS segment initialization switch.
+ */
+#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
+#define CRT0_INIT_BSS TRUE
+#endif
+
+/**
+ * @brief RAM areas initialization switch.
+ */
+#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__)
+#define CRT0_INIT_RAM_AREAS TRUE
+#endif
+
+/**
+ * @brief Constructors invocation switch.
+ */
+#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_CONSTRUCTORS TRUE
+#endif
+
+/**
+ * @brief Destructors invocation switch.
+ */
+#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_DESTRUCTORS TRUE
+#endif
+
+/**
+ * @brief FPU FPCCR register initialization value.
+ * @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
+ */
+#if !defined(CRT0_FPCCR_INIT) || defined(__DOXYGEN__)
+#define CRT0_FPCCR_INIT (FPCCR_ASPEN | FPCCR_LSPEN)
+#endif
+
+/**
+ * @brief CPACR register initialization value.
+ * @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
+ */
+#if !defined(CRT0_CPACR_INIT) || defined(__DOXYGEN__)
+#define CRT0_CPACR_INIT 0x00F00000
+#endif
+
+/*===========================================================================*/
+/* Code section. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+
+ .syntax unified
+ .cpu cortex-m3
+#if CRT0_INIT_FPU == TRUE
+ .fpu fpv4-sp-d16
+#else
+ .fpu softvfp
+#endif
+
+ .thumb
+ .text
+
+/*
+ * CRT0 entry point.
+ */
+ .align 2
+ .thumb_func
+ .global _crt0_entry
+_crt0_entry:
+ /* Interrupts are globally masked initially.*/
+ cpsid i
+
+#if CRT0_FORCE_MSP_INIT == TRUE
+ /* MSP stack pointers initialization.*/
+ ldr r0, =__main_stack_end__
+ msr MSP, r0
+#endif
+
+ /* PSP stack pointers initialization.*/
+ ldr r0, =__process_stack_end__
+ msr PSP, r0
+
+#if CRT0_VTOR_INIT == TRUE
+ ldr r0, =_vectors
+ movw r1, #SCB_VTOR & 0xFFFF
+ movt r1, #SCB_VTOR >> 16
+ str r0, [r1]
+#endif
+
+#if CRT0_INIT_FPU == TRUE
+ /* FPU FPCCR initialization.*/
+ movw r0, #CRT0_FPCCR_INIT & 0xFFFF
+ movt r0, #CRT0_FPCCR_INIT >> 16
+ movw r1, #SCB_FPCCR & 0xFFFF
+ movt r1, #SCB_FPCCR >> 16
+ str r0, [r1]
+ dsb
+ isb
+
+ /* CPACR initialization.*/
+ movw r0, #CRT0_CPACR_INIT & 0xFFFF
+ movt r0, #CRT0_CPACR_INIT >> 16
+ movw r1, #SCB_CPACR & 0xFFFF
+ movt r1, #SCB_CPACR >> 16
+ str r0, [r1]
+ dsb
+ isb
+
+ /* FPU FPSCR initially cleared.*/
+ mov r0, #0
+ vmsr FPSCR, r0
+
+ /* FPU FPDSCR initially cleared.*/
+ movw r1, #SCB_FPDSCR & 0xFFFF
+ movt r1, #SCB_FPDSCR >> 16
+ str r0, [r1]
+
+ /* Enforcing FPCA bit in the CONTROL register.*/
+ movs r0, #CRT0_CONTROL_INIT | CONTROL_FPCA
+
+#else
+ movs r0, #CRT0_CONTROL_INIT
+#endif
+
+ /* CONTROL register initialization as configured.*/
+ msr CONTROL, r0
+ isb
+
+#if CRT0_INIT_CORE == TRUE
+ /* Core initialization.*/
+ bl __core_init
+#endif
+
+ /* Early initialization.*/
+ bl __early_init
+
+#if CRT0_INIT_STACKS == TRUE
+ ldr r0, =CRT0_STACKS_FILL_PATTERN
+ /* Main Stack initialization. Note, it assumes that the
+ stack size is a multiple of 4 so the linker file must
+ ensure this.*/
+ ldr r1, =__main_stack_base__
+ ldr r2, =__main_stack_end__
+msloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo msloop
+
+ /* Process Stack initialization. Note, it assumes that the
+ stack size is a multiple of 4 so the linker file must
+ ensure this.*/
+ ldr r1, =__process_stack_base__
+ ldr r2, =__process_stack_end__
+psloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo psloop
+#endif
+
+#if CRT0_INIT_DATA == TRUE
+ /* Data initialization. Note, it assumes that the DATA size
+ is a multiple of 4 so the linker file must ensure this.*/
+ ldr r1, =__textdata_base__
+ ldr r2, =__data_base__
+ ldr r3, =__data_end__
+dloop:
+ cmp r2, r3
+ ittt lo
+ ldrlo r0, [r1], #4
+ strlo r0, [r2], #4
+ blo dloop
+#endif
+
+#if CRT0_INIT_BSS == TRUE
+ /* BSS initialization. Note, it assumes that the DATA size
+ is a multiple of 4 so the linker file must ensure this.*/
+ movs r0, #0
+ ldr r1, =__bss_base__
+ ldr r2, =__bss_end__
+bloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo bloop
+#endif
+
+#if CRT0_INIT_RAM_AREAS == TRUE
+ /* RAM areas initialization.*/
+ bl __init_ram_areas
+#endif
+
+ /* Late initialization..*/
+ bl __late_init
+
+#if CRT0_CALL_CONSTRUCTORS == TRUE
+ /* Constructors invocation.*/
+ ldr r4, =__init_array_base__
+ ldr r5, =__init_array_end__
+initloop:
+ cmp r4, r5
+ bge endinitloop
+ ldr r1, [r4], #4
+ blx r1
+ b initloop
+endinitloop:
+#endif
+
+ /* Main program invocation, r0 contains the returned value.*/
+ bl main
+
+#if CRT0_CALL_DESTRUCTORS == TRUE
+ /* Destructors invocation.*/
+ ldr r4, =__fini_array_base__
+ ldr r5, =__fini_array_end__
+finiloop:
+ cmp r4, r5
+ bge endfiniloop
+ ldr r1, [r4], #4
+ blx r1
+ b finiloop
+endfiniloop:
+#endif
+
+ /* Branching to the defined exit handler.*/
+ b __default_exit
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/crt1.c b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/crt1.c new file mode 100644 index 0000000..87179c4 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/crt1.c @@ -0,0 +1,219 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/compilers/GCC/crt1.c
+ * @brief Startup stub functions.
+ *
+ * @addtogroup ARMCMx_GCC_STARTUP
+ * @{
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "cmparams.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+#if !defined(CRT1_AREAS_NUMBER) || defined(__DOXYGEN__)
+#define CRT1_AREAS_NUMBER 8
+#endif
+
+#if (CRT1_AREAS_NUMBER < 0) || (CRT1_AREAS_NUMBER > 8)
+#error "CRT1_AREAS_NUMBER must be within 0 and 8"
+#endif
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of an area to be initialized.
+ */
+typedef struct {
+ uint32_t *init_text_area;
+ uint32_t *init_area;
+ uint32_t *clear_area;
+ uint32_t *no_init_area;
+} ram_init_area_t;
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+#if (CRT1_AREAS_NUMBER > 0) || defined(__DOXYGEN__)
+extern uint32_t __ram0_init_text__, __ram0_init__, __ram0_clear__, __ram0_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 1) || defined(__DOXYGEN__)
+extern uint32_t __ram1_init_text__, __ram1_init__, __ram1_clear__, __ram1_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 2) || defined(__DOXYGEN__)
+extern uint32_t __ram2_init_text__, __ram2_init__, __ram2_clear__, __ram2_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 3) || defined(__DOXYGEN__)
+extern uint32_t __ram3_init_text__, __ram3_init__, __ram3_clear__, __ram3_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 4) || defined(__DOXYGEN__)
+extern uint32_t __ram4_init_text__, __ram4_init__, __ram4_clear__, __ram4_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 5) || defined(__DOXYGEN__)
+extern uint32_t __ram5_init_text__, __ram5_init__, __ram5_clear__, __ram5_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 6) || defined(__DOXYGEN__)
+extern uint32_t __ram6_init_text__, __ram6_init__, __ram6_clear__, __ram6_noinit__;
+#endif
+#if (CRT1_AREAS_NUMBER > 7) || defined(__DOXYGEN__)
+extern uint32_t __ram7_init_text__, __ram7_init__, __ram7_clear__, __ram7_noinit__;
+#endif
+
+/**
+ * @brief Static table of areas to be initialized.
+ */
+#if (CRT1_AREAS_NUMBER > 0) || defined(__DOXYGEN__)
+static const ram_init_area_t ram_areas[CRT1_AREAS_NUMBER] = {
+ {&__ram0_init_text__, &__ram0_init__, &__ram0_clear__, &__ram0_noinit__},
+#if (CRT1_AREAS_NUMBER > 1) || defined(__DOXYGEN__)
+ {&__ram1_init_text__, &__ram1_init__, &__ram1_clear__, &__ram1_noinit__},
+#endif
+#if (CRT1_AREAS_NUMBER > 2) || defined(__DOXYGEN__)
+ {&__ram2_init_text__, &__ram2_init__, &__ram2_clear__, &__ram2_noinit__},
+#endif
+#if (CRT1_AREAS_NUMBER > 3) || defined(__DOXYGEN__)
+ {&__ram3_init_text__, &__ram3_init__, &__ram3_clear__, &__ram3_noinit__},
+#endif
+#if (CRT1_AREAS_NUMBER > 4) || defined(__DOXYGEN__)
+ {&__ram4_init_text__, &__ram4_init__, &__ram4_clear__, &__ram4_noinit__},
+#endif
+#if (CRT1_AREAS_NUMBER > 5) || defined(__DOXYGEN__)
+ {&__ram5_init_text__, &__ram5_init__, &__ram5_clear__, &__ram5_noinit__},
+#endif
+#if (CRT1_AREAS_NUMBER > 6) || defined(__DOXYGEN__)
+ {&__ram6_init_text__, &__ram6_init__, &__ram6_clear__, &__ram6_noinit__},
+#endif
+#if (CRT1_AREAS_NUMBER > 7) || defined(__DOXYGEN__)
+ {&__ram7_init_text__, &__ram7_init__, &__ram7_clear__, &__ram7_noinit__},
+#endif
+};
+#endif
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Architecture-dependent core initialization.
+ * @details This hook is invoked immediately after the stack initialization
+ * and before the DATA and BSS segments initialization.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __core_init(void) {
+
+#if CORTEX_MODEL == 7
+ SCB_EnableICache();
+ SCB_EnableDCache();
+#endif
+}
+
+/**
+ * @brief Early initialization.
+ * @details This hook is invoked immediately after the stack and core
+ * initialization and before the DATA and BSS segments
+ * initialization.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __early_init(void) {}
+/*lint -restore*/
+
+/**
+ * @brief Late initialization.
+ * @details This hook is invoked after the DATA and BSS segments
+ * initialization and before any static constructor. The
+ * default behavior is to do nothing.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __late_init(void) {}
+/*lint -restore*/
+
+/**
+ * @brief Default @p main() function exit handler.
+ * @details This handler is invoked or the @p main() function exit. The
+ * default behavior is to enter an infinite loop.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((noreturn, weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __default_exit(void) {
+/*lint -restore*/
+
+ while (true) {
+ }
+}
+
+/**
+ * @brief Performs the initialization of the various RAM areas.
+ */
+void __init_ram_areas(void) {
+#if CRT1_AREAS_NUMBER > 0
+ const ram_init_area_t *rap = ram_areas;
+
+ do {
+ uint32_t *tp = rap->init_text_area;
+ uint32_t *p = rap->init_area;
+
+ /* Copying initialization data.*/
+ while (p < rap->clear_area) {
+ *p = *tp;
+ p++;
+ tp++;
+ }
+
+ /* Zeroing clear area.*/
+ while (p < rap->no_init_area) {
+ *p = 0;
+ p++;
+ }
+ rap++;
+ }
+ while (rap < &ram_areas[CRT1_AREAS_NUMBER]);
+#endif
+}
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/ADUCM360.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/ADUCM360.ld new file mode 100644 index 0000000..6393a09 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/ADUCM360.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ADUCM360 memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x00000000, len = 128k /* On-chip Flash/EE */
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 8k /* SRAM */
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/ADUCM410.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/ADUCM410.ld new file mode 100644 index 0000000..be56f7b --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/ADUCM410.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ADUCM410 memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x00000000, len = 512k /* Flash Block 0 */
+ flash1 (rx) : org = 0x00080000, len = 512k /* Flash Block 1 */
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM with ECC */
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x4.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x4.ld new file mode 100644 index 0000000..52c131a --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x4.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F030x4 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 16k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 4k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x6.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x6.ld new file mode 100644 index 0000000..5afc8cb --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x6.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F030x6 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 32k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 4k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x8.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x8.ld new file mode 100644 index 0000000..c2732f0 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F030x8.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F030x8 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 64k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 8k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F031x6.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F031x6.ld new file mode 100644 index 0000000..5ff7b07 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F031x6.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F031x6 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 32k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 4k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F042x6.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F042x6.ld new file mode 100644 index 0000000..22ee72f --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F042x6.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F042x6 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 32k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 6k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F051x8.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F051x8.ld new file mode 100644 index 0000000..89d3cb0 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F051x8.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F051x8 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 64k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 8k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F070x6.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F070x6.ld new file mode 100644 index 0000000..0430df4 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F070x6.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F070x6 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 32k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 6k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F070xB.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F070xB.ld new file mode 100644 index 0000000..a848ef8 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F070xB.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F070xB memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 128k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 16k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F072xB.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F072xB.ld new file mode 100644 index 0000000..353ffb5 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F072xB.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F072xB memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 128k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 16k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F091xC.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F091xC.ld new file mode 100644 index 0000000..fd5b883 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F091xC.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F091xC memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 256k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 32k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F100xB.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F100xB.ld new file mode 100644 index 0000000..fb6ef4f --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F100xB.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F100xB memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 128k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 8k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103x8.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103x8.ld new file mode 100644 index 0000000..3de103d --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103x8.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103x8 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 64k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 20k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xB.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xB.ld new file mode 100644 index 0000000..2a5b200 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xB.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xB memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 128k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 20k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xB_maplemini_bootloader.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xB_maplemini_bootloader.ld new file mode 100644 index 0000000..be17184 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xB_maplemini_bootloader.ld @@ -0,0 +1,88 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xB memory setup for use with the maplemini bootloader.
+ * You will have to
+ * #define CORTEX_VTOR_INIT 0x5000
+ * in your projects chconf.h
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08005000, len = 128k - 0x5000
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000C00, len = 20k - 0xC00
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xD.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xD.ld new file mode 100644 index 0000000..b5bbb32 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xD.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xE memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 384k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 64k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xE.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xE.ld new file mode 100644 index 0000000..082a76e --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xE.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xE memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 512k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 64k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xG.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xG.ld new file mode 100644 index 0000000..02326fa --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F103xG.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xG memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 96k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F107xC.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F107xC.ld new file mode 100644 index 0000000..0b4749a --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F107xC.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F107xC memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 256k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 64k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F207xG.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F207xG.ld new file mode 100644 index 0000000..853d10e --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F207xG.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F207xG memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
+ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F302x8.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F302x8.ld new file mode 100644 index 0000000..f32b744 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F302x8.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F302x8 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 64k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 16k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303x8.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303x8.ld new file mode 100644 index 0000000..739e7a4 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303x8.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F303x8 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 64k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 12k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = 4k
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303xC.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303xC.ld new file mode 100644 index 0000000..c6e2bc8 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303xC.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F303xC memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 256k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 40k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = 8k
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303xE.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303xE.ld new file mode 100644 index 0000000..ac78bde --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F303xE.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F303xE memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 512k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 64k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = 16k
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F334x8.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F334x8.ld new file mode 100644 index 0000000..c95fb24 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F334x8.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F3334x8 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 64k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 12k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = 4k
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F373xC.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F373xC.ld new file mode 100644 index 0000000..fbb3a3b --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F373xC.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F303xC memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 256k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 32k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F401xC.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F401xC.ld new file mode 100644 index 0000000..33b128f --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F401xC.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F401xC memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 256k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 64k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F401xE.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F401xE.ld new file mode 100644 index 0000000..ad8b786 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F401xE.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F401xE memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 512k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 96k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F405xG.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F405xG.ld new file mode 100644 index 0000000..3d0c214 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F405xG.ld @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F405xG memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
+ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F407xE.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F407xE.ld new file mode 100644 index 0000000..b00c3b8 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F407xE.ld @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F407xE memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 512k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
+ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F407xG.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F407xG.ld new file mode 100644 index 0000000..e6d633a --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F407xG.ld @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F407xG memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
+ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F410x8.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F410x8.ld new file mode 100644 index 0000000..6e5fac4 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F410x8.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F410x8 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 64k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 32k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F410xB.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F410xB.ld new file mode 100644 index 0000000..32737bd --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F410xB.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F410xB memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 128k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 32k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F411xC.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F411xC.ld new file mode 100644 index 0000000..4cc2580 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F411xC.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F411xC memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 256k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 128k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F411xE.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F411xE.ld new file mode 100644 index 0000000..dbaafc4 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F411xE.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F411xE memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 512k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 128k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xE.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xE.ld new file mode 100644 index 0000000..e485983 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xE.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F412xE memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 512k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 256k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xG.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xG.ld new file mode 100644 index 0000000..176d33c --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xG.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F412xG memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 256k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F413xH.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F413xH.ld new file mode 100644 index 0000000..2d32dae --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F413xH.ld @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F413xH memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1536k /* Program memory */
+ flash1 (rx) : org = 0x1FFF7800, len = 528 /* OTP memory */
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 320k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20000000, len = 256k /* SRAM1 */
+ ram2 (wx) : org = 0x20040000, len = 64k /* SRAM2 */
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM2 */
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F429xI.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F429xI.ld new file mode 100644 index 0000000..57c9b41 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F429xI.ld @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F429xI memory setup.
+ * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */
+ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x20020000, len = 64k /* SRAM3 */
+ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
+ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F446xC.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F446xC.ld new file mode 100644 index 0000000..9d5ca51 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F446xC.ld @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F446xC memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 256k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 (wx) : org = 0x00000000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F446xE.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F446xE.ld new file mode 100644 index 0000000..de7d56c --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F446xE.ld @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F446xE memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 512k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
+ ram2 (wx) : org = 0x00000000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F469xI.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F469xI.ld new file mode 100644 index 0000000..5dcac00 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F469xI.ld @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F469xI memory setup.
+ * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 384k /* SRAM1 + SRAM2 + SRAM3 */
+ ram1 (wx) : org = 0x20000000, len = 160k /* SRAM1 */
+ ram2 (wx) : org = 0x20028000, len = 32k /* SRAM2 */
+ ram3 (wx) : org = 0x20030000, len = 128k /* SRAM3 */
+ ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
+ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F722xE.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F722xE.ld new file mode 100644 index 0000000..f3915db --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F722xE.ld @@ -0,0 +1,136 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F722xE generic setup.
+ *
+ * RAM0 - Data, Heap.
+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
+ *
+ * Notes:
+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
+ flash1 (rx) : org = 0x00200000, len = 1M /* Flash as ITCM */
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20010000, len = 192k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20010000, len = 176k /* SRAM1 */
+ ram2 (wx) : org = 0x2003C000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x20000000, len = 64k /* DTCM-RAM */
+ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram3);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
+
+/* Memory rules inclusion.*/
+INCLUDE rules_memory.ld
+
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG.ld new file mode 100644 index 0000000..82ce157 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG.ld @@ -0,0 +1,136 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F746xG generic setup.
+ *
+ * RAM0 - Data, Heap.
+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
+ *
+ * Notes:
+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
+ */
+MEMORY
+{
+ flash0 (RX) : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
+ flash1 (RX) : org = 0x00200000, len = 1M /* Flash as ITCM */
+ flash2 (RX) : org = 0x00000000, len = 0
+ flash3 (RX) : org = 0x00000000, len = 0
+ flash4 (RX) : org = 0x00000000, len = 0
+ flash5 (RX) : org = 0x00000000, len = 0
+ flash6 (RX) : org = 0x00000000, len = 0
+ flash7 (RX) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20010000, len = 240k /* SRAM1 */
+ ram2 (wx) : org = 0x2004C000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x20000000, len = 64k /* DTCM-RAM */
+ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram3);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
+
+/* Memory rules inclusion.*/
+INCLUDE rules_memory.ld
+
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld new file mode 100644 index 0000000..6f6de62 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld @@ -0,0 +1,137 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F746xG Ethernet setup.
+ *
+ * RAM1 - Data, Heap.
+ * RAM2 - ETH.
+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE.
+ *
+ * Notes:
+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
+ flash1 (rx) : org = 0x00200000, len = 1M /* Flash as ITCM */
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20010000, len = 240k /* SRAM1 */
+ ram2 (wx) : org = 0x2004C000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x20000000, len = 64k /* DTCM-RAM */
+ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram1);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram3);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram1);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram2);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
+
+/* Memory rules inclusion.*/
+INCLUDE rules_memory.ld
+
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld new file mode 100644 index 0000000..d2917e9 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld @@ -0,0 +1,138 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F746xG maximum RAM setup.
+ *
+ * RAM0 - Data, BSS, Heap.
+ * RAM3 - Main Stack, Process Stack, NOCACHE, ETH.
+ *
+ * Notes:
+ * BSS is placed in cached RAM, DMA buffers management is delegated to the
+ * application code. This setup maximizes the linear RAM available to BSS and
+ * Heap.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
+ flash1 (rx) : org = 0x00200000, len = 1M /* Flash as ITCM */
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20010000, len = 240k /* SRAM1 */
+ ram2 (wx) : org = 0x2004C000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x20000000, len = 64k /* DTCM-RAM */
+ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
+
+/* Memory rules inclusion.*/
+INCLUDE rules_memory.ld
+
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F756xG.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F756xG.ld new file mode 100644 index 0000000..75ba962 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F756xG.ld @@ -0,0 +1,136 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F756xG generic setup.
+ *
+ * RAM0 - Data, Heap.
+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
+ *
+ * Notes:
+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
+ flash1 (rx) : org = 0x00200000, len = 1M /* Flash as ITCM */
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20010000, len = 240k /* SRAM1 */
+ ram2 (wx) : org = 0x2004C000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x20000000, len = 64k /* DTCM-RAM */
+ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram3);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
+
+/* Memory rules inclusion.*/
+INCLUDE rules_memory.ld
+
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxG.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxG.ld new file mode 100644 index 0000000..74d8ba9 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxG.ld @@ -0,0 +1,136 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F76xxG generic setup.
+ *
+ * RAM0 - Data, Heap.
+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
+ *
+ * Notes:
+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
+ flash1 (rx) : org = 0x00200000, len = 1M /* Flash as ITCM */
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */
+ ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
+ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram3);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
+
+/* Memory rules inclusion.*/
+INCLUDE rules_memory.ld
+
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxI.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxI.ld new file mode 100644 index 0000000..19fbfa8 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxI.ld @@ -0,0 +1,136 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F76xxI generic setup.
+ *
+ * RAM0 - Data, Heap.
+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
+ *
+ * Notes:
+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 2M /* Flash as AXIM (writable) */
+ flash1 (rx) : org = 0x00200000, len = 2M /* Flash as ITCM */
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */
+ ram1 (wx) : org = 0x20020000, len = 368k /* SRAM1 */
+ ram2 (wx) : org = 0x2007C000, len = 16k /* SRAM2 */
+ ram3 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
+ ram4 (wx) : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram3);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
+
+/* Memory rules inclusion.*/
+INCLUDE rules_memory.ld
+
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32G071xB.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32G071xB.ld new file mode 100644 index 0000000..a752e3d --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32G071xB.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32G071xB memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 128k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 36k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32G431xB.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32G431xB.ld new file mode 100644 index 0000000..a02962b --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32G431xB.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32G431xB memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 128k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 32k /* SRAM1+SRAM2+CCM */
+ ram1 (wx) : org = 0x20000000, len = 22k /* SRAM1+SRAM2 */
+ ram2 (wx) : org = 0x20000000, len = 16k /* SRAM1 */
+ ram3 (wx) : org = 0x20004000, len = 6k /* SRAM2 */
+ ram4 (wx) : org = 0x20005800, len = 10k /* CCM */
+ ram5 (wx) : org = 0x10000000, len = 10k /* CCM alias */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32G474xE.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32G474xE.ld new file mode 100644 index 0000000..a412843 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32G474xE.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32G474xE memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 512k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1+SRAM2+CCM */
+ ram1 (wx) : org = 0x20000000, len = 96k /* SRAM1+SRAM2 */
+ ram2 (wx) : org = 0x20000000, len = 80k /* SRAM1 */
+ ram3 (wx) : org = 0x20014000, len = 16k /* SRAM2 */
+ ram4 (wx) : org = 0x20018000, len = 32k /* CCM */
+ ram5 (wx) : org = 0x10000000, len = 32k /* CCM alias */
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H743xI.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H743xI.ld new file mode 100755 index 0000000..f715a8f --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H743xI.ld @@ -0,0 +1,139 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32H743xI generic setup.
+ *
+ * AXI SRAM - BSS, Data, Heap.
+ * SRAM1+SRAM2 - None.
+ * SRAM3 - NOCACHE, ETH.
+ * SRAM4 - None.
+ * DTCM-RAM - Main Stack, Process Stack.
+ * ITCM-RAM - None.
+ * BCKP SRAM - None.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 2M /* Flash bank1+bank2 */
+ flash1 (rx) : org = 0x08000000, len = 1M /* Flash bank 1 */
+ flash2 (rx) : org = 0x08100000, len = 1M /* Flash bank 2 */
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x24000000, len = 512k /* AXI SRAM */
+ ram1 (wx) : org = 0x30000000, len = 256k /* AHB SRAM1+SRAM2 */
+ ram2 (wx) : org = 0x30000000, len = 288k /* AHB SRAM1+SRAM2+SRAM3 */
+ ram3 (wx) : org = 0x30040000, len = 32k /* AHB SRAM3 */
+ ram4 (wx) : org = 0x38000000, len = 64k /* AHB SRAM4 */
+ ram5 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
+ ram6 (wx) : org = 0x00000000, len = 64k /* ITCM-RAM */
+ ram7 (wx) : org = 0x38800000, len = 4k /* BCKP SRAM */
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram5);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram5);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32H7xx. */
+/* SRAM3 is assumed to be marked non-cacheable using MPU. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
+
+/* Memory rules inclusion.*/
+INCLUDE rules_memory.ld
+
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H755xI_M7.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H755xI_M7.ld new file mode 100644 index 0000000..11af7dc --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H755xI_M7.ld @@ -0,0 +1,143 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32H755xI (M7 side) generic setup.
+ * Flash1 is assumed to be in use for the M7 core.
+ * Flash2 is not touched and can be used by the M4 core.
+ * RAM1 and RAM2 are assumed to be in use for the M7 core.
+ * RAM3 and RAM4 are not touched and can be used by the M4 core.
+ *
+ * AXI SRAM - BSS, Data, Heap.
+ * SRAM1+SRAM2 - None.
+ * SRAM3 - NOCACHE, ETH.
+ * SRAM4 - None.
+ * DTCM-RAM - Main Stack, Process Stack.
+ * ITCM-RAM - None.
+ * BCKP SRAM - None.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 2M /* Flash bank1+bank2 */
+ flash1 (rx) : org = 0x08000000, len = 1M /* Flash bank 1 */
+ flash2 (rx) : org = 0x08100000, len = 1M /* Flash bank 2 */
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x24000000, len = 512k /* AXI SRAM */
+ ram1 (wx) : org = 0x30000000, len = 256k /* AHB SRAM1+SRAM2 */
+ ram2 (wx) : org = 0x30000000, len = 288k /* AHB SRAM1+SRAM2+SRAM3 */
+ ram3 (wx) : org = 0x30040000, len = 32k /* AHB SRAM3 */
+ ram4 (wx) : org = 0x38000000, len = 64k /* AHB SRAM4 */
+ ram5 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
+ ram6 (wx) : org = 0x00000000, len = 64k /* ITCM-RAM */
+ ram7 (wx) : org = 0x38800000, len = 4k /* BCKP SRAM */
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash1);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash1);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash1);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash1);
+REGION_ALIAS("RODATA_FLASH_LMA", flash1);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash1);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash1);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram5);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram5);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash1);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32H7xx. */
+/* SRAM3 is assumed to be marked non-cacheable using MPU. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
+
+/* Memory rules inclusion.*/
+INCLUDE rules_memory.ld
+
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L011x3.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L011x3.ld new file mode 100644 index 0000000..878feb4 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L011x3.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L011x3 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 8k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 2k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L011x4.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L011x4.ld new file mode 100644 index 0000000..a896621 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L011x4.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L011x4 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 16k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 2k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L031x4.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L031x4.ld new file mode 100644 index 0000000..527783e --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L031x4.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L031x4 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 16k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 8k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L031x6.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L031x6.ld new file mode 100644 index 0000000..c424b5a --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L031x6.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L031x6 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 32k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 8k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L052x6.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L052x6.ld new file mode 100644 index 0000000..e478aad --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L052x6.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L052x8 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 16k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 8k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L052x8.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L052x8.ld new file mode 100644 index 0000000..64f0c15 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L052x8.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L052x8 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 64k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 8k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L053x6.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L053x6.ld new file mode 100644 index 0000000..6b2116d --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L053x6.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L053x6 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 32k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 8k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L053x8.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L053x8.ld new file mode 100644 index 0000000..3a6f917 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L053x8.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L053x8 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 64k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 8k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073x8.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073x8.ld new file mode 100644 index 0000000..7503de2 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073x8.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L073x8 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 64k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 20k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073xB.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073xB.ld new file mode 100644 index 0000000..1b92681 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073xB.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L073xB memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 128k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 20k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073xZ.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073xZ.ld new file mode 100644 index 0000000..e60ebe0 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L073xZ.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L073xZ memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 192k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 20k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L151x6.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L151x6.ld new file mode 100644 index 0000000..8ec6e1b --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L151x6.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L151x6 memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 32k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 10k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L152xB.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L152xB.ld new file mode 100644 index 0000000..e899a77 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L152xB.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L152xB memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 128k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 16k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L152xE.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L152xE.ld new file mode 100644 index 0000000..5552026 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L152xE.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L152xB memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 512k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 80k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L432xB.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L432xB.ld new file mode 100644 index 0000000..f7e723b --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L432xB.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L432xB memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 128k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 64k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L432xC.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L432xC.ld new file mode 100644 index 0000000..e09722f --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L432xC.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L432xC memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 256k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 64k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L452xE.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L452xE.ld new file mode 100644 index 0000000..d84ddb6 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L452xE.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L452xE memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 512k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 128k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = 32k /* This memory also mapped at address 0x20020000 */
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L476xG.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L476xG.ld new file mode 100644 index 0000000..986e259 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L476xG.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L476xG memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 96k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = 32k
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L496xG.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L496xG.ld new file mode 100644 index 0000000..d773328 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L496xG.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L496xG memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 1M
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 256k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x10000000, len = 64k /* This memory also mapped at address 0x20040000 */
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L4R5xI.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L4R5xI.ld new file mode 100644 index 0000000..64ed234 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L4R5xI.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L4R5xI memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 2M
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 640k /* SRAM1+SRAM2+SRAM3 */
+ ram1 (wx) : org = 0x20000000, len = 192k /* SRAM1 */
+ ram2 (wx) : org = 0x00000000, len = 64k /* SRAM2 */
+ ram3 (wx) : org = 0x00000000, len = 384k /* SRAM3 */
+ ram4 (wx) : org = 0x10000000, len = 64k /* SRAM2 alias */
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L4R9xI.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L4R9xI.ld new file mode 100644 index 0000000..a985bee --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L4R9xI.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L4R9xI memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 2M
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 640k /* SRAM1+SRAM2+SRAM3 */
+ ram1 (wx) : org = 0x20000000, len = 192k /* SRAM1 */
+ ram2 (wx) : org = 0x00000000, len = 64k /* SRAM2 */
+ ram3 (wx) : org = 0x00000000, len = 384k /* SRAM3 */
+ ram4 (wx) : org = 0x10000000, len = 64k /* SRAM2 alias */
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules.ld new file mode 100644 index 0000000..8ca9a47 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules.ld @@ -0,0 +1,11 @@ +/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
+
+/* Memory rules inclusion.*/
+INCLUDE rules_memory.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules_code.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules_code.ld new file mode 100644 index 0000000..5a288af --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules_code.ld @@ -0,0 +1,80 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .vectors : ALIGN(1024)
+ {
+ KEEP(*(.vectors))
+ } > VECTORS_FLASH AT > VECTORS_FLASH_LMA
+
+ .xtors : ALIGN(4)
+ {
+ __init_array_base__ = .;
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ __init_array_end__ = .;
+ __fini_array_base__ = .;
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ __fini_array_end__ = .;
+ } > XTORS_FLASH AT > XTORS_FLASH_LMA
+
+ .text : ALIGN_WITH_INPUT
+ {
+ __text_base__ = .;
+ *(.text)
+ *(.text.*)
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ __text_end__ = .;
+ } > TEXT_FLASH AT > TEXT_FLASH_LMA
+
+ .rodata : ALIGN(4)
+ {
+ __rodata_base__ = .;
+ *(.rodata)
+ *(.rodata.*)
+ . = ALIGN(4);
+ __rodata_end__ = .;
+ } > RODATA_FLASH AT > RODATA_FLASH_LMA
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA
+
+ .ARM.exidx : {
+ __exidx_base__ = .;
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end__ = .;
+ __exidx_end = .;
+ } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules_data.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules_data.ld new file mode 100644 index 0000000..c7fe00c --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules_data.ld @@ -0,0 +1,43 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+SECTIONS
+{
+ .data : ALIGN(4)
+ {
+ PROVIDE(_textdata = LOADADDR(.data));
+ PROVIDE(_data = .);
+ __textdata_base__ = LOADADDR(.data);
+ __data_base__ = .;
+ *(.data)
+ *(.data.*)
+ *(.ramtext)
+ . = ALIGN(4);
+ PROVIDE(_edata = .);
+ __data_end__ = .;
+ } > DATA_RAM AT > DATA_RAM_LMA
+
+ .bss (NOLOAD) : ALIGN(4)
+ {
+ __bss_base__ = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ PROVIDE(end = .);
+ } > BSS_RAM
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules_memory.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules_memory.ld new file mode 100644 index 0000000..ab914b6 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules_memory.ld @@ -0,0 +1,317 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +__ram0_base__ = ORIGIN(ram0); +__ram0_size__ = LENGTH(ram0); +__ram0_end__ = __ram0_base__ + __ram0_size__; +__ram1_base__ = ORIGIN(ram1); +__ram1_size__ = LENGTH(ram1); +__ram1_end__ = __ram1_base__ + __ram1_size__; +__ram2_base__ = ORIGIN(ram2); +__ram2_size__ = LENGTH(ram2); +__ram2_end__ = __ram2_base__ + __ram2_size__; +__ram3_base__ = ORIGIN(ram3); +__ram3_size__ = LENGTH(ram3); +__ram3_end__ = __ram3_base__ + __ram3_size__; +__ram4_base__ = ORIGIN(ram4); +__ram4_size__ = LENGTH(ram4); +__ram4_end__ = __ram4_base__ + __ram4_size__; +__ram5_base__ = ORIGIN(ram5); +__ram5_size__ = LENGTH(ram5); +__ram5_end__ = __ram5_base__ + __ram5_size__; +__ram6_base__ = ORIGIN(ram6); +__ram6_size__ = LENGTH(ram6); +__ram6_end__ = __ram6_base__ + __ram6_size__; +__ram7_base__ = ORIGIN(ram7); +__ram7_size__ = LENGTH(ram7); +__ram7_end__ = __ram7_base__ + __ram7_size__; + +__flash0_base__ = ORIGIN(flash0); +__flash0_size__ = LENGTH(flash0); +__flash0_end__ = __flash0_base__ + __flash0_size__; +__flash1_base__ = ORIGIN(flash1); +__flash1_size__ = LENGTH(flash1); +__flash1_end__ = __flash1_base__ + __flash1_size__; +__flash2_base__ = ORIGIN(flash2); +__flash2_size__ = LENGTH(flash2); +__flash2_end__ = __flash2_base__ + __flash2_size__; +__flash3_base__ = ORIGIN(flash3); +__flash3_size__ = LENGTH(flash3); +__flash3_end__ = __flash3_base__ + __flash3_size__; +__flash4_base__ = ORIGIN(flash4); +__flash4_size__ = LENGTH(flash4); +__flash4_end__ = __flash4_base__ + __flash4_size__; +__flash5_base__ = ORIGIN(flash5); +__flash5_size__ = LENGTH(flash5); +__flash5_end__ = __flash5_base__ + __flash5_size__; +__flash6_base__ = ORIGIN(flash6); +__flash6_size__ = LENGTH(flash6); +__flash6_end__ = __flash6_base__ + __flash6_size__; +__flash7_base__ = ORIGIN(flash7); +__flash7_size__ = LENGTH(flash7); +__flash7_end__ = __flash7_base__ + __flash7_size__; + +SECTIONS +{ + .ram0_init : ALIGN(4) + { + __ram0_init_text__ = LOADADDR(.ram0_init); + __ram0_init__ = .; + KEEP(*(.ram0_init)) + KEEP(*(.ram0_init.*)) + . = ALIGN(4); + } > ram0 AT > RAM_INIT_FLASH_LMA + + .ram0 (NOLOAD) : ALIGN(4) + { + __ram0_clear__ = .; + *(.ram0_clear) + *(.ram0_clear.*) + . = ALIGN(4); + __ram0_noinit__ = .; + *(.ram0) + *(.ram0.*) + . = ALIGN(4); + __ram0_free__ = .; + } > ram0 + + .ram1_init : ALIGN(4) + { + __ram1_init_text__ = LOADADDR(.ram1_init); + __ram1_init__ = .; + KEEP(*(.ram1_init)) + KEEP(*(.ram1_init.*)) + . = ALIGN(4); + } > ram1 AT > RAM_INIT_FLASH_LMA + + .ram1 (NOLOAD) : ALIGN(4) + { + __ram1_clear__ = .; + *(.ram1_clear) + *(.ram1_clear.*) + . = ALIGN(4); + __ram1_noinit__ = .; + *(.ram1) + *(.ram1.*) + . = ALIGN(4); + __ram1_free__ = .; + } > ram1 + + .ram2_init : ALIGN(4) + { + __ram2_init_text__ = LOADADDR(.ram2_init); + __ram2_init__ = .; + KEEP(*(.ram2_init)) + KEEP(*(.ram2_init.*)) + . = ALIGN(4); + } > ram2 AT > RAM_INIT_FLASH_LMA + + .ram2 (NOLOAD) : ALIGN(4) + { + __ram2_clear__ = .; + *(.ram2_clear) + *(.ram2_clear.*) + . = ALIGN(4); + __ram2_noinit__ = .; + *(.ram2) + *(.ram2.*) + . = ALIGN(4); + __ram2_free__ = .; + } > ram2 + + .ram3_init : ALIGN(4) + { + __ram3_init_text__ = LOADADDR(.ram3_init); + __ram3_init__ = .; + KEEP(*(.ram3_init)) + KEEP(*(.ram3_init.*)) + . = ALIGN(4); + } > ram3 AT > RAM_INIT_FLASH_LMA + + .ram3 (NOLOAD) : ALIGN(4) + { + __ram3_clear__ = .; + *(.ram3_clear) + *(.ram3_clear.*) + . = ALIGN(4); + __ram3_noinit__ = .; + *(.ram3) + *(.ram3.*) + . = ALIGN(4); + __ram3_free__ = .; + } > ram3 + + .ram4_init : ALIGN(4) + { + __ram4_init_text__ = LOADADDR(.ram4_init); + __ram4_init__ = .; + KEEP(*(.ram4_init)) + KEEP(*(.ram4_init.*)) + . = ALIGN(4); + } > ram4 AT > RAM_INIT_FLASH_LMA + + .ram4 (NOLOAD) : ALIGN(4) + { + __ram4_clear__ = .; + *(.ram4_clear) + *(.ram4_clear.*) + . = ALIGN(4); + __ram4_noinit__ = .; + *(.ram4) + *(.ram4.*) + . = ALIGN(4); + __ram4_free__ = .; + } > ram4 + + .ram5_init : ALIGN(4) + { + __ram5_init_text__ = LOADADDR(.ram5_init); + __ram5_init__ = .; + KEEP(*(.ram5_init)) + KEEP(*(.ram5_init.*)) + . = ALIGN(4); + } > ram5 AT > RAM_INIT_FLASH_LMA + + .ram5 (NOLOAD) : ALIGN(4) + { + __ram5_clear__ = .; + *(.ram5_clear) + *(.ram5_clear.*) + . = ALIGN(4); + __ram5_noinit__ = .; + *(.ram5) + *(.ram5.*) + . = ALIGN(4); + __ram5_free__ = .; + } > ram5 + + .ram6_init : ALIGN(4) + { + __ram6_init_text__ = LOADADDR(.ram6_init); + __ram6_init__ = .; + KEEP(*(.ram6_init)) + KEEP(*(.ram6_init.*)) + . = ALIGN(4); + } > ram6 AT > RAM_INIT_FLASH_LMA + + .ram6 (NOLOAD) : ALIGN(4) + { + __ram6_clear__ = .; + *(.ram6_clear) + *(.ram6_clear.*) + . = ALIGN(4); + __ram6_noinit__ = .; + *(.ram6) + *(.ram6.*) + . = ALIGN(4); + __ram6_free__ = .; + } > ram6 + + .ram7_init : ALIGN(4) + { + __ram7_init_text__ = LOADADDR(.ram7_init); + __ram7_init__ = .; + KEEP(*(.ram7_init)) + KEEP(*(.ram7_init.*)) + . = ALIGN(4); + } > ram7 AT > RAM_INIT_FLASH_LMA + + .ram7 (NOLOAD) : ALIGN(4) + { + __ram7_clear__ = .; + *(.ram7_clear) + *(.ram7_clear.*) + . = ALIGN(4); + __ram7_noinit__ = .; + *(.ram7) + *(.ram7.*) + . = ALIGN(4); + __ram7_free__ = .; + } > ram7 + + .flash0 : ALIGN(4) + { + __flash0_init__ = .; + KEEP(*(.flash0_init)) + KEEP(*(.flash0_init.*)) + __flash0_free__ = .; + } > flash0 + + .flash1 : ALIGN(4) + { + __flash1_init__ = .; + KEEP(*(.flash1_init)) + KEEP(*(.flash1_init.*)) + __flash1_free__ = .; + } > flash1 + + .flash2 : ALIGN(4) + { + __flash2_init__ = .; + KEEP(*(.flash2_init)) + KEEP(*(.flash2_init.*)) + __flash2_free__ = .; + } > flash2 + + .flash3 : ALIGN(4) + { + __flash3_init__ = .; + KEEP(*(.flash3_init)) + KEEP(*(.flash3_init.*)) + __flash3_free__ = .; + } > flash3 + + .flash4 : ALIGN(4) + { + __flash4_init__ = .; + KEEP(*(.flash4_init)) + KEEP(*(.flash4_init.*)) + __flash4_free__ = .; + } > flash4 + + .flash5 : ALIGN(4) + { + __flash5_init__ = .; + KEEP(*(.flash5_init)) + KEEP(*(.flash5_init.*)) + __flash5_free__ = .; + } > flash5 + + .flash6 : ALIGN(4) + { + __flash6_init__ = .; + KEEP(*(.flash6_init)) + KEEP(*(.flash6_init.*)) + __flash6_free__ = .; + } > flash6 + + .flash7 : ALIGN(4) + { + __flash7_init__ = .; + KEEP(*(.flash7_init)) + KEEP(*(.flash7_init.*)) + __flash7_free__ = .; + } > flash7 + + /* The default heap uses the (statically) unused part of a RAM section.*/ + .heap (NOLOAD) : + { + . = ALIGN(8); + __heap_base__ = .; + . = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM); + __heap_end__ = .; + } > HEAP_RAM +} diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules_stacks.ld b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules_stacks.ld new file mode 100644 index 0000000..1c64a44 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/ld/rules_stacks.ld @@ -0,0 +1,40 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+SECTIONS
+{
+ /* Special section for exceptions stack.*/
+ .mstack (NOLOAD) :
+ {
+ . = ALIGN(8);
+ __main_stack_base__ = .;
+ . += __main_stack_size__;
+ . = ALIGN(8);
+ __main_stack_end__ = .;
+ } > MAIN_STACK_RAM
+
+ /* Special section for process stack.*/
+ .pstack (NOLOAD) :
+ {
+ . = ALIGN(8);
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > PROCESS_STACK_RAM
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/arm-none-eabi.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/arm-none-eabi.mk new file mode 100644 index 0000000..5df5fe2 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/arm-none-eabi.mk @@ -0,0 +1,23 @@ +##############################################################################
+# Compiler settings
+#
+
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+#
+# Compiler settings
+##############################################################################
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/rules.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/rules.mk new file mode 100644 index 0000000..4f7178d --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/rules.mk @@ -0,0 +1,291 @@ +# ARM Cortex-Mx common makefile scripts and rules.
+
+##############################################################################
+# Processing options coming from the upper Makefile.
+#
+
+# Compiler options
+OPT := $(USE_OPT)
+COPT := $(USE_COPT)
+CPPOPT := $(USE_CPPOPT)
+
+# Garbage collection
+ifeq ($(USE_LINK_GC),yes)
+ OPT += -ffunction-sections -fdata-sections -fno-common
+ LDOPT := ,--gc-sections
+else
+ LDOPT :=
+endif
+
+# Linker extra options
+ifneq ($(USE_LDOPT),)
+ LDOPT := $(LDOPT),$(USE_LDOPT)
+endif
+
+# Link time optimizations
+ifeq ($(USE_LTO),yes)
+ OPT += -flto
+endif
+
+# FPU options default (Cortex-M4 and Cortex-M7 single precision).
+ifeq ($(USE_FPU_OPT),)
+ USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16
+endif
+
+# FPU-related options
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+ifneq ($(USE_FPU),no)
+ OPT += $(USE_FPU_OPT)
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+ DADEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+ DADEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
+# Process stack size
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE)
+endif
+
+# Exceptions stack size
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__main_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__main_stack_size__=$(USE_EXCEPTIONS_STACKSIZE)
+endif
+
+# Output directory and files
+ifeq ($(BUILDDIR),)
+ BUILDDIR = build
+endif
+ifeq ($(BUILDDIR),.)
+ BUILDDIR = build
+endif
+
+# Dependencies directory
+ifeq ($(DEPDIR),)
+ DEPDIR = .dep
+endif
+ifeq ($(DEPDIR),.)
+ DEPDIR = .dep
+endif
+
+OUTFILES := $(BUILDDIR)/$(PROJECT).elf \
+ $(BUILDDIR)/$(PROJECT).hex \
+ $(BUILDDIR)/$(PROJECT).bin \
+ $(BUILDDIR)/$(PROJECT).dmp \
+ $(BUILDDIR)/$(PROJECT).list
+
+ifdef SREC
+ OUTFILES += $(BUILDDIR)/$(PROJECT).srec
+endif
+
+# Source files groups and paths
+TCSRC += $(CSRC)
+TCPPSRC += $(CPPSRC)
+TSRC := $(TCSRC) $(TCPPSRC)
+SRCPATHS := $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(TSRC)))
+
+# Various directories
+OBJDIR := $(BUILDDIR)/obj
+LSTDIR := $(BUILDDIR)/lst
+
+# Object files groups
+TCOBJS := $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
+#TCPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
+TCPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(patsubst %.cpp, %.o, $(filter %.cpp, $(TCPPSRC)))))
+TCCOBJS := $(addprefix $(OBJDIR)/, $(notdir $(patsubst %.cc, %.o, $(filter %.cc, $(TCPPSRC)))))
+ASMOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
+ASMXOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+#OBJS := $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
+OBJS := $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) $(TCCOBJS)
+
+# Paths
+IINCDIR := $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
+LLIBDIR := $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+
+# Macros
+DEFS := $(DDEFS) $(UDEFS)
+ADEFS := $(DADEFS) $(UADEFS)
+
+# Libs
+LIBS := $(DLIBS) $(ULIBS)
+
+# Various settings
+MCFLAGS := -mcpu=$(MCU) -mthumb
+ODFLAGS = -x --syms
+ASFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+ASXFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
+CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
+CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
+LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(STARTUPLD),--script=$(LDSCRIPT)$(LDOPT)
+
+# Generate dependency information
+ASFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+ASXFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+CFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+CPPFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+
+# Paths where to search for sources
+VPATH = $(SRCPATHS)
+
+#
+# Makefile rules
+#
+
+all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK
+
+PRE_MAKE_ALL_RULE_HOOK:
+
+POST_MAKE_ALL_RULE_HOOK:
+
+$(OBJS): | PRE_MAKE_ALL_RULE_HOOK $(BUILDDIR) $(OBJDIR) $(LSTDIR) $(DEPDIR)
+
+$(BUILDDIR):
+ifneq ($(USE_VERBOSE_COMPILE),yes)
+ @echo Compiler Options
+ @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
+ @echo
+endif
+ @mkdir -p $(BUILDDIR)
+
+$(OBJDIR):
+ @mkdir -p $(OBJDIR)
+
+$(LSTDIR):
+ @mkdir -p $(LSTDIR)
+
+$(DEPDIR):
+ @mkdir -p $(DEPDIR)
+
+$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCCOBJS) : $(OBJDIR)/%.o : %.cc $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCOBJS) : $(OBJDIR)/%.o : %.c $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMOBJS) : $(OBJDIR)/%.o : %.s $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(BUILDDIR)/$(PROJECT).elf: $(OBJS) $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+else
+ @echo Linking $@
+ @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+endif
+
+%.hex: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(HEX) $< $@
+else
+ @echo Creating $@
+ @$(HEX) $< $@
+endif
+
+%.bin: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(BIN) $< $@
+else
+ @echo Creating $@
+ @$(BIN) $< $@
+endif
+
+%.srec: %.elf
+ifdef SREC
+ ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(SREC) $< $@
+ else
+ @echo Creating $@
+ @$(SREC) $< $@
+ endif
+endif
+
+%.dmp: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(OD) $(ODFLAGS) $< > $@
+ $(SZ) $<
+else
+ @echo Creating $@
+ @$(OD) $(ODFLAGS) $< > $@
+ @echo
+ @$(SZ) $<
+endif
+
+%.list: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(OD) -S $< > $@
+else
+ @echo Creating $@
+ @$(OD) -S $< > $@
+ @echo
+ @echo Done
+endif
+
+lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a
+
+$(BUILDDIR)/lib$(PROJECT).a: $(OBJS)
+ @$(AR) -r $@ $^
+ @echo
+ @echo Done
+
+clean: CLEAN_RULE_HOOK
+ @echo Cleaning
+ @echo - $(DEPDIR)
+ @-rm -fR $(DEPDIR)/* $(BUILDDIR)/* 2>/dev/null
+ @-if [ -d "$(DEPDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(DEPDIR)) 2>/dev/null; fi
+ @echo - $(BUILDDIR)
+ @-if [ -d "$(BUILDDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(BUILDDIR)) 2>/dev/null; fi
+ @echo
+ @echo Done
+
+CLEAN_RULE_HOOK:
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(wildcard $(DEPDIR)/*)
+
+# *** EOF ***
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_aducm36x.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_aducm36x.mk new file mode 100644 index 0000000..7a9ad98 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_aducm36x.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic ADUCM36x startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/ADUCM36x \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ADI/ADUCM36x
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_aducm41x.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_aducm41x.mk new file mode 100644 index 0000000..c40b34b --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_aducm41x.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic ADUCM41x startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/ADUCM41x \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ADI/ADUCM41x
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk new file mode 100644 index 0000000..3101560 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic STM32F0xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F0xx \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ST/STM32F0xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk new file mode 100644 index 0000000..0247e72 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic STM32F1xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F1xx \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ST/STM32F1xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f2xx.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f2xx.mk new file mode 100644 index 0000000..e216f1e --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f2xx.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic STM32F2xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F2xx \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ST/STM32F2xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk new file mode 100644 index 0000000..7650405 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic STM32F3xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F3xx \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ST/STM32F3xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk new file mode 100644 index 0000000..e0c8d55 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic STM32F4xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F4xx \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ST/STM32F4xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk new file mode 100644 index 0000000..1846f43 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic STM32F7xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F7xx \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ST/STM32F7xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32g0xx.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32g0xx.mk new file mode 100644 index 0000000..5f9eb71 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32g0xx.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic STM32G0xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32G0xx \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ST/STM32G0xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32g4xx.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32g4xx.mk new file mode 100644 index 0000000..669ff62 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32g4xx.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic STM32G4xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32G4xx \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ST/STM32G4xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk new file mode 100644 index 0000000..e467162 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic STM32H7xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32H7xx \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ST/STM32H7xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l0xx.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l0xx.mk new file mode 100644 index 0000000..0c6fc35 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l0xx.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic STM32L0xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32L0xx \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ST/STM32L0xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l1xx.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l1xx.mk new file mode 100644 index 0000000..96510e4 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l1xx.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic STM32L1xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32L1xx \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ST/STM32L1xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk new file mode 100644 index 0000000..87f6587 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic STM32L4xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32L4xx \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/ST/STM32L4xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/vectors.S b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/vectors.S new file mode 100644 index 0000000..ef1c7bc --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/GCC/vectors.S @@ -0,0 +1,1031 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/GCC/vectors.S
+ * @brief Interrupt vectors for Cortex-Mx devices.
+ *
+ * @defgroup ARMCMx_GCC_VECTORS Cortex-Mx Interrupt Vectors
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "cmparams.h"
+
+#if (CORTEX_NUM_VECTORS % 8) != 0
+#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8"
+#endif
+
+#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240)
+#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive"
+#endif
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Code section. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+
+ .syntax unified
+ .cpu cortex-m0
+ .thumb
+
+ .section .vectors, "ax"
+ .align 4
+ .globl _vectors
+_vectors:
+ .long __main_stack_end__
+ .long Reset_Handler
+ .long NMI_Handler
+ .long HardFault_Handler
+ .long MemManage_Handler
+ .long BusFault_Handler
+ .long UsageFault_Handler
+ .long Vector1C
+ .long Vector20
+ .long Vector24
+ .long Vector28
+ .long SVC_Handler
+ .long DebugMon_Handler
+ .long Vector34
+ .long PendSV_Handler
+ .long SysTick_Handler
+ .long Vector40, Vector44, Vector48, Vector4C
+#if CORTEX_NUM_VECTORS > 4
+ .long Vector50, Vector54, Vector58, Vector5C
+#endif
+#if CORTEX_NUM_VECTORS > 8
+ .long Vector60, Vector64, Vector68, Vector6C
+#endif
+#if CORTEX_NUM_VECTORS > 12
+ .long Vector70, Vector74, Vector78, Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ .long Vector80, Vector84, Vector88, Vector8C
+#endif
+#if CORTEX_NUM_VECTORS > 20
+ .long Vector90, Vector94, Vector98, Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ .long VectorA0, VectorA4, VectorA8, VectorAC
+#endif
+#if CORTEX_NUM_VECTORS > 28
+ .long VectorB0, VectorB4, VectorB8, VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ .long VectorC0, VectorC4, VectorC8, VectorCC
+#endif
+#if CORTEX_NUM_VECTORS > 36
+ .long VectorD0, VectorD4, VectorD8, VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ .long VectorE0, VectorE4, VectorE8, VectorEC
+#endif
+#if CORTEX_NUM_VECTORS > 44
+ .long VectorF0, VectorF4, VectorF8, VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ .long Vector100, Vector104, Vector108, Vector10C
+#endif
+#if CORTEX_NUM_VECTORS > 52
+ .long Vector110, Vector114, Vector118, Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ .long Vector120, Vector124, Vector128, Vector12C
+#endif
+#if CORTEX_NUM_VECTORS > 60
+ .long Vector130, Vector134, Vector138, Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ .long Vector140, Vector144, Vector148, Vector14C
+#endif
+#if CORTEX_NUM_VECTORS > 68
+ .long Vector150, Vector154, Vector158, Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ .long Vector160, Vector164, Vector168, Vector16C
+#endif
+#if CORTEX_NUM_VECTORS > 76
+ .long Vector170, Vector174, Vector178, Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ .long Vector180, Vector184, Vector188, Vector18C
+#endif
+#if CORTEX_NUM_VECTORS > 84
+ .long Vector190, Vector194, Vector198, Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ .long Vector1A0, Vector1A4, Vector1A8, Vector1AC
+#endif
+#if CORTEX_NUM_VECTORS > 92
+ .long Vector1B0, Vector1B4, Vector1B8, Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ .long Vector1C0, Vector1C4, Vector1C8, Vector1CC
+#endif
+#if CORTEX_NUM_VECTORS > 100
+ .long Vector1D0, Vector1D4, Vector1D8, Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ .long Vector1E0, Vector1E4, Vector1E8, Vector1EC
+#endif
+#if CORTEX_NUM_VECTORS > 108
+ .long Vector1F0, Vector1F4, Vector1F8, Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ .long Vector200, Vector204, Vector208, Vector20C
+#endif
+#if CORTEX_NUM_VECTORS > 116
+ .long Vector210, Vector214, Vector218, Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ .long Vector220, Vector224, Vector228, Vector22C
+#endif
+#if CORTEX_NUM_VECTORS > 124
+ .long Vector230, Vector234, Vector238, Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ .long Vector240, Vector244, Vector248, Vector24C
+#endif
+#if CORTEX_NUM_VECTORS > 132
+ .long Vector250, Vector254, Vector258, Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ .long Vector260, Vector264, Vector268, Vector26C
+#endif
+#if CORTEX_NUM_VECTORS > 140
+ .long Vector270, Vector274, Vector278, Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ .long Vector280, Vector284, Vector288, Vector28C
+#endif
+#if CORTEX_NUM_VECTORS > 148
+ .long Vector290, Vector294, Vector298, Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ .long Vector2A0, Vector2A4, Vector2A8, Vector2AC
+#endif
+#if CORTEX_NUM_VECTORS > 156
+ .long Vector2B0, Vector2B4, Vector2B8, Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ .long Vector2C0, Vector2C4, Vector2C8, Vector2CC
+#endif
+#if CORTEX_NUM_VECTORS > 164
+ .long Vector2D0, Vector2D4, Vector2D8, Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ .long Vector2E0, Vector2E4, Vector2E8, Vector2EC
+#endif
+#if CORTEX_NUM_VECTORS > 172
+ .long Vector2F0, Vector2F4, Vector2F8, Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ .long Vector300, Vector304, Vector308, Vector30C
+#endif
+#if CORTEX_NUM_VECTORS > 180
+ .long Vector310, Vector314, Vector318, Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ .long Vector320, Vector324, Vector328, Vector32C
+#endif
+#if CORTEX_NUM_VECTORS > 188
+ .long Vector330, Vector334, Vector338, Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ .long Vector340, Vector344, Vector348, Vector34C
+#endif
+#if CORTEX_NUM_VECTORS > 196
+ .long Vector350, Vector354, Vector358, Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ .long Vector360, Vector364, Vector368, Vector36C
+#endif
+#if CORTEX_NUM_VECTORS > 204
+ .long Vector370, Vector374, Vector378, Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ .long Vector380, Vector384, Vector388, Vector38C
+#endif
+#if CORTEX_NUM_VECTORS > 212
+ .long Vector390, Vector394, Vector398, Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ .long Vector3A0, Vector3A4, Vector3A8, Vector3AC
+#endif
+#if CORTEX_NUM_VECTORS > 220
+ .long Vector3B0, Vector3B4, Vector3B8, Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ .long Vector3C0, Vector3C4, Vector3C8, Vector3CC
+#endif
+#if CORTEX_NUM_VECTORS > 228
+ .long Vector3D0, Vector3D4, Vector3D8, Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ .long Vector3E0, Vector3E4, Vector3E8, Vector3EC
+#endif
+#if CORTEX_NUM_VECTORS > 236
+ .long Vector3F0, Vector3F4, Vector3F8, Vector3FC
+#endif
+
+ .text
+
+ .align 2
+ .thumb_func
+ .weak Reset_Handler
+Reset_Handler:
+ b _crt0_entry
+
+ .thumb_func
+ .weak NMI_Handler
+ .weak HardFault_Handler
+ .weak MemManage_Handler
+ .weak BusFault_Handler
+ .weak UsageFault_Handler
+ .weak Vector1C
+ .weak Vector20
+ .weak Vector24
+ .weak Vector28
+ .weak SVC_Handler
+ .weak DebugMon_Handler
+ .weak Vector34
+ .weak PendSV_Handler
+ .weak SysTick_Handler
+ .weak Vector40, Vector44, Vector48, Vector4C
+#if CORTEX_NUM_VECTORS > 4
+ .weak Vector50, Vector54, Vector58, Vector5C
+#endif
+#if CORTEX_NUM_VECTORS > 8
+ .weak Vector60, Vector64, Vector68, Vector6C
+#endif
+#if CORTEX_NUM_VECTORS > 12
+ .weak Vector70, Vector74, Vector78, Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ .weak Vector80, Vector84, Vector88, Vector8C
+#endif
+#if CORTEX_NUM_VECTORS > 20
+ .weak Vector90, Vector94, Vector98, Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ .weak VectorA0, VectorA4, VectorA8, VectorAC
+#endif
+#if CORTEX_NUM_VECTORS > 28
+ .weak VectorB0, VectorB4, VectorB8, VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ .weak VectorC0, VectorC4, VectorC8, VectorCC
+#endif
+#if CORTEX_NUM_VECTORS > 36
+ .weak VectorD0, VectorD4, VectorD8, VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ .weak VectorE0, VectorE4, VectorE8, VectorEC
+#endif
+#if CORTEX_NUM_VECTORS > 44
+ .weak VectorF0, VectorF4, VectorF8, VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ .weak Vector100, Vector104, Vector108, Vector10C
+#endif
+#if CORTEX_NUM_VECTORS > 52
+ .weak Vector110, Vector114, Vector118, Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ .weak Vector120, Vector124, Vector128, Vector12C
+#endif
+#if CORTEX_NUM_VECTORS > 60
+ .weak Vector130, Vector134, Vector138, Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ .weak Vector140, Vector144, Vector148, Vector14C
+#endif
+#if CORTEX_NUM_VECTORS > 68
+ .weak Vector150, Vector154, Vector158, Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ .weak Vector160, Vector164, Vector168, Vector16C
+#endif
+#if CORTEX_NUM_VECTORS > 76
+ .weak Vector170, Vector174, Vector178, Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ .weak Vector180, Vector184, Vector188, Vector18C
+#endif
+#if CORTEX_NUM_VECTORS > 84
+ .weak Vector190, Vector194, Vector198, Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ .weak Vector1A0, Vector1A4, Vector1A8, Vector1AC
+#endif
+#if CORTEX_NUM_VECTORS > 92
+ .weak Vector1B0, Vector1B4, Vector1B8, Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ .weak Vector1C0, Vector1C4, Vector1C8, Vector1CC
+#endif
+#if CORTEX_NUM_VECTORS > 100
+ .weak Vector1D0, Vector1D4, Vector1D8, Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ .weak Vector1E0, Vector1E4, Vector1E8, Vector1EC
+#endif
+#if CORTEX_NUM_VECTORS > 108
+ .weak Vector1F0, Vector1F4, Vector1F8, Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ .weak Vector200, Vector204, Vector208, Vector20C
+#endif
+#if CORTEX_NUM_VECTORS > 116
+ .weak Vector210, Vector214, Vector218, Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ .weak Vector220, Vector224, Vector228, Vector22C
+#endif
+#if CORTEX_NUM_VECTORS > 124
+ .weak Vector230, Vector234, Vector238, Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ .weak Vector240, Vector244, Vector248, Vector24C
+#endif
+#if CORTEX_NUM_VECTORS > 132
+ .weak Vector250, Vector254, Vector258, Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ .weak Vector260, Vector264, Vector268, Vector26C
+#endif
+#if CORTEX_NUM_VECTORS > 140
+ .weak Vector270, Vector274, Vector278, Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ .weak Vector280, Vector284, Vector288, Vector28C
+#endif
+#if CORTEX_NUM_VECTORS > 148
+ .weak Vector290, Vector294, Vector298, Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ .weak Vector2A0, Vector2A4, Vector2A8, Vector2AC
+#endif
+#if CORTEX_NUM_VECTORS > 156
+ .weak Vector2B0, Vector2B4, Vector2B8, Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ .weak Vector2C0, Vector2C4, Vector2C8, Vector2CC
+#endif
+#if CORTEX_NUM_VECTORS > 164
+ .weak Vector2D0, Vector2D4, Vector2D8, Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ .weak Vector2E0, Vector2E4, Vector2E8, Vector2EC
+#endif
+#if CORTEX_NUM_VECTORS > 172
+ .weak Vector2F0, Vector2F4, Vector2F8, Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ .weak Vector300, Vector304, Vector308, Vector30C
+#endif
+#if CORTEX_NUM_VECTORS > 180
+ .weak Vector310, Vector314, Vector318, Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ .weak Vector320, Vector324, Vector328, Vector32C
+#endif
+#if CORTEX_NUM_VECTORS > 188
+ .weak Vector330, Vector334, Vector338, Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ .weak Vector340, Vector344, Vector348, Vector34C
+#endif
+#if CORTEX_NUM_VECTORS > 196
+ .weak Vector350, Vector354, Vector358, Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ .weak Vector360, Vector364, Vector368, Vector36C
+#endif
+#if CORTEX_NUM_VECTORS > 204
+ .weak Vector370, Vector374, Vector378, Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ .weak Vector380, Vector384, Vector388, Vector38C
+#endif
+#if CORTEX_NUM_VECTORS > 212
+ .weak Vector390, Vector394, Vector398, Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ .weak Vector3A0, Vector3A4, Vector3A8, Vector3AC
+#endif
+#if CORTEX_NUM_VECTORS > 220
+ .weak Vector3B0, Vector3B4, Vector3B8, Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ .weak Vector3C0, Vector3C4, Vector3C8, Vector3CC
+#endif
+#if CORTEX_NUM_VECTORS > 228
+ .weak Vector3D0, Vector3D4, Vector3D8, Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ .weak Vector3E0, Vector3E4, Vector3E8, Vector3EC
+#endif
+#if CORTEX_NUM_VECTORS > 236
+ .weak Vector3F0, Vector3F4, Vector3F8, Vector3FC
+#endif
+
+ .thumb_func
+NMI_Handler:
+ .thumb_func
+HardFault_Handler:
+ .thumb_func
+MemManage_Handler:
+ .thumb_func
+BusFault_Handler:
+ .thumb_func
+UsageFault_Handler:
+ .thumb_func
+Vector1C:
+ .thumb_func
+Vector20:
+ .thumb_func
+Vector24:
+ .thumb_func
+Vector28:
+ .thumb_func
+SVC_Handler:
+ .thumb_func
+DebugMon_Handler:
+ .thumb_func
+Vector34:
+ .thumb_func
+PendSV_Handler:
+ .thumb_func
+SysTick_Handler:
+ .thumb_func
+Vector40:
+ .thumb_func
+Vector44:
+ .thumb_func
+Vector48:
+ .thumb_func
+Vector4C:
+ .thumb_func
+Vector50:
+ .thumb_func
+Vector54:
+ .thumb_func
+Vector58:
+ .thumb_func
+Vector5C:
+#if CORTEX_NUM_VECTORS > 8
+ .thumb_func
+Vector60:
+ .thumb_func
+Vector64:
+ .thumb_func
+Vector68:
+ .thumb_func
+Vector6C:
+ .thumb_func
+Vector70:
+ .thumb_func
+Vector74:
+ .thumb_func
+Vector78:
+ .thumb_func
+Vector7C:
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ .thumb_func
+Vector80:
+ .thumb_func
+Vector84:
+ .thumb_func
+Vector88:
+ .thumb_func
+Vector8C:
+ .thumb_func
+Vector90:
+ .thumb_func
+Vector94:
+ .thumb_func
+Vector98:
+ .thumb_func
+Vector9C:
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ .thumb_func
+VectorA0:
+ .thumb_func
+VectorA4:
+ .thumb_func
+VectorA8:
+ .thumb_func
+VectorAC:
+ .thumb_func
+VectorB0:
+ .thumb_func
+VectorB4:
+ .thumb_func
+VectorB8:
+ .thumb_func
+VectorBC:
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ .thumb_func
+VectorC0:
+ .thumb_func
+VectorC4:
+ .thumb_func
+VectorC8:
+ .thumb_func
+VectorCC:
+ .thumb_func
+VectorD0:
+ .thumb_func
+VectorD4:
+ .thumb_func
+VectorD8:
+ .thumb_func
+VectorDC:
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ .thumb_func
+VectorE0:
+ .thumb_func
+VectorE4:
+ .thumb_func
+VectorE8:
+ .thumb_func
+VectorEC:
+ .thumb_func
+VectorF0:
+ .thumb_func
+VectorF4:
+ .thumb_func
+VectorF8:
+ .thumb_func
+VectorFC:
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ .thumb_func
+Vector100:
+ .thumb_func
+Vector104:
+ .thumb_func
+Vector108:
+ .thumb_func
+Vector10C:
+ .thumb_func
+Vector110:
+ .thumb_func
+Vector114:
+ .thumb_func
+Vector118:
+ .thumb_func
+Vector11C:
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ .thumb_func
+Vector120:
+ .thumb_func
+Vector124:
+ .thumb_func
+Vector128:
+ .thumb_func
+Vector12C:
+ .thumb_func
+Vector130:
+ .thumb_func
+Vector134:
+ .thumb_func
+Vector138:
+ .thumb_func
+Vector13C:
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ .thumb_func
+Vector140:
+ .thumb_func
+Vector144:
+ .thumb_func
+Vector148:
+ .thumb_func
+Vector14C:
+ .thumb_func
+Vector150:
+ .thumb_func
+Vector154:
+ .thumb_func
+Vector158:
+ .thumb_func
+Vector15C:
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ .thumb_func
+Vector160:
+ .thumb_func
+Vector164:
+ .thumb_func
+Vector168:
+ .thumb_func
+Vector16C:
+ .thumb_func
+Vector170:
+ .thumb_func
+Vector174:
+ .thumb_func
+Vector178:
+ .thumb_func
+Vector17C:
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ .thumb_func
+Vector180:
+ .thumb_func
+Vector184:
+ .thumb_func
+Vector188:
+ .thumb_func
+Vector18C:
+ .thumb_func
+Vector190:
+ .thumb_func
+Vector194:
+ .thumb_func
+Vector198:
+ .thumb_func
+Vector19C:
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ .thumb_func
+Vector1A0:
+ .thumb_func
+Vector1A4:
+ .thumb_func
+Vector1A8:
+ .thumb_func
+Vector1AC:
+ .thumb_func
+Vector1B0:
+ .thumb_func
+Vector1B4:
+ .thumb_func
+Vector1B8:
+ .thumb_func
+Vector1BC:
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ .thumb_func
+Vector1C0:
+ .thumb_func
+Vector1C4:
+ .thumb_func
+Vector1C8:
+ .thumb_func
+Vector1CC:
+ .thumb_func
+Vector1D0:
+ .thumb_func
+Vector1D4:
+ .thumb_func
+Vector1D8:
+ .thumb_func
+Vector1DC:
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ .thumb_func
+Vector1E0:
+ .thumb_func
+Vector1E4:
+ .thumb_func
+Vector1E8:
+ .thumb_func
+Vector1EC:
+ .thumb_func
+Vector1F0:
+ .thumb_func
+Vector1F4:
+ .thumb_func
+Vector1F8:
+ .thumb_func
+Vector1FC:
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ .thumb_func
+Vector200:
+ .thumb_func
+Vector204:
+ .thumb_func
+Vector208:
+ .thumb_func
+Vector20C:
+ .thumb_func
+Vector210:
+ .thumb_func
+Vector214:
+ .thumb_func
+Vector218:
+ .thumb_func
+Vector21C:
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ .thumb_func
+Vector220:
+ .thumb_func
+Vector224:
+ .thumb_func
+Vector228:
+ .thumb_func
+Vector22C:
+ .thumb_func
+Vector230:
+ .thumb_func
+Vector234:
+ .thumb_func
+Vector238:
+ .thumb_func
+Vector23C:
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ .thumb_func
+Vector240:
+ .thumb_func
+Vector244:
+ .thumb_func
+Vector248:
+ .thumb_func
+Vector24C:
+ .thumb_func
+Vector250:
+ .thumb_func
+Vector254:
+ .thumb_func
+Vector258:
+ .thumb_func
+Vector25C:
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ .thumb_func
+Vector260:
+ .thumb_func
+Vector264:
+ .thumb_func
+Vector268:
+ .thumb_func
+Vector26C:
+ .thumb_func
+Vector270:
+ .thumb_func
+Vector274:
+ .thumb_func
+Vector278:
+ .thumb_func
+Vector27C:
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ .thumb_func
+Vector280:
+ .thumb_func
+Vector284:
+ .thumb_func
+Vector288:
+ .thumb_func
+Vector28C:
+ .thumb_func
+Vector290:
+ .thumb_func
+Vector294:
+ .thumb_func
+Vector298:
+ .thumb_func
+Vector29C:
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ .thumb_func
+Vector2A0:
+ .thumb_func
+Vector2A4:
+ .thumb_func
+Vector2A8:
+ .thumb_func
+Vector2AC:
+ .thumb_func
+Vector2B0:
+ .thumb_func
+Vector2B4:
+ .thumb_func
+Vector2B8:
+ .thumb_func
+Vector2BC:
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ .thumb_func
+Vector2C0:
+ .thumb_func
+Vector2C4:
+ .thumb_func
+Vector2C8:
+ .thumb_func
+Vector2CC:
+ .thumb_func
+Vector2D0:
+ .thumb_func
+Vector2D4:
+ .thumb_func
+Vector2D8:
+ .thumb_func
+Vector2DC:
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ .thumb_func
+Vector2E0:
+ .thumb_func
+Vector2E4:
+ .thumb_func
+Vector2E8:
+ .thumb_func
+Vector2EC:
+ .thumb_func
+Vector2F0:
+ .thumb_func
+Vector2F4:
+ .thumb_func
+Vector2F8:
+ .thumb_func
+Vector2FC:
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ .thumb_func
+Vector300:
+ .thumb_func
+Vector304:
+ .thumb_func
+Vector308:
+ .thumb_func
+Vector30C:
+ .thumb_func
+Vector310:
+ .thumb_func
+Vector314:
+ .thumb_func
+Vector318:
+ .thumb_func
+Vector31C:
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ .thumb_func
+Vector320:
+ .thumb_func
+Vector324:
+ .thumb_func
+Vector328:
+ .thumb_func
+Vector32C:
+ .thumb_func
+Vector330:
+ .thumb_func
+Vector334:
+ .thumb_func
+Vector338:
+ .thumb_func
+Vector33C:
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ .thumb_func
+Vector340:
+ .thumb_func
+Vector344:
+ .thumb_func
+Vector348:
+ .thumb_func
+Vector34C:
+ .thumb_func
+Vector350:
+ .thumb_func
+Vector354:
+ .thumb_func
+Vector358:
+ .thumb_func
+Vector35C:
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ .thumb_func
+Vector360:
+ .thumb_func
+Vector364:
+ .thumb_func
+Vector368:
+ .thumb_func
+Vector36C:
+ .thumb_func
+Vector370:
+ .thumb_func
+Vector374:
+ .thumb_func
+Vector378:
+ .thumb_func
+Vector37C:
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ .thumb_func
+Vector380:
+ .thumb_func
+Vector384:
+ .thumb_func
+Vector388:
+ .thumb_func
+Vector38C:
+ .thumb_func
+Vector390:
+ .thumb_func
+Vector394:
+ .thumb_func
+Vector398:
+ .thumb_func
+Vector39C:
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ .thumb_func
+Vector3A0:
+ .thumb_func
+Vector3A4:
+ .thumb_func
+Vector3A8:
+ .thumb_func
+Vector3AC:
+ .thumb_func
+Vector3B0:
+ .thumb_func
+Vector3B4:
+ .thumb_func
+Vector3B8:
+ .thumb_func
+Vector3BC:
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ .thumb_func
+Vector3C0:
+ .thumb_func
+Vector3C4:
+ .thumb_func
+Vector3C8:
+ .thumb_func
+Vector3CC:
+ .thumb_func
+Vector3D0:
+ .thumb_func
+Vector3D4:
+ .thumb_func
+Vector3D8:
+ .thumb_func
+Vector3DC:
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ .thumb_func
+Vector3E0:
+ .thumb_func
+Vector3E4:
+ .thumb_func
+Vector3E8:
+ .thumb_func
+Vector3EC:
+ .thumb_func
+Vector3F0:
+ .thumb_func
+Vector3F4:
+ .thumb_func
+Vector3F8:
+ .thumb_func
+Vector3FC:
+#endif
+ bl _unhandled_exception
+
+ .thumb_func
+ .weak _unhandled_exception
+_unhandled_exception:
+.stay:
+ b .stay
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/IAR/cstartup.s b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/IAR/cstartup.s new file mode 100644 index 0000000..bf7aeca --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/IAR/cstartup.s @@ -0,0 +1,169 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/compilers/IAR/cstartup.s
+ * @brief Generic IAR Cortex-Mx startup file.
+ *
+ * @addtogroup ARMCMx_IAR_STARTUP
+ * @{
+ */
+
+#if !defined(__DOXYGEN__)
+
+#define SCB_VTOR 0xE000ED08
+
+ /**
+ * @brief VTOR special register initialization.
+ * @details VTOR is initialized to point to the vectors table.
+ * @note IAR assembler #if directive conditions do not work like C/C++ conditions.
+ * @details Set to 0 to disable the function, 1 to enable
+ */
+#ifndef CRT0_VTOR_INIT
+#define CRT0_VTOR_INIT 1
+#endif
+/**
+ * @brief Stack segments initialization value.
+ */
+#ifndef CRT0_STACKS_FILL_PATTERN
+#define CRT0_STACKS_FILL_PATTERN 0x55555555
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ * @details Set to 0 to disable the function, 1 to enable
+ */
+#ifndef CRT0_INIT_STACKS
+#define CRT0_INIT_STACKS 1
+#endif
+
+/**
+ * @brief Heap segment initialization value.
+ */
+#ifndef CRT0_HEAP_FILL_PATTERN
+#define CRT0_HEAP_FILL_PATTERN 0xCCCCCCCC
+#endif
+
+/**
+ * @brief Heap segment initialization switch.
+ * @details Set to 0 to disable the function, 1 to enable
+ */
+#ifndef CRT0_INIT_HEAP
+#define CRT0_INIT_HEAP 1
+#endif
+
+
+ MODULE ?cstartup
+
+CONTROL_MODE_PRIVILEGED SET 0
+CONTROL_MODE_UNPRIVILEGED SET 1
+CONTROL_USE_MSP SET 0
+CONTROL_USE_PSP SET 2
+
+ AAPCS INTERWORK, VFP_COMPATIBLE, ROPI
+ PRESERVE8
+
+ SECTION HEAP:DATA:NOROOT(3)
+ PUBLIC __heap_base__
+__heap_base__: /* Note: heap section defines sysheap base */
+
+ SECTION SYSHEAP:DATA:NOROOT(3)
+ PUBLIC __heap_end__
+__heap_end__: /* Note: sysheap section defines sysheap end */
+
+ PUBLIC __iar_program_start
+ EXTWEAK __iar_init_core
+ EXTWEAK __iar_init_vfp
+ EXTERN __cmain
+ EXTERN __vector_table
+ EXTERN __main_stack_base__
+ EXTERN __main_stack_end__
+ EXTERN __process_stack_base__
+ EXTERN __process_stack_end__
+
+ SECTION IRQSTACK:DATA:NOROOT(3)
+ SECTION CSTACK:DATA:NOROOT(3)
+ SECTION .text:CODE:REORDER(2)
+ THUMB
+
+__iar_program_start:
+ cpsid i
+ ldr r0, =SFE(IRQSTACK)
+ msr MSP, r0
+ ldr r0, =SFE(CSTACK)
+ msr PSP, r0
+ movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP
+ msr CONTROL, r0
+ isb
+
+#if (CRT0_VTOR_INIT)
+ ldr r0, =__vector_table
+ movw r1, #SCB_VTOR & 0xFFFF
+ movt r1, #SCB_VTOR >> 16
+ str r0, [r1]
+#endif
+
+#if (CRT0_INIT_STACKS)
+ ldr r0, =CRT0_STACKS_FILL_PATTERN
+ /* Main Stack initialization. Note, it assumes that the stack size
+ is a multiple of 4 so the linker file must ensure this.*/
+ ldr r1, =__main_stack_base__
+ ldr r2, =__main_stack_end__
+msloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo msloop
+
+ /* Process Stack initialization. Note, it assumes that the stack size
+ is a multiple of 4 so the linker file must ensure this.*/
+ ldr r1, =__process_stack_base__
+ ldr r2, =__process_stack_end__
+psloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo psloop
+#endif
+
+#if (CRT0_INIT_HEAP)
+ ldr r0, =CRT0_HEAP_FILL_PATTERN
+ /* Sys Heap initialization. Note, it assumes that the heap size
+ is a multiple of 4 so the linker file must ensure this.*/
+ ldr r1, =__heap_base__
+ ldr r2, =__heap_end__
+hloop:
+ cmp r1, r2
+ itt lo
+ strlo r0, [r1], #4
+ blo hloop
+#endif
+
+ bl __early_init
+ bl __iar_init_core
+ bl __iar_init_vfp
+ b __cmain
+
+ SECTION .text:CODE:NOROOT:REORDER(2)
+ PUBWEAK __early_init
+__early_init:
+ bx lr
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/IAR/vectors.s b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/IAR/vectors.s new file mode 100644 index 0000000..ec0360e --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/IAR/vectors.s @@ -0,0 +1,1006 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/compilers/IAR/vectors.c
+ * @brief Interrupt vectors for Cortex-Mx devices.
+ *
+ * @defgroup ARMCMx_IAR_VECTORS Cortex-Mx Interrupt Vectors
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "cmparams.h"
+
+#if !defined(__DOXYGEN__)
+
+#if (CORTEX_NUM_VECTORS & 7) != 0
+#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8"
+#endif
+
+#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240)
+#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive"
+#endif
+
+ MODULE ?vectors
+
+ AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
+ PRESERVE8
+
+ SECTION IRQSTACK:DATA:NOROOT(3)
+ SECTION .intvec:CODE:NOROOT(3)
+
+ EXTERN __iar_program_start
+ PUBLIC __vector_table
+
+ DATA
+
+__vector_table:
+ DCD SFE(IRQSTACK)
+ DCD __iar_program_start
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+ DCD Vector1C
+ DCD Vector20
+ DCD Vector24
+ DCD Vector28
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD Vector34
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+ DCD Vector40
+ DCD Vector44
+ DCD Vector48
+ DCD Vector4C
+ DCD Vector50
+ DCD Vector54
+ DCD Vector58
+ DCD Vector5C
+#if CORTEX_NUM_VECTORS > 8
+ DCD Vector60
+ DCD Vector64
+ DCD Vector68
+ DCD Vector6C
+ DCD Vector70
+ DCD Vector74
+ DCD Vector78
+ DCD Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ DCD Vector80
+ DCD Vector84
+ DCD Vector88
+ DCD Vector8C
+ DCD Vector90
+ DCD Vector94
+ DCD Vector98
+ DCD Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ DCD VectorA0
+ DCD VectorA4
+ DCD VectorA8
+ DCD VectorAC
+ DCD VectorB0
+ DCD VectorB4
+ DCD VectorB8
+ DCD VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ DCD VectorC0
+ DCD VectorC4
+ DCD VectorC8
+ DCD VectorCC
+ DCD VectorD0
+ DCD VectorD4
+ DCD VectorD8
+ DCD VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ DCD VectorE0
+ DCD VectorE4
+ DCD VectorE8
+ DCD VectorEC
+ DCD VectorF0
+ DCD VectorF4
+ DCD VectorF8
+ DCD VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ DCD Vector100
+ DCD Vector104
+ DCD Vector108
+ DCD Vector10C
+ DCD Vector110
+ DCD Vector114
+ DCD Vector118
+ DCD Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ DCD Vector120
+ DCD Vector124
+ DCD Vector128
+ DCD Vector12C
+ DCD Vector130
+ DCD Vector134
+ DCD Vector138
+ DCD Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ DCD Vector140
+ DCD Vector144
+ DCD Vector148
+ DCD Vector14C
+ DCD Vector150
+ DCD Vector154
+ DCD Vector158
+ DCD Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ DCD Vector160
+ DCD Vector164
+ DCD Vector168
+ DCD Vector16C
+ DCD Vector170
+ DCD Vector174
+ DCD Vector178
+ DCD Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ DCD Vector180
+ DCD Vector184
+ DCD Vector188
+ DCD Vector18C
+ DCD Vector190
+ DCD Vector194
+ DCD Vector198
+ DCD Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ DCD Vector1A0
+ DCD Vector1A4
+ DCD Vector1A8
+ DCD Vector1AC
+ DCD Vector1B0
+ DCD Vector1B4
+ DCD Vector1B8
+ DCD Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ DCD Vector1C0
+ DCD Vector1C4
+ DCD Vector1C8
+ DCD Vector1CC
+ DCD Vector1D0
+ DCD Vector1D4
+ DCD Vector1D8
+ DCD Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ DCD Vector1E0
+ DCD Vector1E4
+ DCD Vector1E8
+ DCD Vector1EC
+ DCD Vector1F0
+ DCD Vector1F4
+ DCD Vector1F8
+ DCD Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ DCD Vector200
+ DCD Vector204
+ DCD Vector208
+ DCD Vector20C
+ DCD Vector210
+ DCD Vector214
+ DCD Vector218
+ DCD Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ DCD Vector220
+ DCD Vector224
+ DCD Vector228
+ DCD Vector22C
+ DCD Vector230
+ DCD Vector234
+ DCD Vector238
+ DCD Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ DCD Vector240
+ DCD Vector244
+ DCD Vector248
+ DCD Vector24C
+ DCD Vector250
+ DCD Vector254
+ DCD Vector258
+ DCD Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ DCD Vector260
+ DCD Vector264
+ DCD Vector268
+ DCD Vector26C
+ DCD Vector270
+ DCD Vector274
+ DCD Vector278
+ DCD Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ DCD Vector280
+ DCD Vector284
+ DCD Vector288
+ DCD Vector28C
+ DCD Vector290
+ DCD Vector294
+ DCD Vector298
+ DCD Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ DCD Vector2A0
+ DCD Vector2A4
+ DCD Vector2A8
+ DCD Vector2AC
+ DCD Vector2B0
+ DCD Vector2B4
+ DCD Vector2B8
+ DCD Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ DCD Vector2C0
+ DCD Vector2C4
+ DCD Vector2C8
+ DCD Vector2CC
+ DCD Vector2D0
+ DCD Vector2D4
+ DCD Vector2D8
+ DCD Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ DCD Vector2E0
+ DCD Vector2E4
+ DCD Vector2E8
+ DCD Vector2EC
+ DCD Vector2F0
+ DCD Vector2F4
+ DCD Vector2F8
+ DCD Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ DCD Vector300
+ DCD Vector304
+ DCD Vector308
+ DCD Vector30C
+ DCD Vector310
+ DCD Vector314
+ DCD Vector318
+ DCD Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ DCD Vector320
+ DCD Vector324
+ DCD Vector328
+ DCD Vector32C
+ DCD Vector330
+ DCD Vector334
+ DCD Vector338
+ DCD Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ DCD Vector340
+ DCD Vector344
+ DCD Vector348
+ DCD Vector34C
+ DCD Vector350
+ DCD Vector354
+ DCD Vector358
+ DCD Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ DCD Vector360
+ DCD Vector364
+ DCD Vector368
+ DCD Vector36C
+ DCD Vector370
+ DCD Vector374
+ DCD Vector378
+ DCD Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ DCD Vector380
+ DCD Vector384
+ DCD Vector388
+ DCD Vector38C
+ DCD Vector390
+ DCD Vector394
+ DCD Vector398
+ DCD Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ DCD Vector3A0
+ DCD Vector3A4
+ DCD Vector3A8
+ DCD Vector3AC
+ DCD Vector3B0
+ DCD Vector3B4
+ DCD Vector3B8
+ DCD Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ DCD Vector3C0
+ DCD Vector3C4
+ DCD Vector3C8
+ DCD Vector3CC
+ DCD Vector3D0
+ DCD Vector3D4
+ DCD Vector3D8
+ DCD Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ DCD Vector3E0
+ DCD Vector3E4
+ DCD Vector3E8
+ DCD Vector3EC
+ DCD Vector3F0
+ DCD Vector3F4
+ DCD Vector3F8
+ DCD Vector3FC
+#endif
+
+/*
+ * Default interrupt handlers.
+ */
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK Vector1C
+ PUBWEAK Vector20
+ PUBWEAK Vector24
+ PUBWEAK Vector28
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK Vector34
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK Vector40
+ PUBWEAK Vector44
+ PUBWEAK Vector48
+ PUBWEAK Vector4C
+ PUBWEAK Vector50
+ PUBWEAK Vector54
+ PUBWEAK Vector58
+ PUBWEAK Vector5C
+#if CORTEX_NUM_VECTORS > 8
+ PUBWEAK Vector60
+ PUBWEAK Vector64
+ PUBWEAK Vector68
+ PUBWEAK Vector6C
+ PUBWEAK Vector70
+ PUBWEAK Vector74
+ PUBWEAK Vector78
+ PUBWEAK Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ PUBWEAK Vector80
+ PUBWEAK Vector84
+ PUBWEAK Vector88
+ PUBWEAK Vector8C
+ PUBWEAK Vector90
+ PUBWEAK Vector94
+ PUBWEAK Vector98
+ PUBWEAK Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ PUBWEAK VectorA0
+ PUBWEAK VectorA4
+ PUBWEAK VectorA8
+ PUBWEAK VectorAC
+ PUBWEAK VectorB0
+ PUBWEAK VectorB4
+ PUBWEAK VectorB8
+ PUBWEAK VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ PUBWEAK VectorC0
+ PUBWEAK VectorC4
+ PUBWEAK VectorC8
+ PUBWEAK VectorCC
+ PUBWEAK VectorD0
+ PUBWEAK VectorD4
+ PUBWEAK VectorD8
+ PUBWEAK VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ PUBWEAK VectorE0
+ PUBWEAK VectorE4
+ PUBWEAK VectorE8
+ PUBWEAK VectorEC
+ PUBWEAK VectorF0
+ PUBWEAK VectorF4
+ PUBWEAK VectorF8
+ PUBWEAK VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ PUBWEAK Vector100
+ PUBWEAK Vector104
+ PUBWEAK Vector108
+ PUBWEAK Vector10C
+ PUBWEAK Vector110
+ PUBWEAK Vector114
+ PUBWEAK Vector118
+ PUBWEAK Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ PUBWEAK Vector120
+ PUBWEAK Vector124
+ PUBWEAK Vector128
+ PUBWEAK Vector12C
+ PUBWEAK Vector130
+ PUBWEAK Vector134
+ PUBWEAK Vector138
+ PUBWEAK Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ PUBWEAK Vector140
+ PUBWEAK Vector144
+ PUBWEAK Vector148
+ PUBWEAK Vector14C
+ PUBWEAK Vector150
+ PUBWEAK Vector154
+ PUBWEAK Vector158
+ PUBWEAK Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ PUBWEAK Vector160
+ PUBWEAK Vector164
+ PUBWEAK Vector168
+ PUBWEAK Vector16C
+ PUBWEAK Vector170
+ PUBWEAK Vector174
+ PUBWEAK Vector178
+ PUBWEAK Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ PUBWEAK Vector180
+ PUBWEAK Vector184
+ PUBWEAK Vector188
+ PUBWEAK Vector18C
+ PUBWEAK Vector190
+ PUBWEAK Vector194
+ PUBWEAK Vector198
+ PUBWEAK Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ PUBWEAK Vector1A0
+ PUBWEAK Vector1A4
+ PUBWEAK Vector1A8
+ PUBWEAK Vector1AC
+ PUBWEAK Vector1B0
+ PUBWEAK Vector1B4
+ PUBWEAK Vector1B8
+ PUBWEAK Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ PUBWEAK Vector1C0
+ PUBWEAK Vector1C4
+ PUBWEAK Vector1C8
+ PUBWEAK Vector1CC
+ PUBWEAK Vector1D0
+ PUBWEAK Vector1D4
+ PUBWEAK Vector1D8
+ PUBWEAK Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ PUBWEAK Vector1E0
+ PUBWEAK Vector1E4
+ PUBWEAK Vector1E8
+ PUBWEAK Vector1EC
+ PUBWEAK Vector1F0
+ PUBWEAK Vector1F4
+ PUBWEAK Vector1F8
+ PUBWEAK Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ PUBWEAK Vector200
+ PUBWEAK Vector204
+ PUBWEAK Vector208
+ PUBWEAK Vector20C
+ PUBWEAK Vector210
+ PUBWEAK Vector214
+ PUBWEAK Vector218
+ PUBWEAK Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ PUBWEAK Vector220
+ PUBWEAK Vector224
+ PUBWEAK Vector228
+ PUBWEAK Vector22C
+ PUBWEAK Vector230
+ PUBWEAK Vector234
+ PUBWEAK Vector238
+ PUBWEAK Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ PUBWEAK Vector240
+ PUBWEAK Vector244
+ PUBWEAK Vector248
+ PUBWEAK Vector24C
+ PUBWEAK Vector250
+ PUBWEAK Vector254
+ PUBWEAK Vector258
+ PUBWEAK Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ PUBWEAK Vector260
+ PUBWEAK Vector264
+ PUBWEAK Vector268
+ PUBWEAK Vector26C
+ PUBWEAK Vector270
+ PUBWEAK Vector274
+ PUBWEAK Vector278
+ PUBWEAK Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ PUBWEAK Vector280
+ PUBWEAK Vector284
+ PUBWEAK Vector288
+ PUBWEAK Vector28C
+ PUBWEAK Vector290
+ PUBWEAK Vector294
+ PUBWEAK Vector298
+ PUBWEAK Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ PUBWEAK Vector2A0
+ PUBWEAK Vector2A4
+ PUBWEAK Vector2A8
+ PUBWEAK Vector2AC
+ PUBWEAK Vector2B0
+ PUBWEAK Vector2B4
+ PUBWEAK Vector2B8
+ PUBWEAK Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ PUBWEAK Vector2C0
+ PUBWEAK Vector2C4
+ PUBWEAK Vector2C8
+ PUBWEAK Vector2CC
+ PUBWEAK Vector2D0
+ PUBWEAK Vector2D4
+ PUBWEAK Vector2D8
+ PUBWEAK Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ PUBWEAK Vector2E0
+ PUBWEAK Vector2E4
+ PUBWEAK Vector2E8
+ PUBWEAK Vector2EC
+ PUBWEAK Vector2F0
+ PUBWEAK Vector2F4
+ PUBWEAK Vector2F8
+ PUBWEAK Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ PUBWEAK Vector300
+ PUBWEAK Vector304
+ PUBWEAK Vector308
+ PUBWEAK Vector30C
+ PUBWEAK Vector310
+ PUBWEAK Vector314
+ PUBWEAK Vector318
+ PUBWEAK Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ PUBWEAK Vector320
+ PUBWEAK Vector324
+ PUBWEAK Vector328
+ PUBWEAK Vector32C
+ PUBWEAK Vector330
+ PUBWEAK Vector334
+ PUBWEAK Vector338
+ PUBWEAK Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ PUBWEAK Vector340
+ PUBWEAK Vector344
+ PUBWEAK Vector348
+ PUBWEAK Vector34C
+ PUBWEAK Vector350
+ PUBWEAK Vector354
+ PUBWEAK Vector358
+ PUBWEAK Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ PUBWEAK Vector360
+ PUBWEAK Vector364
+ PUBWEAK Vector368
+ PUBWEAK Vector36C
+ PUBWEAK Vector370
+ PUBWEAK Vector374
+ PUBWEAK Vector378
+ PUBWEAK Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ PUBWEAK Vector380
+ PUBWEAK Vector384
+ PUBWEAK Vector388
+ PUBWEAK Vector38C
+ PUBWEAK Vector390
+ PUBWEAK Vector394
+ PUBWEAK Vector398
+ PUBWEAK Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ PUBWEAK Vector3A0
+ PUBWEAK Vector3A4
+ PUBWEAK Vector3A8
+ PUBWEAK Vector3AC
+ PUBWEAK Vector3B0
+ PUBWEAK Vector3B4
+ PUBWEAK Vector3B8
+ PUBWEAK Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ PUBWEAK Vector3C0
+ PUBWEAK Vector3C4
+ PUBWEAK Vector3C8
+ PUBWEAK Vector3CC
+ PUBWEAK Vector3D0
+ PUBWEAK Vector3D4
+ PUBWEAK Vector3D8
+ PUBWEAK Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ PUBWEAK Vector3E0
+ PUBWEAK Vector3E4
+ PUBWEAK Vector3E8
+ PUBWEAK Vector3EC
+ PUBWEAK Vector3F0
+ PUBWEAK Vector3F4
+ PUBWEAK Vector3F8
+ PUBWEAK Vector3FC
+#endif
+ PUBLIC _unhandled_exception
+
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ THUMB
+
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+Vector1C
+Vector20
+Vector24
+Vector28
+SVC_Handler
+DebugMon_Handler
+Vector34
+PendSV_Handler
+SysTick_Handler
+Vector40
+Vector44
+Vector48
+Vector4C
+Vector50
+Vector54
+Vector58
+Vector5C
+#if CORTEX_NUM_VECTORS > 8
+Vector60
+Vector64
+Vector68
+Vector6C
+Vector70
+Vector74
+Vector78
+Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+Vector80
+Vector84
+Vector88
+Vector8C
+Vector90
+Vector94
+Vector98
+Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+VectorA0
+VectorA4
+VectorA8
+VectorAC
+VectorB0
+VectorB4
+VectorB8
+VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+VectorC0
+VectorC4
+VectorC8
+VectorCC
+VectorD0
+VectorD4
+VectorD8
+VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+VectorE0
+VectorE4
+VectorE8
+VectorEC
+VectorF0
+VectorF4
+VectorF8
+VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+Vector100
+Vector104
+Vector108
+Vector10C
+Vector110
+Vector114
+Vector118
+Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+Vector120
+Vector124
+Vector128
+Vector12C
+Vector130
+Vector134
+Vector138
+Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+Vector140
+Vector144
+Vector148
+Vector14C
+Vector150
+Vector154
+Vector158
+Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+Vector160
+Vector164
+Vector168
+Vector16C
+Vector170
+Vector174
+Vector178
+Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+Vector180
+Vector184
+Vector188
+Vector18C
+Vector190
+Vector194
+Vector198
+Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+Vector1A0
+Vector1A4
+Vector1A8
+Vector1AC
+Vector1B0
+Vector1B4
+Vector1B8
+Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+Vector1C0
+Vector1C4
+Vector1C8
+Vector1CC
+Vector1D0
+Vector1D4
+Vector1D8
+Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+Vector1E0
+Vector1E4
+Vector1E8
+Vector1EC
+Vector1F0
+Vector1F4
+Vector1F8
+Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+Vector200
+Vector204
+Vector208
+Vector20C
+Vector210
+Vector214
+Vector218
+Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+Vector220
+Vector224
+Vector228
+Vector22C
+Vector230
+Vector234
+Vector238
+Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+Vector240
+Vector244
+Vector248
+Vector24C
+Vector250
+Vector254
+Vector258
+Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+Vector260
+Vector264
+Vector268
+Vector26C
+Vector270
+Vector274
+Vector278
+Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+Vector280
+Vector284
+Vector288
+Vector28C
+Vector290
+Vector294
+Vector298
+Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+Vector2A0
+Vector2A4
+Vector2A8
+Vector2AC
+Vector2B0
+Vector2B4
+Vector2B8
+Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+Vector2C0
+Vector2C4
+Vector2C8
+Vector2CC
+Vector2D0
+Vector2D4
+Vector2D8
+Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+Vector2E0
+Vector2E4
+Vector2E8
+Vector2EC
+Vector2F0
+Vector2F4
+Vector2F8
+Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+Vector300
+Vector304
+Vector308
+Vector30C
+Vector310
+Vector314
+Vector318
+Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+Vector320
+Vector324
+Vector328
+Vector32C
+Vector330
+Vector334
+Vector338
+Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+Vector340
+Vector344
+Vector348
+Vector34C
+Vector350
+Vector354
+Vector358
+Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+Vector360
+Vector364
+Vector368
+Vector36C
+Vector370
+Vector374
+Vector378
+Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+Vector380
+Vector384
+Vector388
+Vector38C
+Vector390
+Vector394
+Vector398
+Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+Vector3A0
+Vector3A4
+Vector3A8
+Vector3AC
+Vector3B0
+Vector3B4
+Vector3B8
+Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+Vector3C0
+Vector3C4
+Vector3C8
+Vector3CC
+Vector3D0
+Vector3D4
+Vector3D8
+Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+Vector3E0
+Vector3E4
+Vector3E8
+Vector3EC
+Vector3F0
+Vector3F4
+Vector3F8
+Vector3FC
+#endif
+_unhandled_exception
+ b _unhandled_exception
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/LLVM/mk/clang.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/LLVM/mk/clang.mk new file mode 100644 index 0000000..db0f1e4 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/LLVM/mk/clang.mk @@ -0,0 +1,19 @@ +##############################################################################
+# Compiler settings
+#
+
+TRGT = aarch32-
+CC = clang
+CPPC = clang++
+LD = clang
+CP = $(TRGT)objcopy
+AS = $(TRGT)as -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+#
+# Compiler settings
+##############################################################################
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/LLVM/mk/rules.mk b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/LLVM/mk/rules.mk new file mode 100644 index 0000000..0d6af76 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/LLVM/mk/rules.mk @@ -0,0 +1,284 @@ +# ARM Cortex-Mx common makefile scripts and rules.
+
+##############################################################################
+# Processing options coming from the upper Makefile.
+#
+
+# Compiler options
+OPT := $(USE_OPT)
+COPT := $(USE_COPT)
+CPPOPT := $(USE_CPPOPT)
+
+# Garbage collection
+ifeq ($(USE_LINK_GC),yes)
+ OPT += -ffunction-sections -fdata-sections -fno-common
+ LDOPT := ,--gc-sections
+else
+ LDOPT :=
+endif
+
+# Linker extra options
+ifneq ($(USE_LDOPT),)
+ LDOPT := $(LDOPT),$(USE_LDOPT)
+endif
+
+# Link time optimizations
+ifeq ($(USE_LTO),yes)
+ OPT += -flto
+endif
+
+# FPU options default (Cortex-M4 and Cortex-M7 single precision).
+ifeq ($(USE_FPU_OPT),)
+ USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16
+endif
+
+# FPU-related options
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+ifneq ($(USE_FPU),no)
+ OPT += $(USE_FPU_OPT)
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+ DADEFS += -DCORTEX_USE_FPU=TRUE
+else
+ OPT += -mfloat-abi=soft
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+ DADEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
+# Process stack size
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE)
+endif
+
+# Exceptions stack size
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__main_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__main_stack_size__=$(USE_EXCEPTIONS_STACKSIZE)
+endif
+
+# Output directory and files
+ifeq ($(BUILDDIR),)
+ BUILDDIR = build
+endif
+ifeq ($(BUILDDIR),.)
+ BUILDDIR = build
+endif
+
+# Dependencies directory
+ifeq ($(DEPDIR),)
+ DEPDIR = .dep
+endif
+ifeq ($(DEPDIR),.)
+ DEPDIR = .dep
+endif
+
+OUTFILES := $(BUILDDIR)/$(PROJECT).elf \
+ $(BUILDDIR)/$(PROJECT).hex \
+ $(BUILDDIR)/$(PROJECT).bin \
+ $(BUILDDIR)/$(PROJECT).dmp \
+ $(BUILDDIR)/$(PROJECT).list + +ifdef SREC + OUTFILES += $(BUILDDIR)/$(PROJECT).srec +endif + +# Source files groups and paths +TCSRC += $(CSRC)
+TCPPSRC += $(CPPSRC)
+TSRC := $(TCSRC) $(TCPPSRC)
+SRCPATHS := $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(TSRC)))
+
+# Various directories
+OBJDIR := $(BUILDDIR)/obj
+LSTDIR := $(BUILDDIR)/lst
+
+# Object files groups
+TCOBJS := $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
+TCPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
+ASMOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
+ASMXOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+OBJS := $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
+
+# Paths
+IINCDIR := $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
+LLIBDIR := $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+
+# Macros
+DEFS := $(DDEFS) $(UDEFS)
+ADEFS := $(DADEFS) $(UADEFS)
+
+# Libs
+LIBS := $(DLIBS) $(ULIBS)
+
+# Various settings
+MCFLAGS := -mcpu=$(MCU) -mthumb
+ODFLAGS = -x --syms
+ASFLAGS = $(MCFLAGS) $(OPT) $(ADEFS)
+ASXFLAGS = $(MCFLAGS) $(OPT) $(ADEFS)
+CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) $(DEFS)
+CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) $(DEFS)
+#ASFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+#ASXFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
+#CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
+#CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
+LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(STARTUPLD),--script=$(LDSCRIPT)$(LDOPT)
+
+# Generate dependency information
+ASFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+ASXFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+CFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+CPPFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+
+# Paths where to search for sources
+VPATH = $(SRCPATHS)
+
+#
+# Makefile rules
+#
+
+all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK
+
+PRE_MAKE_ALL_RULE_HOOK:
+
+POST_MAKE_ALL_RULE_HOOK:
+
+$(OBJS): | PRE_MAKE_ALL_RULE_HOOK $(BUILDDIR) $(OBJDIR) $(LSTDIR) $(DEPDIR)
+
+$(BUILDDIR):
+ifneq ($(USE_VERBOSE_COMPILE),yes)
+ @echo Compiler Options
+ @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
+ @echo
+endif
+ @mkdir -p $(BUILDDIR)
+
+$(OBJDIR):
+ @mkdir -p $(OBJDIR)
+
+$(LSTDIR):
+ @mkdir -p $(LSTDIR)
+
+$(DEPDIR):
+ @mkdir -p $(DEPDIR)
+
+$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCOBJS) : $(OBJDIR)/%.o : %.c $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMOBJS) : $(OBJDIR)/%.o : %.s $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +endif + +$(BUILDDIR)/$(PROJECT).elf: $(OBJS) $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ +else
+ @echo Linking $@
+ @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ +endif + +%.hex: %.elf +ifeq ($(USE_VERBOSE_COMPILE),yes) + $(HEX) $< $@ +else + @echo Creating $@
+ @$(HEX) $< $@ +endif + +%.bin: %.elf +ifeq ($(USE_VERBOSE_COMPILE),yes) + $(BIN) $< $@ +else + @echo Creating $@
+ @$(BIN) $< $@ +endif + +%.srec: %.elf
+ifdef SREC
+ ifeq ($(USE_VERBOSE_COMPILE),yes) + $(SREC) $< $@
+ else
+ @echo Creating $@
+ @$(SREC) $< $@
+ endif
+endif
+
+%.dmp: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(OD) $(ODFLAGS) $< > $@ + $(SZ) $< +else
+ @echo Creating $@
+ @$(OD) $(ODFLAGS) $< > $@
+ @echo
+ @$(SZ) $< +endif + +%.list: %.elf +ifeq ($(USE_VERBOSE_COMPILE),yes) + $(OD) -S $< > $@ +else + @echo Creating $@
+ @$(OD) -S $< > $@
+ @echo
+ @echo Done
+endif
+
+lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a
+
+$(BUILDDIR)/lib$(PROJECT).a: $(OBJS)
+ @$(AR) -r $@ $^
+ @echo
+ @echo Done
+
+clean: CLEAN_RULE_HOOK
+ @echo Cleaning
+ @echo - $(DEPDIR)
+ @-rm -fR $(DEPDIR)/* $(BUILDDIR)/* 2>/dev/null
+ @-if [ -d "$(DEPDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(DEPDIR)) 2>/dev/null; fi
+ @echo - $(BUILDDIR)
+ @-if [ -d "$(BUILDDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(BUILDDIR)) 2>/dev/null; fi
+ @echo
+ @echo Done
+
+CLEAN_RULE_HOOK:
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(wildcard $(DEPDIR)/*)
+
+# *** EOF ***
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/RVCT/cstartup.s b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/RVCT/cstartup.s new file mode 100644 index 0000000..6a94d13 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/RVCT/cstartup.s @@ -0,0 +1,131 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/RVCT/cstartup.s
+ * @brief Generic RVCT Cortex-Mx startup file.
+ *
+ * @addtogroup ARMCMx_RVCT_STARTUP
+ * @{
+ */
+
+#if !defined(__DOXYGEN__)
+
+;/* <<< Use Configuration Wizard in Context Menu >>> */
+
+;// <h> Main Stack Configuration (IRQ Stack)
+;// <o> Main Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;// </h>
+main_stack_size EQU 0x00000400
+
+;// <h> Process Stack Configuration
+;// <o> Process Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;// </h>
+proc_stack_size EQU 0x00000400
+
+;// <h> C-runtime heap size
+;// <o> C-runtime heap size (in Bytes) <0x0-0xFFFFFFFF:8>
+;// </h>
+heap_size EQU 0x00000400
+
+ AREA MSTACK, NOINIT, READWRITE, ALIGN=3
+main_stack_mem SPACE main_stack_size
+ EXPORT __initial_msp
+__initial_msp
+
+ AREA CSTACK, NOINIT, READWRITE, ALIGN=3
+__main_thread_stack_base__
+ EXPORT __main_thread_stack_base__
+proc_stack_mem SPACE proc_stack_size
+ EXPORT __initial_sp
+__initial_sp
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE heap_size
+__heap_limit
+
+CONTROL_MODE_PRIVILEGED EQU 0
+CONTROL_MODE_UNPRIVILEGED EQU 1
+CONTROL_USE_MSP EQU 0
+CONTROL_USE_PSP EQU 2
+
+ PRESERVE8
+ THUMB
+
+ AREA |.text|, CODE, READONLY
+
+/*
+ * Reset handler.
+ */
+ IMPORT __main
+ EXPORT Reset_Handler
+Reset_Handler PROC
+ cpsid i
+ ldr r0, =__initial_sp
+ msr PSP, r0
+ movs r0, #CONTROL_MODE_PRIVILEGED :OR: CONTROL_USE_PSP
+ msr CONTROL, r0
+ isb
+ bl __early_init
+
+ IF {CPU} = "Cortex-M4.fp.sp"
+ LDR R0, =0xE000ED88 ; Enable CP10,CP11
+ LDR R1, [R0]
+ ORR R1, R1, #(0xF << 20)
+ STR R1, [R0]
+ ENDIF
+
+ ldr r0, =__main
+ bx r0
+ ENDP
+
+__early_init PROC
+ EXPORT __early_init [WEAK]
+ bx lr
+ ENDP
+
+ ALIGN
+
+/*
+ * User Initial Stack & Heap.
+ */
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+ ldr r0, =Heap_Mem
+ ldr r1, =(proc_stack_mem + proc_stack_size)
+ ldr r2, =(Heap_Mem + heap_size)
+ ldr r3, =proc_stack_mem
+ bx lr
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/RVCT/vectors.s b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/RVCT/vectors.s new file mode 100644 index 0000000..13329ba --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/compilers/RVCT/vectors.s @@ -0,0 +1,1002 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ARMCMx/RVCT/vectors.c
+ * @brief Interrupt vectors for Cortex-Mx devices.
+ *
+ * @defgroup ARMCMx_RVCT_VECTORS Cortex-Mx Interrupt Vectors
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "cmparams.h"
+
+#if !defined(__DOXYGEN__)
+
+#if (CORTEX_NUM_VECTORS & 7) != 0
+#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8"
+#endif
+
+#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240)
+#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive"
+#endif
+
+ PRESERVE8
+
+ AREA RESET, DATA, READONLY
+
+ IMPORT __initial_msp
+ IMPORT Reset_Handler
+ EXPORT __Vectors
+
+__Vectors
+ DCD __initial_msp
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+ DCD Vector1C
+ DCD Vector20
+ DCD Vector24
+ DCD Vector28
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD Vector34
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+ DCD Vector40
+ DCD Vector44
+ DCD Vector48
+ DCD Vector4C
+ DCD Vector50
+ DCD Vector54
+ DCD Vector58
+ DCD Vector5C
+#if CORTEX_NUM_VECTORS > 8
+ DCD Vector60
+ DCD Vector64
+ DCD Vector68
+ DCD Vector6C
+ DCD Vector70
+ DCD Vector74
+ DCD Vector78
+ DCD Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ DCD Vector80
+ DCD Vector84
+ DCD Vector88
+ DCD Vector8C
+ DCD Vector90
+ DCD Vector94
+ DCD Vector98
+ DCD Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ DCD VectorA0
+ DCD VectorA4
+ DCD VectorA8
+ DCD VectorAC
+ DCD VectorB0
+ DCD VectorB4
+ DCD VectorB8
+ DCD VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ DCD VectorC0
+ DCD VectorC4
+ DCD VectorC8
+ DCD VectorCC
+ DCD VectorD0
+ DCD VectorD4
+ DCD VectorD8
+ DCD VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ DCD VectorE0
+ DCD VectorE4
+ DCD VectorE8
+ DCD VectorEC
+ DCD VectorF0
+ DCD VectorF4
+ DCD VectorF8
+ DCD VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ DCD Vector100
+ DCD Vector104
+ DCD Vector108
+ DCD Vector10C
+ DCD Vector110
+ DCD Vector114
+ DCD Vector118
+ DCD Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ DCD Vector120
+ DCD Vector124
+ DCD Vector128
+ DCD Vector12C
+ DCD Vector130
+ DCD Vector134
+ DCD Vector138
+ DCD Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ DCD Vector140
+ DCD Vector144
+ DCD Vector148
+ DCD Vector14C
+ DCD Vector150
+ DCD Vector154
+ DCD Vector158
+ DCD Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ DCD Vector160
+ DCD Vector164
+ DCD Vector168
+ DCD Vector16C
+ DCD Vector170
+ DCD Vector174
+ DCD Vector178
+ DCD Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ DCD Vector180
+ DCD Vector184
+ DCD Vector188
+ DCD Vector18C
+ DCD Vector190
+ DCD Vector194
+ DCD Vector198
+ DCD Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ DCD Vector1A0
+ DCD Vector1A4
+ DCD Vector1A8
+ DCD Vector1AC
+ DCD Vector1B0
+ DCD Vector1B4
+ DCD Vector1B8
+ DCD Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ DCD Vector1C0
+ DCD Vector1C4
+ DCD Vector1C8
+ DCD Vector1CC
+ DCD Vector1D0
+ DCD Vector1D4
+ DCD Vector1D8
+ DCD Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ DCD Vector1E0
+ DCD Vector1E4
+ DCD Vector1E8
+ DCD Vector1EC
+ DCD Vector1F0
+ DCD Vector1F4
+ DCD Vector1F8
+ DCD Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ DCD Vector200
+ DCD Vector204
+ DCD Vector208
+ DCD Vector20C
+ DCD Vector210
+ DCD Vector214
+ DCD Vector218
+ DCD Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ DCD Vector220
+ DCD Vector224
+ DCD Vector228
+ DCD Vector22C
+ DCD Vector230
+ DCD Vector234
+ DCD Vector238
+ DCD Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ DCD Vector240
+ DCD Vector244
+ DCD Vector248
+ DCD Vector24C
+ DCD Vector250
+ DCD Vector254
+ DCD Vector258
+ DCD Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ DCD Vector260
+ DCD Vector264
+ DCD Vector268
+ DCD Vector26C
+ DCD Vector270
+ DCD Vector274
+ DCD Vector278
+ DCD Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ DCD Vector280
+ DCD Vector284
+ DCD Vector288
+ DCD Vector28C
+ DCD Vector290
+ DCD Vector294
+ DCD Vector298
+ DCD Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ DCD Vector2A0
+ DCD Vector2A4
+ DCD Vector2A8
+ DCD Vector2AC
+ DCD Vector2B0
+ DCD Vector2B4
+ DCD Vector2B8
+ DCD Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ DCD Vector2C0
+ DCD Vector2C4
+ DCD Vector2C8
+ DCD Vector2CC
+ DCD Vector2D0
+ DCD Vector2D4
+ DCD Vector2D8
+ DCD Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ DCD Vector2E0
+ DCD Vector2E4
+ DCD Vector2E8
+ DCD Vector2EC
+ DCD Vector2F0
+ DCD Vector2F4
+ DCD Vector2F8
+ DCD Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ DCD Vector300
+ DCD Vector304
+ DCD Vector308
+ DCD Vector30C
+ DCD Vector310
+ DCD Vector314
+ DCD Vector318
+ DCD Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ DCD Vector320
+ DCD Vector324
+ DCD Vector328
+ DCD Vector32C
+ DCD Vector330
+ DCD Vector334
+ DCD Vector338
+ DCD Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ DCD Vector340
+ DCD Vector344
+ DCD Vector348
+ DCD Vector34C
+ DCD Vector350
+ DCD Vector354
+ DCD Vector358
+ DCD Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ DCD Vector360
+ DCD Vector364
+ DCD Vector368
+ DCD Vector36C
+ DCD Vector370
+ DCD Vector374
+ DCD Vector378
+ DCD Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ DCD Vector380
+ DCD Vector384
+ DCD Vector388
+ DCD Vector38C
+ DCD Vector390
+ DCD Vector394
+ DCD Vector398
+ DCD Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ DCD Vector3A0
+ DCD Vector3A4
+ DCD Vector3A8
+ DCD Vector3AC
+ DCD Vector3B0
+ DCD Vector3B4
+ DCD Vector3B8
+ DCD Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ DCD Vector3C0
+ DCD Vector3C4
+ DCD Vector3C8
+ DCD Vector3CC
+ DCD Vector3D0
+ DCD Vector3D4
+ DCD Vector3D8
+ DCD Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ DCD Vector3E0
+ DCD Vector3E4
+ DCD Vector3E8
+ DCD Vector3EC
+ DCD Vector3F0
+ DCD Vector3F4
+ DCD Vector3F8
+ DCD Vector3FC
+#endif
+
+ AREA |.text|, CODE, READONLY
+ THUMB
+
+/*
+ * Default interrupt handlers.
+ */
+ EXPORT _unhandled_exception
+_unhandled_exception PROC
+ EXPORT NMI_Handler [WEAK]
+ EXPORT HardFault_Handler [WEAK]
+ EXPORT MemManage_Handler [WEAK]
+ EXPORT BusFault_Handler [WEAK]
+ EXPORT UsageFault_Handler [WEAK]
+ EXPORT Vector1C [WEAK]
+ EXPORT Vector20 [WEAK]
+ EXPORT Vector24 [WEAK]
+ EXPORT Vector28 [WEAK]
+ EXPORT SVC_Handler [WEAK]
+ EXPORT DebugMon_Handler [WEAK]
+ EXPORT Vector34 [WEAK]
+ EXPORT PendSV_Handler [WEAK]
+ EXPORT SysTick_Handler [WEAK]
+ EXPORT Vector40 [WEAK]
+ EXPORT Vector44 [WEAK]
+ EXPORT Vector48 [WEAK]
+ EXPORT Vector4C [WEAK]
+ EXPORT Vector50 [WEAK]
+ EXPORT Vector54 [WEAK]
+ EXPORT Vector58 [WEAK]
+ EXPORT Vector5C [WEAK]
+#if CORTEX_NUM_VECTORS > 8
+ EXPORT Vector60 [WEAK]
+ EXPORT Vector64 [WEAK]
+ EXPORT Vector68 [WEAK]
+ EXPORT Vector6C [WEAK]
+ EXPORT Vector70 [WEAK]
+ EXPORT Vector74 [WEAK]
+ EXPORT Vector78 [WEAK]
+ EXPORT Vector7C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ EXPORT Vector80 [WEAK]
+ EXPORT Vector84 [WEAK]
+ EXPORT Vector88 [WEAK]
+ EXPORT Vector8C [WEAK]
+ EXPORT Vector90 [WEAK]
+ EXPORT Vector94 [WEAK]
+ EXPORT Vector98 [WEAK]
+ EXPORT Vector9C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ EXPORT VectorA0 [WEAK]
+ EXPORT VectorA4 [WEAK]
+ EXPORT VectorA8 [WEAK]
+ EXPORT VectorAC [WEAK]
+ EXPORT VectorB0 [WEAK]
+ EXPORT VectorB4 [WEAK]
+ EXPORT VectorB8 [WEAK]
+ EXPORT VectorBC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ EXPORT VectorC0 [WEAK]
+ EXPORT VectorC4 [WEAK]
+ EXPORT VectorC8 [WEAK]
+ EXPORT VectorCC [WEAK]
+ EXPORT VectorD0 [WEAK]
+ EXPORT VectorD4 [WEAK]
+ EXPORT VectorD8 [WEAK]
+ EXPORT VectorDC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ EXPORT VectorE0 [WEAK]
+ EXPORT VectorE4 [WEAK]
+ EXPORT VectorE8 [WEAK]
+ EXPORT VectorEC [WEAK]
+ EXPORT VectorF0 [WEAK]
+ EXPORT VectorF4 [WEAK]
+ EXPORT VectorF8 [WEAK]
+ EXPORT VectorFC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ EXPORT Vector100 [WEAK]
+ EXPORT Vector104 [WEAK]
+ EXPORT Vector108 [WEAK]
+ EXPORT Vector10C [WEAK]
+ EXPORT Vector110 [WEAK]
+ EXPORT Vector114 [WEAK]
+ EXPORT Vector118 [WEAK]
+ EXPORT Vector11C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ EXPORT Vector120 [WEAK]
+ EXPORT Vector124 [WEAK]
+ EXPORT Vector128 [WEAK]
+ EXPORT Vector12C [WEAK]
+ EXPORT Vector130 [WEAK]
+ EXPORT Vector134 [WEAK]
+ EXPORT Vector138 [WEAK]
+ EXPORT Vector13C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ EXPORT Vector140 [WEAK]
+ EXPORT Vector144 [WEAK]
+ EXPORT Vector148 [WEAK]
+ EXPORT Vector14C [WEAK]
+ EXPORT Vector150 [WEAK]
+ EXPORT Vector154 [WEAK]
+ EXPORT Vector158 [WEAK]
+ EXPORT Vector15C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ EXPORT Vector160 [WEAK]
+ EXPORT Vector164 [WEAK]
+ EXPORT Vector168 [WEAK]
+ EXPORT Vector16C [WEAK]
+ EXPORT Vector170 [WEAK]
+ EXPORT Vector174 [WEAK]
+ EXPORT Vector178 [WEAK]
+ EXPORT Vector17C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ EXPORT Vector180 [WEAK]
+ EXPORT Vector184 [WEAK]
+ EXPORT Vector188 [WEAK]
+ EXPORT Vector18C [WEAK]
+ EXPORT Vector190 [WEAK]
+ EXPORT Vector194 [WEAK]
+ EXPORT Vector198 [WEAK]
+ EXPORT Vector19C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ EXPORT Vector1A0 [WEAK]
+ EXPORT Vector1A4 [WEAK]
+ EXPORT Vector1A8 [WEAK]
+ EXPORT Vector1AC [WEAK]
+ EXPORT Vector1B0 [WEAK]
+ EXPORT Vector1B4 [WEAK]
+ EXPORT Vector1B8 [WEAK]
+ EXPORT Vector1BC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ EXPORT Vector1C0 [WEAK]
+ EXPORT Vector1C4 [WEAK]
+ EXPORT Vector1C8 [WEAK]
+ EXPORT Vector1CC [WEAK]
+ EXPORT Vector1D0 [WEAK]
+ EXPORT Vector1D4 [WEAK]
+ EXPORT Vector1D8 [WEAK]
+ EXPORT Vector1DC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ EXPORT Vector1E0 [WEAK]
+ EXPORT Vector1E4 [WEAK]
+ EXPORT Vector1E8 [WEAK]
+ EXPORT Vector1EC [WEAK]
+ EXPORT Vector1F0 [WEAK]
+ EXPORT Vector1F4 [WEAK]
+ EXPORT Vector1F8 [WEAK]
+ EXPORT Vector1FC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ EXPORT Vector200 [WEAK]
+ EXPORT Vector204 [WEAK]
+ EXPORT Vector208 [WEAK]
+ EXPORT Vector20C [WEAK]
+ EXPORT Vector210 [WEAK]
+ EXPORT Vector214 [WEAK]
+ EXPORT Vector218 [WEAK]
+ EXPORT Vector21C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ EXPORT Vector220 [WEAK]
+ EXPORT Vector224 [WEAK]
+ EXPORT Vector228 [WEAK]
+ EXPORT Vector22C [WEAK]
+ EXPORT Vector230 [WEAK]
+ EXPORT Vector234 [WEAK]
+ EXPORT Vector238 [WEAK]
+ EXPORT Vector23C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ EXPORT Vector240 [WEAK]
+ EXPORT Vector244 [WEAK]
+ EXPORT Vector248 [WEAK]
+ EXPORT Vector24C [WEAK]
+ EXPORT Vector250 [WEAK]
+ EXPORT Vector254 [WEAK]
+ EXPORT Vector258 [WEAK]
+ EXPORT Vector25C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ EXPORT Vector260 [WEAK]
+ EXPORT Vector264 [WEAK]
+ EXPORT Vector268 [WEAK]
+ EXPORT Vector26C [WEAK]
+ EXPORT Vector270 [WEAK]
+ EXPORT Vector274 [WEAK]
+ EXPORT Vector278 [WEAK]
+ EXPORT Vector27C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ EXPORT Vector280 [WEAK]
+ EXPORT Vector284 [WEAK]
+ EXPORT Vector288 [WEAK]
+ EXPORT Vector28C [WEAK]
+ EXPORT Vector290 [WEAK]
+ EXPORT Vector294 [WEAK]
+ EXPORT Vector298 [WEAK]
+ EXPORT Vector29C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ EXPORT Vector2A0 [WEAK]
+ EXPORT Vector2A4 [WEAK]
+ EXPORT Vector2A8 [WEAK]
+ EXPORT Vector2AC [WEAK]
+ EXPORT Vector2B0 [WEAK]
+ EXPORT Vector2B4 [WEAK]
+ EXPORT Vector2B8 [WEAK]
+ EXPORT Vector2BC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ EXPORT Vector2C0 [WEAK]
+ EXPORT Vector2C4 [WEAK]
+ EXPORT Vector2C8 [WEAK]
+ EXPORT Vector2CC [WEAK]
+ EXPORT Vector2D0 [WEAK]
+ EXPORT Vector2D4 [WEAK]
+ EXPORT Vector2D8 [WEAK]
+ EXPORT Vector2DC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ EXPORT Vector2E0 [WEAK]
+ EXPORT Vector2E4 [WEAK]
+ EXPORT Vector2E8 [WEAK]
+ EXPORT Vector2EC [WEAK]
+ EXPORT Vector2F0 [WEAK]
+ EXPORT Vector2F4 [WEAK]
+ EXPORT Vector2F8 [WEAK]
+ EXPORT Vector2FC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ EXPORT Vector300 [WEAK]
+ EXPORT Vector304 [WEAK]
+ EXPORT Vector308 [WEAK]
+ EXPORT Vector30C [WEAK]
+ EXPORT Vector310 [WEAK]
+ EXPORT Vector314 [WEAK]
+ EXPORT Vector318 [WEAK]
+ EXPORT Vector31C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ EXPORT Vector320 [WEAK]
+ EXPORT Vector324 [WEAK]
+ EXPORT Vector328 [WEAK]
+ EXPORT Vector32C [WEAK]
+ EXPORT Vector330 [WEAK]
+ EXPORT Vector334 [WEAK]
+ EXPORT Vector338 [WEAK]
+ EXPORT Vector33C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ EXPORT Vector340 [WEAK]
+ EXPORT Vector344 [WEAK]
+ EXPORT Vector348 [WEAK]
+ EXPORT Vector34C [WEAK]
+ EXPORT Vector350 [WEAK]
+ EXPORT Vector354 [WEAK]
+ EXPORT Vector358 [WEAK]
+ EXPORT Vector35C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ EXPORT Vector360 [WEAK]
+ EXPORT Vector364 [WEAK]
+ EXPORT Vector368 [WEAK]
+ EXPORT Vector36C [WEAK]
+ EXPORT Vector370 [WEAK]
+ EXPORT Vector374 [WEAK]
+ EXPORT Vector378 [WEAK]
+ EXPORT Vector37C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ EXPORT Vector380 [WEAK]
+ EXPORT Vector384 [WEAK]
+ EXPORT Vector388 [WEAK]
+ EXPORT Vector38C [WEAK]
+ EXPORT Vector390 [WEAK]
+ EXPORT Vector394 [WEAK]
+ EXPORT Vector398 [WEAK]
+ EXPORT Vector39C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ EXPORT Vector3A0 [WEAK]
+ EXPORT Vector3A4 [WEAK]
+ EXPORT Vector3A8 [WEAK]
+ EXPORT Vector3AC [WEAK]
+ EXPORT Vector3B0 [WEAK]
+ EXPORT Vector3B4 [WEAK]
+ EXPORT Vector3B8 [WEAK]
+ EXPORT Vector3BC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ EXPORT Vector3C0 [WEAK]
+ EXPORT Vector3C4 [WEAK]
+ EXPORT Vector3C8 [WEAK]
+ EXPORT Vector3CC [WEAK]
+ EXPORT Vector3D0 [WEAK]
+ EXPORT Vector3D4 [WEAK]
+ EXPORT Vector3D8 [WEAK]
+ EXPORT Vector3DC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ EXPORT Vector3E0 [WEAK]
+ EXPORT Vector3E4 [WEAK]
+ EXPORT Vector3E8 [WEAK]
+ EXPORT Vector3EC [WEAK]
+ EXPORT Vector3F0 [WEAK]
+ EXPORT Vector3F4 [WEAK]
+ EXPORT Vector3F8 [WEAK]
+ EXPORT Vector3FC [WEAK]
+#endif
+
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+Vector1C
+Vector20
+Vector24
+Vector28
+SVC_Handler
+DebugMon_Handler
+Vector34
+PendSV_Handler
+SysTick_Handler
+Vector40
+Vector44
+Vector48
+Vector4C
+Vector50
+Vector54
+Vector58
+Vector5C
+#if CORTEX_NUM_VECTORS > 8
+Vector60
+Vector64
+Vector68
+Vector6C
+Vector70
+Vector74
+Vector78
+Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+Vector80
+Vector84
+Vector88
+Vector8C
+Vector90
+Vector94
+Vector98
+Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+VectorA0
+VectorA4
+VectorA8
+VectorAC
+VectorB0
+VectorB4
+VectorB8
+VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+VectorC0
+VectorC4
+VectorC8
+VectorCC
+VectorD0
+VectorD4
+VectorD8
+VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+VectorE0
+VectorE4
+VectorE8
+VectorEC
+VectorF0
+VectorF4
+VectorF8
+VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+Vector100
+Vector104
+Vector108
+Vector10C
+Vector110
+Vector114
+Vector118
+Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+Vector120
+Vector124
+Vector128
+Vector12C
+Vector130
+Vector134
+Vector138
+Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+Vector140
+Vector144
+Vector148
+Vector14C
+Vector150
+Vector154
+Vector158
+Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+Vector160
+Vector164
+Vector168
+Vector16C
+Vector170
+Vector174
+Vector178
+Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+Vector180
+Vector184
+Vector188
+Vector18C
+Vector190
+Vector194
+Vector198
+Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+Vector1A0
+Vector1A4
+Vector1A8
+Vector1AC
+Vector1B0
+Vector1B4
+Vector1B8
+Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+Vector1C0
+Vector1C4
+Vector1C8
+Vector1CC
+Vector1D0
+Vector1D4
+Vector1D8
+Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+Vector1E0
+Vector1E4
+Vector1E8
+Vector1EC
+Vector1F0
+Vector1F4
+Vector1F8
+Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+Vector200
+Vector204
+Vector208
+Vector20C
+Vector210
+Vector214
+Vector218
+Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+Vector220
+Vector224
+Vector228
+Vector22C
+Vector230
+Vector234
+Vector238
+Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+Vector240
+Vector244
+Vector248
+Vector24C
+Vector250
+Vector254
+Vector258
+Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+Vector260
+Vector264
+Vector268
+Vector26C
+Vector270
+Vector274
+Vector278
+Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+Vector280
+Vector284
+Vector288
+Vector28C
+Vector290
+Vector294
+Vector298
+Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+Vector2A0
+Vector2A4
+Vector2A8
+Vector2AC
+Vector2B0
+Vector2B4
+Vector2B8
+Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+Vector2C0
+Vector2C4
+Vector2C8
+Vector2CC
+Vector2D0
+Vector2D4
+Vector2D8
+Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+Vector2E0
+Vector2E4
+Vector2E8
+Vector2EC
+Vector2F0
+Vector2F4
+Vector2F8
+Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+Vector300
+Vector304
+Vector308
+Vector30C
+Vector310
+Vector314
+Vector318
+Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+Vector320
+Vector324
+Vector328
+Vector32C
+Vector330
+Vector334
+Vector338
+Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+Vector340
+Vector344
+Vector348
+Vector34C
+Vector350
+Vector354
+Vector358
+Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+Vector360
+Vector364
+Vector368
+Vector36C
+Vector370
+Vector374
+Vector378
+Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+Vector380
+Vector384
+Vector388
+Vector38C
+Vector390
+Vector394
+Vector398
+Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+Vector3A0
+Vector3A4
+Vector3A8
+Vector3AC
+Vector3B0
+Vector3B4
+Vector3B8
+Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+Vector3C0
+Vector3C4
+Vector3C8
+Vector3CC
+Vector3D0
+Vector3D4
+Vector3D8
+Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+Vector3E0
+Vector3E4
+Vector3E8
+Vector3EC
+Vector3F0
+Vector3F4
+Vector3F8
+Vector3FC
+#endif
+ b _unhandled_exception
+ ENDP
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/ADUCM36x/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/ADUCM36x/cmparams.h new file mode 100644 index 0000000..cd712bd --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/ADUCM36x/cmparams.h @@ -0,0 +1,84 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F2xx/cmparams.h
+ * @brief ARM Cortex-M3 parameters for the STM32F2xx.
+ *
+ * @defgroup ARMCMx_STM32F2xx STM32F2xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M3 specific parameters for the
+ * STM32F2xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 3
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 3
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(ADUCM36X)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 40
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "ADuCM36x.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/ADUCM41x/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/ADUCM41x/cmparams.h new file mode 100644 index 0000000..536b70e --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/ADUCM41x/cmparams.h @@ -0,0 +1,89 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ADUCM41x/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the ADUCM41x.
+ *
+ * @defgroup ARMCMx_ADUCM41x ADUCM41x Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M33 specific parameters for the
+ * ADUCM41x platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ * @todo Switch to M33 when port is done.
+ */
+#define CORTEX_MODEL 4
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 3
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(ADUCM41X)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 80
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "aducm41x.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_HAS_FPU != __FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F0xx/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F0xx/cmparams.h new file mode 100644 index 0000000..a5ffdcf --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F0xx/cmparams.h @@ -0,0 +1,93 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F0xx/cmparams.h
+ * @brief ARM Cortex-M0 parameters for the STM32F0xx.
+ *
+ * @defgroup ARMCMx_STM32F0xx STM32F0xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M0 specific parameters for the
+ * STM32F0xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 0
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 2
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined (STM32F030x4) && !defined (STM32F030x6) && \
+ !defined (STM32F030x8) && !defined (STM32F030xC) && \
+ !defined (STM32F070x6) && !defined (STM32F070xB) && \
+ !defined (STM32F031x6) && !defined (STM32F051x8) && \
+ !defined (STM32F071xB) && !defined (STM32F091xC) && \
+ !defined (STM32F042x6) && !defined (STM32F072xB) && \
+ !defined (STM32F038xx) && !defined (STM32F048xx) && \
+ !defined (STM32F058xx) && !defined (STM32F078xx) && \
+ !defined (STM32F098xx) \
+
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 32
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f0xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F1xx/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F1xx/cmparams.h new file mode 100644 index 0000000..8ac35ed --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F1xx/cmparams.h @@ -0,0 +1,90 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F1xx/cmparams.h
+ * @brief ARM Cortex-M3 parameters for the STM32F1xx.
+ *
+ * @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32F1xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 3
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32F100xB) && !defined(STM32F100xE) && \
+ !defined(STM32F101x6) && !defined(STM32F101xB) && \
+ !defined(STM32F101xE) && !defined(STM32F101xG) && \
+ !defined(STM32F102x6) && !defined(STM32F102xB) && \
+ !defined(STM32F103x6) && !defined(STM32F103xB) && \
+ !defined(STM32F103xE) && !defined(STM32F103xG) && \
+ !defined(STM32F105xC) && !defined(STM32F107xC)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 72
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f1xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F2xx/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F2xx/cmparams.h new file mode 100644 index 0000000..0451134 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F2xx/cmparams.h @@ -0,0 +1,84 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F2xx/cmparams.h
+ * @brief ARM Cortex-M3 parameters for the STM32F2xx.
+ *
+ * @defgroup ARMCMx_STM32F2xx STM32F2xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M3 specific parameters for the
+ * STM32F2xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 3
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32F2XX)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 96
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f2xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F3xx/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F3xx/cmparams.h new file mode 100644 index 0000000..8c2877e --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F3xx/cmparams.h @@ -0,0 +1,93 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F3xx/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the STM32F3xx.
+ *
+ * @defgroup ARMCMx_STM32F3xx STM32F3xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32F3xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 4
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined (STM32F301x8) && !defined (STM32F318xx) && \
+ !defined (STM32F302x8) && !defined (STM32F302xC) && \
+ !defined (STM32F303x8) && !defined (STM32F303xC) && \
+ !defined (STM32F358xx) && !defined (STM32F334x8) && \
+ !defined (STM32F328xx) && \
+ !defined (STM32F373xC) && !defined (STM32F378xx)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 88
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f3xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_HAS_FPU != __FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F4xx/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F4xx/cmparams.h new file mode 100644 index 0000000..1fa5e8c --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F4xx/cmparams.h @@ -0,0 +1,100 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F4xx/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the STM32F4xx.
+ *
+ * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32F4xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 4
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32F405xx) && !defined(STM32F415xx) && \
+ !defined(STM32F407xx) && !defined(STM32F417xx) && \
+ !defined(STM32F427xx) && !defined(STM32F437xx) && \
+ !defined(STM32F429xx) && !defined(STM32F439xx) && \
+ !defined(STM32F401xC) && !defined(STM32F401xE) && \
+ !defined(STM32F410Cx) && !defined(STM32F410Rx) && \
+ !defined(STM32F410Tx) && \
+ !defined(STM32F411xE) && \
+ !defined(STM32F412Cx) && !defined(STM32F412Rx) && \
+ !defined(STM32F412Vx) && !defined(STM32F412Zx) && \
+ !defined(STM32F413xx) && \
+ !defined(STM32F446xx) && \
+ !defined(STM32F469xx) && !defined(STM32F479xx)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 104
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f4xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_HAS_FPU != __FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F7xx/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F7xx/cmparams.h new file mode 100644 index 0000000..fae6394 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32F7xx/cmparams.h @@ -0,0 +1,93 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F7xx/cmparams.h
+ * @brief ARM Cortex-M7 parameters for the STM32F4xx.
+ *
+ * @defgroup ARMCMx_STM32F7xx STM32F7xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M7 specific parameters for the
+ * STM32F7xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 7
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32F722xx) && !defined(STM32F723xx) && \
+ !defined(STM32F732xx) && !defined(STM32F733xx) && \
+ !defined(STM32F745xx) && !defined(STM32F746xx) && \
+ !defined(STM32F756xx) && !defined(STM32F765xx) && \
+ !defined(STM32F767xx) && !defined(STM32F769xx) && \
+ !defined(STM32F777xx) && !defined(STM32F779xx)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 112
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f7xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_HAS_FPU != __FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32G0xx/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32G0xx/cmparams.h new file mode 100644 index 0000000..83121a3 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32G0xx/cmparams.h @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32G0xx/cmparams.h
+ * @brief ARM Cortex-M0 parameters for the STM32G0xx.
+ *
+ * @defgroup ARMCMx_STM32G0xx STM32G0xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M0 specific parameters for the
+ * STM32G0xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 0
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 2
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined (STM32G071xx) && !defined (STM32G081xx) && \
+ !defined (STM32G070xx)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 32
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32g0xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32G4xx/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32G4xx/cmparams.h new file mode 100644 index 0000000..972f9df --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32G4xx/cmparams.h @@ -0,0 +1,91 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32G4xx/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the STM32G4xx.
+ *
+ * @defgroup ARMCMx_STM32FGxx STM32FGxx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32G4xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 4
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32G431xx) && !defined(STM32G441xx) && \
+ !defined(STM32G471xx) && !defined(STM32G473xx) && \
+ !defined(STM32G474xx) && !defined(STM32G483xx) && \
+ !defined(STM32G484xx) && !defined(STM32GBK1CB)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 104
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32g4xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_HAS_FPU != __FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32H7xx/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32H7xx/cmparams.h new file mode 100644 index 0000000..0854f36 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32H7xx/cmparams.h @@ -0,0 +1,94 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32H7xx/cmparams.h
+ * @brief ARM Cortex-M7 parameters for the STM32F4xx.
+ *
+ * @defgroup ARMCMx_STM32H7xx STM32H7xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M7 specific parameters for the
+ * STM32H7xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 7
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32H742xx) && !defined(STM32H750xx) && \
+ !defined(STM32H743xx) && !defined(STM32H753xx) && \
+ !defined(STM32H747xx) && !defined(STM32H757xx) && \
+ !defined(STM32H745xx) && !defined(STM32H755xx) && \
+ !defined(STM32H7B0xx) && !defined(STM32H7B0xxQ) && \
+ !defined(STM32H7A3xx) && !defined(STM32H7A3xxQ) && \
+ !defined(STM32H7B3xx) && !defined(STM32H7B3xxQ)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 152
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32h7xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_HAS_FPU != __FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32L0xx/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32L0xx/cmparams.h new file mode 100644 index 0000000..1913a67 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32L0xx/cmparams.h @@ -0,0 +1,88 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L0xx/cmparams.h
+ * @brief ARM Cortex-M0+ parameters for the STM32L0xx.
+ *
+ * @defgroup ARMCMx_STM32L0xx STM32L0xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M0 specific parameters for the
+ * STM32L0xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 0
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 2
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32L011xx) && !defined(STM32L031xx) && \
+ !defined(STM32L051xx) && !defined(STM32L052xx) && \
+ !defined(STM32L053xx) && !defined(STM32L061xx) && \
+ !defined(STM32L062xx) && !defined(STM32L063xx) && \
+ !defined(STM32L073xx)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 32
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32l0xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32L1xx/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32L1xx/cmparams.h new file mode 100644 index 0000000..5b3f5f4 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32L1xx/cmparams.h @@ -0,0 +1,97 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L1xx/cmparams.h
+ * @brief ARM Cortex-M3 parameters for the STM32L1xx.
+ *
+ * @defgroup ARMCMx_STM32L1xx STM32L1xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M3 specific parameters for the
+ * STM32L1xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 3
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32L100xB) && !defined(STM32L100xBA) && \
+ !defined(STM32L100xC) && !defined(STM32L151xB) && \
+ !defined(STM32L151xBA) && !defined(STM32L151xC) && \
+ !defined(STM32L151xCA) && !defined(STM32L151xD) && \
+ !defined(STM32L151xDX) && !defined(STM32L151xE) && \
+ !defined(STM32L152xB) && !defined(STM32L152xBA) && \
+ !defined(STM32L152xC) && !defined(STM32L152xCA) && \
+ !defined(STM32L152xD) && !defined(STM32L152xDX) && \
+ !defined(STM32L152xE) && !defined(STM32L162xC) && \
+ !defined(STM32L162xCA) && !defined(STM32L162xD) && \
+ !defined(STM32L162xDX) && !defined(STM32L162xE)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 64
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32l1xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+/* Fix for yet another consistency error in ST headers.*/
+#define SVCall_IRQn SVC_IRQn
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h new file mode 100644 index 0000000..c55fcc1 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/ARMCMx/devices/STM32L4xx/cmparams.h @@ -0,0 +1,104 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the STM32L4xx.
+ *
+ * @defgroup ARMCMx_STM32L4xx STM32L4xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32L4xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 4
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32L431xx) && !defined(STM32L432xx) && \
+ !defined(STM32L433xx) && !defined(STM32L442xx) && \
+ !defined(STM32L443xx) && !defined(STM32L451xx) && \
+ !defined(STM32L452xx) && !defined(STM32L462xx) && \
+ !defined(STM32L471xx) && !defined(STM32L475xx) && \
+ !defined(STM32L476xx) && !defined(STM32L485xx) && \
+ !defined(STM32L486xx) && !defined(STM32L496xx) && \
+ !defined(STM32L4A6xx) && \
+ !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && \
+ !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && \
+ !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#if defined(STM32L496xx) || defined(STM32L4A6xx) || defined(STM32L4R5xx) || \
+ defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
+ defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define CORTEX_NUM_VECTORS 96
+#else
+#define CORTEX_NUM_VECTORS 88
+#endif
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32l4xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_HAS_FPU != __FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/SIMIA32/compilers/GCC/rules.mk b/ChibiOS_20.3.2/os/common/startup/SIMIA32/compilers/GCC/rules.mk new file mode 100644 index 0000000..73a6d14 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/SIMIA32/compilers/GCC/rules.mk @@ -0,0 +1,206 @@ +# e200z common makefile scripts and rules.
+
+##############################################################################
+# Processing options coming from the upper Makefile.
+#
+
+# Compiler options
+OPT = $(USE_OPT)
+COPT = $(USE_COPT)
+CPPOPT = $(USE_CPPOPT)
+
+# Garbage collection
+ifeq ($(USE_LINK_GC),yes)
+ OPT += -ffunction-sections -fdata-sections -fno-common
+ LDOPT := --gc-sections
+else
+ LDOPT := --no-gc-sections
+endif
+
+# Linker extra options
+ifneq ($(USE_LDOPT),)
+ LDOPT := $(LDOPT),$(USE_LDOPT)
+endif
+
+# Link time optimizations
+ifeq ($(USE_LTO),yes)
+ OPT += -flto
+endif
+
+# Output directory and files
+ifeq ($(BUILDDIR),)
+ BUILDDIR = build
+endif
+ifeq ($(BUILDDIR),.)
+ BUILDDIR = build
+endif
+
+# Dependencies directory
+ifeq ($(DEPDIR),)
+ DEPDIR = .dep
+endif
+ifeq ($(DEPDIR),.)
+ DEPDIR = .dep
+endif
+
+OUTFILES = $(BUILDDIR)/$(PROJECT)
+
+# Source files groups and paths
+SRC = $(CSRC)$(CPPSRC)
+SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(SRC)))
+
+# Various directories
+OBJDIR = $(BUILDDIR)/obj
+LSTDIR = $(BUILDDIR)/lst
+
+# Object files groups
+COBJS = $(addprefix $(OBJDIR)/, $(notdir $(CSRC:.c=.o)))
+#CPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(CPPSRC:.cpp=.o)))
+CPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(patsubst %.cpp, %.o, $(filter %.cpp, $(CPPSRC)))))
+CCOBJS := $(addprefix $(OBJDIR)/, $(notdir $(patsubst %.cc, %.o, $(filter %.cc, $(CPPSRC)))))
+ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
+ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+#OBJS = $(ASMXOBJS) $(ASMOBJS) $(COBJS) $(CPPOBJS)
+OBJS = $(ASMXOBJS) $(ASMOBJS) $(COBJS) $(CPPOBJS) $(CCOBJS)
+
+# Paths
+IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
+LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+
+# Macros
+DEFS = $(DDEFS) $(UDEFS)
+ADEFS = $(DADEFS) $(UADEFS)
+
+# Libs
+LIBS = $(DLIBS) $(ULIBS)
+
+# Various settings
+MCFLAGS =
+ODFLAGS = -x --syms
+ASFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+ASXFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
+CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
+CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
+LDFLAGS = $(MCFLAGS) $(OPT) $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,$(LDOPT)
+
+# Generate dependency information
+ASFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+ASXFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+CFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+CPPFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+
+# Paths where to search for sources
+VPATH = $(SRCPATHS)
+
+#
+# Makefile rules
+#
+
+all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK
+
+PRE_MAKE_ALL_RULE_HOOK:
+
+POST_MAKE_ALL_RULE_HOOK:
+
+$(OBJS): | PRE_MAKE_ALL_RULE_HOOK $(BUILDDIR) $(OBJDIR) $(LSTDIR) $(DEPDIR)
+
+$(BUILDDIR):
+ifneq ($(USE_VERBOSE_COMPILE),yes)
+ @echo Compiler Options
+ @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
+ @echo
+endif
+ @mkdir -p $(BUILDDIR)
+
+$(OBJDIR):
+ @mkdir -p $(OBJDIR)
+
+$(LSTDIR):
+ @mkdir -p $(LSTDIR)
+
+$(DEPDIR):
+ @mkdir -p $(DEPDIR)
+
+$(CPPOBJS) : $(OBJDIR)/%.o : %.cpp $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(CCOBJS) : $(OBJDIR)/%.o : %.cc $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(COBJS) : $(OBJDIR)/%.o : %.c $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMOBJS) : $(OBJDIR)/%.o : %.s $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(BUILDDIR)/$(PROJECT): $(OBJS)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+else
+ @echo Linking $@
+ @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+endif
+
+lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a
+
+$(BUILDDIR)/lib$(PROJECT).a: $(OBJS)
+ @$(AR) -r $@ $^
+ @echo
+ @echo Done
+
+clean: CLEAN_RULE_HOOK
+ @echo Cleaning
+ @echo - $(DEPDIR)
+ @-rm -fR $(DEPDIR)/* $(BUILDDIR)/* 2>/dev/null
+ @-if [ -d "$(DEPDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(DEPDIR)) 2>/dev/null; fi
+ @echo - $(BUILDDIR)
+ @-if [ -d "$(BUILDDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(BUILDDIR)) 2>/dev/null; fi
+ @echo
+ @echo Done
+
+CLEAN_RULE_HOOK:
+
+.PHONY: gcov
+gcov:
+ $(COV) -u -b -o $(BUILDDIR)/obj $(GCOVSRC)
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(wildcard $(DEPDIR)/*)
+
+# *** EOF ***
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/CW/crt0.s b/ChibiOS_20.3.2/os/common/startup/e200/compilers/CW/crt0.s new file mode 100644 index 0000000..e99935a --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/CW/crt0.s @@ -0,0 +1,258 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file CW/crt0.s
+ * @brief Generic PowerPC startup file for CodeWarrior.
+ *
+ * @addtogroup PPC_CW_CORE
+ * @{
+ */
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
+#define CRT0_STACKS_FILL_PATTERN 0x55555555
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
+#define CRT0_INIT_STACKS TRUE
+#endif
+
+/**
+ * @brief DATA segment initialization switch.
+ */
+#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
+#define CRT0_INIT_DATA TRUE
+#endif
+
+/**
+ * @brief BSS segment initialization switch.
+ */
+#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
+#define CRT0_INIT_BSS TRUE
+#endif
+
+/**
+ * @brief Constructors invocation switch.
+ */
+#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_CONSTRUCTORS FALSE
+#endif
+
+/**
+ * @brief Destructors invocation switch.
+ */
+#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_DESTRUCTORS FALSE
+#endif
+
+/*===========================================================================*/
+/* Code section. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+ .extern __sdata2_start__
+ .extern __sdata_start__
+ .extern __bss_start__
+ .extern __bss_end__
+ .extern __irq_stack_base__
+ .extern __irq_stack_end__
+ .extern __process_stack_end__
+ .extern __process_stack_base__
+ .extern __romdata_start__
+ .extern __data_start__
+ .extern __data_end__
+ .extern __init_array_start
+ .extern __init_array_end
+ .extern __fini_array_start
+ .extern __fini_array_end
+
+ .extern main
+
+ .section .crt0, text_vle
+ .align 16
+ .globl _boot_address
+ .type _boot_address, @function
+_boot_address:
+ /* Stack setup.*/
+ e_lis r1, __process_stack_end__@h
+ e_or2i r1, __process_stack_end__@l
+ se_li r0, 0
+ e_stwu r0, -8(r1)
+
+ /* Small sections registers initialization.*/
+ e_lis r2, __sdata2_start__@h
+ e_or2i r2, __sdata2_start__@l
+ e_lis r13, __sdata_start__@h
+ e_or2i r13, __sdata_start__@l
+
+ /* Early initialization.*/
+ e_bl __early_init
+
+#if CRT0_INIT_STACKS == TRUE
+ /* Stacks fill pattern.*/
+ e_lis r7, CRT0_STACKS_FILL_PATTERN@h
+ e_or2i r7, CRT0_STACKS_FILL_PATTERN@l
+
+ /* IRQ Stack initialization. Note, the architecture does not use this
+ stack, the size is usually zero. An OS can have special SW handling
+ and require this. A 4 bytes alignment is assumed and required.*/
+ e_lis r4, __irq_stack_base__@h
+ e_or2i r4, __irq_stack_base__@l
+ e_lis r5, __irq_stack_end__@h
+ e_or2i r5, __irq_stack_end__@l
+.irqsloop:
+ se_cmpl r4, r5
+ se_bge .irqsend
+ se_stw r7, 0(r4)
+ se_addi r4, 4
+ se_b .irqsloop
+.irqsend:
+
+ /* Process Stack initialization. Note, does not overwrite the already
+ written EABI frame. A 4 bytes alignment is assumed and required.*/
+ e_lis r4, __process_stack_base__@h
+ e_or2i r4, __process_stack_base__@l
+ e_lis r5, (__process_stack_end__ - 8)@h
+ e_or2i r5, (__process_stack_end__ - 8)@l
+.prcsloop:
+ se_cmpl r4, r5
+ se_bge .prcsend
+ se_stw r7, 0(r4)
+ se_addi r4, 4
+ se_b .prcsloop
+.prcsend:
+#endif
+
+#if CRT0_INIT_BSS == TRUE
+ /* BSS clearing.*/
+ e_lis r4, __bss_start__@h
+ e_or2i r4, __bss_start__@l
+ e_lis r5, __bss_end__@h
+ e_or2i r5, __bss_end__@l
+ se_li r7, 0
+.bssloop:
+ se_cmpl r4, r5
+ se_bge .bssend
+ se_stw r7, 0(r4)
+ se_addi r4, 4
+ se_b .bssloop
+.bssend:
+#endif
+
+#if CRT0_INIT_DATA == TRUE
+ /* DATA initialization.*/
+ e_lis r4, __romdata_start__@h
+ e_or2i r4, __romdata_start__@l
+ e_lis r5, __data_start__@h
+ e_or2i r5, __data_start__@l
+ e_lis r6, __data_end__@h
+ e_or2i r6, __data_end__@l
+.dataloop:
+ se_cmpl r5, r6
+ se_bge .dataend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .dataloop
+.dataend:
+#endif
+
+ /* Late initialization.*/
+ e_bl __late_init
+
+#if CRT0_CALL_CONSTRUCTORS == TRUE
+ /* Constructors invocation.*/
+ e_lis r4, __init_array_start@h
+ e_or2i r4, __init_array_start@l
+ e_lis r5, __init_array_end@h
+ e_or2i r5, __init_array_end@l
+.iniloop:
+ se_cmpl r4, r5
+ se_bge .iniend
+ se_lwz r6, 0(r4)
+ se_mtctr r6
+ se_addi r4, 4
+ se_bctrl
+ se_b .iniloop
+.iniend:
+#endif
+
+ /* Main program invocation.*/
+ e_bl main
+
+#if CRT0_CALL_DESTRUCTORS == TRUE
+ /* Destructors invocation.*/
+ e_lis r4, __fini_array_start@h
+ e_or2i r4, __fini_array_start@l
+ e_lis r5, __fini_array_end@h
+ e_or2i r5, __fini_array_end@l
+.finiloop:
+ se_cmpl r4, r5
+ se_bge .finiend
+ se_lwz r6, 0(r4)
+ se_mtctr r6
+ se_addi r4, 4
+ se_bctrl
+ se_b .finiloop
+.finiend:
+#endif
+
+ /* Branching to the defined exit handler.*/
+ e_b __default_exit
+
+#endif /* !defined(__DOXYGEN__) */
+
+ .section .text_vle
+ .align 4
+
+ /* Default main exit code, infinite loop.*/
+ .weak __default_exit
+__default_exit:
+ e_b __default_exit
+
+ /* Default early initialization code, none.*/
+ .weak __early_init
+ se_blr
+
+ /* Default late initialization code, none.*/
+ .weak __late_init
+__late_init:
+ se_blr
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/CW/unhandled.s b/ChibiOS_20.3.2/os/common/startup/e200/compilers/CW/unhandled.s new file mode 100644 index 0000000..f318979 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/CW/unhandled.s @@ -0,0 +1,1858 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file weak.s
+ * @brief Unhandled IRQs.
+ *
+ * @addtogroup PPC_CW_CORE
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "ppcparams.h"
+
+#if defined(VECTORS_RENAMING)
+#include "isrs.h"
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ .section .text_vle
+ .align 4
+
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR4:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR10:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+ .global _unhandled_exception
+_unhandled_exception:
+ se_b _unhandled_exception
+
+ .weak vector0, vector1, vector2, vector3
+#if PPC_NUM_VECTORS > 4
+ .weak vector4, vector5, vector6, vector7
+#endif
+#if PPC_NUM_VECTORS > 8
+ .weak vector8, vector9, vector10, vector11
+#endif
+#if PPC_NUM_VECTORS > 12
+ .weak vector12, vector13, vector14, vector15
+#endif
+#if PPC_NUM_VECTORS > 16
+ .weak vector16, vector17, vector18, vector19
+#endif
+#if PPC_NUM_VECTORS > 20
+ .weak vector20, vector21, vector22, vector23
+#endif
+#if PPC_NUM_VECTORS > 24
+ .weak vector24, vector25, vector26, vector27
+#endif
+#if PPC_NUM_VECTORS > 28
+ .weak vector28, vector29, vector30, vector31
+#endif
+#if PPC_NUM_VECTORS > 32
+ .weak vector32, vector33, vector34, vector35
+#endif
+#if PPC_NUM_VECTORS > 36
+ .weak vector36, vector37, vector38, vector39
+#endif
+#if PPC_NUM_VECTORS > 40
+ .weak vector40, vector41, vector42, vector43
+#endif
+#if PPC_NUM_VECTORS > 44
+ .weak vector44, vector45, vector46, vector47
+#endif
+#if PPC_NUM_VECTORS > 48
+ .weak vector48, vector49, vector50, vector51
+#endif
+#if PPC_NUM_VECTORS > 52
+ .weak vector52, vector53, vector54, vector55
+#endif
+#if PPC_NUM_VECTORS > 56
+ .weak vector56, vector57, vector58, vector59
+#endif
+#if PPC_NUM_VECTORS > 60
+ .weak vector60, vector61, vector62, vector63
+#endif
+#if PPC_NUM_VECTORS > 64
+ .weak vector64, vector65, vector66, vector67
+#endif
+#if PPC_NUM_VECTORS > 68
+ .weak vector68, vector69, vector70, vector71
+#endif
+#if PPC_NUM_VECTORS > 72
+ .weak vector72, vector73, vector74, vector75
+#endif
+#if PPC_NUM_VECTORS > 76
+ .weak vector76, vector77, vector78, vector79
+#endif
+#if PPC_NUM_VECTORS > 80
+ .weak vector80, vector81, vector82, vector83
+#endif
+#if PPC_NUM_VECTORS > 84
+ .weak vector84, vector85, vector86, vector87
+#endif
+#if PPC_NUM_VECTORS > 88
+ .weak vector88, vector89, vector90, vector91
+#endif
+#if PPC_NUM_VECTORS > 92
+ .weak vector92, vector93, vector94, vector95
+#endif
+#if PPC_NUM_VECTORS > 96
+ .weak vector96, vector97, vector98, vector99
+#endif
+#if PPC_NUM_VECTORS > 100
+ .weak vector100, vector101, vector102, vector103
+#endif
+#if PPC_NUM_VECTORS > 104
+ .weak vector104, vector105, vector106, vector107
+#endif
+#if PPC_NUM_VECTORS > 108
+ .weak vector108, vector109, vector110, vector111
+#endif
+#if PPC_NUM_VECTORS > 112
+ .weak vector112, vector113, vector114, vector115
+#endif
+#if PPC_NUM_VECTORS > 116
+ .weak vector116, vector117, vector118, vector119
+#endif
+#if PPC_NUM_VECTORS > 120
+ .weak vector120, vector121, vector122, vector123
+#endif
+#if PPC_NUM_VECTORS > 124
+ .weak vector124, vector125, vector126, vector127
+#endif
+#if PPC_NUM_VECTORS > 128
+ .weak vector128, vector129, vector130, vector131
+#endif
+#if PPC_NUM_VECTORS > 132
+ .weak vector132, vector133, vector134, vector135
+#endif
+#if PPC_NUM_VECTORS > 136
+ .weak vector136, vector137, vector138, vector139
+#endif
+#if PPC_NUM_VECTORS > 140
+ .weak vector140, vector141, vector142, vector143
+#endif
+#if PPC_NUM_VECTORS > 144
+ .weak vector144, vector145, vector146, vector147
+#endif
+#if PPC_NUM_VECTORS > 148
+ .weak vector148, vector149, vector150, vector151
+#endif
+#if PPC_NUM_VECTORS > 152
+ .weak vector152, vector153, vector154, vector155
+#endif
+#if PPC_NUM_VECTORS > 156
+ .weak vector156, vector157, vector158, vector159
+#endif
+#if PPC_NUM_VECTORS > 160
+ .weak vector160, vector161, vector162, vector163
+#endif
+#if PPC_NUM_VECTORS > 164
+ .weak vector164, vector165, vector166, vector167
+#endif
+#if PPC_NUM_VECTORS > 168
+ .weak vector168, vector169, vector170, vector171
+#endif
+#if PPC_NUM_VECTORS > 172
+ .weak vector172, vector173, vector174, vector175
+#endif
+#if PPC_NUM_VECTORS > 176
+ .weak vector176, vector177, vector178, vector179
+#endif
+#if PPC_NUM_VECTORS > 180
+ .weak vector180, vector181, vector182, vector183
+#endif
+#if PPC_NUM_VECTORS > 184
+ .weak vector184, vector185, vector186, vector187
+#endif
+#if PPC_NUM_VECTORS > 188
+ .weak vector188, vector189, vector190, vector191
+#endif
+#if PPC_NUM_VECTORS > 192
+ .weak vector192, vector193, vector194, vector195
+#endif
+#if PPC_NUM_VECTORS > 196
+ .weak vector196, vector197, vector198, vector199
+#endif
+#if PPC_NUM_VECTORS > 200
+ .weak vector200, vector201, vector202, vector203
+#endif
+#if PPC_NUM_VECTORS > 204
+ .weak vector204, vector205, vector206, vector207
+#endif
+#if PPC_NUM_VECTORS > 208
+ .weak vector208, vector209, vector210, vector211
+#endif
+#if PPC_NUM_VECTORS > 212
+ .weak vector212, vector213, vector214, vector215
+#endif
+#if PPC_NUM_VECTORS > 216
+ .weak vector216, vector217, vector218, vector219
+#endif
+#if PPC_NUM_VECTORS > 220
+ .weak vector220, vector221, vector222, vector223
+#endif
+#if PPC_NUM_VECTORS > 224
+ .weak vector224, vector225, vector226, vector227
+#endif
+#if PPC_NUM_VECTORS > 228
+ .weak vector228, vector229, vector230, vector231
+#endif
+#if PPC_NUM_VECTORS > 232
+ .weak vector232, vector233, vector234, vector235
+#endif
+#if PPC_NUM_VECTORS > 236
+ .weak vector236, vector237, vector238, vector239
+#endif
+#if PPC_NUM_VECTORS > 240
+ .weak vector240, vector241, vector242, vector243
+#endif
+#if PPC_NUM_VECTORS > 244
+ .weak vector244, vector245, vector246, vector247
+#endif
+#if PPC_NUM_VECTORS > 248
+ .weak vector248, vector249, vector250, vector251
+#endif
+#if PPC_NUM_VECTORS > 252
+ .weak vector252, vector253, vector254, vector255
+#endif
+#if PPC_NUM_VECTORS > 256
+ .weak vector256, vector257, vector258, vector259
+#endif
+#if PPC_NUM_VECTORS > 260
+ .weak vector260, vector261, vector262, vector263
+#endif
+#if PPC_NUM_VECTORS > 264
+ .weak vector264, vector265, vector266, vector267
+#endif
+#if PPC_NUM_VECTORS > 268
+ .weak vector268, vector269, vector270, vector271
+#endif
+#if PPC_NUM_VECTORS > 272
+ .weak vector272, vector273, vector274, vector275
+#endif
+#if PPC_NUM_VECTORS > 276
+ .weak vector276, vector277, vector278, vector279
+#endif
+#if PPC_NUM_VECTORS > 280
+ .weak vector280, vector281, vector282, vector283
+#endif
+#if PPC_NUM_VECTORS > 284
+ .weak vector284, vector285, vector286, vector287
+#endif
+#if PPC_NUM_VECTORS > 288
+ .weak vector288, vector289, vector290, vector291
+#endif
+#if PPC_NUM_VECTORS > 292
+ .weak vector292, vector293, vector294, vector295
+#endif
+#if PPC_NUM_VECTORS > 296
+ .weak vector296, vector297, vector298, vector299
+#endif
+#if PPC_NUM_VECTORS > 300
+ .weak vector300, vector301, vector302, vector303
+#endif
+#if PPC_NUM_VECTORS > 304
+ .weak vector304, vector305, vector306, vector307
+#endif
+#if PPC_NUM_VECTORS > 308
+ .weak vector308, vector309, vector310, vector311
+#endif
+#if PPC_NUM_VECTORS > 312
+ .weak vector312, vector313, vector314, vector315
+#endif
+#if PPC_NUM_VECTORS > 316
+ .weak vector316, vector317, vector318, vector319
+#endif
+#if PPC_NUM_VECTORS > 320
+ .weak vector320, vector321, vector322, vector323
+#endif
+#if PPC_NUM_VECTORS > 324
+ .weak vector324, vector325, vector326, vector327
+#endif
+#if PPC_NUM_VECTORS > 328
+ .weak vector328, vector329, vector330, vector331
+#endif
+#if PPC_NUM_VECTORS > 332
+ .weak vector332, vector333, vector334, vector335
+#endif
+#if PPC_NUM_VECTORS > 336
+ .weak vector336, vector337, vector338, vector339
+#endif
+#if PPC_NUM_VECTORS > 340
+ .weak vector340, vector341, vector342, vector343
+#endif
+#if PPC_NUM_VECTORS > 344
+ .weak vector344, vector345, vector346, vector347
+#endif
+#if PPC_NUM_VECTORS > 348
+ .weak vector348, vector349, vector350, vector351
+#endif
+#if PPC_NUM_VECTORS > 352
+ .weak vector352, vector353, vector354, vector355
+#endif
+#if PPC_NUM_VECTORS > 356
+ .weak vector356, vector357, vector358, vector359
+#endif
+#if PPC_NUM_VECTORS > 360
+ .weak vector360, vector361, vector362, vector363
+#endif
+#if PPC_NUM_VECTORS > 364
+ .weak vector364, vector365, vector366, vector367
+#endif
+#if PPC_NUM_VECTORS > 368
+ .weak vector368, vector369, vector370, vector371
+#endif
+#if PPC_NUM_VECTORS > 372
+ .weak vector372, vector373, vector374, vector375
+#endif
+#if PPC_NUM_VECTORS > 376
+ .weak vector376, vector377, vector378, vector379
+#endif
+#if PPC_NUM_VECTORS > 380
+ .weak vector380, vector381, vector382, vector383
+#endif
+#if PPC_NUM_VECTORS > 384
+ .weak vector384, vector385, vector386, vector387
+#endif
+#if PPC_NUM_VECTORS > 388
+ .weak vector388, vector389, vector390, vector391
+#endif
+#if PPC_NUM_VECTORS > 392
+ .weak vector392, vector393, vector394, vector395
+#endif
+#if PPC_NUM_VECTORS > 396
+ .weak vector396, vector397, vector398, vector399
+#endif
+#if PPC_NUM_VECTORS > 400
+ .weak vector400, vector401, vector402, vector403
+#endif
+#if PPC_NUM_VECTORS > 404
+ .weak vector404, vector405, vector406, vector407
+#endif
+#if PPC_NUM_VECTORS > 408
+ .weak vector408, vector409, vector410, vector411
+#endif
+#if PPC_NUM_VECTORS > 412
+ .weak vector412, vector413, vector414, vector415
+#endif
+#if PPC_NUM_VECTORS > 416
+ .weak vector416, vector417, vector418, vector419
+#endif
+#if PPC_NUM_VECTORS > 420
+ .weak vector420, vector421, vector422, vector423
+#endif
+#if PPC_NUM_VECTORS > 424
+ .weak vector424, vector425, vector426, vector427
+#endif
+#if PPC_NUM_VECTORS > 428
+ .weak vector428, vector429, vector430, vector431
+#endif
+#if PPC_NUM_VECTORS > 432
+ .weak vector432, vector433, vector434, vector435
+#endif
+#if PPC_NUM_VECTORS > 436
+ .weak vector436, vector437, vector438, vector439
+#endif
+#if PPC_NUM_VECTORS > 440
+ .weak vector440, vector441, vector442, vector443
+#endif
+#if PPC_NUM_VECTORS > 444
+ .weak vector444, vector445, vector446, vector447
+#endif
+#if PPC_NUM_VECTORS > 448
+ .weak vector448, vector449, vector450, vector451
+#endif
+#if PPC_NUM_VECTORS > 452
+ .weak vector452, vector453, vector454, vector455
+#endif
+#if PPC_NUM_VECTORS > 456
+ .weak vector456, vector457, vector458, vector459
+#endif
+#if PPC_NUM_VECTORS > 460
+ .weak vector460, vector461, vector462, vector463
+#endif
+#if PPC_NUM_VECTORS > 464
+ .weak vector464, vector465, vector466, vector467
+#endif
+#if PPC_NUM_VECTORS > 468
+ .weak vector468, vector469, vector470, vector471
+#endif
+#if PPC_NUM_VECTORS > 472
+ .weak vector472, vector473, vector474, vector475
+#endif
+#if PPC_NUM_VECTORS > 476
+ .weak vector476, vector477, vector478, vector479
+#endif
+#if PPC_NUM_VECTORS > 480
+ .weak vector480, vector481, vector482, vector483
+#endif
+#if PPC_NUM_VECTORS > 484
+ .weak vector484, vector485, vector486, vector487
+#endif
+#if PPC_NUM_VECTORS > 488
+ .weak vector488, vector489, vector490, vector491
+#endif
+#if PPC_NUM_VECTORS > 492
+ .weak vector492, vector493, vector494, vector495
+#endif
+#if PPC_NUM_VECTORS > 496
+ .weak vector496, vector497, vector498, vector499
+#endif
+#if PPC_NUM_VECTORS > 500
+ .weak vector500, vector501, vector502, vector503
+#endif
+#if PPC_NUM_VECTORS > 504
+ .weak vector504, vector505, vector506, vector507
+#endif
+#if PPC_NUM_VECTORS > 508
+ .weak vector508, vector509, vector510, vector511
+#endif
+#if PPC_NUM_VECTORS > 512
+ .weak vector512, vector513, vector514, vector515
+#endif
+#if PPC_NUM_VECTORS > 516
+ .weak vector516, vector517, vector518, vector519
+#endif
+#if PPC_NUM_VECTORS > 520
+ .weak vector520, vector521, vector522, vector523
+#endif
+#if PPC_NUM_VECTORS > 524
+ .weak vector524, vector525, vector526, vector527
+#endif
+#if PPC_NUM_VECTORS > 528
+ .weak vector528, vector529, vector530, vector531
+#endif
+#if PPC_NUM_VECTORS > 532
+ .weak vector532, vector533, vector534, vector535
+#endif
+#if PPC_NUM_VECTORS > 536
+ .weak vector536, vector537, vector538, vector539
+#endif
+#if PPC_NUM_VECTORS > 540
+ .weak vector540, vector541, vector542, vector543
+#endif
+#if PPC_NUM_VECTORS > 544
+ .weak vector544, vector545, vector546, vector547
+#endif
+#if PPC_NUM_VECTORS > 548
+ .weak vector548, vector549, vector550, vector551
+#endif
+#if PPC_NUM_VECTORS > 552
+ .weak vector552, vector553, vector554, vector555
+#endif
+#if PPC_NUM_VECTORS > 556
+ .weak vector556, vector557, vector558, vector559
+#endif
+#if PPC_NUM_VECTORS > 560
+ .weak vector560, vector561, vector562, vector563
+#endif
+#if PPC_NUM_VECTORS > 564
+ .weak vector564, vector565, vector566, vector567
+#endif
+#if PPC_NUM_VECTORS > 568
+ .weak vector568, vector569, vector570, vector571
+#endif
+#if PPC_NUM_VECTORS > 572
+ .weak vector572, vector573, vector574, vector575
+#endif
+#if PPC_NUM_VECTORS > 576
+ .weak vector576, vector577, vector578, vector579
+#endif
+#if PPC_NUM_VECTORS > 580
+ .weak vector580, vector581, vector582, vector583
+#endif
+#if PPC_NUM_VECTORS > 584
+ .weak vector584, vector585, vector586, vector587
+#endif
+#if PPC_NUM_VECTORS > 588
+ .weak vector588, vector589, vector590, vector591
+#endif
+#if PPC_NUM_VECTORS > 592
+ .weak vector592, vector593, vector594, vector595
+#endif
+#if PPC_NUM_VECTORS > 596
+ .weak vector596, vector597, vector598, vector599
+#endif
+#if PPC_NUM_VECTORS > 600
+ .weak vector600, vector601, vector602, vector603
+#endif
+#if PPC_NUM_VECTORS > 604
+ .weak vector604, vector605, vector606, vector607
+#endif
+#if PPC_NUM_VECTORS > 608
+ .weak vector608, vector609, vector610, vector611
+#endif
+#if PPC_NUM_VECTORS > 612
+ .weak vector612, vector613, vector614, vector615
+#endif
+#if PPC_NUM_VECTORS > 616
+ .weak vector616, vector617, vector618, vector619
+#endif
+#if PPC_NUM_VECTORS > 620
+ .weak vector620, vector621, vector622, vector623
+#endif
+#if PPC_NUM_VECTORS > 624
+ .weak vector624, vector625, vector626, vector627
+#endif
+#if PPC_NUM_VECTORS > 628
+ .weak vector628, vector629, vector630, vector631
+#endif
+#if PPC_NUM_VECTORS > 632
+ .weak vector632, vector633, vector634, vector635
+#endif
+#if PPC_NUM_VECTORS > 636
+ .weak vector636, vector637, vector638, vector639
+#endif
+#if PPC_NUM_VECTORS > 640
+ .weak vector640, vector641, vector642, vector643
+#endif
+#if PPC_NUM_VECTORS > 644
+ .weak vector644, vector645, vector646, vector647
+#endif
+#if PPC_NUM_VECTORS > 648
+ .weak vector648, vector649, vector650, vector651
+#endif
+#if PPC_NUM_VECTORS > 652
+ .weak vector652, vector653, vector654, vector655
+#endif
+#if PPC_NUM_VECTORS > 656
+ .weak vector656, vector657, vector658, vector659
+#endif
+#if PPC_NUM_VECTORS > 660
+ .weak vector660, vector661, vector662, vector663
+#endif
+#if PPC_NUM_VECTORS > 664
+ .weak vector664, vector665, vector666, vector667
+#endif
+#if PPC_NUM_VECTORS > 668
+ .weak vector668, vector669, vector670, vector671
+#endif
+#if PPC_NUM_VECTORS > 672
+ .weak vector672, vector673, vector674, vector675
+#endif
+#if PPC_NUM_VECTORS > 676
+ .weak vector676, vector677, vector678, vector679
+#endif
+#if PPC_NUM_VECTORS > 680
+ .weak vector680, vector681, vector682, vector683
+#endif
+#if PPC_NUM_VECTORS > 684
+ .weak vector684, vector685, vector686, vector687
+#endif
+#if PPC_NUM_VECTORS > 688
+ .weak vector688, vector689, vector690, vector691
+#endif
+#if PPC_NUM_VECTORS > 692
+ .weak vector692, vector693, vector694, vector695
+#endif
+#if PPC_NUM_VECTORS > 696
+ .weak vector696, vector697, vector698, vector699
+#endif
+#if PPC_NUM_VECTORS > 700
+ .weak vector700, vector701, vector702, vector703
+#endif
+#if PPC_NUM_VECTORS > 704
+ .weak vector704, vector705, vector706, vector707
+#endif
+#if PPC_NUM_VECTORS > 708
+ .weak vector708, vector709, vector710, vector711
+#endif
+#if PPC_NUM_VECTORS > 712
+ .weak vector712, vector713, vector714, vector715
+#endif
+#if PPC_NUM_VECTORS > 716
+ .weak vector716, vector717, vector718, vector719
+#endif
+#if PPC_NUM_VECTORS > 720
+ .weak vector720, vector721, vector722, vector723
+#endif
+#if PPC_NUM_VECTORS > 724
+ .weak vector724, vector725, vector726, vector727
+#endif
+#if PPC_NUM_VECTORS > 728
+ .weak vector728, vector729, vector730, vector731
+#endif
+#if PPC_NUM_VECTORS > 732
+ .weak vector732, vector733, vector734, vector735
+#endif
+#if PPC_NUM_VECTORS > 736
+ .weak vector736, vector737, vector738, vector739
+#endif
+#if PPC_NUM_VECTORS > 740
+ .weak vector740, vector741, vector742, vector743
+#endif
+#if PPC_NUM_VECTORS > 744
+ .weak vector744, vector745, vector746, vector747
+#endif
+#if PPC_NUM_VECTORS > 748
+ .weak vector748, vector749, vector750, vector751
+#endif
+#if PPC_NUM_VECTORS > 752
+ .weak vector752, vector753, vector754, vector755
+#endif
+#if PPC_NUM_VECTORS > 756
+ .weak vector756, vector757, vector758, vector759
+#endif
+#if PPC_NUM_VECTORS > 760
+ .weak vector760, vector761, vector762, vector763
+#endif
+#if PPC_NUM_VECTORS > 764
+ .weak vector764, vector765, vector766, vector767
+#endif
+#if PPC_NUM_VECTORS > 768
+ .weak vector768, vector769, vector770, vector771
+#endif
+#if PPC_NUM_VECTORS > 772
+ .weak vector772, vector773, vector774, vector775
+#endif
+#if PPC_NUM_VECTORS > 776
+ .weak vector776, vector777, vector778, vector779
+#endif
+#if PPC_NUM_VECTORS > 780
+ .weak vector780, vector781, vector782, vector783
+#endif
+#if PPC_NUM_VECTORS > 784
+ .weak vector784, vector785, vector786, vector787
+#endif
+#if PPC_NUM_VECTORS > 788
+ .weak vector788, vector789, vector790, vector791
+#endif
+#if PPC_NUM_VECTORS > 792
+ .weak vector792, vector793, vector794, vector795
+#endif
+#if PPC_NUM_VECTORS > 796
+ .weak vector796, vector797, vector798, vector799
+#endif
+#if PPC_NUM_VECTORS > 800
+ .weak vector800, vector801, vector802, vector803
+#endif
+#if PPC_NUM_VECTORS > 804
+ .weak vector804, vector805, vector806, vector807
+#endif
+#if PPC_NUM_VECTORS > 808
+ .weak vector808, vector809, vector810, vector811
+#endif
+#if PPC_NUM_VECTORS > 812
+ .weak vector812, vector813, vector814, vector815
+#endif
+#if PPC_NUM_VECTORS > 816
+ .weak vector816, vector817, vector818, vector819
+#endif
+#if PPC_NUM_VECTORS > 820
+ .weak vector820, vector821, vector822, vector823
+#endif
+#if PPC_NUM_VECTORS > 824
+ .weak vector824, vector825, vector826, vector827
+#endif
+#if PPC_NUM_VECTORS > 828
+ .weak vector828, vector829, vector830, vector831
+#endif
+#if PPC_NUM_VECTORS > 832
+ .weak vector832, vector833, vector834, vector835
+#endif
+#if PPC_NUM_VECTORS > 836
+ .weak vector836, vector837, vector838, vector839
+#endif
+#if PPC_NUM_VECTORS > 840
+ .weak vector840, vector841, vector842, vector843
+#endif
+#if PPC_NUM_VECTORS > 844
+ .weak vector844, vector845, vector846, vector847
+#endif
+#if PPC_NUM_VECTORS > 848
+ .weak vector848, vector849, vector850, vector851
+#endif
+#if PPC_NUM_VECTORS > 852
+ .weak vector852, vector853, vector854, vector855
+#endif
+#if PPC_NUM_VECTORS > 856
+ .weak vector856, vector857, vector858, vector859
+#endif
+#if PPC_NUM_VECTORS > 860
+ .weak vector860, vector861, vector862, vector863
+#endif
+#if PPC_NUM_VECTORS > 864
+ .weak vector864, vector865, vector866, vector867
+#endif
+#if PPC_NUM_VECTORS > 868
+ .weak vector868, vector869, vector870, vector871
+#endif
+#if PPC_NUM_VECTORS > 872
+ .weak vector872, vector873, vector874, vector875
+#endif
+#if PPC_NUM_VECTORS > 876
+ .weak vector876, vector877, vector878, vector879
+#endif
+#if PPC_NUM_VECTORS > 880
+ .weak vector880, vector881, vector882, vector883
+#endif
+#if PPC_NUM_VECTORS > 884
+ .weak vector884, vector885, vector886, vector887
+#endif
+#if PPC_NUM_VECTORS > 888
+ .weak vector888, vector889, vector890, vector891
+#endif
+#if PPC_NUM_VECTORS > 892
+ .weak vector892, vector893, vector894, vector895
+#endif
+#if PPC_NUM_VECTORS > 896
+ .weak vector896, vector897, vector898, vector899
+#endif
+#if PPC_NUM_VECTORS > 900
+ .weak vector900, vector901, vector902, vector903
+#endif
+#if PPC_NUM_VECTORS > 904
+ .weak vector904, vector905, vector906, vector907
+#endif
+#if PPC_NUM_VECTORS > 908
+ .weak vector908, vector909, vector910, vector911
+#endif
+#if PPC_NUM_VECTORS > 912
+ .weak vector912, vector913, vector914, vector915
+#endif
+#if PPC_NUM_VECTORS > 916
+ .weak vector916, vector917, vector918, vector919
+#endif
+#if PPC_NUM_VECTORS > 920
+ .weak vector920, vector921, vector922, vector923
+#endif
+#if PPC_NUM_VECTORS > 924
+ .weak vector924, vector925, vector926, vector927
+#endif
+#if PPC_NUM_VECTORS > 928
+ .weak vector928, vector929, vector930, vector931
+#endif
+#if PPC_NUM_VECTORS > 932
+ .weak vector932, vector933, vector934, vector935
+#endif
+#if PPC_NUM_VECTORS > 936
+ .weak vector936, vector937, vector938, vector939
+#endif
+#if PPC_NUM_VECTORS > 940
+ .weak vector940, vector941, vector942, vector943
+#endif
+#if PPC_NUM_VECTORS > 944
+ .weak vector944, vector945, vector946, vector947
+#endif
+#if PPC_NUM_VECTORS > 948
+ .weak vector948, vector949, vector950, vector951
+#endif
+#if PPC_NUM_VECTORS > 952
+ .weak vector952, vector953, vector954, vector955
+#endif
+#if PPC_NUM_VECTORS > 956
+ .weak vector956, vector957, vector958, vector959
+#endif
+#if PPC_NUM_VECTORS > 960
+ .weak vector960, vector961, vector962, vector963
+#endif
+#if PPC_NUM_VECTORS > 964
+ .weak vector964, vector965, vector966, vector967
+#endif
+#if PPC_NUM_VECTORS > 968
+ .weak vector968, vector969, vector970, vector971
+#endif
+#if PPC_NUM_VECTORS > 972
+ .weak vector972, vector973, vector974, vector975
+#endif
+#if PPC_NUM_VECTORS > 976
+ .weak vector976, vector977, vector978, vector979
+#endif
+#if PPC_NUM_VECTORS > 980
+ .weak vector980, vector981, vector982, vector983
+#endif
+#if PPC_NUM_VECTORS > 984
+ .weak vector984, vector985, vector986, vector987
+#endif
+#if PPC_NUM_VECTORS > 988
+ .weak vector988, vector989, vector990, vector991
+#endif
+#if PPC_NUM_VECTORS > 992
+ .weak vector992, vector993, vector994, vector995
+#endif
+#if PPC_NUM_VECTORS > 996
+ .weak vector996, vector997, vector998, vector999
+#endif
+#if PPC_NUM_VECTORS > 1000
+ .weak vector1000, vector1001, vector1002, vector1003
+#endif
+#if PPC_NUM_VECTORS > 1004
+ .weak vector1004, vector1005, vector1006, vector1007
+#endif
+#if PPC_NUM_VECTORS > 1008
+ .weak vector1008, vector1009, vector1010, vector1011
+#endif
+#if PPC_NUM_VECTORS > 1012
+ .weak vector1012, vector1013, vector1014, vector1015
+#endif
+#if PPC_NUM_VECTORS > 1016
+ .weak vector1016, vector1017, vector1018, vector1019
+#endif
+#if PPC_NUM_VECTORS > 1020
+ .weak vector1020, vector1021, vector1022, vector1023
+#endif
+
+vector0:
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+vector569:
+vector570:
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+vector615:
+vector616:
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+vector619:
+vector620:
+vector621:
+vector622:
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+vector624:
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+vector628:
+vector629:
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+vector714:
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+vector718:
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+vector720:
+vector721:
+vector722:
+vector723:
+vector724:
+vector725:
+vector726:
+vector727:
+vector728:
+vector729:
+vector730:
+vector731:
+vector732:
+vector733:
+vector734:
+vector735:
+vector736:
+vector737:
+vector738:
+vector739:
+vector740:
+vector741:
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+vector743:
+vector744:
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+vector747:
+vector748:
+vector749:
+vector750:
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+vector796:
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+vector798:
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+vector800:
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+vector811:
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+vector816:
+vector817:
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+vector820:
+vector821:
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+vector824:
+vector825:
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+vector830:
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+vector832:
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+vector834:
+vector835:
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+vector837:
+vector838:
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+vector860:
+vector861:
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+vector863:
+vector864:
+vector865:
+vector866:
+vector867:
+vector868:
+vector869:
+vector870:
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+vector873:
+vector874:
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+vector877:
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+vector880:
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+vector882:
+vector883:
+vector884:
+vector885:
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+vector887:
+vector888:
+vector889:
+vector890:
+vector891:
+vector892:
+vector893:
+vector894:
+vector895:
+vector896:
+vector897:
+vector898:
+vector899:
+vector900:
+vector901:
+vector902:
+vector903:
+vector904:
+vector905:
+vector906:
+vector907:
+vector908:
+vector909:
+vector910:
+vector911:
+vector912:
+vector913:
+vector914:
+vector915:
+vector916:
+vector917:
+vector918:
+vector919:
+vector920:
+vector921:
+vector922:
+vector923:
+vector924:
+vector925:
+vector926:
+vector927:
+vector928:
+vector929:
+vector930:
+vector931:
+vector932:
+vector933:
+vector934:
+vector935:
+vector936:
+vector937:
+vector938:
+vector939:
+vector940:
+vector941:
+vector942:
+vector943:
+vector944:
+vector945:
+vector946:
+vector947:
+vector948:
+vector949:
+vector950:
+vector951:
+vector952:
+vector953:
+vector954:
+vector955:
+vector956:
+vector957:
+vector958:
+vector959:
+vector960:
+vector961:
+vector962:
+vector963:
+vector964:
+vector965:
+vector966:
+vector967:
+vector968:
+vector969:
+vector970:
+vector971:
+vector972:
+vector973:
+vector974:
+vector975:
+vector976:
+vector977:
+vector978:
+vector979:
+vector980:
+vector981:
+vector982:
+vector983:
+vector984:
+vector985:
+vector986:
+vector987:
+vector988:
+vector989:
+vector990:
+vector991:
+vector992:
+vector993:
+vector994:
+vector995:
+vector996:
+vector997:
+vector998:
+vector999:
+vector1000:
+vector1001:
+vector1002:
+vector1003:
+vector1004:
+vector1005:
+vector1006:
+vector1007:
+vector1008:
+vector1009:
+vector1010:
+vector1011:
+vector1012:
+vector1013:
+vector1014:
+vector1015:
+vector1016:
+vector1017:
+vector1018:
+vector1019:
+vector1020:
+vector1021:
+vector1022:
+vector1023:
+
+ .global _unhandled_irq
+_unhandled_irq:
+ se_b _unhandled_irq
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/CW/vectors.h b/ChibiOS_20.3.2/os/common/startup/e200/compilers/CW/vectors.h new file mode 100644 index 0000000..4ef2993 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/CW/vectors.h @@ -0,0 +1,78 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file vectors.h
+ * @brief ISR vector module header.
+ *
+ * @addtogroup PPC_CW_CORE
+ * @{
+ */
+
+#ifndef VECTORS_H
+#define VECTORS_H
+
+#include "ppcparams.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+#if !defined(__DOXYGEN__)
+extern uint32_t _vectors[PPC_NUM_VECTORS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _unhandled_irq(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* VECTORS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/CW/vectors.s b/ChibiOS_20.3.2/os/common/startup/e200/compilers/CW/vectors.s new file mode 100644 index 0000000..43dcbfc --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/CW/vectors.s @@ -0,0 +1,1577 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file vectors.s
+ * @brief SPC56x vectors table.
+ *
+ * @addtogroup PPC_CW_CORE
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "ppcparams.h"
+
+#if defined(VECTORS_RENAMING)
+#include "isrs.h"
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ .global vector0, vector1, vector2, vector3
+#if PPC_NUM_VECTORS > 4
+ .global vector4, vector5, vector6, vector7
+#endif
+#if PPC_NUM_VECTORS > 8
+ .global vector8, vector9, vector10, vector11
+#endif
+#if PPC_NUM_VECTORS > 12
+ .global vector12, vector13, vector14, vector15
+#endif
+#if PPC_NUM_VECTORS > 16
+ .global vector16, vector17, vector18, vector19
+#endif
+#if PPC_NUM_VECTORS > 20
+ .global vector20, vector21, vector22, vector23
+#endif
+#if PPC_NUM_VECTORS > 24
+ .global vector24, vector25, vector26, vector27
+#endif
+#if PPC_NUM_VECTORS > 28
+ .global vector28, vector29, vector30, vector31
+#endif
+#if PPC_NUM_VECTORS > 32
+ .global vector32, vector33, vector34, vector35
+#endif
+#if PPC_NUM_VECTORS > 36
+ .global vector36, vector37, vector38, vector39
+#endif
+#if PPC_NUM_VECTORS > 40
+ .global vector40, vector41, vector42, vector43
+#endif
+#if PPC_NUM_VECTORS > 44
+ .global vector44, vector45, vector46, vector47
+#endif
+#if PPC_NUM_VECTORS > 48
+ .global vector48, vector49, vector50, vector51
+#endif
+#if PPC_NUM_VECTORS > 52
+ .global vector52, vector53, vector54, vector55
+#endif
+#if PPC_NUM_VECTORS > 56
+ .global vector56, vector57, vector58, vector59
+#endif
+#if PPC_NUM_VECTORS > 60
+ .global vector60, vector61, vector62, vector63
+#endif
+#if PPC_NUM_VECTORS > 64
+ .global vector64, vector65, vector66, vector67
+#endif
+#if PPC_NUM_VECTORS > 68
+ .global vector68, vector69, vector70, vector71
+#endif
+#if PPC_NUM_VECTORS > 72
+ .global vector72, vector73, vector74, vector75
+#endif
+#if PPC_NUM_VECTORS > 76
+ .global vector76, vector77, vector78, vector79
+#endif
+#if PPC_NUM_VECTORS > 80
+ .global vector80, vector81, vector82, vector83
+#endif
+#if PPC_NUM_VECTORS > 84
+ .global vector84, vector85, vector86, vector87
+#endif
+#if PPC_NUM_VECTORS > 88
+ .global vector88, vector89, vector90, vector91
+#endif
+#if PPC_NUM_VECTORS > 92
+ .global vector92, vector93, vector94, vector95
+#endif
+#if PPC_NUM_VECTORS > 96
+ .global vector96, vector97, vector98, vector99
+#endif
+#if PPC_NUM_VECTORS > 100
+ .global vector100, vector101, vector102, vector103
+#endif
+#if PPC_NUM_VECTORS > 104
+ .global vector104, vector105, vector106, vector107
+#endif
+#if PPC_NUM_VECTORS > 108
+ .global vector108, vector109, vector110, vector111
+#endif
+#if PPC_NUM_VECTORS > 112
+ .global vector112, vector113, vector114, vector115
+#endif
+#if PPC_NUM_VECTORS > 116
+ .global vector116, vector117, vector118, vector119
+#endif
+#if PPC_NUM_VECTORS > 120
+ .global vector120, vector121, vector122, vector123
+#endif
+#if PPC_NUM_VECTORS > 124
+ .global vector124, vector125, vector126, vector127
+#endif
+#if PPC_NUM_VECTORS > 128
+ .global vector128, vector129, vector130, vector131
+#endif
+#if PPC_NUM_VECTORS > 132
+ .global vector132, vector133, vector134, vector135
+#endif
+#if PPC_NUM_VECTORS > 136
+ .global vector136, vector137, vector138, vector139
+#endif
+#if PPC_NUM_VECTORS > 140
+ .global vector140, vector141, vector142, vector143
+#endif
+#if PPC_NUM_VECTORS > 144
+ .global vector144, vector145, vector146, vector147
+#endif
+#if PPC_NUM_VECTORS > 148
+ .global vector148, vector149, vector150, vector151
+#endif
+#if PPC_NUM_VECTORS > 152
+ .global vector152, vector153, vector154, vector155
+#endif
+#if PPC_NUM_VECTORS > 156
+ .global vector156, vector157, vector158, vector159
+#endif
+#if PPC_NUM_VECTORS > 160
+ .global vector160, vector161, vector162, vector163
+#endif
+#if PPC_NUM_VECTORS > 164
+ .global vector164, vector165, vector166, vector167
+#endif
+#if PPC_NUM_VECTORS > 168
+ .global vector168, vector169, vector170, vector171
+#endif
+#if PPC_NUM_VECTORS > 172
+ .global vector172, vector173, vector174, vector175
+#endif
+#if PPC_NUM_VECTORS > 176
+ .global vector176, vector177, vector178, vector179
+#endif
+#if PPC_NUM_VECTORS > 180
+ .global vector180, vector181, vector182, vector183
+#endif
+#if PPC_NUM_VECTORS > 184
+ .global vector184, vector185, vector186, vector187
+#endif
+#if PPC_NUM_VECTORS > 188
+ .global vector188, vector189, vector190, vector191
+#endif
+#if PPC_NUM_VECTORS > 192
+ .global vector192, vector193, vector194, vector195
+#endif
+#if PPC_NUM_VECTORS > 196
+ .global vector196, vector197, vector198, vector199
+#endif
+#if PPC_NUM_VECTORS > 200
+ .global vector200, vector201, vector202, vector203
+#endif
+#if PPC_NUM_VECTORS > 204
+ .global vector204, vector205, vector206, vector207
+#endif
+#if PPC_NUM_VECTORS > 208
+ .global vector208, vector209, vector210, vector211
+#endif
+#if PPC_NUM_VECTORS > 212
+ .global vector212, vector213, vector214, vector215
+#endif
+#if PPC_NUM_VECTORS > 216
+ .global vector216, vector217, vector218, vector219
+#endif
+#if PPC_NUM_VECTORS > 220
+ .global vector220, vector221, vector222, vector223
+#endif
+#if PPC_NUM_VECTORS > 224
+ .global vector224, vector225, vector226, vector227
+#endif
+#if PPC_NUM_VECTORS > 228
+ .global vector228, vector229, vector230, vector231
+#endif
+#if PPC_NUM_VECTORS > 232
+ .global vector232, vector233, vector234, vector235
+#endif
+#if PPC_NUM_VECTORS > 236
+ .global vector236, vector237, vector238, vector239
+#endif
+#if PPC_NUM_VECTORS > 240
+ .global vector240, vector241, vector242, vector243
+#endif
+#if PPC_NUM_VECTORS > 244
+ .global vector244, vector245, vector246, vector247
+#endif
+#if PPC_NUM_VECTORS > 248
+ .global vector248, vector249, vector250, vector251
+#endif
+#if PPC_NUM_VECTORS > 252
+ .global vector252, vector253, vector254, vector255
+#endif
+#if PPC_NUM_VECTORS > 256
+ .global vector256, vector257, vector258, vector259
+#endif
+#if PPC_NUM_VECTORS > 260
+ .global vector260, vector261, vector262, vector263
+#endif
+#if PPC_NUM_VECTORS > 264
+ .global vector264, vector265, vector266, vector267
+#endif
+#if PPC_NUM_VECTORS > 268
+ .global vector268, vector269, vector270, vector271
+#endif
+#if PPC_NUM_VECTORS > 272
+ .global vector272, vector273, vector274, vector275
+#endif
+#if PPC_NUM_VECTORS > 276
+ .global vector276, vector277, vector278, vector279
+#endif
+#if PPC_NUM_VECTORS > 280
+ .global vector280, vector281, vector282, vector283
+#endif
+#if PPC_NUM_VECTORS > 284
+ .global vector284, vector285, vector286, vector287
+#endif
+#if PPC_NUM_VECTORS > 288
+ .global vector288, vector289, vector290, vector291
+#endif
+#if PPC_NUM_VECTORS > 292
+ .global vector292, vector293, vector294, vector295
+#endif
+#if PPC_NUM_VECTORS > 296
+ .global vector296, vector297, vector298, vector299
+#endif
+#if PPC_NUM_VECTORS > 300
+ .global vector300, vector301, vector302, vector303
+#endif
+#if PPC_NUM_VECTORS > 304
+ .global vector304, vector305, vector306, vector307
+#endif
+#if PPC_NUM_VECTORS > 308
+ .global vector308, vector309, vector310, vector311
+#endif
+#if PPC_NUM_VECTORS > 312
+ .global vector312, vector313, vector314, vector315
+#endif
+#if PPC_NUM_VECTORS > 316
+ .global vector316, vector317, vector318, vector319
+#endif
+#if PPC_NUM_VECTORS > 320
+ .global vector320, vector321, vector322, vector323
+#endif
+#if PPC_NUM_VECTORS > 324
+ .global vector324, vector325, vector326, vector327
+#endif
+#if PPC_NUM_VECTORS > 328
+ .global vector328, vector329, vector330, vector331
+#endif
+#if PPC_NUM_VECTORS > 332
+ .global vector332, vector333, vector334, vector335
+#endif
+#if PPC_NUM_VECTORS > 336
+ .global vector336, vector337, vector338, vector339
+#endif
+#if PPC_NUM_VECTORS > 340
+ .global vector340, vector341, vector342, vector343
+#endif
+#if PPC_NUM_VECTORS > 344
+ .global vector344, vector345, vector346, vector347
+#endif
+#if PPC_NUM_VECTORS > 348
+ .global vector348, vector349, vector350, vector351
+#endif
+#if PPC_NUM_VECTORS > 352
+ .global vector352, vector353, vector354, vector355
+#endif
+#if PPC_NUM_VECTORS > 356
+ .global vector356, vector357, vector358, vector359
+#endif
+#if PPC_NUM_VECTORS > 360
+ .global vector360, vector361, vector362, vector363
+#endif
+#if PPC_NUM_VECTORS > 364
+ .global vector364, vector365, vector366, vector367
+#endif
+#if PPC_NUM_VECTORS > 368
+ .global vector368, vector369, vector370, vector371
+#endif
+#if PPC_NUM_VECTORS > 372
+ .global vector372, vector373, vector374, vector375
+#endif
+#if PPC_NUM_VECTORS > 376
+ .global vector376, vector377, vector378, vector379
+#endif
+#if PPC_NUM_VECTORS > 380
+ .global vector380, vector381, vector382, vector383
+#endif
+#if PPC_NUM_VECTORS > 384
+ .global vector384, vector385, vector386, vector387
+#endif
+#if PPC_NUM_VECTORS > 388
+ .global vector388, vector389, vector390, vector391
+#endif
+#if PPC_NUM_VECTORS > 392
+ .global vector392, vector393, vector394, vector395
+#endif
+#if PPC_NUM_VECTORS > 396
+ .global vector396, vector397, vector398, vector399
+#endif
+#if PPC_NUM_VECTORS > 400
+ .global vector400, vector401, vector402, vector403
+#endif
+#if PPC_NUM_VECTORS > 404
+ .global vector404, vector405, vector406, vector407
+#endif
+#if PPC_NUM_VECTORS > 408
+ .global vector408, vector409, vector410, vector411
+#endif
+#if PPC_NUM_VECTORS > 412
+ .global vector412, vector413, vector414, vector415
+#endif
+#if PPC_NUM_VECTORS > 416
+ .global vector416, vector417, vector418, vector419
+#endif
+#if PPC_NUM_VECTORS > 420
+ .global vector420, vector421, vector422, vector423
+#endif
+#if PPC_NUM_VECTORS > 424
+ .global vector424, vector425, vector426, vector427
+#endif
+#if PPC_NUM_VECTORS > 428
+ .global vector428, vector429, vector430, vector431
+#endif
+#if PPC_NUM_VECTORS > 432
+ .global vector432, vector433, vector434, vector435
+#endif
+#if PPC_NUM_VECTORS > 436
+ .global vector436, vector437, vector438, vector439
+#endif
+#if PPC_NUM_VECTORS > 440
+ .global vector440, vector441, vector442, vector443
+#endif
+#if PPC_NUM_VECTORS > 444
+ .global vector444, vector445, vector446, vector447
+#endif
+#if PPC_NUM_VECTORS > 448
+ .global vector448, vector449, vector450, vector451
+#endif
+#if PPC_NUM_VECTORS > 452
+ .global vector452, vector453, vector454, vector455
+#endif
+#if PPC_NUM_VECTORS > 456
+ .global vector456, vector457, vector458, vector459
+#endif
+#if PPC_NUM_VECTORS > 460
+ .global vector460, vector461, vector462, vector463
+#endif
+#if PPC_NUM_VECTORS > 464
+ .global vector464, vector465, vector466, vector467
+#endif
+#if PPC_NUM_VECTORS > 468
+ .global vector468, vector469, vector470, vector471
+#endif
+#if PPC_NUM_VECTORS > 472
+ .global vector472, vector473, vector474, vector475
+#endif
+#if PPC_NUM_VECTORS > 476
+ .global vector476, vector477, vector478, vector479
+#endif
+#if PPC_NUM_VECTORS > 480
+ .global vector480, vector481, vector482, vector483
+#endif
+#if PPC_NUM_VECTORS > 484
+ .global vector484, vector485, vector486, vector487
+#endif
+#if PPC_NUM_VECTORS > 488
+ .global vector488, vector489, vector490, vector491
+#endif
+#if PPC_NUM_VECTORS > 492
+ .global vector492, vector493, vector494, vector495
+#endif
+#if PPC_NUM_VECTORS > 496
+ .global vector496, vector497, vector498, vector499
+#endif
+#if PPC_NUM_VECTORS > 500
+ .global vector500, vector501, vector502, vector503
+#endif
+#if PPC_NUM_VECTORS > 504
+ .global vector504, vector505, vector506, vector507
+#endif
+#if PPC_NUM_VECTORS > 508
+ .global vector508, vector509, vector510, vector511
+#endif
+#if PPC_NUM_VECTORS > 512
+ .global vector512, vector513, vector514, vector515
+#endif
+#if PPC_NUM_VECTORS > 516
+ .global vector516, vector517, vector518, vector519
+#endif
+#if PPC_NUM_VECTORS > 520
+ .global vector520, vector521, vector522, vector523
+#endif
+#if PPC_NUM_VECTORS > 524
+ .global vector524, vector525, vector526, vector527
+#endif
+#if PPC_NUM_VECTORS > 528
+ .global vector528, vector529, vector530, vector531
+#endif
+#if PPC_NUM_VECTORS > 532
+ .global vector532, vector533, vector534, vector535
+#endif
+#if PPC_NUM_VECTORS > 536
+ .global vector536, vector537, vector538, vector539
+#endif
+#if PPC_NUM_VECTORS > 540
+ .global vector540, vector541, vector542, vector543
+#endif
+#if PPC_NUM_VECTORS > 544
+ .global vector544, vector545, vector546, vector547
+#endif
+#if PPC_NUM_VECTORS > 548
+ .global vector548, vector549, vector550, vector551
+#endif
+#if PPC_NUM_VECTORS > 552
+ .global vector552, vector553, vector554, vector555
+#endif
+#if PPC_NUM_VECTORS > 556
+ .global vector556, vector557, vector558, vector559
+#endif
+#if PPC_NUM_VECTORS > 560
+ .global vector560, vector561, vector562, vector563
+#endif
+#if PPC_NUM_VECTORS > 564
+ .global vector564, vector565, vector566, vector567
+#endif
+#if PPC_NUM_VECTORS > 568
+ .global vector568, vector569, vector570, vector571
+#endif
+#if PPC_NUM_VECTORS > 572
+ .global vector572, vector573, vector574, vector575
+#endif
+#if PPC_NUM_VECTORS > 576
+ .global vector576, vector577, vector578, vector579
+#endif
+#if PPC_NUM_VECTORS > 580
+ .global vector580, vector581, vector582, vector583
+#endif
+#if PPC_NUM_VECTORS > 584
+ .global vector584, vector585, vector586, vector587
+#endif
+#if PPC_NUM_VECTORS > 588
+ .global vector588, vector589, vector590, vector591
+#endif
+#if PPC_NUM_VECTORS > 592
+ .global vector592, vector593, vector594, vector595
+#endif
+#if PPC_NUM_VECTORS > 596
+ .global vector596, vector597, vector598, vector599
+#endif
+#if PPC_NUM_VECTORS > 600
+ .global vector600, vector601, vector602, vector603
+#endif
+#if PPC_NUM_VECTORS > 604
+ .global vector604, vector605, vector606, vector607
+#endif
+#if PPC_NUM_VECTORS > 608
+ .global vector608, vector609, vector610, vector611
+#endif
+#if PPC_NUM_VECTORS > 612
+ .global vector612, vector613, vector614, vector615
+#endif
+#if PPC_NUM_VECTORS > 616
+ .global vector616, vector617, vector618, vector619
+#endif
+#if PPC_NUM_VECTORS > 620
+ .global vector620, vector621, vector622, vector623
+#endif
+#if PPC_NUM_VECTORS > 624
+ .global vector624, vector625, vector626, vector627
+#endif
+#if PPC_NUM_VECTORS > 628
+ .global vector628, vector629, vector630, vector631
+#endif
+#if PPC_NUM_VECTORS > 632
+ .global vector632, vector633, vector634, vector635
+#endif
+#if PPC_NUM_VECTORS > 636
+ .global vector636, vector637, vector638, vector639
+#endif
+#if PPC_NUM_VECTORS > 640
+ .global vector640, vector641, vector642, vector643
+#endif
+#if PPC_NUM_VECTORS > 644
+ .global vector644, vector645, vector646, vector647
+#endif
+#if PPC_NUM_VECTORS > 648
+ .global vector648, vector649, vector650, vector651
+#endif
+#if PPC_NUM_VECTORS > 652
+ .global vector652, vector653, vector654, vector655
+#endif
+#if PPC_NUM_VECTORS > 656
+ .global vector656, vector657, vector658, vector659
+#endif
+#if PPC_NUM_VECTORS > 660
+ .global vector660, vector661, vector662, vector663
+#endif
+#if PPC_NUM_VECTORS > 664
+ .global vector664, vector665, vector666, vector667
+#endif
+#if PPC_NUM_VECTORS > 668
+ .global vector668, vector669, vector670, vector671
+#endif
+#if PPC_NUM_VECTORS > 672
+ .global vector672, vector673, vector674, vector675
+#endif
+#if PPC_NUM_VECTORS > 676
+ .global vector676, vector677, vector678, vector679
+#endif
+#if PPC_NUM_VECTORS > 680
+ .global vector680, vector681, vector682, vector683
+#endif
+#if PPC_NUM_VECTORS > 684
+ .global vector684, vector685, vector686, vector687
+#endif
+#if PPC_NUM_VECTORS > 688
+ .global vector688, vector689, vector690, vector691
+#endif
+#if PPC_NUM_VECTORS > 692
+ .global vector692, vector693, vector694, vector695
+#endif
+#if PPC_NUM_VECTORS > 696
+ .global vector696, vector697, vector698, vector699
+#endif
+#if PPC_NUM_VECTORS > 700
+ .global vector700, vector701, vector702, vector703
+#endif
+#if PPC_NUM_VECTORS > 704
+ .global vector704, vector705, vector706, vector707
+#endif
+#if PPC_NUM_VECTORS > 708
+ .global vector708, vector709, vector710, vector711
+#endif
+#if PPC_NUM_VECTORS > 712
+ .global vector712, vector713, vector714, vector715
+#endif
+#if PPC_NUM_VECTORS > 716
+ .global vector716, vector717, vector718, vector719
+#endif
+#if PPC_NUM_VECTORS > 720
+ .global vector720, vector721, vector722, vector723
+#endif
+#if PPC_NUM_VECTORS > 724
+ .global vector724, vector725, vector726, vector727
+#endif
+#if PPC_NUM_VECTORS > 728
+ .global vector728, vector729, vector730, vector731
+#endif
+#if PPC_NUM_VECTORS > 732
+ .global vector732, vector733, vector734, vector735
+#endif
+#if PPC_NUM_VECTORS > 736
+ .global vector736, vector737, vector738, vector739
+#endif
+#if PPC_NUM_VECTORS > 740
+ .global vector740, vector741, vector742, vector743
+#endif
+#if PPC_NUM_VECTORS > 744
+ .global vector744, vector745, vector746, vector747
+#endif
+#if PPC_NUM_VECTORS > 748
+ .global vector748, vector749, vector750, vector751
+#endif
+#if PPC_NUM_VECTORS > 752
+ .global vector752, vector753, vector754, vector755
+#endif
+#if PPC_NUM_VECTORS > 756
+ .global vector756, vector757, vector758, vector759
+#endif
+#if PPC_NUM_VECTORS > 760
+ .global vector760, vector761, vector762, vector763
+#endif
+#if PPC_NUM_VECTORS > 764
+ .global vector764, vector765, vector766, vector767
+#endif
+#if PPC_NUM_VECTORS > 768
+ .global vector768, vector769, vector770, vector771
+#endif
+#if PPC_NUM_VECTORS > 772
+ .global vector772, vector773, vector774, vector775
+#endif
+#if PPC_NUM_VECTORS > 776
+ .global vector776, vector777, vector778, vector779
+#endif
+#if PPC_NUM_VECTORS > 780
+ .global vector780, vector781, vector782, vector783
+#endif
+#if PPC_NUM_VECTORS > 784
+ .global vector784, vector785, vector786, vector787
+#endif
+#if PPC_NUM_VECTORS > 788
+ .global vector788, vector789, vector790, vector791
+#endif
+#if PPC_NUM_VECTORS > 792
+ .global vector792, vector793, vector794, vector795
+#endif
+#if PPC_NUM_VECTORS > 796
+ .global vector796, vector797, vector798, vector799
+#endif
+#if PPC_NUM_VECTORS > 800
+ .global vector800, vector801, vector802, vector803
+#endif
+#if PPC_NUM_VECTORS > 804
+ .global vector804, vector805, vector806, vector807
+#endif
+#if PPC_NUM_VECTORS > 808
+ .global vector808, vector809, vector810, vector811
+#endif
+#if PPC_NUM_VECTORS > 812
+ .global vector812, vector813, vector814, vector815
+#endif
+#if PPC_NUM_VECTORS > 816
+ .global vector816, vector817, vector818, vector819
+#endif
+#if PPC_NUM_VECTORS > 820
+ .global vector820, vector821, vector822, vector823
+#endif
+#if PPC_NUM_VECTORS > 824
+ .global vector824, vector825, vector826, vector827
+#endif
+#if PPC_NUM_VECTORS > 828
+ .global vector828, vector829, vector830, vector831
+#endif
+#if PPC_NUM_VECTORS > 832
+ .global vector832, vector833, vector834, vector835
+#endif
+#if PPC_NUM_VECTORS > 836
+ .global vector836, vector837, vector838, vector839
+#endif
+#if PPC_NUM_VECTORS > 840
+ .global vector840, vector841, vector842, vector843
+#endif
+#if PPC_NUM_VECTORS > 844
+ .global vector844, vector845, vector846, vector847
+#endif
+#if PPC_NUM_VECTORS > 848
+ .global vector848, vector849, vector850, vector851
+#endif
+#if PPC_NUM_VECTORS > 852
+ .global vector852, vector853, vector854, vector855
+#endif
+#if PPC_NUM_VECTORS > 856
+ .global vector856, vector857, vector858, vector859
+#endif
+#if PPC_NUM_VECTORS > 860
+ .global vector860, vector861, vector862, vector863
+#endif
+#if PPC_NUM_VECTORS > 864
+ .global vector864, vector865, vector866, vector867
+#endif
+#if PPC_NUM_VECTORS > 868
+ .global vector868, vector869, vector870, vector871
+#endif
+#if PPC_NUM_VECTORS > 872
+ .global vector872, vector873, vector874, vector875
+#endif
+#if PPC_NUM_VECTORS > 876
+ .global vector876, vector877, vector878, vector879
+#endif
+#if PPC_NUM_VECTORS > 880
+ .global vector880, vector881, vector882, vector883
+#endif
+#if PPC_NUM_VECTORS > 884
+ .global vector884, vector885, vector886, vector887
+#endif
+#if PPC_NUM_VECTORS > 888
+ .global vector888, vector889, vector890, vector891
+#endif
+#if PPC_NUM_VECTORS > 892
+ .global vector892, vector893, vector894, vector895
+#endif
+#if PPC_NUM_VECTORS > 896
+ .global vector896, vector897, vector898, vector899
+#endif
+#if PPC_NUM_VECTORS > 900
+ .global vector900, vector901, vector902, vector903
+#endif
+#if PPC_NUM_VECTORS > 904
+ .global vector904, vector905, vector906, vector907
+#endif
+#if PPC_NUM_VECTORS > 908
+ .global vector908, vector909, vector910, vector911
+#endif
+#if PPC_NUM_VECTORS > 912
+ .global vector912, vector913, vector914, vector915
+#endif
+#if PPC_NUM_VECTORS > 916
+ .global vector916, vector917, vector918, vector919
+#endif
+#if PPC_NUM_VECTORS > 920
+ .global vector920, vector921, vector922, vector923
+#endif
+#if PPC_NUM_VECTORS > 924
+ .global vector924, vector925, vector926, vector927
+#endif
+#if PPC_NUM_VECTORS > 928
+ .global vector928, vector929, vector930, vector931
+#endif
+#if PPC_NUM_VECTORS > 932
+ .global vector932, vector933, vector934, vector935
+#endif
+#if PPC_NUM_VECTORS > 936
+ .global vector936, vector937, vector938, vector939
+#endif
+#if PPC_NUM_VECTORS > 940
+ .global vector940, vector941, vector942, vector943
+#endif
+#if PPC_NUM_VECTORS > 944
+ .global vector944, vector945, vector946, vector947
+#endif
+#if PPC_NUM_VECTORS > 948
+ .global vector948, vector949, vector950, vector951
+#endif
+#if PPC_NUM_VECTORS > 952
+ .global vector952, vector953, vector954, vector955
+#endif
+#if PPC_NUM_VECTORS > 956
+ .global vector956, vector957, vector958, vector959
+#endif
+#if PPC_NUM_VECTORS > 960
+ .global vector960, vector961, vector962, vector963
+#endif
+#if PPC_NUM_VECTORS > 964
+ .global vector964, vector965, vector966, vector967
+#endif
+#if PPC_NUM_VECTORS > 968
+ .global vector968, vector969, vector970, vector971
+#endif
+#if PPC_NUM_VECTORS > 972
+ .global vector972, vector973, vector974, vector975
+#endif
+#if PPC_NUM_VECTORS > 976
+ .global vector976, vector977, vector978, vector979
+#endif
+#if PPC_NUM_VECTORS > 980
+ .global vector980, vector981, vector982, vector983
+#endif
+#if PPC_NUM_VECTORS > 984
+ .global vector984, vector985, vector986, vector987
+#endif
+#if PPC_NUM_VECTORS > 988
+ .global vector988, vector989, vector990, vector991
+#endif
+#if PPC_NUM_VECTORS > 992
+ .global vector992, vector993, vector994, vector995
+#endif
+#if PPC_NUM_VECTORS > 996
+ .global vector996, vector997, vector998, vector999
+#endif
+#if PPC_NUM_VECTORS > 1000
+ .global vector1000, vector1001, vector1002, vector1003
+#endif
+#if PPC_NUM_VECTORS > 1004
+ .global vector1004, vector1005, vector1006, vector1007
+#endif
+#if PPC_NUM_VECTORS > 1008
+ .global vector1008, vector1009, vector1010, vector1011
+#endif
+#if PPC_NUM_VECTORS > 1012
+ .global vector1012, vector1013, vector1014, vector1015
+#endif
+#if PPC_NUM_VECTORS > 1016
+ .global vector1016, vector1017, vector1018, vector1019
+#endif
+#if PPC_NUM_VECTORS > 1020
+ .global vector1020, vector1021, vector1022, vector1023
+#endif
+
+ /* Software vectors table. The vectors are accessed from the IVOR4
+ handler only. In order to declare an interrupt handler just create
+ a function withe the same name of a vector, the symbol will
+ override the weak symbol declared here.*/
+ .section .vectors
+ .globl _vectors
+_vectors:
+ .long vector0, vector1, vector2, vector3
+#if PPC_NUM_VECTORS > 4
+ .long vector4, vector5, vector6, vector7
+#endif
+#if PPC_NUM_VECTORS > 8
+ .long vector8, vector9, vector10, vector11
+#endif
+#if PPC_NUM_VECTORS > 12
+ .long vector12, vector13, vector14, vector15
+#endif
+#if PPC_NUM_VECTORS > 16
+ .long vector16, vector17, vector18, vector19
+#endif
+#if PPC_NUM_VECTORS > 20
+ .long vector20, vector21, vector22, vector23
+#endif
+#if PPC_NUM_VECTORS > 24
+ .long vector24, vector25, vector26, vector27
+#endif
+#if PPC_NUM_VECTORS > 28
+ .long vector28, vector29, vector30, vector31
+#endif
+#if PPC_NUM_VECTORS > 32
+ .long vector32, vector33, vector34, vector35
+#endif
+#if PPC_NUM_VECTORS > 36
+ .long vector36, vector37, vector38, vector39
+#endif
+#if PPC_NUM_VECTORS > 40
+ .long vector40, vector41, vector42, vector43
+#endif
+#if PPC_NUM_VECTORS > 44
+ .long vector44, vector45, vector46, vector47
+#endif
+#if PPC_NUM_VECTORS > 48
+ .long vector48, vector49, vector50, vector51
+#endif
+#if PPC_NUM_VECTORS > 52
+ .long vector52, vector53, vector54, vector55
+#endif
+#if PPC_NUM_VECTORS > 56
+ .long vector56, vector57, vector58, vector59
+#endif
+#if PPC_NUM_VECTORS > 60
+ .long vector60, vector61, vector62, vector63
+#endif
+#if PPC_NUM_VECTORS > 64
+ .long vector64, vector65, vector66, vector67
+#endif
+#if PPC_NUM_VECTORS > 68
+ .long vector68, vector69, vector70, vector71
+#endif
+#if PPC_NUM_VECTORS > 72
+ .long vector72, vector73, vector74, vector75
+#endif
+#if PPC_NUM_VECTORS > 76
+ .long vector76, vector77, vector78, vector79
+#endif
+#if PPC_NUM_VECTORS > 80
+ .long vector80, vector81, vector82, vector83
+#endif
+#if PPC_NUM_VECTORS > 84
+ .long vector84, vector85, vector86, vector87
+#endif
+#if PPC_NUM_VECTORS > 88
+ .long vector88, vector89, vector90, vector91
+#endif
+#if PPC_NUM_VECTORS > 92
+ .long vector92, vector93, vector94, vector95
+#endif
+#if PPC_NUM_VECTORS > 96
+ .long vector96, vector97, vector98, vector99
+#endif
+#if PPC_NUM_VECTORS > 100
+ .long vector100, vector101, vector102, vector103
+#endif
+#if PPC_NUM_VECTORS > 104
+ .long vector104, vector105, vector106, vector107
+#endif
+#if PPC_NUM_VECTORS > 108
+ .long vector108, vector109, vector110, vector111
+#endif
+#if PPC_NUM_VECTORS > 112
+ .long vector112, vector113, vector114, vector115
+#endif
+#if PPC_NUM_VECTORS > 116
+ .long vector116, vector117, vector118, vector119
+#endif
+#if PPC_NUM_VECTORS > 120
+ .long vector120, vector121, vector122, vector123
+#endif
+#if PPC_NUM_VECTORS > 124
+ .long vector124, vector125, vector126, vector127
+#endif
+#if PPC_NUM_VECTORS > 128
+ .long vector128, vector129, vector130, vector131
+#endif
+#if PPC_NUM_VECTORS > 132
+ .long vector132, vector133, vector134, vector135
+#endif
+#if PPC_NUM_VECTORS > 136
+ .long vector136, vector137, vector138, vector139
+#endif
+#if PPC_NUM_VECTORS > 140
+ .long vector140, vector141, vector142, vector143
+#endif
+#if PPC_NUM_VECTORS > 144
+ .long vector144, vector145, vector146, vector147
+#endif
+#if PPC_NUM_VECTORS > 148
+ .long vector148, vector149, vector150, vector151
+#endif
+#if PPC_NUM_VECTORS > 152
+ .long vector152, vector153, vector154, vector155
+#endif
+#if PPC_NUM_VECTORS > 156
+ .long vector156, vector157, vector158, vector159
+#endif
+#if PPC_NUM_VECTORS > 160
+ .long vector160, vector161, vector162, vector163
+#endif
+#if PPC_NUM_VECTORS > 164
+ .long vector164, vector165, vector166, vector167
+#endif
+#if PPC_NUM_VECTORS > 168
+ .long vector168, vector169, vector170, vector171
+#endif
+#if PPC_NUM_VECTORS > 172
+ .long vector172, vector173, vector174, vector175
+#endif
+#if PPC_NUM_VECTORS > 176
+ .long vector176, vector177, vector178, vector179
+#endif
+#if PPC_NUM_VECTORS > 180
+ .long vector180, vector181, vector182, vector183
+#endif
+#if PPC_NUM_VECTORS > 184
+ .long vector184, vector185, vector186, vector187
+#endif
+#if PPC_NUM_VECTORS > 188
+ .long vector188, vector189, vector190, vector191
+#endif
+#if PPC_NUM_VECTORS > 192
+ .long vector192, vector193, vector194, vector195
+#endif
+#if PPC_NUM_VECTORS > 196
+ .long vector196, vector197, vector198, vector199
+#endif
+#if PPC_NUM_VECTORS > 200
+ .long vector200, vector201, vector202, vector203
+#endif
+#if PPC_NUM_VECTORS > 204
+ .long vector204, vector205, vector206, vector207
+#endif
+#if PPC_NUM_VECTORS > 208
+ .long vector208, vector209, vector210, vector211
+#endif
+#if PPC_NUM_VECTORS > 212
+ .long vector212, vector213, vector214, vector215
+#endif
+#if PPC_NUM_VECTORS > 216
+ .long vector216, vector217, vector218, vector219
+#endif
+#if PPC_NUM_VECTORS > 220
+ .long vector220, vector221, vector222, vector223
+#endif
+#if PPC_NUM_VECTORS > 224
+ .long vector224, vector225, vector226, vector227
+#endif
+#if PPC_NUM_VECTORS > 228
+ .long vector228, vector229, vector230, vector231
+#endif
+#if PPC_NUM_VECTORS > 232
+ .long vector232, vector233, vector234, vector235
+#endif
+#if PPC_NUM_VECTORS > 236
+ .long vector236, vector237, vector238, vector239
+#endif
+#if PPC_NUM_VECTORS > 240
+ .long vector240, vector241, vector242, vector243
+#endif
+#if PPC_NUM_VECTORS > 244
+ .long vector244, vector245, vector246, vector247
+#endif
+#if PPC_NUM_VECTORS > 248
+ .long vector248, vector249, vector250, vector251
+#endif
+#if PPC_NUM_VECTORS > 252
+ .long vector252, vector253, vector254, vector255
+#endif
+#if PPC_NUM_VECTORS > 256
+ .long vector256, vector257, vector258, vector259
+#endif
+#if PPC_NUM_VECTORS > 260
+ .long vector260, vector261, vector262, vector263
+#endif
+#if PPC_NUM_VECTORS > 264
+ .long vector264, vector265, vector266, vector267
+#endif
+#if PPC_NUM_VECTORS > 268
+ .long vector268, vector269, vector270, vector271
+#endif
+#if PPC_NUM_VECTORS > 272
+ .long vector272, vector273, vector274, vector275
+#endif
+#if PPC_NUM_VECTORS > 276
+ .long vector276, vector277, vector278, vector279
+#endif
+#if PPC_NUM_VECTORS > 280
+ .long vector280, vector281, vector282, vector283
+#endif
+#if PPC_NUM_VECTORS > 284
+ .long vector284, vector285, vector286, vector287
+#endif
+#if PPC_NUM_VECTORS > 288
+ .long vector288, vector289, vector290, vector291
+#endif
+#if PPC_NUM_VECTORS > 292
+ .long vector292, vector293, vector294, vector295
+#endif
+#if PPC_NUM_VECTORS > 296
+ .long vector296, vector297, vector298, vector299
+#endif
+#if PPC_NUM_VECTORS > 300
+ .long vector300, vector301, vector302, vector303
+#endif
+#if PPC_NUM_VECTORS > 304
+ .long vector304, vector305, vector306, vector307
+#endif
+#if PPC_NUM_VECTORS > 308
+ .long vector308, vector309, vector310, vector311
+#endif
+#if PPC_NUM_VECTORS > 312
+ .long vector312, vector313, vector314, vector315
+#endif
+#if PPC_NUM_VECTORS > 316
+ .long vector316, vector317, vector318, vector319
+#endif
+#if PPC_NUM_VECTORS > 320
+ .long vector320, vector321, vector322, vector323
+#endif
+#if PPC_NUM_VECTORS > 324
+ .long vector324, vector325, vector326, vector327
+#endif
+#if PPC_NUM_VECTORS > 328
+ .long vector328, vector329, vector330, vector331
+#endif
+#if PPC_NUM_VECTORS > 332
+ .long vector332, vector333, vector334, vector335
+#endif
+#if PPC_NUM_VECTORS > 336
+ .long vector336, vector337, vector338, vector339
+#endif
+#if PPC_NUM_VECTORS > 340
+ .long vector340, vector341, vector342, vector343
+#endif
+#if PPC_NUM_VECTORS > 344
+ .long vector344, vector345, vector346, vector347
+#endif
+#if PPC_NUM_VECTORS > 348
+ .long vector348, vector349, vector350, vector351
+#endif
+#if PPC_NUM_VECTORS > 352
+ .long vector352, vector353, vector354, vector355
+#endif
+#if PPC_NUM_VECTORS > 356
+ .long vector356, vector357, vector358, vector359
+#endif
+#if PPC_NUM_VECTORS > 360
+ .long vector360, vector361, vector362, vector363
+#endif
+#if PPC_NUM_VECTORS > 364
+ .long vector364, vector365, vector366, vector367
+#endif
+#if PPC_NUM_VECTORS > 368
+ .long vector368, vector369, vector370, vector371
+#endif
+#if PPC_NUM_VECTORS > 372
+ .long vector372, vector373, vector374, vector375
+#endif
+#if PPC_NUM_VECTORS > 376
+ .long vector376, vector377, vector378, vector379
+#endif
+#if PPC_NUM_VECTORS > 380
+ .long vector380, vector381, vector382, vector383
+#endif
+#if PPC_NUM_VECTORS > 384
+ .long vector384, vector385, vector386, vector387
+#endif
+#if PPC_NUM_VECTORS > 388
+ .long vector388, vector389, vector390, vector391
+#endif
+#if PPC_NUM_VECTORS > 392
+ .long vector392, vector393, vector394, vector395
+#endif
+#if PPC_NUM_VECTORS > 396
+ .long vector396, vector397, vector398, vector399
+#endif
+#if PPC_NUM_VECTORS > 400
+ .long vector400, vector401, vector402, vector403
+#endif
+#if PPC_NUM_VECTORS > 404
+ .long vector404, vector405, vector406, vector407
+#endif
+#if PPC_NUM_VECTORS > 408
+ .long vector408, vector409, vector410, vector411
+#endif
+#if PPC_NUM_VECTORS > 412
+ .long vector412, vector413, vector414, vector415
+#endif
+#if PPC_NUM_VECTORS > 416
+ .long vector416, vector417, vector418, vector419
+#endif
+#if PPC_NUM_VECTORS > 420
+ .long vector420, vector421, vector422, vector423
+#endif
+#if PPC_NUM_VECTORS > 424
+ .long vector424, vector425, vector426, vector427
+#endif
+#if PPC_NUM_VECTORS > 428
+ .long vector428, vector429, vector430, vector431
+#endif
+#if PPC_NUM_VECTORS > 432
+ .long vector432, vector433, vector434, vector435
+#endif
+#if PPC_NUM_VECTORS > 436
+ .long vector436, vector437, vector438, vector439
+#endif
+#if PPC_NUM_VECTORS > 440
+ .long vector440, vector441, vector442, vector443
+#endif
+#if PPC_NUM_VECTORS > 444
+ .long vector444, vector445, vector446, vector447
+#endif
+#if PPC_NUM_VECTORS > 448
+ .long vector448, vector449, vector450, vector451
+#endif
+#if PPC_NUM_VECTORS > 452
+ .long vector452, vector453, vector454, vector455
+#endif
+#if PPC_NUM_VECTORS > 456
+ .long vector456, vector457, vector458, vector459
+#endif
+#if PPC_NUM_VECTORS > 460
+ .long vector460, vector461, vector462, vector463
+#endif
+#if PPC_NUM_VECTORS > 464
+ .long vector464, vector465, vector466, vector467
+#endif
+#if PPC_NUM_VECTORS > 468
+ .long vector468, vector469, vector470, vector471
+#endif
+#if PPC_NUM_VECTORS > 472
+ .long vector472, vector473, vector474, vector475
+#endif
+#if PPC_NUM_VECTORS > 476
+ .long vector476, vector477, vector478, vector479
+#endif
+#if PPC_NUM_VECTORS > 480
+ .long vector480, vector481, vector482, vector483
+#endif
+#if PPC_NUM_VECTORS > 484
+ .long vector484, vector485, vector486, vector487
+#endif
+#if PPC_NUM_VECTORS > 488
+ .long vector488, vector489, vector490, vector491
+#endif
+#if PPC_NUM_VECTORS > 492
+ .long vector492, vector493, vector494, vector495
+#endif
+#if PPC_NUM_VECTORS > 496
+ .long vector496, vector497, vector498, vector499
+#endif
+#if PPC_NUM_VECTORS > 500
+ .long vector500, vector501, vector502, vector503
+#endif
+#if PPC_NUM_VECTORS > 504
+ .long vector504, vector505, vector506, vector507
+#endif
+#if PPC_NUM_VECTORS > 508
+ .long vector508, vector509, vector510, vector511
+#endif
+#if PPC_NUM_VECTORS > 512
+ .long vector512, vector513, vector514, vector515
+#endif
+#if PPC_NUM_VECTORS > 516
+ .long vector516, vector517, vector518, vector519
+#endif
+#if PPC_NUM_VECTORS > 520
+ .long vector520, vector521, vector522, vector523
+#endif
+#if PPC_NUM_VECTORS > 524
+ .long vector524, vector525, vector526, vector527
+#endif
+#if PPC_NUM_VECTORS > 528
+ .long vector528, vector529, vector530, vector531
+#endif
+#if PPC_NUM_VECTORS > 532
+ .long vector532, vector533, vector534, vector535
+#endif
+#if PPC_NUM_VECTORS > 536
+ .long vector536, vector537, vector538, vector539
+#endif
+#if PPC_NUM_VECTORS > 540
+ .long vector540, vector541, vector542, vector543
+#endif
+#if PPC_NUM_VECTORS > 544
+ .long vector544, vector545, vector546, vector547
+#endif
+#if PPC_NUM_VECTORS > 548
+ .long vector548, vector549, vector550, vector551
+#endif
+#if PPC_NUM_VECTORS > 552
+ .long vector552, vector553, vector554, vector555
+#endif
+#if PPC_NUM_VECTORS > 556
+ .long vector556, vector557, vector558, vector559
+#endif
+#if PPC_NUM_VECTORS > 560
+ .long vector560, vector561, vector562, vector563
+#endif
+#if PPC_NUM_VECTORS > 564
+ .long vector564, vector565, vector566, vector567
+#endif
+#if PPC_NUM_VECTORS > 568
+ .long vector568, vector569, vector570, vector571
+#endif
+#if PPC_NUM_VECTORS > 572
+ .long vector572, vector573, vector574, vector575
+#endif
+#if PPC_NUM_VECTORS > 576
+ .long vector576, vector577, vector578, vector579
+#endif
+#if PPC_NUM_VECTORS > 580
+ .long vector580, vector581, vector582, vector583
+#endif
+#if PPC_NUM_VECTORS > 584
+ .long vector584, vector585, vector586, vector587
+#endif
+#if PPC_NUM_VECTORS > 588
+ .long vector588, vector589, vector590, vector591
+#endif
+#if PPC_NUM_VECTORS > 592
+ .long vector592, vector593, vector594, vector595
+#endif
+#if PPC_NUM_VECTORS > 596
+ .long vector596, vector597, vector598, vector599
+#endif
+#if PPC_NUM_VECTORS > 600
+ .long vector600, vector601, vector602, vector603
+#endif
+#if PPC_NUM_VECTORS > 604
+ .long vector604, vector605, vector606, vector607
+#endif
+#if PPC_NUM_VECTORS > 608
+ .long vector608, vector609, vector610, vector611
+#endif
+#if PPC_NUM_VECTORS > 612
+ .long vector612, vector613, vector614, vector615
+#endif
+#if PPC_NUM_VECTORS > 616
+ .long vector616, vector617, vector618, vector619
+#endif
+#if PPC_NUM_VECTORS > 620
+ .long vector620, vector621, vector622, vector623
+#endif
+#if PPC_NUM_VECTORS > 624
+ .long vector624, vector625, vector626, vector627
+#endif
+#if PPC_NUM_VECTORS > 628
+ .long vector628, vector629, vector630, vector631
+#endif
+#if PPC_NUM_VECTORS > 632
+ .long vector632, vector633, vector634, vector635
+#endif
+#if PPC_NUM_VECTORS > 636
+ .long vector636, vector637, vector638, vector639
+#endif
+#if PPC_NUM_VECTORS > 640
+ .long vector640, vector641, vector642, vector643
+#endif
+#if PPC_NUM_VECTORS > 644
+ .long vector644, vector645, vector646, vector647
+#endif
+#if PPC_NUM_VECTORS > 648
+ .long vector648, vector649, vector650, vector651
+#endif
+#if PPC_NUM_VECTORS > 652
+ .long vector652, vector653, vector654, vector655
+#endif
+#if PPC_NUM_VECTORS > 656
+ .long vector656, vector657, vector658, vector659
+#endif
+#if PPC_NUM_VECTORS > 660
+ .long vector660, vector661, vector662, vector663
+#endif
+#if PPC_NUM_VECTORS > 664
+ .long vector664, vector665, vector666, vector667
+#endif
+#if PPC_NUM_VECTORS > 668
+ .long vector668, vector669, vector670, vector671
+#endif
+#if PPC_NUM_VECTORS > 672
+ .long vector672, vector673, vector674, vector675
+#endif
+#if PPC_NUM_VECTORS > 676
+ .long vector676, vector677, vector678, vector679
+#endif
+#if PPC_NUM_VECTORS > 680
+ .long vector680, vector681, vector682, vector683
+#endif
+#if PPC_NUM_VECTORS > 684
+ .long vector684, vector685, vector686, vector687
+#endif
+#if PPC_NUM_VECTORS > 688
+ .long vector688, vector689, vector690, vector691
+#endif
+#if PPC_NUM_VECTORS > 692
+ .long vector692, vector693, vector694, vector695
+#endif
+#if PPC_NUM_VECTORS > 696
+ .long vector696, vector697, vector698, vector699
+#endif
+#if PPC_NUM_VECTORS > 700
+ .long vector700, vector701, vector702, vector703
+#endif
+#if PPC_NUM_VECTORS > 704
+ .long vector704, vector705, vector706, vector707
+#endif
+#if PPC_NUM_VECTORS > 708
+ .long vector708, vector709, vector710, vector711
+#endif
+#if PPC_NUM_VECTORS > 712
+ .long vector712, vector713, vector714, vector715
+#endif
+#if PPC_NUM_VECTORS > 716
+ .long vector716, vector717, vector718, vector719
+#endif
+#if PPC_NUM_VECTORS > 720
+ .long vector720, vector721, vector722, vector723
+#endif
+#if PPC_NUM_VECTORS > 724
+ .long vector724, vector725, vector726, vector727
+#endif
+#if PPC_NUM_VECTORS > 728
+ .long vector728, vector729, vector730, vector731
+#endif
+#if PPC_NUM_VECTORS > 732
+ .long vector732, vector733, vector734, vector735
+#endif
+#if PPC_NUM_VECTORS > 736
+ .long vector736, vector737, vector738, vector739
+#endif
+#if PPC_NUM_VECTORS > 740
+ .long vector740, vector741, vector742, vector743
+#endif
+#if PPC_NUM_VECTORS > 744
+ .long vector744, vector745, vector746, vector747
+#endif
+#if PPC_NUM_VECTORS > 748
+ .long vector748, vector749, vector750, vector751
+#endif
+#if PPC_NUM_VECTORS > 752
+ .long vector752, vector753, vector754, vector755
+#endif
+#if PPC_NUM_VECTORS > 756
+ .long vector756, vector757, vector758, vector759
+#endif
+#if PPC_NUM_VECTORS > 760
+ .long vector760, vector761, vector762, vector763
+#endif
+#if PPC_NUM_VECTORS > 764
+ .long vector764, vector765, vector766, vector767
+#endif
+#if PPC_NUM_VECTORS > 768
+ .long vector768, vector769, vector770, vector771
+#endif
+#if PPC_NUM_VECTORS > 772
+ .long vector772, vector773, vector774, vector775
+#endif
+#if PPC_NUM_VECTORS > 776
+ .long vector776, vector777, vector778, vector779
+#endif
+#if PPC_NUM_VECTORS > 780
+ .long vector780, vector781, vector782, vector783
+#endif
+#if PPC_NUM_VECTORS > 784
+ .long vector784, vector785, vector786, vector787
+#endif
+#if PPC_NUM_VECTORS > 788
+ .long vector788, vector789, vector790, vector791
+#endif
+#if PPC_NUM_VECTORS > 792
+ .long vector792, vector793, vector794, vector795
+#endif
+#if PPC_NUM_VECTORS > 796
+ .long vector796, vector797, vector798, vector799
+#endif
+#if PPC_NUM_VECTORS > 800
+ .long vector800, vector801, vector802, vector803
+#endif
+#if PPC_NUM_VECTORS > 804
+ .long vector804, vector805, vector806, vector807
+#endif
+#if PPC_NUM_VECTORS > 808
+ .long vector808, vector809, vector810, vector811
+#endif
+#if PPC_NUM_VECTORS > 812
+ .long vector812, vector813, vector814, vector815
+#endif
+#if PPC_NUM_VECTORS > 816
+ .long vector816, vector817, vector818, vector819
+#endif
+#if PPC_NUM_VECTORS > 820
+ .long vector820, vector821, vector822, vector823
+#endif
+#if PPC_NUM_VECTORS > 824
+ .long vector824, vector825, vector826, vector827
+#endif
+#if PPC_NUM_VECTORS > 828
+ .long vector828, vector829, vector830, vector831
+#endif
+#if PPC_NUM_VECTORS > 832
+ .long vector832, vector833, vector834, vector835
+#endif
+#if PPC_NUM_VECTORS > 836
+ .long vector836, vector837, vector838, vector839
+#endif
+#if PPC_NUM_VECTORS > 840
+ .long vector840, vector841, vector842, vector843
+#endif
+#if PPC_NUM_VECTORS > 844
+ .long vector844, vector845, vector846, vector847
+#endif
+#if PPC_NUM_VECTORS > 848
+ .long vector848, vector849, vector850, vector851
+#endif
+#if PPC_NUM_VECTORS > 852
+ .long vector852, vector853, vector854, vector855
+#endif
+#if PPC_NUM_VECTORS > 856
+ .long vector856, vector857, vector858, vector859
+#endif
+#if PPC_NUM_VECTORS > 860
+ .long vector860, vector861, vector862, vector863
+#endif
+#if PPC_NUM_VECTORS > 864
+ .long vector864, vector865, vector866, vector867
+#endif
+#if PPC_NUM_VECTORS > 868
+ .long vector868, vector869, vector870, vector871
+#endif
+#if PPC_NUM_VECTORS > 872
+ .long vector872, vector873, vector874, vector875
+#endif
+#if PPC_NUM_VECTORS > 876
+ .long vector876, vector877, vector878, vector879
+#endif
+#if PPC_NUM_VECTORS > 880
+ .long vector880, vector881, vector882, vector883
+#endif
+#if PPC_NUM_VECTORS > 884
+ .long vector884, vector885, vector886, vector887
+#endif
+#if PPC_NUM_VECTORS > 888
+ .long vector888, vector889, vector890, vector891
+#endif
+#if PPC_NUM_VECTORS > 892
+ .long vector892, vector893, vector894, vector895
+#endif
+#if PPC_NUM_VECTORS > 896
+ .long vector896, vector897, vector898, vector899
+#endif
+#if PPC_NUM_VECTORS > 900
+ .long vector900, vector901, vector902, vector903
+#endif
+#if PPC_NUM_VECTORS > 904
+ .long vector904, vector905, vector906, vector907
+#endif
+#if PPC_NUM_VECTORS > 908
+ .long vector908, vector909, vector910, vector911
+#endif
+#if PPC_NUM_VECTORS > 912
+ .long vector912, vector913, vector914, vector915
+#endif
+#if PPC_NUM_VECTORS > 916
+ .long vector916, vector917, vector918, vector919
+#endif
+#if PPC_NUM_VECTORS > 920
+ .long vector920, vector921, vector922, vector923
+#endif
+#if PPC_NUM_VECTORS > 924
+ .long vector924, vector925, vector926, vector927
+#endif
+#if PPC_NUM_VECTORS > 928
+ .long vector928, vector929, vector930, vector931
+#endif
+#if PPC_NUM_VECTORS > 932
+ .long vector932, vector933, vector934, vector935
+#endif
+#if PPC_NUM_VECTORS > 936
+ .long vector936, vector937, vector938, vector939
+#endif
+#if PPC_NUM_VECTORS > 940
+ .long vector940, vector941, vector942, vector943
+#endif
+#if PPC_NUM_VECTORS > 944
+ .long vector944, vector945, vector946, vector947
+#endif
+#if PPC_NUM_VECTORS > 948
+ .long vector948, vector949, vector950, vector951
+#endif
+#if PPC_NUM_VECTORS > 952
+ .long vector952, vector953, vector954, vector955
+#endif
+#if PPC_NUM_VECTORS > 956
+ .long vector956, vector957, vector958, vector959
+#endif
+#if PPC_NUM_VECTORS > 960
+ .long vector960, vector961, vector962, vector963
+#endif
+#if PPC_NUM_VECTORS > 964
+ .long vector964, vector965, vector966, vector967
+#endif
+#if PPC_NUM_VECTORS > 968
+ .long vector968, vector969, vector970, vector971
+#endif
+#if PPC_NUM_VECTORS > 972
+ .long vector972, vector973, vector974, vector975
+#endif
+#if PPC_NUM_VECTORS > 976
+ .long vector976, vector977, vector978, vector979
+#endif
+#if PPC_NUM_VECTORS > 980
+ .long vector980, vector981, vector982, vector983
+#endif
+#if PPC_NUM_VECTORS > 984
+ .long vector984, vector985, vector986, vector987
+#endif
+#if PPC_NUM_VECTORS > 988
+ .long vector988, vector989, vector990, vector991
+#endif
+#if PPC_NUM_VECTORS > 992
+ .long vector992, vector993, vector994, vector995
+#endif
+#if PPC_NUM_VECTORS > 996
+ .long vector996, vector997, vector998, vector999
+#endif
+#if PPC_NUM_VECTORS > 1000
+ .long vector1000, vector1001, vector1002, vector1003
+#endif
+#if PPC_NUM_VECTORS > 1004
+ .long vector1004, vector1005, vector1006, vector1007
+#endif
+#if PPC_NUM_VECTORS > 1008
+ .long vector1008, vector1009, vector1010, vector1011
+#endif
+#if PPC_NUM_VECTORS > 1012
+ .long vector1012, vector1013, vector1014, vector1015
+#endif
+#if PPC_NUM_VECTORS > 1016
+ .long vector1016, vector1017, vector1018, vector1019
+#endif
+#if PPC_NUM_VECTORS > 1020
+ .long vector1020, vector1021, vector1022, vector1023
+#endif
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/crt0.S b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/crt0.S new file mode 100644 index 0000000..eff066f --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/crt0.S @@ -0,0 +1,246 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file GCC/crt0.S
+ * @brief Generic PowerPC startup file for GCC.
+ *
+ * @addtogroup PPC_GCC_CORE
+ * @{
+ */
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+#if defined(__HIGHTEC__)
+#define se_bge bge
+#endif
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
+#define CRT0_STACKS_FILL_PATTERN 0x55555555
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
+#define CRT0_INIT_STACKS TRUE
+#endif
+
+/**
+ * @brief DATA segment initialization switch.
+ */
+#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
+#define CRT0_INIT_DATA TRUE
+#endif
+
+/**
+ * @brief BSS segment initialization switch.
+ */
+#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
+#define CRT0_INIT_BSS TRUE
+#endif
+
+/**
+ * @brief Constructors invocation switch.
+ */
+#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_CONSTRUCTORS TRUE
+#endif
+
+/**
+ * @brief Destructors invocation switch.
+ */
+#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_DESTRUCTORS TRUE
+#endif
+
+/*===========================================================================*/
+/* Code section. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+
+ .section .crt0, "ax"
+ .align 2
+ .globl _boot_address
+ .type _boot_address, @function
+_boot_address:
+ /* Stack setup.*/
+ e_lis r1, __process_stack_end__@h
+ e_or2i r1, __process_stack_end__@l
+ se_li r0, 0
+ e_stwu r0, -8(r1)
+
+ /* Small sections registers initialization.*/
+ e_lis r2, __sdata2_start__@h
+ e_or2i r2, __sdata2_start__@l
+ e_lis r13, __sdata_start__@h
+ e_or2i r13, __sdata_start__@l
+
+ /* Early initialization.*/
+ e_bl __early_init
+
+#if CRT0_INIT_STACKS == TRUE
+ /* Stacks fill pattern.*/
+ e_lis r7, CRT0_STACKS_FILL_PATTERN@h
+ e_or2i r7, CRT0_STACKS_FILL_PATTERN@l
+
+ /* IRQ Stack initialization. Note, the architecture does not use this
+ stack, the size is usually zero. An OS can have special SW handling
+ and require this. A 4 bytes alignment is assmend and required.*/
+ e_lis r4, __irq_stack_base__@h
+ e_or2i r4, __irq_stack_base__@l
+ e_lis r5, __irq_stack_end__@h
+ e_or2i r5, __irq_stack_end__@l
+.irqsloop:
+ se_cmpl r4, r5
+ se_bge .irqsend
+ se_stw r7, 0(r4)
+ se_addi r4, 4
+ se_b .irqsloop
+.irqsend:
+
+ /* Process Stack initialization. Note, does not overwrite the already
+ written EABI frame. A 4 bytes alignment is assmend and required.*/
+ e_lis r4, __process_stack_base__@h
+ e_or2i r4, __process_stack_base__@l
+ e_lis r5, (__process_stack_end__ - 8)@h
+ e_or2i r5, (__process_stack_end__ - 8)@l
+.prcsloop:
+ se_cmpl r4, r5
+ se_bge .prcsend
+ se_stw r7, 0(r4)
+ se_addi r4, 4
+ se_b .prcsloop
+.prcsend:
+#endif
+
+#if CRT0_INIT_BSS == TRUE
+ /* BSS clearing.*/
+ e_lis r4, __bss_start__@h
+ e_or2i r4, __bss_start__@l
+ e_lis r5, __bss_end__@h
+ e_or2i r5, __bss_end__@l
+ se_li r7, 0
+.bssloop:
+ se_cmpl r4, r5
+ se_bge .bssend
+ se_stw r7, 0(r4)
+ se_addi r4, 4
+ se_b .bssloop
+.bssend:
+#endif
+
+#if CRT0_INIT_DATA == TRUE
+ /* DATA initialization.*/
+ e_lis r4, __romdata_start__@h
+ e_or2i r4, __romdata_start__@l
+ e_lis r5, __data_start__@h
+ e_or2i r5, __data_start__@l
+ e_lis r6, __data_end__@h
+ e_or2i r6, __data_end__@l
+.dataloop:
+ se_cmpl r5, r6
+ se_bge .dataend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .dataloop
+.dataend:
+#endif
+
+ /* Late initialization.*/
+ e_bl __late_init
+
+#if CRT0_CALL_CONSTRUCTORS == TRUE
+ /* Constructors invocation.*/
+ e_lis r4, __init_array_start@h
+ e_or2i r4, __init_array_start@l
+ e_lis r5, __init_array_end@h
+ e_or2i r5, __init_array_end@l
+.iniloop:
+ se_cmpl r4, r5
+ se_bge .iniend
+ se_lwz r6, 0(r4)
+ mtctr r6
+ se_addi r4, 4
+ se_bctrl
+ se_b .iniloop
+.iniend:
+#endif
+
+ /* Main program invocation.*/
+ e_bl main
+
+#if CRT0_CALL_DESTRUCTORS == TRUE
+ /* Destructors invocation.*/
+ e_lis r4, __fini_array_start@h
+ e_or2i r4, __fini_array_start@l
+ e_lis r5, __fini_array_end@h
+ e_or2i r5, __fini_array_end@l
+.finiloop:
+ se_cmpl r4, r5
+ se_bge .finiend
+ se_lwz r6, 0(r4)
+ mtctr r6
+ se_addi r4, 4
+ se_bctrl
+ se_b .finiloop
+.finiend:
+#endif
+
+ /* Branching to the defined exit handler.*/
+ e_b __default_exit
+
+ /* Default main exit code, infinite loop.*/
+ .weak __default_exit
+ .type __default_exit, @function
+__default_exit:
+ e_b __default_exit
+
+ /* Default early initialization code, none.*/
+ .weak __early_init
+ .type __early_init, @function
+__early_init:
+ se_blr
+
+ /* Default late initialization code, none.*/
+ .weak __late_init
+ .type __late_init, @function
+__late_init:
+ se_blr
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560B50.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560B50.ld new file mode 100644 index 0000000..f9b0cdf --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560B50.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560B50 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 512k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 32k
+}
+
+INCLUDE rules_z0.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560B60.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560B60.ld new file mode 100644 index 0000000..141c7e1 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560B60.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560B60 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 1024k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 80k
+}
+
+INCLUDE rules_z0.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560B64.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560B64.ld new file mode 100644 index 0000000..06302d3 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560B64.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560B64 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 1536k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 96k
+}
+
+INCLUDE rules_z0.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560D40.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560D40.ld new file mode 100644 index 0000000..8ca58ac --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560D40.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560D40 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 256k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 16k
+}
+
+INCLUDE rules_z0.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560P50.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560P50.ld new file mode 100644 index 0000000..d90287a --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC560P50.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560P50 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 512k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 40k
+}
+
+INCLUDE rules_z0.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC563M64.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC563M64.ld new file mode 100644 index 0000000..a934f28 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC563M64.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC563M64 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 1536k
+ ram : org = 0x40000000, len = 94k
+}
+
+INCLUDE rules_z3.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC564A70.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC564A70.ld new file mode 100644 index 0000000..0cc7207 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC564A70.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC563A70 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 2M
+ ram : org = 0x40000000, len = 128k
+}
+
+INCLUDE rules_z4.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC564A80.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC564A80.ld new file mode 100644 index 0000000..f0ee575 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC564A80.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC563A80 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 4M
+ ram : org = 0x40000000, len = 192k
+}
+
+INCLUDE rules_z4.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC56EC74.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC56EC74.ld new file mode 100644 index 0000000..451eb24 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC56EC74.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC56EC74 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 3M
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 256k
+}
+
+INCLUDE rules_z4.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC56EL54_LSM.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC56EL54_LSM.ld new file mode 100644 index 0000000..06232c1 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC56EL54_LSM.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC56EL54 memory setup in LSM mode.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 768k
+ ram : org = 0x40000000, len = 128k
+}
+
+INCLUDE rules_z4.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC56EL60_LSM.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC56EL60_LSM.ld new file mode 100644 index 0000000..4884fee --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC56EL60_LSM.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC56EL60 memory setup in LSM mode.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 1M
+ ram : org = 0x40000000, len = 128k
+}
+
+INCLUDE rules_z4.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC56EL70_LSM.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC56EL70_LSM.ld new file mode 100644 index 0000000..e4b907b --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/SPC56EL70_LSM.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC56EL70 memory setup in LSM mode.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 2M
+ ram : org = 0x40000000, len = 192k
+}
+
+INCLUDE rules_z4.ld
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/rules_z0.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/rules_z0.ld new file mode 100644 index 0000000..e6cc68e --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/rules_z0.ld @@ -0,0 +1,159 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+__ram_size__ = LENGTH(ram);
+__ram_start__ = ORIGIN(ram);
+__ram_end__ = ORIGIN(ram) + LENGTH(ram);
+
+ENTRY(_reset_address)
+
+SECTIONS
+{
+ . = ORIGIN(flash);
+ .boot0 : ALIGN(16)
+ {
+ KEEP(*(.boot))
+ } > flash
+
+ .boot1 : ALIGN(16)
+ {
+ KEEP(*(.handlers))
+ KEEP(*(.crt0))
+ /* The vectors table requires a 2kB alignment.*/
+ . = ALIGN(0x800);
+ KEEP(*(.vectors))
+ /* The IVPR register requires a 4kB alignment.*/
+ . = ALIGN(0x1000);
+ __ivpr_base__ = .;
+ KEEP(*(.ivors))
+ } > flash
+
+ constructors : ALIGN(4)
+ {
+ PROVIDE(__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors : ALIGN(4)
+ {
+ PROVIDE(__fini_array_start = .);
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .text_vle : ALIGN(16)
+ {
+ *(.text_vle)
+ *(.text_vle.*)
+ *(.gnu.linkonce.t_vle.*)
+ } > flash
+
+ .text : ALIGN(16)
+ {
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ } > flash
+
+ .rodata : ALIGN(16)
+ {
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ *(.rodata)
+ *(.rodata.*)
+ *(.rodata1)
+ } > flash
+
+ .sdata2 : ALIGN(16)
+ {
+ __sdata2_start__ = . + 0x8000;
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ } > flash
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > flash
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > flash
+
+ .romdata : ALIGN(16)
+ {
+ __romdata_start__ = .;
+ } > flash
+
+ .stacks (NOLOAD) : ALIGN(16)
+ {
+ . = ALIGN(8);
+ __irq_stack_base__ = .;
+ . += __irq_stack_size__;
+ . = ALIGN(8);
+ __irq_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .data : AT(__romdata_start__)
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ __sdata_start__ = . + 0x8000;
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ __data_end__ = .;
+ } > ram
+
+ .sbss (NOLOAD) :
+ {
+ __bss_start__ = .;
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ } > ram
+
+ .bss (NOLOAD) :
+ {
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > ram
+
+ __heap_base__ = __bss_end__;
+ __heap_end__ = __ram_end__;
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/rules_z3.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/rules_z3.ld new file mode 100644 index 0000000..cda44ab --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/rules_z3.ld @@ -0,0 +1,156 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+__ram_size__ = LENGTH(ram);
+__ram_start__ = ORIGIN(ram);
+__ram_end__ = ORIGIN(ram) + LENGTH(ram);
+
+ENTRY(_reset_address)
+
+SECTIONS
+{
+ . = ORIGIN(flash);
+ .boot0 : ALIGN(16)
+ {
+ __ivpr_base__ = .;
+ KEEP(*(.boot))
+ } > flash
+
+ .boot1 : ALIGN(16)
+ {
+ KEEP(*(.handlers))
+ KEEP(*(.crt0))
+ /* The vectors table requires a 2kB alignment.*/
+ . = ALIGN(0x800);
+ KEEP(*(.vectors))
+ } > flash
+
+ constructors : ALIGN(4)
+ {
+ PROVIDE(__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors : ALIGN(4)
+ {
+ PROVIDE(__fini_array_start = .);
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .text_vle : ALIGN(16)
+ {
+ *(.text_vle)
+ *(.text_vle.*)
+ *(.gnu.linkonce.t_vle.*)
+ } > flash
+
+ .text : ALIGN(16)
+ {
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ } > flash
+
+ .rodata : ALIGN(16)
+ {
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ *(.rodata)
+ *(.rodata.*)
+ *(.rodata1)
+ } > flash
+
+ .sdata2 : ALIGN(16)
+ {
+ __sdata2_start__ = . + 0x8000;
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ } > flash
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > flash
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > flash
+
+ .romdata : ALIGN(16)
+ {
+ __romdata_start__ = .;
+ } > flash
+
+ .stacks (NOLOAD) : ALIGN(16)
+ {
+ . = ALIGN(8);
+ __irq_stack_base__ = .;
+ . += __irq_stack_size__;
+ . = ALIGN(8);
+ __irq_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .data : AT(__romdata_start__)
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ __sdata_start__ = . + 0x8000;
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ __data_end__ = .;
+ } > ram
+
+ .sbss (NOLOAD) :
+ {
+ __bss_start__ = .;
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ } > ram
+
+ .bss (NOLOAD) :
+ {
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > ram
+
+ __heap_base__ = __bss_end__;
+ __heap_end__ = __ram_end__;
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/rules_z4.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/rules_z4.ld new file mode 100644 index 0000000..cda44ab --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/ld/rules_z4.ld @@ -0,0 +1,156 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+__ram_size__ = LENGTH(ram);
+__ram_start__ = ORIGIN(ram);
+__ram_end__ = ORIGIN(ram) + LENGTH(ram);
+
+ENTRY(_reset_address)
+
+SECTIONS
+{
+ . = ORIGIN(flash);
+ .boot0 : ALIGN(16)
+ {
+ __ivpr_base__ = .;
+ KEEP(*(.boot))
+ } > flash
+
+ .boot1 : ALIGN(16)
+ {
+ KEEP(*(.handlers))
+ KEEP(*(.crt0))
+ /* The vectors table requires a 2kB alignment.*/
+ . = ALIGN(0x800);
+ KEEP(*(.vectors))
+ } > flash
+
+ constructors : ALIGN(4)
+ {
+ PROVIDE(__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors : ALIGN(4)
+ {
+ PROVIDE(__fini_array_start = .);
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .text_vle : ALIGN(16)
+ {
+ *(.text_vle)
+ *(.text_vle.*)
+ *(.gnu.linkonce.t_vle.*)
+ } > flash
+
+ .text : ALIGN(16)
+ {
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ } > flash
+
+ .rodata : ALIGN(16)
+ {
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ *(.rodata)
+ *(.rodata.*)
+ *(.rodata1)
+ } > flash
+
+ .sdata2 : ALIGN(16)
+ {
+ __sdata2_start__ = . + 0x8000;
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ } > flash
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > flash
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > flash
+
+ .romdata : ALIGN(16)
+ {
+ __romdata_start__ = .;
+ } > flash
+
+ .stacks (NOLOAD) : ALIGN(16)
+ {
+ . = ALIGN(8);
+ __irq_stack_base__ = .;
+ . += __irq_stack_size__;
+ . = ALIGN(8);
+ __irq_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .data : AT(__romdata_start__)
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ __sdata_start__ = . + 0x8000;
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ __data_end__ = .;
+ } > ram
+
+ .sbss (NOLOAD) :
+ {
+ __bss_start__ = .;
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ } > ram
+
+ .bss (NOLOAD) :
+ {
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > ram
+
+ __heap_base__ = __bss_end__;
+ __heap_end__ = __ram_end__;
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc560bcxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc560bcxx.mk new file mode 100644 index 0000000..e7ae4b3 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc560bcxx.mk @@ -0,0 +1,17 @@ +# List of the ChibiOS e200z0 SPC560BCxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC560BCxx/boot.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/vectors.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/crt0.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC560BCxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc560bxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc560bxx.mk new file mode 100644 index 0000000..8b1cb74 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc560bxx.mk @@ -0,0 +1,17 @@ +# List of the ChibiOS e200z0 SPC560Bxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC560Bxx/boot.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/vectors.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/crt0.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC560Bxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc560dxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc560dxx.mk new file mode 100644 index 0000000..f533524 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc560dxx.mk @@ -0,0 +1,17 @@ +# List of the ChibiOS e200z0 SPC560Dxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC560Dxx/boot.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/vectors.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/crt0.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC560Dxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc560pxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc560pxx.mk new file mode 100644 index 0000000..10ca985 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc560pxx.mk @@ -0,0 +1,17 @@ +# List of the ChibiOS e200z0 SPC560Pxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC560Pxx/boot.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/vectors.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/crt0.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC560Pxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc563mxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc563mxx.mk new file mode 100644 index 0000000..1057cd4 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc563mxx.mk @@ -0,0 +1,17 @@ +# List of the ChibiOS e200z3 SPC563Mxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC563Mxx/boot.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/vectors.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/crt0.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC563Mxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc564axx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc564axx.mk new file mode 100644 index 0000000..98d8ce0 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc564axx.mk @@ -0,0 +1,17 @@ +# List of the ChibiOS e200z4 SPC564Axx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC564Axx/boot.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/vectors.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/crt0.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC564Axx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc56ecxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc56ecxx.mk new file mode 100644 index 0000000..6eed564 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc56ecxx.mk @@ -0,0 +1,17 @@ +# List of the ChibiOS e200z4 SPC56ECxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC56ECxx/boot.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/vectors.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/crt0.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC56ECxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc56elxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc56elxx.mk new file mode 100644 index 0000000..ed28954 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/mk/startup_spc56elxx.mk @@ -0,0 +1,17 @@ +# List of the ChibiOS e200z4 SPC56ELxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC56ELxx/boot.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/vectors.S \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GCC/crt0.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC56ELxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/rules.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/rules.mk new file mode 100644 index 0000000..e53aabf --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/rules.mk @@ -0,0 +1,260 @@ +# e200z common makefile scripts and rules.
+
+##############################################################################
+# Processing options coming from the upper Makefile.
+#
+
+# Compiler options
+OPT = $(USE_OPT)
+COPT = $(USE_COPT)
+CPPOPT = $(USE_CPPOPT)
+
+# Garbage collection
+ifeq ($(USE_LINK_GC),yes)
+ OPT += -ffunction-sections -fdata-sections -fno-common
+ LDOPT := --gc-sections
+else
+ LDOPT := --no-gc-sections
+endif
+
+# Linker extra options
+ifneq ($(USE_LDOPT),)
+ LDOPT := $(LDOPT),$(USE_LDOPT)
+endif
+
+# Link time optimizations
+ifeq ($(USE_LTO),yes)
+ OPT += -flto
+endif
+
+# VLE option handling.
+ifeq ($(USE_VLE),yes)
+ DDEFS += -DPPC_USE_VLE=1
+ DADEFS += -DPPC_USE_VLE=1
+ MCU += -mvle
+else
+ DDEFS += -DPPC_USE_VLE=0
+ DADEFS += -DPPC_USE_VLE=0
+endif
+
+# Process stack size
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE)
+endif
+
+# Exceptions stack size
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__irq_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__irq_stack_size__=$(USE_EXCEPTIONS_STACKSIZE)
+endif
+
+# Output directory and files
+ifeq ($(BUILDDIR),)
+ BUILDDIR = build
+endif
+ifeq ($(BUILDDIR),.)
+ BUILDDIR = build
+endif
+
+# Dependencies directory
+ifeq ($(DEPDIR),)
+ DEPDIR = .dep
+endif
+ifeq ($(DEPDIR),.)
+ DEPDIR = .dep
+endif
+
+OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
+ $(BUILDDIR)/$(PROJECT).mot $(BUILDDIR)/$(PROJECT).bin \
+ $(BUILDDIR)/$(PROJECT).dmp $(BUILDDIR)/$(PROJECT).list
+
+# Source files groups and paths
+SRC = $(CSRC)$(CPPSRC)
+SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(SRC)))
+
+# Various directories
+OBJDIR = $(BUILDDIR)/obj
+LSTDIR = $(BUILDDIR)/lst
+
+# Object files groups
+COBJS = $(addprefix $(OBJDIR)/, $(notdir $(CSRC:.c=.o)))
+CPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(CPPSRC:.cpp=.o)))
+ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
+ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+OBJS = $(ASMXOBJS) $(ASMOBJS) $(COBJS) $(CPPOBJS)
+
+# Paths
+IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
+LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+
+# Macros
+DEFS = $(DDEFS) $(UDEFS)
+ADEFS = $(DADEFS) $(UADEFS)
+
+# Libs
+LIBS = $(DLIBS) $(ULIBS)
+
+# Various settings
+MCFLAGS = -mcpu=$(MCU)
+ODFLAGS = -x --syms
+ASFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+ASXFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
+CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
+CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
+LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH)/ld,$(LDOPT),--script=$(LDSCRIPT)
+
+# Generate dependency information
+ASFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+ASXFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+CFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+CPPFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+
+# Paths where to search for sources
+VPATH = $(SRCPATHS)
+
+#
+# Makefile rules
+#
+
+all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK
+
+PRE_MAKE_ALL_RULE_HOOK:
+
+POST_MAKE_ALL_RULE_HOOK:
+
+$(OBJS): | PRE_MAKE_ALL_RULE_HOOK $(BUILDDIR) $(OBJDIR) $(LSTDIR) $(DEPDIR)
+
+$(BUILDDIR):
+ifneq ($(USE_VERBOSE_COMPILE),yes)
+ @echo Compiler Options
+ @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
+ @echo
+endif
+ @mkdir -p $(BUILDDIR)
+
+$(OBJDIR):
+ @mkdir -p $(OBJDIR)
+
+$(LSTDIR):
+ @mkdir -p $(LSTDIR)
+
+$(DEPDIR):
+ @mkdir -p $(DEPDIR)
+
+$(CPPOBJS) : $(OBJDIR)/%.o : %.cpp $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(COBJS) : $(OBJDIR)/%.o : %.c $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMOBJS) : $(OBJDIR)/%.o : %.s $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+%.elf: $(OBJS) $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+else
+ @echo Linking $@
+ @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+endif
+
+%.hex: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(HEX) $< $@
+else
+ @echo Creating $@
+ @$(HEX) $< $@
+endif
+
+%.mot: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(MOT) $< $@
+else
+ @echo Creating $@
+ @$(MOT) $< $@
+endif
+
+%.bin: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(BIN) $< $@
+else
+ @echo Creating $@
+ @$(BIN) $< $@
+endif
+
+%.dmp: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(OD) $(ODFLAGS) $< > $@
+ $(SZ) $<
+else
+ @echo Creating $@
+ @$(OD) $(ODFLAGS) $< > $@
+ @echo
+ @$(SZ) $<
+endif
+
+%.list: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(OD) -S $< > $@
+else
+ @echo Creating $@
+ @$(OD) -S $< > $@
+ @echo Done
+endif
+
+lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a
+
+$(BUILDDIR)/lib$(PROJECT).a: $(OBJS)
+ @$(AR) -r $@ $^
+ @echo
+ @echo Done
+
+clean: CLEAN_RULE_HOOK
+ @echo Cleaning
+ @echo - $(DEPDIR)
+ @-rm -fR $(DEPDIR)/* $(BUILDDIR)/* 2>/dev/null
+ @-if [ -d "$(DEPDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(DEPDIR)) 2>/dev/null; fi
+ @echo - $(BUILDDIR)
+ @-if [ -d "$(BUILDDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(BUILDDIR)) 2>/dev/null; fi
+ @echo
+ @echo Done
+
+CLEAN_RULE_HOOK:
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(wildcard $(DEPDIR)/*)
+
+# *** EOF ***
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/vectors.S b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/vectors.S new file mode 100644 index 0000000..e3227ab --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/vectors.S @@ -0,0 +1,2612 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file vectors.S
+ * @brief INTC vectors table.
+ *
+ * @addtogroup PPC_GCC_CORE
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "ppcparams.h"
+
+#if defined(VECTORS_RENAMING)
+#include "isrs.h"
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ /* Software vectors table. The vectors are accessed from the IVOR4
+ handler only. In order to declare an interrupt handler just create
+ a function withe the same name of a vector, the symbol will
+ override the weak symbol declared here.*/
+ .section .vectors, "ax"
+ .align 4
+ .globl _vectors
+_vectors:
+ .long vector0, vector1, vector2, vector3
+#if PPC_NUM_VECTORS > 4
+ .long vector4, vector5, vector6, vector7
+#endif
+#if PPC_NUM_VECTORS > 8
+ .long vector8, vector9, vector10, vector11
+#endif
+#if PPC_NUM_VECTORS > 12
+ .long vector12, vector13, vector14, vector15
+#endif
+#if PPC_NUM_VECTORS > 16
+ .long vector16, vector17, vector18, vector19
+#endif
+#if PPC_NUM_VECTORS > 20
+ .long vector20, vector21, vector22, vector23
+#endif
+#if PPC_NUM_VECTORS > 24
+ .long vector24, vector25, vector26, vector27
+#endif
+#if PPC_NUM_VECTORS > 28
+ .long vector28, vector29, vector30, vector31
+#endif
+#if PPC_NUM_VECTORS > 32
+ .long vector32, vector33, vector34, vector35
+#endif
+#if PPC_NUM_VECTORS > 36
+ .long vector36, vector37, vector38, vector39
+#endif
+#if PPC_NUM_VECTORS > 40
+ .long vector40, vector41, vector42, vector43
+#endif
+#if PPC_NUM_VECTORS > 44
+ .long vector44, vector45, vector46, vector47
+#endif
+#if PPC_NUM_VECTORS > 48
+ .long vector48, vector49, vector50, vector51
+#endif
+#if PPC_NUM_VECTORS > 52
+ .long vector52, vector53, vector54, vector55
+#endif
+#if PPC_NUM_VECTORS > 56
+ .long vector56, vector57, vector58, vector59
+#endif
+#if PPC_NUM_VECTORS > 60
+ .long vector60, vector61, vector62, vector63
+#endif
+#if PPC_NUM_VECTORS > 64
+ .long vector64, vector65, vector66, vector67
+#endif
+#if PPC_NUM_VECTORS > 68
+ .long vector68, vector69, vector70, vector71
+#endif
+#if PPC_NUM_VECTORS > 72
+ .long vector72, vector73, vector74, vector75
+#endif
+#if PPC_NUM_VECTORS > 76
+ .long vector76, vector77, vector78, vector79
+#endif
+#if PPC_NUM_VECTORS > 80
+ .long vector80, vector81, vector82, vector83
+#endif
+#if PPC_NUM_VECTORS > 84
+ .long vector84, vector85, vector86, vector87
+#endif
+#if PPC_NUM_VECTORS > 88
+ .long vector88, vector89, vector90, vector91
+#endif
+#if PPC_NUM_VECTORS > 92
+ .long vector92, vector93, vector94, vector95
+#endif
+#if PPC_NUM_VECTORS > 96
+ .long vector96, vector97, vector98, vector99
+#endif
+#if PPC_NUM_VECTORS > 100
+ .long vector100, vector101, vector102, vector103
+#endif
+#if PPC_NUM_VECTORS > 104
+ .long vector104, vector105, vector106, vector107
+#endif
+#if PPC_NUM_VECTORS > 108
+ .long vector108, vector109, vector110, vector111
+#endif
+#if PPC_NUM_VECTORS > 112
+ .long vector112, vector113, vector114, vector115
+#endif
+#if PPC_NUM_VECTORS > 116
+ .long vector116, vector117, vector118, vector119
+#endif
+#if PPC_NUM_VECTORS > 120
+ .long vector120, vector121, vector122, vector123
+#endif
+#if PPC_NUM_VECTORS > 124
+ .long vector124, vector125, vector126, vector127
+#endif
+#if PPC_NUM_VECTORS > 128
+ .long vector128, vector129, vector130, vector131
+#endif
+#if PPC_NUM_VECTORS > 132
+ .long vector132, vector133, vector134, vector135
+#endif
+#if PPC_NUM_VECTORS > 136
+ .long vector136, vector137, vector138, vector139
+#endif
+#if PPC_NUM_VECTORS > 140
+ .long vector140, vector141, vector142, vector143
+#endif
+#if PPC_NUM_VECTORS > 144
+ .long vector144, vector145, vector146, vector147
+#endif
+#if PPC_NUM_VECTORS > 148
+ .long vector148, vector149, vector150, vector151
+#endif
+#if PPC_NUM_VECTORS > 152
+ .long vector152, vector153, vector154, vector155
+#endif
+#if PPC_NUM_VECTORS > 156
+ .long vector156, vector157, vector158, vector159
+#endif
+#if PPC_NUM_VECTORS > 160
+ .long vector160, vector161, vector162, vector163
+#endif
+#if PPC_NUM_VECTORS > 164
+ .long vector164, vector165, vector166, vector167
+#endif
+#if PPC_NUM_VECTORS > 168
+ .long vector168, vector169, vector170, vector171
+#endif
+#if PPC_NUM_VECTORS > 172
+ .long vector172, vector173, vector174, vector175
+#endif
+#if PPC_NUM_VECTORS > 176
+ .long vector176, vector177, vector178, vector179
+#endif
+#if PPC_NUM_VECTORS > 180
+ .long vector180, vector181, vector182, vector183
+#endif
+#if PPC_NUM_VECTORS > 184
+ .long vector184, vector185, vector186, vector187
+#endif
+#if PPC_NUM_VECTORS > 188
+ .long vector188, vector189, vector190, vector191
+#endif
+#if PPC_NUM_VECTORS > 192
+ .long vector192, vector193, vector194, vector195
+#endif
+#if PPC_NUM_VECTORS > 196
+ .long vector196, vector197, vector198, vector199
+#endif
+#if PPC_NUM_VECTORS > 200
+ .long vector200, vector201, vector202, vector203
+#endif
+#if PPC_NUM_VECTORS > 204
+ .long vector204, vector205, vector206, vector207
+#endif
+#if PPC_NUM_VECTORS > 208
+ .long vector208, vector209, vector210, vector211
+#endif
+#if PPC_NUM_VECTORS > 212
+ .long vector212, vector213, vector214, vector215
+#endif
+#if PPC_NUM_VECTORS > 216
+ .long vector216, vector217, vector218, vector219
+#endif
+#if PPC_NUM_VECTORS > 220
+ .long vector220, vector221, vector222, vector223
+#endif
+#if PPC_NUM_VECTORS > 224
+ .long vector224, vector225, vector226, vector227
+#endif
+#if PPC_NUM_VECTORS > 228
+ .long vector228, vector229, vector230, vector231
+#endif
+#if PPC_NUM_VECTORS > 232
+ .long vector232, vector233, vector234, vector235
+#endif
+#if PPC_NUM_VECTORS > 236
+ .long vector236, vector237, vector238, vector239
+#endif
+#if PPC_NUM_VECTORS > 240
+ .long vector240, vector241, vector242, vector243
+#endif
+#if PPC_NUM_VECTORS > 244
+ .long vector244, vector245, vector246, vector247
+#endif
+#if PPC_NUM_VECTORS > 248
+ .long vector248, vector249, vector250, vector251
+#endif
+#if PPC_NUM_VECTORS > 252
+ .long vector252, vector253, vector254, vector255
+#endif
+#if PPC_NUM_VECTORS > 256
+ .long vector256, vector257, vector258, vector259
+#endif
+#if PPC_NUM_VECTORS > 260
+ .long vector260, vector261, vector262, vector263
+#endif
+#if PPC_NUM_VECTORS > 264
+ .long vector264, vector265, vector266, vector267
+#endif
+#if PPC_NUM_VECTORS > 268
+ .long vector268, vector269, vector270, vector271
+#endif
+#if PPC_NUM_VECTORS > 272
+ .long vector272, vector273, vector274, vector275
+#endif
+#if PPC_NUM_VECTORS > 276
+ .long vector276, vector277, vector278, vector279
+#endif
+#if PPC_NUM_VECTORS > 280
+ .long vector280, vector281, vector282, vector283
+#endif
+#if PPC_NUM_VECTORS > 284
+ .long vector284, vector285, vector286, vector287
+#endif
+#if PPC_NUM_VECTORS > 288
+ .long vector288, vector289, vector290, vector291
+#endif
+#if PPC_NUM_VECTORS > 292
+ .long vector292, vector293, vector294, vector295
+#endif
+#if PPC_NUM_VECTORS > 296
+ .long vector296, vector297, vector298, vector299
+#endif
+#if PPC_NUM_VECTORS > 300
+ .long vector300, vector301, vector302, vector303
+#endif
+#if PPC_NUM_VECTORS > 304
+ .long vector304, vector305, vector306, vector307
+#endif
+#if PPC_NUM_VECTORS > 308
+ .long vector308, vector309, vector310, vector311
+#endif
+#if PPC_NUM_VECTORS > 312
+ .long vector312, vector313, vector314, vector315
+#endif
+#if PPC_NUM_VECTORS > 316
+ .long vector316, vector317, vector318, vector319
+#endif
+#if PPC_NUM_VECTORS > 320
+ .long vector320, vector321, vector322, vector323
+#endif
+#if PPC_NUM_VECTORS > 324
+ .long vector324, vector325, vector326, vector327
+#endif
+#if PPC_NUM_VECTORS > 328
+ .long vector328, vector329, vector330, vector331
+#endif
+#if PPC_NUM_VECTORS > 332
+ .long vector332, vector333, vector334, vector335
+#endif
+#if PPC_NUM_VECTORS > 336
+ .long vector336, vector337, vector338, vector339
+#endif
+#if PPC_NUM_VECTORS > 340
+ .long vector340, vector341, vector342, vector343
+#endif
+#if PPC_NUM_VECTORS > 344
+ .long vector344, vector345, vector346, vector347
+#endif
+#if PPC_NUM_VECTORS > 348
+ .long vector348, vector349, vector350, vector351
+#endif
+#if PPC_NUM_VECTORS > 352
+ .long vector352, vector353, vector354, vector355
+#endif
+#if PPC_NUM_VECTORS > 356
+ .long vector356, vector357, vector358, vector359
+#endif
+#if PPC_NUM_VECTORS > 360
+ .long vector360, vector361, vector362, vector363
+#endif
+#if PPC_NUM_VECTORS > 364
+ .long vector364, vector365, vector366, vector367
+#endif
+#if PPC_NUM_VECTORS > 368
+ .long vector368, vector369, vector370, vector371
+#endif
+#if PPC_NUM_VECTORS > 372
+ .long vector372, vector373, vector374, vector375
+#endif
+#if PPC_NUM_VECTORS > 376
+ .long vector376, vector377, vector378, vector379
+#endif
+#if PPC_NUM_VECTORS > 380
+ .long vector380, vector381, vector382, vector383
+#endif
+#if PPC_NUM_VECTORS > 384
+ .long vector384, vector385, vector386, vector387
+#endif
+#if PPC_NUM_VECTORS > 388
+ .long vector388, vector389, vector390, vector391
+#endif
+#if PPC_NUM_VECTORS > 392
+ .long vector392, vector393, vector394, vector395
+#endif
+#if PPC_NUM_VECTORS > 396
+ .long vector396, vector397, vector398, vector399
+#endif
+#if PPC_NUM_VECTORS > 400
+ .long vector400, vector401, vector402, vector403
+#endif
+#if PPC_NUM_VECTORS > 404
+ .long vector404, vector405, vector406, vector407
+#endif
+#if PPC_NUM_VECTORS > 408
+ .long vector408, vector409, vector410, vector411
+#endif
+#if PPC_NUM_VECTORS > 412
+ .long vector412, vector413, vector414, vector415
+#endif
+#if PPC_NUM_VECTORS > 416
+ .long vector416, vector417, vector418, vector419
+#endif
+#if PPC_NUM_VECTORS > 420
+ .long vector420, vector421, vector422, vector423
+#endif
+#if PPC_NUM_VECTORS > 424
+ .long vector424, vector425, vector426, vector427
+#endif
+#if PPC_NUM_VECTORS > 428
+ .long vector428, vector429, vector430, vector431
+#endif
+#if PPC_NUM_VECTORS > 432
+ .long vector432, vector433, vector434, vector435
+#endif
+#if PPC_NUM_VECTORS > 436
+ .long vector436, vector437, vector438, vector439
+#endif
+#if PPC_NUM_VECTORS > 440
+ .long vector440, vector441, vector442, vector443
+#endif
+#if PPC_NUM_VECTORS > 444
+ .long vector444, vector445, vector446, vector447
+#endif
+#if PPC_NUM_VECTORS > 448
+ .long vector448, vector449, vector450, vector451
+#endif
+#if PPC_NUM_VECTORS > 452
+ .long vector452, vector453, vector454, vector455
+#endif
+#if PPC_NUM_VECTORS > 456
+ .long vector456, vector457, vector458, vector459
+#endif
+#if PPC_NUM_VECTORS > 460
+ .long vector460, vector461, vector462, vector463
+#endif
+#if PPC_NUM_VECTORS > 464
+ .long vector464, vector465, vector466, vector467
+#endif
+#if PPC_NUM_VECTORS > 468
+ .long vector468, vector469, vector470, vector471
+#endif
+#if PPC_NUM_VECTORS > 472
+ .long vector472, vector473, vector474, vector475
+#endif
+#if PPC_NUM_VECTORS > 476
+ .long vector476, vector477, vector478, vector479
+#endif
+#if PPC_NUM_VECTORS > 480
+ .long vector480, vector481, vector482, vector483
+#endif
+#if PPC_NUM_VECTORS > 484
+ .long vector484, vector485, vector486, vector487
+#endif
+#if PPC_NUM_VECTORS > 488
+ .long vector488, vector489, vector490, vector491
+#endif
+#if PPC_NUM_VECTORS > 492
+ .long vector492, vector493, vector494, vector495
+#endif
+#if PPC_NUM_VECTORS > 496
+ .long vector496, vector497, vector498, vector499
+#endif
+#if PPC_NUM_VECTORS > 500
+ .long vector500, vector501, vector502, vector503
+#endif
+#if PPC_NUM_VECTORS > 504
+ .long vector504, vector505, vector506, vector507
+#endif
+#if PPC_NUM_VECTORS > 508
+ .long vector508, vector509, vector510, vector511
+#endif
+#if PPC_NUM_VECTORS > 512
+ .long vector512, vector513, vector514, vector515
+#endif
+#if PPC_NUM_VECTORS > 516
+ .long vector516, vector517, vector518, vector519
+#endif
+#if PPC_NUM_VECTORS > 520
+ .long vector520, vector521, vector522, vector523
+#endif
+#if PPC_NUM_VECTORS > 524
+ .long vector524, vector525, vector526, vector527
+#endif
+#if PPC_NUM_VECTORS > 528
+ .long vector528, vector529, vector530, vector531
+#endif
+#if PPC_NUM_VECTORS > 532
+ .long vector532, vector533, vector534, vector535
+#endif
+#if PPC_NUM_VECTORS > 536
+ .long vector536, vector537, vector538, vector539
+#endif
+#if PPC_NUM_VECTORS > 540
+ .long vector540, vector541, vector542, vector543
+#endif
+#if PPC_NUM_VECTORS > 544
+ .long vector544, vector545, vector546, vector547
+#endif
+#if PPC_NUM_VECTORS > 548
+ .long vector548, vector549, vector550, vector551
+#endif
+#if PPC_NUM_VECTORS > 552
+ .long vector552, vector553, vector554, vector555
+#endif
+#if PPC_NUM_VECTORS > 556
+ .long vector556, vector557, vector558, vector559
+#endif
+#if PPC_NUM_VECTORS > 560
+ .long vector560, vector561, vector562, vector563
+#endif
+#if PPC_NUM_VECTORS > 564
+ .long vector564, vector565, vector566, vector567
+#endif
+#if PPC_NUM_VECTORS > 568
+ .long vector568, vector569, vector570, vector571
+#endif
+#if PPC_NUM_VECTORS > 572
+ .long vector572, vector573, vector574, vector575
+#endif
+#if PPC_NUM_VECTORS > 576
+ .long vector576, vector577, vector578, vector579
+#endif
+#if PPC_NUM_VECTORS > 580
+ .long vector580, vector581, vector582, vector583
+#endif
+#if PPC_NUM_VECTORS > 584
+ .long vector584, vector585, vector586, vector587
+#endif
+#if PPC_NUM_VECTORS > 588
+ .long vector588, vector589, vector590, vector591
+#endif
+#if PPC_NUM_VECTORS > 592
+ .long vector592, vector593, vector594, vector595
+#endif
+#if PPC_NUM_VECTORS > 596
+ .long vector596, vector597, vector598, vector599
+#endif
+#if PPC_NUM_VECTORS > 600
+ .long vector600, vector601, vector602, vector603
+#endif
+#if PPC_NUM_VECTORS > 604
+ .long vector604, vector605, vector606, vector607
+#endif
+#if PPC_NUM_VECTORS > 608
+ .long vector608, vector609, vector610, vector611
+#endif
+#if PPC_NUM_VECTORS > 612
+ .long vector612, vector613, vector614, vector615
+#endif
+#if PPC_NUM_VECTORS > 616
+ .long vector616, vector617, vector618, vector619
+#endif
+#if PPC_NUM_VECTORS > 620
+ .long vector620, vector621, vector622, vector623
+#endif
+#if PPC_NUM_VECTORS > 624
+ .long vector624, vector625, vector626, vector627
+#endif
+#if PPC_NUM_VECTORS > 628
+ .long vector628, vector629, vector630, vector631
+#endif
+#if PPC_NUM_VECTORS > 632
+ .long vector632, vector633, vector634, vector635
+#endif
+#if PPC_NUM_VECTORS > 636
+ .long vector636, vector637, vector638, vector639
+#endif
+#if PPC_NUM_VECTORS > 640
+ .long vector640, vector641, vector642, vector643
+#endif
+#if PPC_NUM_VECTORS > 644
+ .long vector644, vector645, vector646, vector647
+#endif
+#if PPC_NUM_VECTORS > 648
+ .long vector648, vector649, vector650, vector651
+#endif
+#if PPC_NUM_VECTORS > 652
+ .long vector652, vector653, vector654, vector655
+#endif
+#if PPC_NUM_VECTORS > 656
+ .long vector656, vector657, vector658, vector659
+#endif
+#if PPC_NUM_VECTORS > 660
+ .long vector660, vector661, vector662, vector663
+#endif
+#if PPC_NUM_VECTORS > 664
+ .long vector664, vector665, vector666, vector667
+#endif
+#if PPC_NUM_VECTORS > 668
+ .long vector668, vector669, vector670, vector671
+#endif
+#if PPC_NUM_VECTORS > 672
+ .long vector672, vector673, vector674, vector675
+#endif
+#if PPC_NUM_VECTORS > 676
+ .long vector676, vector677, vector678, vector679
+#endif
+#if PPC_NUM_VECTORS > 680
+ .long vector680, vector681, vector682, vector683
+#endif
+#if PPC_NUM_VECTORS > 684
+ .long vector684, vector685, vector686, vector687
+#endif
+#if PPC_NUM_VECTORS > 688
+ .long vector688, vector689, vector690, vector691
+#endif
+#if PPC_NUM_VECTORS > 692
+ .long vector692, vector693, vector694, vector695
+#endif
+#if PPC_NUM_VECTORS > 696
+ .long vector696, vector697, vector698, vector699
+#endif
+#if PPC_NUM_VECTORS > 700
+ .long vector700, vector701, vector702, vector703
+#endif
+#if PPC_NUM_VECTORS > 704
+ .long vector704, vector705, vector706, vector707
+#endif
+#if PPC_NUM_VECTORS > 708
+ .long vector708, vector709, vector710, vector711
+#endif
+#if PPC_NUM_VECTORS > 712
+ .long vector712, vector713, vector714, vector715
+#endif
+#if PPC_NUM_VECTORS > 716
+ .long vector716, vector717, vector718, vector719
+#endif
+#if PPC_NUM_VECTORS > 720
+ .long vector720, vector721, vector722, vector723
+#endif
+#if PPC_NUM_VECTORS > 724
+ .long vector724, vector725, vector726, vector727
+#endif
+#if PPC_NUM_VECTORS > 728
+ .long vector728, vector729, vector730, vector731
+#endif
+#if PPC_NUM_VECTORS > 732
+ .long vector732, vector733, vector734, vector735
+#endif
+#if PPC_NUM_VECTORS > 736
+ .long vector736, vector737, vector738, vector739
+#endif
+#if PPC_NUM_VECTORS > 740
+ .long vector740, vector741, vector742, vector743
+#endif
+#if PPC_NUM_VECTORS > 744
+ .long vector744, vector745, vector746, vector747
+#endif
+#if PPC_NUM_VECTORS > 748
+ .long vector748, vector749, vector750, vector751
+#endif
+#if PPC_NUM_VECTORS > 752
+ .long vector752, vector753, vector754, vector755
+#endif
+#if PPC_NUM_VECTORS > 756
+ .long vector756, vector757, vector758, vector759
+#endif
+#if PPC_NUM_VECTORS > 760
+ .long vector760, vector761, vector762, vector763
+#endif
+#if PPC_NUM_VECTORS > 764
+ .long vector764, vector765, vector766, vector767
+#endif
+#if PPC_NUM_VECTORS > 768
+ .long vector768, vector769, vector770, vector771
+#endif
+#if PPC_NUM_VECTORS > 772
+ .long vector772, vector773, vector774, vector775
+#endif
+#if PPC_NUM_VECTORS > 776
+ .long vector776, vector777, vector778, vector779
+#endif
+#if PPC_NUM_VECTORS > 780
+ .long vector780, vector781, vector782, vector783
+#endif
+#if PPC_NUM_VECTORS > 784
+ .long vector784, vector785, vector786, vector787
+#endif
+#if PPC_NUM_VECTORS > 788
+ .long vector788, vector789, vector790, vector791
+#endif
+#if PPC_NUM_VECTORS > 792
+ .long vector792, vector793, vector794, vector795
+#endif
+#if PPC_NUM_VECTORS > 796
+ .long vector796, vector797, vector798, vector799
+#endif
+#if PPC_NUM_VECTORS > 800
+ .long vector800, vector801, vector802, vector803
+#endif
+#if PPC_NUM_VECTORS > 804
+ .long vector804, vector805, vector806, vector807
+#endif
+#if PPC_NUM_VECTORS > 808
+ .long vector808, vector809, vector810, vector811
+#endif
+#if PPC_NUM_VECTORS > 812
+ .long vector812, vector813, vector814, vector815
+#endif
+#if PPC_NUM_VECTORS > 816
+ .long vector816, vector817, vector818, vector819
+#endif
+#if PPC_NUM_VECTORS > 820
+ .long vector820, vector821, vector822, vector823
+#endif
+#if PPC_NUM_VECTORS > 824
+ .long vector824, vector825, vector826, vector827
+#endif
+#if PPC_NUM_VECTORS > 828
+ .long vector828, vector829, vector830, vector831
+#endif
+#if PPC_NUM_VECTORS > 832
+ .long vector832, vector833, vector834, vector835
+#endif
+#if PPC_NUM_VECTORS > 836
+ .long vector836, vector837, vector838, vector839
+#endif
+#if PPC_NUM_VECTORS > 840
+ .long vector840, vector841, vector842, vector843
+#endif
+#if PPC_NUM_VECTORS > 844
+ .long vector844, vector845, vector846, vector847
+#endif
+#if PPC_NUM_VECTORS > 848
+ .long vector848, vector849, vector850, vector851
+#endif
+#if PPC_NUM_VECTORS > 852
+ .long vector852, vector853, vector854, vector855
+#endif
+#if PPC_NUM_VECTORS > 856
+ .long vector856, vector857, vector858, vector859
+#endif
+#if PPC_NUM_VECTORS > 860
+ .long vector860, vector861, vector862, vector863
+#endif
+#if PPC_NUM_VECTORS > 864
+ .long vector864, vector865, vector866, vector867
+#endif
+#if PPC_NUM_VECTORS > 868
+ .long vector868, vector869, vector870, vector871
+#endif
+#if PPC_NUM_VECTORS > 872
+ .long vector872, vector873, vector874, vector875
+#endif
+#if PPC_NUM_VECTORS > 876
+ .long vector876, vector877, vector878, vector879
+#endif
+#if PPC_NUM_VECTORS > 880
+ .long vector880, vector881, vector882, vector883
+#endif
+#if PPC_NUM_VECTORS > 884
+ .long vector884, vector885, vector886, vector887
+#endif
+#if PPC_NUM_VECTORS > 888
+ .long vector888, vector889, vector890, vector891
+#endif
+#if PPC_NUM_VECTORS > 892
+ .long vector892, vector893, vector894, vector895
+#endif
+#if PPC_NUM_VECTORS > 896
+ .long vector896, vector897, vector898, vector899
+#endif
+#if PPC_NUM_VECTORS > 900
+ .long vector900, vector901, vector902, vector903
+#endif
+#if PPC_NUM_VECTORS > 904
+ .long vector904, vector905, vector906, vector907
+#endif
+#if PPC_NUM_VECTORS > 908
+ .long vector908, vector909, vector910, vector911
+#endif
+#if PPC_NUM_VECTORS > 912
+ .long vector912, vector913, vector914, vector915
+#endif
+#if PPC_NUM_VECTORS > 916
+ .long vector916, vector917, vector918, vector919
+#endif
+#if PPC_NUM_VECTORS > 920
+ .long vector920, vector921, vector922, vector923
+#endif
+#if PPC_NUM_VECTORS > 924
+ .long vector924, vector925, vector926, vector927
+#endif
+#if PPC_NUM_VECTORS > 928
+ .long vector928, vector929, vector930, vector931
+#endif
+#if PPC_NUM_VECTORS > 932
+ .long vector932, vector933, vector934, vector935
+#endif
+#if PPC_NUM_VECTORS > 936
+ .long vector936, vector937, vector938, vector939
+#endif
+#if PPC_NUM_VECTORS > 940
+ .long vector940, vector941, vector942, vector943
+#endif
+#if PPC_NUM_VECTORS > 944
+ .long vector944, vector945, vector946, vector947
+#endif
+#if PPC_NUM_VECTORS > 948
+ .long vector948, vector949, vector950, vector951
+#endif
+#if PPC_NUM_VECTORS > 952
+ .long vector952, vector953, vector954, vector955
+#endif
+#if PPC_NUM_VECTORS > 956
+ .long vector956, vector957, vector958, vector959
+#endif
+#if PPC_NUM_VECTORS > 960
+ .long vector960, vector961, vector962, vector963
+#endif
+#if PPC_NUM_VECTORS > 964
+ .long vector964, vector965, vector966, vector967
+#endif
+#if PPC_NUM_VECTORS > 968
+ .long vector968, vector969, vector970, vector971
+#endif
+#if PPC_NUM_VECTORS > 972
+ .long vector972, vector973, vector974, vector975
+#endif
+#if PPC_NUM_VECTORS > 976
+ .long vector976, vector977, vector978, vector979
+#endif
+#if PPC_NUM_VECTORS > 980
+ .long vector980, vector981, vector982, vector983
+#endif
+#if PPC_NUM_VECTORS > 984
+ .long vector984, vector985, vector986, vector987
+#endif
+#if PPC_NUM_VECTORS > 988
+ .long vector988, vector989, vector990, vector991
+#endif
+#if PPC_NUM_VECTORS > 992
+ .long vector992, vector993, vector994, vector995
+#endif
+#if PPC_NUM_VECTORS > 996
+ .long vector996, vector997, vector998, vector999
+#endif
+#if PPC_NUM_VECTORS > 1000
+ .long vector1000, vector1001, vector1002, vector1003
+#endif
+#if PPC_NUM_VECTORS > 1004
+ .long vector1004, vector1005, vector1006, vector1007
+#endif
+#if PPC_NUM_VECTORS > 1008
+ .long vector1008, vector1009, vector1010, vector1011
+#endif
+#if PPC_NUM_VECTORS > 1012
+ .long vector1012, vector1013, vector1014, vector1015
+#endif
+#if PPC_NUM_VECTORS > 1016
+ .long vector1016, vector1017, vector1018, vector1019
+#endif
+#if PPC_NUM_VECTORS > 1020
+ .long vector1020, vector1021, vector1022, vector1023
+#endif
+
+ .text
+ .align 2
+
+ .weak vector0, vector1, vector2, vector3
+#if PPC_NUM_VECTORS > 4
+ .weak vector4, vector5, vector6, vector7
+#endif
+#if PPC_NUM_VECTORS > 8
+ .weak vector8, vector9, vector10, vector11
+#endif
+#if PPC_NUM_VECTORS > 12
+ .weak vector12, vector13, vector14, vector15
+#endif
+#if PPC_NUM_VECTORS > 16
+ .weak vector16, vector17, vector18, vector19
+#endif
+#if PPC_NUM_VECTORS > 20
+ .weak vector20, vector21, vector22, vector23
+#endif
+#if PPC_NUM_VECTORS > 24
+ .weak vector24, vector25, vector26, vector27
+#endif
+#if PPC_NUM_VECTORS > 28
+ .weak vector28, vector29, vector30, vector31
+#endif
+#if PPC_NUM_VECTORS > 32
+ .weak vector32, vector33, vector34, vector35
+#endif
+#if PPC_NUM_VECTORS > 36
+ .weak vector36, vector37, vector38, vector39
+#endif
+#if PPC_NUM_VECTORS > 40
+ .weak vector40, vector41, vector42, vector43
+#endif
+#if PPC_NUM_VECTORS > 44
+ .weak vector44, vector45, vector46, vector47
+#endif
+#if PPC_NUM_VECTORS > 48
+ .weak vector48, vector49, vector50, vector51
+#endif
+#if PPC_NUM_VECTORS > 52
+ .weak vector52, vector53, vector54, vector55
+#endif
+#if PPC_NUM_VECTORS > 56
+ .weak vector56, vector57, vector58, vector59
+#endif
+#if PPC_NUM_VECTORS > 60
+ .weak vector60, vector61, vector62, vector63
+#endif
+#if PPC_NUM_VECTORS > 64
+ .weak vector64, vector65, vector66, vector67
+#endif
+#if PPC_NUM_VECTORS > 68
+ .weak vector68, vector69, vector70, vector71
+#endif
+#if PPC_NUM_VECTORS > 72
+ .weak vector72, vector73, vector74, vector75
+#endif
+#if PPC_NUM_VECTORS > 76
+ .weak vector76, vector77, vector78, vector79
+#endif
+#if PPC_NUM_VECTORS > 80
+ .weak vector80, vector81, vector82, vector83
+#endif
+#if PPC_NUM_VECTORS > 84
+ .weak vector84, vector85, vector86, vector87
+#endif
+#if PPC_NUM_VECTORS > 88
+ .weak vector88, vector89, vector90, vector91
+#endif
+#if PPC_NUM_VECTORS > 92
+ .weak vector92, vector93, vector94, vector95
+#endif
+#if PPC_NUM_VECTORS > 96
+ .weak vector96, vector97, vector98, vector99
+#endif
+#if PPC_NUM_VECTORS > 100
+ .weak vector100, vector101, vector102, vector103
+#endif
+#if PPC_NUM_VECTORS > 104
+ .weak vector104, vector105, vector106, vector107
+#endif
+#if PPC_NUM_VECTORS > 108
+ .weak vector108, vector109, vector110, vector111
+#endif
+#if PPC_NUM_VECTORS > 112
+ .weak vector112, vector113, vector114, vector115
+#endif
+#if PPC_NUM_VECTORS > 116
+ .weak vector116, vector117, vector118, vector119
+#endif
+#if PPC_NUM_VECTORS > 120
+ .weak vector120, vector121, vector122, vector123
+#endif
+#if PPC_NUM_VECTORS > 124
+ .weak vector124, vector125, vector126, vector127
+#endif
+#if PPC_NUM_VECTORS > 128
+ .weak vector128, vector129, vector130, vector131
+#endif
+#if PPC_NUM_VECTORS > 132
+ .weak vector132, vector133, vector134, vector135
+#endif
+#if PPC_NUM_VECTORS > 136
+ .weak vector136, vector137, vector138, vector139
+#endif
+#if PPC_NUM_VECTORS > 140
+ .weak vector140, vector141, vector142, vector143
+#endif
+#if PPC_NUM_VECTORS > 144
+ .weak vector144, vector145, vector146, vector147
+#endif
+#if PPC_NUM_VECTORS > 148
+ .weak vector148, vector149, vector150, vector151
+#endif
+#if PPC_NUM_VECTORS > 152
+ .weak vector152, vector153, vector154, vector155
+#endif
+#if PPC_NUM_VECTORS > 156
+ .weak vector156, vector157, vector158, vector159
+#endif
+#if PPC_NUM_VECTORS > 160
+ .weak vector160, vector161, vector162, vector163
+#endif
+#if PPC_NUM_VECTORS > 164
+ .weak vector164, vector165, vector166, vector167
+#endif
+#if PPC_NUM_VECTORS > 168
+ .weak vector168, vector169, vector170, vector171
+#endif
+#if PPC_NUM_VECTORS > 172
+ .weak vector172, vector173, vector174, vector175
+#endif
+#if PPC_NUM_VECTORS > 176
+ .weak vector176, vector177, vector178, vector179
+#endif
+#if PPC_NUM_VECTORS > 180
+ .weak vector180, vector181, vector182, vector183
+#endif
+#if PPC_NUM_VECTORS > 184
+ .weak vector184, vector185, vector186, vector187
+#endif
+#if PPC_NUM_VECTORS > 188
+ .weak vector188, vector189, vector190, vector191
+#endif
+#if PPC_NUM_VECTORS > 192
+ .weak vector192, vector193, vector194, vector195
+#endif
+#if PPC_NUM_VECTORS > 196
+ .weak vector196, vector197, vector198, vector199
+#endif
+#if PPC_NUM_VECTORS > 200
+ .weak vector200, vector201, vector202, vector203
+#endif
+#if PPC_NUM_VECTORS > 204
+ .weak vector204, vector205, vector206, vector207
+#endif
+#if PPC_NUM_VECTORS > 208
+ .weak vector208, vector209, vector210, vector211
+#endif
+#if PPC_NUM_VECTORS > 212
+ .weak vector212, vector213, vector214, vector215
+#endif
+#if PPC_NUM_VECTORS > 216
+ .weak vector216, vector217, vector218, vector219
+#endif
+#if PPC_NUM_VECTORS > 220
+ .weak vector220, vector221, vector222, vector223
+#endif
+#if PPC_NUM_VECTORS > 224
+ .weak vector224, vector225, vector226, vector227
+#endif
+#if PPC_NUM_VECTORS > 228
+ .weak vector228, vector229, vector230, vector231
+#endif
+#if PPC_NUM_VECTORS > 232
+ .weak vector232, vector233, vector234, vector235
+#endif
+#if PPC_NUM_VECTORS > 236
+ .weak vector236, vector237, vector238, vector239
+#endif
+#if PPC_NUM_VECTORS > 240
+ .weak vector240, vector241, vector242, vector243
+#endif
+#if PPC_NUM_VECTORS > 244
+ .weak vector244, vector245, vector246, vector247
+#endif
+#if PPC_NUM_VECTORS > 248
+ .weak vector248, vector249, vector250, vector251
+#endif
+#if PPC_NUM_VECTORS > 252
+ .weak vector252, vector253, vector254, vector255
+#endif
+#if PPC_NUM_VECTORS > 256
+ .weak vector256, vector257, vector258, vector259
+#endif
+#if PPC_NUM_VECTORS > 260
+ .weak vector260, vector261, vector262, vector263
+#endif
+#if PPC_NUM_VECTORS > 264
+ .weak vector264, vector265, vector266, vector267
+#endif
+#if PPC_NUM_VECTORS > 268
+ .weak vector268, vector269, vector270, vector271
+#endif
+#if PPC_NUM_VECTORS > 272
+ .weak vector272, vector273, vector274, vector275
+#endif
+#if PPC_NUM_VECTORS > 276
+ .weak vector276, vector277, vector278, vector279
+#endif
+#if PPC_NUM_VECTORS > 280
+ .weak vector280, vector281, vector282, vector283
+#endif
+#if PPC_NUM_VECTORS > 284
+ .weak vector284, vector285, vector286, vector287
+#endif
+#if PPC_NUM_VECTORS > 288
+ .weak vector288, vector289, vector290, vector291
+#endif
+#if PPC_NUM_VECTORS > 292
+ .weak vector292, vector293, vector294, vector295
+#endif
+#if PPC_NUM_VECTORS > 296
+ .weak vector296, vector297, vector298, vector299
+#endif
+#if PPC_NUM_VECTORS > 300
+ .weak vector300, vector301, vector302, vector303
+#endif
+#if PPC_NUM_VECTORS > 304
+ .weak vector304, vector305, vector306, vector307
+#endif
+#if PPC_NUM_VECTORS > 308
+ .weak vector308, vector309, vector310, vector311
+#endif
+#if PPC_NUM_VECTORS > 312
+ .weak vector312, vector313, vector314, vector315
+#endif
+#if PPC_NUM_VECTORS > 316
+ .weak vector316, vector317, vector318, vector319
+#endif
+#if PPC_NUM_VECTORS > 320
+ .weak vector320, vector321, vector322, vector323
+#endif
+#if PPC_NUM_VECTORS > 324
+ .weak vector324, vector325, vector326, vector327
+#endif
+#if PPC_NUM_VECTORS > 328
+ .weak vector328, vector329, vector330, vector331
+#endif
+#if PPC_NUM_VECTORS > 332
+ .weak vector332, vector333, vector334, vector335
+#endif
+#if PPC_NUM_VECTORS > 336
+ .weak vector336, vector337, vector338, vector339
+#endif
+#if PPC_NUM_VECTORS > 340
+ .weak vector340, vector341, vector342, vector343
+#endif
+#if PPC_NUM_VECTORS > 344
+ .weak vector344, vector345, vector346, vector347
+#endif
+#if PPC_NUM_VECTORS > 348
+ .weak vector348, vector349, vector350, vector351
+#endif
+#if PPC_NUM_VECTORS > 352
+ .weak vector352, vector353, vector354, vector355
+#endif
+#if PPC_NUM_VECTORS > 356
+ .weak vector356, vector357, vector358, vector359
+#endif
+#if PPC_NUM_VECTORS > 360
+ .weak vector360, vector361, vector362, vector363
+#endif
+#if PPC_NUM_VECTORS > 364
+ .weak vector364, vector365, vector366, vector367
+#endif
+#if PPC_NUM_VECTORS > 368
+ .weak vector368, vector369, vector370, vector371
+#endif
+#if PPC_NUM_VECTORS > 372
+ .weak vector372, vector373, vector374, vector375
+#endif
+#if PPC_NUM_VECTORS > 376
+ .weak vector376, vector377, vector378, vector379
+#endif
+#if PPC_NUM_VECTORS > 380
+ .weak vector380, vector381, vector382, vector383
+#endif
+#if PPC_NUM_VECTORS > 384
+ .weak vector384, vector385, vector386, vector387
+#endif
+#if PPC_NUM_VECTORS > 388
+ .weak vector388, vector389, vector390, vector391
+#endif
+#if PPC_NUM_VECTORS > 392
+ .weak vector392, vector393, vector394, vector395
+#endif
+#if PPC_NUM_VECTORS > 396
+ .weak vector396, vector397, vector398, vector399
+#endif
+#if PPC_NUM_VECTORS > 400
+ .weak vector400, vector401, vector402, vector403
+#endif
+#if PPC_NUM_VECTORS > 404
+ .weak vector404, vector405, vector406, vector407
+#endif
+#if PPC_NUM_VECTORS > 408
+ .weak vector408, vector409, vector410, vector411
+#endif
+#if PPC_NUM_VECTORS > 412
+ .weak vector412, vector413, vector414, vector415
+#endif
+#if PPC_NUM_VECTORS > 416
+ .weak vector416, vector417, vector418, vector419
+#endif
+#if PPC_NUM_VECTORS > 420
+ .weak vector420, vector421, vector422, vector423
+#endif
+#if PPC_NUM_VECTORS > 424
+ .weak vector424, vector425, vector426, vector427
+#endif
+#if PPC_NUM_VECTORS > 428
+ .weak vector428, vector429, vector430, vector431
+#endif
+#if PPC_NUM_VECTORS > 432
+ .weak vector432, vector433, vector434, vector435
+#endif
+#if PPC_NUM_VECTORS > 436
+ .weak vector436, vector437, vector438, vector439
+#endif
+#if PPC_NUM_VECTORS > 440
+ .weak vector440, vector441, vector442, vector443
+#endif
+#if PPC_NUM_VECTORS > 444
+ .weak vector444, vector445, vector446, vector447
+#endif
+#if PPC_NUM_VECTORS > 448
+ .weak vector448, vector449, vector450, vector451
+#endif
+#if PPC_NUM_VECTORS > 452
+ .weak vector452, vector453, vector454, vector455
+#endif
+#if PPC_NUM_VECTORS > 456
+ .weak vector456, vector457, vector458, vector459
+#endif
+#if PPC_NUM_VECTORS > 460
+ .weak vector460, vector461, vector462, vector463
+#endif
+#if PPC_NUM_VECTORS > 464
+ .weak vector464, vector465, vector466, vector467
+#endif
+#if PPC_NUM_VECTORS > 468
+ .weak vector468, vector469, vector470, vector471
+#endif
+#if PPC_NUM_VECTORS > 472
+ .weak vector472, vector473, vector474, vector475
+#endif
+#if PPC_NUM_VECTORS > 476
+ .weak vector476, vector477, vector478, vector479
+#endif
+#if PPC_NUM_VECTORS > 480
+ .weak vector480, vector481, vector482, vector483
+#endif
+#if PPC_NUM_VECTORS > 484
+ .weak vector484, vector485, vector486, vector487
+#endif
+#if PPC_NUM_VECTORS > 488
+ .weak vector488, vector489, vector490, vector491
+#endif
+#if PPC_NUM_VECTORS > 492
+ .weak vector492, vector493, vector494, vector495
+#endif
+#if PPC_NUM_VECTORS > 496
+ .weak vector496, vector497, vector498, vector499
+#endif
+#if PPC_NUM_VECTORS > 500
+ .weak vector500, vector501, vector502, vector503
+#endif
+#if PPC_NUM_VECTORS > 504
+ .weak vector504, vector505, vector506, vector507
+#endif
+#if PPC_NUM_VECTORS > 508
+ .weak vector508, vector509, vector510, vector511
+#endif
+#if PPC_NUM_VECTORS > 512
+ .weak vector512, vector513, vector514, vector515
+#endif
+#if PPC_NUM_VECTORS > 516
+ .weak vector516, vector517, vector518, vector519
+#endif
+#if PPC_NUM_VECTORS > 520
+ .weak vector520, vector521, vector522, vector523
+#endif
+#if PPC_NUM_VECTORS > 524
+ .weak vector524, vector525, vector526, vector527
+#endif
+#if PPC_NUM_VECTORS > 528
+ .weak vector528, vector529, vector530, vector531
+#endif
+#if PPC_NUM_VECTORS > 532
+ .weak vector532, vector533, vector534, vector535
+#endif
+#if PPC_NUM_VECTORS > 536
+ .weak vector536, vector537, vector538, vector539
+#endif
+#if PPC_NUM_VECTORS > 540
+ .weak vector540, vector541, vector542, vector543
+#endif
+#if PPC_NUM_VECTORS > 544
+ .weak vector544, vector545, vector546, vector547
+#endif
+#if PPC_NUM_VECTORS > 548
+ .weak vector548, vector549, vector550, vector551
+#endif
+#if PPC_NUM_VECTORS > 552
+ .weak vector552, vector553, vector554, vector555
+#endif
+#if PPC_NUM_VECTORS > 556
+ .weak vector556, vector557, vector558, vector559
+#endif
+#if PPC_NUM_VECTORS > 560
+ .weak vector560, vector561, vector562, vector563
+#endif
+#if PPC_NUM_VECTORS > 564
+ .weak vector564, vector565, vector566, vector567
+#endif
+#if PPC_NUM_VECTORS > 568
+ .weak vector568, vector569, vector570, vector571
+#endif
+#if PPC_NUM_VECTORS > 572
+ .weak vector572, vector573, vector574, vector575
+#endif
+#if PPC_NUM_VECTORS > 576
+ .weak vector576, vector577, vector578, vector579
+#endif
+#if PPC_NUM_VECTORS > 580
+ .weak vector580, vector581, vector582, vector583
+#endif
+#if PPC_NUM_VECTORS > 584
+ .weak vector584, vector585, vector586, vector587
+#endif
+#if PPC_NUM_VECTORS > 588
+ .weak vector588, vector589, vector590, vector591
+#endif
+#if PPC_NUM_VECTORS > 592
+ .weak vector592, vector593, vector594, vector595
+#endif
+#if PPC_NUM_VECTORS > 596
+ .weak vector596, vector597, vector598, vector599
+#endif
+#if PPC_NUM_VECTORS > 600
+ .weak vector600, vector601, vector602, vector603
+#endif
+#if PPC_NUM_VECTORS > 604
+ .weak vector604, vector605, vector606, vector607
+#endif
+#if PPC_NUM_VECTORS > 608
+ .weak vector608, vector609, vector610, vector611
+#endif
+#if PPC_NUM_VECTORS > 612
+ .weak vector612, vector613, vector614, vector615
+#endif
+#if PPC_NUM_VECTORS > 616
+ .weak vector616, vector617, vector618, vector619
+#endif
+#if PPC_NUM_VECTORS > 620
+ .weak vector620, vector621, vector622, vector623
+#endif
+#if PPC_NUM_VECTORS > 624
+ .weak vector624, vector625, vector626, vector627
+#endif
+#if PPC_NUM_VECTORS > 628
+ .weak vector628, vector629, vector630, vector631
+#endif
+#if PPC_NUM_VECTORS > 632
+ .weak vector632, vector633, vector634, vector635
+#endif
+#if PPC_NUM_VECTORS > 636
+ .weak vector636, vector637, vector638, vector639
+#endif
+#if PPC_NUM_VECTORS > 640
+ .weak vector640, vector641, vector642, vector643
+#endif
+#if PPC_NUM_VECTORS > 644
+ .weak vector644, vector645, vector646, vector647
+#endif
+#if PPC_NUM_VECTORS > 648
+ .weak vector648, vector649, vector650, vector651
+#endif
+#if PPC_NUM_VECTORS > 652
+ .weak vector652, vector653, vector654, vector655
+#endif
+#if PPC_NUM_VECTORS > 656
+ .weak vector656, vector657, vector658, vector659
+#endif
+#if PPC_NUM_VECTORS > 660
+ .weak vector660, vector661, vector662, vector663
+#endif
+#if PPC_NUM_VECTORS > 664
+ .weak vector664, vector665, vector666, vector667
+#endif
+#if PPC_NUM_VECTORS > 668
+ .weak vector668, vector669, vector670, vector671
+#endif
+#if PPC_NUM_VECTORS > 672
+ .weak vector672, vector673, vector674, vector675
+#endif
+#if PPC_NUM_VECTORS > 676
+ .weak vector676, vector677, vector678, vector679
+#endif
+#if PPC_NUM_VECTORS > 680
+ .weak vector680, vector681, vector682, vector683
+#endif
+#if PPC_NUM_VECTORS > 684
+ .weak vector684, vector685, vector686, vector687
+#endif
+#if PPC_NUM_VECTORS > 688
+ .weak vector688, vector689, vector690, vector691
+#endif
+#if PPC_NUM_VECTORS > 692
+ .weak vector692, vector693, vector694, vector695
+#endif
+#if PPC_NUM_VECTORS > 696
+ .weak vector696, vector697, vector698, vector699
+#endif
+#if PPC_NUM_VECTORS > 700
+ .weak vector700, vector701, vector702, vector703
+#endif
+#if PPC_NUM_VECTORS > 704
+ .weak vector704, vector705, vector706, vector707
+#endif
+#if PPC_NUM_VECTORS > 708
+ .weak vector708, vector709, vector710, vector711
+#endif
+#if PPC_NUM_VECTORS > 712
+ .weak vector712, vector713, vector714, vector715
+#endif
+#if PPC_NUM_VECTORS > 716
+ .weak vector716, vector717, vector718, vector719
+#endif
+#if PPC_NUM_VECTORS > 720
+ .weak vector720, vector721, vector722, vector723
+#endif
+#if PPC_NUM_VECTORS > 724
+ .weak vector724, vector725, vector726, vector727
+#endif
+#if PPC_NUM_VECTORS > 728
+ .weak vector728, vector729, vector730, vector731
+#endif
+#if PPC_NUM_VECTORS > 732
+ .weak vector732, vector733, vector734, vector735
+#endif
+#if PPC_NUM_VECTORS > 736
+ .weak vector736, vector737, vector738, vector739
+#endif
+#if PPC_NUM_VECTORS > 740
+ .weak vector740, vector741, vector742, vector743
+#endif
+#if PPC_NUM_VECTORS > 744
+ .weak vector744, vector745, vector746, vector747
+#endif
+#if PPC_NUM_VECTORS > 748
+ .weak vector748, vector749, vector750, vector751
+#endif
+#if PPC_NUM_VECTORS > 752
+ .weak vector752, vector753, vector754, vector755
+#endif
+#if PPC_NUM_VECTORS > 756
+ .weak vector756, vector757, vector758, vector759
+#endif
+#if PPC_NUM_VECTORS > 760
+ .weak vector760, vector761, vector762, vector763
+#endif
+#if PPC_NUM_VECTORS > 764
+ .weak vector764, vector765, vector766, vector767
+#endif
+#if PPC_NUM_VECTORS > 768
+ .weak vector768, vector769, vector770, vector771
+#endif
+#if PPC_NUM_VECTORS > 772
+ .weak vector772, vector773, vector774, vector775
+#endif
+#if PPC_NUM_VECTORS > 776
+ .weak vector776, vector777, vector778, vector779
+#endif
+#if PPC_NUM_VECTORS > 780
+ .weak vector780, vector781, vector782, vector783
+#endif
+#if PPC_NUM_VECTORS > 784
+ .weak vector784, vector785, vector786, vector787
+#endif
+#if PPC_NUM_VECTORS > 788
+ .weak vector788, vector789, vector790, vector791
+#endif
+#if PPC_NUM_VECTORS > 792
+ .weak vector792, vector793, vector794, vector795
+#endif
+#if PPC_NUM_VECTORS > 796
+ .weak vector796, vector797, vector798, vector799
+#endif
+#if PPC_NUM_VECTORS > 800
+ .weak vector800, vector801, vector802, vector803
+#endif
+#if PPC_NUM_VECTORS > 804
+ .weak vector804, vector805, vector806, vector807
+#endif
+#if PPC_NUM_VECTORS > 808
+ .weak vector808, vector809, vector810, vector811
+#endif
+#if PPC_NUM_VECTORS > 812
+ .weak vector812, vector813, vector814, vector815
+#endif
+#if PPC_NUM_VECTORS > 816
+ .weak vector816, vector817, vector818, vector819
+#endif
+#if PPC_NUM_VECTORS > 820
+ .weak vector820, vector821, vector822, vector823
+#endif
+#if PPC_NUM_VECTORS > 824
+ .weak vector824, vector825, vector826, vector827
+#endif
+#if PPC_NUM_VECTORS > 828
+ .weak vector828, vector829, vector830, vector831
+#endif
+#if PPC_NUM_VECTORS > 832
+ .weak vector832, vector833, vector834, vector835
+#endif
+#if PPC_NUM_VECTORS > 836
+ .weak vector836, vector837, vector838, vector839
+#endif
+#if PPC_NUM_VECTORS > 840
+ .weak vector840, vector841, vector842, vector843
+#endif
+#if PPC_NUM_VECTORS > 844
+ .weak vector844, vector845, vector846, vector847
+#endif
+#if PPC_NUM_VECTORS > 848
+ .weak vector848, vector849, vector850, vector851
+#endif
+#if PPC_NUM_VECTORS > 852
+ .weak vector852, vector853, vector854, vector855
+#endif
+#if PPC_NUM_VECTORS > 856
+ .weak vector856, vector857, vector858, vector859
+#endif
+#if PPC_NUM_VECTORS > 860
+ .weak vector860, vector861, vector862, vector863
+#endif
+#if PPC_NUM_VECTORS > 864
+ .weak vector864, vector865, vector866, vector867
+#endif
+#if PPC_NUM_VECTORS > 868
+ .weak vector868, vector869, vector870, vector871
+#endif
+#if PPC_NUM_VECTORS > 872
+ .weak vector872, vector873, vector874, vector875
+#endif
+#if PPC_NUM_VECTORS > 876
+ .weak vector876, vector877, vector878, vector879
+#endif
+#if PPC_NUM_VECTORS > 880
+ .weak vector880, vector881, vector882, vector883
+#endif
+#if PPC_NUM_VECTORS > 884
+ .weak vector884, vector885, vector886, vector887
+#endif
+#if PPC_NUM_VECTORS > 888
+ .weak vector888, vector889, vector890, vector891
+#endif
+#if PPC_NUM_VECTORS > 892
+ .weak vector892, vector893, vector894, vector895
+#endif
+#if PPC_NUM_VECTORS > 896
+ .weak vector896, vector897, vector898, vector899
+#endif
+#if PPC_NUM_VECTORS > 900
+ .weak vector900, vector901, vector902, vector903
+#endif
+#if PPC_NUM_VECTORS > 904
+ .weak vector904, vector905, vector906, vector907
+#endif
+#if PPC_NUM_VECTORS > 908
+ .weak vector908, vector909, vector910, vector911
+#endif
+#if PPC_NUM_VECTORS > 912
+ .weak vector912, vector913, vector914, vector915
+#endif
+#if PPC_NUM_VECTORS > 916
+ .weak vector916, vector917, vector918, vector919
+#endif
+#if PPC_NUM_VECTORS > 920
+ .weak vector920, vector921, vector922, vector923
+#endif
+#if PPC_NUM_VECTORS > 924
+ .weak vector924, vector925, vector926, vector927
+#endif
+#if PPC_NUM_VECTORS > 928
+ .weak vector928, vector929, vector930, vector931
+#endif
+#if PPC_NUM_VECTORS > 932
+ .weak vector932, vector933, vector934, vector935
+#endif
+#if PPC_NUM_VECTORS > 936
+ .weak vector936, vector937, vector938, vector939
+#endif
+#if PPC_NUM_VECTORS > 940
+ .weak vector940, vector941, vector942, vector943
+#endif
+#if PPC_NUM_VECTORS > 944
+ .weak vector944, vector945, vector946, vector947
+#endif
+#if PPC_NUM_VECTORS > 948
+ .weak vector948, vector949, vector950, vector951
+#endif
+#if PPC_NUM_VECTORS > 952
+ .weak vector952, vector953, vector954, vector955
+#endif
+#if PPC_NUM_VECTORS > 956
+ .weak vector956, vector957, vector958, vector959
+#endif
+#if PPC_NUM_VECTORS > 960
+ .weak vector960, vector961, vector962, vector963
+#endif
+#if PPC_NUM_VECTORS > 964
+ .weak vector964, vector965, vector966, vector967
+#endif
+#if PPC_NUM_VECTORS > 968
+ .weak vector968, vector969, vector970, vector971
+#endif
+#if PPC_NUM_VECTORS > 972
+ .weak vector972, vector973, vector974, vector975
+#endif
+#if PPC_NUM_VECTORS > 976
+ .weak vector976, vector977, vector978, vector979
+#endif
+#if PPC_NUM_VECTORS > 980
+ .weak vector980, vector981, vector982, vector983
+#endif
+#if PPC_NUM_VECTORS > 984
+ .weak vector984, vector985, vector986, vector987
+#endif
+#if PPC_NUM_VECTORS > 988
+ .weak vector988, vector989, vector990, vector991
+#endif
+#if PPC_NUM_VECTORS > 992
+ .weak vector992, vector993, vector994, vector995
+#endif
+#if PPC_NUM_VECTORS > 996
+ .weak vector996, vector997, vector998, vector999
+#endif
+#if PPC_NUM_VECTORS > 1000
+ .weak vector1000, vector1001, vector1002, vector1003
+#endif
+#if PPC_NUM_VECTORS > 1004
+ .weak vector1004, vector1005, vector1006, vector1007
+#endif
+#if PPC_NUM_VECTORS > 1008
+ .weak vector1008, vector1009, vector1010, vector1011
+#endif
+#if PPC_NUM_VECTORS > 1012
+ .weak vector1012, vector1013, vector1014, vector1015
+#endif
+#if PPC_NUM_VECTORS > 1016
+ .weak vector1016, vector1017, vector1018, vector1019
+#endif
+#if PPC_NUM_VECTORS > 1020
+ .weak vector1020, vector1021, vector1022, vector1023
+#endif
+
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+vector1010:
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+vector1017:
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+vector1019:
+vector1020:
+vector1021:
+vector1022:
+vector1023:
+ e_b _unhandled_irq
+
+ .weak _unhandled_irq
+ .type _unhandled_irq, @function
+_unhandled_irq:
+ e_b _unhandled_irq
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/vectors.h b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/vectors.h new file mode 100644 index 0000000..bb36b54 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GCC/vectors.h @@ -0,0 +1,78 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file vectors.h
+ * @brief ISR vector module header.
+ *
+ * @addtogroup PPC_GCC_CORE
+ * @{
+ */
+
+#ifndef VECTORS_H
+#define VECTORS_H
+
+#include "ppcparams.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+#if !defined(__DOXYGEN__)
+extern uint32_t _vectors[PPC_NUM_VECTORS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _unhandled_irq(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* VECTORS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/crt0.s b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/crt0.s new file mode 100644 index 0000000..5b2658c --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/crt0.s @@ -0,0 +1,244 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file GCC/crt0.S
+ * @brief Generic PowerPC startup file for GCC.
+ *
+ * @addtogroup PPC_GCC_CORE
+ * @{
+ */
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
+#define CRT0_STACKS_FILL_PATTERN 0x55555555
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
+#define CRT0_INIT_STACKS TRUE
+#endif
+
+/**
+ * @brief DATA segment initialization switch.
+ */
+#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
+#define CRT0_INIT_DATA TRUE
+#endif
+
+/**
+ * @brief BSS segment initialization switch.
+ */
+#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
+#define CRT0_INIT_BSS TRUE
+#endif
+
+/**
+ * @brief Constructors invocation switch.
+ */
+#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_CONSTRUCTORS TRUE
+#endif
+
+/**
+ * @brief Destructors invocation switch.
+ */
+#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_DESTRUCTORS TRUE
+#endif
+
+/*===========================================================================*/
+/* Code section. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+
+ .vle
+
+ .section .crt0, "axv"
+ .align 2
+ .globl _boot_address
+ .type _boot_address, @function
+_boot_address:
+ /* Stack setup.*/
+ e_lis r1, __process_stack_end__@h
+ e_or2i r1, __process_stack_end__@l
+ se_li r0, 0
+ e_stwu r0, -8(r1)
+
+ /* Small sections registers initialization.*/
+ e_lis r2, __sdata2_start__@h
+ e_or2i r2, __sdata2_start__@l
+ e_lis r13, __sdata_start__@h
+ e_or2i r13, __sdata_start__@l
+
+ /* Early initialization.*/
+ e_bl __early_init
+
+#if CRT0_INIT_STACKS == TRUE
+ /* Stacks fill pattern.*/
+ e_lis r7, CRT0_STACKS_FILL_PATTERN@h
+ e_or2i r7, CRT0_STACKS_FILL_PATTERN@l
+
+ /* IRQ Stack initialization. Note, the architecture does not use this
+ stack, the size is usually zero. An OS can have special SW handling
+ and require this. A 4 bytes alignment is assmend and required.*/
+ e_lis r4, __irq_stack_base__@h
+ e_or2i r4, __irq_stack_base__@l
+ e_lis r5, __irq_stack_end__@h
+ e_or2i r5, __irq_stack_end__@l
+.irqsloop:
+ se_cmpl r4, r5
+ se_bge .irqsend
+ se_stw r7, 0(r4)
+ se_addi r4, 4
+ se_b .irqsloop
+.irqsend:
+
+ /* Process Stack initialization. Note, does not overwrite the already
+ written EABI frame. A 4 bytes alignment is assmend and required.*/
+ e_lis r4, __process_stack_base__@h
+ e_or2i r4, __process_stack_base__@l
+ e_lis r5, (__process_stack_end__ - 8)@h
+ e_or2i r5, (__process_stack_end__ - 8)@l
+.prcsloop:
+ se_cmpl r4, r5
+ se_bge .prcsend
+ se_stw r7, 0(r4)
+ se_addi r4, 4
+ se_b .prcsloop
+.prcsend:
+#endif
+
+#if CRT0_INIT_BSS == TRUE
+ /* BSS clearing.*/
+ e_lis r4, __bss_start__@h
+ e_or2i r4, __bss_start__@l
+ e_lis r5, __bss_end__@h
+ e_or2i r5, __bss_end__@l
+ se_li r7, 0
+.bssloop:
+ se_cmpl r4, r5
+ se_bge .bssend
+ se_stw r7, 0(r4)
+ se_addi r4, 4
+ se_b .bssloop
+.bssend:
+#endif
+
+#if CRT0_INIT_DATA == TRUE
+ /* DATA initialization.*/
+ e_lis r4, __romdata_start__@h
+ e_or2i r4, __romdata_start__@l
+ e_lis r5, __data_start__@h
+ e_or2i r5, __data_start__@l
+ e_lis r6, __data_end__@h
+ e_or2i r6, __data_end__@l
+.dataloop:
+ se_cmpl r5, r6
+ se_bge .dataend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .dataloop
+.dataend:
+#endif
+
+ /* Late initialization.*/
+ e_bl __late_init
+
+#if CRT0_CALL_CONSTRUCTORS == TRUE
+ /* Constructors invocation.*/
+ e_lis r4, __init_array_start@h
+ e_or2i r4, __init_array_start@l
+ e_lis r5, __init_array_end@h
+ e_or2i r5, __init_array_end@l
+.iniloop:
+ se_cmpl r4, r5
+ se_bge .iniend
+ se_lwz r6, 0(r4)
+ mtctr r6
+ se_addi r4, 4
+ se_bctrl
+ se_b .iniloop
+.iniend:
+#endif
+
+ /* Main program invocation.*/
+ e_bl main
+
+#if CRT0_CALL_DESTRUCTORS == TRUE
+ /* Destructors invocation.*/
+ e_lis r4, __fini_array_start@h
+ e_or2i r4, __fini_array_start@l
+ e_lis r5, __fini_array_end@h
+ e_or2i r5, __fini_array_end@l
+.finiloop:
+ se_cmpl r4, r5
+ se_bge .finiend
+ se_lwz r6, 0(r4)
+ mtctr r6
+ se_addi r4, 4
+ se_bctrl
+ se_b .finiloop
+.finiend:
+#endif
+
+ /* Branching to the defined exit handler.*/
+ e_b __default_exit
+
+ /* Default main exit code, infinite loop.*/
+ .weak __default_exit
+ .type __default_exit, @function
+__default_exit:
+ e_b __default_exit
+
+ /* Default early initialization code, none.*/
+ .weak __early_init
+ .type __early_init, @function
+__early_init:
+ se_blr
+
+ /* Default late initialization code, none.*/
+ .weak __late_init
+ .type __late_init, @function
+__late_init:
+ se_blr
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560B50.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560B50.ld new file mode 100644 index 0000000..b2bfaf0 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560B50.ld @@ -0,0 +1,165 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560B50 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 512k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 32k
+}
+
+OPTION ("-e=_reset_address")
+
+SECTIONS
+{
+ .boot0 ALIGN(16) :
+ {
+ *(.boot)
+ *(.handlers)
+ *(.crt0)
+ } > flash
+
+ .vectors ALIGN(0x800) :
+ {
+ /* The vectors table requires a 2kB alignment.*/
+ *(.vectors)
+ } > flash
+
+ .ivors ALIGN(0x1000) :
+ {
+ /* The IVORs table requires a 4kB alignment.*/
+ __ivpr_base__ = .;
+ *(.ivors)
+ } > flash
+
+ constructors ALIGN(4) :
+ {
+ PROVIDE(__init_array_start = .);
+ "*(.init_array.*)"
+ *(.init_array)
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors ALIGN(4) :
+ {
+ PROVIDE(__fini_array_start = .);
+ *(.fini_array)
+ "*(.fini_array.*)"
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .vletext ALIGN(16) :
+ {
+ *(.vletext)
+ "*(.vletext.*)"
+ } > flash
+
+ .text ALIGN(16) :
+ {
+ *(.text)
+ "*(.text.*)"
+ } > flash
+
+ .rodata ALIGN(16) :
+ {
+ *(.rodata)
+ "*(.rodata.*)"
+ *(.rodata1)
+ } > flash
+
+ .sdata2 ALIGN(16) :
+ {
+ __sdata2_start__ = . + 0x8000;
+ *(.sdata2)
+ "*(.sdata2.*)"
+ *(.sbss2)
+ "*(.sbss2.*)"
+ } > flash
+
+ .stacks ALIGN(16) :
+ {
+ . = ALIGN(8);
+ __irq_stack_base__ = .;
+ . += __irq_stack_size__;
+ . = ALIGN(8);
+ __irq_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .romdatastart ALIGN(16) :
+ {
+ __romdata_start__ = .;
+ } > flash
+
+ .data ALIGN(4) : AT(__romdata_start__)
+ {
+ __data_start__ = .;
+ *(.data)
+ "*(.data.*)"
+ . = ALIGN(4);
+ *(.ramtext)
+ . = ALIGN(4);
+ __data_end__ = .;
+ } > ram
+
+ __romsdata_start__ = (__data_end__ - __data_start__) + __romdata_start__;
+
+ .sdata ALIGN(4) : AT(__romsdata_start__)
+ {
+ __sdata_start__ = . + 0x8000;
+ *(.sdata)
+ "*(.sdata.*)"
+ } > ram
+
+ .sbss ALIGN(4) :
+ {
+ __bss_start__ = .;
+ *(.sbss)
+ "*(.sbss.*)"
+ *(.scommon)
+ } > ram
+
+ .bss ALIGN(4) :
+ {
+ *(.bss)
+ "*(.bss.*)"
+ *(COMMON)
+ __bss_end__ = .;
+ } > ram
+
+ __flash_size__ = SIZEOF(flash);
+ __flash_start__ = ADDR(flash);
+ __flash_end__ = ENDADDR(flash);
+
+ __dataflash_size__ = SIZEOF(dataflash);
+ __dataflash_start__ = ADDR(dataflash);
+ __dataflash_end__ = ENDADDR(dataflash);
+
+ __ram_size__ = SIZEOF(ram);
+ __ram_start__ = ADDR(ram);
+ __ram_end__ = ENDADDR(ram);
+
+ __heap_base__ = __bss_end__;
+ __heap_end__ = __ram_end__;
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560B60.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560B60.ld new file mode 100644 index 0000000..548d0d8 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560B60.ld @@ -0,0 +1,165 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560B60 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 1024k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 80k
+}
+
+OPTION ("-e=_reset_address")
+
+SECTIONS
+{
+ .boot0 ALIGN(16) :
+ {
+ *(.boot)
+ *(.handlers)
+ *(.crt0)
+ } > flash
+
+ .vectors ALIGN(0x800) :
+ {
+ /* The vectors table requires a 2kB alignment.*/
+ *(.vectors)
+ } > flash
+
+ .ivors ALIGN(0x1000) :
+ {
+ /* The IVORs table requires a 4kB alignment.*/
+ __ivpr_base__ = .;
+ *(.ivors)
+ } > flash
+
+ constructors ALIGN(4) :
+ {
+ PROVIDE(__init_array_start = .);
+ "*(.init_array.*)"
+ *(.init_array)
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors ALIGN(4) :
+ {
+ PROVIDE(__fini_array_start = .);
+ *(.fini_array)
+ "*(.fini_array.*)"
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .vletext ALIGN(16) :
+ {
+ *(.vletext)
+ "*(.vletext.*)"
+ } > flash
+
+ .text ALIGN(16) :
+ {
+ *(.text)
+ "*(.text.*)"
+ } > flash
+
+ .rodata ALIGN(16) :
+ {
+ *(.rodata)
+ "*(.rodata.*)"
+ *(.rodata1)
+ } > flash
+
+ .sdata2 ALIGN(16) :
+ {
+ __sdata2_start__ = . + 0x8000;
+ *(.sdata2)
+ "*(.sdata2.*)"
+ *(.sbss2)
+ "*(.sbss2.*)"
+ } > flash
+
+ .stacks ALIGN(16) :
+ {
+ . = ALIGN(8);
+ __irq_stack_base__ = .;
+ . += __irq_stack_size__;
+ . = ALIGN(8);
+ __irq_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .romdatastart ALIGN(16) :
+ {
+ __romdata_start__ = .;
+ } > flash
+
+ .data ALIGN(4) : AT(__romdata_start__)
+ {
+ __data_start__ = .;
+ *(.data)
+ "*(.data.*)"
+ . = ALIGN(4);
+ *(.ramtext)
+ . = ALIGN(4);
+ __data_end__ = .;
+ } > ram
+
+ __romsdata_start__ = (__data_end__ - __data_start__) + __romdata_start__;
+
+ .sdata ALIGN(4) : AT(__romsdata_start__)
+ {
+ __sdata_start__ = . + 0x8000;
+ *(.sdata)
+ "*(.sdata.*)"
+ } > ram
+
+ .sbss ALIGN(4) :
+ {
+ __bss_start__ = .;
+ *(.sbss)
+ "*(.sbss.*)"
+ *(.scommon)
+ } > ram
+
+ .bss ALIGN(4) :
+ {
+ *(.bss)
+ "*(.bss.*)"
+ *(COMMON)
+ __bss_end__ = .;
+ } > ram
+
+ __flash_size__ = SIZEOF(flash);
+ __flash_start__ = ADDR(flash);
+ __flash_end__ = ENDADDR(flash);
+
+ __dataflash_size__ = SIZEOF(dataflash);
+ __dataflash_start__ = ADDR(dataflash);
+ __dataflash_end__ = ENDADDR(dataflash);
+
+ __ram_size__ = SIZEOF(ram);
+ __ram_start__ = ADDR(ram);
+ __ram_end__ = ENDADDR(ram);
+
+ __heap_base__ = __bss_end__;
+ __heap_end__ = __ram_end__;
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560B64.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560B64.ld new file mode 100644 index 0000000..39fb141 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560B64.ld @@ -0,0 +1,165 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560B64 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 1536k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 96k
+}
+
+OPTION ("-e=_reset_address")
+
+SECTIONS
+{
+ .boot0 ALIGN(16) :
+ {
+ *(.boot)
+ *(.handlers)
+ *(.crt0)
+ } > flash
+
+ .vectors ALIGN(0x800) :
+ {
+ /* The vectors table requires a 2kB alignment.*/
+ *(.vectors)
+ } > flash
+
+ .ivors ALIGN(0x1000) :
+ {
+ /* The IVORs table requires a 4kB alignment.*/
+ __ivpr_base__ = .;
+ *(.ivors)
+ } > flash
+
+ constructors ALIGN(4) :
+ {
+ PROVIDE(__init_array_start = .);
+ "*(.init_array.*)"
+ *(.init_array)
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors ALIGN(4) :
+ {
+ PROVIDE(__fini_array_start = .);
+ *(.fini_array)
+ "*(.fini_array.*)"
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .vletext ALIGN(16) :
+ {
+ *(.vletext)
+ "*(.vletext.*)"
+ } > flash
+
+ .text ALIGN(16) :
+ {
+ *(.text)
+ "*(.text.*)"
+ } > flash
+
+ .rodata ALIGN(16) :
+ {
+ *(.rodata)
+ "*(.rodata.*)"
+ *(.rodata1)
+ } > flash
+
+ .sdata2 ALIGN(16) :
+ {
+ __sdata2_start__ = . + 0x8000;
+ *(.sdata2)
+ "*(.sdata2.*)"
+ *(.sbss2)
+ "*(.sbss2.*)"
+ } > flash
+
+ .stacks ALIGN(16) :
+ {
+ . = ALIGN(8);
+ __irq_stack_base__ = .;
+ . += __irq_stack_size__;
+ . = ALIGN(8);
+ __irq_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .romdatastart ALIGN(16) :
+ {
+ __romdata_start__ = .;
+ } > flash
+
+ .data ALIGN(4) : AT(__romdata_start__)
+ {
+ __data_start__ = .;
+ *(.data)
+ "*(.data.*)"
+ . = ALIGN(4);
+ *(.ramtext)
+ . = ALIGN(4);
+ __data_end__ = .;
+ } > ram
+
+ __romsdata_start__ = (__data_end__ - __data_start__) + __romdata_start__;
+
+ .sdata ALIGN(4) : AT(__romsdata_start__)
+ {
+ __sdata_start__ = . + 0x8000;
+ *(.sdata)
+ "*(.sdata.*)"
+ } > ram
+
+ .sbss ALIGN(4) :
+ {
+ __bss_start__ = .;
+ *(.sbss)
+ "*(.sbss.*)"
+ *(.scommon)
+ } > ram
+
+ .bss ALIGN(4) :
+ {
+ *(.bss)
+ "*(.bss.*)"
+ *(COMMON)
+ __bss_end__ = .;
+ } > ram
+
+ __flash_size__ = SIZEOF(flash);
+ __flash_start__ = ADDR(flash);
+ __flash_end__ = ENDADDR(flash);
+
+ __dataflash_size__ = SIZEOF(dataflash);
+ __dataflash_start__ = ADDR(dataflash);
+ __dataflash_end__ = ENDADDR(dataflash);
+
+ __ram_size__ = SIZEOF(ram);
+ __ram_start__ = ADDR(ram);
+ __ram_end__ = ENDADDR(ram);
+
+ __heap_base__ = __bss_end__;
+ __heap_end__ = __ram_end__;
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560D40.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560D40.ld new file mode 100644 index 0000000..11dffc6 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560D40.ld @@ -0,0 +1,165 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560D40 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 256k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 16k
+}
+
+OPTION ("-e=_reset_address")
+
+SECTIONS
+{
+ .boot0 ALIGN(16) :
+ {
+ *(.boot)
+ *(.handlers)
+ *(.crt0)
+ } > flash
+
+ .vectors ALIGN(0x800) :
+ {
+ /* The vectors table requires a 2kB alignment.*/
+ *(.vectors)
+ } > flash
+
+ .ivors ALIGN(0x1000) :
+ {
+ /* The IVORs table requires a 4kB alignment.*/
+ __ivpr_base__ = .;
+ *(.ivors)
+ } > flash
+
+ constructors ALIGN(4) :
+ {
+ PROVIDE(__init_array_start = .);
+ "*(.init_array.*)"
+ *(.init_array)
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors ALIGN(4) :
+ {
+ PROVIDE(__fini_array_start = .);
+ *(.fini_array)
+ "*(.fini_array.*)"
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .vletext ALIGN(16) :
+ {
+ *(.vletext)
+ "*(.vletext.*)"
+ } > flash
+
+ .text ALIGN(16) :
+ {
+ *(.text)
+ "*(.text.*)"
+ } > flash
+
+ .rodata ALIGN(16) :
+ {
+ *(.rodata)
+ "*(.rodata.*)"
+ *(.rodata1)
+ } > flash
+
+ .sdata2 ALIGN(16) :
+ {
+ __sdata2_start__ = . + 0x8000;
+ *(.sdata2)
+ "*(.sdata2.*)"
+ *(.sbss2)
+ "*(.sbss2.*)"
+ } > flash
+
+ .stacks ALIGN(16) :
+ {
+ . = ALIGN(8);
+ __irq_stack_base__ = .;
+ . += __irq_stack_size__;
+ . = ALIGN(8);
+ __irq_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .romdatastart ALIGN(16) :
+ {
+ __romdata_start__ = .;
+ } > flash
+
+ .data ALIGN(4) : AT(__romdata_start__)
+ {
+ __data_start__ = .;
+ *(.data)
+ "*(.data.*)"
+ . = ALIGN(4);
+ *(.ramtext)
+ . = ALIGN(4);
+ __data_end__ = .;
+ } > ram
+
+ __romsdata_start__ = (__data_end__ - __data_start__) + __romdata_start__;
+
+ .sdata ALIGN(4) : AT(__romsdata_start__)
+ {
+ __sdata_start__ = . + 0x8000;
+ *(.sdata)
+ "*(.sdata.*)"
+ } > ram
+
+ .sbss ALIGN(4) :
+ {
+ __bss_start__ = .;
+ *(.sbss)
+ "*(.sbss.*)"
+ *(.scommon)
+ } > ram
+
+ .bss ALIGN(4) :
+ {
+ *(.bss)
+ "*(.bss.*)"
+ *(COMMON)
+ __bss_end__ = .;
+ } > ram
+
+ __flash_size__ = SIZEOF(flash);
+ __flash_start__ = ADDR(flash);
+ __flash_end__ = ENDADDR(flash);
+
+ __dataflash_size__ = SIZEOF(dataflash);
+ __dataflash_start__ = ADDR(dataflash);
+ __dataflash_end__ = ENDADDR(dataflash);
+
+ __ram_size__ = SIZEOF(ram);
+ __ram_start__ = ADDR(ram);
+ __ram_end__ = ENDADDR(ram);
+
+ __heap_base__ = __bss_end__;
+ __heap_end__ = __ram_end__;
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560P50.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560P50.ld new file mode 100644 index 0000000..e4afb2a --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC560P50.ld @@ -0,0 +1,165 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560P50 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 512k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 40k
+}
+
+OPTION ("-e=_reset_address")
+
+SECTIONS
+{
+ .boot0 ALIGN(16) :
+ {
+ *(.boot)
+ *(.handlers)
+ *(.crt0)
+ } > flash
+
+ .vectors ALIGN(0x800) :
+ {
+ /* The vectors table requires a 2kB alignment.*/
+ *(.vectors)
+ } > flash
+
+ .ivors ALIGN(0x1000) :
+ {
+ /* The IVORs table requires a 4kB alignment.*/
+ __ivpr_base__ = .;
+ *(.ivors)
+ } > flash
+
+ constructors ALIGN(4) :
+ {
+ PROVIDE(__init_array_start = .);
+ "*(.init_array.*)"
+ *(.init_array)
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors ALIGN(4) :
+ {
+ PROVIDE(__fini_array_start = .);
+ *(.fini_array)
+ "*(.fini_array.*)"
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .vletext ALIGN(16) :
+ {
+ *(.vletext)
+ "*(.vletext.*)"
+ } > flash
+
+ .text ALIGN(16) :
+ {
+ *(.text)
+ "*(.text.*)"
+ } > flash
+
+ .rodata ALIGN(16) :
+ {
+ *(.rodata)
+ "*(.rodata.*)"
+ *(.rodata1)
+ } > flash
+
+ .sdata2 ALIGN(16) :
+ {
+ __sdata2_start__ = . + 0x8000;
+ *(.sdata2)
+ "*(.sdata2.*)"
+ *(.sbss2)
+ "*(.sbss2.*)"
+ } > flash
+
+ .stacks ALIGN(16) :
+ {
+ . = ALIGN(8);
+ __irq_stack_base__ = .;
+ . += __irq_stack_size__;
+ . = ALIGN(8);
+ __irq_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .romdatastart ALIGN(16) :
+ {
+ __romdata_start__ = .;
+ } > flash
+
+ .data ALIGN(4) : AT(__romdata_start__)
+ {
+ __data_start__ = .;
+ *(.data)
+ "*(.data.*)"
+ . = ALIGN(4);
+ *(.ramtext)
+ . = ALIGN(4);
+ __data_end__ = .;
+ } > ram
+
+ __romsdata_start__ = (__data_end__ - __data_start__) + __romdata_start__;
+
+ .sdata ALIGN(4) : AT(__romsdata_start__)
+ {
+ __sdata_start__ = . + 0x8000;
+ *(.sdata)
+ "*(.sdata.*)"
+ } > ram
+
+ .sbss ALIGN(4) :
+ {
+ __bss_start__ = .;
+ *(.sbss)
+ "*(.sbss.*)"
+ *(.scommon)
+ } > ram
+
+ .bss ALIGN(4) :
+ {
+ *(.bss)
+ "*(.bss.*)"
+ *(COMMON)
+ __bss_end__ = .;
+ } > ram
+
+ __flash_size__ = SIZEOF(flash);
+ __flash_start__ = ADDR(flash);
+ __flash_end__ = ENDADDR(flash);
+
+ __dataflash_size__ = SIZEOF(dataflash);
+ __dataflash_start__ = ADDR(dataflash);
+ __dataflash_end__ = ENDADDR(dataflash);
+
+ __ram_size__ = SIZEOF(ram);
+ __ram_start__ = ADDR(ram);
+ __ram_end__ = ENDADDR(ram);
+
+ __heap_base__ = __bss_end__;
+ __heap_end__ = __ram_end__;
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC56EC74.ld b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC56EC74.ld new file mode 100644 index 0000000..b935340 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/ld/SPC56EC74.ld @@ -0,0 +1,159 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC56EC74 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 3M
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 256k
+}
+
+OPTION ("-e=_reset_address")
+
+SECTIONS
+{
+ .boot0 ALIGN(16) :
+ {
+ __ivpr_base__ = .;
+ *(.boot)
+ *(.handlers)
+ *(.crt0)
+ } > flash
+
+ .vectors ALIGN(0x800) :
+ {
+ /* The vectors table requires a 2kB alignment.*/
+ *(.vectors)
+ } > flash
+
+ constructors ALIGN(4) :
+ {
+ PROVIDE(__init_array_start = .);
+ "*(.init_array.*)"
+ *(.init_array)
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors ALIGN(4) :
+ {
+ PROVIDE(__fini_array_start = .);
+ *(.fini_array)
+ "*(.fini_array.*)"
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .vletext ALIGN(16) :
+ {
+ *(.vletext)
+ "*(.vletext.*)"
+ } > flash
+
+ .text ALIGN(16) :
+ {
+ *(.text)
+ "*(.text.*)"
+ } > flash
+
+ .rodata ALIGN(16) :
+ {
+ *(.rodata)
+ "*(.rodata.*)"
+ *(.rodata1)
+ } > flash
+
+ .sdata2 ALIGN(16) :
+ {
+ __sdata2_start__ = . + 0x8000;
+ *(.sdata2)
+ "*(.sdata2.*)"
+ *(.sbss2)
+ "*(.sbss2.*)"
+ } > flash
+
+ .stacks ALIGN(16) :
+ {
+ . = ALIGN(8);
+ __irq_stack_base__ = .;
+ . += __irq_stack_size__;
+ . = ALIGN(8);
+ __irq_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .romdatastart ALIGN(16) :
+ {
+ __romdata_start__ = .;
+ } > flash
+
+ .data ALIGN(4) : AT(__romdata_start__)
+ {
+ __data_start__ = .;
+ *(.data)
+ "*(.data.*)"
+ . = ALIGN(4);
+ *(.ramtext)
+ . = ALIGN(4);
+ __data_end__ = .;
+ } > ram
+
+ __romsdata_start__ = (__data_end__ - __data_start__) + __romdata_start__;
+
+ .sdata ALIGN(4) : AT(__romsdata_start__)
+ {
+ __sdata_start__ = . + 0x8000;
+ *(.sdata)
+ "*(.sdata.*)"
+ } > ram
+
+ .sbss ALIGN(4) :
+ {
+ __bss_start__ = .;
+ *(.sbss)
+ "*(.sbss.*)"
+ *(.scommon)
+ } > ram
+
+ .bss ALIGN(4) :
+ {
+ *(.bss)
+ "*(.bss.*)"
+ *(COMMON)
+ __bss_end__ = .;
+ } > ram
+
+ __flash_size__ = SIZEOF(flash);
+ __flash_start__ = ADDR(flash);
+ __flash_end__ = ENDADDR(flash);
+
+ __dataflash_size__ = SIZEOF(dataflash);
+ __dataflash_start__ = ADDR(dataflash);
+ __dataflash_end__ = ENDADDR(dataflash);
+
+ __ram_size__ = SIZEOF(ram);
+ __ram_start__ = ADDR(ram);
+ __ram_end__ = ENDADDR(ram);
+
+ __heap_base__ = __bss_end__;
+ __heap_end__ = __ram_end__;
+}
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc560bcxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc560bcxx.mk new file mode 100644 index 0000000..6d42e60 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc560bcxx.mk @@ -0,0 +1,16 @@ +# List of the ChibiOS e200z0 SPC560BCxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC560BCxx/boot_ghs.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/vectors.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/crt0.s
+
+STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC560BCxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
+
+# Shared variables
+ALLASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc560bxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc560bxx.mk new file mode 100644 index 0000000..51fe2e2 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc560bxx.mk @@ -0,0 +1,16 @@ +# List of the ChibiOS e200z0 SPC560Bxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC560Bxx/boot_ghs.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/vectors.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/crt0.s
+
+STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC560Bxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
+
+# Shared variables
+ALLASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc560dxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc560dxx.mk new file mode 100644 index 0000000..8ffda95 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc560dxx.mk @@ -0,0 +1,16 @@ +# List of the ChibiOS e200z0 SPC560Dxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC560Dxx/boot_ghs.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/vectors.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/crt0.s
+
+STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC560Dxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
+
+# Shared variables
+ALLASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc560pxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc560pxx.mk new file mode 100644 index 0000000..acd202a --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc560pxx.mk @@ -0,0 +1,16 @@ +# List of the ChibiOS e200z0 SPC560Pxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC560Pxx/boot_ghs.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/vectors.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/crt0.s
+
+STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC560Pxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
+
+# Shared variables
+ALLASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc563mxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc563mxx.mk new file mode 100644 index 0000000..be60849 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc563mxx.mk @@ -0,0 +1,16 @@ +# List of the ChibiOS e200z3 SPC563Mxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC563Mxx/boot_ghs.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/vectors.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/crt0.s
+
+STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC563Mxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
+
+# Shared variables
+ALLASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc564axx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc564axx.mk new file mode 100644 index 0000000..cd40e66 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc564axx.mk @@ -0,0 +1,16 @@ +# List of the ChibiOS e200z4 SPC564Axx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC564Axx/boot_ghs.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/vectors.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/crt0.s
+
+STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC564Axx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
+
+# Shared variables
+ALLASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc56ecxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc56ecxx.mk new file mode 100644 index 0000000..b4dcc2d --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc56ecxx.mk @@ -0,0 +1,16 @@ +# List of the ChibiOS e200z4 SPC56ECxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC56ECxx/boot_ghs.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/vectors.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/crt0.s
+
+STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC56ECxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
+
+# Shared variables
+ALLASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc56elxx.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc56elxx.mk new file mode 100644 index 0000000..85a447f --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/mk/startup_spc56elxx.mk @@ -0,0 +1,16 @@ +# List of the ChibiOS e200z4 SPC56ELxx startup files.
+STARTUPSRC =
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/e200/devices/SPC56ELxx/boot_ghs.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/vectors.s \
+ $(CHIBIOS)/os/common/startup/e200/compilers/GHS/crt0.s
+
+STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
+ ${CHIBIOS}/os/common/startup/e200/devices/SPC56ELxx
+
+STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
+
+# Shared variables
+ALLASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/rules.mk b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/rules.mk new file mode 100644 index 0000000..0237437 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/rules.mk @@ -0,0 +1,253 @@ +# e200z common makefile scripts and rules.
+
+##############################################################################
+# Processing options coming from the upper Makefile.
+#
+
+# Compiler options
+OPT = $(USE_OPT)
+COPT = $(USE_COPT)
+CPPOPT = $(USE_CPPOPT)
+
+# Garbage collection
+ifeq ($(USE_LINK_GC),yes)
+ OPT += --no_commons
+ LDOPT := -delete
+endif
+
+# Linker extra options
+ifneq ($(USE_LDOPT),)
+ LDOPT := $(LDOPT) $(USE_LDOPT)
+endif
+
+# Link time optimizations
+ifeq ($(USE_LTO),yes)
+ OPT += -Owholeprogram
+endif
+
+# VLE option handling.
+ifeq ($(USE_VLE),yes)
+ DDEFS += -DPPC_USE_VLE=1
+ DADEFS += -DPPC_USE_VLE=1
+ OPT += -vle
+ COPT += -vle
+else
+ DDEFS += -DPPC_USE_VLE=0
+ DADEFS += -DPPC_USE_VLE=0
+endif
+
+# Process stack size
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ LDOPT := $(LDOPT) -C__process_stack_size__=0x400 #,--defsym=__process_stack_size__=0x400
+else
+ LDOPT := $(LDOPT) -C__process_stack_size__=$(USE_PROCESS_STACKSIZE) #,--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE)
+endif
+
+# Exceptions stack size
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ LDOPT := $(LDOPT) -C__irq_stack_size__=0x400 #,--defsym=__irq_stack_size__=0x400
+else
+ LDOPT := $(LDOPT) -C__irq_stack_size__=$(USE_EXCEPTIONS_STACKSIZE) #,--defsym=__irq_stack_size__=$(USE_EXCEPTIONS_STACKSIZE)
+endif
+
+# Output directory and files
+ifeq ($(BUILDDIR),)
+ BUILDDIR = build
+endif
+ifeq ($(BUILDDIR),.)
+ BUILDDIR = build
+endif
+
+OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
+ $(BUILDDIR)/$(PROJECT).mot $(BUILDDIR)/$(PROJECT).bin \
+ $(BUILDDIR)/$(PROJECT).dmp
+
+# Source files groups and paths
+SRC = $(CSRC)$(CPPSRC)
+SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(SRC)))
+
+# Various directories
+OBJDIR = $(BUILDDIR)/obj
+LSTDIR = $(BUILDDIR)/lst
+
+# Object files groups
+COBJS = $(addprefix $(OBJDIR)/, $(notdir $(CSRC:.c=.o)))
+CPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(CPPSRC:.cpp=.o)))
+ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
+ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+OBJS = $(ASMXOBJS) $(ASMOBJS) $(COBJS) $(CPPOBJS)
+
+# Paths
+IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
+LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+
+# Macros
+DEFS = $(DDEFS) $(UDEFS)
+ADEFS = $(DADEFS) $(UADEFS)
+
+# Libs
+LIBS = $(DLIBS) $(ULIBS)
+
+# Various settings
+WARN = --incorrect_pragma_warnings --unknown_pragma_warnings --prototype_warnings --diag_error 236
+LIST = -list -tmp=$(OBJDIR)
+
+MCFLAGS = -cpu=$(MCU)
+
+ODFLAGS = -ysec -full
+
+ASFLAGS = $(MCFLAGS) $(OPT) $(LIST) -list=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) $(WARN) -preprocess_assembly_files
+ASXFLAGS = $(MCFLAGS) $(OPT) $(LIST) -list=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) $(WARN) -preprocess_assembly_files
+CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) $(LIST) -list=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
+CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) $(LIST) -list=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
+
+LDFLAGS := $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR)
+LDFLAGS += -map=$(BUILDDIR)/$(PROJECT).map
+LDFLAGS += -Mx
+LDFLAGS += $(LDOPT)
+LDFLAGS += $(LDSCRIPT)
+
+# Generate dependency information
+ASFLAGS += -MD
+ASXFLAGS += -MD
+CFLAGS += -MD
+CPPFLAGS += -MD
+
+# Paths where to search for sources
+VPATH = $(SRCPATHS)
+
+#
+# Makefile rules
+#
+
+all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK
+
+PRE_MAKE_ALL_RULE_HOOK:
+
+POST_MAKE_ALL_RULE_HOOK:
+
+$(OBJS): | PRE_MAKE_ALL_RULE_HOOK $(BUILDDIR) $(OBJDIR) $(LSTDIR) $(DEPDIR)
+
+$(BUILDDIR):
+ifneq ($(USE_VERBOSE_COMPILE),yes)
+ @echo Compiler Options
+ @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
+ @echo
+endif
+ @mkdir -p $(BUILDDIR)
+
+$(OBJDIR):
+ @mkdir -p $(OBJDIR)
+
+$(LSTDIR):
+ @mkdir -p $(LSTDIR)
+
+$(DEPDIR):
+ @mkdir -p $(DEPDIR)
+
+$(CPPOBJS) : $(OBJDIR)/%.o : %.cpp $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(COBJS) : $(OBJDIR)/%.o : %.c $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMOBJS) : $(OBJDIR)/%.o : %.s $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+%.elf: $(OBJS) $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+else
+ @echo Linking $@
+ @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+endif
+
+%.hex: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(HEX) $< -o $@
+else
+ @echo Creating $@
+ @$(HEX) $< -o $@
+endif
+
+%.mot: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(MOT) $< -o $@
+else
+ @echo Creating $@
+ @$(MOT) $< -o $@
+endif
+
+%.bin: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(BIN) $< -o $@
+else
+ @echo Creating $@
+ @$(BIN) $< -o $@
+endif
+
+%.dmp: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(OD) $(ODFLAGS) $< > $@
+else
+ @echo Creating $@
+ @$(OD) $(ODFLAGS) $< > $@
+ @echo
+# @$(SZ) -addr -file -hex $<
+# @echo
+ @echo Done
+endif
+
+lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a
+
+$(BUILDDIR)/lib$(PROJECT).a: $(OBJS)
+ @$(AR) -r $@ $^
+ @echo
+ @echo Done
+
+clean: CLEAN_RULE_HOOK
+ @echo Cleaning
+ @echo - $(DEPDIR)
+ @-rm -fR $(DEPDIR)/* $(BUILDDIR)/* 2>/dev/null
+ @-if [ -d "$(DEPDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(DEPDIR)) 2>/dev/null; fi
+ @echo - $(BUILDDIR)
+ @-if [ -d "$(BUILDDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(BUILDDIR)) 2>/dev/null; fi
+ @echo
+ @echo Done
+
+CLEAN_RULE_HOOK:
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(wildcard $(DEPDIR)/*)
+
+# *** EOF ***
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/vectors.h b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/vectors.h new file mode 100644 index 0000000..bb36b54 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/vectors.h @@ -0,0 +1,78 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file vectors.h
+ * @brief ISR vector module header.
+ *
+ * @addtogroup PPC_GCC_CORE
+ * @{
+ */
+
+#ifndef VECTORS_H
+#define VECTORS_H
+
+#include "ppcparams.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+#if !defined(__DOXYGEN__)
+extern uint32_t _vectors[PPC_NUM_VECTORS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _unhandled_irq(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* VECTORS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/vectors.s b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/vectors.s new file mode 100644 index 0000000..871a2ab --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/compilers/GHS/vectors.s @@ -0,0 +1,2614 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file vectors.S
+ * @brief INTC vectors table.
+ *
+ * @addtogroup PPC_GCC_CORE
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "ppcparams.h"
+
+#if defined(VECTORS_RENAMING)
+#include "isrs.h"
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ .vle
+
+ /* Software vectors table. The vectors are accessed from the IVOR4
+ handler only. In order to declare an interrupt handler just create
+ a function withe the same name of a vector, the symbol will
+ override the weak symbol declared here.*/
+ .section .vectors, "axv"
+ .align 4
+ .globl _vectors
+_vectors:
+ .long vector0, vector1, vector2, vector3
+#if PPC_NUM_VECTORS > 4
+ .long vector4, vector5, vector6, vector7
+#endif
+#if PPC_NUM_VECTORS > 8
+ .long vector8, vector9, vector10, vector11
+#endif
+#if PPC_NUM_VECTORS > 12
+ .long vector12, vector13, vector14, vector15
+#endif
+#if PPC_NUM_VECTORS > 16
+ .long vector16, vector17, vector18, vector19
+#endif
+#if PPC_NUM_VECTORS > 20
+ .long vector20, vector21, vector22, vector23
+#endif
+#if PPC_NUM_VECTORS > 24
+ .long vector24, vector25, vector26, vector27
+#endif
+#if PPC_NUM_VECTORS > 28
+ .long vector28, vector29, vector30, vector31
+#endif
+#if PPC_NUM_VECTORS > 32
+ .long vector32, vector33, vector34, vector35
+#endif
+#if PPC_NUM_VECTORS > 36
+ .long vector36, vector37, vector38, vector39
+#endif
+#if PPC_NUM_VECTORS > 40
+ .long vector40, vector41, vector42, vector43
+#endif
+#if PPC_NUM_VECTORS > 44
+ .long vector44, vector45, vector46, vector47
+#endif
+#if PPC_NUM_VECTORS > 48
+ .long vector48, vector49, vector50, vector51
+#endif
+#if PPC_NUM_VECTORS > 52
+ .long vector52, vector53, vector54, vector55
+#endif
+#if PPC_NUM_VECTORS > 56
+ .long vector56, vector57, vector58, vector59
+#endif
+#if PPC_NUM_VECTORS > 60
+ .long vector60, vector61, vector62, vector63
+#endif
+#if PPC_NUM_VECTORS > 64
+ .long vector64, vector65, vector66, vector67
+#endif
+#if PPC_NUM_VECTORS > 68
+ .long vector68, vector69, vector70, vector71
+#endif
+#if PPC_NUM_VECTORS > 72
+ .long vector72, vector73, vector74, vector75
+#endif
+#if PPC_NUM_VECTORS > 76
+ .long vector76, vector77, vector78, vector79
+#endif
+#if PPC_NUM_VECTORS > 80
+ .long vector80, vector81, vector82, vector83
+#endif
+#if PPC_NUM_VECTORS > 84
+ .long vector84, vector85, vector86, vector87
+#endif
+#if PPC_NUM_VECTORS > 88
+ .long vector88, vector89, vector90, vector91
+#endif
+#if PPC_NUM_VECTORS > 92
+ .long vector92, vector93, vector94, vector95
+#endif
+#if PPC_NUM_VECTORS > 96
+ .long vector96, vector97, vector98, vector99
+#endif
+#if PPC_NUM_VECTORS > 100
+ .long vector100, vector101, vector102, vector103
+#endif
+#if PPC_NUM_VECTORS > 104
+ .long vector104, vector105, vector106, vector107
+#endif
+#if PPC_NUM_VECTORS > 108
+ .long vector108, vector109, vector110, vector111
+#endif
+#if PPC_NUM_VECTORS > 112
+ .long vector112, vector113, vector114, vector115
+#endif
+#if PPC_NUM_VECTORS > 116
+ .long vector116, vector117, vector118, vector119
+#endif
+#if PPC_NUM_VECTORS > 120
+ .long vector120, vector121, vector122, vector123
+#endif
+#if PPC_NUM_VECTORS > 124
+ .long vector124, vector125, vector126, vector127
+#endif
+#if PPC_NUM_VECTORS > 128
+ .long vector128, vector129, vector130, vector131
+#endif
+#if PPC_NUM_VECTORS > 132
+ .long vector132, vector133, vector134, vector135
+#endif
+#if PPC_NUM_VECTORS > 136
+ .long vector136, vector137, vector138, vector139
+#endif
+#if PPC_NUM_VECTORS > 140
+ .long vector140, vector141, vector142, vector143
+#endif
+#if PPC_NUM_VECTORS > 144
+ .long vector144, vector145, vector146, vector147
+#endif
+#if PPC_NUM_VECTORS > 148
+ .long vector148, vector149, vector150, vector151
+#endif
+#if PPC_NUM_VECTORS > 152
+ .long vector152, vector153, vector154, vector155
+#endif
+#if PPC_NUM_VECTORS > 156
+ .long vector156, vector157, vector158, vector159
+#endif
+#if PPC_NUM_VECTORS > 160
+ .long vector160, vector161, vector162, vector163
+#endif
+#if PPC_NUM_VECTORS > 164
+ .long vector164, vector165, vector166, vector167
+#endif
+#if PPC_NUM_VECTORS > 168
+ .long vector168, vector169, vector170, vector171
+#endif
+#if PPC_NUM_VECTORS > 172
+ .long vector172, vector173, vector174, vector175
+#endif
+#if PPC_NUM_VECTORS > 176
+ .long vector176, vector177, vector178, vector179
+#endif
+#if PPC_NUM_VECTORS > 180
+ .long vector180, vector181, vector182, vector183
+#endif
+#if PPC_NUM_VECTORS > 184
+ .long vector184, vector185, vector186, vector187
+#endif
+#if PPC_NUM_VECTORS > 188
+ .long vector188, vector189, vector190, vector191
+#endif
+#if PPC_NUM_VECTORS > 192
+ .long vector192, vector193, vector194, vector195
+#endif
+#if PPC_NUM_VECTORS > 196
+ .long vector196, vector197, vector198, vector199
+#endif
+#if PPC_NUM_VECTORS > 200
+ .long vector200, vector201, vector202, vector203
+#endif
+#if PPC_NUM_VECTORS > 204
+ .long vector204, vector205, vector206, vector207
+#endif
+#if PPC_NUM_VECTORS > 208
+ .long vector208, vector209, vector210, vector211
+#endif
+#if PPC_NUM_VECTORS > 212
+ .long vector212, vector213, vector214, vector215
+#endif
+#if PPC_NUM_VECTORS > 216
+ .long vector216, vector217, vector218, vector219
+#endif
+#if PPC_NUM_VECTORS > 220
+ .long vector220, vector221, vector222, vector223
+#endif
+#if PPC_NUM_VECTORS > 224
+ .long vector224, vector225, vector226, vector227
+#endif
+#if PPC_NUM_VECTORS > 228
+ .long vector228, vector229, vector230, vector231
+#endif
+#if PPC_NUM_VECTORS > 232
+ .long vector232, vector233, vector234, vector235
+#endif
+#if PPC_NUM_VECTORS > 236
+ .long vector236, vector237, vector238, vector239
+#endif
+#if PPC_NUM_VECTORS > 240
+ .long vector240, vector241, vector242, vector243
+#endif
+#if PPC_NUM_VECTORS > 244
+ .long vector244, vector245, vector246, vector247
+#endif
+#if PPC_NUM_VECTORS > 248
+ .long vector248, vector249, vector250, vector251
+#endif
+#if PPC_NUM_VECTORS > 252
+ .long vector252, vector253, vector254, vector255
+#endif
+#if PPC_NUM_VECTORS > 256
+ .long vector256, vector257, vector258, vector259
+#endif
+#if PPC_NUM_VECTORS > 260
+ .long vector260, vector261, vector262, vector263
+#endif
+#if PPC_NUM_VECTORS > 264
+ .long vector264, vector265, vector266, vector267
+#endif
+#if PPC_NUM_VECTORS > 268
+ .long vector268, vector269, vector270, vector271
+#endif
+#if PPC_NUM_VECTORS > 272
+ .long vector272, vector273, vector274, vector275
+#endif
+#if PPC_NUM_VECTORS > 276
+ .long vector276, vector277, vector278, vector279
+#endif
+#if PPC_NUM_VECTORS > 280
+ .long vector280, vector281, vector282, vector283
+#endif
+#if PPC_NUM_VECTORS > 284
+ .long vector284, vector285, vector286, vector287
+#endif
+#if PPC_NUM_VECTORS > 288
+ .long vector288, vector289, vector290, vector291
+#endif
+#if PPC_NUM_VECTORS > 292
+ .long vector292, vector293, vector294, vector295
+#endif
+#if PPC_NUM_VECTORS > 296
+ .long vector296, vector297, vector298, vector299
+#endif
+#if PPC_NUM_VECTORS > 300
+ .long vector300, vector301, vector302, vector303
+#endif
+#if PPC_NUM_VECTORS > 304
+ .long vector304, vector305, vector306, vector307
+#endif
+#if PPC_NUM_VECTORS > 308
+ .long vector308, vector309, vector310, vector311
+#endif
+#if PPC_NUM_VECTORS > 312
+ .long vector312, vector313, vector314, vector315
+#endif
+#if PPC_NUM_VECTORS > 316
+ .long vector316, vector317, vector318, vector319
+#endif
+#if PPC_NUM_VECTORS > 320
+ .long vector320, vector321, vector322, vector323
+#endif
+#if PPC_NUM_VECTORS > 324
+ .long vector324, vector325, vector326, vector327
+#endif
+#if PPC_NUM_VECTORS > 328
+ .long vector328, vector329, vector330, vector331
+#endif
+#if PPC_NUM_VECTORS > 332
+ .long vector332, vector333, vector334, vector335
+#endif
+#if PPC_NUM_VECTORS > 336
+ .long vector336, vector337, vector338, vector339
+#endif
+#if PPC_NUM_VECTORS > 340
+ .long vector340, vector341, vector342, vector343
+#endif
+#if PPC_NUM_VECTORS > 344
+ .long vector344, vector345, vector346, vector347
+#endif
+#if PPC_NUM_VECTORS > 348
+ .long vector348, vector349, vector350, vector351
+#endif
+#if PPC_NUM_VECTORS > 352
+ .long vector352, vector353, vector354, vector355
+#endif
+#if PPC_NUM_VECTORS > 356
+ .long vector356, vector357, vector358, vector359
+#endif
+#if PPC_NUM_VECTORS > 360
+ .long vector360, vector361, vector362, vector363
+#endif
+#if PPC_NUM_VECTORS > 364
+ .long vector364, vector365, vector366, vector367
+#endif
+#if PPC_NUM_VECTORS > 368
+ .long vector368, vector369, vector370, vector371
+#endif
+#if PPC_NUM_VECTORS > 372
+ .long vector372, vector373, vector374, vector375
+#endif
+#if PPC_NUM_VECTORS > 376
+ .long vector376, vector377, vector378, vector379
+#endif
+#if PPC_NUM_VECTORS > 380
+ .long vector380, vector381, vector382, vector383
+#endif
+#if PPC_NUM_VECTORS > 384
+ .long vector384, vector385, vector386, vector387
+#endif
+#if PPC_NUM_VECTORS > 388
+ .long vector388, vector389, vector390, vector391
+#endif
+#if PPC_NUM_VECTORS > 392
+ .long vector392, vector393, vector394, vector395
+#endif
+#if PPC_NUM_VECTORS > 396
+ .long vector396, vector397, vector398, vector399
+#endif
+#if PPC_NUM_VECTORS > 400
+ .long vector400, vector401, vector402, vector403
+#endif
+#if PPC_NUM_VECTORS > 404
+ .long vector404, vector405, vector406, vector407
+#endif
+#if PPC_NUM_VECTORS > 408
+ .long vector408, vector409, vector410, vector411
+#endif
+#if PPC_NUM_VECTORS > 412
+ .long vector412, vector413, vector414, vector415
+#endif
+#if PPC_NUM_VECTORS > 416
+ .long vector416, vector417, vector418, vector419
+#endif
+#if PPC_NUM_VECTORS > 420
+ .long vector420, vector421, vector422, vector423
+#endif
+#if PPC_NUM_VECTORS > 424
+ .long vector424, vector425, vector426, vector427
+#endif
+#if PPC_NUM_VECTORS > 428
+ .long vector428, vector429, vector430, vector431
+#endif
+#if PPC_NUM_VECTORS > 432
+ .long vector432, vector433, vector434, vector435
+#endif
+#if PPC_NUM_VECTORS > 436
+ .long vector436, vector437, vector438, vector439
+#endif
+#if PPC_NUM_VECTORS > 440
+ .long vector440, vector441, vector442, vector443
+#endif
+#if PPC_NUM_VECTORS > 444
+ .long vector444, vector445, vector446, vector447
+#endif
+#if PPC_NUM_VECTORS > 448
+ .long vector448, vector449, vector450, vector451
+#endif
+#if PPC_NUM_VECTORS > 452
+ .long vector452, vector453, vector454, vector455
+#endif
+#if PPC_NUM_VECTORS > 456
+ .long vector456, vector457, vector458, vector459
+#endif
+#if PPC_NUM_VECTORS > 460
+ .long vector460, vector461, vector462, vector463
+#endif
+#if PPC_NUM_VECTORS > 464
+ .long vector464, vector465, vector466, vector467
+#endif
+#if PPC_NUM_VECTORS > 468
+ .long vector468, vector469, vector470, vector471
+#endif
+#if PPC_NUM_VECTORS > 472
+ .long vector472, vector473, vector474, vector475
+#endif
+#if PPC_NUM_VECTORS > 476
+ .long vector476, vector477, vector478, vector479
+#endif
+#if PPC_NUM_VECTORS > 480
+ .long vector480, vector481, vector482, vector483
+#endif
+#if PPC_NUM_VECTORS > 484
+ .long vector484, vector485, vector486, vector487
+#endif
+#if PPC_NUM_VECTORS > 488
+ .long vector488, vector489, vector490, vector491
+#endif
+#if PPC_NUM_VECTORS > 492
+ .long vector492, vector493, vector494, vector495
+#endif
+#if PPC_NUM_VECTORS > 496
+ .long vector496, vector497, vector498, vector499
+#endif
+#if PPC_NUM_VECTORS > 500
+ .long vector500, vector501, vector502, vector503
+#endif
+#if PPC_NUM_VECTORS > 504
+ .long vector504, vector505, vector506, vector507
+#endif
+#if PPC_NUM_VECTORS > 508
+ .long vector508, vector509, vector510, vector511
+#endif
+#if PPC_NUM_VECTORS > 512
+ .long vector512, vector513, vector514, vector515
+#endif
+#if PPC_NUM_VECTORS > 516
+ .long vector516, vector517, vector518, vector519
+#endif
+#if PPC_NUM_VECTORS > 520
+ .long vector520, vector521, vector522, vector523
+#endif
+#if PPC_NUM_VECTORS > 524
+ .long vector524, vector525, vector526, vector527
+#endif
+#if PPC_NUM_VECTORS > 528
+ .long vector528, vector529, vector530, vector531
+#endif
+#if PPC_NUM_VECTORS > 532
+ .long vector532, vector533, vector534, vector535
+#endif
+#if PPC_NUM_VECTORS > 536
+ .long vector536, vector537, vector538, vector539
+#endif
+#if PPC_NUM_VECTORS > 540
+ .long vector540, vector541, vector542, vector543
+#endif
+#if PPC_NUM_VECTORS > 544
+ .long vector544, vector545, vector546, vector547
+#endif
+#if PPC_NUM_VECTORS > 548
+ .long vector548, vector549, vector550, vector551
+#endif
+#if PPC_NUM_VECTORS > 552
+ .long vector552, vector553, vector554, vector555
+#endif
+#if PPC_NUM_VECTORS > 556
+ .long vector556, vector557, vector558, vector559
+#endif
+#if PPC_NUM_VECTORS > 560
+ .long vector560, vector561, vector562, vector563
+#endif
+#if PPC_NUM_VECTORS > 564
+ .long vector564, vector565, vector566, vector567
+#endif
+#if PPC_NUM_VECTORS > 568
+ .long vector568, vector569, vector570, vector571
+#endif
+#if PPC_NUM_VECTORS > 572
+ .long vector572, vector573, vector574, vector575
+#endif
+#if PPC_NUM_VECTORS > 576
+ .long vector576, vector577, vector578, vector579
+#endif
+#if PPC_NUM_VECTORS > 580
+ .long vector580, vector581, vector582, vector583
+#endif
+#if PPC_NUM_VECTORS > 584
+ .long vector584, vector585, vector586, vector587
+#endif
+#if PPC_NUM_VECTORS > 588
+ .long vector588, vector589, vector590, vector591
+#endif
+#if PPC_NUM_VECTORS > 592
+ .long vector592, vector593, vector594, vector595
+#endif
+#if PPC_NUM_VECTORS > 596
+ .long vector596, vector597, vector598, vector599
+#endif
+#if PPC_NUM_VECTORS > 600
+ .long vector600, vector601, vector602, vector603
+#endif
+#if PPC_NUM_VECTORS > 604
+ .long vector604, vector605, vector606, vector607
+#endif
+#if PPC_NUM_VECTORS > 608
+ .long vector608, vector609, vector610, vector611
+#endif
+#if PPC_NUM_VECTORS > 612
+ .long vector612, vector613, vector614, vector615
+#endif
+#if PPC_NUM_VECTORS > 616
+ .long vector616, vector617, vector618, vector619
+#endif
+#if PPC_NUM_VECTORS > 620
+ .long vector620, vector621, vector622, vector623
+#endif
+#if PPC_NUM_VECTORS > 624
+ .long vector624, vector625, vector626, vector627
+#endif
+#if PPC_NUM_VECTORS > 628
+ .long vector628, vector629, vector630, vector631
+#endif
+#if PPC_NUM_VECTORS > 632
+ .long vector632, vector633, vector634, vector635
+#endif
+#if PPC_NUM_VECTORS > 636
+ .long vector636, vector637, vector638, vector639
+#endif
+#if PPC_NUM_VECTORS > 640
+ .long vector640, vector641, vector642, vector643
+#endif
+#if PPC_NUM_VECTORS > 644
+ .long vector644, vector645, vector646, vector647
+#endif
+#if PPC_NUM_VECTORS > 648
+ .long vector648, vector649, vector650, vector651
+#endif
+#if PPC_NUM_VECTORS > 652
+ .long vector652, vector653, vector654, vector655
+#endif
+#if PPC_NUM_VECTORS > 656
+ .long vector656, vector657, vector658, vector659
+#endif
+#if PPC_NUM_VECTORS > 660
+ .long vector660, vector661, vector662, vector663
+#endif
+#if PPC_NUM_VECTORS > 664
+ .long vector664, vector665, vector666, vector667
+#endif
+#if PPC_NUM_VECTORS > 668
+ .long vector668, vector669, vector670, vector671
+#endif
+#if PPC_NUM_VECTORS > 672
+ .long vector672, vector673, vector674, vector675
+#endif
+#if PPC_NUM_VECTORS > 676
+ .long vector676, vector677, vector678, vector679
+#endif
+#if PPC_NUM_VECTORS > 680
+ .long vector680, vector681, vector682, vector683
+#endif
+#if PPC_NUM_VECTORS > 684
+ .long vector684, vector685, vector686, vector687
+#endif
+#if PPC_NUM_VECTORS > 688
+ .long vector688, vector689, vector690, vector691
+#endif
+#if PPC_NUM_VECTORS > 692
+ .long vector692, vector693, vector694, vector695
+#endif
+#if PPC_NUM_VECTORS > 696
+ .long vector696, vector697, vector698, vector699
+#endif
+#if PPC_NUM_VECTORS > 700
+ .long vector700, vector701, vector702, vector703
+#endif
+#if PPC_NUM_VECTORS > 704
+ .long vector704, vector705, vector706, vector707
+#endif
+#if PPC_NUM_VECTORS > 708
+ .long vector708, vector709, vector710, vector711
+#endif
+#if PPC_NUM_VECTORS > 712
+ .long vector712, vector713, vector714, vector715
+#endif
+#if PPC_NUM_VECTORS > 716
+ .long vector716, vector717, vector718, vector719
+#endif
+#if PPC_NUM_VECTORS > 720
+ .long vector720, vector721, vector722, vector723
+#endif
+#if PPC_NUM_VECTORS > 724
+ .long vector724, vector725, vector726, vector727
+#endif
+#if PPC_NUM_VECTORS > 728
+ .long vector728, vector729, vector730, vector731
+#endif
+#if PPC_NUM_VECTORS > 732
+ .long vector732, vector733, vector734, vector735
+#endif
+#if PPC_NUM_VECTORS > 736
+ .long vector736, vector737, vector738, vector739
+#endif
+#if PPC_NUM_VECTORS > 740
+ .long vector740, vector741, vector742, vector743
+#endif
+#if PPC_NUM_VECTORS > 744
+ .long vector744, vector745, vector746, vector747
+#endif
+#if PPC_NUM_VECTORS > 748
+ .long vector748, vector749, vector750, vector751
+#endif
+#if PPC_NUM_VECTORS > 752
+ .long vector752, vector753, vector754, vector755
+#endif
+#if PPC_NUM_VECTORS > 756
+ .long vector756, vector757, vector758, vector759
+#endif
+#if PPC_NUM_VECTORS > 760
+ .long vector760, vector761, vector762, vector763
+#endif
+#if PPC_NUM_VECTORS > 764
+ .long vector764, vector765, vector766, vector767
+#endif
+#if PPC_NUM_VECTORS > 768
+ .long vector768, vector769, vector770, vector771
+#endif
+#if PPC_NUM_VECTORS > 772
+ .long vector772, vector773, vector774, vector775
+#endif
+#if PPC_NUM_VECTORS > 776
+ .long vector776, vector777, vector778, vector779
+#endif
+#if PPC_NUM_VECTORS > 780
+ .long vector780, vector781, vector782, vector783
+#endif
+#if PPC_NUM_VECTORS > 784
+ .long vector784, vector785, vector786, vector787
+#endif
+#if PPC_NUM_VECTORS > 788
+ .long vector788, vector789, vector790, vector791
+#endif
+#if PPC_NUM_VECTORS > 792
+ .long vector792, vector793, vector794, vector795
+#endif
+#if PPC_NUM_VECTORS > 796
+ .long vector796, vector797, vector798, vector799
+#endif
+#if PPC_NUM_VECTORS > 800
+ .long vector800, vector801, vector802, vector803
+#endif
+#if PPC_NUM_VECTORS > 804
+ .long vector804, vector805, vector806, vector807
+#endif
+#if PPC_NUM_VECTORS > 808
+ .long vector808, vector809, vector810, vector811
+#endif
+#if PPC_NUM_VECTORS > 812
+ .long vector812, vector813, vector814, vector815
+#endif
+#if PPC_NUM_VECTORS > 816
+ .long vector816, vector817, vector818, vector819
+#endif
+#if PPC_NUM_VECTORS > 820
+ .long vector820, vector821, vector822, vector823
+#endif
+#if PPC_NUM_VECTORS > 824
+ .long vector824, vector825, vector826, vector827
+#endif
+#if PPC_NUM_VECTORS > 828
+ .long vector828, vector829, vector830, vector831
+#endif
+#if PPC_NUM_VECTORS > 832
+ .long vector832, vector833, vector834, vector835
+#endif
+#if PPC_NUM_VECTORS > 836
+ .long vector836, vector837, vector838, vector839
+#endif
+#if PPC_NUM_VECTORS > 840
+ .long vector840, vector841, vector842, vector843
+#endif
+#if PPC_NUM_VECTORS > 844
+ .long vector844, vector845, vector846, vector847
+#endif
+#if PPC_NUM_VECTORS > 848
+ .long vector848, vector849, vector850, vector851
+#endif
+#if PPC_NUM_VECTORS > 852
+ .long vector852, vector853, vector854, vector855
+#endif
+#if PPC_NUM_VECTORS > 856
+ .long vector856, vector857, vector858, vector859
+#endif
+#if PPC_NUM_VECTORS > 860
+ .long vector860, vector861, vector862, vector863
+#endif
+#if PPC_NUM_VECTORS > 864
+ .long vector864, vector865, vector866, vector867
+#endif
+#if PPC_NUM_VECTORS > 868
+ .long vector868, vector869, vector870, vector871
+#endif
+#if PPC_NUM_VECTORS > 872
+ .long vector872, vector873, vector874, vector875
+#endif
+#if PPC_NUM_VECTORS > 876
+ .long vector876, vector877, vector878, vector879
+#endif
+#if PPC_NUM_VECTORS > 880
+ .long vector880, vector881, vector882, vector883
+#endif
+#if PPC_NUM_VECTORS > 884
+ .long vector884, vector885, vector886, vector887
+#endif
+#if PPC_NUM_VECTORS > 888
+ .long vector888, vector889, vector890, vector891
+#endif
+#if PPC_NUM_VECTORS > 892
+ .long vector892, vector893, vector894, vector895
+#endif
+#if PPC_NUM_VECTORS > 896
+ .long vector896, vector897, vector898, vector899
+#endif
+#if PPC_NUM_VECTORS > 900
+ .long vector900, vector901, vector902, vector903
+#endif
+#if PPC_NUM_VECTORS > 904
+ .long vector904, vector905, vector906, vector907
+#endif
+#if PPC_NUM_VECTORS > 908
+ .long vector908, vector909, vector910, vector911
+#endif
+#if PPC_NUM_VECTORS > 912
+ .long vector912, vector913, vector914, vector915
+#endif
+#if PPC_NUM_VECTORS > 916
+ .long vector916, vector917, vector918, vector919
+#endif
+#if PPC_NUM_VECTORS > 920
+ .long vector920, vector921, vector922, vector923
+#endif
+#if PPC_NUM_VECTORS > 924
+ .long vector924, vector925, vector926, vector927
+#endif
+#if PPC_NUM_VECTORS > 928
+ .long vector928, vector929, vector930, vector931
+#endif
+#if PPC_NUM_VECTORS > 932
+ .long vector932, vector933, vector934, vector935
+#endif
+#if PPC_NUM_VECTORS > 936
+ .long vector936, vector937, vector938, vector939
+#endif
+#if PPC_NUM_VECTORS > 940
+ .long vector940, vector941, vector942, vector943
+#endif
+#if PPC_NUM_VECTORS > 944
+ .long vector944, vector945, vector946, vector947
+#endif
+#if PPC_NUM_VECTORS > 948
+ .long vector948, vector949, vector950, vector951
+#endif
+#if PPC_NUM_VECTORS > 952
+ .long vector952, vector953, vector954, vector955
+#endif
+#if PPC_NUM_VECTORS > 956
+ .long vector956, vector957, vector958, vector959
+#endif
+#if PPC_NUM_VECTORS > 960
+ .long vector960, vector961, vector962, vector963
+#endif
+#if PPC_NUM_VECTORS > 964
+ .long vector964, vector965, vector966, vector967
+#endif
+#if PPC_NUM_VECTORS > 968
+ .long vector968, vector969, vector970, vector971
+#endif
+#if PPC_NUM_VECTORS > 972
+ .long vector972, vector973, vector974, vector975
+#endif
+#if PPC_NUM_VECTORS > 976
+ .long vector976, vector977, vector978, vector979
+#endif
+#if PPC_NUM_VECTORS > 980
+ .long vector980, vector981, vector982, vector983
+#endif
+#if PPC_NUM_VECTORS > 984
+ .long vector984, vector985, vector986, vector987
+#endif
+#if PPC_NUM_VECTORS > 988
+ .long vector988, vector989, vector990, vector991
+#endif
+#if PPC_NUM_VECTORS > 992
+ .long vector992, vector993, vector994, vector995
+#endif
+#if PPC_NUM_VECTORS > 996
+ .long vector996, vector997, vector998, vector999
+#endif
+#if PPC_NUM_VECTORS > 1000
+ .long vector1000, vector1001, vector1002, vector1003
+#endif
+#if PPC_NUM_VECTORS > 1004
+ .long vector1004, vector1005, vector1006, vector1007
+#endif
+#if PPC_NUM_VECTORS > 1008
+ .long vector1008, vector1009, vector1010, vector1011
+#endif
+#if PPC_NUM_VECTORS > 1012
+ .long vector1012, vector1013, vector1014, vector1015
+#endif
+#if PPC_NUM_VECTORS > 1016
+ .long vector1016, vector1017, vector1018, vector1019
+#endif
+#if PPC_NUM_VECTORS > 1020
+ .long vector1020, vector1021, vector1022, vector1023
+#endif
+
+ .section .vletext, "axv"
+ .align 2
+
+ .weak vector0, vector1, vector2, vector3
+#if PPC_NUM_VECTORS > 4
+ .weak vector4, vector5, vector6, vector7
+#endif
+#if PPC_NUM_VECTORS > 8
+ .weak vector8, vector9, vector10, vector11
+#endif
+#if PPC_NUM_VECTORS > 12
+ .weak vector12, vector13, vector14, vector15
+#endif
+#if PPC_NUM_VECTORS > 16
+ .weak vector16, vector17, vector18, vector19
+#endif
+#if PPC_NUM_VECTORS > 20
+ .weak vector20, vector21, vector22, vector23
+#endif
+#if PPC_NUM_VECTORS > 24
+ .weak vector24, vector25, vector26, vector27
+#endif
+#if PPC_NUM_VECTORS > 28
+ .weak vector28, vector29, vector30, vector31
+#endif
+#if PPC_NUM_VECTORS > 32
+ .weak vector32, vector33, vector34, vector35
+#endif
+#if PPC_NUM_VECTORS > 36
+ .weak vector36, vector37, vector38, vector39
+#endif
+#if PPC_NUM_VECTORS > 40
+ .weak vector40, vector41, vector42, vector43
+#endif
+#if PPC_NUM_VECTORS > 44
+ .weak vector44, vector45, vector46, vector47
+#endif
+#if PPC_NUM_VECTORS > 48
+ .weak vector48, vector49, vector50, vector51
+#endif
+#if PPC_NUM_VECTORS > 52
+ .weak vector52, vector53, vector54, vector55
+#endif
+#if PPC_NUM_VECTORS > 56
+ .weak vector56, vector57, vector58, vector59
+#endif
+#if PPC_NUM_VECTORS > 60
+ .weak vector60, vector61, vector62, vector63
+#endif
+#if PPC_NUM_VECTORS > 64
+ .weak vector64, vector65, vector66, vector67
+#endif
+#if PPC_NUM_VECTORS > 68
+ .weak vector68, vector69, vector70, vector71
+#endif
+#if PPC_NUM_VECTORS > 72
+ .weak vector72, vector73, vector74, vector75
+#endif
+#if PPC_NUM_VECTORS > 76
+ .weak vector76, vector77, vector78, vector79
+#endif
+#if PPC_NUM_VECTORS > 80
+ .weak vector80, vector81, vector82, vector83
+#endif
+#if PPC_NUM_VECTORS > 84
+ .weak vector84, vector85, vector86, vector87
+#endif
+#if PPC_NUM_VECTORS > 88
+ .weak vector88, vector89, vector90, vector91
+#endif
+#if PPC_NUM_VECTORS > 92
+ .weak vector92, vector93, vector94, vector95
+#endif
+#if PPC_NUM_VECTORS > 96
+ .weak vector96, vector97, vector98, vector99
+#endif
+#if PPC_NUM_VECTORS > 100
+ .weak vector100, vector101, vector102, vector103
+#endif
+#if PPC_NUM_VECTORS > 104
+ .weak vector104, vector105, vector106, vector107
+#endif
+#if PPC_NUM_VECTORS > 108
+ .weak vector108, vector109, vector110, vector111
+#endif
+#if PPC_NUM_VECTORS > 112
+ .weak vector112, vector113, vector114, vector115
+#endif
+#if PPC_NUM_VECTORS > 116
+ .weak vector116, vector117, vector118, vector119
+#endif
+#if PPC_NUM_VECTORS > 120
+ .weak vector120, vector121, vector122, vector123
+#endif
+#if PPC_NUM_VECTORS > 124
+ .weak vector124, vector125, vector126, vector127
+#endif
+#if PPC_NUM_VECTORS > 128
+ .weak vector128, vector129, vector130, vector131
+#endif
+#if PPC_NUM_VECTORS > 132
+ .weak vector132, vector133, vector134, vector135
+#endif
+#if PPC_NUM_VECTORS > 136
+ .weak vector136, vector137, vector138, vector139
+#endif
+#if PPC_NUM_VECTORS > 140
+ .weak vector140, vector141, vector142, vector143
+#endif
+#if PPC_NUM_VECTORS > 144
+ .weak vector144, vector145, vector146, vector147
+#endif
+#if PPC_NUM_VECTORS > 148
+ .weak vector148, vector149, vector150, vector151
+#endif
+#if PPC_NUM_VECTORS > 152
+ .weak vector152, vector153, vector154, vector155
+#endif
+#if PPC_NUM_VECTORS > 156
+ .weak vector156, vector157, vector158, vector159
+#endif
+#if PPC_NUM_VECTORS > 160
+ .weak vector160, vector161, vector162, vector163
+#endif
+#if PPC_NUM_VECTORS > 164
+ .weak vector164, vector165, vector166, vector167
+#endif
+#if PPC_NUM_VECTORS > 168
+ .weak vector168, vector169, vector170, vector171
+#endif
+#if PPC_NUM_VECTORS > 172
+ .weak vector172, vector173, vector174, vector175
+#endif
+#if PPC_NUM_VECTORS > 176
+ .weak vector176, vector177, vector178, vector179
+#endif
+#if PPC_NUM_VECTORS > 180
+ .weak vector180, vector181, vector182, vector183
+#endif
+#if PPC_NUM_VECTORS > 184
+ .weak vector184, vector185, vector186, vector187
+#endif
+#if PPC_NUM_VECTORS > 188
+ .weak vector188, vector189, vector190, vector191
+#endif
+#if PPC_NUM_VECTORS > 192
+ .weak vector192, vector193, vector194, vector195
+#endif
+#if PPC_NUM_VECTORS > 196
+ .weak vector196, vector197, vector198, vector199
+#endif
+#if PPC_NUM_VECTORS > 200
+ .weak vector200, vector201, vector202, vector203
+#endif
+#if PPC_NUM_VECTORS > 204
+ .weak vector204, vector205, vector206, vector207
+#endif
+#if PPC_NUM_VECTORS > 208
+ .weak vector208, vector209, vector210, vector211
+#endif
+#if PPC_NUM_VECTORS > 212
+ .weak vector212, vector213, vector214, vector215
+#endif
+#if PPC_NUM_VECTORS > 216
+ .weak vector216, vector217, vector218, vector219
+#endif
+#if PPC_NUM_VECTORS > 220
+ .weak vector220, vector221, vector222, vector223
+#endif
+#if PPC_NUM_VECTORS > 224
+ .weak vector224, vector225, vector226, vector227
+#endif
+#if PPC_NUM_VECTORS > 228
+ .weak vector228, vector229, vector230, vector231
+#endif
+#if PPC_NUM_VECTORS > 232
+ .weak vector232, vector233, vector234, vector235
+#endif
+#if PPC_NUM_VECTORS > 236
+ .weak vector236, vector237, vector238, vector239
+#endif
+#if PPC_NUM_VECTORS > 240
+ .weak vector240, vector241, vector242, vector243
+#endif
+#if PPC_NUM_VECTORS > 244
+ .weak vector244, vector245, vector246, vector247
+#endif
+#if PPC_NUM_VECTORS > 248
+ .weak vector248, vector249, vector250, vector251
+#endif
+#if PPC_NUM_VECTORS > 252
+ .weak vector252, vector253, vector254, vector255
+#endif
+#if PPC_NUM_VECTORS > 256
+ .weak vector256, vector257, vector258, vector259
+#endif
+#if PPC_NUM_VECTORS > 260
+ .weak vector260, vector261, vector262, vector263
+#endif
+#if PPC_NUM_VECTORS > 264
+ .weak vector264, vector265, vector266, vector267
+#endif
+#if PPC_NUM_VECTORS > 268
+ .weak vector268, vector269, vector270, vector271
+#endif
+#if PPC_NUM_VECTORS > 272
+ .weak vector272, vector273, vector274, vector275
+#endif
+#if PPC_NUM_VECTORS > 276
+ .weak vector276, vector277, vector278, vector279
+#endif
+#if PPC_NUM_VECTORS > 280
+ .weak vector280, vector281, vector282, vector283
+#endif
+#if PPC_NUM_VECTORS > 284
+ .weak vector284, vector285, vector286, vector287
+#endif
+#if PPC_NUM_VECTORS > 288
+ .weak vector288, vector289, vector290, vector291
+#endif
+#if PPC_NUM_VECTORS > 292
+ .weak vector292, vector293, vector294, vector295
+#endif
+#if PPC_NUM_VECTORS > 296
+ .weak vector296, vector297, vector298, vector299
+#endif
+#if PPC_NUM_VECTORS > 300
+ .weak vector300, vector301, vector302, vector303
+#endif
+#if PPC_NUM_VECTORS > 304
+ .weak vector304, vector305, vector306, vector307
+#endif
+#if PPC_NUM_VECTORS > 308
+ .weak vector308, vector309, vector310, vector311
+#endif
+#if PPC_NUM_VECTORS > 312
+ .weak vector312, vector313, vector314, vector315
+#endif
+#if PPC_NUM_VECTORS > 316
+ .weak vector316, vector317, vector318, vector319
+#endif
+#if PPC_NUM_VECTORS > 320
+ .weak vector320, vector321, vector322, vector323
+#endif
+#if PPC_NUM_VECTORS > 324
+ .weak vector324, vector325, vector326, vector327
+#endif
+#if PPC_NUM_VECTORS > 328
+ .weak vector328, vector329, vector330, vector331
+#endif
+#if PPC_NUM_VECTORS > 332
+ .weak vector332, vector333, vector334, vector335
+#endif
+#if PPC_NUM_VECTORS > 336
+ .weak vector336, vector337, vector338, vector339
+#endif
+#if PPC_NUM_VECTORS > 340
+ .weak vector340, vector341, vector342, vector343
+#endif
+#if PPC_NUM_VECTORS > 344
+ .weak vector344, vector345, vector346, vector347
+#endif
+#if PPC_NUM_VECTORS > 348
+ .weak vector348, vector349, vector350, vector351
+#endif
+#if PPC_NUM_VECTORS > 352
+ .weak vector352, vector353, vector354, vector355
+#endif
+#if PPC_NUM_VECTORS > 356
+ .weak vector356, vector357, vector358, vector359
+#endif
+#if PPC_NUM_VECTORS > 360
+ .weak vector360, vector361, vector362, vector363
+#endif
+#if PPC_NUM_VECTORS > 364
+ .weak vector364, vector365, vector366, vector367
+#endif
+#if PPC_NUM_VECTORS > 368
+ .weak vector368, vector369, vector370, vector371
+#endif
+#if PPC_NUM_VECTORS > 372
+ .weak vector372, vector373, vector374, vector375
+#endif
+#if PPC_NUM_VECTORS > 376
+ .weak vector376, vector377, vector378, vector379
+#endif
+#if PPC_NUM_VECTORS > 380
+ .weak vector380, vector381, vector382, vector383
+#endif
+#if PPC_NUM_VECTORS > 384
+ .weak vector384, vector385, vector386, vector387
+#endif
+#if PPC_NUM_VECTORS > 388
+ .weak vector388, vector389, vector390, vector391
+#endif
+#if PPC_NUM_VECTORS > 392
+ .weak vector392, vector393, vector394, vector395
+#endif
+#if PPC_NUM_VECTORS > 396
+ .weak vector396, vector397, vector398, vector399
+#endif
+#if PPC_NUM_VECTORS > 400
+ .weak vector400, vector401, vector402, vector403
+#endif
+#if PPC_NUM_VECTORS > 404
+ .weak vector404, vector405, vector406, vector407
+#endif
+#if PPC_NUM_VECTORS > 408
+ .weak vector408, vector409, vector410, vector411
+#endif
+#if PPC_NUM_VECTORS > 412
+ .weak vector412, vector413, vector414, vector415
+#endif
+#if PPC_NUM_VECTORS > 416
+ .weak vector416, vector417, vector418, vector419
+#endif
+#if PPC_NUM_VECTORS > 420
+ .weak vector420, vector421, vector422, vector423
+#endif
+#if PPC_NUM_VECTORS > 424
+ .weak vector424, vector425, vector426, vector427
+#endif
+#if PPC_NUM_VECTORS > 428
+ .weak vector428, vector429, vector430, vector431
+#endif
+#if PPC_NUM_VECTORS > 432
+ .weak vector432, vector433, vector434, vector435
+#endif
+#if PPC_NUM_VECTORS > 436
+ .weak vector436, vector437, vector438, vector439
+#endif
+#if PPC_NUM_VECTORS > 440
+ .weak vector440, vector441, vector442, vector443
+#endif
+#if PPC_NUM_VECTORS > 444
+ .weak vector444, vector445, vector446, vector447
+#endif
+#if PPC_NUM_VECTORS > 448
+ .weak vector448, vector449, vector450, vector451
+#endif
+#if PPC_NUM_VECTORS > 452
+ .weak vector452, vector453, vector454, vector455
+#endif
+#if PPC_NUM_VECTORS > 456
+ .weak vector456, vector457, vector458, vector459
+#endif
+#if PPC_NUM_VECTORS > 460
+ .weak vector460, vector461, vector462, vector463
+#endif
+#if PPC_NUM_VECTORS > 464
+ .weak vector464, vector465, vector466, vector467
+#endif
+#if PPC_NUM_VECTORS > 468
+ .weak vector468, vector469, vector470, vector471
+#endif
+#if PPC_NUM_VECTORS > 472
+ .weak vector472, vector473, vector474, vector475
+#endif
+#if PPC_NUM_VECTORS > 476
+ .weak vector476, vector477, vector478, vector479
+#endif
+#if PPC_NUM_VECTORS > 480
+ .weak vector480, vector481, vector482, vector483
+#endif
+#if PPC_NUM_VECTORS > 484
+ .weak vector484, vector485, vector486, vector487
+#endif
+#if PPC_NUM_VECTORS > 488
+ .weak vector488, vector489, vector490, vector491
+#endif
+#if PPC_NUM_VECTORS > 492
+ .weak vector492, vector493, vector494, vector495
+#endif
+#if PPC_NUM_VECTORS > 496
+ .weak vector496, vector497, vector498, vector499
+#endif
+#if PPC_NUM_VECTORS > 500
+ .weak vector500, vector501, vector502, vector503
+#endif
+#if PPC_NUM_VECTORS > 504
+ .weak vector504, vector505, vector506, vector507
+#endif
+#if PPC_NUM_VECTORS > 508
+ .weak vector508, vector509, vector510, vector511
+#endif
+#if PPC_NUM_VECTORS > 512
+ .weak vector512, vector513, vector514, vector515
+#endif
+#if PPC_NUM_VECTORS > 516
+ .weak vector516, vector517, vector518, vector519
+#endif
+#if PPC_NUM_VECTORS > 520
+ .weak vector520, vector521, vector522, vector523
+#endif
+#if PPC_NUM_VECTORS > 524
+ .weak vector524, vector525, vector526, vector527
+#endif
+#if PPC_NUM_VECTORS > 528
+ .weak vector528, vector529, vector530, vector531
+#endif
+#if PPC_NUM_VECTORS > 532
+ .weak vector532, vector533, vector534, vector535
+#endif
+#if PPC_NUM_VECTORS > 536
+ .weak vector536, vector537, vector538, vector539
+#endif
+#if PPC_NUM_VECTORS > 540
+ .weak vector540, vector541, vector542, vector543
+#endif
+#if PPC_NUM_VECTORS > 544
+ .weak vector544, vector545, vector546, vector547
+#endif
+#if PPC_NUM_VECTORS > 548
+ .weak vector548, vector549, vector550, vector551
+#endif
+#if PPC_NUM_VECTORS > 552
+ .weak vector552, vector553, vector554, vector555
+#endif
+#if PPC_NUM_VECTORS > 556
+ .weak vector556, vector557, vector558, vector559
+#endif
+#if PPC_NUM_VECTORS > 560
+ .weak vector560, vector561, vector562, vector563
+#endif
+#if PPC_NUM_VECTORS > 564
+ .weak vector564, vector565, vector566, vector567
+#endif
+#if PPC_NUM_VECTORS > 568
+ .weak vector568, vector569, vector570, vector571
+#endif
+#if PPC_NUM_VECTORS > 572
+ .weak vector572, vector573, vector574, vector575
+#endif
+#if PPC_NUM_VECTORS > 576
+ .weak vector576, vector577, vector578, vector579
+#endif
+#if PPC_NUM_VECTORS > 580
+ .weak vector580, vector581, vector582, vector583
+#endif
+#if PPC_NUM_VECTORS > 584
+ .weak vector584, vector585, vector586, vector587
+#endif
+#if PPC_NUM_VECTORS > 588
+ .weak vector588, vector589, vector590, vector591
+#endif
+#if PPC_NUM_VECTORS > 592
+ .weak vector592, vector593, vector594, vector595
+#endif
+#if PPC_NUM_VECTORS > 596
+ .weak vector596, vector597, vector598, vector599
+#endif
+#if PPC_NUM_VECTORS > 600
+ .weak vector600, vector601, vector602, vector603
+#endif
+#if PPC_NUM_VECTORS > 604
+ .weak vector604, vector605, vector606, vector607
+#endif
+#if PPC_NUM_VECTORS > 608
+ .weak vector608, vector609, vector610, vector611
+#endif
+#if PPC_NUM_VECTORS > 612
+ .weak vector612, vector613, vector614, vector615
+#endif
+#if PPC_NUM_VECTORS > 616
+ .weak vector616, vector617, vector618, vector619
+#endif
+#if PPC_NUM_VECTORS > 620
+ .weak vector620, vector621, vector622, vector623
+#endif
+#if PPC_NUM_VECTORS > 624
+ .weak vector624, vector625, vector626, vector627
+#endif
+#if PPC_NUM_VECTORS > 628
+ .weak vector628, vector629, vector630, vector631
+#endif
+#if PPC_NUM_VECTORS > 632
+ .weak vector632, vector633, vector634, vector635
+#endif
+#if PPC_NUM_VECTORS > 636
+ .weak vector636, vector637, vector638, vector639
+#endif
+#if PPC_NUM_VECTORS > 640
+ .weak vector640, vector641, vector642, vector643
+#endif
+#if PPC_NUM_VECTORS > 644
+ .weak vector644, vector645, vector646, vector647
+#endif
+#if PPC_NUM_VECTORS > 648
+ .weak vector648, vector649, vector650, vector651
+#endif
+#if PPC_NUM_VECTORS > 652
+ .weak vector652, vector653, vector654, vector655
+#endif
+#if PPC_NUM_VECTORS > 656
+ .weak vector656, vector657, vector658, vector659
+#endif
+#if PPC_NUM_VECTORS > 660
+ .weak vector660, vector661, vector662, vector663
+#endif
+#if PPC_NUM_VECTORS > 664
+ .weak vector664, vector665, vector666, vector667
+#endif
+#if PPC_NUM_VECTORS > 668
+ .weak vector668, vector669, vector670, vector671
+#endif
+#if PPC_NUM_VECTORS > 672
+ .weak vector672, vector673, vector674, vector675
+#endif
+#if PPC_NUM_VECTORS > 676
+ .weak vector676, vector677, vector678, vector679
+#endif
+#if PPC_NUM_VECTORS > 680
+ .weak vector680, vector681, vector682, vector683
+#endif
+#if PPC_NUM_VECTORS > 684
+ .weak vector684, vector685, vector686, vector687
+#endif
+#if PPC_NUM_VECTORS > 688
+ .weak vector688, vector689, vector690, vector691
+#endif
+#if PPC_NUM_VECTORS > 692
+ .weak vector692, vector693, vector694, vector695
+#endif
+#if PPC_NUM_VECTORS > 696
+ .weak vector696, vector697, vector698, vector699
+#endif
+#if PPC_NUM_VECTORS > 700
+ .weak vector700, vector701, vector702, vector703
+#endif
+#if PPC_NUM_VECTORS > 704
+ .weak vector704, vector705, vector706, vector707
+#endif
+#if PPC_NUM_VECTORS > 708
+ .weak vector708, vector709, vector710, vector711
+#endif
+#if PPC_NUM_VECTORS > 712
+ .weak vector712, vector713, vector714, vector715
+#endif
+#if PPC_NUM_VECTORS > 716
+ .weak vector716, vector717, vector718, vector719
+#endif
+#if PPC_NUM_VECTORS > 720
+ .weak vector720, vector721, vector722, vector723
+#endif
+#if PPC_NUM_VECTORS > 724
+ .weak vector724, vector725, vector726, vector727
+#endif
+#if PPC_NUM_VECTORS > 728
+ .weak vector728, vector729, vector730, vector731
+#endif
+#if PPC_NUM_VECTORS > 732
+ .weak vector732, vector733, vector734, vector735
+#endif
+#if PPC_NUM_VECTORS > 736
+ .weak vector736, vector737, vector738, vector739
+#endif
+#if PPC_NUM_VECTORS > 740
+ .weak vector740, vector741, vector742, vector743
+#endif
+#if PPC_NUM_VECTORS > 744
+ .weak vector744, vector745, vector746, vector747
+#endif
+#if PPC_NUM_VECTORS > 748
+ .weak vector748, vector749, vector750, vector751
+#endif
+#if PPC_NUM_VECTORS > 752
+ .weak vector752, vector753, vector754, vector755
+#endif
+#if PPC_NUM_VECTORS > 756
+ .weak vector756, vector757, vector758, vector759
+#endif
+#if PPC_NUM_VECTORS > 760
+ .weak vector760, vector761, vector762, vector763
+#endif
+#if PPC_NUM_VECTORS > 764
+ .weak vector764, vector765, vector766, vector767
+#endif
+#if PPC_NUM_VECTORS > 768
+ .weak vector768, vector769, vector770, vector771
+#endif
+#if PPC_NUM_VECTORS > 772
+ .weak vector772, vector773, vector774, vector775
+#endif
+#if PPC_NUM_VECTORS > 776
+ .weak vector776, vector777, vector778, vector779
+#endif
+#if PPC_NUM_VECTORS > 780
+ .weak vector780, vector781, vector782, vector783
+#endif
+#if PPC_NUM_VECTORS > 784
+ .weak vector784, vector785, vector786, vector787
+#endif
+#if PPC_NUM_VECTORS > 788
+ .weak vector788, vector789, vector790, vector791
+#endif
+#if PPC_NUM_VECTORS > 792
+ .weak vector792, vector793, vector794, vector795
+#endif
+#if PPC_NUM_VECTORS > 796
+ .weak vector796, vector797, vector798, vector799
+#endif
+#if PPC_NUM_VECTORS > 800
+ .weak vector800, vector801, vector802, vector803
+#endif
+#if PPC_NUM_VECTORS > 804
+ .weak vector804, vector805, vector806, vector807
+#endif
+#if PPC_NUM_VECTORS > 808
+ .weak vector808, vector809, vector810, vector811
+#endif
+#if PPC_NUM_VECTORS > 812
+ .weak vector812, vector813, vector814, vector815
+#endif
+#if PPC_NUM_VECTORS > 816
+ .weak vector816, vector817, vector818, vector819
+#endif
+#if PPC_NUM_VECTORS > 820
+ .weak vector820, vector821, vector822, vector823
+#endif
+#if PPC_NUM_VECTORS > 824
+ .weak vector824, vector825, vector826, vector827
+#endif
+#if PPC_NUM_VECTORS > 828
+ .weak vector828, vector829, vector830, vector831
+#endif
+#if PPC_NUM_VECTORS > 832
+ .weak vector832, vector833, vector834, vector835
+#endif
+#if PPC_NUM_VECTORS > 836
+ .weak vector836, vector837, vector838, vector839
+#endif
+#if PPC_NUM_VECTORS > 840
+ .weak vector840, vector841, vector842, vector843
+#endif
+#if PPC_NUM_VECTORS > 844
+ .weak vector844, vector845, vector846, vector847
+#endif
+#if PPC_NUM_VECTORS > 848
+ .weak vector848, vector849, vector850, vector851
+#endif
+#if PPC_NUM_VECTORS > 852
+ .weak vector852, vector853, vector854, vector855
+#endif
+#if PPC_NUM_VECTORS > 856
+ .weak vector856, vector857, vector858, vector859
+#endif
+#if PPC_NUM_VECTORS > 860
+ .weak vector860, vector861, vector862, vector863
+#endif
+#if PPC_NUM_VECTORS > 864
+ .weak vector864, vector865, vector866, vector867
+#endif
+#if PPC_NUM_VECTORS > 868
+ .weak vector868, vector869, vector870, vector871
+#endif
+#if PPC_NUM_VECTORS > 872
+ .weak vector872, vector873, vector874, vector875
+#endif
+#if PPC_NUM_VECTORS > 876
+ .weak vector876, vector877, vector878, vector879
+#endif
+#if PPC_NUM_VECTORS > 880
+ .weak vector880, vector881, vector882, vector883
+#endif
+#if PPC_NUM_VECTORS > 884
+ .weak vector884, vector885, vector886, vector887
+#endif
+#if PPC_NUM_VECTORS > 888
+ .weak vector888, vector889, vector890, vector891
+#endif
+#if PPC_NUM_VECTORS > 892
+ .weak vector892, vector893, vector894, vector895
+#endif
+#if PPC_NUM_VECTORS > 896
+ .weak vector896, vector897, vector898, vector899
+#endif
+#if PPC_NUM_VECTORS > 900
+ .weak vector900, vector901, vector902, vector903
+#endif
+#if PPC_NUM_VECTORS > 904
+ .weak vector904, vector905, vector906, vector907
+#endif
+#if PPC_NUM_VECTORS > 908
+ .weak vector908, vector909, vector910, vector911
+#endif
+#if PPC_NUM_VECTORS > 912
+ .weak vector912, vector913, vector914, vector915
+#endif
+#if PPC_NUM_VECTORS > 916
+ .weak vector916, vector917, vector918, vector919
+#endif
+#if PPC_NUM_VECTORS > 920
+ .weak vector920, vector921, vector922, vector923
+#endif
+#if PPC_NUM_VECTORS > 924
+ .weak vector924, vector925, vector926, vector927
+#endif
+#if PPC_NUM_VECTORS > 928
+ .weak vector928, vector929, vector930, vector931
+#endif
+#if PPC_NUM_VECTORS > 932
+ .weak vector932, vector933, vector934, vector935
+#endif
+#if PPC_NUM_VECTORS > 936
+ .weak vector936, vector937, vector938, vector939
+#endif
+#if PPC_NUM_VECTORS > 940
+ .weak vector940, vector941, vector942, vector943
+#endif
+#if PPC_NUM_VECTORS > 944
+ .weak vector944, vector945, vector946, vector947
+#endif
+#if PPC_NUM_VECTORS > 948
+ .weak vector948, vector949, vector950, vector951
+#endif
+#if PPC_NUM_VECTORS > 952
+ .weak vector952, vector953, vector954, vector955
+#endif
+#if PPC_NUM_VECTORS > 956
+ .weak vector956, vector957, vector958, vector959
+#endif
+#if PPC_NUM_VECTORS > 960
+ .weak vector960, vector961, vector962, vector963
+#endif
+#if PPC_NUM_VECTORS > 964
+ .weak vector964, vector965, vector966, vector967
+#endif
+#if PPC_NUM_VECTORS > 968
+ .weak vector968, vector969, vector970, vector971
+#endif
+#if PPC_NUM_VECTORS > 972
+ .weak vector972, vector973, vector974, vector975
+#endif
+#if PPC_NUM_VECTORS > 976
+ .weak vector976, vector977, vector978, vector979
+#endif
+#if PPC_NUM_VECTORS > 980
+ .weak vector980, vector981, vector982, vector983
+#endif
+#if PPC_NUM_VECTORS > 984
+ .weak vector984, vector985, vector986, vector987
+#endif
+#if PPC_NUM_VECTORS > 988
+ .weak vector988, vector989, vector990, vector991
+#endif
+#if PPC_NUM_VECTORS > 992
+ .weak vector992, vector993, vector994, vector995
+#endif
+#if PPC_NUM_VECTORS > 996
+ .weak vector996, vector997, vector998, vector999
+#endif
+#if PPC_NUM_VECTORS > 1000
+ .weak vector1000, vector1001, vector1002, vector1003
+#endif
+#if PPC_NUM_VECTORS > 1004
+ .weak vector1004, vector1005, vector1006, vector1007
+#endif
+#if PPC_NUM_VECTORS > 1008
+ .weak vector1008, vector1009, vector1010, vector1011
+#endif
+#if PPC_NUM_VECTORS > 1012
+ .weak vector1012, vector1013, vector1014, vector1015
+#endif
+#if PPC_NUM_VECTORS > 1016
+ .weak vector1016, vector1017, vector1018, vector1019
+#endif
+#if PPC_NUM_VECTORS > 1020
+ .weak vector1020, vector1021, vector1022, vector1023
+#endif
+
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+vector977:
+vector978:
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+vector980:
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+vector984:
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+vector986:
+vector987:
+vector988:
+vector989:
+vector990:
+vector991:
+vector992:
+vector993:
+vector994:
+vector995:
+vector996:
+vector997:
+vector998:
+vector999:
+vector1000:
+vector1001:
+vector1002:
+vector1003:
+vector1004:
+vector1005:
+vector1006:
+vector1007:
+vector1008:
+vector1009:
+vector1010:
+vector1011:
+vector1012:
+vector1013:
+vector1014:
+vector1015:
+vector1016:
+vector1017:
+vector1018:
+vector1019:
+vector1020:
+vector1021:
+vector1022:
+vector1023:
+ e_b _unhandled_irq
+
+ .weak _unhandled_irq
+ .type _unhandled_irq, @function
+_unhandled_irq:
+ e_b _unhandled_irq
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560BCxx/boot.S b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560BCxx/boot.S new file mode 100644 index 0000000..d4dd163 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560BCxx/boot.S @@ -0,0 +1,218 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560BCxx/boot.s
+ * @brief SPC560BCxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if defined(__HIGHTEC__)
+#define se_bge bge
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ e_bl _coreinit
+#endif
+ e_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_or2i r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ se_blr
+
+ .section .ivors, "ax"
+
+ .globl IVORS
+IVORS:
+ e_b _IVOR0
+ .align 4
+ e_b _IVOR1
+ .align 4
+ e_b _IVOR2
+ .align 4
+ e_b _IVOR3
+ .align 4
+ e_b _IVOR4
+ .align 4
+ e_b _IVOR5
+ .align 4
+ e_b _IVOR6
+ .align 4
+ e_b _IVOR7
+ .align 4
+ e_b _IVOR8
+ .align 4
+ e_b _IVOR9
+ .align 4
+ e_b _IVOR10
+ .align 4
+ e_b _IVOR11
+ .align 4
+ e_b _IVOR12
+ .align 4
+ e_b _IVOR13
+ .align 4
+ e_b _IVOR14
+ .align 4
+ e_b _IVOR15
+
+ .section .handlers, "ax"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+ .global _unhandled_exception
+_unhandled_exception:
+ se_b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560BCxx/boot.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560BCxx/boot.h new file mode 100644 index 0000000..b54da3b --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560BCxx/boot.h @@ -0,0 +1,114 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC560BCxx.
+ * @{
+ */
+
+#ifndef BOOT_H
+#define BOOT_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_ME 0x00001000
+#define MSR_DE 0x00000200
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* BOOT_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560BCxx/intc.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560BCxx/intc.h new file mode 100644 index 0000000..0c92ba4 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560BCxx/intc.h @@ -0,0 +1,93 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560BCxx/intc.h
+ * @brief SPC560BCxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef INTC_H
+#define INTC_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* INTC_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560BCxx/ppcparams.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560BCxx/ppcparams.h new file mode 100644 index 0000000..d17d5cf --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560BCxx/ppcparams.h @@ -0,0 +1,83 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560BCxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC560BCxx.
+ *
+ * @defgroup PPC_SPC560BCxx SPC560BCxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC560BCxx platform.
+ * @{
+ */
+
+#ifndef PPCPARAMS_H
+#define PPCPARAMS_H
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC560BCxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z0
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 20
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS FALSE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE FALSE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER FALSE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 217
+
+#endif /* PPCPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Bxx/boot.S b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Bxx/boot.S new file mode 100644 index 0000000..2f87029 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Bxx/boot.S @@ -0,0 +1,218 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Bxx/boot.s
+ * @brief SPC560Bxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if defined(__HIGHTEC__)
+#define se_bge bge
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ e_bl _coreinit
+#endif
+ e_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_or2i r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ se_blr
+
+ .section .ivors, "ax"
+
+ .globl IVORS
+IVORS:
+ e_b _IVOR0
+ .align 4
+ e_b _IVOR1
+ .align 4
+ e_b _IVOR2
+ .align 4
+ e_b _IVOR3
+ .align 4
+ e_b _IVOR4
+ .align 4
+ e_b _IVOR5
+ .align 4
+ e_b _IVOR6
+ .align 4
+ e_b _IVOR7
+ .align 4
+ e_b _IVOR8
+ .align 4
+ e_b _IVOR9
+ .align 4
+ e_b _IVOR10
+ .align 4
+ e_b _IVOR11
+ .align 4
+ e_b _IVOR12
+ .align 4
+ e_b _IVOR13
+ .align 4
+ e_b _IVOR14
+ .align 4
+ e_b _IVOR15
+
+ .section .handlers, "ax"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+ .global _unhandled_exception
+_unhandled_exception:
+ se_b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Bxx/boot.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Bxx/boot.h new file mode 100644 index 0000000..8fe5f7c --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Bxx/boot.h @@ -0,0 +1,114 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC560Bxx.
+ * @{
+ */
+
+#ifndef BOOT_H
+#define BOOT_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_ME 0x00001000
+#define MSR_DE 0x00000200
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* BOOT_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Bxx/intc.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Bxx/intc.h new file mode 100644 index 0000000..92f4b22 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Bxx/intc.h @@ -0,0 +1,93 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Bxx/intc.h
+ * @brief SPC560Bxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef INTC_H
+#define INTC_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* INTC_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Bxx/ppcparams.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Bxx/ppcparams.h new file mode 100644 index 0000000..ed9165c --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Bxx/ppcparams.h @@ -0,0 +1,83 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Bxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC560Bxx.
+ *
+ * @defgroup PPC_SPC560Bxx SPC560Bxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC560Bxx platform.
+ * @{
+ */
+
+#ifndef PPCPARAMS_H
+#define PPCPARAMS_H
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC560Bxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z0
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 20
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS FALSE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE FALSE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER FALSE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 234
+
+#endif /* PPCPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/boot.S b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/boot.S new file mode 100644 index 0000000..78fb871 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/boot.S @@ -0,0 +1,218 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Dxx/boot.s
+ * @brief SPC560Dxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if defined(__HIGHTEC__)
+#define se_bge bge
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ e_bl _coreinit
+#endif
+ e_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_or2i r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ se_blr
+
+ .section .ivors, "ax"
+
+ .globl IVORS
+IVORS:
+ e_b _IVOR0
+ .align 4
+ e_b _IVOR1
+ .align 4
+ e_b _IVOR2
+ .align 4
+ e_b _IVOR3
+ .align 4
+ e_b _IVOR4
+ .align 4
+ e_b _IVOR5
+ .align 4
+ e_b _IVOR6
+ .align 4
+ e_b _IVOR7
+ .align 4
+ e_b _IVOR8
+ .align 4
+ e_b _IVOR9
+ .align 4
+ e_b _IVOR10
+ .align 4
+ e_b _IVOR11
+ .align 4
+ e_b _IVOR12
+ .align 4
+ e_b _IVOR13
+ .align 4
+ e_b _IVOR14
+ .align 4
+ e_b _IVOR15
+
+ .section .handlers, "ax"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+ .global _unhandled_exception
+_unhandled_exception:
+ e_b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/boot.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/boot.h new file mode 100644 index 0000000..9c9605a --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/boot.h @@ -0,0 +1,114 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC560Dxx.
+ * @{
+ */
+
+#ifndef BOOT_H
+#define BOOT_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_ME 0x00001000
+#define MSR_DE 0x00000200
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* BOOT_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/boot_cw.s b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/boot_cw.s new file mode 100644 index 0000000..ef8851b --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/boot_cw.s @@ -0,0 +1,200 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Dxx/boot.s
+ * @brief SPC560Dxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ .extern _boot_address
+ .extern __ram_start__
+ .extern __ram_end__
+ .extern __ivpr_base__
+
+ .extern _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .extern _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .extern _IVOR12, _IVOR13, _IVOR14, _IVOR15
+
+ /* BAM record.*/
+ .section .boot, 16
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 4
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ se_bl _coreinit
+#endif
+ se_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 4
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 4
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_ori r3, r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ se_blr
+
+ .section .ivors, text_vle
+ .align 16
+ .globl IVORS
+IVORS:
+ e_b _IVOR0
+ .align 16
+ e_b _IVOR1
+ .align 16
+ e_b _IVOR2
+ .align 16
+ e_b _IVOR3
+ .align 16
+ e_b _IVOR4
+ .align 16
+ e_b _IVOR5
+ .align 16
+ e_b _IVOR6
+ .align 16
+ e_b _IVOR7
+ .align 16
+ e_b _IVOR8
+ .align 16
+ e_b _IVOR9
+ .align 16
+ e_b _IVOR10
+ .align 16
+ e_b _IVOR11
+ .align 16
+ e_b _IVOR12
+ .align 16
+ e_b _IVOR13
+ .align 16
+ e_b _IVOR14
+ .align 16
+ e_b _IVOR15
+
+ .section .handlers, text_vle
+ .align 16
+
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/boot_ghs.s b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/boot_ghs.s new file mode 100644 index 0000000..5026cb1 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/boot_ghs.s @@ -0,0 +1,216 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Dxx/boot_ghs.s
+ * @brief SPC560Dxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ .vle
+
+ /* BAM record.*/
+ .section .boot, "axv"
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ e_bl _coreinit
+#endif
+ e_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_or2i r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ se_blr
+
+ .section .ivors, "axv"
+
+ .globl IVORS
+IVORS:
+ e_b _IVOR0
+ .align 4
+ e_b _IVOR1
+ .align 4
+ e_b _IVOR2
+ .align 4
+ e_b _IVOR3
+ .align 4
+ e_b _IVOR4
+ .align 4
+ e_b _IVOR5
+ .align 4
+ e_b _IVOR6
+ .align 4
+ e_b _IVOR7
+ .align 4
+ e_b _IVOR8
+ .align 4
+ e_b _IVOR9
+ .align 4
+ e_b _IVOR10
+ .align 4
+ e_b _IVOR11
+ .align 4
+ e_b _IVOR12
+ .align 4
+ e_b _IVOR13
+ .align 4
+ e_b _IVOR14
+ .align 4
+ e_b _IVOR15
+
+ .section .handlers, "axv"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+ .global _unhandled_exception
+_unhandled_exception:
+ e_b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/intc.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/intc.h new file mode 100644 index 0000000..e12f50d --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/intc.h @@ -0,0 +1,93 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Dxx/intc.h
+ * @brief SPC560Dxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef INTC_H
+#define INTC_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* INTC_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/ppcparams.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/ppcparams.h new file mode 100644 index 0000000..ae21300 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Dxx/ppcparams.h @@ -0,0 +1,83 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Dxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC560Dxx.
+ *
+ * @defgroup PPC_SPC560Dxx SPC560Dxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC560Dxx platform.
+ * @{
+ */
+
+#ifndef PPCPARAMS_H
+#define PPCPARAMS_H
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC560Dxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z0
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 20
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS FALSE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE FALSE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER FALSE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 155
+
+#endif /* PPCPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Pxx/boot.S b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Pxx/boot.S new file mode 100644 index 0000000..8c8c7e2 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Pxx/boot.S @@ -0,0 +1,218 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Pxx/boot.s
+ * @brief SPC560Pxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if defined(__HIGHTEC__)
+#define se_bge bge
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ e_bl _coreinit
+#endif
+ e_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_or2i r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ se_blr
+
+ .section .ivors, "ax"
+
+ .globl IVORS
+IVORS:
+ e_b _IVOR0
+ .align 4
+ e_b _IVOR1
+ .align 4
+ e_b _IVOR2
+ .align 4
+ e_b _IVOR3
+ .align 4
+ e_b _IVOR4
+ .align 4
+ e_b _IVOR5
+ .align 4
+ e_b _IVOR6
+ .align 4
+ e_b _IVOR7
+ .align 4
+ e_b _IVOR8
+ .align 4
+ e_b _IVOR9
+ .align 4
+ e_b _IVOR10
+ .align 4
+ e_b _IVOR11
+ .align 4
+ e_b _IVOR12
+ .align 4
+ e_b _IVOR13
+ .align 4
+ e_b _IVOR14
+ .align 4
+ e_b _IVOR15
+
+ .section .handlers, "ax"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+ .global _unhandled_exception
+_unhandled_exception:
+ se_b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Pxx/boot.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Pxx/boot.h new file mode 100644 index 0000000..c928a9a --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Pxx/boot.h @@ -0,0 +1,114 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC560Pxx.
+ * @{
+ */
+
+#ifndef BOOT_H
+#define BOOT_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_ME 0x00001000
+#define MSR_DE 0x00000200
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* BOOT_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Pxx/intc.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Pxx/intc.h new file mode 100644 index 0000000..281a783 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Pxx/intc.h @@ -0,0 +1,93 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Pxx/intc.h
+ * @brief SPC560Pxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef INTC_H
+#define INTC_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* INTC_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Pxx/ppcparams.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Pxx/ppcparams.h new file mode 100644 index 0000000..7cce954 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC560Pxx/ppcparams.h @@ -0,0 +1,83 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Pxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC560Pxx.
+ *
+ * @defgroup PPC_SPC560Pxx SPC560Pxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC560Pxx platform.
+ * @{
+ */
+
+#ifndef PPCPARAMS_H
+#define PPCPARAMS_H
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC560Pxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z0
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 20
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS FALSE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE FALSE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER FALSE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 261
+
+#endif /* PPCPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/boot.S b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/boot.S new file mode 100644 index 0000000..04f297c --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/boot.S @@ -0,0 +1,192 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC563Mxx/boot.s
+ * @brief SPC563Mxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if defined(__HIGHTEC__)
+#define se_bge bge
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ e_bl _coreinit
+#endif
+ e_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_or2i r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ /* IVORs initialization.*/
+ e_lis r3, _unhandled_exception@h
+ e_or2i r3, _unhandled_exception@l
+
+ mtspr 400, r3 /* IVOR0-15 */
+ mtspr 401, r3
+ mtspr 402, r3
+ mtspr 403, r3
+ mtspr 404, r3
+ mtspr 405, r3
+ mtspr 406, r3
+ mtspr 407, r3
+ mtspr 408, r3
+ mtspr 409, r3
+ mtspr 410, r3
+ mtspr 411, r3
+ mtspr 412, r3
+ mtspr 413, r3
+ mtspr 414, r3
+ mtspr 415, r3
+ mtspr 528, r3 /* IVOR32-34 */
+ mtspr 529, r3
+ mtspr 530, r3
+
+ se_blr
+
+ .section .handlers, "ax"
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _unhandled_exception
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ se_b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/boot.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/boot.h new file mode 100644 index 0000000..f9168f5 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/boot.h @@ -0,0 +1,119 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC563Mxx.
+ * @{
+ */
+
+#ifndef BOOT_H
+#define BOOT_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_UCLE 0x04000000
+#define MSR_SPE 0x02000000
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_FP 0x00002000
+#define MSR_ME 0x00001000
+#define MSR_FE0 0x00000800
+#define MSR_DE 0x00000200
+#define MSR_FE1 0x00000100
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* BOOT_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/intc.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/intc.h new file mode 100644 index 0000000..c60b31c --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/intc.h @@ -0,0 +1,93 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC563Mxx/intc.h
+ * @brief SPC563Mxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef INTC_H
+#define INTC_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* INTC_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/ppcparams.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/ppcparams.h new file mode 100644 index 0000000..705e3fc --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC563Mxx/ppcparams.h @@ -0,0 +1,83 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC563Mxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC563Mxx.
+ *
+ * @defgroup PPC_SPC563Mxx SPC563Mxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC563Mxx platform.
+ * @{
+ */
+
+#ifndef PPCPARAMS_H
+#define PPCPARAMS_H
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC563Mxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z3
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 16
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS TRUE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE TRUE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER TRUE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 360
+
+#endif /* PPCPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.S b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.S new file mode 100644 index 0000000..cd20b66 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.S @@ -0,0 +1,357 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC564Axx/boot.s
+ * @brief SPC564Axx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if defined(__HIGHTEC__)
+#define se_bge bge
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ e_bl _coreinit
+#endif
+ e_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_ramcode:
+ tlbwe
+ se_isync
+ se_blr
+
+ .align 2
+_coreinit:
+ /*
+ * Invalidating all TLBs except TLB1.
+ */
+ e_lis r3, 0
+ mtspr 625, r3 /* MAS1 */
+ mtspr 626, r3 /* MAS2 */
+ mtspr 627, r3 /* MAS3 */
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+
+ /*
+ * TLB0 allocated to internal RAM.
+ */
+ e_lis r3, TLB0_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB0_MAS1@h
+ e_or2i r3, TLB0_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB0_MAS2@h
+ e_or2i r3, TLB0_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB0_MAS3@h
+ e_or2i r3, TLB0_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB2 allocated to internal Peripherals Bridge A.
+ */
+ e_lis r3, TLB2_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB2_MAS1@h
+ e_or2i r3, TLB2_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB2_MAS2@h
+ e_or2i r3, TLB2_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB2_MAS3@h
+ e_or2i r3, TLB2_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB3 allocated to internal Peripherals Bridge B.
+ */
+ e_lis r3, TLB3_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB3_MAS1@h
+ e_or2i r3, TLB3_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB3_MAS2@h
+ e_or2i r3, TLB3_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB3_MAS3@h
+ e_or2i r3, TLB3_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB4 allocated to on-platform peripherals.
+ */
+ e_lis r3, TLB4_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB4_MAS1@h
+ e_or2i r3, TLB4_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB4_MAS2@h
+ e_or2i r3, TLB4_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB4_MAS3@h
+ e_or2i r3, TLB4_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+
+ /*
+ * *Finally* the TLB1 is re-allocated to flash, note, the final phase
+ * is executed from RAM.
+ */
+ e_lis r3, TLB1_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB1_MAS1@h
+ e_or2i r3, TLB1_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB1_MAS2@h
+ e_or2i r3, TLB1_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB1_MAS3@h
+ e_or2i r3, TLB1_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ mflr r4
+ e_lis r6, _ramcode@h
+ e_or2i r6, _ramcode@l
+ e_lis r7, 0x40010000@h
+ mtctr r7
+ se_lwz r3, 0(r6)
+ se_stw r3, 0(r7)
+ se_lwz r3, 4(r6)
+ se_stw r3, 4(r7)
+ se_lwz r3, 8(r6)
+ se_stw r3, 8(r7)
+ se_bctrl
+ mtlr r4
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ /*
+ * Cache invalidated and then enabled.
+ */
+ e_li r3, LICSR1_ICINV
+ mtspr 1011, r3 /* LICSR1 */
+.inv: mfspr r3, 1011 /* LICSR1 */
+ e_and2i. r3, LICSR1_ICINV
+ se_bne .inv
+ e_lis r3, BOOT_LICSR1_DEFAULT@h
+ e_or2i r3, BOOT_LICSR1_DEFAULT@l
+ mtspr 1011, r3 /* LICSR1 */
+
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_or2i r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ /* IVORs initialization.*/
+ e_lis r3, _unhandled_exception@h
+ e_or2i r3, _unhandled_exception@l
+
+ mtspr 400, r3 /* IVOR0-15 */
+ mtspr 401, r3
+ mtspr 402, r3
+ mtspr 403, r3
+ mtspr 404, r3
+ mtspr 405, r3
+ mtspr 406, r3
+ mtspr 407, r3
+ mtspr 408, r3
+ mtspr 409, r3
+ mtspr 410, r3
+ mtspr 411, r3
+ mtspr 412, r3
+ mtspr 413, r3
+ mtspr 414, r3
+ mtspr 415, r3
+ mtspr 528, r3 /* IVOR32-34 */
+ mtspr 529, r3
+ mtspr 530, r3
+
+ se_blr
+
+ .section .handlers, "ax"
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _unhandled_exception
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ se_b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.h new file mode 100644 index 0000000..fb07f22 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.h @@ -0,0 +1,242 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC564Axx.
+ * @{
+ */
+
+#ifndef BOOT_H
+#define BOOT_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name MASx registers definitions
+ * @{
+ */
+#define MAS0_TBLMAS_TBL 0x10000000
+#define MAS0_ESEL_MASK 0x000F0000
+#define MAS0_ESEL(n) ((n) << 16)
+
+#define MAS1_VALID 0x80000000
+#define MAS1_IPROT 0x40000000
+#define MAS1_TID_MASK 0x00FF0000
+#define MAS1_TS 0x00001000
+#define MAS1_TSISE_MASK 0x00000F80
+#define MAS1_TSISE_1K 0x00000000
+#define MAS1_TSISE_2K 0x00000080
+#define MAS1_TSISE_4K 0x00000100
+#define MAS1_TSISE_8K 0x00000180
+#define MAS1_TSISE_16K 0x00000200
+#define MAS1_TSISE_32K 0x00000280
+#define MAS1_TSISE_64K 0x00000300
+#define MAS1_TSISE_128K 0x00000380
+#define MAS1_TSISE_256K 0x00000400
+#define MAS1_TSISE_512K 0x00000480
+#define MAS1_TSISE_1M 0x00000500
+#define MAS1_TSISE_2M 0x00000580
+#define MAS1_TSISE_4M 0x00000600
+#define MAS1_TSISE_8M 0x00000680
+#define MAS1_TSISE_16M 0x00000700
+#define MAS1_TSISE_32M 0x00000780
+#define MAS1_TSISE_64M 0x00000800
+#define MAS1_TSISE_128M 0x00000880
+#define MAS1_TSISE_256M 0x00000900
+#define MAS1_TSISE_512M 0x00000980
+#define MAS1_TSISE_1G 0x00000A00
+#define MAS1_TSISE_2G 0x00000A80
+#define MAS1_TSISE_4G 0x00000B00
+
+#define MAS2_EPN_MASK 0xFFFFFC00
+#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
+#define MAS2_EBOOK 0x00000000
+#define MAS2_VLE 0x00000020
+#define MAS2_W 0x00000010
+#define MAS2_I 0x00000008
+#define MAS2_M 0x00000004
+#define MAS2_G 0x00000002
+#define MAS2_E 0x00000001
+
+#define MAS3_RPN_MASK 0xFFFFFC00
+#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
+#define MAS3_U0 0x00000200
+#define MAS3_U1 0x00000100
+#define MAS3_U2 0x00000080
+#define MAS3_U3 0x00000040
+#define MAS3_UX 0x00000020
+#define MAS3_SX 0x00000010
+#define MAS3_UW 0x00000008
+#define MAS3_SW 0x00000004
+#define MAS3_UR 0x00000002
+#define MAS3_SR 0x00000001
+/** @} */
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BPRED_MASK 0x00000006
+#define BUCSR_BPRED_0 0x00000000
+#define BUCSR_BPRED_1 0x00000002
+#define BUCSR_BPRED_2 0x00000004
+#define BUCSR_BPRED_3 0x00000006
+#define BUCSR_BALLOC_MASK 0x00000030
+#define BUCSR_BALLOC_0 0x00000000
+#define BUCSR_BALLOC_1 0x00000010
+#define BUCSR_BALLOC_2 0x00000020
+#define BUCSR_BALLOC_3 0x00000030
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name LICSR1 registers definitions
+ * @{
+ */
+#define LICSR1_ICE 0x00000001
+#define LICSR1_ICINV 0x00000002
+#define LICSR1_ICORG 0x00000010
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_UCLE 0x04000000
+#define MSR_SPE 0x02000000
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_FP 0x00002000
+#define MSR_ME 0x00001000
+#define MSR_FE0 0x00000800
+#define MSR_DE 0x00000200
+#define MSR_FE1 0x00000100
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * TLB default settings.
+ */
+#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
+#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
+#define TLB0_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
+#define TLB0_MAS3 (MAS3_RPN(0x40000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
+#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
+#define TLB1_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
+#define TLB1_MAS3 (MAS3_RPN(0x00000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
+#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
+#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
+#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
+#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
+#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB4_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
+#define TLB4_MAS3 (MAS3_RPN(0xFFF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
+ BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * LICSR1 default settings.
+ */
+#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* BOOT_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/intc.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/intc.h new file mode 100644 index 0000000..d30418f --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/intc.h @@ -0,0 +1,93 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC564Axx/intc.h
+ * @brief SPC564Axx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef INTC_H
+#define INTC_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* INTC_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/ppcparams.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/ppcparams.h new file mode 100644 index 0000000..cf598fd --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/ppcparams.h @@ -0,0 +1,83 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC564Axx/ppcparams.h
+ * @brief PowerPC parameters for the SPC564Axx.
+ *
+ * @defgroup PPC_SPC564Axx SPC564Axx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC564Axx platform.
+ * @{
+ */
+
+#ifndef PPCPARAMS_H
+#define PPCPARAMS_H
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC564Axx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z4
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 16
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS TRUE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE TRUE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER TRUE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 486
+
+#endif /* PPCPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/boot.S b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/boot.S new file mode 100644 index 0000000..b202cb4 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/boot.S @@ -0,0 +1,408 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ECxx/boot.s
+ * @brief SPC56ECxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if defined(__HIGHTEC__)
+#define se_bge bge
+#define se_bne bne
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ e_bl _coreinit
+#endif
+ e_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_ramcode:
+ tlbwe
+ se_isync
+ se_blr
+
+ .align 2
+_coreinit:
+ /*
+ * Invalidating all TLBs except TLB0.
+ */
+ e_lis r3, 0
+ mtspr 625, r3 /* MAS1 */
+ mtspr 626, r3 /* MAS2 */
+ mtspr 627, r3 /* MAS3 */
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+
+ /*
+ * TLB1 allocated to internal RAM.
+ */
+ e_lis r3, TLB1_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB1_MAS1@h
+ e_or2i r3, TLB1_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB1_MAS2@h
+ e_or2i r3, TLB1_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB1_MAS3@h
+ e_or2i r3, TLB1_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB2 allocated to internal Peripherals Bridge A.
+ */
+ e_lis r3, TLB2_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB2_MAS1@h
+ e_or2i r3, TLB2_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB2_MAS2@h
+ e_or2i r3, TLB2_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB2_MAS3@h
+ e_or2i r3, TLB2_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB3 allocated to internal Peripherals Bridge B.
+ */
+ e_lis r3, TLB3_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB3_MAS1@h
+ e_or2i r3, TLB3_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB3_MAS2@h
+ e_or2i r3, TLB3_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB3_MAS3@h
+ e_or2i r3, TLB3_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB4 allocated to on-platform peripherals.
+ */
+ e_lis r3, TLB4_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB4_MAS1@h
+ e_or2i r3, TLB4_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB4_MAS2@h
+ e_or2i r3, TLB4_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB4_MAS3@h
+ e_or2i r3, TLB4_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB5 allocated to on-platform peripherals.
+ */
+ e_lis r3, TLB5_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB5_MAS1@h
+ e_or2i r3, TLB5_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB5_MAS2@h
+ e_or2i r3, TLB5_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB5_MAS3@h
+ e_or2i r3, TLB5_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+
+ /*
+ * Special function registers clearing, required in order to avoid
+ * possible problems with lockstep mode.
+ */
+ mtcrf 0xFF, r31
+ mtspr 9, r31 /* CTR */
+ mtspr 22, r31 /* DEC */
+ mtspr 26, r31 /* SRR0-1 */
+ mtspr 27, r31
+ mtspr 54, r31 /* DECAR */
+ mtspr 58, r31 /* CSRR0-1 */
+ mtspr 59, r31
+ mtspr 61, r31 /* DEAR */
+ mtspr 256, r31 /* USPRG0 */
+ mtspr 272, r31 /* SPRG1-7 */
+ mtspr 273, r31
+ mtspr 274, r31
+ mtspr 275, r31
+ mtspr 276, r31
+ mtspr 277, r31
+ mtspr 278, r31
+ mtspr 279, r31
+ mtspr 285, r31 /* TBU */
+ mtspr 284, r31 /* TBL */
+#if 0
+ mtspr 318, r31 /* DVC1-2 */
+ mtspr 319, r31
+#endif
+ mtspr 562, r31 /* DBCNT */
+ mtspr 570, r31 /* MCSRR0 */
+ mtspr 571, r31 /* MCSRR1 */
+ mtspr 604, r31 /* SPRG8-9 */
+ mtspr 605, r31
+
+ /*
+ * *Finally* the TLB0 is re-allocated to flash, note, the final phase
+ * is executed from RAM.
+ */
+ e_lis r3, TLB0_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB0_MAS1@h
+ e_or2i r3, TLB0_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB0_MAS2@h
+ e_or2i r3, TLB0_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB0_MAS3@h
+ e_or2i r3, TLB0_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ mflr r4
+ e_lis r6, _ramcode@h
+ e_or2i r6, _ramcode@l
+ e_lis r7, 0x40010000@h
+ mtctr r7
+ se_lwz r3, 0(r6)
+ se_stw r3, 0(r7)
+ se_lwz r3, 4(r6)
+ se_stw r3, 4(r7)
+ se_lwz r3, 8(r6)
+ se_stw r3, 8(r7)
+ se_bctrl
+ mtlr r4
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ /*
+ * Cache invalidated and then enabled.
+ */
+ e_li r3, LICSR1_ICINV
+ mtspr 1011, r3 /* LICSR1 */
+.inv: mfspr r3, 1011 /* LICSR1 */
+ e_and2i. r3, LICSR1_ICINV
+ se_bne .inv
+ e_lis r3, BOOT_LICSR1_DEFAULT@h
+ e_or2i r3, BOOT_LICSR1_DEFAULT@l
+ mtspr 1011, r3 /* LICSR1 */
+
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_or2i r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ /* IVORs initialization.*/
+ e_lis r3, _unhandled_exception@h
+ e_or2i r3, _unhandled_exception@l
+
+ mtspr 400, r3 /* IVOR0-15 */
+ mtspr 401, r3
+ mtspr 402, r3
+ mtspr 403, r3
+ mtspr 404, r3
+ mtspr 405, r3
+ mtspr 406, r3
+ mtspr 407, r3
+ mtspr 408, r3
+ mtspr 409, r3
+ mtspr 410, r3
+ mtspr 411, r3
+ mtspr 412, r3
+ mtspr 413, r3
+ mtspr 414, r3
+ mtspr 415, r3
+ mtspr 528, r3 /* IVOR32-34 */
+ mtspr 529, r3
+ mtspr 530, r3
+
+ se_blr
+
+ .section .handlers, "ax"
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _unhandled_exception
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ se_b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/boot.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/boot.h new file mode 100644 index 0000000..1a5a1e8 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/boot.h @@ -0,0 +1,248 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC56ECxx.
+ * @{
+ */
+
+#ifndef BOOT_H
+#define BOOT_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name MASx registers definitions
+ * @{
+ */
+#define MAS0_TBLMAS_TBL 0x10000000
+#define MAS0_ESEL_MASK 0x000F0000
+#define MAS0_ESEL(n) ((n) << 16)
+
+#define MAS1_VALID 0x80000000
+#define MAS1_IPROT 0x40000000
+#define MAS1_TID_MASK 0x00FF0000
+#define MAS1_TS 0x00001000
+#define MAS1_TSISE_MASK 0x00000F80
+#define MAS1_TSISE_1K 0x00000000
+#define MAS1_TSISE_2K 0x00000080
+#define MAS1_TSISE_4K 0x00000100
+#define MAS1_TSISE_8K 0x00000180
+#define MAS1_TSISE_16K 0x00000200
+#define MAS1_TSISE_32K 0x00000280
+#define MAS1_TSISE_64K 0x00000300
+#define MAS1_TSISE_128K 0x00000380
+#define MAS1_TSISE_256K 0x00000400
+#define MAS1_TSISE_512K 0x00000480
+#define MAS1_TSISE_1M 0x00000500
+#define MAS1_TSISE_2M 0x00000580
+#define MAS1_TSISE_4M 0x00000600
+#define MAS1_TSISE_8M 0x00000680
+#define MAS1_TSISE_16M 0x00000700
+#define MAS1_TSISE_32M 0x00000780
+#define MAS1_TSISE_64M 0x00000800
+#define MAS1_TSISE_128M 0x00000880
+#define MAS1_TSISE_256M 0x00000900
+#define MAS1_TSISE_512M 0x00000980
+#define MAS1_TSISE_1G 0x00000A00
+#define MAS1_TSISE_2G 0x00000A80
+#define MAS1_TSISE_4G 0x00000B00
+
+#define MAS2_EPN_MASK 0xFFFFFC00
+#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
+#define MAS2_EBOOK 0x00000000
+#define MAS2_VLE 0x00000020
+#define MAS2_W 0x00000010
+#define MAS2_I 0x00000008
+#define MAS2_M 0x00000004
+#define MAS2_G 0x00000002
+#define MAS2_E 0x00000001
+
+#define MAS3_RPN_MASK 0xFFFFFC00
+#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
+#define MAS3_U0 0x00000200
+#define MAS3_U1 0x00000100
+#define MAS3_U2 0x00000080
+#define MAS3_U3 0x00000040
+#define MAS3_UX 0x00000020
+#define MAS3_SX 0x00000010
+#define MAS3_UW 0x00000008
+#define MAS3_SW 0x00000004
+#define MAS3_UR 0x00000002
+#define MAS3_SR 0x00000001
+/** @} */
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BPRED_MASK 0x00000006
+#define BUCSR_BPRED_0 0x00000000
+#define BUCSR_BPRED_1 0x00000002
+#define BUCSR_BPRED_2 0x00000004
+#define BUCSR_BPRED_3 0x00000006
+#define BUCSR_BALLOC_MASK 0x00000030
+#define BUCSR_BALLOC_0 0x00000000
+#define BUCSR_BALLOC_1 0x00000010
+#define BUCSR_BALLOC_2 0x00000020
+#define BUCSR_BALLOC_3 0x00000030
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name LICSR1 registers definitions
+ * @{
+ */
+#define LICSR1_ICE 0x00000001
+#define LICSR1_ICINV 0x00000002
+#define LICSR1_ICORG 0x00000010
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_UCLE 0x04000000
+#define MSR_SPE 0x02000000
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_FP 0x00002000
+#define MSR_ME 0x00001000
+#define MSR_FE0 0x00000800
+#define MSR_DE 0x00000200
+#define MSR_FE1 0x00000100
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * TLB default settings.
+ */
+#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
+#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
+#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
+#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
+#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
+#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
+#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
+#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
+#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
+#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
+#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
+#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I)
+#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
+#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
+#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
+ BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * LICSR1 default settings.
+ */
+#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* BOOT_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/boot_cw.s b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/boot_cw.s new file mode 100644 index 0000000..9d69618 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/boot_cw.s @@ -0,0 +1,400 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ECxx/boot.s
+ * @brief SPC56ECxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ .extern _boot_address
+ .extern __ram_start__
+ .extern __ram_end__
+ .extern __ivpr_base__
+
+ .extern _unhandled_exception
+
+ /* BAM record.*/
+ .section .boot, 16
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 4
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ e_bl _coreinit
+#endif
+ e_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 4
+_ramcode:
+ tlbwe
+ se_isync
+ se_blr
+
+ .align 2
+_coreinit:
+ /*
+ * Invalidating all TLBs except TLB0.
+ */
+ e_lis r3, 0
+ mtspr 625, r3 /* MAS1 */
+ mtspr 626, r3 /* MAS2 */
+ mtspr 627, r3 /* MAS3 */
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+
+ /*
+ * TLB1 allocated to internal RAM.
+ */
+ e_lis r3, TLB1_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB1_MAS1@h
+ e_or2i r3, TLB1_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB1_MAS2@h
+ e_or2i r3, TLB1_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB1_MAS3@h
+ e_or2i r3, TLB1_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB2 allocated to internal Peripherals Bridge A.
+ */
+ e_lis r3, TLB2_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB2_MAS1@h
+ e_or2i r3, TLB2_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB2_MAS2@h
+ e_or2i r3, TLB2_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB2_MAS3@h
+ e_or2i r3, TLB2_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB3 allocated to internal Peripherals Bridge B.
+ */
+ e_lis r3, TLB3_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB3_MAS1@h
+ e_or2i r3, TLB3_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB3_MAS2@h
+ e_or2i r3, TLB3_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB3_MAS3@h
+ e_or2i r3, TLB3_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB4 allocated to on-platform peripherals.
+ */
+ e_lis r3, TLB4_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB4_MAS1@h
+ e_or2i r3, TLB4_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB4_MAS2@h
+ e_or2i r3, TLB4_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB4_MAS3@h
+ e_or2i r3, TLB4_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB5 allocated to on-platform peripherals.
+ */
+ e_lis r3, TLB5_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB5_MAS1@h
+ e_or2i r3, TLB5_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB5_MAS2@h
+ e_or2i r3, TLB5_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB5_MAS3@h
+ e_or2i r3, TLB5_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+
+ /*
+ * Special function registers clearing, required in order to avoid
+ * possible problems with lockstep mode.
+ */
+ mtcrf 0xFF, r31
+ mtspr 9, r31 /* CTR */
+ mtspr 22, r31 /* DEC */
+ mtspr 26, r31 /* SRR0-1 */
+ mtspr 27, r31
+ mtspr 54, r31 /* DECAR */
+ mtspr 58, r31 /* CSRR0-1 */
+ mtspr 59, r31
+ mtspr 61, r31 /* DEAR */
+ mtspr 256, r31 /* USPRG0 */
+ mtspr 272, r31 /* SPRG1-7 */
+ mtspr 273, r31
+ mtspr 274, r31
+ mtspr 275, r31
+ mtspr 276, r31
+ mtspr 277, r31
+ mtspr 278, r31
+ mtspr 279, r31
+ mtspr 285, r31 /* TBU */
+ mtspr 284, r31 /* TBL */
+#if 0
+ mtspr 318, r31 /* DVC1-2 */
+ mtspr 319, r31
+#endif
+ mtspr 562, r31 /* DBCNT */
+ mtspr 570, r31 /* MCSRR0 */
+ mtspr 571, r31 /* MCSRR1 */
+ mtspr 604, r31 /* SPRG8-9 */
+ mtspr 605, r31
+
+ /*
+ * *Finally* the TLB0 is re-allocated to flash, note, the final phase
+ * is executed from RAM.
+ */
+ e_lis r3, TLB0_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB0_MAS1@h
+ e_or2i r3, TLB0_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB0_MAS2@h
+ e_or2i r3, TLB0_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB0_MAS3@h
+ e_or2i r3, TLB0_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ se_mflr r4
+ e_lis r6, _ramcode@h
+ e_or2i r6, _ramcode@l
+ e_lis r7, 0x40010000@h
+ mtctr r7
+ se_lwz r3, 0(r6)
+ se_stw r3, 0(r7)
+ se_lwz r3, 4(r6)
+ se_stw r3, 4(r7)
+ se_lwz r3, 8(r6)
+ se_stw r3, 8(r7)
+ se_bctrl
+ mtlr r4
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ /*
+ * Cache invalidated and then enabled.
+ */
+ se_li r3, LICSR1_ICINV
+ mtspr 1011, r3 /* LICSR1 */
+.inv: mfspr r3, 1011 /* LICSR1 */
+ e_andi. r3, r3, LICSR1_ICINV
+ se_bne .inv
+ e_lis r3, BOOT_LICSR1_DEFAULT@h
+ e_or2i r3, BOOT_LICSR1_DEFAULT@l
+ mtspr 1011, r3 /* LICSR1 */
+
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 4
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_ori r3, r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ /* IVORs initialization.*/
+ e_lis r3, _unhandled_exception@h
+ e_or2i r3, _unhandled_exception@l
+
+ mtspr 400, r3 /* IVOR0-15 */
+ mtspr 401, r3
+ mtspr 402, r3
+ mtspr 403, r3
+ mtspr 404, r3
+ mtspr 405, r3
+ mtspr 406, r3
+ mtspr 407, r3
+ mtspr 408, r3
+ mtspr 409, r3
+ mtspr 410, r3
+ mtspr 411, r3
+ mtspr 412, r3
+ mtspr 413, r3
+ mtspr 414, r3
+ mtspr 415, r3
+ mtspr 528, r3 /* IVOR32-34 */
+ mtspr 529, r3
+ mtspr 530, r3
+
+ se_blr
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/boot_ghs.s b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/boot_ghs.s new file mode 100644 index 0000000..0e91386 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/boot_ghs.s @@ -0,0 +1,405 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ECxx/boot_ghs.s
+ * @brief SPC56ECxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ .vle
+
+ /* BAM record.*/
+ .section .boot, "axv"
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ se_bl _coreinit
+#endif
+ se_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_ramcode:
+ tlbwe
+ se_isync
+ se_blr
+
+ .align 2
+_coreinit:
+ /*
+ * Invalidating all TLBs except TLB0.
+ */
+ e_lis r3, 0
+ mtspr 625, r3 /* MAS1 */
+ mtspr 626, r3 /* MAS2 */
+ mtspr 627, r3 /* MAS3 */
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+
+ /*
+ * TLB1 allocated to internal RAM.
+ */
+ e_lis r3, TLB1_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB1_MAS1@h
+ e_or2i r3, TLB1_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB1_MAS2@h
+ e_or2i r3, TLB1_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB1_MAS3@h
+ e_or2i r3, TLB1_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB2 allocated to internal Peripherals Bridge A.
+ */
+ e_lis r3, TLB2_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB2_MAS1@h
+ e_or2i r3, TLB2_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB2_MAS2@h
+ e_or2i r3, TLB2_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB2_MAS3@h
+ e_or2i r3, TLB2_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB3 allocated to internal Peripherals Bridge B.
+ */
+ e_lis r3, TLB3_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB3_MAS1@h
+ e_or2i r3, TLB3_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB3_MAS2@h
+ e_or2i r3, TLB3_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB3_MAS3@h
+ e_or2i r3, TLB3_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB4 allocated to on-platform peripherals.
+ */
+ e_lis r3, TLB4_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB4_MAS1@h
+ e_or2i r3, TLB4_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB4_MAS2@h
+ e_or2i r3, TLB4_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB4_MAS3@h
+ e_or2i r3, TLB4_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB5 allocated to on-platform peripherals.
+ */
+ e_lis r3, TLB5_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB5_MAS1@h
+ e_or2i r3, TLB5_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB5_MAS2@h
+ e_or2i r3, TLB5_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB5_MAS3@h
+ e_or2i r3, TLB5_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+
+ /*
+ * Special function registers clearing, required in order to avoid
+ * possible problems with lockstep mode.
+ */
+ mtcrf 0xFF, r31
+ mtspr 9, r31 /* CTR */
+ mtspr 22, r31 /* DEC */
+ mtspr 26, r31 /* SRR0-1 */
+ mtspr 27, r31
+ mtspr 54, r31 /* DECAR */
+ mtspr 58, r31 /* CSRR0-1 */
+ mtspr 59, r31
+ mtspr 61, r31 /* DEAR */
+ mtspr 256, r31 /* USPRG0 */
+ mtspr 272, r31 /* SPRG1-7 */
+ mtspr 273, r31
+ mtspr 274, r31
+ mtspr 275, r31
+ mtspr 276, r31
+ mtspr 277, r31
+ mtspr 278, r31
+ mtspr 279, r31
+ mtspr 285, r31 /* TBU */
+ mtspr 284, r31 /* TBL */
+#if 0
+ mtspr 318, r31 /* DVC1-2 */
+ mtspr 319, r31
+#endif
+ mtspr 562, r31 /* DBCNT */
+ mtspr 570, r31 /* MCSRR0 */
+ mtspr 571, r31 /* MCSRR1 */
+ mtspr 604, r31 /* SPRG8-9 */
+ mtspr 605, r31
+
+ /*
+ * *Finally* the TLB0 is re-allocated to flash, note, the final phase
+ * is executed from RAM.
+ */
+ e_lis r3, TLB0_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB0_MAS1@h
+ e_or2i r3, TLB0_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB0_MAS2@h
+ e_or2i r3, TLB0_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB0_MAS3@h
+ e_or2i r3, TLB0_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ mflr r4
+ e_lis r6, _ramcode@h
+ e_or2i r6, _ramcode@l
+ e_lis r7, 0x40010000@h
+ mtctr r7
+ se_lwz r3, 0(r6)
+ se_stw r3, 0(r7)
+ se_lwz r3, 4(r6)
+ se_stw r3, 4(r7)
+ se_lwz r3, 8(r6)
+ se_stw r3, 8(r7)
+ se_bctrl
+ mtlr r4
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ /*
+ * Cache invalidated and then enabled.
+ */
+ e_li r3, LICSR1_ICINV
+ mtspr 1011, r3 /* LICSR1 */
+.inv: mfspr r3, 1011 /* LICSR1 */
+ e_and2i. r3, LICSR1_ICINV
+ se_bne .inv
+ e_lis r3, BOOT_LICSR1_DEFAULT@h
+ e_or2i r3, BOOT_LICSR1_DEFAULT@l
+ mtspr 1011, r3 /* LICSR1 */
+
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_or2i r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ /* IVORs initialization.*/
+ e_lis r3, _unhandled_exception@h
+ e_or2i r3, _unhandled_exception@l
+
+ mtspr 400, r3 /* IVOR0-15 */
+ mtspr 401, r3
+ mtspr 402, r3
+ mtspr 403, r3
+ mtspr 404, r3
+ mtspr 405, r3
+ mtspr 406, r3
+ mtspr 407, r3
+ mtspr 408, r3
+ mtspr 409, r3
+ mtspr 410, r3
+ mtspr 411, r3
+ mtspr 412, r3
+ mtspr 413, r3
+ mtspr 414, r3
+ mtspr 415, r3
+ mtspr 528, r3 /* IVOR32-34 */
+ mtspr 529, r3
+ mtspr 530, r3
+
+ se_blr
+
+ .section .handlers, "axv"
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _unhandled_exception
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ se_b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/intc.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/intc.h new file mode 100644 index 0000000..6cbe300 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/intc.h @@ -0,0 +1,95 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ECxx/intc.h
+ * @brief SPC56ECxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef INTC_H
+#define INTC_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+#define INTC_PSR_CORE1 0xC0
+#define INTC_PSR_CORES01 0x40
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* INTC_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/ppcparams.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/ppcparams.h new file mode 100644 index 0000000..8acb128 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ECxx/ppcparams.h @@ -0,0 +1,83 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ECxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC56ECxx.
+ *
+ * @defgroup PPC_SPC56ECxx SPC56ECxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC56ECxx platform.
+ * @{
+ */
+
+#ifndef PPCPARAMS_H
+#define PPCPARAMS_H
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC56ECxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z4
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 16
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS TRUE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE TRUE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER TRUE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 279
+
+#endif /* PPCPARAMS_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ELxx/boot.S b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ELxx/boot.S new file mode 100644 index 0000000..748906f --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ELxx/boot.S @@ -0,0 +1,409 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ELxx/boot.s
+ * @brief SPC56ELxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if defined(__HIGHTEC__)
+#define se_bge bge
+#endif
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+ e_bl _coreinit
+ e_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_ramcode:
+ tlbwe
+ se_isync
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ .align 2
+_coreinit:
+#if BOOT_PERFORM_CORE_INIT
+ /*
+ * Invalidating all TLBs except TLB0.
+ */
+ e_lis r3, 0
+ mtspr 625, r3 /* MAS1 */
+ mtspr 626, r3 /* MAS2 */
+ mtspr 627, r3 /* MAS3 */
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+
+ /*
+ * TLB1 allocated to internal RAM.
+ */
+ e_lis r3, TLB1_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB1_MAS1@h
+ e_or2i r3, TLB1_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB1_MAS2@h
+ e_or2i r3, TLB1_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB1_MAS3@h
+ e_or2i r3, TLB1_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB2 allocated to internal Peripherals Bridge A.
+ */
+ e_lis r3, TLB2_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB2_MAS1@h
+ e_or2i r3, TLB2_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB2_MAS2@h
+ e_or2i r3, TLB2_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB2_MAS3@h
+ e_or2i r3, TLB2_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB3 allocated to internal Peripherals Bridge B.
+ */
+ e_lis r3, TLB3_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB3_MAS1@h
+ e_or2i r3, TLB3_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB3_MAS2@h
+ e_or2i r3, TLB3_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB3_MAS3@h
+ e_or2i r3, TLB3_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB4 allocated to on-platform peripherals.
+ */
+ e_lis r3, TLB4_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB4_MAS1@h
+ e_or2i r3, TLB4_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB4_MAS2@h
+ e_or2i r3, TLB4_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB4_MAS3@h
+ e_or2i r3, TLB4_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB5 allocated to on-platform peripherals.
+ */
+ e_lis r3, TLB5_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB5_MAS1@h
+ e_or2i r3, TLB5_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB5_MAS2@h
+ e_or2i r3, TLB5_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB5_MAS3@h
+ e_or2i r3, TLB5_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Special function registers clearing, required in order to avoid
+ * possible problems with lockstep mode.
+ */
+ mtcrf 0xFF, r31
+ mtspr 9, r31 /* CTR */
+ mtspr 22, r31 /* DEC */
+ mtspr 26, r31 /* SRR0-1 */
+ mtspr 27, r31
+ mtspr 54, r31 /* DECAR */
+ mtspr 58, r31 /* CSRR0-1 */
+ mtspr 59, r31
+ mtspr 61, r31 /* DEAR */
+ mtspr 256, r31 /* USPRG0 */
+ mtspr 272, r31 /* SPRG1-7 */
+ mtspr 273, r31
+ mtspr 274, r31
+ mtspr 275, r31
+ mtspr 276, r31
+ mtspr 277, r31
+ mtspr 278, r31
+ mtspr 279, r31
+ mtspr 285, r31 /* TBU */
+ mtspr 284, r31 /* TBL */
+#if 0
+ mtspr 318, r31 /* DVC1-2 */
+ mtspr 319, r31
+#endif
+ mtspr 562, r31 /* DBCNT */
+ mtspr 570, r31 /* MCSRR0 */
+ mtspr 571, r31 /* MCSRR1 */
+ mtspr 604, r31 /* SPRG8-9 */
+ mtspr 605, r31
+
+#if BOOT_PERFORM_CORE_INIT
+ /*
+ * *Finally* the TLB0 is re-allocated to flash, note, the final phase
+ * is executed from RAM.
+ */
+ e_lis r3, TLB0_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB0_MAS1@h
+ e_or2i r3, TLB0_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB0_MAS2@h
+ e_or2i r3, TLB0_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB0_MAS3@h
+ e_or2i r3, TLB0_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ mflr r4
+ e_lis r6, _ramcode@h
+ e_or2i r6, _ramcode@l
+ e_lis r7, 0x40010000@h
+ mtctr r7
+ se_lwz r3, 0(r6)
+ se_stw r3, 0(r7)
+ se_lwz r3, 4(r6)
+ se_stw r3, 4(r7)
+ se_lwz r3, 8(r6)
+ se_stw r3, 8(r7)
+ se_bctrl
+ mtlr r4
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ /*
+ * Cache invalidated and then enabled.
+ */
+ e_li r3, LICSR1_ICINV
+ mtspr 1011, r3 /* LICSR1 */
+.inv: mfspr r3, 1011 /* LICSR1 */
+ e_and2i. r3, LICSR1_ICINV
+ se_bne .inv
+ e_lis r3, BOOT_LICSR1_DEFAULT@h
+ e_or2i r3, BOOT_LICSR1_DEFAULT@l
+ mtspr 1011, r3 /* LICSR1 */
+
+ se_blr
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_or2i r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ /* IVORs initialization.*/
+ e_lis r3, _unhandled_exception@h
+ e_or2i r3, _unhandled_exception@l
+
+ mtspr 400, r3 /* IVOR0-15 */
+ mtspr 401, r3
+ mtspr 402, r3
+ mtspr 403, r3
+ mtspr 404, r3
+ mtspr 405, r3
+ mtspr 406, r3
+ mtspr 407, r3
+ mtspr 408, r3
+ mtspr 409, r3
+ mtspr 410, r3
+ mtspr 411, r3
+ mtspr 412, r3
+ mtspr 413, r3
+ mtspr 414, r3
+ mtspr 415, r3
+ mtspr 528, r3 /* IVOR32-34 */
+ mtspr 529, r3
+ mtspr 530, r3
+
+ se_blr
+
+ .section .handlers, "ax"
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _unhandled_exception
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ se_b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ELxx/boot.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ELxx/boot.h new file mode 100644 index 0000000..71ae0eb --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ELxx/boot.h @@ -0,0 +1,248 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC56ELxx.
+ * @{
+ */
+
+#ifndef BOOT_H
+#define BOOT_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name MASx registers definitions
+ * @{
+ */
+#define MAS0_TBLMAS_TBL 0x10000000
+#define MAS0_ESEL_MASK 0x000F0000
+#define MAS0_ESEL(n) ((n) << 16)
+
+#define MAS1_VALID 0x80000000
+#define MAS1_IPROT 0x40000000
+#define MAS1_TID_MASK 0x00FF0000
+#define MAS1_TS 0x00001000
+#define MAS1_TSISE_MASK 0x00000F80
+#define MAS1_TSISE_1K 0x00000000
+#define MAS1_TSISE_2K 0x00000080
+#define MAS1_TSISE_4K 0x00000100
+#define MAS1_TSISE_8K 0x00000180
+#define MAS1_TSISE_16K 0x00000200
+#define MAS1_TSISE_32K 0x00000280
+#define MAS1_TSISE_64K 0x00000300
+#define MAS1_TSISE_128K 0x00000380
+#define MAS1_TSISE_256K 0x00000400
+#define MAS1_TSISE_512K 0x00000480
+#define MAS1_TSISE_1M 0x00000500
+#define MAS1_TSISE_2M 0x00000580
+#define MAS1_TSISE_4M 0x00000600
+#define MAS1_TSISE_8M 0x00000680
+#define MAS1_TSISE_16M 0x00000700
+#define MAS1_TSISE_32M 0x00000780
+#define MAS1_TSISE_64M 0x00000800
+#define MAS1_TSISE_128M 0x00000880
+#define MAS1_TSISE_256M 0x00000900
+#define MAS1_TSISE_512M 0x00000980
+#define MAS1_TSISE_1G 0x00000A00
+#define MAS1_TSISE_2G 0x00000A80
+#define MAS1_TSISE_4G 0x00000B00
+
+#define MAS2_EPN_MASK 0xFFFFFC00
+#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
+#define MAS2_EBOOK 0x00000000
+#define MAS2_VLE 0x00000020
+#define MAS2_W 0x00000010
+#define MAS2_I 0x00000008
+#define MAS2_M 0x00000004
+#define MAS2_G 0x00000002
+#define MAS2_E 0x00000001
+
+#define MAS3_RPN_MASK 0xFFFFFC00
+#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
+#define MAS3_U0 0x00000200
+#define MAS3_U1 0x00000100
+#define MAS3_U2 0x00000080
+#define MAS3_U3 0x00000040
+#define MAS3_UX 0x00000020
+#define MAS3_SX 0x00000010
+#define MAS3_UW 0x00000008
+#define MAS3_SW 0x00000004
+#define MAS3_UR 0x00000002
+#define MAS3_SR 0x00000001
+/** @} */
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BPRED_MASK 0x00000006
+#define BUCSR_BPRED_0 0x00000000
+#define BUCSR_BPRED_1 0x00000002
+#define BUCSR_BPRED_2 0x00000004
+#define BUCSR_BPRED_3 0x00000006
+#define BUCSR_BALLOC_MASK 0x00000030
+#define BUCSR_BALLOC_0 0x00000000
+#define BUCSR_BALLOC_1 0x00000010
+#define BUCSR_BALLOC_2 0x00000020
+#define BUCSR_BALLOC_3 0x00000030
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name LICSR1 registers definitions
+ * @{
+ */
+#define LICSR1_ICE 0x00000001
+#define LICSR1_ICINV 0x00000002
+#define LICSR1_ICORG 0x00000010
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_UCLE 0x04000000
+#define MSR_SPE 0x02000000
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_FP 0x00002000
+#define MSR_ME 0x00001000
+#define MSR_FE0 0x00000800
+#define MSR_DE 0x00000200
+#define MSR_FE1 0x00000100
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * TLB default settings.
+ */
+#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
+#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M)
+#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
+#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
+#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
+#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
+#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
+#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
+#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
+#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
+#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
+#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I)
+#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
+#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
+#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
+ BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * LICSR1 default settings.
+ */
+#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* BOOT_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ELxx/intc.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ELxx/intc.h new file mode 100644 index 0000000..6900b6c --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ELxx/intc.h @@ -0,0 +1,93 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ELxx/intc.h
+ * @brief SPC56ELxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef INTC_H
+#define INTC_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* INTC_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h new file mode 100644 index 0000000..11363a4 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h @@ -0,0 +1,83 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ELxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC56ELxx.
+ *
+ * @defgroup PPC_SPC56ELxx SPC56ELxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC56ELxx platform.
+ * @{
+ */
+
+#ifndef PPCPARAMS_H
+#define PPCPARAMS_H
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC56ELxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z4
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 16
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS TRUE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE TRUE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER TRUE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 256
+
+#endif /* PPCPARAMS_H */
+
+/** @} */
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