diff options
Diffstat (limited to 'ChibiOS_20.3.2/os/hal')
77 files changed, 37245 insertions, 1473 deletions
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/board.c b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/board.c new file mode 100644 index 0000000..2868726 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/board.c @@ -0,0 +1,266 @@ +/*
+ ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ gpio_setup_t PKData;
+#endif
+} gpio_config_t;
+
+/**
+ * @brief STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
+#endif
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetAHB4(STM32_GPIO_EN_MASK);
+ rccEnableAHB4(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+ gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+ gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
+ */
+void __early_init(void) {
+
+ stm32_gpio_init();
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @note You can add your board-specific code here.
+ */
+void boardInit(void) {
+
+}
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/board.h b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/board.h new file mode 100644 index 0000000..aea5c80 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/board.h @@ -0,0 +1,1642 @@ +/*
+ ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * Setup for STMicroelectronics STM32 Nucleo144-H743ZI board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_NUCLEO144_H743ZI
+#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-H743ZI"
+
+/*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID MII_LAN8742A_ID
+#define BOARD_PHY_RMII
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768U
+#endif
+
+#define STM32_LSEDRV (3U << 3U)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000U
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32H743xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_PIN0 0U
+#define GPIOA_RMII_REF_CLK 1U
+#define GPIOA_RMII_MDIO 2U
+#define GPIOA_PIN3 3U
+#define GPIOA_PIN4 4U
+#define GPIOA_PIN5 5U
+#define GPIOA_PIN6 6U
+#define GPIOA_RMII_CRS_DV 7U
+#define GPIOA_USB_SOF 8U
+#define GPIOA_MCO1 8U
+#define GPIOA_USB_VBUS 9U
+#define GPIOA_USB_ID 10U
+#define GPIOA_USB_DM 11U
+#define GPIOA_USB_DP 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_T_JTDI 15U
+
+#define GPIOB_LED1 0U
+#define GPIOB_LED_GREEN 0U
+#define GPIOB_LED 0U
+#define GPIOB_PIN1 1U
+#define GPIOB_PIN2 2U
+#define GPIOB_SWO 3U
+#define GPIOB_PIN4 4U
+#define GPIOB_PIN5 5U
+#define GPIOB_PIN6 6U
+#define GPIOB_LED2 7U
+#define GPIOB_LED_BLUE 7U
+#define GPIOB_PIN8 8U
+#define GPIOB_PIN9 9U
+#define GPIOB_PIN10 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_PIN12 12U
+#define GPIOB_RMII_TXD1 13U
+#define GPIOB_LED3 14U
+#define GPIOB_LED_RED 14U
+#define GPIOB_PIN15 15U
+
+#define GPIOC_PIN0 0U
+#define GPIOC_RMII_MDC 1U
+#define GPIOC_PIN2 2U
+#define GPIOC_PIN3 3U
+#define GPIOC_RMII_RXD0 4U
+#define GPIOC_RMII_RXD1 5U
+#define GPIOC_PIN6 6U
+#define GPIOC_PIN7 7U
+#define GPIOC_PIN8 8U
+#define GPIOC_PIN9 9U
+#define GPIOC_PIN10 10U
+#define GPIOC_PIN11 11U
+#define GPIOC_PIN12 12U
+#define GPIOC_BUTTON 13U
+#define GPIOC_OSC32_IN 14U
+#define GPIOC_OSC32_OUT 15U
+
+#define GPIOD_PIN0 0U
+#define GPIOD_PIN1 1U
+#define GPIOD_PIN2 2U
+#define GPIOD_PIN3 3U
+#define GPIOD_PIN4 4U
+#define GPIOD_PIN5 5U
+#define GPIOD_PIN6 6U
+#define GPIOD_PIN7 7U
+#define GPIOD_USART3_RX 8U
+#define GPIOD_STLK_RX 8U
+#define GPIOD_USART3_TX 9U
+#define GPIOD_STLK_TX 9U
+#define GPIOD_PIN10 10U
+#define GPIOD_PIN11 11U
+#define GPIOD_PIN12 12U
+#define GPIOD_PIN13 13U
+#define GPIOD_PIN14 14U
+#define GPIOD_PIN15 15U
+
+#define GPIOE_PIN0 0U
+#define GPIOE_PIN1 1U
+#define GPIOE_PIN2 2U
+#define GPIOE_PIN3 3U
+#define GPIOE_PIN4 4U
+#define GPIOE_PIN5 5U
+#define GPIOE_PIN6 6U
+#define GPIOE_PIN7 7U
+#define GPIOE_PIN8 8U
+#define GPIOE_PIN9 9U
+#define GPIOE_PIN10 10U
+#define GPIOE_PIN11 11U
+#define GPIOE_PIN12 12U
+#define GPIOE_PIN13 13U
+#define GPIOE_PIN14 14U
+#define GPIOE_PIN15 15U
+
+#define GPIOF_PIN0 0U
+#define GPIOF_PIN1 1U
+#define GPIOF_PIN2 2U
+#define GPIOF_PIN3 3U
+#define GPIOF_PIN4 4U
+#define GPIOF_PIN5 5U
+#define GPIOF_PIN6 6U
+#define GPIOF_PIN7 7U
+#define GPIOF_PIN8 8U
+#define GPIOF_PIN9 9U
+#define GPIOF_PIN10 10U
+#define GPIOF_PIN11 11U
+#define GPIOF_PIN12 12U
+#define GPIOF_PIN13 13U
+#define GPIOF_PIN14 14U
+#define GPIOF_PIN15 15U
+
+#define GPIOG_PIN0 0U
+#define GPIOG_PIN1 1U
+#define GPIOG_PIN2 2U
+#define GPIOG_PIN3 3U
+#define GPIOG_PIN4 4U
+#define GPIOG_PIN5 5U
+#define GPIOG_USB_FS_PWR_EN 6U
+#define GPIOG_USB_FS_OVCR 7U
+#define GPIOG_PIN8 8U
+#define GPIOG_PIN9 9U
+#define GPIOG_PIN10 10U
+#define GPIOG_RMII_TX_EN 11U
+#define GPIOG_PIN12 12U
+#define GPIOG_RMII_TXD0 13U
+#define GPIOG_PIN14 14U
+#define GPIOG_PIN15 15U
+
+#define GPIOH_OSC_IN 0U
+#define GPIOH_OSC_OUT 1U
+#define GPIOH_PIN2 2U
+#define GPIOH_PIN3 3U
+#define GPIOH_PIN4 4U
+#define GPIOH_PIN5 5U
+#define GPIOH_PIN6 6U
+#define GPIOH_PIN7 7U
+#define GPIOH_PIN8 8U
+#define GPIOH_PIN9 9U
+#define GPIOH_PIN10 10U
+#define GPIOH_PIN11 11U
+#define GPIOH_PIN12 12U
+#define GPIOH_PIN13 13U
+#define GPIOH_PIN14 14U
+#define GPIOH_PIN15 15U
+
+#define GPIOI_PIN0 0U
+#define GPIOI_PIN1 1U
+#define GPIOI_PIN2 2U
+#define GPIOI_PIN3 3U
+#define GPIOI_PIN4 4U
+#define GPIOI_PIN5 5U
+#define GPIOI_PIN6 6U
+#define GPIOI_PIN7 7U
+#define GPIOI_PIN8 8U
+#define GPIOI_PIN9 9U
+#define GPIOI_PIN10 10U
+#define GPIOI_PIN11 11U
+#define GPIOI_PIN12 12U
+#define GPIOI_PIN13 13U
+#define GPIOI_PIN14 14U
+#define GPIOI_PIN15 15U
+
+#define GPIOJ_PIN0 0U
+#define GPIOJ_PIN1 1U
+#define GPIOJ_PIN2 2U
+#define GPIOJ_PIN3 3U
+#define GPIOJ_PIN4 4U
+#define GPIOJ_PIN5 5U
+#define GPIOJ_PIN6 6U
+#define GPIOJ_PIN7 7U
+#define GPIOJ_PIN8 8U
+#define GPIOJ_PIN9 9U
+#define GPIOJ_PIN10 10U
+#define GPIOJ_PIN11 11U
+#define GPIOJ_PIN12 12U
+#define GPIOJ_PIN13 13U
+#define GPIOJ_PIN14 14U
+#define GPIOJ_PIN15 15U
+
+#define GPIOK_PIN0 0U
+#define GPIOK_PIN1 1U
+#define GPIOK_PIN2 2U
+#define GPIOK_PIN3 3U
+#define GPIOK_PIN4 4U
+#define GPIOK_PIN5 5U
+#define GPIOK_PIN6 6U
+#define GPIOK_PIN7 7U
+#define GPIOK_PIN8 8U
+#define GPIOK_PIN9 9U
+#define GPIOK_PIN10 10U
+#define GPIOK_PIN11 11U
+#define GPIOK_PIN12 12U
+#define GPIOK_PIN13 13U
+#define GPIOK_PIN14 14U
+#define GPIOK_PIN15 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_RMII_REF_CLK PAL_LINE(GPIOA, 1U)
+#define LINE_RMII_MDIO PAL_LINE(GPIOA, 2U)
+#define LINE_RMII_CRS_DV PAL_LINE(GPIOA, 7U)
+#define LINE_USB_SOF PAL_LINE(GPIOA, 8U)
+#define LINE_MCO1 PAL_LINE(GPIOA, 8U)
+#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U)
+#define LINE_USB_ID PAL_LINE(GPIOA, 10U)
+#define LINE_USB_DM PAL_LINE(GPIOA, 11U)
+#define LINE_USB_DP PAL_LINE(GPIOA, 12U)
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
+#define LINE_T_JTDI PAL_LINE(GPIOA, 15U)
+#define LINE_LED1 PAL_LINE(GPIOB, 0U)
+#define LINE_LED_GREEN PAL_LINE(GPIOB, 0U)
+#define LINE_LED PAL_LINE(GPIOB, 0U)
+#define LINE_SWO PAL_LINE(GPIOB, 3U)
+#define LINE_LED2 PAL_LINE(GPIOB, 7U)
+#define LINE_LED_BLUE PAL_LINE(GPIOB, 7U)
+#define LINE_RMII_TXD1 PAL_LINE(GPIOB, 13U)
+#define LINE_LED3 PAL_LINE(GPIOB, 14U)
+#define LINE_LED_RED PAL_LINE(GPIOB, 14U)
+#define LINE_RMII_MDC PAL_LINE(GPIOC, 1U)
+#define LINE_RMII_RXD0 PAL_LINE(GPIOC, 4U)
+#define LINE_RMII_RXD1 PAL_LINE(GPIOC, 5U)
+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
+#define LINE_USART3_RX PAL_LINE(GPIOD, 8U)
+#define LINE_STLK_RX PAL_LINE(GPIOD, 8U)
+#define LINE_USART3_TX PAL_LINE(GPIOD, 9U)
+#define LINE_STLK_TX PAL_LINE(GPIOD, 9U)
+#define LINE_USB_FS_PWR_EN PAL_LINE(GPIOG, 6U)
+#define LINE_USB_FS_OVCR PAL_LINE(GPIOG, 7U)
+#define LINE_RMII_TX_EN PAL_LINE(GPIOG, 11U)
+#define LINE_RMII_TXD0 PAL_LINE(GPIOG, 13U)
+#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
+#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - PIN0 (input pullup).
+ * PA1 - RMII_REF_CLK (alternate 11).
+ * PA2 - RMII_MDIO (alternate 11).
+ * PA3 - PIN3 (input pullup).
+ * PA4 - PIN4 (input pullup).
+ * PA5 - PIN5 (input pullup).
+ * PA6 - PIN6 (input pullup).
+ * PA7 - RMII_CRS_DV (alternate 11).
+ * PA8 - USB_SOF MCO1 (alternate 10).
+ * PA9 - USB_VBUS (analog).
+ * PA10 - USB_ID (alternate 10).
+ * PA11 - USB_DM (alternate 10).
+ * PA12 - USB_DP (alternate 10).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - T_JTDI (alternate 0).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \
+ PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\
+ PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \
+ PIN_MODE_INPUT(GPIOA_PIN3) | \
+ PIN_MODE_INPUT(GPIOA_PIN4) | \
+ PIN_MODE_INPUT(GPIOA_PIN5) | \
+ PIN_MODE_INPUT(GPIOA_PIN6) | \
+ PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) |\
+ PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \
+ PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_ALTERNATE(GPIOA_T_JTDI))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_T_JTDI))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \
+ PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOA_RMII_CRS_DV) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_ID) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_DM) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_DP) | \
+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
+ PIN_OSPEED_HIGH(GPIOA_T_JTDI))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\
+ PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOA_RMII_CRS_DV) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \
+ PIN_PUPDR_PULLUP(GPIOA_T_JTDI))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \
+ PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \
+ PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \
+ PIN_ODR_HIGH(GPIOA_PIN3) | \
+ PIN_ODR_HIGH(GPIOA_PIN4) | \
+ PIN_ODR_HIGH(GPIOA_PIN5) | \
+ PIN_ODR_HIGH(GPIOA_PIN6) | \
+ PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) | \
+ PIN_ODR_HIGH(GPIOA_USB_SOF) | \
+ PIN_ODR_HIGH(GPIOA_USB_VBUS) | \
+ PIN_ODR_HIGH(GPIOA_USB_ID) | \
+ PIN_ODR_HIGH(GPIOA_USB_DM) | \
+ PIN_ODR_HIGH(GPIOA_USB_DP) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_T_JTDI))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \
+ PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) | \
+ PIN_AFIO_AF(GPIOA_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11U))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \
+ PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \
+ PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \
+ PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \
+ PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
+ PIN_AFIO_AF(GPIOA_T_JTDI, 0U))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - LED1 LED_GREEN LED (output pushpull maximum).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - SWO (alternate 0).
+ * PB4 - PIN4 (input pullup).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - PIN6 (input pullup).
+ * PB7 - LED2 LED_BLUE (output pushpull maximum).
+ * PB8 - PIN8 (input pullup).
+ * PB9 - PIN9 (input pullup).
+ * PB10 - PIN10 (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - RMII_TXD1 (alternate 11).
+ * PB14 - LED3 LED_RED (output pushpull maximum).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_LED1) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \
+ PIN_MODE_INPUT(GPIOB_PIN4) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_INPUT(GPIOB_PIN6) | \
+ PIN_MODE_OUTPUT(GPIOB_LED2) | \
+ PIN_MODE_INPUT(GPIOB_PIN8) | \
+ PIN_MODE_INPUT(GPIOB_PIN9) | \
+ PIN_MODE_INPUT(GPIOB_PIN10) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOB_RMII_TXD1) | \
+ PIN_MODE_OUTPUT(GPIOB_LED3) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_LED1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_LED2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_RMII_TXD1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_LED1) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOB_SWO) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOB_LED2) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOB_RMII_TXD1) | \
+ PIN_OSPEED_HIGH(GPIOB_LED3) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_LED1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOB_SWO) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOB_LED2) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_RMII_TXD1) | \
+ PIN_PUPDR_FLOATING(GPIOB_LED3) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_LED1) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_SWO) | \
+ PIN_ODR_HIGH(GPIOB_PIN4) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_PIN6) | \
+ PIN_ODR_LOW(GPIOB_LED2) | \
+ PIN_ODR_HIGH(GPIOB_PIN8) | \
+ PIN_ODR_HIGH(GPIOB_PIN9) | \
+ PIN_ODR_HIGH(GPIOB_PIN10) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_RMII_TXD1) | \
+ PIN_ODR_LOW(GPIOB_LED3) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_LED1, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOB_SWO, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOB_LED2, 0U))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOB_RMII_TXD1, 11U) | \
+ PIN_AFIO_AF(GPIOB_LED3, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0U))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - PIN0 (input pullup).
+ * PC1 - RMII_MDC (alternate 11).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PIN3 (input pullup).
+ * PC4 - RMII_RXD0 (alternate 11).
+ * PC5 - RMII_RXD1 (alternate 11).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - PIN7 (input pullup).
+ * PC8 - PIN8 (input pullup).
+ * PC9 - PIN9 (input pullup).
+ * PC10 - PIN10 (input pullup).
+ * PC11 - PIN11 (input pullup).
+ * PC12 - PIN12 (input pullup).
+ * PC13 - BUTTON (input floating).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
+ PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PIN3) | \
+ PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \
+ PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_INPUT(GPIOC_PIN7) | \
+ PIN_MODE_INPUT(GPIOC_PIN8) | \
+ PIN_MODE_INPUT(GPIOC_PIN9) | \
+ PIN_MODE_INPUT(GPIOC_PIN10) | \
+ PIN_MODE_INPUT(GPIOC_PIN11) | \
+ PIN_MODE_INPUT(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \
+ PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOC_BUTTON) | \
+ PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \
+ PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
+ PIN_ODR_HIGH(GPIOC_RMII_MDC) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PIN3) | \
+ PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \
+ PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_PIN7) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_PIN10) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_PIN12) | \
+ PIN_ODR_HIGH(GPIOC_BUTTON) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) | \
+ PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN7, 0U))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - PIN4 (input pullup).
+ * PD5 - PIN5 (input pullup).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - USART3_RX STLK_RX (alternate 7).
+ * PD9 - USART3_TX STLK_TX (alternate 7).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_INPUT(GPIOD_PIN4) | \
+ PIN_MODE_INPUT(GPIOD_PIN5) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \
+ PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \
+ PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_USART3_RX) | \
+ PIN_ODR_HIGH(GPIOD_USART3_TX) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \
+ PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (input pullup).
+ * PE1 - PIN1 (input pullup).
+ * PE2 - PIN2 (input pullup).
+ * PE3 - PIN3 (input pullup).
+ * PE4 - PIN4 (input pullup).
+ * PE5 - PIN5 (input pullup).
+ * PE6 - PIN6 (input pullup).
+ * PE7 - PIN7 (input pullup).
+ * PE8 - PIN8 (input pullup).
+ * PE9 - PIN9 (input pullup).
+ * PE10 - PIN10 (input pullup).
+ * PE11 - PIN11 (input pullup).
+ * PE12 - PIN12 (input pullup).
+ * PE13 - PIN13 (input pullup).
+ * PE14 - PIN14 (input pullup).
+ * PE15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
+ PIN_MODE_INPUT(GPIOE_PIN1) | \
+ PIN_MODE_INPUT(GPIOE_PIN2) | \
+ PIN_MODE_INPUT(GPIOE_PIN3) | \
+ PIN_MODE_INPUT(GPIOE_PIN4) | \
+ PIN_MODE_INPUT(GPIOE_PIN5) | \
+ PIN_MODE_INPUT(GPIOE_PIN6) | \
+ PIN_MODE_INPUT(GPIOE_PIN7) | \
+ PIN_MODE_INPUT(GPIOE_PIN8) | \
+ PIN_MODE_INPUT(GPIOE_PIN9) | \
+ PIN_MODE_INPUT(GPIOE_PIN10) | \
+ PIN_MODE_INPUT(GPIOE_PIN11) | \
+ PIN_MODE_INPUT(GPIOE_PIN12) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PIN14) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
+ PIN_ODR_HIGH(GPIOE_PIN1) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_PIN3) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0U))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0U))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - PIN0 (input pullup).
+ * PF1 - PIN1 (input pullup).
+ * PF2 - PIN2 (input pullup).
+ * PF3 - PIN3 (input pullup).
+ * PF4 - PIN4 (input pullup).
+ * PF5 - PIN5 (input pullup).
+ * PF6 - PIN6 (input pullup).
+ * PF7 - PIN7 (input pullup).
+ * PF8 - PIN8 (input pullup).
+ * PF9 - PIN9 (input pullup).
+ * PF10 - PIN10 (input pullup).
+ * PF11 - PIN11 (input pullup).
+ * PF12 - PIN12 (input pullup).
+ * PF13 - PIN13 (input pullup).
+ * PF14 - PIN14 (input pullup).
+ * PF15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
+ PIN_MODE_INPUT(GPIOF_PIN1) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0U))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0U))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (input pullup).
+ * PG1 - PIN1 (input pullup).
+ * PG2 - PIN2 (input pullup).
+ * PG3 - PIN3 (input pullup).
+ * PG4 - PIN4 (input pullup).
+ * PG5 - PIN5 (input pullup).
+ * PG6 - USB_FS_PWR_EN (output pushpull minimum).
+ * PG7 - USB_FS_OVCR (input floating).
+ * PG8 - PIN8 (input pullup).
+ * PG9 - PIN9 (input pullup).
+ * PG10 - PIN10 (input pullup).
+ * PG11 - RMII_TX_EN (alternate 11).
+ * PG12 - PIN12 (input pullup).
+ * PG13 - RMII_TXD0 (alternate 11).
+ * PG14 - PIN14 (input pullup).
+ * PG15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \
+ PIN_MODE_INPUT(GPIOG_PIN1) | \
+ PIN_MODE_INPUT(GPIOG_PIN2) | \
+ PIN_MODE_INPUT(GPIOG_PIN3) | \
+ PIN_MODE_INPUT(GPIOG_PIN4) | \
+ PIN_MODE_INPUT(GPIOG_PIN5) | \
+ PIN_MODE_OUTPUT(GPIOG_USB_FS_PWR_EN) | \
+ PIN_MODE_INPUT(GPIOG_USB_FS_OVCR) | \
+ PIN_MODE_INPUT(GPIOG_PIN8) | \
+ PIN_MODE_INPUT(GPIOG_PIN9) | \
+ PIN_MODE_INPUT(GPIOG_PIN10) | \
+ PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \
+ PIN_MODE_INPUT(GPIOG_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \
+ PIN_MODE_INPUT(GPIOG_PIN14) | \
+ PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_USB_FS_PWR_EN) |\
+ PIN_OTYPE_PUSHPULL(GPIOG_USB_FS_OVCR) |\
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOG_USB_FS_PWR_EN) |\
+ PIN_OSPEED_VERYLOW(GPIOG_USB_FS_OVCR) |\
+ PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOG_USB_FS_PWR_EN) |\
+ PIN_PUPDR_FLOATING(GPIOG_USB_FS_OVCR) |\
+ PIN_PUPDR_PULLUP(GPIOG_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
+ PIN_ODR_HIGH(GPIOG_PIN1) | \
+ PIN_ODR_HIGH(GPIOG_PIN2) | \
+ PIN_ODR_HIGH(GPIOG_PIN3) | \
+ PIN_ODR_HIGH(GPIOG_PIN4) | \
+ PIN_ODR_HIGH(GPIOG_PIN5) | \
+ PIN_ODR_LOW(GPIOG_USB_FS_PWR_EN) | \
+ PIN_ODR_HIGH(GPIOG_USB_FS_OVCR) | \
+ PIN_ODR_HIGH(GPIOG_PIN8) | \
+ PIN_ODR_HIGH(GPIOG_PIN9) | \
+ PIN_ODR_HIGH(GPIOG_PIN10) | \
+ PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \
+ PIN_ODR_HIGH(GPIOG_PIN12) | \
+ PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \
+ PIN_ODR_HIGH(GPIOG_PIN14) | \
+ PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOG_USB_FS_PWR_EN, 0U) | \
+ PIN_AFIO_AF(GPIOG_USB_FS_OVCR, 0U))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) | \
+ PIN_AFIO_AF(GPIOG_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0U))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input pullup).
+ * PH3 - PIN3 (input pullup).
+ * PH4 - PIN4 (input pullup).
+ * PH5 - PIN5 (input pullup).
+ * PH6 - PIN6 (input pullup).
+ * PH7 - PIN7 (input pullup).
+ * PH8 - PIN8 (input pullup).
+ * PH9 - PIN9 (input pullup).
+ * PH10 - PIN10 (input pullup).
+ * PH11 - PIN11 (input pullup).
+ * PH12 - PIN12 (input pullup).
+ * PH13 - PIN13 (input pullup).
+ * PH14 - PIN14 (input pullup).
+ * PH15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \
+ PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0U))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0U))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0 - PIN0 (input pullup).
+ * PI1 - PIN1 (input pullup).
+ * PI2 - PIN2 (input pullup).
+ * PI3 - PIN3 (input pullup).
+ * PI4 - PIN4 (input pullup).
+ * PI5 - PIN5 (input pullup).
+ * PI6 - PIN6 (input pullup).
+ * PI7 - PIN7 (input pullup).
+ * PI8 - PIN8 (input pullup).
+ * PI9 - PIN9 (input pullup).
+ * PI10 - PIN10 (input pullup).
+ * PI11 - PIN11 (input pullup).
+ * PI12 - PIN12 (input pullup).
+ * PI13 - PIN13 (input pullup).
+ * PI14 - PIN14 (input pullup).
+ * PI15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
+ PIN_MODE_INPUT(GPIOI_PIN1) | \
+ PIN_MODE_INPUT(GPIOI_PIN2) | \
+ PIN_MODE_INPUT(GPIOI_PIN3) | \
+ PIN_MODE_INPUT(GPIOI_PIN4) | \
+ PIN_MODE_INPUT(GPIOI_PIN5) | \
+ PIN_MODE_INPUT(GPIOI_PIN6) | \
+ PIN_MODE_INPUT(GPIOI_PIN7) | \
+ PIN_MODE_INPUT(GPIOI_PIN8) | \
+ PIN_MODE_INPUT(GPIOI_PIN9) | \
+ PIN_MODE_INPUT(GPIOI_PIN10) | \
+ PIN_MODE_INPUT(GPIOI_PIN11) | \
+ PIN_MODE_INPUT(GPIOI_PIN12) | \
+ PIN_MODE_INPUT(GPIOI_PIN13) | \
+ PIN_MODE_INPUT(GPIOI_PIN14) | \
+ PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN15))
+#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
+ PIN_ODR_HIGH(GPIOI_PIN1) | \
+ PIN_ODR_HIGH(GPIOI_PIN2) | \
+ PIN_ODR_HIGH(GPIOI_PIN3) | \
+ PIN_ODR_HIGH(GPIOI_PIN4) | \
+ PIN_ODR_HIGH(GPIOI_PIN5) | \
+ PIN_ODR_HIGH(GPIOI_PIN6) | \
+ PIN_ODR_HIGH(GPIOI_PIN7) | \
+ PIN_ODR_HIGH(GPIOI_PIN8) | \
+ PIN_ODR_HIGH(GPIOI_PIN9) | \
+ PIN_ODR_HIGH(GPIOI_PIN10) | \
+ PIN_ODR_HIGH(GPIOI_PIN11) | \
+ PIN_ODR_HIGH(GPIOI_PIN12) | \
+ PIN_ODR_HIGH(GPIOI_PIN13) | \
+ PIN_ODR_HIGH(GPIOI_PIN14) | \
+ PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN7, 0U))
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN15, 0U))
+
+/*
+ * GPIOJ setup:
+ *
+ * PJ0 - PIN0 (input pullup).
+ * PJ1 - PIN1 (input pullup).
+ * PJ2 - PIN2 (input pullup).
+ * PJ3 - PIN3 (input pullup).
+ * PJ4 - PIN4 (input pullup).
+ * PJ5 - PIN5 (input pullup).
+ * PJ6 - PIN6 (input pullup).
+ * PJ7 - PIN7 (input pullup).
+ * PJ8 - PIN8 (input pullup).
+ * PJ9 - PIN9 (input pullup).
+ * PJ10 - PIN10 (input pullup).
+ * PJ11 - PIN11 (input pullup).
+ * PJ12 - PIN12 (input pullup).
+ * PJ13 - PIN13 (input pullup).
+ * PJ14 - PIN14 (input pullup).
+ * PJ15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \
+ PIN_MODE_INPUT(GPIOJ_PIN1) | \
+ PIN_MODE_INPUT(GPIOJ_PIN2) | \
+ PIN_MODE_INPUT(GPIOJ_PIN3) | \
+ PIN_MODE_INPUT(GPIOJ_PIN4) | \
+ PIN_MODE_INPUT(GPIOJ_PIN5) | \
+ PIN_MODE_INPUT(GPIOJ_PIN6) | \
+ PIN_MODE_INPUT(GPIOJ_PIN7) | \
+ PIN_MODE_INPUT(GPIOJ_PIN8) | \
+ PIN_MODE_INPUT(GPIOJ_PIN9) | \
+ PIN_MODE_INPUT(GPIOJ_PIN10) | \
+ PIN_MODE_INPUT(GPIOJ_PIN11) | \
+ PIN_MODE_INPUT(GPIOJ_PIN12) | \
+ PIN_MODE_INPUT(GPIOJ_PIN13) | \
+ PIN_MODE_INPUT(GPIOJ_PIN14) | \
+ PIN_MODE_INPUT(GPIOJ_PIN15))
+#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN15))
+#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN15))
+#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLUP(GPIOJ_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN15))
+#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \
+ PIN_ODR_HIGH(GPIOJ_PIN1) | \
+ PIN_ODR_HIGH(GPIOJ_PIN2) | \
+ PIN_ODR_HIGH(GPIOJ_PIN3) | \
+ PIN_ODR_HIGH(GPIOJ_PIN4) | \
+ PIN_ODR_HIGH(GPIOJ_PIN5) | \
+ PIN_ODR_HIGH(GPIOJ_PIN6) | \
+ PIN_ODR_HIGH(GPIOJ_PIN7) | \
+ PIN_ODR_HIGH(GPIOJ_PIN8) | \
+ PIN_ODR_HIGH(GPIOJ_PIN9) | \
+ PIN_ODR_HIGH(GPIOJ_PIN10) | \
+ PIN_ODR_HIGH(GPIOJ_PIN11) | \
+ PIN_ODR_HIGH(GPIOJ_PIN12) | \
+ PIN_ODR_HIGH(GPIOJ_PIN13) | \
+ PIN_ODR_HIGH(GPIOJ_PIN14) | \
+ PIN_ODR_HIGH(GPIOJ_PIN15))
+#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN7, 0U))
+#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN15, 0U))
+
+/*
+ * GPIOK setup:
+ *
+ * PK0 - PIN0 (input pullup).
+ * PK1 - PIN1 (input pullup).
+ * PK2 - PIN2 (input pullup).
+ * PK3 - PIN3 (input pullup).
+ * PK4 - PIN4 (input pullup).
+ * PK5 - PIN5 (input pullup).
+ * PK6 - PIN6 (input pullup).
+ * PK7 - PIN7 (input pullup).
+ * PK8 - PIN8 (input pullup).
+ * PK9 - PIN9 (input pullup).
+ * PK10 - PIN10 (input pullup).
+ * PK11 - PIN11 (input pullup).
+ * PK12 - PIN12 (input pullup).
+ * PK13 - PIN13 (input pullup).
+ * PK14 - PIN14 (input pullup).
+ * PK15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \
+ PIN_MODE_INPUT(GPIOK_PIN1) | \
+ PIN_MODE_INPUT(GPIOK_PIN2) | \
+ PIN_MODE_INPUT(GPIOK_PIN3) | \
+ PIN_MODE_INPUT(GPIOK_PIN4) | \
+ PIN_MODE_INPUT(GPIOK_PIN5) | \
+ PIN_MODE_INPUT(GPIOK_PIN6) | \
+ PIN_MODE_INPUT(GPIOK_PIN7) | \
+ PIN_MODE_INPUT(GPIOK_PIN8) | \
+ PIN_MODE_INPUT(GPIOK_PIN9) | \
+ PIN_MODE_INPUT(GPIOK_PIN10) | \
+ PIN_MODE_INPUT(GPIOK_PIN11) | \
+ PIN_MODE_INPUT(GPIOK_PIN12) | \
+ PIN_MODE_INPUT(GPIOK_PIN13) | \
+ PIN_MODE_INPUT(GPIOK_PIN14) | \
+ PIN_MODE_INPUT(GPIOK_PIN15))
+#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN15))
+#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN15))
+#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLUP(GPIOK_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN15))
+#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \
+ PIN_ODR_HIGH(GPIOK_PIN1) | \
+ PIN_ODR_HIGH(GPIOK_PIN2) | \
+ PIN_ODR_HIGH(GPIOK_PIN3) | \
+ PIN_ODR_HIGH(GPIOK_PIN4) | \
+ PIN_ODR_HIGH(GPIOK_PIN5) | \
+ PIN_ODR_HIGH(GPIOK_PIN6) | \
+ PIN_ODR_HIGH(GPIOK_PIN7) | \
+ PIN_ODR_HIGH(GPIOK_PIN8) | \
+ PIN_ODR_HIGH(GPIOK_PIN9) | \
+ PIN_ODR_HIGH(GPIOK_PIN10) | \
+ PIN_ODR_HIGH(GPIOK_PIN11) | \
+ PIN_ODR_HIGH(GPIOK_PIN12) | \
+ PIN_ODR_HIGH(GPIOK_PIN13) | \
+ PIN_ODR_HIGH(GPIOK_PIN14) | \
+ PIN_ODR_HIGH(GPIOK_PIN15))
+#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN7, 0U))
+#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN15, 0U))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/board.mk b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/board.mk new file mode 100644 index 0000000..2b81cfe --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H743ZI/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H743ZI
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/cfg/board.chcfg b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/cfg/board.chcfg new file mode 100644 index 0000000..c9948ca --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/cfg/board.chcfg @@ -0,0 +1,1459 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F7xx board Template -->
+<board
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32h7xx_board.xsd">
+ <configuration_settings>
+ <templates_path>resources/gencfg/processors/boards/stm32h7xx/templates</templates_path>
+ <output_path>..</output_path>
+ <hal_version>5.0.x</hal_version>
+ </configuration_settings>
+ <board_name>STMicroelectronics STM32 Nucleo144-H743ZI</board_name>
+ <board_id>ST_NUCLEO144_H743ZI</board_id>
+ <board_functions></board_functions>
+ <headers></headers>
+ <ethernet_phy>
+ <identifier>MII_LAN8742A_ID</identifier>
+ <bus_type>RMII</bus_type>
+ </ethernet_phy>
+ <subtype>STM32H743xx</subtype>
+ <clocks
+ HSEFrequency="8000000"
+ HSEBypass="true"
+ LSEFrequency="32768"
+ LSEBypass="false"
+ VDD="300"
+ LSEDrive="3 High Drive (default)" />
+ <ports>
+ <GPIOA>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="RMII_REF_CLK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin2
+ ID="RMII_MDIO"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID="RMII_CRS_DV"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin8
+ ID="USB_SOF MCO1"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin9
+ ID="USB_VBUS"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID="USB_ID"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin11
+ ID="USB_DM"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin12
+ ID="USB_DP"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin13
+ ID="SWDIO"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin14
+ ID="SWCLK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin15
+ ID="T_JTDI"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Alternate"
+ Alternate="0" />
+ </GPIOA>
+ <GPIOB>
+ <pin0
+ ID="LED1 LED_GREEN LED"
+ Type="PushPull"
+ Level="Low"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="SWO"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID="LED2 LED_BLUE"
+ Type="PushPull"
+ Level="Low"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID="RMII_TXD1"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin14
+ ID="LED3 LED_RED"
+ Type="PushPull"
+ Level="Low"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOB>
+ <GPIOC>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="RMII_MDC"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID="RMII_RXD0"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin5
+ ID="RMII_RXD1"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID="BUTTON"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID="OSC32_IN"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID="OSC32_OUT"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOC>
+ <GPIOD>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID="USART3_RX STLK_RX"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="7" />
+ <pin9
+ ID="USART3_TX STLK_TX"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="7" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOD>
+ <GPIOE>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOE>
+ <GPIOF>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOF>
+ <GPIOG>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID="USB_FS_PWR_EN"
+ Type="PushPull"
+ Level="Low"
+ Speed="Minimum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin7
+ ID="USB_FS_OVCR"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID="RMII_TX_EN"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID="RMII_TXD0"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOG>
+ <GPIOH>
+ <pin0
+ ID="OSC_IN"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="OSC_OUT"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOH>
+ <GPIOI>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOI>
+ <GPIOJ>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOJ>
+ <GPIOK>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOK>
+ </ports>
+</board>
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/cfg/board.fmpp b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/cfg/board.fmpp new file mode 100644 index 0000000..5003d98 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H743ZI/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../tools/ftl/processors/boards/stm32h7xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +} diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/board.c b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/board.c new file mode 100644 index 0000000..2868726 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/board.c @@ -0,0 +1,266 @@ +/*
+ ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ gpio_setup_t PKData;
+#endif
+} gpio_config_t;
+
+/**
+ * @brief STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
+#endif
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetAHB4(STM32_GPIO_EN_MASK);
+ rccEnableAHB4(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+ gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+ gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
+ */
+void __early_init(void) {
+
+ stm32_gpio_init();
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @note You can add your board-specific code here.
+ */
+void boardInit(void) {
+
+}
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/board.h b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/board.h new file mode 100644 index 0000000..ab8b5b9 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/board.h @@ -0,0 +1,1642 @@ +/*
+ ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * Setup for STMicroelectronics STM32 Nucleo144-H755ZI board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_NUCLEO144_H755ZI
+#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-H755ZI"
+
+/*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID MII_LAN8742A_ID
+#define BOARD_PHY_RMII
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768U
+#endif
+
+#define STM32_LSEDRV (3U << 3U)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000U
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32H755xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_PIN0 0U
+#define GPIOA_RMII_REF_CLK 1U
+#define GPIOA_RMII_MDIO 2U
+#define GPIOA_PIN3 3U
+#define GPIOA_PIN4 4U
+#define GPIOA_PIN5 5U
+#define GPIOA_PIN6 6U
+#define GPIOA_RMII_CRS_DV 7U
+#define GPIOA_USB_SOF 8U
+#define GPIOA_MCO1 8U
+#define GPIOA_USB_VBUS 9U
+#define GPIOA_USB_ID 10U
+#define GPIOA_USB_DM 11U
+#define GPIOA_USB_DP 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_T_JTDI 15U
+
+#define GPIOB_LED1 0U
+#define GPIOB_LED_GREEN 0U
+#define GPIOB_LED 0U
+#define GPIOB_PIN1 1U
+#define GPIOB_PIN2 2U
+#define GPIOB_SWO 3U
+#define GPIOB_PIN4 4U
+#define GPIOB_PIN5 5U
+#define GPIOB_PIN6 6U
+#define GPIOB_PIN7 7U
+#define GPIOB_PIN8 8U
+#define GPIOB_PIN9 9U
+#define GPIOB_PIN10 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_PIN12 12U
+#define GPIOB_RMII_TXD1 13U
+#define GPIOB_LED3 14U
+#define GPIOB_LED_RED 14U
+#define GPIOB_PIN15 15U
+
+#define GPIOC_PIN0 0U
+#define GPIOC_RMII_MDC 1U
+#define GPIOC_PIN2 2U
+#define GPIOC_PIN3 3U
+#define GPIOC_RMII_RXD0 4U
+#define GPIOC_RMII_RXD1 5U
+#define GPIOC_PIN6 6U
+#define GPIOC_PIN7 7U
+#define GPIOC_PIN8 8U
+#define GPIOC_PIN9 9U
+#define GPIOC_PIN10 10U
+#define GPIOC_PIN11 11U
+#define GPIOC_PIN12 12U
+#define GPIOC_BUTTON 13U
+#define GPIOC_OSC32_IN 14U
+#define GPIOC_OSC32_OUT 15U
+
+#define GPIOD_PIN0 0U
+#define GPIOD_PIN1 1U
+#define GPIOD_PIN2 2U
+#define GPIOD_PIN3 3U
+#define GPIOD_PIN4 4U
+#define GPIOD_PIN5 5U
+#define GPIOD_PIN6 6U
+#define GPIOD_PIN7 7U
+#define GPIOD_USART3_RX 8U
+#define GPIOD_STLK_RX 8U
+#define GPIOD_USART3_TX 9U
+#define GPIOD_STLK_TX 9U
+#define GPIOD_USB_FS_PWR_EN 10U
+#define GPIOD_PIN11 11U
+#define GPIOD_PIN12 12U
+#define GPIOD_PIN13 13U
+#define GPIOD_PIN14 14U
+#define GPIOD_PIN15 15U
+
+#define GPIOE_PIN0 0U
+#define GPIOE_LED2 1U
+#define GPIOE_LED_YELLOW 1U
+#define GPIOE_PIN2 2U
+#define GPIOE_PIN3 3U
+#define GPIOE_PIN4 4U
+#define GPIOE_PIN5 5U
+#define GPIOE_PIN6 6U
+#define GPIOE_PIN7 7U
+#define GPIOE_PIN8 8U
+#define GPIOE_PIN9 9U
+#define GPIOE_PIN10 10U
+#define GPIOE_PIN11 11U
+#define GPIOE_PIN12 12U
+#define GPIOE_PIN13 13U
+#define GPIOE_PIN14 14U
+#define GPIOE_PIN15 15U
+
+#define GPIOF_PIN0 0U
+#define GPIOF_PIN1 1U
+#define GPIOF_PIN2 2U
+#define GPIOF_PIN3 3U
+#define GPIOF_PIN4 4U
+#define GPIOF_PIN5 5U
+#define GPIOF_PIN6 6U
+#define GPIOF_PIN7 7U
+#define GPIOF_PIN8 8U
+#define GPIOF_PIN9 9U
+#define GPIOF_PIN10 10U
+#define GPIOF_PIN11 11U
+#define GPIOF_PIN12 12U
+#define GPIOF_PIN13 13U
+#define GPIOF_PIN14 14U
+#define GPIOF_PIN15 15U
+
+#define GPIOG_PIN0 0U
+#define GPIOG_PIN1 1U
+#define GPIOG_PIN2 2U
+#define GPIOG_PIN3 3U
+#define GPIOG_PIN4 4U
+#define GPIOG_PIN5 5U
+#define GPIOG_PIN6 6U
+#define GPIOG_USB_FS_OVCR 7U
+#define GPIOG_PIN8 8U
+#define GPIOG_PIN9 9U
+#define GPIOG_PIN10 10U
+#define GPIOG_RMII_TX_EN 11U
+#define GPIOG_PIN12 12U
+#define GPIOG_RMII_TXD0 13U
+#define GPIOG_PIN14 14U
+#define GPIOG_PIN15 15U
+
+#define GPIOH_OSC_IN 0U
+#define GPIOH_OSC_OUT 1U
+#define GPIOH_PIN2 2U
+#define GPIOH_PIN3 3U
+#define GPIOH_PIN4 4U
+#define GPIOH_PIN5 5U
+#define GPIOH_PIN6 6U
+#define GPIOH_PIN7 7U
+#define GPIOH_PIN8 8U
+#define GPIOH_PIN9 9U
+#define GPIOH_PIN10 10U
+#define GPIOH_PIN11 11U
+#define GPIOH_PIN12 12U
+#define GPIOH_PIN13 13U
+#define GPIOH_PIN14 14U
+#define GPIOH_PIN15 15U
+
+#define GPIOI_PIN0 0U
+#define GPIOI_PIN1 1U
+#define GPIOI_PIN2 2U
+#define GPIOI_PIN3 3U
+#define GPIOI_PIN4 4U
+#define GPIOI_PIN5 5U
+#define GPIOI_PIN6 6U
+#define GPIOI_PIN7 7U
+#define GPIOI_PIN8 8U
+#define GPIOI_PIN9 9U
+#define GPIOI_PIN10 10U
+#define GPIOI_PIN11 11U
+#define GPIOI_PIN12 12U
+#define GPIOI_PIN13 13U
+#define GPIOI_PIN14 14U
+#define GPIOI_PIN15 15U
+
+#define GPIOJ_PIN0 0U
+#define GPIOJ_PIN1 1U
+#define GPIOJ_PIN2 2U
+#define GPIOJ_PIN3 3U
+#define GPIOJ_PIN4 4U
+#define GPIOJ_PIN5 5U
+#define GPIOJ_PIN6 6U
+#define GPIOJ_PIN7 7U
+#define GPIOJ_PIN8 8U
+#define GPIOJ_PIN9 9U
+#define GPIOJ_PIN10 10U
+#define GPIOJ_PIN11 11U
+#define GPIOJ_PIN12 12U
+#define GPIOJ_PIN13 13U
+#define GPIOJ_PIN14 14U
+#define GPIOJ_PIN15 15U
+
+#define GPIOK_PIN0 0U
+#define GPIOK_PIN1 1U
+#define GPIOK_PIN2 2U
+#define GPIOK_PIN3 3U
+#define GPIOK_PIN4 4U
+#define GPIOK_PIN5 5U
+#define GPIOK_PIN6 6U
+#define GPIOK_PIN7 7U
+#define GPIOK_PIN8 8U
+#define GPIOK_PIN9 9U
+#define GPIOK_PIN10 10U
+#define GPIOK_PIN11 11U
+#define GPIOK_PIN12 12U
+#define GPIOK_PIN13 13U
+#define GPIOK_PIN14 14U
+#define GPIOK_PIN15 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_RMII_REF_CLK PAL_LINE(GPIOA, 1U)
+#define LINE_RMII_MDIO PAL_LINE(GPIOA, 2U)
+#define LINE_RMII_CRS_DV PAL_LINE(GPIOA, 7U)
+#define LINE_USB_SOF PAL_LINE(GPIOA, 8U)
+#define LINE_MCO1 PAL_LINE(GPIOA, 8U)
+#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U)
+#define LINE_USB_ID PAL_LINE(GPIOA, 10U)
+#define LINE_USB_DM PAL_LINE(GPIOA, 11U)
+#define LINE_USB_DP PAL_LINE(GPIOA, 12U)
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
+#define LINE_T_JTDI PAL_LINE(GPIOA, 15U)
+#define LINE_LED1 PAL_LINE(GPIOB, 0U)
+#define LINE_LED_GREEN PAL_LINE(GPIOB, 0U)
+#define LINE_LED PAL_LINE(GPIOB, 0U)
+#define LINE_SWO PAL_LINE(GPIOB, 3U)
+#define LINE_RMII_TXD1 PAL_LINE(GPIOB, 13U)
+#define LINE_LED3 PAL_LINE(GPIOB, 14U)
+#define LINE_LED_RED PAL_LINE(GPIOB, 14U)
+#define LINE_RMII_MDC PAL_LINE(GPIOC, 1U)
+#define LINE_RMII_RXD0 PAL_LINE(GPIOC, 4U)
+#define LINE_RMII_RXD1 PAL_LINE(GPIOC, 5U)
+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
+#define LINE_USART3_RX PAL_LINE(GPIOD, 8U)
+#define LINE_STLK_RX PAL_LINE(GPIOD, 8U)
+#define LINE_USART3_TX PAL_LINE(GPIOD, 9U)
+#define LINE_STLK_TX PAL_LINE(GPIOD, 9U)
+#define LINE_USB_FS_PWR_EN PAL_LINE(GPIOD, 10U)
+#define LINE_LED2 PAL_LINE(GPIOE, 1U)
+#define LINE_LED_YELLOW PAL_LINE(GPIOE, 1U)
+#define LINE_USB_FS_OVCR PAL_LINE(GPIOG, 7U)
+#define LINE_RMII_TX_EN PAL_LINE(GPIOG, 11U)
+#define LINE_RMII_TXD0 PAL_LINE(GPIOG, 13U)
+#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
+#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - PIN0 (input pullup).
+ * PA1 - RMII_REF_CLK (alternate 11).
+ * PA2 - RMII_MDIO (alternate 11).
+ * PA3 - PIN3 (input pullup).
+ * PA4 - PIN4 (input pullup).
+ * PA5 - PIN5 (input pullup).
+ * PA6 - PIN6 (input pullup).
+ * PA7 - RMII_CRS_DV (alternate 11).
+ * PA8 - USB_SOF MCO1 (alternate 10).
+ * PA9 - USB_VBUS (analog).
+ * PA10 - USB_ID (alternate 10).
+ * PA11 - USB_DM (alternate 10).
+ * PA12 - USB_DP (alternate 10).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - T_JTDI (alternate 0).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \
+ PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\
+ PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \
+ PIN_MODE_INPUT(GPIOA_PIN3) | \
+ PIN_MODE_INPUT(GPIOA_PIN4) | \
+ PIN_MODE_INPUT(GPIOA_PIN5) | \
+ PIN_MODE_INPUT(GPIOA_PIN6) | \
+ PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) |\
+ PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \
+ PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_ALTERNATE(GPIOA_T_JTDI))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_T_JTDI))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \
+ PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOA_RMII_CRS_DV) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_ID) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_DM) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_DP) | \
+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
+ PIN_OSPEED_HIGH(GPIOA_T_JTDI))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\
+ PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOA_RMII_CRS_DV) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \
+ PIN_PUPDR_PULLUP(GPIOA_T_JTDI))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \
+ PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \
+ PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \
+ PIN_ODR_HIGH(GPIOA_PIN3) | \
+ PIN_ODR_HIGH(GPIOA_PIN4) | \
+ PIN_ODR_HIGH(GPIOA_PIN5) | \
+ PIN_ODR_HIGH(GPIOA_PIN6) | \
+ PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) | \
+ PIN_ODR_HIGH(GPIOA_USB_SOF) | \
+ PIN_ODR_HIGH(GPIOA_USB_VBUS) | \
+ PIN_ODR_HIGH(GPIOA_USB_ID) | \
+ PIN_ODR_HIGH(GPIOA_USB_DM) | \
+ PIN_ODR_HIGH(GPIOA_USB_DP) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_T_JTDI))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \
+ PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) | \
+ PIN_AFIO_AF(GPIOA_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11U))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \
+ PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \
+ PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \
+ PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \
+ PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
+ PIN_AFIO_AF(GPIOA_T_JTDI, 0U))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - LED1 LED_GREEN LED (output pushpull maximum).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - SWO (alternate 0).
+ * PB4 - PIN4 (input pullup).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - PIN6 (input pullup).
+ * PB7 - PIN7 (input pullup).
+ * PB8 - PIN8 (input pullup).
+ * PB9 - PIN9 (input pullup).
+ * PB10 - PIN10 (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - RMII_TXD1 (alternate 11).
+ * PB14 - LED3 LED_RED (output pushpull maximum).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_LED1) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \
+ PIN_MODE_INPUT(GPIOB_PIN4) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_INPUT(GPIOB_PIN6) | \
+ PIN_MODE_INPUT(GPIOB_PIN7) | \
+ PIN_MODE_INPUT(GPIOB_PIN8) | \
+ PIN_MODE_INPUT(GPIOB_PIN9) | \
+ PIN_MODE_INPUT(GPIOB_PIN10) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOB_RMII_TXD1) | \
+ PIN_MODE_OUTPUT(GPIOB_LED3) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_LED1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_RMII_TXD1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_LED1) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOB_SWO) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOB_RMII_TXD1) | \
+ PIN_OSPEED_HIGH(GPIOB_LED3) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_LED1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOB_SWO) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_RMII_TXD1) | \
+ PIN_PUPDR_FLOATING(GPIOB_LED3) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_LED1) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_SWO) | \
+ PIN_ODR_HIGH(GPIOB_PIN4) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_PIN6) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_PIN8) | \
+ PIN_ODR_HIGH(GPIOB_PIN9) | \
+ PIN_ODR_HIGH(GPIOB_PIN10) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_RMII_TXD1) | \
+ PIN_ODR_LOW(GPIOB_LED3) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_LED1, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOB_SWO, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0U))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOB_RMII_TXD1, 11U) | \
+ PIN_AFIO_AF(GPIOB_LED3, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0U))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - PIN0 (input pullup).
+ * PC1 - RMII_MDC (alternate 11).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PIN3 (input pullup).
+ * PC4 - RMII_RXD0 (alternate 11).
+ * PC5 - RMII_RXD1 (alternate 11).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - PIN7 (input pullup).
+ * PC8 - PIN8 (input pullup).
+ * PC9 - PIN9 (input pullup).
+ * PC10 - PIN10 (input pullup).
+ * PC11 - PIN11 (input pullup).
+ * PC12 - PIN12 (input pullup).
+ * PC13 - BUTTON (input floating).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
+ PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PIN3) | \
+ PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \
+ PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_INPUT(GPIOC_PIN7) | \
+ PIN_MODE_INPUT(GPIOC_PIN8) | \
+ PIN_MODE_INPUT(GPIOC_PIN9) | \
+ PIN_MODE_INPUT(GPIOC_PIN10) | \
+ PIN_MODE_INPUT(GPIOC_PIN11) | \
+ PIN_MODE_INPUT(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \
+ PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOC_BUTTON) | \
+ PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \
+ PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
+ PIN_ODR_HIGH(GPIOC_RMII_MDC) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PIN3) | \
+ PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \
+ PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_PIN7) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_PIN10) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_PIN12) | \
+ PIN_ODR_HIGH(GPIOC_BUTTON) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) | \
+ PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN7, 0U))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - PIN4 (input pullup).
+ * PD5 - PIN5 (input pullup).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - USART3_RX STLK_RX (alternate 7).
+ * PD9 - USART3_TX STLK_TX (alternate 7).
+ * PD10 - USB_FS_PWR_EN (output opendrain minimum).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_INPUT(GPIOD_PIN4) | \
+ PIN_MODE_INPUT(GPIOD_PIN5) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \
+ PIN_MODE_OUTPUT(GPIOD_USB_FS_PWR_EN) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \
+ PIN_OTYPE_OPENDRAIN(GPIOD_USB_FS_PWR_EN) |\
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \
+ PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \
+ PIN_OSPEED_VERYLOW(GPIOD_USB_FS_PWR_EN) |\
+ PIN_OSPEED_VERYLOW(GPIOD_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \
+ PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \
+ PIN_PUPDR_FLOATING(GPIOD_USB_FS_PWR_EN) |\
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_USART3_RX) | \
+ PIN_ODR_HIGH(GPIOD_USART3_TX) | \
+ PIN_ODR_HIGH(GPIOD_USB_FS_PWR_EN) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \
+ PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \
+ PIN_AFIO_AF(GPIOD_USB_FS_PWR_EN, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (input pullup).
+ * PE1 - LED2 LED_YELLOW (output pushpull maximum).
+ * PE2 - PIN2 (input pullup).
+ * PE3 - PIN3 (input pullup).
+ * PE4 - PIN4 (input pullup).
+ * PE5 - PIN5 (input pullup).
+ * PE6 - PIN6 (input pullup).
+ * PE7 - PIN7 (input pullup).
+ * PE8 - PIN8 (input pullup).
+ * PE9 - PIN9 (input pullup).
+ * PE10 - PIN10 (input pullup).
+ * PE11 - PIN11 (input pullup).
+ * PE12 - PIN12 (input pullup).
+ * PE13 - PIN13 (input pullup).
+ * PE14 - PIN14 (input pullup).
+ * PE15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
+ PIN_MODE_OUTPUT(GPIOE_LED2) | \
+ PIN_MODE_INPUT(GPIOE_PIN2) | \
+ PIN_MODE_INPUT(GPIOE_PIN3) | \
+ PIN_MODE_INPUT(GPIOE_PIN4) | \
+ PIN_MODE_INPUT(GPIOE_PIN5) | \
+ PIN_MODE_INPUT(GPIOE_PIN6) | \
+ PIN_MODE_INPUT(GPIOE_PIN7) | \
+ PIN_MODE_INPUT(GPIOE_PIN8) | \
+ PIN_MODE_INPUT(GPIOE_PIN9) | \
+ PIN_MODE_INPUT(GPIOE_PIN10) | \
+ PIN_MODE_INPUT(GPIOE_PIN11) | \
+ PIN_MODE_INPUT(GPIOE_PIN12) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PIN14) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LED2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOE_LED2) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOE_LED2) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
+ PIN_ODR_LOW(GPIOE_LED2) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_PIN3) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOE_LED2, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0U))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0U))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - PIN0 (input pullup).
+ * PF1 - PIN1 (input pullup).
+ * PF2 - PIN2 (input pullup).
+ * PF3 - PIN3 (input pullup).
+ * PF4 - PIN4 (input pullup).
+ * PF5 - PIN5 (input pullup).
+ * PF6 - PIN6 (input pullup).
+ * PF7 - PIN7 (input pullup).
+ * PF8 - PIN8 (input pullup).
+ * PF9 - PIN9 (input pullup).
+ * PF10 - PIN10 (input pullup).
+ * PF11 - PIN11 (input pullup).
+ * PF12 - PIN12 (input pullup).
+ * PF13 - PIN13 (input pullup).
+ * PF14 - PIN14 (input pullup).
+ * PF15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
+ PIN_MODE_INPUT(GPIOF_PIN1) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0U))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0U))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (input pullup).
+ * PG1 - PIN1 (input pullup).
+ * PG2 - PIN2 (input pullup).
+ * PG3 - PIN3 (input pullup).
+ * PG4 - PIN4 (input pullup).
+ * PG5 - PIN5 (input pullup).
+ * PG6 - PIN6 (input pullup).
+ * PG7 - USB_FS_OVCR (input floating).
+ * PG8 - PIN8 (input pullup).
+ * PG9 - PIN9 (input pullup).
+ * PG10 - PIN10 (input pullup).
+ * PG11 - RMII_TX_EN (alternate 11).
+ * PG12 - PIN12 (input pullup).
+ * PG13 - RMII_TXD0 (alternate 11).
+ * PG14 - PIN14 (input pullup).
+ * PG15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \
+ PIN_MODE_INPUT(GPIOG_PIN1) | \
+ PIN_MODE_INPUT(GPIOG_PIN2) | \
+ PIN_MODE_INPUT(GPIOG_PIN3) | \
+ PIN_MODE_INPUT(GPIOG_PIN4) | \
+ PIN_MODE_INPUT(GPIOG_PIN5) | \
+ PIN_MODE_INPUT(GPIOG_PIN6) | \
+ PIN_MODE_INPUT(GPIOG_USB_FS_OVCR) | \
+ PIN_MODE_INPUT(GPIOG_PIN8) | \
+ PIN_MODE_INPUT(GPIOG_PIN9) | \
+ PIN_MODE_INPUT(GPIOG_PIN10) | \
+ PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \
+ PIN_MODE_INPUT(GPIOG_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \
+ PIN_MODE_INPUT(GPIOG_PIN14) | \
+ PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_USB_FS_OVCR) |\
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOG_USB_FS_OVCR) |\
+ PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOG_USB_FS_OVCR) |\
+ PIN_PUPDR_PULLUP(GPIOG_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
+ PIN_ODR_HIGH(GPIOG_PIN1) | \
+ PIN_ODR_HIGH(GPIOG_PIN2) | \
+ PIN_ODR_HIGH(GPIOG_PIN3) | \
+ PIN_ODR_HIGH(GPIOG_PIN4) | \
+ PIN_ODR_HIGH(GPIOG_PIN5) | \
+ PIN_ODR_HIGH(GPIOG_PIN6) | \
+ PIN_ODR_HIGH(GPIOG_USB_FS_OVCR) | \
+ PIN_ODR_HIGH(GPIOG_PIN8) | \
+ PIN_ODR_HIGH(GPIOG_PIN9) | \
+ PIN_ODR_HIGH(GPIOG_PIN10) | \
+ PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \
+ PIN_ODR_HIGH(GPIOG_PIN12) | \
+ PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \
+ PIN_ODR_HIGH(GPIOG_PIN14) | \
+ PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOG_USB_FS_OVCR, 0U))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) | \
+ PIN_AFIO_AF(GPIOG_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0U))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input pullup).
+ * PH3 - PIN3 (input pullup).
+ * PH4 - PIN4 (input pullup).
+ * PH5 - PIN5 (input pullup).
+ * PH6 - PIN6 (input pullup).
+ * PH7 - PIN7 (input pullup).
+ * PH8 - PIN8 (input pullup).
+ * PH9 - PIN9 (input pullup).
+ * PH10 - PIN10 (input pullup).
+ * PH11 - PIN11 (input pullup).
+ * PH12 - PIN12 (input pullup).
+ * PH13 - PIN13 (input pullup).
+ * PH14 - PIN14 (input pullup).
+ * PH15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \
+ PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0U))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0U))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0 - PIN0 (input pullup).
+ * PI1 - PIN1 (input pullup).
+ * PI2 - PIN2 (input pullup).
+ * PI3 - PIN3 (input pullup).
+ * PI4 - PIN4 (input pullup).
+ * PI5 - PIN5 (input pullup).
+ * PI6 - PIN6 (input pullup).
+ * PI7 - PIN7 (input pullup).
+ * PI8 - PIN8 (input pullup).
+ * PI9 - PIN9 (input pullup).
+ * PI10 - PIN10 (input pullup).
+ * PI11 - PIN11 (input pullup).
+ * PI12 - PIN12 (input pullup).
+ * PI13 - PIN13 (input pullup).
+ * PI14 - PIN14 (input pullup).
+ * PI15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
+ PIN_MODE_INPUT(GPIOI_PIN1) | \
+ PIN_MODE_INPUT(GPIOI_PIN2) | \
+ PIN_MODE_INPUT(GPIOI_PIN3) | \
+ PIN_MODE_INPUT(GPIOI_PIN4) | \
+ PIN_MODE_INPUT(GPIOI_PIN5) | \
+ PIN_MODE_INPUT(GPIOI_PIN6) | \
+ PIN_MODE_INPUT(GPIOI_PIN7) | \
+ PIN_MODE_INPUT(GPIOI_PIN8) | \
+ PIN_MODE_INPUT(GPIOI_PIN9) | \
+ PIN_MODE_INPUT(GPIOI_PIN10) | \
+ PIN_MODE_INPUT(GPIOI_PIN11) | \
+ PIN_MODE_INPUT(GPIOI_PIN12) | \
+ PIN_MODE_INPUT(GPIOI_PIN13) | \
+ PIN_MODE_INPUT(GPIOI_PIN14) | \
+ PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN15))
+#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
+ PIN_ODR_HIGH(GPIOI_PIN1) | \
+ PIN_ODR_HIGH(GPIOI_PIN2) | \
+ PIN_ODR_HIGH(GPIOI_PIN3) | \
+ PIN_ODR_HIGH(GPIOI_PIN4) | \
+ PIN_ODR_HIGH(GPIOI_PIN5) | \
+ PIN_ODR_HIGH(GPIOI_PIN6) | \
+ PIN_ODR_HIGH(GPIOI_PIN7) | \
+ PIN_ODR_HIGH(GPIOI_PIN8) | \
+ PIN_ODR_HIGH(GPIOI_PIN9) | \
+ PIN_ODR_HIGH(GPIOI_PIN10) | \
+ PIN_ODR_HIGH(GPIOI_PIN11) | \
+ PIN_ODR_HIGH(GPIOI_PIN12) | \
+ PIN_ODR_HIGH(GPIOI_PIN13) | \
+ PIN_ODR_HIGH(GPIOI_PIN14) | \
+ PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN7, 0U))
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN15, 0U))
+
+/*
+ * GPIOJ setup:
+ *
+ * PJ0 - PIN0 (input pullup).
+ * PJ1 - PIN1 (input pullup).
+ * PJ2 - PIN2 (input pullup).
+ * PJ3 - PIN3 (input pullup).
+ * PJ4 - PIN4 (input pullup).
+ * PJ5 - PIN5 (input pullup).
+ * PJ6 - PIN6 (input pullup).
+ * PJ7 - PIN7 (input pullup).
+ * PJ8 - PIN8 (input pullup).
+ * PJ9 - PIN9 (input pullup).
+ * PJ10 - PIN10 (input pullup).
+ * PJ11 - PIN11 (input pullup).
+ * PJ12 - PIN12 (input pullup).
+ * PJ13 - PIN13 (input pullup).
+ * PJ14 - PIN14 (input pullup).
+ * PJ15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \
+ PIN_MODE_INPUT(GPIOJ_PIN1) | \
+ PIN_MODE_INPUT(GPIOJ_PIN2) | \
+ PIN_MODE_INPUT(GPIOJ_PIN3) | \
+ PIN_MODE_INPUT(GPIOJ_PIN4) | \
+ PIN_MODE_INPUT(GPIOJ_PIN5) | \
+ PIN_MODE_INPUT(GPIOJ_PIN6) | \
+ PIN_MODE_INPUT(GPIOJ_PIN7) | \
+ PIN_MODE_INPUT(GPIOJ_PIN8) | \
+ PIN_MODE_INPUT(GPIOJ_PIN9) | \
+ PIN_MODE_INPUT(GPIOJ_PIN10) | \
+ PIN_MODE_INPUT(GPIOJ_PIN11) | \
+ PIN_MODE_INPUT(GPIOJ_PIN12) | \
+ PIN_MODE_INPUT(GPIOJ_PIN13) | \
+ PIN_MODE_INPUT(GPIOJ_PIN14) | \
+ PIN_MODE_INPUT(GPIOJ_PIN15))
+#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN15))
+#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN15))
+#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLUP(GPIOJ_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN15))
+#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \
+ PIN_ODR_HIGH(GPIOJ_PIN1) | \
+ PIN_ODR_HIGH(GPIOJ_PIN2) | \
+ PIN_ODR_HIGH(GPIOJ_PIN3) | \
+ PIN_ODR_HIGH(GPIOJ_PIN4) | \
+ PIN_ODR_HIGH(GPIOJ_PIN5) | \
+ PIN_ODR_HIGH(GPIOJ_PIN6) | \
+ PIN_ODR_HIGH(GPIOJ_PIN7) | \
+ PIN_ODR_HIGH(GPIOJ_PIN8) | \
+ PIN_ODR_HIGH(GPIOJ_PIN9) | \
+ PIN_ODR_HIGH(GPIOJ_PIN10) | \
+ PIN_ODR_HIGH(GPIOJ_PIN11) | \
+ PIN_ODR_HIGH(GPIOJ_PIN12) | \
+ PIN_ODR_HIGH(GPIOJ_PIN13) | \
+ PIN_ODR_HIGH(GPIOJ_PIN14) | \
+ PIN_ODR_HIGH(GPIOJ_PIN15))
+#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN7, 0U))
+#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN15, 0U))
+
+/*
+ * GPIOK setup:
+ *
+ * PK0 - PIN0 (input pullup).
+ * PK1 - PIN1 (input pullup).
+ * PK2 - PIN2 (input pullup).
+ * PK3 - PIN3 (input pullup).
+ * PK4 - PIN4 (input pullup).
+ * PK5 - PIN5 (input pullup).
+ * PK6 - PIN6 (input pullup).
+ * PK7 - PIN7 (input pullup).
+ * PK8 - PIN8 (input pullup).
+ * PK9 - PIN9 (input pullup).
+ * PK10 - PIN10 (input pullup).
+ * PK11 - PIN11 (input pullup).
+ * PK12 - PIN12 (input pullup).
+ * PK13 - PIN13 (input pullup).
+ * PK14 - PIN14 (input pullup).
+ * PK15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \
+ PIN_MODE_INPUT(GPIOK_PIN1) | \
+ PIN_MODE_INPUT(GPIOK_PIN2) | \
+ PIN_MODE_INPUT(GPIOK_PIN3) | \
+ PIN_MODE_INPUT(GPIOK_PIN4) | \
+ PIN_MODE_INPUT(GPIOK_PIN5) | \
+ PIN_MODE_INPUT(GPIOK_PIN6) | \
+ PIN_MODE_INPUT(GPIOK_PIN7) | \
+ PIN_MODE_INPUT(GPIOK_PIN8) | \
+ PIN_MODE_INPUT(GPIOK_PIN9) | \
+ PIN_MODE_INPUT(GPIOK_PIN10) | \
+ PIN_MODE_INPUT(GPIOK_PIN11) | \
+ PIN_MODE_INPUT(GPIOK_PIN12) | \
+ PIN_MODE_INPUT(GPIOK_PIN13) | \
+ PIN_MODE_INPUT(GPIOK_PIN14) | \
+ PIN_MODE_INPUT(GPIOK_PIN15))
+#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN15))
+#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN15))
+#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLUP(GPIOK_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN15))
+#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \
+ PIN_ODR_HIGH(GPIOK_PIN1) | \
+ PIN_ODR_HIGH(GPIOK_PIN2) | \
+ PIN_ODR_HIGH(GPIOK_PIN3) | \
+ PIN_ODR_HIGH(GPIOK_PIN4) | \
+ PIN_ODR_HIGH(GPIOK_PIN5) | \
+ PIN_ODR_HIGH(GPIOK_PIN6) | \
+ PIN_ODR_HIGH(GPIOK_PIN7) | \
+ PIN_ODR_HIGH(GPIOK_PIN8) | \
+ PIN_ODR_HIGH(GPIOK_PIN9) | \
+ PIN_ODR_HIGH(GPIOK_PIN10) | \
+ PIN_ODR_HIGH(GPIOK_PIN11) | \
+ PIN_ODR_HIGH(GPIOK_PIN12) | \
+ PIN_ODR_HIGH(GPIOK_PIN13) | \
+ PIN_ODR_HIGH(GPIOK_PIN14) | \
+ PIN_ODR_HIGH(GPIOK_PIN15))
+#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN7, 0U))
+#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN15, 0U))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/board.mk b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/board.mk new file mode 100644 index 0000000..f37066e --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H755ZI/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H755ZI
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/cfg/board.chcfg b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/cfg/board.chcfg new file mode 100644 index 0000000..6aa144f --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/cfg/board.chcfg @@ -0,0 +1,1459 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F7xx board Template -->
+<board
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32h7xx_board.xsd">
+ <configuration_settings>
+ <templates_path>resources/gencfg/processors/boards/stm32h7xx/templates</templates_path>
+ <output_path>..</output_path>
+ <hal_version>5.0.x</hal_version>
+ </configuration_settings>
+ <board_name>STMicroelectronics STM32 Nucleo144-H755ZI</board_name>
+ <board_id>ST_NUCLEO144_H755ZI</board_id>
+ <board_functions></board_functions>
+ <headers></headers>
+ <ethernet_phy>
+ <identifier>MII_LAN8742A_ID</identifier>
+ <bus_type>RMII</bus_type>
+ </ethernet_phy>
+ <subtype>STM32H755xx</subtype>
+ <clocks
+ HSEFrequency="8000000"
+ HSEBypass="true"
+ LSEFrequency="32768"
+ LSEBypass="false"
+ VDD="300"
+ LSEDrive="3 High Drive (default)" />
+ <ports>
+ <GPIOA>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="RMII_REF_CLK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin2
+ ID="RMII_MDIO"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID="RMII_CRS_DV"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin8
+ ID="USB_SOF MCO1"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin9
+ ID="USB_VBUS"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID="USB_ID"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin11
+ ID="USB_DM"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin12
+ ID="USB_DP"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin13
+ ID="SWDIO"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin14
+ ID="SWCLK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin15
+ ID="T_JTDI"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Alternate"
+ Alternate="0" />
+ </GPIOA>
+ <GPIOB>
+ <pin0
+ ID="LED1 LED_GREEN LED"
+ Type="PushPull"
+ Level="Low"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="SWO"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID="RMII_TXD1"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin14
+ ID="LED3 LED_RED"
+ Type="PushPull"
+ Level="Low"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOB>
+ <GPIOC>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="RMII_MDC"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID="RMII_RXD0"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin5
+ ID="RMII_RXD1"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID="BUTTON"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID="OSC32_IN"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID="OSC32_OUT"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOC>
+ <GPIOD>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID="USART3_RX STLK_RX"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="7" />
+ <pin9
+ ID="USART3_TX STLK_TX"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="7" />
+ <pin10
+ ID="USB_FS_PWR_EN"
+ Type="OpenDrain"
+ Level="High"
+ Speed="Minimum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOD>
+ <GPIOE>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="LED2 LED_YELLOW"
+ Type="PushPull"
+ Level="Low"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOE>
+ <GPIOF>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOF>
+ <GPIOG>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID="USB_FS_OVCR"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID="RMII_TX_EN"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID="RMII_TXD0"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="11" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOG>
+ <GPIOH>
+ <pin0
+ ID="OSC_IN"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="OSC_OUT"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOH>
+ <GPIOI>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOI>
+ <GPIOJ>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOJ>
+ <GPIOK>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOK>
+ </ports>
+</board>
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/cfg/board.fmpp b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/cfg/board.fmpp new file mode 100644 index 0000000..5003d98 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO144_H755ZI/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../tools/ftl/processors/boards/stm32h7xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +} diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/board.c b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/board.c new file mode 100644 index 0000000..54ad8c3 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/board.c @@ -0,0 +1,266 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ gpio_setup_t PKData;
+#endif
+} gpio_config_t;
+
+/**
+ * @brief STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
+#endif
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetIOP(STM32_GPIO_EN_MASK);
+ rccEnableIOP(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+ gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+ gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
+ */
+void __early_init(void) {
+
+ stm32_gpio_init();
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @note Add your board-specific code, if any.
+ */
+void boardInit(void) {
+
+}
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/board.h b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/board.h new file mode 100644 index 0000000..2ae23b2 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/board.h @@ -0,0 +1,796 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * Setup for STMicroelectronics STM32 Nucleo64-G071RB board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_NUCLEO64_G071RB
+#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-G071RB"
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768U
+#endif
+
+#define STM32_LSEDRV (3U << 11U)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000U
+#endif
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32G071xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_PIN0 0U
+#define GPIOA_PIN1 1U
+#define GPIOA_STLK_RX 2U
+#define GPIOA_STLK_TX 3U
+#define GPIOA_PIN4 4U
+#define GPIOA_LED_GREEN 5U
+#define GPIOA_PIN6 6U
+#define GPIOA_PIN7 7U
+#define GPIOA_PIN8 8U
+#define GPIOA_PIN9 9U
+#define GPIOA_PIN10 10U
+#define GPIOA_PIN11 11U
+#define GPIOA_PIN12 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_PIN15 15U
+
+#define GPIOB_PIN0 0U
+#define GPIOB_PIN1 1U
+#define GPIOB_PIN2 2U
+#define GPIOB_PIN3 3U
+#define GPIOB_PIN4 4U
+#define GPIOB_PIN5 5U
+#define GPIOB_PIN6 6U
+#define GPIOB_PIN7 7U
+#define GPIOB_PIN8 8U
+#define GPIOB_PIN9 9U
+#define GPIOB_PIN10 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_PIN12 12U
+#define GPIOB_PIN13 13U
+#define GPIOB_PIN14 14U
+#define GPIOB_PIN15 15U
+
+#define GPIOC_PIN0 0U
+#define GPIOC_PIN1 1U
+#define GPIOC_PIN2 2U
+#define GPIOC_PIN3 3U
+#define GPIOC_PIN4 4U
+#define GPIOC_PIN5 5U
+#define GPIOC_PIN6 6U
+#define GPIOC_PIN7 7U
+#define GPIOC_PIN8 8U
+#define GPIOC_PIN9 9U
+#define GPIOC_PIN10 10U
+#define GPIOC_PIN11 11U
+#define GPIOC_PIN12 12U
+#define GPIOC_BUTTON 13U
+#define GPIOC_OSC32_IN 14U
+#define GPIOC_OSC32_OUT 15U
+
+#define GPIOD_PIN0 0U
+#define GPIOD_PIN1 1U
+#define GPIOD_PIN2 2U
+#define GPIOD_PIN3 3U
+#define GPIOD_PIN4 4U
+#define GPIOD_PIN5 5U
+#define GPIOD_PIN6 6U
+#define GPIOD_PIN7 7U
+#define GPIOD_PIN8 8U
+#define GPIOD_PIN9 9U
+#define GPIOD_PIN10 10U
+#define GPIOD_PIN11 11U
+#define GPIOD_PIN12 12U
+#define GPIOD_PIN13 13U
+#define GPIOD_PIN14 14U
+#define GPIOD_PIN15 15U
+
+#define GPIOF_OSC_IN 0U
+#define GPIOF_OSC_OUT 1U
+#define GPIOF_PIN2 2U
+#define GPIOF_PIN3 3U
+#define GPIOF_PIN4 4U
+#define GPIOF_PIN5 5U
+#define GPIOF_PIN6 6U
+#define GPIOF_PIN7 7U
+#define GPIOF_PIN8 8U
+#define GPIOF_PIN9 9U
+#define GPIOF_PIN10 10U
+#define GPIOF_PIN11 11U
+#define GPIOF_PIN12 12U
+#define GPIOF_PIN13 13U
+#define GPIOF_PIN14 14U
+#define GPIOF_PIN15 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_STLK_RX PAL_LINE(GPIOA, 2U)
+#define LINE_STLK_TX PAL_LINE(GPIOA, 3U)
+#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U)
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
+#define LINE_OSC_IN PAL_LINE(GPIOF, 0U)
+#define LINE_OSC_OUT PAL_LINE(GPIOF, 1U)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - PIN0 (input pullup).
+ * PA1 - PIN1 (input pullup).
+ * PA2 - STLK_RX (alternate 1).
+ * PA3 - STLK_TX (alternate 1).
+ * PA4 - PIN4 (input pullup).
+ * PA5 - LED_GREEN (output pushpull maximum).
+ * PA6 - PIN6 (input pullup).
+ * PA7 - PIN7 (input pullup).
+ * PA8 - PIN8 (input pullup).
+ * PA9 - PIN9 (input pullup).
+ * PA10 - PIN10 (input pullup).
+ * PA11 - PIN11 (input pullup).
+ * PA12 - PIN12 (input pullup).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \
+ PIN_MODE_INPUT(GPIOA_PIN1) | \
+ PIN_MODE_ALTERNATE(GPIOA_STLK_RX) | \
+ PIN_MODE_ALTERNATE(GPIOA_STLK_TX) | \
+ PIN_MODE_INPUT(GPIOA_PIN4) | \
+ PIN_MODE_OUTPUT(GPIOA_LED_GREEN) | \
+ PIN_MODE_INPUT(GPIOA_PIN6) | \
+ PIN_MODE_INPUT(GPIOA_PIN7) | \
+ PIN_MODE_INPUT(GPIOA_PIN8) | \
+ PIN_MODE_INPUT(GPIOA_PIN9) | \
+ PIN_MODE_INPUT(GPIOA_PIN10) | \
+ PIN_MODE_INPUT(GPIOA_PIN11) | \
+ PIN_MODE_INPUT(GPIOA_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_STLK_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_STLK_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_LED_GREEN) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN1) | \
+ PIN_OSPEED_MEDIUM(GPIOA_STLK_RX) | \
+ PIN_OSPEED_MEDIUM(GPIOA_STLK_TX) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOA_LED_GREEN) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOA_STLK_RX) | \
+ PIN_PUPDR_FLOATING(GPIOA_STLK_TX) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOA_LED_GREEN) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \
+ PIN_ODR_HIGH(GPIOA_PIN1) | \
+ PIN_ODR_HIGH(GPIOA_STLK_RX) | \
+ PIN_ODR_HIGH(GPIOA_STLK_TX) | \
+ PIN_ODR_HIGH(GPIOA_PIN4) | \
+ PIN_ODR_LOW(GPIOA_LED_GREEN) | \
+ PIN_ODR_HIGH(GPIOA_PIN6) | \
+ PIN_ODR_HIGH(GPIOA_PIN7) | \
+ PIN_ODR_HIGH(GPIOA_PIN8) | \
+ PIN_ODR_HIGH(GPIOA_PIN9) | \
+ PIN_ODR_HIGH(GPIOA_PIN10) | \
+ PIN_ODR_HIGH(GPIOA_PIN11) | \
+ PIN_ODR_HIGH(GPIOA_PIN12) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOA_STLK_RX, 1U) | \
+ PIN_AFIO_AF(GPIOA_STLK_TX, 1U) | \
+ PIN_AFIO_AF(GPIOA_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOA_LED_GREEN, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN7, 0U))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0U))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - PIN0 (input pullup).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - PIN3 (input pullup).
+ * PB4 - PIN4 (input pullup).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - PIN6 (input pullup).
+ * PB7 - PIN7 (input pullup).
+ * PB8 - PIN8 (input pullup).
+ * PB9 - PIN9 (input pullup).
+ * PB10 - PIN10 (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - PIN13 (input pullup).
+ * PB14 - PIN14 (input pullup).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_INPUT(GPIOB_PIN3) | \
+ PIN_MODE_INPUT(GPIOB_PIN4) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_INPUT(GPIOB_PIN6) | \
+ PIN_MODE_INPUT(GPIOB_PIN7) | \
+ PIN_MODE_INPUT(GPIOB_PIN8) | \
+ PIN_MODE_INPUT(GPIOB_PIN9) | \
+ PIN_MODE_INPUT(GPIOB_PIN10) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_PIN13) | \
+ PIN_MODE_INPUT(GPIOB_PIN14) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_PIN3) | \
+ PIN_ODR_HIGH(GPIOB_PIN4) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_PIN6) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_PIN8) | \
+ PIN_ODR_HIGH(GPIOB_PIN9) | \
+ PIN_ODR_HIGH(GPIOB_PIN10) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0U))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0U))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - PIN0 (input pullup).
+ * PC1 - PIN1 (input pullup).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PIN3 (input pullup).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - PIN5 (input pullup).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - PIN7 (input pullup).
+ * PC8 - PIN8 (input pullup).
+ * PC9 - PIN9 (input pullup).
+ * PC10 - PIN10 (input pullup).
+ * PC11 - PIN11 (input pullup).
+ * PC12 - PIN12 (input pullup).
+ * PC13 - BUTTON (input floating).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
+ PIN_MODE_INPUT(GPIOC_PIN1) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PIN3) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_INPUT(GPIOC_PIN5) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_INPUT(GPIOC_PIN7) | \
+ PIN_MODE_INPUT(GPIOC_PIN8) | \
+ PIN_MODE_INPUT(GPIOC_PIN9) | \
+ PIN_MODE_INPUT(GPIOC_PIN10) | \
+ PIN_MODE_INPUT(GPIOC_PIN11) | \
+ PIN_MODE_INPUT(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOC_BUTTON) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
+ PIN_ODR_HIGH(GPIOC_PIN1) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PIN3) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_PIN7) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_PIN10) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_PIN12) | \
+ PIN_ODR_HIGH(GPIOC_BUTTON) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN7, 0U))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - PIN4 (input pullup).
+ * PD5 - PIN5 (input pullup).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_INPUT(GPIOD_PIN4) | \
+ PIN_MODE_INPUT(GPIOD_PIN5) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - OSC_IN (input floating).
+ * PF1 - OSC_OUT (input floating).
+ * PF2 - PIN2 (input pullup).
+ * PF3 - PIN3 (input pullup).
+ * PF4 - PIN4 (input pullup).
+ * PF5 - PIN5 (input pullup).
+ * PF6 - PIN6 (input pullup).
+ * PF7 - PIN7 (input pullup).
+ * PF8 - PIN8 (input pullup).
+ * PF9 - PIN9 (input pullup).
+ * PF10 - PIN10 (input pullup).
+ * PF11 - PIN11 (input pullup).
+ * PF12 - PIN12 (input pullup).
+ * PF13 - PIN13 (input pullup).
+ * PF14 - PIN14 (input pullup).
+ * PF15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOF_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_OSC_IN) | \
+ PIN_OSPEED_HIGH(GPIOF_OSC_OUT) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOF_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \
+ PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0U))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0U))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/board.mk b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/board.mk new file mode 100644 index 0000000..a6f1329 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G071RB/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G071RB
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.chcfg b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.chcfg new file mode 100644 index 0000000..817dfc6 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.chcfg @@ -0,0 +1,669 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- STM32G0xx board Template --> +<board + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" + xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32g0xx_board.xsd"> + <configuration_settings> + <templates_path>resources/gencfg/processors/boards/stm32g0xx/templates</templates_path> + <output_path>..</output_path> + <hal_version>5.0.x</hal_version> + </configuration_settings> + <board_name>STMicroelectronics STM32 Nucleo64-G071RB</board_name> + <board_id>ST_NUCLEO64_G071RB</board_id> + <board_functions></board_functions> + <subtype>STM32G071xx</subtype> + <clocks HSEFrequency="8000000" HSEBypass="false" LSEFrequency="32768" + LSEBypass="false" LSEDrive="3 High Drive (default)" /> + <ports> + <GPIOA> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="STLK_RX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="1" /> + <pin3 + ID="STLK_TX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="1"/> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="LED_GREEN" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="SWDIO" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="0" /> + <pin14 + ID="SWCLK" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullDown" + Mode="Alternate" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + </GPIOA> + <GPIOB> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + </GPIOB> + <GPIOC> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="BUTTON" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin14 + ID="OSC32_IN" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin15 + ID="OSC32_OUT" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + </GPIOC> + <GPIOD> + <pin0 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOD> + <GPIOF> + <pin0 + ID="OSC_IN" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="OSC_OUT" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOF> + </ports> +</board> diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.fmpp b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.fmpp new file mode 100644 index 0000000..b24df35 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G071RB/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../tools/ftl/processors/boards/stm32g0xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +} diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/board.c b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/board.c new file mode 100644 index 0000000..568c450 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/board.c @@ -0,0 +1,266 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ gpio_setup_t PKData;
+#endif
+} gpio_config_t;
+
+/**
+ * @brief STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
+#endif
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetAHB2(STM32_GPIO_EN_MASK);
+ rccEnableAHB2(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+ gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+ gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
+ */
+void __early_init(void) {
+
+ stm32_gpio_init();
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @note You can add your board-specific code here.
+ */
+void boardInit(void) {
+
+}
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/board.h b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/board.h new file mode 100644 index 0000000..09924a6 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/board.h @@ -0,0 +1,1078 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * Setup for STMicroelectronics STM32 Nucleo64-G431RB board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_NUCLEO64_G431RB
+#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-G431RB"
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768U
+#endif
+
+#define STM32_LSEDRV (3U << 3U)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 24000000U
+#endif
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 300U
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32G431xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_PIN0 0U
+#define GPIOA_PIN1 1U
+#define GPIOA_STLINK_TX 2U
+#define GPIOA_STLINK_RX 3U
+#define GPIOA_PIN4 4U
+#define GPIOA_LED 5U
+#define GPIOA_LED_GREEN 5U
+#define GPIOA_PIN6 6U
+#define GPIOA_PIN7 7U
+#define GPIOA_PIN8 8U
+#define GPIOA_PIN9 9U
+#define GPIOA_PIN10 10U
+#define GPIOA_PIN11 11U
+#define GPIOA_PIN12 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_PIN15 15U
+
+#define GPIOB_PIN0 0U
+#define GPIOB_PIN1 1U
+#define GPIOB_BOOT1 2U
+#define GPIOB_TRACESWO 3U
+#define GPIOB_PIN4 4U
+#define GPIOB_PIN5 5U
+#define GPIOB_PIN6 6U
+#define GPIOB_PIN7 7U
+#define GPIOB_PIN8 8U
+#define GPIOB_PIN9 9U
+#define GPIOB_PIN10 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_PIN12 12U
+#define GPIOB_PIN13 13U
+#define GPIOB_PIN14 14U
+#define GPIOB_PIN15 15U
+
+#define GPIOC_PIN0 0U
+#define GPIOC_PIN1 1U
+#define GPIOC_PIN2 2U
+#define GPIOC_PIN3 3U
+#define GPIOC_PIN4 4U
+#define GPIOC_PIN5 5U
+#define GPIOC_PIN6 6U
+#define GPIOC_PIN7 7U
+#define GPIOC_PIN8 8U
+#define GPIOC_PIN9 9U
+#define GPIOC_PIN10 10U
+#define GPIOC_PIN11 11U
+#define GPIOC_PIN12 12U
+#define GPIOC_BUTTON 13U
+#define GPIOC_USER_BUTTON 13U
+#define GPIOC_OSC32_IN 14U
+#define GPIOC_OSC32_OUT 15U
+
+#define GPIOD_PIN0 0U
+#define GPIOD_PIN1 1U
+#define GPIOD_PIN2 2U
+#define GPIOD_PIN3 3U
+#define GPIOD_PIN4 4U
+#define GPIOD_PIN5 5U
+#define GPIOD_PIN6 6U
+#define GPIOD_PIN7 7U
+#define GPIOD_PIN8 8U
+#define GPIOD_PIN9 9U
+#define GPIOD_PIN10 10U
+#define GPIOD_PIN11 11U
+#define GPIOD_PIN12 12U
+#define GPIOD_PIN13 13U
+#define GPIOD_PIN14 14U
+#define GPIOD_PIN15 15U
+
+#define GPIOE_PIN0 0U
+#define GPIOE_PIN1 1U
+#define GPIOE_PIN2 2U
+#define GPIOE_PIN3 3U
+#define GPIOE_PIN4 4U
+#define GPIOE_PIN5 5U
+#define GPIOE_PIN6 6U
+#define GPIOE_PIN7 7U
+#define GPIOE_PIN8 8U
+#define GPIOE_PIN9 9U
+#define GPIOE_PIN10 10U
+#define GPIOE_PIN11 11U
+#define GPIOE_PIN12 12U
+#define GPIOE_PIN13 13U
+#define GPIOE_PIN14 14U
+#define GPIOE_PIN15 15U
+
+#define GPIOF_OSC_IN 0U
+#define GPIOF_OSC_OUT 1U
+#define GPIOF_PIN2 2U
+#define GPIOF_PIN3 3U
+#define GPIOF_PIN4 4U
+#define GPIOF_PIN5 5U
+#define GPIOF_PIN6 6U
+#define GPIOF_PIN7 7U
+#define GPIOF_PIN8 8U
+#define GPIOF_PIN9 9U
+#define GPIOF_PIN10 10U
+#define GPIOF_PIN11 11U
+#define GPIOF_PIN12 12U
+#define GPIOF_PIN13 13U
+#define GPIOF_PIN14 14U
+#define GPIOF_PIN15 15U
+
+#define GPIOG_PIN0 0U
+#define GPIOG_PIN1 1U
+#define GPIOG_PIN2 2U
+#define GPIOG_PIN3 3U
+#define GPIOG_PIN4 4U
+#define GPIOG_PIN5 5U
+#define GPIOG_PIN6 6U
+#define GPIOG_PIN7 7U
+#define GPIOG_PIN8 8U
+#define GPIOG_PIN9 9U
+#define GPIOG_PIN10 10U
+#define GPIOG_PIN11 11U
+#define GPIOG_PIN12 12U
+#define GPIOG_PIN13 13U
+#define GPIOG_PIN14 14U
+#define GPIOG_PIN15 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_STLINK_TX PAL_LINE(GPIOA, 2U)
+#define LINE_STLINK_RX PAL_LINE(GPIOA, 3U)
+#define LINE_LED PAL_LINE(GPIOA, 5U)
+#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U)
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
+#define LINE_BOOT1 PAL_LINE(GPIOB, 2U)
+#define LINE_TRACESWO PAL_LINE(GPIOB, 3U)
+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
+#define LINE_USER_BUTTON PAL_LINE(GPIOC, 13U)
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
+#define LINE_OSC_IN PAL_LINE(GPIOF, 0U)
+#define LINE_OSC_OUT PAL_LINE(GPIOF, 1U)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+#define PIN_LOCKR_DISABLED(n) (0U << (n))
+#define PIN_LOCKR_ENABLED(n) (1U << (n))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - PIN0 (analog).
+ * PA1 - PIN1 (analog).
+ * PA2 - STLINK_TX (alternate 12).
+ * PA3 - STLINK_RX (alternate 12).
+ * PA4 - PIN4 (analog).
+ * PA5 - LED LED_GREEN (output pushpull maximum).
+ * PA6 - PIN6 (analog).
+ * PA7 - PIN7 (analog).
+ * PA8 - PIN8 (analog).
+ * PA9 - PIN9 (analog).
+ * PA10 - PIN10 (analog).
+ * PA11 - PIN11 (analog).
+ * PA12 - PIN12 (analog).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (analog).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_PIN0) | \
+ PIN_MODE_ANALOG(GPIOA_PIN1) | \
+ PIN_MODE_ALTERNATE(GPIOA_STLINK_TX) | \
+ PIN_MODE_ALTERNATE(GPIOA_STLINK_RX) | \
+ PIN_MODE_ANALOG(GPIOA_PIN4) | \
+ PIN_MODE_OUTPUT(GPIOA_LED) | \
+ PIN_MODE_ANALOG(GPIOA_PIN6) | \
+ PIN_MODE_ANALOG(GPIOA_PIN7) | \
+ PIN_MODE_ANALOG(GPIOA_PIN8) | \
+ PIN_MODE_ANALOG(GPIOA_PIN9) | \
+ PIN_MODE_ANALOG(GPIOA_PIN10) | \
+ PIN_MODE_ANALOG(GPIOA_PIN11) | \
+ PIN_MODE_ANALOG(GPIOA_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_ANALOG(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_STLINK_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_STLINK_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_LED) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOA_STLINK_TX) | \
+ PIN_OSPEED_VERYLOW(GPIOA_STLINK_RX) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOA_LED) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOA_STLINK_TX) | \
+ PIN_PUPDR_FLOATING(GPIOA_STLINK_RX) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOA_LED) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_PIN0) | \
+ PIN_ODR_LOW(GPIOA_PIN1) | \
+ PIN_ODR_LOW(GPIOA_STLINK_TX) | \
+ PIN_ODR_LOW(GPIOA_STLINK_RX) | \
+ PIN_ODR_LOW(GPIOA_PIN4) | \
+ PIN_ODR_LOW(GPIOA_LED) | \
+ PIN_ODR_LOW(GPIOA_PIN6) | \
+ PIN_ODR_LOW(GPIOA_PIN7) | \
+ PIN_ODR_LOW(GPIOA_PIN8) | \
+ PIN_ODR_LOW(GPIOA_PIN9) | \
+ PIN_ODR_LOW(GPIOA_PIN10) | \
+ PIN_ODR_LOW(GPIOA_PIN11) | \
+ PIN_ODR_LOW(GPIOA_PIN12) | \
+ PIN_ODR_LOW(GPIOA_SWDIO) | \
+ PIN_ODR_LOW(GPIOA_SWCLK) | \
+ PIN_ODR_LOW(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOA_STLINK_TX, 12U) | \
+ PIN_AFIO_AF(GPIOA_STLINK_RX, 12U) | \
+ PIN_AFIO_AF(GPIOA_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOA_LED, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN7, 0U))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0U))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - PIN0 (analog).
+ * PB1 - PIN1 (analog).
+ * PB2 - BOOT1 (analog).
+ * PB3 - TRACESWO (alternate 0).
+ * PB4 - PIN4 (analog).
+ * PB5 - PIN5 (analog).
+ * PB6 - PIN6 (analog).
+ * PB7 - PIN7 (analog).
+ * PB8 - PIN8 (analog).
+ * PB9 - PIN9 (analog).
+ * PB10 - PIN10 (analog).
+ * PB11 - PIN11 (analog).
+ * PB12 - PIN12 (analog).
+ * PB13 - PIN13 (analog).
+ * PB14 - PIN14 (analog).
+ * PB15 - PIN15 (analog).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \
+ PIN_MODE_ANALOG(GPIOB_PIN1) | \
+ PIN_MODE_ANALOG(GPIOB_BOOT1) | \
+ PIN_MODE_ALTERNATE(GPIOB_TRACESWO) | \
+ PIN_MODE_ANALOG(GPIOB_PIN4) | \
+ PIN_MODE_ANALOG(GPIOB_PIN5) | \
+ PIN_MODE_ANALOG(GPIOB_PIN6) | \
+ PIN_MODE_ANALOG(GPIOB_PIN7) | \
+ PIN_MODE_ANALOG(GPIOB_PIN8) | \
+ PIN_MODE_ANALOG(GPIOB_PIN9) | \
+ PIN_MODE_ANALOG(GPIOB_PIN10) | \
+ PIN_MODE_ANALOG(GPIOB_PIN11) | \
+ PIN_MODE_ANALOG(GPIOB_PIN12) | \
+ PIN_MODE_ANALOG(GPIOB_PIN13) | \
+ PIN_MODE_ANALOG(GPIOB_PIN14) | \
+ PIN_MODE_ANALOG(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_TRACESWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOB_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOB_BOOT1) | \
+ PIN_OSPEED_HIGH(GPIOB_TRACESWO) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \
+ PIN_PUPDR_FLOATING(GPIOB_TRACESWO) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_PIN0) | \
+ PIN_ODR_LOW(GPIOB_PIN1) | \
+ PIN_ODR_LOW(GPIOB_BOOT1) | \
+ PIN_ODR_LOW(GPIOB_TRACESWO) | \
+ PIN_ODR_LOW(GPIOB_PIN4) | \
+ PIN_ODR_LOW(GPIOB_PIN5) | \
+ PIN_ODR_LOW(GPIOB_PIN6) | \
+ PIN_ODR_LOW(GPIOB_PIN7) | \
+ PIN_ODR_LOW(GPIOB_PIN8) | \
+ PIN_ODR_LOW(GPIOB_PIN9) | \
+ PIN_ODR_LOW(GPIOB_PIN10) | \
+ PIN_ODR_LOW(GPIOB_PIN11) | \
+ PIN_ODR_LOW(GPIOB_PIN12) | \
+ PIN_ODR_LOW(GPIOB_PIN13) | \
+ PIN_ODR_LOW(GPIOB_PIN14) | \
+ PIN_ODR_LOW(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOB_BOOT1, 0U) | \
+ PIN_AFIO_AF(GPIOB_TRACESWO, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0U))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0U))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - PIN0 (analog).
+ * PC1 - PIN1 (analog).
+ * PC2 - PIN2 (analog).
+ * PC3 - PIN3 (analog).
+ * PC4 - PIN4 (analog).
+ * PC5 - PIN5 (analog).
+ * PC6 - PIN6 (analog).
+ * PC7 - PIN7 (analog).
+ * PC8 - PIN8 (analog).
+ * PC9 - PIN9 (analog).
+ * PC10 - PIN10 (analog).
+ * PC11 - PIN11 (analog).
+ * PC12 - PIN12 (analog).
+ * PC13 - BUTTON USER_BUTTON (input floating).
+ * PC14 - OSC32_IN (analog).
+ * PC15 - OSC32_OUT (analog).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \
+ PIN_MODE_ANALOG(GPIOC_PIN1) | \
+ PIN_MODE_ANALOG(GPIOC_PIN2) | \
+ PIN_MODE_ANALOG(GPIOC_PIN3) | \
+ PIN_MODE_ANALOG(GPIOC_PIN4) | \
+ PIN_MODE_ANALOG(GPIOC_PIN5) | \
+ PIN_MODE_ANALOG(GPIOC_PIN6) | \
+ PIN_MODE_ANALOG(GPIOC_PIN7) | \
+ PIN_MODE_ANALOG(GPIOC_PIN8) | \
+ PIN_MODE_ANALOG(GPIOC_PIN9) | \
+ PIN_MODE_ANALOG(GPIOC_PIN10) | \
+ PIN_MODE_ANALOG(GPIOC_PIN11) | \
+ PIN_MODE_ANALOG(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
+ PIN_MODE_ANALOG(GPIOC_OSC32_IN) | \
+ PIN_MODE_ANALOG(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOC_BUTTON) | \
+ PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_LOW(GPIOC_PIN0) | \
+ PIN_ODR_LOW(GPIOC_PIN1) | \
+ PIN_ODR_LOW(GPIOC_PIN2) | \
+ PIN_ODR_LOW(GPIOC_PIN3) | \
+ PIN_ODR_LOW(GPIOC_PIN4) | \
+ PIN_ODR_LOW(GPIOC_PIN5) | \
+ PIN_ODR_LOW(GPIOC_PIN6) | \
+ PIN_ODR_LOW(GPIOC_PIN7) | \
+ PIN_ODR_LOW(GPIOC_PIN8) | \
+ PIN_ODR_LOW(GPIOC_PIN9) | \
+ PIN_ODR_LOW(GPIOC_PIN10) | \
+ PIN_ODR_LOW(GPIOC_PIN11) | \
+ PIN_ODR_LOW(GPIOC_PIN12) | \
+ PIN_ODR_LOW(GPIOC_BUTTON) | \
+ PIN_ODR_LOW(GPIOC_OSC32_IN) | \
+ PIN_ODR_LOW(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN7, 0U))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (analog).
+ * PD1 - PIN1 (analog).
+ * PD2 - PIN2 (analog).
+ * PD3 - PIN3 (analog).
+ * PD4 - PIN4 (analog).
+ * PD5 - PIN5 (analog).
+ * PD6 - PIN6 (analog).
+ * PD7 - PIN7 (analog).
+ * PD8 - PIN8 (analog).
+ * PD9 - PIN9 (analog).
+ * PD10 - PIN10 (analog).
+ * PD11 - PIN11 (analog).
+ * PD12 - PIN12 (analog).
+ * PD13 - PIN13 (analog).
+ * PD14 - PIN14 (analog).
+ * PD15 - PIN15 (analog).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \
+ PIN_MODE_ANALOG(GPIOD_PIN1) | \
+ PIN_MODE_ANALOG(GPIOD_PIN2) | \
+ PIN_MODE_ANALOG(GPIOD_PIN3) | \
+ PIN_MODE_ANALOG(GPIOD_PIN4) | \
+ PIN_MODE_ANALOG(GPIOD_PIN5) | \
+ PIN_MODE_ANALOG(GPIOD_PIN6) | \
+ PIN_MODE_ANALOG(GPIOD_PIN7) | \
+ PIN_MODE_ANALOG(GPIOD_PIN8) | \
+ PIN_MODE_ANALOG(GPIOD_PIN9) | \
+ PIN_MODE_ANALOG(GPIOD_PIN10) | \
+ PIN_MODE_ANALOG(GPIOD_PIN11) | \
+ PIN_MODE_ANALOG(GPIOD_PIN12) | \
+ PIN_MODE_ANALOG(GPIOD_PIN13) | \
+ PIN_MODE_ANALOG(GPIOD_PIN14) | \
+ PIN_MODE_ANALOG(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_LOW(GPIOD_PIN0) | \
+ PIN_ODR_LOW(GPIOD_PIN1) | \
+ PIN_ODR_LOW(GPIOD_PIN2) | \
+ PIN_ODR_LOW(GPIOD_PIN3) | \
+ PIN_ODR_LOW(GPIOD_PIN4) | \
+ PIN_ODR_LOW(GPIOD_PIN5) | \
+ PIN_ODR_LOW(GPIOD_PIN6) | \
+ PIN_ODR_LOW(GPIOD_PIN7) | \
+ PIN_ODR_LOW(GPIOD_PIN8) | \
+ PIN_ODR_LOW(GPIOD_PIN9) | \
+ PIN_ODR_LOW(GPIOD_PIN10) | \
+ PIN_ODR_LOW(GPIOD_PIN11) | \
+ PIN_ODR_LOW(GPIOD_PIN12) | \
+ PIN_ODR_LOW(GPIOD_PIN13) | \
+ PIN_ODR_LOW(GPIOD_PIN14) | \
+ PIN_ODR_LOW(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (analog).
+ * PE1 - PIN1 (analog).
+ * PE2 - PIN2 (analog).
+ * PE3 - PIN3 (analog).
+ * PE4 - PIN4 (analog).
+ * PE5 - PIN5 (analog).
+ * PE6 - PIN6 (analog).
+ * PE7 - PIN7 (analog).
+ * PE8 - PIN8 (analog).
+ * PE9 - PIN9 (analog).
+ * PE10 - PIN10 (analog).
+ * PE11 - PIN11 (analog).
+ * PE12 - PIN12 (analog).
+ * PE13 - PIN13 (analog).
+ * PE14 - PIN14 (analog).
+ * PE15 - PIN15 (analog).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \
+ PIN_MODE_ANALOG(GPIOE_PIN1) | \
+ PIN_MODE_ANALOG(GPIOE_PIN2) | \
+ PIN_MODE_ANALOG(GPIOE_PIN3) | \
+ PIN_MODE_ANALOG(GPIOE_PIN4) | \
+ PIN_MODE_ANALOG(GPIOE_PIN5) | \
+ PIN_MODE_ANALOG(GPIOE_PIN6) | \
+ PIN_MODE_ANALOG(GPIOE_PIN7) | \
+ PIN_MODE_ANALOG(GPIOE_PIN8) | \
+ PIN_MODE_ANALOG(GPIOE_PIN9) | \
+ PIN_MODE_ANALOG(GPIOE_PIN10) | \
+ PIN_MODE_ANALOG(GPIOE_PIN11) | \
+ PIN_MODE_ANALOG(GPIOE_PIN12) | \
+ PIN_MODE_ANALOG(GPIOE_PIN13) | \
+ PIN_MODE_ANALOG(GPIOE_PIN14) | \
+ PIN_MODE_ANALOG(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_LOW(GPIOE_PIN0) | \
+ PIN_ODR_LOW(GPIOE_PIN1) | \
+ PIN_ODR_LOW(GPIOE_PIN2) | \
+ PIN_ODR_LOW(GPIOE_PIN3) | \
+ PIN_ODR_LOW(GPIOE_PIN4) | \
+ PIN_ODR_LOW(GPIOE_PIN5) | \
+ PIN_ODR_LOW(GPIOE_PIN6) | \
+ PIN_ODR_LOW(GPIOE_PIN7) | \
+ PIN_ODR_LOW(GPIOE_PIN8) | \
+ PIN_ODR_LOW(GPIOE_PIN9) | \
+ PIN_ODR_LOW(GPIOE_PIN10) | \
+ PIN_ODR_LOW(GPIOE_PIN11) | \
+ PIN_ODR_LOW(GPIOE_PIN12) | \
+ PIN_ODR_LOW(GPIOE_PIN13) | \
+ PIN_ODR_LOW(GPIOE_PIN14) | \
+ PIN_ODR_LOW(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0U))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0U))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - OSC_IN (analog).
+ * PF1 - OSC_OUT (analog).
+ * PF2 - PIN2 (analog).
+ * PF3 - PIN3 (analog).
+ * PF4 - PIN4 (analog).
+ * PF5 - PIN5 (analog).
+ * PF6 - PIN6 (analog).
+ * PF7 - PIN7 (analog).
+ * PF8 - PIN8 (analog).
+ * PF9 - PIN9 (analog).
+ * PF10 - PIN10 (analog).
+ * PF11 - PIN11 (analog).
+ * PF12 - PIN12 (analog).
+ * PF13 - PIN13 (analog).
+ * PF14 - PIN14 (analog).
+ * PF15 - PIN15 (analog).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_OSC_IN) | \
+ PIN_MODE_ANALOG(GPIOF_OSC_OUT) | \
+ PIN_MODE_ANALOG(GPIOF_PIN2) | \
+ PIN_MODE_ANALOG(GPIOF_PIN3) | \
+ PIN_MODE_ANALOG(GPIOF_PIN4) | \
+ PIN_MODE_ANALOG(GPIOF_PIN5) | \
+ PIN_MODE_ANALOG(GPIOF_PIN6) | \
+ PIN_MODE_ANALOG(GPIOF_PIN7) | \
+ PIN_MODE_ANALOG(GPIOF_PIN8) | \
+ PIN_MODE_ANALOG(GPIOF_PIN9) | \
+ PIN_MODE_ANALOG(GPIOF_PIN10) | \
+ PIN_MODE_ANALOG(GPIOF_PIN11) | \
+ PIN_MODE_ANALOG(GPIOF_PIN12) | \
+ PIN_MODE_ANALOG(GPIOF_PIN13) | \
+ PIN_MODE_ANALOG(GPIOF_PIN14) | \
+ PIN_MODE_ANALOG(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_OSC_IN) | \
+ PIN_OSPEED_VERYLOW(GPIOF_OSC_OUT) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_LOW(GPIOF_OSC_IN) | \
+ PIN_ODR_LOW(GPIOF_OSC_OUT) | \
+ PIN_ODR_LOW(GPIOF_PIN2) | \
+ PIN_ODR_LOW(GPIOF_PIN3) | \
+ PIN_ODR_LOW(GPIOF_PIN4) | \
+ PIN_ODR_LOW(GPIOF_PIN5) | \
+ PIN_ODR_LOW(GPIOF_PIN6) | \
+ PIN_ODR_LOW(GPIOF_PIN7) | \
+ PIN_ODR_LOW(GPIOF_PIN8) | \
+ PIN_ODR_LOW(GPIOF_PIN9) | \
+ PIN_ODR_LOW(GPIOF_PIN10) | \
+ PIN_ODR_LOW(GPIOF_PIN11) | \
+ PIN_ODR_LOW(GPIOF_PIN12) | \
+ PIN_ODR_LOW(GPIOF_PIN13) | \
+ PIN_ODR_LOW(GPIOF_PIN14) | \
+ PIN_ODR_LOW(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \
+ PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0U))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0U))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (analog).
+ * PG1 - PIN1 (analog).
+ * PG2 - PIN2 (analog).
+ * PG3 - PIN3 (analog).
+ * PG4 - PIN4 (analog).
+ * PG5 - PIN5 (analog).
+ * PG6 - PIN6 (analog).
+ * PG7 - PIN7 (analog).
+ * PG8 - PIN8 (analog).
+ * PG9 - PIN9 (analog).
+ * PG10 - PIN10 (analog).
+ * PG11 - PIN11 (analog).
+ * PG12 - PIN12 (analog).
+ * PG13 - PIN13 (analog).
+ * PG14 - PIN14 (analog).
+ * PG15 - PIN15 (analog).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \
+ PIN_MODE_ANALOG(GPIOG_PIN1) | \
+ PIN_MODE_ANALOG(GPIOG_PIN2) | \
+ PIN_MODE_ANALOG(GPIOG_PIN3) | \
+ PIN_MODE_ANALOG(GPIOG_PIN4) | \
+ PIN_MODE_ANALOG(GPIOG_PIN5) | \
+ PIN_MODE_ANALOG(GPIOG_PIN6) | \
+ PIN_MODE_ANALOG(GPIOG_PIN7) | \
+ PIN_MODE_ANALOG(GPIOG_PIN8) | \
+ PIN_MODE_ANALOG(GPIOG_PIN9) | \
+ PIN_MODE_ANALOG(GPIOG_PIN10) | \
+ PIN_MODE_ANALOG(GPIOG_PIN11) | \
+ PIN_MODE_ANALOG(GPIOG_PIN12) | \
+ PIN_MODE_ANALOG(GPIOG_PIN13) | \
+ PIN_MODE_ANALOG(GPIOG_PIN14) | \
+ PIN_MODE_ANALOG(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_LOW(GPIOG_PIN0) | \
+ PIN_ODR_LOW(GPIOG_PIN1) | \
+ PIN_ODR_LOW(GPIOG_PIN2) | \
+ PIN_ODR_LOW(GPIOG_PIN3) | \
+ PIN_ODR_LOW(GPIOG_PIN4) | \
+ PIN_ODR_LOW(GPIOG_PIN5) | \
+ PIN_ODR_LOW(GPIOG_PIN6) | \
+ PIN_ODR_LOW(GPIOG_PIN7) | \
+ PIN_ODR_LOW(GPIOG_PIN8) | \
+ PIN_ODR_LOW(GPIOG_PIN9) | \
+ PIN_ODR_LOW(GPIOG_PIN10) | \
+ PIN_ODR_LOW(GPIOG_PIN11) | \
+ PIN_ODR_LOW(GPIOG_PIN12) | \
+ PIN_ODR_LOW(GPIOG_PIN13) | \
+ PIN_ODR_LOW(GPIOG_PIN14) | \
+ PIN_ODR_LOW(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN7, 0U))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0U))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/board.mk b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/board.mk new file mode 100644 index 0000000..b837794 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G431RB/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G431RB
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/cfg/board.chcfg b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/cfg/board.chcfg new file mode 100644 index 0000000..2f96088 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/cfg/board.chcfg @@ -0,0 +1,929 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32G4xx board Template -->
+<board
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32g4xx_board.xsd">
+ <configuration_settings>
+ <templates_path>resources/gencfg/processors/boards/stm32g4xx/templates</templates_path>
+ <output_path>..</output_path>
+ <hal_version>5.0.x</hal_version>
+ </configuration_settings>
+ <board_name>STMicroelectronics STM32 Nucleo64-G431RB</board_name>
+ <board_id>ST_NUCLEO64_G431RB</board_id>
+ <board_functions></board_functions>
+ <subtype>STM32G431xx</subtype>
+ <clocks HSEFrequency="24000000" HSEBypass="false" LSEFrequency="32768"
+ LSEBypass="false" VDD="300" LSEDrive="3 High Drive (default)" ></clocks>
+ <ports>
+ <GPIOA>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID="STLINK_TX"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Alternate"
+ Alternate="12" />
+ <pin3
+ ID="STLINK_RX"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Alternate"
+ Alternate="12" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID="LED LED_GREEN"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Output"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID="SWDIO"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Level="Low"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin14
+ ID="SWCLK"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullDown"
+ Level="Low"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOA>
+ <GPIOB>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID="BOOT1"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin3
+ ID="TRACESWO"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOB>
+ <GPIOC>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID="BUTTON USER_BUTTON"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID="OSC32_IN"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin15
+ ID="OSC32_OUT"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOC>
+ <GPIOD>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOD>
+ <GPIOE>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOE>
+ <GPIOF>
+ <pin0
+ ID="OSC_IN"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID="OSC_OUT"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOF>
+ <GPIOG>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOG>
+ </ports>
+</board>
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/cfg/board.fmpp b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/cfg/board.fmpp new file mode 100644 index 0000000..f48751c --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G431RB/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../tools/ftl/processors/boards/stm32g4xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +} diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/board.c b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/board.c new file mode 100644 index 0000000..568c450 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/board.c @@ -0,0 +1,266 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ gpio_setup_t PKData;
+#endif
+} gpio_config_t;
+
+/**
+ * @brief STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
+#endif
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetAHB2(STM32_GPIO_EN_MASK);
+ rccEnableAHB2(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+ gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+ gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
+ */
+void __early_init(void) {
+
+ stm32_gpio_init();
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @note You can add your board-specific code here.
+ */
+void boardInit(void) {
+
+}
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/board.h b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/board.h new file mode 100644 index 0000000..75c25f6 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/board.h @@ -0,0 +1,1078 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * Setup for STMicroelectronics STM32 Nucleo64-G474RE board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_NUCLEO64_G474RE
+#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-G474RE"
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768U
+#endif
+
+#define STM32_LSEDRV (3U << 3U)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 24000000U
+#endif
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 300U
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32G474xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_PIN0 0U
+#define GPIOA_PIN1 1U
+#define GPIOA_STLINK_TX 2U
+#define GPIOA_STLINK_RX 3U
+#define GPIOA_PIN4 4U
+#define GPIOA_LED 5U
+#define GPIOA_LED_GREEN 5U
+#define GPIOA_PIN6 6U
+#define GPIOA_PIN7 7U
+#define GPIOA_PIN8 8U
+#define GPIOA_PIN9 9U
+#define GPIOA_PIN10 10U
+#define GPIOA_PIN11 11U
+#define GPIOA_PIN12 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_PIN15 15U
+
+#define GPIOB_PIN0 0U
+#define GPIOB_PIN1 1U
+#define GPIOB_BOOT1 2U
+#define GPIOB_TRACESWO 3U
+#define GPIOB_PIN4 4U
+#define GPIOB_PIN5 5U
+#define GPIOB_PIN6 6U
+#define GPIOB_PIN7 7U
+#define GPIOB_PIN8 8U
+#define GPIOB_PIN9 9U
+#define GPIOB_PIN10 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_PIN12 12U
+#define GPIOB_PIN13 13U
+#define GPIOB_PIN14 14U
+#define GPIOB_PIN15 15U
+
+#define GPIOC_PIN0 0U
+#define GPIOC_PIN1 1U
+#define GPIOC_PIN2 2U
+#define GPIOC_PIN3 3U
+#define GPIOC_PIN4 4U
+#define GPIOC_PIN5 5U
+#define GPIOC_PIN6 6U
+#define GPIOC_PIN7 7U
+#define GPIOC_PIN8 8U
+#define GPIOC_PIN9 9U
+#define GPIOC_PIN10 10U
+#define GPIOC_PIN11 11U
+#define GPIOC_PIN12 12U
+#define GPIOC_BUTTON 13U
+#define GPIOC_USER_BUTTON 13U
+#define GPIOC_OSC32_IN 14U
+#define GPIOC_OSC32_OUT 15U
+
+#define GPIOD_PIN0 0U
+#define GPIOD_PIN1 1U
+#define GPIOD_PIN2 2U
+#define GPIOD_PIN3 3U
+#define GPIOD_PIN4 4U
+#define GPIOD_PIN5 5U
+#define GPIOD_PIN6 6U
+#define GPIOD_PIN7 7U
+#define GPIOD_PIN8 8U
+#define GPIOD_PIN9 9U
+#define GPIOD_PIN10 10U
+#define GPIOD_PIN11 11U
+#define GPIOD_PIN12 12U
+#define GPIOD_PIN13 13U
+#define GPIOD_PIN14 14U
+#define GPIOD_PIN15 15U
+
+#define GPIOE_PIN0 0U
+#define GPIOE_PIN1 1U
+#define GPIOE_PIN2 2U
+#define GPIOE_PIN3 3U
+#define GPIOE_PIN4 4U
+#define GPIOE_PIN5 5U
+#define GPIOE_PIN6 6U
+#define GPIOE_PIN7 7U
+#define GPIOE_PIN8 8U
+#define GPIOE_PIN9 9U
+#define GPIOE_PIN10 10U
+#define GPIOE_PIN11 11U
+#define GPIOE_PIN12 12U
+#define GPIOE_PIN13 13U
+#define GPIOE_PIN14 14U
+#define GPIOE_PIN15 15U
+
+#define GPIOF_OSC_IN 0U
+#define GPIOF_OSC_OUT 1U
+#define GPIOF_PIN2 2U
+#define GPIOF_PIN3 3U
+#define GPIOF_PIN4 4U
+#define GPIOF_PIN5 5U
+#define GPIOF_PIN6 6U
+#define GPIOF_PIN7 7U
+#define GPIOF_PIN8 8U
+#define GPIOF_PIN9 9U
+#define GPIOF_PIN10 10U
+#define GPIOF_PIN11 11U
+#define GPIOF_PIN12 12U
+#define GPIOF_PIN13 13U
+#define GPIOF_PIN14 14U
+#define GPIOF_PIN15 15U
+
+#define GPIOG_PIN0 0U
+#define GPIOG_PIN1 1U
+#define GPIOG_PIN2 2U
+#define GPIOG_PIN3 3U
+#define GPIOG_PIN4 4U
+#define GPIOG_PIN5 5U
+#define GPIOG_PIN6 6U
+#define GPIOG_PIN7 7U
+#define GPIOG_PIN8 8U
+#define GPIOG_PIN9 9U
+#define GPIOG_PIN10 10U
+#define GPIOG_PIN11 11U
+#define GPIOG_PIN12 12U
+#define GPIOG_PIN13 13U
+#define GPIOG_PIN14 14U
+#define GPIOG_PIN15 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_STLINK_TX PAL_LINE(GPIOA, 2U)
+#define LINE_STLINK_RX PAL_LINE(GPIOA, 3U)
+#define LINE_LED PAL_LINE(GPIOA, 5U)
+#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U)
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
+#define LINE_BOOT1 PAL_LINE(GPIOB, 2U)
+#define LINE_TRACESWO PAL_LINE(GPIOB, 3U)
+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
+#define LINE_USER_BUTTON PAL_LINE(GPIOC, 13U)
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
+#define LINE_OSC_IN PAL_LINE(GPIOF, 0U)
+#define LINE_OSC_OUT PAL_LINE(GPIOF, 1U)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+#define PIN_LOCKR_DISABLED(n) (0U << (n))
+#define PIN_LOCKR_ENABLED(n) (1U << (n))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - PIN0 (analog).
+ * PA1 - PIN1 (analog).
+ * PA2 - STLINK_TX (alternate 12).
+ * PA3 - STLINK_RX (alternate 12).
+ * PA4 - PIN4 (analog).
+ * PA5 - LED LED_GREEN (output pushpull maximum).
+ * PA6 - PIN6 (analog).
+ * PA7 - PIN7 (analog).
+ * PA8 - PIN8 (analog).
+ * PA9 - PIN9 (analog).
+ * PA10 - PIN10 (analog).
+ * PA11 - PIN11 (analog).
+ * PA12 - PIN12 (analog).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (analog).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_PIN0) | \
+ PIN_MODE_ANALOG(GPIOA_PIN1) | \
+ PIN_MODE_ALTERNATE(GPIOA_STLINK_TX) | \
+ PIN_MODE_ALTERNATE(GPIOA_STLINK_RX) | \
+ PIN_MODE_ANALOG(GPIOA_PIN4) | \
+ PIN_MODE_OUTPUT(GPIOA_LED) | \
+ PIN_MODE_ANALOG(GPIOA_PIN6) | \
+ PIN_MODE_ANALOG(GPIOA_PIN7) | \
+ PIN_MODE_ANALOG(GPIOA_PIN8) | \
+ PIN_MODE_ANALOG(GPIOA_PIN9) | \
+ PIN_MODE_ANALOG(GPIOA_PIN10) | \
+ PIN_MODE_ANALOG(GPIOA_PIN11) | \
+ PIN_MODE_ANALOG(GPIOA_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_ANALOG(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_STLINK_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_STLINK_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_LED) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOA_STLINK_TX) | \
+ PIN_OSPEED_VERYLOW(GPIOA_STLINK_RX) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOA_LED) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOA_STLINK_TX) | \
+ PIN_PUPDR_FLOATING(GPIOA_STLINK_RX) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOA_LED) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_PIN0) | \
+ PIN_ODR_LOW(GPIOA_PIN1) | \
+ PIN_ODR_LOW(GPIOA_STLINK_TX) | \
+ PIN_ODR_LOW(GPIOA_STLINK_RX) | \
+ PIN_ODR_LOW(GPIOA_PIN4) | \
+ PIN_ODR_LOW(GPIOA_LED) | \
+ PIN_ODR_LOW(GPIOA_PIN6) | \
+ PIN_ODR_LOW(GPIOA_PIN7) | \
+ PIN_ODR_LOW(GPIOA_PIN8) | \
+ PIN_ODR_LOW(GPIOA_PIN9) | \
+ PIN_ODR_LOW(GPIOA_PIN10) | \
+ PIN_ODR_LOW(GPIOA_PIN11) | \
+ PIN_ODR_LOW(GPIOA_PIN12) | \
+ PIN_ODR_LOW(GPIOA_SWDIO) | \
+ PIN_ODR_LOW(GPIOA_SWCLK) | \
+ PIN_ODR_LOW(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOA_STLINK_TX, 12U) | \
+ PIN_AFIO_AF(GPIOA_STLINK_RX, 12U) | \
+ PIN_AFIO_AF(GPIOA_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOA_LED, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN7, 0U))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0U))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - PIN0 (analog).
+ * PB1 - PIN1 (analog).
+ * PB2 - BOOT1 (analog).
+ * PB3 - TRACESWO (alternate 0).
+ * PB4 - PIN4 (analog).
+ * PB5 - PIN5 (analog).
+ * PB6 - PIN6 (analog).
+ * PB7 - PIN7 (analog).
+ * PB8 - PIN8 (analog).
+ * PB9 - PIN9 (analog).
+ * PB10 - PIN10 (analog).
+ * PB11 - PIN11 (analog).
+ * PB12 - PIN12 (analog).
+ * PB13 - PIN13 (analog).
+ * PB14 - PIN14 (analog).
+ * PB15 - PIN15 (analog).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \
+ PIN_MODE_ANALOG(GPIOB_PIN1) | \
+ PIN_MODE_ANALOG(GPIOB_BOOT1) | \
+ PIN_MODE_ALTERNATE(GPIOB_TRACESWO) | \
+ PIN_MODE_ANALOG(GPIOB_PIN4) | \
+ PIN_MODE_ANALOG(GPIOB_PIN5) | \
+ PIN_MODE_ANALOG(GPIOB_PIN6) | \
+ PIN_MODE_ANALOG(GPIOB_PIN7) | \
+ PIN_MODE_ANALOG(GPIOB_PIN8) | \
+ PIN_MODE_ANALOG(GPIOB_PIN9) | \
+ PIN_MODE_ANALOG(GPIOB_PIN10) | \
+ PIN_MODE_ANALOG(GPIOB_PIN11) | \
+ PIN_MODE_ANALOG(GPIOB_PIN12) | \
+ PIN_MODE_ANALOG(GPIOB_PIN13) | \
+ PIN_MODE_ANALOG(GPIOB_PIN14) | \
+ PIN_MODE_ANALOG(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_TRACESWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOB_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOB_BOOT1) | \
+ PIN_OSPEED_HIGH(GPIOB_TRACESWO) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \
+ PIN_PUPDR_FLOATING(GPIOB_TRACESWO) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_PIN0) | \
+ PIN_ODR_LOW(GPIOB_PIN1) | \
+ PIN_ODR_LOW(GPIOB_BOOT1) | \
+ PIN_ODR_LOW(GPIOB_TRACESWO) | \
+ PIN_ODR_LOW(GPIOB_PIN4) | \
+ PIN_ODR_LOW(GPIOB_PIN5) | \
+ PIN_ODR_LOW(GPIOB_PIN6) | \
+ PIN_ODR_LOW(GPIOB_PIN7) | \
+ PIN_ODR_LOW(GPIOB_PIN8) | \
+ PIN_ODR_LOW(GPIOB_PIN9) | \
+ PIN_ODR_LOW(GPIOB_PIN10) | \
+ PIN_ODR_LOW(GPIOB_PIN11) | \
+ PIN_ODR_LOW(GPIOB_PIN12) | \
+ PIN_ODR_LOW(GPIOB_PIN13) | \
+ PIN_ODR_LOW(GPIOB_PIN14) | \
+ PIN_ODR_LOW(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOB_BOOT1, 0U) | \
+ PIN_AFIO_AF(GPIOB_TRACESWO, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0U))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0U))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - PIN0 (analog).
+ * PC1 - PIN1 (analog).
+ * PC2 - PIN2 (analog).
+ * PC3 - PIN3 (analog).
+ * PC4 - PIN4 (analog).
+ * PC5 - PIN5 (analog).
+ * PC6 - PIN6 (analog).
+ * PC7 - PIN7 (analog).
+ * PC8 - PIN8 (analog).
+ * PC9 - PIN9 (analog).
+ * PC10 - PIN10 (analog).
+ * PC11 - PIN11 (analog).
+ * PC12 - PIN12 (analog).
+ * PC13 - BUTTON USER_BUTTON (input floating).
+ * PC14 - OSC32_IN (analog).
+ * PC15 - OSC32_OUT (analog).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \
+ PIN_MODE_ANALOG(GPIOC_PIN1) | \
+ PIN_MODE_ANALOG(GPIOC_PIN2) | \
+ PIN_MODE_ANALOG(GPIOC_PIN3) | \
+ PIN_MODE_ANALOG(GPIOC_PIN4) | \
+ PIN_MODE_ANALOG(GPIOC_PIN5) | \
+ PIN_MODE_ANALOG(GPIOC_PIN6) | \
+ PIN_MODE_ANALOG(GPIOC_PIN7) | \
+ PIN_MODE_ANALOG(GPIOC_PIN8) | \
+ PIN_MODE_ANALOG(GPIOC_PIN9) | \
+ PIN_MODE_ANALOG(GPIOC_PIN10) | \
+ PIN_MODE_ANALOG(GPIOC_PIN11) | \
+ PIN_MODE_ANALOG(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
+ PIN_MODE_ANALOG(GPIOC_OSC32_IN) | \
+ PIN_MODE_ANALOG(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOC_BUTTON) | \
+ PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_LOW(GPIOC_PIN0) | \
+ PIN_ODR_LOW(GPIOC_PIN1) | \
+ PIN_ODR_LOW(GPIOC_PIN2) | \
+ PIN_ODR_LOW(GPIOC_PIN3) | \
+ PIN_ODR_LOW(GPIOC_PIN4) | \
+ PIN_ODR_LOW(GPIOC_PIN5) | \
+ PIN_ODR_LOW(GPIOC_PIN6) | \
+ PIN_ODR_LOW(GPIOC_PIN7) | \
+ PIN_ODR_LOW(GPIOC_PIN8) | \
+ PIN_ODR_LOW(GPIOC_PIN9) | \
+ PIN_ODR_LOW(GPIOC_PIN10) | \
+ PIN_ODR_LOW(GPIOC_PIN11) | \
+ PIN_ODR_LOW(GPIOC_PIN12) | \
+ PIN_ODR_LOW(GPIOC_BUTTON) | \
+ PIN_ODR_LOW(GPIOC_OSC32_IN) | \
+ PIN_ODR_LOW(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN7, 0U))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (analog).
+ * PD1 - PIN1 (analog).
+ * PD2 - PIN2 (analog).
+ * PD3 - PIN3 (analog).
+ * PD4 - PIN4 (analog).
+ * PD5 - PIN5 (analog).
+ * PD6 - PIN6 (analog).
+ * PD7 - PIN7 (analog).
+ * PD8 - PIN8 (analog).
+ * PD9 - PIN9 (analog).
+ * PD10 - PIN10 (analog).
+ * PD11 - PIN11 (analog).
+ * PD12 - PIN12 (analog).
+ * PD13 - PIN13 (analog).
+ * PD14 - PIN14 (analog).
+ * PD15 - PIN15 (analog).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \
+ PIN_MODE_ANALOG(GPIOD_PIN1) | \
+ PIN_MODE_ANALOG(GPIOD_PIN2) | \
+ PIN_MODE_ANALOG(GPIOD_PIN3) | \
+ PIN_MODE_ANALOG(GPIOD_PIN4) | \
+ PIN_MODE_ANALOG(GPIOD_PIN5) | \
+ PIN_MODE_ANALOG(GPIOD_PIN6) | \
+ PIN_MODE_ANALOG(GPIOD_PIN7) | \
+ PIN_MODE_ANALOG(GPIOD_PIN8) | \
+ PIN_MODE_ANALOG(GPIOD_PIN9) | \
+ PIN_MODE_ANALOG(GPIOD_PIN10) | \
+ PIN_MODE_ANALOG(GPIOD_PIN11) | \
+ PIN_MODE_ANALOG(GPIOD_PIN12) | \
+ PIN_MODE_ANALOG(GPIOD_PIN13) | \
+ PIN_MODE_ANALOG(GPIOD_PIN14) | \
+ PIN_MODE_ANALOG(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_LOW(GPIOD_PIN0) | \
+ PIN_ODR_LOW(GPIOD_PIN1) | \
+ PIN_ODR_LOW(GPIOD_PIN2) | \
+ PIN_ODR_LOW(GPIOD_PIN3) | \
+ PIN_ODR_LOW(GPIOD_PIN4) | \
+ PIN_ODR_LOW(GPIOD_PIN5) | \
+ PIN_ODR_LOW(GPIOD_PIN6) | \
+ PIN_ODR_LOW(GPIOD_PIN7) | \
+ PIN_ODR_LOW(GPIOD_PIN8) | \
+ PIN_ODR_LOW(GPIOD_PIN9) | \
+ PIN_ODR_LOW(GPIOD_PIN10) | \
+ PIN_ODR_LOW(GPIOD_PIN11) | \
+ PIN_ODR_LOW(GPIOD_PIN12) | \
+ PIN_ODR_LOW(GPIOD_PIN13) | \
+ PIN_ODR_LOW(GPIOD_PIN14) | \
+ PIN_ODR_LOW(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (analog).
+ * PE1 - PIN1 (analog).
+ * PE2 - PIN2 (analog).
+ * PE3 - PIN3 (analog).
+ * PE4 - PIN4 (analog).
+ * PE5 - PIN5 (analog).
+ * PE6 - PIN6 (analog).
+ * PE7 - PIN7 (analog).
+ * PE8 - PIN8 (analog).
+ * PE9 - PIN9 (analog).
+ * PE10 - PIN10 (analog).
+ * PE11 - PIN11 (analog).
+ * PE12 - PIN12 (analog).
+ * PE13 - PIN13 (analog).
+ * PE14 - PIN14 (analog).
+ * PE15 - PIN15 (analog).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \
+ PIN_MODE_ANALOG(GPIOE_PIN1) | \
+ PIN_MODE_ANALOG(GPIOE_PIN2) | \
+ PIN_MODE_ANALOG(GPIOE_PIN3) | \
+ PIN_MODE_ANALOG(GPIOE_PIN4) | \
+ PIN_MODE_ANALOG(GPIOE_PIN5) | \
+ PIN_MODE_ANALOG(GPIOE_PIN6) | \
+ PIN_MODE_ANALOG(GPIOE_PIN7) | \
+ PIN_MODE_ANALOG(GPIOE_PIN8) | \
+ PIN_MODE_ANALOG(GPIOE_PIN9) | \
+ PIN_MODE_ANALOG(GPIOE_PIN10) | \
+ PIN_MODE_ANALOG(GPIOE_PIN11) | \
+ PIN_MODE_ANALOG(GPIOE_PIN12) | \
+ PIN_MODE_ANALOG(GPIOE_PIN13) | \
+ PIN_MODE_ANALOG(GPIOE_PIN14) | \
+ PIN_MODE_ANALOG(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_LOW(GPIOE_PIN0) | \
+ PIN_ODR_LOW(GPIOE_PIN1) | \
+ PIN_ODR_LOW(GPIOE_PIN2) | \
+ PIN_ODR_LOW(GPIOE_PIN3) | \
+ PIN_ODR_LOW(GPIOE_PIN4) | \
+ PIN_ODR_LOW(GPIOE_PIN5) | \
+ PIN_ODR_LOW(GPIOE_PIN6) | \
+ PIN_ODR_LOW(GPIOE_PIN7) | \
+ PIN_ODR_LOW(GPIOE_PIN8) | \
+ PIN_ODR_LOW(GPIOE_PIN9) | \
+ PIN_ODR_LOW(GPIOE_PIN10) | \
+ PIN_ODR_LOW(GPIOE_PIN11) | \
+ PIN_ODR_LOW(GPIOE_PIN12) | \
+ PIN_ODR_LOW(GPIOE_PIN13) | \
+ PIN_ODR_LOW(GPIOE_PIN14) | \
+ PIN_ODR_LOW(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0U))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0U))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - OSC_IN (analog).
+ * PF1 - OSC_OUT (analog).
+ * PF2 - PIN2 (analog).
+ * PF3 - PIN3 (analog).
+ * PF4 - PIN4 (analog).
+ * PF5 - PIN5 (analog).
+ * PF6 - PIN6 (analog).
+ * PF7 - PIN7 (analog).
+ * PF8 - PIN8 (analog).
+ * PF9 - PIN9 (analog).
+ * PF10 - PIN10 (analog).
+ * PF11 - PIN11 (analog).
+ * PF12 - PIN12 (analog).
+ * PF13 - PIN13 (analog).
+ * PF14 - PIN14 (analog).
+ * PF15 - PIN15 (analog).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_OSC_IN) | \
+ PIN_MODE_ANALOG(GPIOF_OSC_OUT) | \
+ PIN_MODE_ANALOG(GPIOF_PIN2) | \
+ PIN_MODE_ANALOG(GPIOF_PIN3) | \
+ PIN_MODE_ANALOG(GPIOF_PIN4) | \
+ PIN_MODE_ANALOG(GPIOF_PIN5) | \
+ PIN_MODE_ANALOG(GPIOF_PIN6) | \
+ PIN_MODE_ANALOG(GPIOF_PIN7) | \
+ PIN_MODE_ANALOG(GPIOF_PIN8) | \
+ PIN_MODE_ANALOG(GPIOF_PIN9) | \
+ PIN_MODE_ANALOG(GPIOF_PIN10) | \
+ PIN_MODE_ANALOG(GPIOF_PIN11) | \
+ PIN_MODE_ANALOG(GPIOF_PIN12) | \
+ PIN_MODE_ANALOG(GPIOF_PIN13) | \
+ PIN_MODE_ANALOG(GPIOF_PIN14) | \
+ PIN_MODE_ANALOG(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_OSC_IN) | \
+ PIN_OSPEED_VERYLOW(GPIOF_OSC_OUT) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_LOW(GPIOF_OSC_IN) | \
+ PIN_ODR_LOW(GPIOF_OSC_OUT) | \
+ PIN_ODR_LOW(GPIOF_PIN2) | \
+ PIN_ODR_LOW(GPIOF_PIN3) | \
+ PIN_ODR_LOW(GPIOF_PIN4) | \
+ PIN_ODR_LOW(GPIOF_PIN5) | \
+ PIN_ODR_LOW(GPIOF_PIN6) | \
+ PIN_ODR_LOW(GPIOF_PIN7) | \
+ PIN_ODR_LOW(GPIOF_PIN8) | \
+ PIN_ODR_LOW(GPIOF_PIN9) | \
+ PIN_ODR_LOW(GPIOF_PIN10) | \
+ PIN_ODR_LOW(GPIOF_PIN11) | \
+ PIN_ODR_LOW(GPIOF_PIN12) | \
+ PIN_ODR_LOW(GPIOF_PIN13) | \
+ PIN_ODR_LOW(GPIOF_PIN14) | \
+ PIN_ODR_LOW(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | \
+ PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0U))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0U))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (analog).
+ * PG1 - PIN1 (analog).
+ * PG2 - PIN2 (analog).
+ * PG3 - PIN3 (analog).
+ * PG4 - PIN4 (analog).
+ * PG5 - PIN5 (analog).
+ * PG6 - PIN6 (analog).
+ * PG7 - PIN7 (analog).
+ * PG8 - PIN8 (analog).
+ * PG9 - PIN9 (analog).
+ * PG10 - PIN10 (analog).
+ * PG11 - PIN11 (analog).
+ * PG12 - PIN12 (analog).
+ * PG13 - PIN13 (analog).
+ * PG14 - PIN14 (analog).
+ * PG15 - PIN15 (analog).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \
+ PIN_MODE_ANALOG(GPIOG_PIN1) | \
+ PIN_MODE_ANALOG(GPIOG_PIN2) | \
+ PIN_MODE_ANALOG(GPIOG_PIN3) | \
+ PIN_MODE_ANALOG(GPIOG_PIN4) | \
+ PIN_MODE_ANALOG(GPIOG_PIN5) | \
+ PIN_MODE_ANALOG(GPIOG_PIN6) | \
+ PIN_MODE_ANALOG(GPIOG_PIN7) | \
+ PIN_MODE_ANALOG(GPIOG_PIN8) | \
+ PIN_MODE_ANALOG(GPIOG_PIN9) | \
+ PIN_MODE_ANALOG(GPIOG_PIN10) | \
+ PIN_MODE_ANALOG(GPIOG_PIN11) | \
+ PIN_MODE_ANALOG(GPIOG_PIN12) | \
+ PIN_MODE_ANALOG(GPIOG_PIN13) | \
+ PIN_MODE_ANALOG(GPIOG_PIN14) | \
+ PIN_MODE_ANALOG(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_LOW(GPIOG_PIN0) | \
+ PIN_ODR_LOW(GPIOG_PIN1) | \
+ PIN_ODR_LOW(GPIOG_PIN2) | \
+ PIN_ODR_LOW(GPIOG_PIN3) | \
+ PIN_ODR_LOW(GPIOG_PIN4) | \
+ PIN_ODR_LOW(GPIOG_PIN5) | \
+ PIN_ODR_LOW(GPIOG_PIN6) | \
+ PIN_ODR_LOW(GPIOG_PIN7) | \
+ PIN_ODR_LOW(GPIOG_PIN8) | \
+ PIN_ODR_LOW(GPIOG_PIN9) | \
+ PIN_ODR_LOW(GPIOG_PIN10) | \
+ PIN_ODR_LOW(GPIOG_PIN11) | \
+ PIN_ODR_LOW(GPIOG_PIN12) | \
+ PIN_ODR_LOW(GPIOG_PIN13) | \
+ PIN_ODR_LOW(GPIOG_PIN14) | \
+ PIN_ODR_LOW(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN7, 0U))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0U))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/board.mk b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/board.mk new file mode 100644 index 0000000..61c8e1a --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G474RE/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G474RE
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/cfg/board.chcfg b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/cfg/board.chcfg new file mode 100644 index 0000000..3e9fdea --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/cfg/board.chcfg @@ -0,0 +1,929 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32G4xx board Template -->
+<board
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32g4xx_board.xsd">
+ <configuration_settings>
+ <templates_path>resources/gencfg/processors/boards/stm32g4xx/templates</templates_path>
+ <output_path>..</output_path>
+ <hal_version>5.0.x</hal_version>
+ </configuration_settings>
+ <board_name>STMicroelectronics STM32 Nucleo64-G474RE</board_name>
+ <board_id>ST_NUCLEO64_G474RE</board_id>
+ <board_functions></board_functions>
+ <subtype>STM32G474xx</subtype>
+ <clocks HSEFrequency="24000000" HSEBypass="false" LSEFrequency="32768"
+ LSEBypass="false" VDD="300" LSEDrive="3 High Drive (default)" ></clocks>
+ <ports>
+ <GPIOA>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID="STLINK_TX"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Alternate"
+ Alternate="12" />
+ <pin3
+ ID="STLINK_RX"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Alternate"
+ Alternate="12" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID="LED LED_GREEN"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Output"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID="SWDIO"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Level="Low"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin14
+ ID="SWCLK"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullDown"
+ Level="Low"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOA>
+ <GPIOB>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID="BOOT1"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin3
+ ID="TRACESWO"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOB>
+ <GPIOC>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID="BUTTON USER_BUTTON"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID="OSC32_IN"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin15
+ ID="OSC32_OUT"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOC>
+ <GPIOD>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOD>
+ <GPIOE>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOE>
+ <GPIOF>
+ <pin0
+ ID="OSC_IN"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID="OSC_OUT"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOF>
+ <GPIOG>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Analog"
+ Alternate="0" />
+ </GPIOG>
+ </ports>
+</board>
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/cfg/board.fmpp b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/cfg/board.fmpp new file mode 100644 index 0000000..f48751c --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_G474RE/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../tools/ftl/processors/boards/stm32g4xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +} diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/board.c b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/board.c new file mode 100644 index 0000000..fbea4c4 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/board.c @@ -0,0 +1,266 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ gpio_setup_t PKData;
+#endif
+} gpio_config_t;
+
+/**
+ * @brief STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
+#endif
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetIOP(STM32_GPIO_EN_MASK);
+ rccEnableIOP(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+ gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+ gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
+ */
+void __early_init(void) {
+
+ stm32_gpio_init();
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @note You can add your board-specific code here.
+ */
+void boardInit(void) {
+
+}
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/board.h b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/board.h new file mode 100644 index 0000000..dc3fe15 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/board.h @@ -0,0 +1,837 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * Setup for STMicroelectronics STM32 Nucleo64-L053R8 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_NUCLEO64_L053R8
+#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-L053R8"
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768U
+#endif
+
+#define STM32_LSEDRV (3U << 11U)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000U
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32L053xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_ARD_A0 0U
+#define GPIOA_ACD1_IN0 0U
+#define GPIOA_ARD_A1 1U
+#define GPIOA_ACD1_IN1 1U
+#define GPIOA_ARD_D1 2U
+#define GPIOA_USART2_TX 2U
+#define GPIOA_ARD_D0 3U
+#define GPIOA_USART2_RX 3U
+#define GPIOA_ARD_A2 4U
+#define GPIOA_ACD1_IN4 4U
+#define GPIOA_LED_GREEN 5U
+#define GPIOA_ARD_D13 5U
+#define GPIOA_ARD_D12 6U
+#define GPIOA_ARD_D11 7U
+#define GPIOA_ARD_D7 8U
+#define GPIOA_ARD_D8 9U
+#define GPIOA_ARD_D2 10U
+#define GPIOA_PIN11 11U
+#define GPIOA_PIN12 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_PIN15 15U
+
+#define GPIOB_ARD_A3 0U
+#define GPIOB_ACD1_IN8 0U
+#define GPIOB_PIN1 1U
+#define GPIOB_PIN2 2U
+#define GPIOB_SWO 3U
+#define GPIOB_ARD_D3 3U
+#define GPIOB_ARD_D5 4U
+#define GPIOB_ARD_D4 5U
+#define GPIOB_ARD_D10 6U
+#define GPIOB_PIN7 7U
+#define GPIOB_ARD_D15 8U
+#define GPIOB_ARD_D14 9U
+#define GPIOB_ARD_D6 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_PIN12 12U
+#define GPIOB_PIN13 13U
+#define GPIOB_PIN14 14U
+#define GPIOB_PIN15 15U
+
+#define GPIOC_ARD_A5 0U
+#define GPIOC_ACD1_IN10 0U
+#define GPIOC_ARD_A4 1U
+#define GPIOC_ACD1_IN11 1U
+#define GPIOC_PIN2 2U
+#define GPIOC_PIN3 3U
+#define GPIOC_PIN4 4U
+#define GPIOC_PIN5 5U
+#define GPIOC_PIN6 6U
+#define GPIOC_ARD_D9 7U
+#define GPIOC_PIN8 8U
+#define GPIOC_PIN9 9U
+#define GPIOC_PIN10 10U
+#define GPIOC_PIN11 11U
+#define GPIOC_PIN12 12U
+#define GPIOC_BUTTON 13U
+#define GPIOC_OSC32_IN 14U
+#define GPIOC_OSC32_OUT 15U
+
+#define GPIOD_PIN0 0U
+#define GPIOD_PIN1 1U
+#define GPIOD_PIN2 2U
+#define GPIOD_PIN3 3U
+#define GPIOD_PIN4 4U
+#define GPIOD_PIN5 5U
+#define GPIOD_PIN6 6U
+#define GPIOD_PIN7 7U
+#define GPIOD_PIN8 8U
+#define GPIOD_PIN9 9U
+#define GPIOD_PIN10 10U
+#define GPIOD_PIN11 11U
+#define GPIOD_PIN12 12U
+#define GPIOD_PIN13 13U
+#define GPIOD_PIN14 14U
+#define GPIOD_PIN15 15U
+
+#define GPIOH_OSC_IN 0U
+#define GPIOH_OSC_OUT 1U
+#define GPIOH_PIN2 2U
+#define GPIOH_PIN3 3U
+#define GPIOH_PIN4 4U
+#define GPIOH_PIN5 5U
+#define GPIOH_PIN6 6U
+#define GPIOH_PIN7 7U
+#define GPIOH_PIN8 8U
+#define GPIOH_PIN9 9U
+#define GPIOH_PIN10 10U
+#define GPIOH_PIN11 11U
+#define GPIOH_PIN12 12U
+#define GPIOH_PIN13 13U
+#define GPIOH_PIN14 14U
+#define GPIOH_PIN15 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U)
+#define LINE_ACD1_IN0 PAL_LINE(GPIOA, 0U)
+#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U)
+#define LINE_ACD1_IN1 PAL_LINE(GPIOA, 1U)
+#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U)
+#define LINE_USART2_TX PAL_LINE(GPIOA, 2U)
+#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U)
+#define LINE_USART2_RX PAL_LINE(GPIOA, 3U)
+#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U)
+#define LINE_ACD1_IN4 PAL_LINE(GPIOA, 4U)
+#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U)
+#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U)
+#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U)
+#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U)
+#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U)
+#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U)
+#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U)
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
+#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U)
+#define LINE_ACD1_IN8 PAL_LINE(GPIOB, 0U)
+#define LINE_SWO PAL_LINE(GPIOB, 3U)
+#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U)
+#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U)
+#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U)
+#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U)
+#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U)
+#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U)
+#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U)
+#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U)
+#define LINE_ACD1_IN10 PAL_LINE(GPIOC, 0U)
+#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U)
+#define LINE_ACD1_IN11 PAL_LINE(GPIOC, 1U)
+#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U)
+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
+#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
+#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - ARD_A0 ACD1_IN0 (input pullup).
+ * PA1 - ARD_A1 ACD1_IN1 (input pullup).
+ * PA2 - ARD_D1 USART2_TX (alternate 4).
+ * PA3 - ARD_D0 USART2_RX (alternate 4).
+ * PA4 - ARD_A2 ACD1_IN4 (input pullup).
+ * PA5 - LED_GREEN ARD_D13 (output pushpull maximum).
+ * PA6 - ARD_D12 (input pullup).
+ * PA7 - ARD_D11 (input pullup).
+ * PA8 - ARD_D7 (input pullup).
+ * PA9 - ARD_D8 (input pullup).
+ * PA10 - ARD_D2 (input pullup).
+ * PA11 - PIN11 (input pullup).
+ * PA12 - PIN12 (input pullup).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ARD_A0) | \
+ PIN_MODE_INPUT(GPIOA_ARD_A1) | \
+ PIN_MODE_ALTERNATE(GPIOA_ARD_D1) | \
+ PIN_MODE_ALTERNATE(GPIOA_ARD_D0) | \
+ PIN_MODE_INPUT(GPIOA_ARD_A2) | \
+ PIN_MODE_OUTPUT(GPIOA_LED_GREEN) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D12) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D11) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D7) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D8) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D2) | \
+ PIN_MODE_INPUT(GPIOA_PIN11) | \
+ PIN_MODE_INPUT(GPIOA_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_LED_GREEN) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \
+ PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | \
+ PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \
+ PIN_OSPEED_HIGH(GPIOA_LED_GREEN) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D7) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D8) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_A1) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_A2) | \
+ PIN_PUPDR_FLOATING(GPIOA_LED_GREEN) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D12) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D11) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D7) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D8) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D2) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \
+ PIN_ODR_HIGH(GPIOA_ARD_A1) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D1) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D0) | \
+ PIN_ODR_HIGH(GPIOA_ARD_A2) | \
+ PIN_ODR_LOW(GPIOA_LED_GREEN) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D12) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D11) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D7) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D8) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D2) | \
+ PIN_ODR_HIGH(GPIOA_PIN11) | \
+ PIN_ODR_HIGH(GPIOA_PIN12) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D1, 4U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D0, 4U) | \
+ PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \
+ PIN_AFIO_AF(GPIOA_LED_GREEN, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D11, 0U))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0U))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - ARD_A3 ACD1_IN8 (input pullup).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - SWO ARD_D3 (alternate 0).
+ * PB4 - ARD_D5 (input pullup).
+ * PB5 - ARD_D4 (input pullup).
+ * PB6 - ARD_D10 (input pullup).
+ * PB7 - PIN7 (input pullup).
+ * PB8 - ARD_D15 (input pullup).
+ * PB9 - ARD_D14 (input pullup).
+ * PB10 - ARD_D6 (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - PIN13 (input pullup).
+ * PB14 - PIN14 (input pullup).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_ARD_A3) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D5) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D4) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D10) | \
+ PIN_MODE_INPUT(GPIOB_PIN7) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D15) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D14) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D6) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_PIN13) | \
+ PIN_MODE_INPUT(GPIOB_PIN14) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_A3) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOB_SWO) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D10) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ARD_A3) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOB_SWO) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D5) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D4) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D10) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D15) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D14) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D6) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_A3) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_SWO) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D5) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D4) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D10) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D15) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D14) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D6) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOB_SWO, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0U))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0U))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - ARD_A5 ACD1_IN10 (input pullup).
+ * PC1 - ARD_A4 ACD1_IN11 (input pullup).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PIN3 (input pullup).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - PIN5 (input pullup).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - ARD_D9 (input pullup).
+ * PC8 - PIN8 (input pullup).
+ * PC9 - PIN9 (input pullup).
+ * PC10 - PIN10 (input pullup).
+ * PC11 - PIN11 (input pullup).
+ * PC12 - PIN12 (input pullup).
+ * PC13 - BUTTON (input floating).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ARD_A5) | \
+ PIN_MODE_INPUT(GPIOC_ARD_A4) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PIN3) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_INPUT(GPIOC_PIN5) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_INPUT(GPIOC_ARD_D9) | \
+ PIN_MODE_INPUT(GPIOC_PIN8) | \
+ PIN_MODE_INPUT(GPIOC_PIN9) | \
+ PIN_MODE_INPUT(GPIOC_PIN10) | \
+ PIN_MODE_INPUT(GPIOC_PIN11) | \
+ PIN_MODE_INPUT(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_D9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A5) | \
+ PIN_OSPEED_HIGH(GPIOC_ARD_A4) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOC_ARD_D9) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOC_BUTTON) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_ARD_A5) | \
+ PIN_PUPDR_PULLUP(GPIOC_ARD_A4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOC_ARD_D9) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A5) | \
+ PIN_ODR_HIGH(GPIOC_ARD_A4) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PIN3) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_ARD_D9) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_PIN10) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_PIN12) | \
+ PIN_ODR_HIGH(GPIOC_BUTTON) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_D9, 0U))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - PIN4 (input pullup).
+ * PD5 - PIN5 (input pullup).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_INPUT(GPIOD_PIN4) | \
+ PIN_MODE_INPUT(GPIOD_PIN5) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input pullup).
+ * PH3 - PIN3 (input pullup).
+ * PH4 - PIN4 (input pullup).
+ * PH5 - PIN5 (input pullup).
+ * PH6 - PIN6 (input pullup).
+ * PH7 - PIN7 (input pullup).
+ * PH8 - PIN8 (input pullup).
+ * PH9 - PIN9 (input pullup).
+ * PH10 - PIN10 (input pullup).
+ * PH11 - PIN11 (input pullup).
+ * PH12 - PIN12 (input pullup).
+ * PH13 - PIN13 (input pullup).
+ * PH14 - PIN14 (input pullup).
+ * PH15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \
+ PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0U))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0U))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/board.mk b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/board.mk new file mode 100644 index 0000000..2a8d78c --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L053R8/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L053R8
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/cfg/board.chcfg b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/cfg/board.chcfg new file mode 100644 index 0000000..4a3bfc4 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/cfg/board.chcfg @@ -0,0 +1,669 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- STM32L0xx board Template --> +<board + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" + xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32l0xx_board.xsd"> + <configuration_settings> + <templates_path>resources/gencfg/processors/boards/stm32l0xx/templates</templates_path> + <output_path>..</output_path> + <hal_version>5.0.x</hal_version> + </configuration_settings> + <board_name>STMicroelectronics STM32 Nucleo64-L053R8</board_name> + <board_id>ST_NUCLEO64_L053R8</board_id> + <board_functions></board_functions> + <subtype>STM32L053xx</subtype> + <clocks HSEFrequency="8000000" HSEBypass="true" LSEFrequency="32768" + LSEBypass="false" LSEDrive="3 High Drive (default)" /> + <ports> + <GPIOA> + <pin0 + ID="ARD_A0 ACD1_IN0" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="ARD_A1 ACD1_IN1" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="ARD_D1 USART2_TX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="4" /> + <pin3 + ID="ARD_D0 USART2_RX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="4"/> + <pin4 + ID="ARD_A2 ACD1_IN4" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="LED_GREEN ARD_D13" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin6 + ID="ARD_D12" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="ARD_D11" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="ARD_D7" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="ARD_D8" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="ARD_D2" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="SWDIO" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="0" /> + <pin14 + ID="SWCLK" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullDown" + Mode="Alternate" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + </GPIOA> + <GPIOB> + <pin0 + ID="ARD_A3 ACD1_IN8" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin3 + ID="SWO ARD_D3" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="0" /> + <pin4 + ID="ARD_D5" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="ARD_D4" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin6 + ID="ARD_D10" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="ARD_D15" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="ARD_D14" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="ARD_D6" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + </GPIOB> + <GPIOC> + <pin0 + ID="ARD_A5 ACD1_IN10" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="ARD_A4 ACD1_IN11" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="ARD_D9" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="BUTTON" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin14 + ID="OSC32_IN" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin15 + ID="OSC32_OUT" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + </GPIOC> + <GPIOD> + <pin0 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOD> + <GPIOH> + <pin0 + ID="OSC_IN" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="OSC_OUT" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOH> + </ports> +</board> diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/cfg/board.fmpp b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/cfg/board.fmpp new file mode 100644 index 0000000..b3ba947 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L053R8/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../tools/ftl/processors/boards/stm32l0xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +} diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/board.c b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/board.c new file mode 100644 index 0000000..fbea4c4 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/board.c @@ -0,0 +1,266 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ gpio_setup_t PKData;
+#endif
+} gpio_config_t;
+
+/**
+ * @brief STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
+#endif
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetIOP(STM32_GPIO_EN_MASK);
+ rccEnableIOP(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+ gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+ gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
+ */
+void __early_init(void) {
+
+ stm32_gpio_init();
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @note You can add your board-specific code here.
+ */
+void boardInit(void) {
+
+}
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/board.h b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/board.h new file mode 100644 index 0000000..668e727 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/board.h @@ -0,0 +1,971 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * Setup for STMicroelectronics STM32 Nucleo64-L073RZ board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_NUCLEO64_L073RZ
+#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-L073RZ"
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768U
+#endif
+
+#define STM32_LSEDRV (3U << 11U)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000U
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32L073xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_ARD_A0 0U
+#define GPIOA_ACD1_IN0 0U
+#define GPIOA_ARD_A1 1U
+#define GPIOA_ACD1_IN1 1U
+#define GPIOA_ARD_D1 2U
+#define GPIOA_USART2_TX 2U
+#define GPIOA_ARD_D0 3U
+#define GPIOA_USART2_RX 3U
+#define GPIOA_ARD_A2 4U
+#define GPIOA_ACD1_IN4 4U
+#define GPIOA_LED_GREEN 5U
+#define GPIOA_ARD_D13 5U
+#define GPIOA_ARD_D12 6U
+#define GPIOA_ARD_D11 7U
+#define GPIOA_ARD_D7 8U
+#define GPIOA_ARD_D8 9U
+#define GPIOA_ARD_D2 10U
+#define GPIOA_PIN11 11U
+#define GPIOA_PIN12 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_PIN15 15U
+
+#define GPIOB_ARD_A3 0U
+#define GPIOB_ACD1_IN8 0U
+#define GPIOB_PIN1 1U
+#define GPIOB_PIN2 2U
+#define GPIOB_SWO 3U
+#define GPIOB_ARD_D3 3U
+#define GPIOB_ARD_D5 4U
+#define GPIOB_ARD_D4 5U
+#define GPIOB_ARD_D10 6U
+#define GPIOB_PIN7 7U
+#define GPIOB_ARD_D15 8U
+#define GPIOB_ARD_D14 9U
+#define GPIOB_ARD_D6 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_PIN12 12U
+#define GPIOB_PIN13 13U
+#define GPIOB_PIN14 14U
+#define GPIOB_PIN15 15U
+
+#define GPIOC_ARD_A5 0U
+#define GPIOC_ACD1_IN10 0U
+#define GPIOC_ARD_A4 1U
+#define GPIOC_ACD1_IN11 1U
+#define GPIOC_PIN2 2U
+#define GPIOC_PIN3 3U
+#define GPIOC_PIN4 4U
+#define GPIOC_PIN5 5U
+#define GPIOC_PIN6 6U
+#define GPIOC_ARD_D9 7U
+#define GPIOC_PIN8 8U
+#define GPIOC_PIN9 9U
+#define GPIOC_PIN10 10U
+#define GPIOC_PIN11 11U
+#define GPIOC_PIN12 12U
+#define GPIOC_BUTTON 13U
+#define GPIOC_OSC32_IN 14U
+#define GPIOC_OSC32_OUT 15U
+
+#define GPIOD_PIN0 0U
+#define GPIOD_PIN1 1U
+#define GPIOD_PIN2 2U
+#define GPIOD_PIN3 3U
+#define GPIOD_PIN4 4U
+#define GPIOD_PIN5 5U
+#define GPIOD_PIN6 6U
+#define GPIOD_PIN7 7U
+#define GPIOD_PIN8 8U
+#define GPIOD_PIN9 9U
+#define GPIOD_PIN10 10U
+#define GPIOD_PIN11 11U
+#define GPIOD_PIN12 12U
+#define GPIOD_PIN13 13U
+#define GPIOD_PIN14 14U
+#define GPIOD_PIN15 15U
+
+#define GPIOE_PIN0 0U
+#define GPIOE_PIN1 1U
+#define GPIOE_PIN2 2U
+#define GPIOE_PIN3 3U
+#define GPIOE_PIN4 4U
+#define GPIOE_PIN5 5U
+#define GPIOE_PIN6 6U
+#define GPIOE_PIN7 7U
+#define GPIOE_PIN8 8U
+#define GPIOE_PIN9 9U
+#define GPIOE_PIN10 10U
+#define GPIOE_PIN11 11U
+#define GPIOE_PIN12 12U
+#define GPIOE_PIN13 13U
+#define GPIOE_PIN14 14U
+#define GPIOE_PIN15 15U
+
+#define GPIOH_OSC_IN 0U
+#define GPIOH_OSC_OUT 1U
+#define GPIOH_PIN2 2U
+#define GPIOH_PIN3 3U
+#define GPIOH_PIN4 4U
+#define GPIOH_PIN5 5U
+#define GPIOH_PIN6 6U
+#define GPIOH_PIN7 7U
+#define GPIOH_PIN8 8U
+#define GPIOH_PIN9 9U
+#define GPIOH_PIN10 10U
+#define GPIOH_PIN11 11U
+#define GPIOH_PIN12 12U
+#define GPIOH_PIN13 13U
+#define GPIOH_PIN14 14U
+#define GPIOH_PIN15 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U)
+#define LINE_ACD1_IN0 PAL_LINE(GPIOA, 0U)
+#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U)
+#define LINE_ACD1_IN1 PAL_LINE(GPIOA, 1U)
+#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U)
+#define LINE_USART2_TX PAL_LINE(GPIOA, 2U)
+#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U)
+#define LINE_USART2_RX PAL_LINE(GPIOA, 3U)
+#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U)
+#define LINE_ACD1_IN4 PAL_LINE(GPIOA, 4U)
+#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U)
+#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U)
+#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U)
+#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U)
+#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U)
+#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U)
+#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U)
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
+#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U)
+#define LINE_ACD1_IN8 PAL_LINE(GPIOB, 0U)
+#define LINE_SWO PAL_LINE(GPIOB, 3U)
+#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U)
+#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U)
+#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U)
+#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U)
+#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U)
+#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U)
+#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U)
+#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U)
+#define LINE_ACD1_IN10 PAL_LINE(GPIOC, 0U)
+#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U)
+#define LINE_ACD1_IN11 PAL_LINE(GPIOC, 1U)
+#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U)
+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
+#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
+#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - ARD_A0 ACD1_IN0 (input pullup).
+ * PA1 - ARD_A1 ACD1_IN1 (input pullup).
+ * PA2 - ARD_D1 USART2_TX (alternate 4).
+ * PA3 - ARD_D0 USART2_RX (alternate 4).
+ * PA4 - ARD_A2 ACD1_IN4 (input pullup).
+ * PA5 - LED_GREEN ARD_D13 (output pushpull maximum).
+ * PA6 - ARD_D12 (input pullup).
+ * PA7 - ARD_D11 (input pullup).
+ * PA8 - ARD_D7 (input pullup).
+ * PA9 - ARD_D8 (input pullup).
+ * PA10 - ARD_D2 (input pullup).
+ * PA11 - PIN11 (input pullup).
+ * PA12 - PIN12 (input pullup).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ARD_A0) | \
+ PIN_MODE_INPUT(GPIOA_ARD_A1) | \
+ PIN_MODE_ALTERNATE(GPIOA_ARD_D1) | \
+ PIN_MODE_ALTERNATE(GPIOA_ARD_D0) | \
+ PIN_MODE_INPUT(GPIOA_ARD_A2) | \
+ PIN_MODE_OUTPUT(GPIOA_LED_GREEN) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D12) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D11) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D7) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D8) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D2) | \
+ PIN_MODE_INPUT(GPIOA_PIN11) | \
+ PIN_MODE_INPUT(GPIOA_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_LED_GREEN) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \
+ PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | \
+ PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \
+ PIN_OSPEED_HIGH(GPIOA_LED_GREEN) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D7) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D8) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_A1) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_A2) | \
+ PIN_PUPDR_FLOATING(GPIOA_LED_GREEN) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D12) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D11) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D7) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D8) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D2) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \
+ PIN_ODR_HIGH(GPIOA_ARD_A1) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D1) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D0) | \
+ PIN_ODR_HIGH(GPIOA_ARD_A2) | \
+ PIN_ODR_LOW(GPIOA_LED_GREEN) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D12) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D11) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D7) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D8) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D2) | \
+ PIN_ODR_HIGH(GPIOA_PIN11) | \
+ PIN_ODR_HIGH(GPIOA_PIN12) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D1, 4U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D0, 4U) | \
+ PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \
+ PIN_AFIO_AF(GPIOA_LED_GREEN, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D11, 0U))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0U))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - ARD_A3 ACD1_IN8 (input pullup).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - SWO ARD_D3 (alternate 0).
+ * PB4 - ARD_D5 (input pullup).
+ * PB5 - ARD_D4 (input pullup).
+ * PB6 - ARD_D10 (input pullup).
+ * PB7 - PIN7 (input pullup).
+ * PB8 - ARD_D15 (input pullup).
+ * PB9 - ARD_D14 (input pullup).
+ * PB10 - ARD_D6 (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - PIN13 (input pullup).
+ * PB14 - PIN14 (input pullup).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_ARD_A3) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D5) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D4) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D10) | \
+ PIN_MODE_INPUT(GPIOB_PIN7) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D15) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D14) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D6) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_PIN13) | \
+ PIN_MODE_INPUT(GPIOB_PIN14) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_A3) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOB_SWO) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D10) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ARD_A3) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOB_SWO) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D5) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D4) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D10) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D15) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D14) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D6) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_A3) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_SWO) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D5) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D4) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D10) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D15) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D14) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D6) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOB_SWO, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0U))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0U))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - ARD_A5 ACD1_IN10 (input pullup).
+ * PC1 - ARD_A4 ACD1_IN11 (input pullup).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PIN3 (input pullup).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - PIN5 (input pullup).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - ARD_D9 (input pullup).
+ * PC8 - PIN8 (input pullup).
+ * PC9 - PIN9 (input pullup).
+ * PC10 - PIN10 (input pullup).
+ * PC11 - PIN11 (input pullup).
+ * PC12 - PIN12 (input pullup).
+ * PC13 - BUTTON (input floating).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ARD_A5) | \
+ PIN_MODE_INPUT(GPIOC_ARD_A4) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PIN3) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_INPUT(GPIOC_PIN5) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_INPUT(GPIOC_ARD_D9) | \
+ PIN_MODE_INPUT(GPIOC_PIN8) | \
+ PIN_MODE_INPUT(GPIOC_PIN9) | \
+ PIN_MODE_INPUT(GPIOC_PIN10) | \
+ PIN_MODE_INPUT(GPIOC_PIN11) | \
+ PIN_MODE_INPUT(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_D9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A5) | \
+ PIN_OSPEED_HIGH(GPIOC_ARD_A4) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOC_ARD_D9) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOC_BUTTON) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_ARD_A5) | \
+ PIN_PUPDR_PULLUP(GPIOC_ARD_A4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOC_ARD_D9) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A5) | \
+ PIN_ODR_HIGH(GPIOC_ARD_A4) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PIN3) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_ARD_D9) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_PIN10) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_PIN12) | \
+ PIN_ODR_HIGH(GPIOC_BUTTON) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_D9, 0U))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - PIN4 (input pullup).
+ * PD5 - PIN5 (input pullup).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_INPUT(GPIOD_PIN4) | \
+ PIN_MODE_INPUT(GPIOD_PIN5) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (input pullup).
+ * PE1 - PIN1 (input pullup).
+ * PE2 - PIN2 (input pullup).
+ * PE3 - PIN3 (input pullup).
+ * PE4 - PIN4 (input pullup).
+ * PE5 - PIN5 (input pullup).
+ * PE6 - PIN6 (input pullup).
+ * PE7 - PIN7 (input pullup).
+ * PE8 - PIN8 (input pullup).
+ * PE9 - PIN9 (input pullup).
+ * PE10 - PIN10 (input pullup).
+ * PE11 - PIN11 (input pullup).
+ * PE12 - PIN12 (input pullup).
+ * PE13 - PIN13 (input pullup).
+ * PE14 - PIN14 (input pullup).
+ * PE15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
+ PIN_MODE_INPUT(GPIOE_PIN1) | \
+ PIN_MODE_INPUT(GPIOE_PIN2) | \
+ PIN_MODE_INPUT(GPIOE_PIN3) | \
+ PIN_MODE_INPUT(GPIOE_PIN4) | \
+ PIN_MODE_INPUT(GPIOE_PIN5) | \
+ PIN_MODE_INPUT(GPIOE_PIN6) | \
+ PIN_MODE_INPUT(GPIOE_PIN7) | \
+ PIN_MODE_INPUT(GPIOE_PIN8) | \
+ PIN_MODE_INPUT(GPIOE_PIN9) | \
+ PIN_MODE_INPUT(GPIOE_PIN10) | \
+ PIN_MODE_INPUT(GPIOE_PIN11) | \
+ PIN_MODE_INPUT(GPIOE_PIN12) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PIN14) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
+ PIN_ODR_HIGH(GPIOE_PIN1) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_PIN3) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0U))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0U))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input pullup).
+ * PH3 - PIN3 (input pullup).
+ * PH4 - PIN4 (input pullup).
+ * PH5 - PIN5 (input pullup).
+ * PH6 - PIN6 (input pullup).
+ * PH7 - PIN7 (input pullup).
+ * PH8 - PIN8 (input pullup).
+ * PH9 - PIN9 (input pullup).
+ * PH10 - PIN10 (input pullup).
+ * PH11 - PIN11 (input pullup).
+ * PH12 - PIN12 (input pullup).
+ * PH13 - PIN13 (input pullup).
+ * PH14 - PIN14 (input pullup).
+ * PH15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \
+ PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0U))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0U))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/board.mk b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/board.mk new file mode 100644 index 0000000..d99e2a4 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L073RZ/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L073RZ
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/cfg/board.chcfg b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/cfg/board.chcfg new file mode 100644 index 0000000..6e8dfc6 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/cfg/board.chcfg @@ -0,0 +1,799 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- STM32L0xx board Template --> +<board + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" + xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32l0xx_board.xsd"> + <configuration_settings> + <templates_path>resources/gencfg/processors/boards/stm32l0xx/templates</templates_path> + <output_path>..</output_path> + <hal_version>5.0.x</hal_version> + </configuration_settings> + <board_name>STMicroelectronics STM32 Nucleo64-L073RZ</board_name> + <board_id>ST_NUCLEO64_L073RZ</board_id> + <board_functions></board_functions> + <subtype>STM32L073xx</subtype> + <clocks HSEFrequency="8000000" HSEBypass="true" LSEFrequency="32768" + LSEBypass="false" LSEDrive="3 High Drive (default)" /> + <ports> + <GPIOA> + <pin0 + ID="ARD_A0 ACD1_IN0" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="ARD_A1 ACD1_IN1" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="ARD_D1 USART2_TX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="4" /> + <pin3 + ID="ARD_D0 USART2_RX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="4"/> + <pin4 + ID="ARD_A2 ACD1_IN4" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="LED_GREEN ARD_D13" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin6 + ID="ARD_D12" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="ARD_D11" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="ARD_D7" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="ARD_D8" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="ARD_D2" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="SWDIO" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="0" /> + <pin14 + ID="SWCLK" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullDown" + Mode="Alternate" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + </GPIOA> + <GPIOB> + <pin0 + ID="ARD_A3 ACD1_IN8" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin3 + ID="SWO ARD_D3" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="0" /> + <pin4 + ID="ARD_D5" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="ARD_D4" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin6 + ID="ARD_D10" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="ARD_D15" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="ARD_D14" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="ARD_D6" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + </GPIOB> + <GPIOC> + <pin0 + ID="ARD_A5 ACD1_IN10" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="ARD_A4 ACD1_IN11" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="ARD_D9" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="BUTTON" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin14 + ID="OSC32_IN" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin15 + ID="OSC32_OUT" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + </GPIOC> + <GPIOD> + <pin0 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOD> + <GPIOE> + <pin0 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOE> + <GPIOH> + <pin0 + ID="OSC_IN" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="OSC_OUT" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOH> + </ports> +</board> diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/cfg/board.fmpp b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/cfg/board.fmpp new file mode 100644 index 0000000..b3ba947 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L073RZ/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../tools/ftl/processors/boards/stm32l0xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +} diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/board.c b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/board.c new file mode 100644 index 0000000..29d73fe --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/board.c @@ -0,0 +1,266 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ gpio_setup_t PKData;
+#endif
+} gpio_config_t;
+
+/**
+ * @brief STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
+#endif
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetAHB(STM32_GPIO_EN_MASK);
+ rccEnableAHB(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+ gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+ gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
+ */
+void __early_init(void) {
+
+ stm32_gpio_init();
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @note You can add your board-specific code here.
+ */
+void boardInit(void) {
+
+}
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/board.h b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/board.h new file mode 100644 index 0000000..2f598a2 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/board.h @@ -0,0 +1,1237 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * Setup for STMicroelectronics STM32 Nucleo64-L152RE board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_NUCLEO64_L152RE
+#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-L152RE"
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768U
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000U
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32L152xE
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_ARD_A0 0U
+#define GPIOA_ACD1_IN0 0U
+#define GPIOA_ARD_A1 1U
+#define GPIOA_ACD1_IN1 1U
+#define GPIOA_ARD_D1 2U
+#define GPIOA_USART2_TX 2U
+#define GPIOA_ARD_D0 3U
+#define GPIOA_USART2_RX 3U
+#define GPIOA_ARD_A2 4U
+#define GPIOA_ACD1_IN4 4U
+#define GPIOA_LED_GREEN 5U
+#define GPIOA_ARD_D13 5U
+#define GPIOA_ARD_D12 6U
+#define GPIOA_ARD_D11 7U
+#define GPIOA_ARD_D7 8U
+#define GPIOA_ARD_D8 9U
+#define GPIOA_ARD_D2 10U
+#define GPIOA_PIN11 11U
+#define GPIOA_PIN12 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_PIN15 15U
+
+#define GPIOB_ARD_A3 0U
+#define GPIOB_ACD1_IN8 0U
+#define GPIOB_PIN1 1U
+#define GPIOB_PIN2 2U
+#define GPIOB_SWO 3U
+#define GPIOB_ARD_D3 3U
+#define GPIOB_ARD_D5 4U
+#define GPIOB_ARD_D4 5U
+#define GPIOB_ARD_D10 6U
+#define GPIOB_PIN7 7U
+#define GPIOB_ARD_D15 8U
+#define GPIOB_ARD_D14 9U
+#define GPIOB_ARD_D6 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_PIN12 12U
+#define GPIOB_PIN13 13U
+#define GPIOB_PIN14 14U
+#define GPIOB_PIN15 15U
+
+#define GPIOC_ARD_A5 0U
+#define GPIOC_ACD1_IN10 0U
+#define GPIOC_ARD_A4 1U
+#define GPIOC_ACD1_IN11 1U
+#define GPIOC_PIN2 2U
+#define GPIOC_PIN3 3U
+#define GPIOC_PIN4 4U
+#define GPIOC_PIN5 5U
+#define GPIOC_PIN6 6U
+#define GPIOC_ARD_D9 7U
+#define GPIOC_PIN8 8U
+#define GPIOC_PIN9 9U
+#define GPIOC_PIN10 10U
+#define GPIOC_PIN11 11U
+#define GPIOC_PIN12 12U
+#define GPIOC_BUTTON 13U
+#define GPIOC_OSC32_IN 14U
+#define GPIOC_OSC32_OUT 15U
+
+#define GPIOD_PIN0 0U
+#define GPIOD_PIN1 1U
+#define GPIOD_PIN2 2U
+#define GPIOD_PIN3 3U
+#define GPIOD_PIN4 4U
+#define GPIOD_PIN5 5U
+#define GPIOD_PIN6 6U
+#define GPIOD_PIN7 7U
+#define GPIOD_PIN8 8U
+#define GPIOD_PIN9 9U
+#define GPIOD_PIN10 10U
+#define GPIOD_PIN11 11U
+#define GPIOD_PIN12 12U
+#define GPIOD_PIN13 13U
+#define GPIOD_PIN14 14U
+#define GPIOD_PIN15 15U
+
+#define GPIOE_PIN0 0U
+#define GPIOE_PIN1 1U
+#define GPIOE_PIN2 2U
+#define GPIOE_PIN3 3U
+#define GPIOE_PIN4 4U
+#define GPIOE_PIN5 5U
+#define GPIOE_PIN6 6U
+#define GPIOE_PIN7 7U
+#define GPIOE_PIN8 8U
+#define GPIOE_PIN9 9U
+#define GPIOE_PIN10 10U
+#define GPIOE_PIN11 11U
+#define GPIOE_PIN12 12U
+#define GPIOE_PIN13 13U
+#define GPIOE_PIN14 14U
+#define GPIOE_PIN15 15U
+
+#define GPIOF_PIN0 0U
+#define GPIOF_PIN1 1U
+#define GPIOF_PIN2 2U
+#define GPIOF_PIN3 3U
+#define GPIOF_PIN4 4U
+#define GPIOF_PIN5 5U
+#define GPIOF_PIN6 6U
+#define GPIOF_PIN7 7U
+#define GPIOF_PIN8 8U
+#define GPIOF_PIN9 9U
+#define GPIOF_PIN10 10U
+#define GPIOF_PIN11 11U
+#define GPIOF_PIN12 12U
+#define GPIOF_PIN13 13U
+#define GPIOF_PIN14 14U
+#define GPIOF_PIN15 15U
+
+#define GPIOG_PIN0 0U
+#define GPIOG_PIN1 1U
+#define GPIOG_PIN2 2U
+#define GPIOG_PIN3 3U
+#define GPIOG_PIN4 4U
+#define GPIOG_PIN5 5U
+#define GPIOG_PIN6 6U
+#define GPIOG_PIN7 7U
+#define GPIOG_PIN8 8U
+#define GPIOG_PIN9 9U
+#define GPIOG_PIN10 10U
+#define GPIOG_PIN11 11U
+#define GPIOG_PIN12 12U
+#define GPIOG_PIN13 13U
+#define GPIOG_PIN14 14U
+#define GPIOG_PIN15 15U
+
+#define GPIOH_OSC_IN 0U
+#define GPIOH_OSC_OUT 1U
+#define GPIOH_PIN2 2U
+#define GPIOH_PIN3 3U
+#define GPIOH_PIN4 4U
+#define GPIOH_PIN5 5U
+#define GPIOH_PIN6 6U
+#define GPIOH_PIN7 7U
+#define GPIOH_PIN8 8U
+#define GPIOH_PIN9 9U
+#define GPIOH_PIN10 10U
+#define GPIOH_PIN11 11U
+#define GPIOH_PIN12 12U
+#define GPIOH_PIN13 13U
+#define GPIOH_PIN14 14U
+#define GPIOH_PIN15 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U)
+#define LINE_ACD1_IN0 PAL_LINE(GPIOA, 0U)
+#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U)
+#define LINE_ACD1_IN1 PAL_LINE(GPIOA, 1U)
+#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U)
+#define LINE_USART2_TX PAL_LINE(GPIOA, 2U)
+#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U)
+#define LINE_USART2_RX PAL_LINE(GPIOA, 3U)
+#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U)
+#define LINE_ACD1_IN4 PAL_LINE(GPIOA, 4U)
+#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U)
+#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U)
+#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U)
+#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U)
+#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U)
+#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U)
+#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U)
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
+#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U)
+#define LINE_ACD1_IN8 PAL_LINE(GPIOB, 0U)
+#define LINE_SWO PAL_LINE(GPIOB, 3U)
+#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U)
+#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U)
+#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U)
+#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U)
+#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U)
+#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U)
+#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U)
+#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U)
+#define LINE_ACD1_IN10 PAL_LINE(GPIOC, 0U)
+#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U)
+#define LINE_ACD1_IN11 PAL_LINE(GPIOC, 1U)
+#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U)
+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
+#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
+#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - ARD_A0 ACD1_IN0 (input pullup).
+ * PA1 - ARD_A1 ACD1_IN1 (input pullup).
+ * PA2 - ARD_D1 USART2_TX (alternate 7).
+ * PA3 - ARD_D0 USART2_RX (alternate 7).
+ * PA4 - ARD_A2 ACD1_IN4 (input pullup).
+ * PA5 - LED_GREEN ARD_D13 (output pushpull high).
+ * PA6 - ARD_D12 (input pullup).
+ * PA7 - ARD_D11 (input pullup).
+ * PA8 - ARD_D7 (input pullup).
+ * PA9 - ARD_D8 (input pullup).
+ * PA10 - ARD_D2 (input pullup).
+ * PA11 - PIN11 (input pullup).
+ * PA12 - PIN12 (input pullup).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ARD_A0) | \
+ PIN_MODE_INPUT(GPIOA_ARD_A1) | \
+ PIN_MODE_ALTERNATE(GPIOA_ARD_D1) | \
+ PIN_MODE_ALTERNATE(GPIOA_ARD_D0) | \
+ PIN_MODE_INPUT(GPIOA_ARD_A2) | \
+ PIN_MODE_OUTPUT(GPIOA_LED_GREEN) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D12) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D11) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D7) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D8) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D2) | \
+ PIN_MODE_INPUT(GPIOA_PIN11) | \
+ PIN_MODE_INPUT(GPIOA_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_LED_GREEN) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \
+ PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | \
+ PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \
+ PIN_OSPEED_MEDIUM(GPIOA_LED_GREEN) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D7) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D8) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_A1) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_A2) | \
+ PIN_PUPDR_FLOATING(GPIOA_LED_GREEN) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D12) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D11) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D7) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D8) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D2) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \
+ PIN_ODR_HIGH(GPIOA_ARD_A1) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D1) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D0) | \
+ PIN_ODR_HIGH(GPIOA_ARD_A2) | \
+ PIN_ODR_LOW(GPIOA_LED_GREEN) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D12) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D11) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D7) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D8) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D2) | \
+ PIN_ODR_HIGH(GPIOA_PIN11) | \
+ PIN_ODR_HIGH(GPIOA_PIN12) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D1, 7U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D0, 7U) | \
+ PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \
+ PIN_AFIO_AF(GPIOA_LED_GREEN, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D11, 0U))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0U))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - ARD_A3 ACD1_IN8 (input pullup).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - SWO ARD_D3 (alternate 0).
+ * PB4 - ARD_D5 (input pullup).
+ * PB5 - ARD_D4 (input pullup).
+ * PB6 - ARD_D10 (input pullup).
+ * PB7 - PIN7 (input pullup).
+ * PB8 - ARD_D15 (input pullup).
+ * PB9 - ARD_D14 (input pullup).
+ * PB10 - ARD_D6 (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - PIN13 (input pullup).
+ * PB14 - PIN14 (input pullup).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_ARD_A3) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D5) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D4) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D10) | \
+ PIN_MODE_INPUT(GPIOB_PIN7) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D15) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D14) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D6) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_PIN13) | \
+ PIN_MODE_INPUT(GPIOB_PIN14) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_A3) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOB_SWO) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D10) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ARD_A3) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOB_SWO) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D5) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D4) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D10) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D15) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D14) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D6) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_A3) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_SWO) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D5) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D4) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D10) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D15) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D14) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D6) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOB_SWO, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0U))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0U))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - ARD_A5 ACD1_IN10 (input pullup).
+ * PC1 - ARD_A4 ACD1_IN11 (input pullup).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PIN3 (input pullup).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - PIN5 (input pullup).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - ARD_D9 (input pullup).
+ * PC8 - PIN8 (input pullup).
+ * PC9 - PIN9 (input pullup).
+ * PC10 - PIN10 (input pullup).
+ * PC11 - PIN11 (input pullup).
+ * PC12 - PIN12 (input pullup).
+ * PC13 - BUTTON (input floating).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ARD_A5) | \
+ PIN_MODE_INPUT(GPIOC_ARD_A4) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PIN3) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_INPUT(GPIOC_PIN5) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_INPUT(GPIOC_ARD_D9) | \
+ PIN_MODE_INPUT(GPIOC_PIN8) | \
+ PIN_MODE_INPUT(GPIOC_PIN9) | \
+ PIN_MODE_INPUT(GPIOC_PIN10) | \
+ PIN_MODE_INPUT(GPIOC_PIN11) | \
+ PIN_MODE_INPUT(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_D9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A5) | \
+ PIN_OSPEED_HIGH(GPIOC_ARD_A4) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOC_ARD_D9) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOC_BUTTON) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_ARD_A5) | \
+ PIN_PUPDR_PULLUP(GPIOC_ARD_A4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOC_ARD_D9) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A5) | \
+ PIN_ODR_HIGH(GPIOC_ARD_A4) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PIN3) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_ARD_D9) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_PIN10) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_PIN12) | \
+ PIN_ODR_HIGH(GPIOC_BUTTON) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_D9, 0U))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - PIN4 (input pullup).
+ * PD5 - PIN5 (input pullup).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_INPUT(GPIOD_PIN4) | \
+ PIN_MODE_INPUT(GPIOD_PIN5) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (input pullup).
+ * PE1 - PIN1 (input pullup).
+ * PE2 - PIN2 (input pullup).
+ * PE3 - PIN3 (input pullup).
+ * PE4 - PIN4 (input pullup).
+ * PE5 - PIN5 (input pullup).
+ * PE6 - PIN6 (input pullup).
+ * PE7 - PIN7 (input pullup).
+ * PE8 - PIN8 (input pullup).
+ * PE9 - PIN9 (input pullup).
+ * PE10 - PIN10 (input pullup).
+ * PE11 - PIN11 (input pullup).
+ * PE12 - PIN12 (input pullup).
+ * PE13 - PIN13 (input pullup).
+ * PE14 - PIN14 (input pullup).
+ * PE15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
+ PIN_MODE_INPUT(GPIOE_PIN1) | \
+ PIN_MODE_INPUT(GPIOE_PIN2) | \
+ PIN_MODE_INPUT(GPIOE_PIN3) | \
+ PIN_MODE_INPUT(GPIOE_PIN4) | \
+ PIN_MODE_INPUT(GPIOE_PIN5) | \
+ PIN_MODE_INPUT(GPIOE_PIN6) | \
+ PIN_MODE_INPUT(GPIOE_PIN7) | \
+ PIN_MODE_INPUT(GPIOE_PIN8) | \
+ PIN_MODE_INPUT(GPIOE_PIN9) | \
+ PIN_MODE_INPUT(GPIOE_PIN10) | \
+ PIN_MODE_INPUT(GPIOE_PIN11) | \
+ PIN_MODE_INPUT(GPIOE_PIN12) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PIN14) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
+ PIN_ODR_HIGH(GPIOE_PIN1) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_PIN3) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0U))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0U))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - PIN0 (input pullup).
+ * PF1 - PIN1 (input pullup).
+ * PF2 - PIN2 (input pullup).
+ * PF3 - PIN3 (input pullup).
+ * PF4 - PIN4 (input pullup).
+ * PF5 - PIN5 (input pullup).
+ * PF6 - PIN6 (input pullup).
+ * PF7 - PIN7 (input pullup).
+ * PF8 - PIN8 (input pullup).
+ * PF9 - PIN9 (input pullup).
+ * PF10 - PIN10 (input pullup).
+ * PF11 - PIN11 (input pullup).
+ * PF12 - PIN12 (input pullup).
+ * PF13 - PIN13 (input pullup).
+ * PF14 - PIN14 (input pullup).
+ * PF15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
+ PIN_MODE_INPUT(GPIOF_PIN1) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0U))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0U))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (input pullup).
+ * PG1 - PIN1 (input pullup).
+ * PG2 - PIN2 (input pullup).
+ * PG3 - PIN3 (input pullup).
+ * PG4 - PIN4 (input pullup).
+ * PG5 - PIN5 (input pullup).
+ * PG6 - PIN6 (input pullup).
+ * PG7 - PIN7 (input pullup).
+ * PG8 - PIN8 (input pullup).
+ * PG9 - PIN9 (input pullup).
+ * PG10 - PIN10 (input pullup).
+ * PG11 - PIN11 (input pullup).
+ * PG12 - PIN12 (input pullup).
+ * PG13 - PIN13 (input pullup).
+ * PG14 - PIN14 (input pullup).
+ * PG15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \
+ PIN_MODE_INPUT(GPIOG_PIN1) | \
+ PIN_MODE_INPUT(GPIOG_PIN2) | \
+ PIN_MODE_INPUT(GPIOG_PIN3) | \
+ PIN_MODE_INPUT(GPIOG_PIN4) | \
+ PIN_MODE_INPUT(GPIOG_PIN5) | \
+ PIN_MODE_INPUT(GPIOG_PIN6) | \
+ PIN_MODE_INPUT(GPIOG_PIN7) | \
+ PIN_MODE_INPUT(GPIOG_PIN8) | \
+ PIN_MODE_INPUT(GPIOG_PIN9) | \
+ PIN_MODE_INPUT(GPIOG_PIN10) | \
+ PIN_MODE_INPUT(GPIOG_PIN11) | \
+ PIN_MODE_INPUT(GPIOG_PIN12) | \
+ PIN_MODE_INPUT(GPIOG_PIN13) | \
+ PIN_MODE_INPUT(GPIOG_PIN14) | \
+ PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
+ PIN_ODR_HIGH(GPIOG_PIN1) | \
+ PIN_ODR_HIGH(GPIOG_PIN2) | \
+ PIN_ODR_HIGH(GPIOG_PIN3) | \
+ PIN_ODR_HIGH(GPIOG_PIN4) | \
+ PIN_ODR_HIGH(GPIOG_PIN5) | \
+ PIN_ODR_HIGH(GPIOG_PIN6) | \
+ PIN_ODR_HIGH(GPIOG_PIN7) | \
+ PIN_ODR_HIGH(GPIOG_PIN8) | \
+ PIN_ODR_HIGH(GPIOG_PIN9) | \
+ PIN_ODR_HIGH(GPIOG_PIN10) | \
+ PIN_ODR_HIGH(GPIOG_PIN11) | \
+ PIN_ODR_HIGH(GPIOG_PIN12) | \
+ PIN_ODR_HIGH(GPIOG_PIN13) | \
+ PIN_ODR_HIGH(GPIOG_PIN14) | \
+ PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN7, 0U))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0U))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input pullup).
+ * PH3 - PIN3 (input pullup).
+ * PH4 - PIN4 (input pullup).
+ * PH5 - PIN5 (input pullup).
+ * PH6 - PIN6 (input pullup).
+ * PH7 - PIN7 (input pullup).
+ * PH8 - PIN8 (input pullup).
+ * PH9 - PIN9 (input pullup).
+ * PH10 - PIN10 (input pullup).
+ * PH11 - PIN11 (input pullup).
+ * PH12 - PIN12 (input pullup).
+ * PH13 - PIN13 (input pullup).
+ * PH14 - PIN14 (input pullup).
+ * PH15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \
+ PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0U))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0U))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/board.mk b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/board.mk new file mode 100644 index 0000000..8535ad1 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L152RE/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L152RE
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/cfg/board.chcfg b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/cfg/board.chcfg new file mode 100644 index 0000000..fd034a6 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/cfg/board.chcfg @@ -0,0 +1,1063 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- STM32L1xx board Template --> +<board + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" + xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32l1xx_board.xsd"> + <configuration_settings> + <templates_path>resources/gencfg/processors/boards/stm32l1xx/templates</templates_path> + <output_path>..</output_path> + <hal_version>5.0.x</hal_version> + </configuration_settings> + <board_name>STMicroelectronics STM32 Nucleo64-L152RE</board_name> + <board_id>ST_NUCLEO64_L152RE</board_id> + <board_functions></board_functions> + <subtype>STM32L152xE</subtype> + <clocks + HSEFrequency="8000000" + HSEBypass="true" + LSEFrequency="32768" + LSEBypass="false" + /> + <ports> + <GPIOA> + <pin0 + ID="ARD_A0 ACD1_IN0" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="ARD_A1 ACD1_IN1" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="ARD_D1 USART2_TX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="7" /> + <pin3 + ID="ARD_D0 USART2_RX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="7" /> + <pin4 + ID="ARD_A2 ACD1_IN4" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="LED_GREEN ARD_D13" + Type="PushPull" + Level="Low" + Speed="High" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin6 + ID="ARD_D12" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="ARD_D11" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="ARD_D7" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="ARD_D8" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="ARD_D2" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="SWDIO" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="0" /> + <pin14 + ID="SWCLK" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullDown" + Mode="Alternate" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + </GPIOA> + <GPIOB> + <pin0 + ID="ARD_A3 ACD1_IN8" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin3 + ID="SWO ARD_D3" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="0" /> + <pin4 + ID="ARD_D5" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="ARD_D4" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin6 + ID="ARD_D10" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="ARD_D15" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="ARD_D14" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="ARD_D6" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + </GPIOB> + <GPIOC> + <pin0 + ID="ARD_A5 ACD1_IN10" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="ARD_A4 ACD1_IN11" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin7 + ID="ARD_D9" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin13 + ID="BUTTON" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin14 + ID="OSC32_IN" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin15 + ID="OSC32_OUT" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + </GPIOC> + <GPIOD> + <pin0 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOD> + <GPIOE> + <pin0 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOE> + <GPIOF> + <pin0 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOF> + <GPIOG> + <pin0 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOG> + <GPIOH> + <pin0 + ID="OSC_IN" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0"/> + <pin1 + ID="OSC_OUT" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOH> + </ports> +</board> diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/cfg/board.fmpp b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/cfg/board.fmpp new file mode 100644 index 0000000..029da4f --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L152RE/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../tools/ftl/processors/boards/stm32l1xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +} diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/board.c b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/board.c new file mode 100644 index 0000000..cd16e43 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/board.c @@ -0,0 +1,281 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+ uint32_t ascr;
+ uint32_t lockr;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ gpio_setup_t PKData;
+#endif
+} gpio_config_t;
+
+/**
+ * @brief STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR,
+ VAL_GPIOA_LOCKR},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR,
+ VAL_GPIOB_LOCKR},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR,
+ VAL_GPIOC_LOCKR},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR,
+ VAL_GPIOD_LOCKR},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR,
+ VAL_GPIOE_LOCKR},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR,
+ VAL_GPIOF_LOCKR},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR,
+ VAL_GPIOG_LOCKR},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR,
+ VAL_GPIOH_LOCKR},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR,
+ VAL_GPIOI_LOCKR},
+#endif
+#if STM32_HAS_GPIOJ
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR,
+ VAL_GPIOJ_LOCKR},
+#endif
+#if STM32_HAS_GPIOK
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR,
+ VAL_GPIOK_LOCKR}
+#endif
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->ASCR = config->ascr;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+ gpiop->LOCKR = config->lockr;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetAHB2(STM32_GPIO_EN_MASK);
+ rccEnableAHB2(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+ gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+ gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
+ */
+void __early_init(void) {
+
+ stm32_gpio_init();
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @note You can add your board-specific code here.
+ */
+void boardInit(void) {
+
+}
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/board.h b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/board.h new file mode 100644 index 0000000..43c5350 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/board.h @@ -0,0 +1,1505 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * Setup for STMicroelectronics STM32 Nucleo64-L452RE-P board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_NUCLEO64_L452RE_P
+#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-L452RE-P"
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768U
+#endif
+
+#define STM32_LSEDRV (3U << 3U)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000U
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 300U
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32L452xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_ARD_A0 0U
+#define GPIOA_ADC1_IN5 0U
+#define GPIOA_ARD_A1 1U
+#define GPIOA_ADC1_IN6 1U
+#define GPIOA_STLINK_TX 2U
+#define GPIOA_STLINK_RX 3U
+#define GPIOA_SMPS_EN 4U
+#define GPIOA_SMPS_V1 5U
+#define GPIOA_SMPS_PG 6U
+#define GPIOA_SMPS_SW 7U
+#define GPIOA_ARD_D9 8U
+#define GPIOA_ARD_D1_TX 9U
+#define GPIOA_ARD_D0_RX 10U
+#define GPIOA_ARD_D10 11U
+#define GPIOA_ARD_D2 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_ARD_D5 15U
+
+#define GPIOB_PIN0 0U
+#define GPIOB_PIN1 1U
+#define GPIOB_PIN2 2U
+#define GPIOB_ARD_D3 3U
+#define GPIOB_PIN4 4U
+#define GPIOB_ARD_D4 5U
+#define GPIOB_ARD_D8 6U
+#define GPIOB_ARD_D14 7U
+#define GPIOB_ARD_D15 8U
+#define GPIOB_PIN9 9U
+#define GPIOB_ARD_D6 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_PIN12 12U
+#define GPIOB_ARD_D13 13U
+#define GPIOB_LED_GREEN 13U
+#define GPIOB_ARD_D12 14U
+#define GPIOB_ARD_D11 15U
+
+#define GPIOC_ARD_A5 0U
+#define GPIOC_ADC1_IN1 0U
+#define GPIOC_ARD_A4 1U
+#define GPIOC_ADC1_IN2 1U
+#define GPIOC_ARD_A3 2U
+#define GPIOC_ADC1_IN3 2U
+#define GPIOC_ARD_A2 3U
+#define GPIOC_ADC1_IN4 3U
+#define GPIOC_PIN4 4U
+#define GPIOC_PIN5 5U
+#define GPIOC_PIN6 6U
+#define GPIOC_ARD_D7 7U
+#define GPIOC_PIN8 8U
+#define GPIOC_PIN9 9U
+#define GPIOC_PIN10 10U
+#define GPIOC_PIN11 11U
+#define GPIOC_PIN12 12U
+#define GPIOC_BUTTON 13U
+#define GPIOC_OSC32_IN 14U
+#define GPIOC_OSC32_OUT 15U
+
+#define GPIOD_PIN0 0U
+#define GPIOD_PIN1 1U
+#define GPIOD_PIN2 2U
+#define GPIOD_PIN3 3U
+#define GPIOD_PIN4 4U
+#define GPIOD_PIN5 5U
+#define GPIOD_PIN6 6U
+#define GPIOD_PIN7 7U
+#define GPIOD_PIN8 8U
+#define GPIOD_PIN9 9U
+#define GPIOD_PIN10 10U
+#define GPIOD_PIN11 11U
+#define GPIOD_PIN12 12U
+#define GPIOD_PIN13 13U
+#define GPIOD_PIN14 14U
+#define GPIOD_PIN15 15U
+
+#define GPIOE_PIN0 0U
+#define GPIOE_PIN1 1U
+#define GPIOE_PIN2 2U
+#define GPIOE_PIN3 3U
+#define GPIOE_PIN4 4U
+#define GPIOE_PIN5 5U
+#define GPIOE_PIN6 6U
+#define GPIOE_PIN7 7U
+#define GPIOE_PIN8 8U
+#define GPIOE_PIN9 9U
+#define GPIOE_PIN10 10U
+#define GPIOE_PIN11 11U
+#define GPIOE_PIN12 12U
+#define GPIOE_PIN13 13U
+#define GPIOE_PIN14 14U
+#define GPIOE_PIN15 15U
+
+#define GPIOF_PIN0 0U
+#define GPIOF_PIN1 1U
+#define GPIOF_PIN2 2U
+#define GPIOF_PIN3 3U
+#define GPIOF_PIN4 4U
+#define GPIOF_PIN5 5U
+#define GPIOF_PIN6 6U
+#define GPIOF_PIN7 7U
+#define GPIOF_PIN8 8U
+#define GPIOF_PIN9 9U
+#define GPIOF_PIN10 10U
+#define GPIOF_PIN11 11U
+#define GPIOF_PIN12 12U
+#define GPIOF_PIN13 13U
+#define GPIOF_PIN14 14U
+#define GPIOF_PIN15 15U
+
+#define GPIOG_PIN0 0U
+#define GPIOG_PIN1 1U
+#define GPIOG_PIN2 2U
+#define GPIOG_PIN3 3U
+#define GPIOG_PIN4 4U
+#define GPIOG_PIN5 5U
+#define GPIOG_PIN6 6U
+#define GPIOG_PIN7 7U
+#define GPIOG_PIN8 8U
+#define GPIOG_PIN9 9U
+#define GPIOG_PIN10 10U
+#define GPIOG_PIN11 11U
+#define GPIOG_PIN12 12U
+#define GPIOG_PIN13 13U
+#define GPIOG_PIN14 14U
+#define GPIOG_PIN15 15U
+
+#define GPIOH_OSC_IN 0U
+#define GPIOH_OSC_OUT 1U
+#define GPIOH_PIN2 2U
+#define GPIOH_PIN3 3U
+#define GPIOH_PIN4 4U
+#define GPIOH_PIN5 5U
+#define GPIOH_PIN6 6U
+#define GPIOH_PIN7 7U
+#define GPIOH_PIN8 8U
+#define GPIOH_PIN9 9U
+#define GPIOH_PIN10 10U
+#define GPIOH_PIN11 11U
+#define GPIOH_PIN12 12U
+#define GPIOH_PIN13 13U
+#define GPIOH_PIN14 14U
+#define GPIOH_PIN15 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U)
+#define LINE_ADC1_IN5 PAL_LINE(GPIOA, 0U)
+#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U)
+#define LINE_ADC1_IN6 PAL_LINE(GPIOA, 1U)
+#define LINE_STLINK_TX PAL_LINE(GPIOA, 2U)
+#define LINE_STLINK_RX PAL_LINE(GPIOA, 3U)
+#define LINE_SMPS_EN PAL_LINE(GPIOA, 4U)
+#define LINE_SMPS_V1 PAL_LINE(GPIOA, 5U)
+#define LINE_SMPS_PG PAL_LINE(GPIOA, 6U)
+#define LINE_SMPS_SW PAL_LINE(GPIOA, 7U)
+#define LINE_ARD_D9 PAL_LINE(GPIOA, 8U)
+#define LINE_ARD_D1_TX PAL_LINE(GPIOA, 9U)
+#define LINE_ARD_D0_RX PAL_LINE(GPIOA, 10U)
+#define LINE_ARD_D10 PAL_LINE(GPIOA, 11U)
+#define LINE_ARD_D2 PAL_LINE(GPIOA, 12U)
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
+#define LINE_ARD_D5 PAL_LINE(GPIOA, 15U)
+#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U)
+#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U)
+#define LINE_ARD_D8 PAL_LINE(GPIOB, 6U)
+#define LINE_ARD_D14 PAL_LINE(GPIOB, 7U)
+#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U)
+#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U)
+#define LINE_ARD_D13 PAL_LINE(GPIOB, 13U)
+#define LINE_LED_GREEN PAL_LINE(GPIOB, 13U)
+#define LINE_ARD_D12 PAL_LINE(GPIOB, 14U)
+#define LINE_ARD_D11 PAL_LINE(GPIOB, 15U)
+#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U)
+#define LINE_ADC1_IN1 PAL_LINE(GPIOC, 0U)
+#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U)
+#define LINE_ADC1_IN2 PAL_LINE(GPIOC, 1U)
+#define LINE_ARD_A3 PAL_LINE(GPIOC, 2U)
+#define LINE_ADC1_IN3 PAL_LINE(GPIOC, 2U)
+#define LINE_ARD_A2 PAL_LINE(GPIOC, 3U)
+#define LINE_ADC1_IN4 PAL_LINE(GPIOC, 3U)
+#define LINE_ARD_D7 PAL_LINE(GPIOC, 7U)
+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
+#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
+#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+#define PIN_ASCR_DISABLED(n) (0U << (n))
+#define PIN_ASCR_ENABLED(n) (1U << (n))
+#define PIN_LOCKR_DISABLED(n) (0U << (n))
+#define PIN_LOCKR_ENABLED(n) (1U << (n))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - ARD_A0 ADC1_IN5 (analog).
+ * PA1 - ARD_A1 ADC1_IN6 (analog).
+ * PA2 - STLINK_TX (alternate 8).
+ * PA3 - STLINK_RX (alternate 8).
+ * PA4 - SMPS_EN (analog).
+ * PA5 - SMPS_V1 (analog).
+ * PA6 - SMPS_PG (analog).
+ * PA7 - SMPS_SW (analog).
+ * PA8 - ARD_D9 (analog).
+ * PA9 - ARD_D1_TX (analog).
+ * PA10 - ARD_D0_RX (analog).
+ * PA11 - ARD_D10 (analog).
+ * PA12 - ARD_D2 (analog).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - ARD_D5 (analog).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_ARD_A0) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_A1) | \
+ PIN_MODE_ALTERNATE(GPIOA_STLINK_TX) | \
+ PIN_MODE_ALTERNATE(GPIOA_STLINK_RX) | \
+ PIN_MODE_ANALOG(GPIOA_SMPS_EN) | \
+ PIN_MODE_ANALOG(GPIOA_SMPS_V1) | \
+ PIN_MODE_ANALOG(GPIOA_SMPS_PG) | \
+ PIN_MODE_ANALOG(GPIOA_SMPS_SW) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_D9) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_D1_TX) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_D0_RX) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_D10) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_D2) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_D5))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_STLINK_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_STLINK_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SMPS_EN) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SMPS_V1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SMPS_PG) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SMPS_SW) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D9) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D10) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D5))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \
+ PIN_OSPEED_MEDIUM(GPIOA_STLINK_TX) | \
+ PIN_OSPEED_MEDIUM(GPIOA_STLINK_RX) | \
+ PIN_OSPEED_HIGH(GPIOA_SMPS_EN) | \
+ PIN_OSPEED_HIGH(GPIOA_SMPS_V1) | \
+ PIN_OSPEED_HIGH(GPIOA_SMPS_PG) | \
+ PIN_OSPEED_HIGH(GPIOA_SMPS_SW) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D9) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D1_TX) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D0_RX) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D10) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \
+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D5))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_ARD_A0) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_A1) | \
+ PIN_PUPDR_FLOATING(GPIOA_STLINK_TX) | \
+ PIN_PUPDR_FLOATING(GPIOA_STLINK_RX) | \
+ PIN_PUPDR_FLOATING(GPIOA_SMPS_EN) | \
+ PIN_PUPDR_FLOATING(GPIOA_SMPS_V1) | \
+ PIN_PUPDR_FLOATING(GPIOA_SMPS_PG) | \
+ PIN_PUPDR_FLOATING(GPIOA_SMPS_SW) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D9) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D1_TX) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D0_RX) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D10) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D2) | \
+ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D5))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \
+ PIN_ODR_HIGH(GPIOA_ARD_A1) | \
+ PIN_ODR_HIGH(GPIOA_STLINK_TX) | \
+ PIN_ODR_HIGH(GPIOA_STLINK_RX) | \
+ PIN_ODR_HIGH(GPIOA_SMPS_EN) | \
+ PIN_ODR_HIGH(GPIOA_SMPS_V1) | \
+ PIN_ODR_HIGH(GPIOA_SMPS_PG) | \
+ PIN_ODR_HIGH(GPIOA_SMPS_SW) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D9) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D1_TX) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D0_RX) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D10) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D2) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D5))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \
+ PIN_AFIO_AF(GPIOA_STLINK_TX, 8U) | \
+ PIN_AFIO_AF(GPIOA_STLINK_RX, 8U) | \
+ PIN_AFIO_AF(GPIOA_SMPS_EN, 0U) | \
+ PIN_AFIO_AF(GPIOA_SMPS_V1, 0U) | \
+ PIN_AFIO_AF(GPIOA_SMPS_PG, 0U) | \
+ PIN_AFIO_AF(GPIOA_SMPS_SW, 0U))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D9, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D1_TX, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D0_RX, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D10, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D5, 0U))
+#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_ARD_A0) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_A1) | \
+ PIN_ASCR_DISABLED(GPIOA_STLINK_TX) | \
+ PIN_ASCR_DISABLED(GPIOA_STLINK_RX) | \
+ PIN_ASCR_DISABLED(GPIOA_SMPS_EN) | \
+ PIN_ASCR_DISABLED(GPIOA_SMPS_V1) | \
+ PIN_ASCR_DISABLED(GPIOA_SMPS_PG) | \
+ PIN_ASCR_DISABLED(GPIOA_SMPS_SW) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D9) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D1_TX) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D0_RX) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D10) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D2) | \
+ PIN_ASCR_DISABLED(GPIOA_SWDIO) | \
+ PIN_ASCR_DISABLED(GPIOA_SWCLK) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D5))
+#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_ARD_A0) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_A1) | \
+ PIN_LOCKR_DISABLED(GPIOA_STLINK_TX) | \
+ PIN_LOCKR_DISABLED(GPIOA_STLINK_RX) | \
+ PIN_LOCKR_DISABLED(GPIOA_SMPS_EN) | \
+ PIN_LOCKR_DISABLED(GPIOA_SMPS_V1) | \
+ PIN_LOCKR_DISABLED(GPIOA_SMPS_PG) | \
+ PIN_LOCKR_DISABLED(GPIOA_SMPS_SW) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D9) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D1_TX) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D0_RX) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D10) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D2) | \
+ PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \
+ PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D5))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - PIN0 (analog).
+ * PB1 - PIN1 (analog).
+ * PB2 - PIN2 (analog).
+ * PB3 - ARD_D3 (analog).
+ * PB4 - PIN4 (analog).
+ * PB5 - ARD_D4 (analog).
+ * PB6 - ARD_D8 (analog).
+ * PB7 - ARD_D14 (analog).
+ * PB8 - ARD_D15 (analog).
+ * PB9 - PIN9 (analog).
+ * PB10 - ARD_D6 (analog).
+ * PB11 - PIN11 (analog).
+ * PB12 - PIN12 (analog).
+ * PB13 - ARD_D13 LED_GREEN (output pushpull maximum).
+ * PB14 - ARD_D12 (analog).
+ * PB15 - ARD_D11 (analog).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \
+ PIN_MODE_ANALOG(GPIOB_PIN1) | \
+ PIN_MODE_ANALOG(GPIOB_PIN2) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D3) | \
+ PIN_MODE_ANALOG(GPIOB_PIN4) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D4) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D8) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D14) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D15) | \
+ PIN_MODE_ANALOG(GPIOB_PIN9) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D6) | \
+ PIN_MODE_ANALOG(GPIOB_PIN11) | \
+ PIN_MODE_ANALOG(GPIOB_PIN12) | \
+ PIN_MODE_OUTPUT(GPIOB_ARD_D13) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D12) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D11))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D3) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D8) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D11))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D3) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D8) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D13) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D12) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D11))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D3) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D4) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D8) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D14) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D15) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D6) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D13) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D12) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D11))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D3) | \
+ PIN_ODR_HIGH(GPIOB_PIN4) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D4) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D8) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D14) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D15) | \
+ PIN_ODR_HIGH(GPIOB_PIN9) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D6) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_LOW(GPIOB_ARD_D13) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D12) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D11))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D3, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D8, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D14, 0U))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D13, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D12, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D11, 0U))
+#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_PIN0) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN1) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D3) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D4) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D8) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D14) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D15) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D6) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D13) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D12) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D11))
+#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_PIN0) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN1) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D3) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D4) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D8) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D14) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D15) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D6) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D13) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D12) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D11))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - ARD_A5 ADC1_IN1 (analog).
+ * PC1 - ARD_A4 ADC1_IN2 (analog).
+ * PC2 - ARD_A3 ADC1_IN3 (analog).
+ * PC3 - ARD_A2 ADC1_IN4 (analog).
+ * PC4 - PIN4 (analog).
+ * PC5 - PIN5 (analog).
+ * PC6 - PIN6 (analog).
+ * PC7 - ARD_D7 (analog).
+ * PC8 - PIN8 (analog).
+ * PC9 - PIN9 (analog).
+ * PC10 - PIN10 (analog).
+ * PC11 - PIN11 (analog).
+ * PC12 - PIN12 (analog).
+ * PC13 - BUTTON (input floating).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_ARD_A5) | \
+ PIN_MODE_ANALOG(GPIOC_ARD_A4) | \
+ PIN_MODE_ANALOG(GPIOC_ARD_A3) | \
+ PIN_MODE_ANALOG(GPIOC_ARD_A2) | \
+ PIN_MODE_ANALOG(GPIOC_PIN4) | \
+ PIN_MODE_ANALOG(GPIOC_PIN5) | \
+ PIN_MODE_ANALOG(GPIOC_PIN6) | \
+ PIN_MODE_ANALOG(GPIOC_ARD_D7) | \
+ PIN_MODE_ANALOG(GPIOC_PIN8) | \
+ PIN_MODE_ANALOG(GPIOC_PIN9) | \
+ PIN_MODE_ANALOG(GPIOC_PIN10) | \
+ PIN_MODE_ANALOG(GPIOC_PIN11) | \
+ PIN_MODE_ANALOG(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_A3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_A2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_D7) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A5) | \
+ PIN_OSPEED_HIGH(GPIOC_ARD_A4) | \
+ PIN_OSPEED_HIGH(GPIOC_ARD_A3) | \
+ PIN_OSPEED_HIGH(GPIOC_ARD_A2) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOC_ARD_D7) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOC_BUTTON) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ARD_A5) | \
+ PIN_PUPDR_FLOATING(GPIOC_ARD_A4) | \
+ PIN_PUPDR_FLOATING(GPIOC_ARD_A3) | \
+ PIN_PUPDR_FLOATING(GPIOC_ARD_A2) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOC_ARD_D7) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A5) | \
+ PIN_ODR_HIGH(GPIOC_ARD_A4) | \
+ PIN_ODR_HIGH(GPIOC_ARD_A3) | \
+ PIN_ODR_HIGH(GPIOC_ARD_A2) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_ARD_D7) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_PIN10) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_PIN12) | \
+ PIN_ODR_HIGH(GPIOC_BUTTON) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_A3, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_A2, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_D7, 0U))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
+#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_ARD_A5) | \
+ PIN_ASCR_DISABLED(GPIOC_ARD_A4) | \
+ PIN_ASCR_DISABLED(GPIOC_ARD_A3) | \
+ PIN_ASCR_DISABLED(GPIOC_ARD_A2) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN5) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN6) | \
+ PIN_ASCR_DISABLED(GPIOC_ARD_D7) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN8) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN10) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOC_BUTTON) | \
+ PIN_ASCR_DISABLED(GPIOC_OSC32_IN) | \
+ PIN_ASCR_DISABLED(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_ARD_A5) | \
+ PIN_LOCKR_DISABLED(GPIOC_ARD_A4) | \
+ PIN_LOCKR_DISABLED(GPIOC_ARD_A3) | \
+ PIN_LOCKR_DISABLED(GPIOC_ARD_A2) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN5) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN6) | \
+ PIN_LOCKR_DISABLED(GPIOC_ARD_D7) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN8) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN10) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOC_BUTTON) | \
+ PIN_LOCKR_DISABLED(GPIOC_OSC32_IN) | \
+ PIN_LOCKR_DISABLED(GPIOC_OSC32_OUT))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (analog).
+ * PD1 - PIN1 (analog).
+ * PD2 - PIN2 (analog).
+ * PD3 - PIN3 (analog).
+ * PD4 - PIN4 (analog).
+ * PD5 - PIN5 (analog).
+ * PD6 - PIN6 (analog).
+ * PD7 - PIN7 (analog).
+ * PD8 - PIN8 (analog).
+ * PD9 - PIN9 (analog).
+ * PD10 - PIN10 (analog).
+ * PD11 - PIN11 (analog).
+ * PD12 - PIN12 (analog).
+ * PD13 - PIN13 (analog).
+ * PD14 - PIN14 (analog).
+ * PD15 - PIN15 (analog).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \
+ PIN_MODE_ANALOG(GPIOD_PIN1) | \
+ PIN_MODE_ANALOG(GPIOD_PIN2) | \
+ PIN_MODE_ANALOG(GPIOD_PIN3) | \
+ PIN_MODE_ANALOG(GPIOD_PIN4) | \
+ PIN_MODE_ANALOG(GPIOD_PIN5) | \
+ PIN_MODE_ANALOG(GPIOD_PIN6) | \
+ PIN_MODE_ANALOG(GPIOD_PIN7) | \
+ PIN_MODE_ANALOG(GPIOD_PIN8) | \
+ PIN_MODE_ANALOG(GPIOD_PIN9) | \
+ PIN_MODE_ANALOG(GPIOD_PIN10) | \
+ PIN_MODE_ANALOG(GPIOD_PIN11) | \
+ PIN_MODE_ANALOG(GPIOD_PIN12) | \
+ PIN_MODE_ANALOG(GPIOD_PIN13) | \
+ PIN_MODE_ANALOG(GPIOD_PIN14) | \
+ PIN_MODE_ANALOG(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))
+#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN1) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN3) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN5) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN6) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN7) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN8) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN10) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN13) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN14) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN15))
+#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_PIN0) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN1) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN3) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN5) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN6) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN7) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN8) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN10) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN13) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN14) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN15))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (analog).
+ * PE1 - PIN1 (analog).
+ * PE2 - PIN2 (analog).
+ * PE3 - PIN3 (analog).
+ * PE4 - PIN4 (analog).
+ * PE5 - PIN5 (analog).
+ * PE6 - PIN6 (analog).
+ * PE7 - PIN7 (analog).
+ * PE8 - PIN8 (analog).
+ * PE9 - PIN9 (analog).
+ * PE10 - PIN10 (analog).
+ * PE11 - PIN11 (analog).
+ * PE12 - PIN12 (analog).
+ * PE13 - PIN13 (analog).
+ * PE14 - PIN14 (analog).
+ * PE15 - PIN15 (analog).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \
+ PIN_MODE_ANALOG(GPIOE_PIN1) | \
+ PIN_MODE_ANALOG(GPIOE_PIN2) | \
+ PIN_MODE_ANALOG(GPIOE_PIN3) | \
+ PIN_MODE_ANALOG(GPIOE_PIN4) | \
+ PIN_MODE_ANALOG(GPIOE_PIN5) | \
+ PIN_MODE_ANALOG(GPIOE_PIN6) | \
+ PIN_MODE_ANALOG(GPIOE_PIN7) | \
+ PIN_MODE_ANALOG(GPIOE_PIN8) | \
+ PIN_MODE_ANALOG(GPIOE_PIN9) | \
+ PIN_MODE_ANALOG(GPIOE_PIN10) | \
+ PIN_MODE_ANALOG(GPIOE_PIN11) | \
+ PIN_MODE_ANALOG(GPIOE_PIN12) | \
+ PIN_MODE_ANALOG(GPIOE_PIN13) | \
+ PIN_MODE_ANALOG(GPIOE_PIN14) | \
+ PIN_MODE_ANALOG(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
+ PIN_ODR_HIGH(GPIOE_PIN1) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_PIN3) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0U))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0U))
+#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN1) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN3) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN5) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN6) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN7) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN8) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN10) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN13) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN14) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN15))
+#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_PIN0) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN1) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN3) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN5) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN6) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN7) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN8) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN10) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN13) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN14) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN15))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - PIN0 (analog).
+ * PF1 - PIN1 (analog).
+ * PF2 - PIN2 (analog).
+ * PF3 - PIN3 (analog).
+ * PF4 - PIN4 (analog).
+ * PF5 - PIN5 (analog).
+ * PF6 - PIN6 (analog).
+ * PF7 - PIN7 (analog).
+ * PF8 - PIN8 (analog).
+ * PF9 - PIN9 (analog).
+ * PF10 - PIN10 (analog).
+ * PF11 - PIN11 (analog).
+ * PF12 - PIN12 (analog).
+ * PF13 - PIN13 (analog).
+ * PF14 - PIN14 (analog).
+ * PF15 - PIN15 (analog).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \
+ PIN_MODE_ANALOG(GPIOF_PIN1) | \
+ PIN_MODE_ANALOG(GPIOF_PIN2) | \
+ PIN_MODE_ANALOG(GPIOF_PIN3) | \
+ PIN_MODE_ANALOG(GPIOF_PIN4) | \
+ PIN_MODE_ANALOG(GPIOF_PIN5) | \
+ PIN_MODE_ANALOG(GPIOF_PIN6) | \
+ PIN_MODE_ANALOG(GPIOF_PIN7) | \
+ PIN_MODE_ANALOG(GPIOF_PIN8) | \
+ PIN_MODE_ANALOG(GPIOF_PIN9) | \
+ PIN_MODE_ANALOG(GPIOF_PIN10) | \
+ PIN_MODE_ANALOG(GPIOF_PIN11) | \
+ PIN_MODE_ANALOG(GPIOF_PIN12) | \
+ PIN_MODE_ANALOG(GPIOF_PIN13) | \
+ PIN_MODE_ANALOG(GPIOF_PIN14) | \
+ PIN_MODE_ANALOG(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0U))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0U))
+#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN1) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN3) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN5) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN6) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN7) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN8) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN10) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN13) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN14) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN15))
+#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_PIN0) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN1) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN3) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN5) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN6) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN7) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN8) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN10) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN13) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN14) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN15))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (analog).
+ * PG1 - PIN1 (analog).
+ * PG2 - PIN2 (analog).
+ * PG3 - PIN3 (analog).
+ * PG4 - PIN4 (analog).
+ * PG5 - PIN5 (analog).
+ * PG6 - PIN6 (analog).
+ * PG7 - PIN7 (analog).
+ * PG8 - PIN8 (analog).
+ * PG9 - PIN9 (analog).
+ * PG10 - PIN10 (analog).
+ * PG11 - PIN11 (analog).
+ * PG12 - PIN12 (analog).
+ * PG13 - PIN13 (analog).
+ * PG14 - PIN14 (analog).
+ * PG15 - PIN15 (analog).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \
+ PIN_MODE_ANALOG(GPIOG_PIN1) | \
+ PIN_MODE_ANALOG(GPIOG_PIN2) | \
+ PIN_MODE_ANALOG(GPIOG_PIN3) | \
+ PIN_MODE_ANALOG(GPIOG_PIN4) | \
+ PIN_MODE_ANALOG(GPIOG_PIN5) | \
+ PIN_MODE_ANALOG(GPIOG_PIN6) | \
+ PIN_MODE_ANALOG(GPIOG_PIN7) | \
+ PIN_MODE_ANALOG(GPIOG_PIN8) | \
+ PIN_MODE_ANALOG(GPIOG_PIN9) | \
+ PIN_MODE_ANALOG(GPIOG_PIN10) | \
+ PIN_MODE_ANALOG(GPIOG_PIN11) | \
+ PIN_MODE_ANALOG(GPIOG_PIN12) | \
+ PIN_MODE_ANALOG(GPIOG_PIN13) | \
+ PIN_MODE_ANALOG(GPIOG_PIN14) | \
+ PIN_MODE_ANALOG(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
+ PIN_ODR_HIGH(GPIOG_PIN1) | \
+ PIN_ODR_HIGH(GPIOG_PIN2) | \
+ PIN_ODR_HIGH(GPIOG_PIN3) | \
+ PIN_ODR_HIGH(GPIOG_PIN4) | \
+ PIN_ODR_HIGH(GPIOG_PIN5) | \
+ PIN_ODR_HIGH(GPIOG_PIN6) | \
+ PIN_ODR_HIGH(GPIOG_PIN7) | \
+ PIN_ODR_HIGH(GPIOG_PIN8) | \
+ PIN_ODR_HIGH(GPIOG_PIN9) | \
+ PIN_ODR_HIGH(GPIOG_PIN10) | \
+ PIN_ODR_HIGH(GPIOG_PIN11) | \
+ PIN_ODR_HIGH(GPIOG_PIN12) | \
+ PIN_ODR_HIGH(GPIOG_PIN13) | \
+ PIN_ODR_HIGH(GPIOG_PIN14) | \
+ PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN7, 0U))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0U))
+#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN1) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN3) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN5) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN6) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN7) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN8) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN10) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN13) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN14) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN15))
+#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_PIN0) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN1) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN3) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN5) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN6) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN7) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN8) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN10) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN13) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN14) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN15))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (analog).
+ * PH3 - PIN3 (analog).
+ * PH4 - PIN4 (analog).
+ * PH5 - PIN5 (analog).
+ * PH6 - PIN6 (analog).
+ * PH7 - PIN7 (analog).
+ * PH8 - PIN8 (analog).
+ * PH9 - PIN9 (analog).
+ * PH10 - PIN10 (analog).
+ * PH11 - PIN11 (analog).
+ * PH12 - PIN12 (analog).
+ * PH13 - PIN13 (analog).
+ * PH14 - PIN14 (analog).
+ * PH15 - PIN15 (analog).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_ANALOG(GPIOH_PIN2) | \
+ PIN_MODE_ANALOG(GPIOH_PIN3) | \
+ PIN_MODE_ANALOG(GPIOH_PIN4) | \
+ PIN_MODE_ANALOG(GPIOH_PIN5) | \
+ PIN_MODE_ANALOG(GPIOH_PIN6) | \
+ PIN_MODE_ANALOG(GPIOH_PIN7) | \
+ PIN_MODE_ANALOG(GPIOH_PIN8) | \
+ PIN_MODE_ANALOG(GPIOH_PIN9) | \
+ PIN_MODE_ANALOG(GPIOH_PIN10) | \
+ PIN_MODE_ANALOG(GPIOH_PIN11) | \
+ PIN_MODE_ANALOG(GPIOH_PIN12) | \
+ PIN_MODE_ANALOG(GPIOH_PIN13) | \
+ PIN_MODE_ANALOG(GPIOH_PIN14) | \
+ PIN_MODE_ANALOG(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \
+ PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0U))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0U))
+#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_OSC_IN) | \
+ PIN_ASCR_DISABLED(GPIOH_OSC_OUT) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN3) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN5) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN6) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN7) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN8) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN10) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN13) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN14) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN15))
+#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_OSC_IN) | \
+ PIN_LOCKR_DISABLED(GPIOH_OSC_OUT) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN3) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN5) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN6) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN7) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN8) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN10) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN13) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN14) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN15))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/board.mk b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/board.mk new file mode 100644 index 0000000..500dd00 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L452RE_P/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L452RE_P
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/cfg/board.chcfg b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/cfg/board.chcfg new file mode 100644 index 0000000..aef8ac3 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/cfg/board.chcfg @@ -0,0 +1,1320 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- STM32L4xx board Template --> +<board + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" + xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32l4xx_board.xsd"> + <configuration_settings> + <templates_path>resources/gencfg/processors/boards/stm32l4xx/templates</templates_path> + <output_path>..</output_path> + <hal_version>5.0.x</hal_version> + </configuration_settings> + <board_name>STMicroelectronics STM32 Nucleo64-L452RE-P</board_name> + <board_id>ST_NUCLEO64_L452RE_P</board_id> + <board_functions></board_functions> + <subtype>STM32L452xx</subtype> + <clocks + HSEFrequency="8000000" + HSEBypass="true" + LSEFrequency="32768" + LSEBypass="false" + LSEDrive="3 High Drive (default)" + VDD="300" /> + <ports> + <GPIOA> + <pin0 + ID="ARD_A0 ADC1_IN5" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="ARD_A1 ADC1_IN6" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="STLINK_TX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="8" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="STLINK_RX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="8" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="SMPS_EN" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="SMPS_V1" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="SMPS_PG" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="SMPS_SW" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="ARD_D9" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="ARD_D1_TX" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="ARD_D0_RX" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="ARD_D10" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="ARD_D2" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="SWDIO" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="SWCLK" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullDown" + Mode="Alternate" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="ARD_D5" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOA> + <GPIOB> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="ARD_D3" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="ARD_D4" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="ARD_D8" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="ARD_D14" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="ARD_D15" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="ARD_D6" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="ARD_D13 LED_GREEN" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="ARD_D12" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="ARD_D11" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOB> + <GPIOC> + <pin0 + ID="ARD_A5 ADC1_IN1" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="ARD_A4 ADC1_IN2" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="ARD_A3 ADC1_IN3" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="ARD_A2 ADC1_IN4" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="ARD_D7" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="BUTTON" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="OSC32_IN" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="OSC32_OUT" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOC> + <GPIOD> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOD> + <GPIOE> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOE> + <GPIOF> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOF> + <GPIOG> + <pin0 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOG> + <GPIOH> + <pin0 + ID="OSC_IN" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="OSC_OUT" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOH> + </ports> +</board> diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/cfg/board.fmpp b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/cfg/board.fmpp new file mode 100644 index 0000000..3c311d3 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L452RE_P/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../tools/ftl/processors/boards/stm32l4xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +} diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/board.c b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/board.c new file mode 100644 index 0000000..cd16e43 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/board.c @@ -0,0 +1,281 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+ uint32_t ascr;
+ uint32_t lockr;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ gpio_setup_t PKData;
+#endif
+} gpio_config_t;
+
+/**
+ * @brief STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR,
+ VAL_GPIOA_LOCKR},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR,
+ VAL_GPIOB_LOCKR},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR,
+ VAL_GPIOC_LOCKR},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR,
+ VAL_GPIOD_LOCKR},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR,
+ VAL_GPIOE_LOCKR},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR,
+ VAL_GPIOF_LOCKR},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR,
+ VAL_GPIOG_LOCKR},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR,
+ VAL_GPIOH_LOCKR},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR,
+ VAL_GPIOI_LOCKR},
+#endif
+#if STM32_HAS_GPIOJ
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR,
+ VAL_GPIOJ_LOCKR},
+#endif
+#if STM32_HAS_GPIOK
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR,
+ VAL_GPIOK_LOCKR}
+#endif
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->ASCR = config->ascr;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+ gpiop->LOCKR = config->lockr;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetAHB2(STM32_GPIO_EN_MASK);
+ rccEnableAHB2(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+ gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+ gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
+ */
+void __early_init(void) {
+
+ stm32_gpio_init();
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* CHTODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @note You can add your board-specific code here.
+ */
+void boardInit(void) {
+
+}
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/board.h b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/board.h new file mode 100644 index 0000000..ff42cd1 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/board.h @@ -0,0 +1,1505 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * Setup for STMicroelectronics STM32 Nucleo64-L476RG board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_NUCLEO64_L476RG
+#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-L476RG"
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768U
+#endif
+
+#define STM32_LSEDRV (3U << 3U)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000U
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 300U
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32L476xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_ARD_A0 0U
+#define GPIOA_ACD12_IN5 0U
+#define GPIOA_ARD_A1 1U
+#define GPIOA_ACD12_IN6 1U
+#define GPIOA_ARD_D1 2U
+#define GPIOA_USART2_TX 2U
+#define GPIOA_ARD_D0 3U
+#define GPIOA_USART2_RX 3U
+#define GPIOA_ARD_A2 4U
+#define GPIOA_ACD12_IN9 4U
+#define GPIOA_ARD_D13 5U
+#define GPIOA_LED_GREEN 5U
+#define GPIOA_ARD_D12 6U
+#define GPIOA_ARD_D11 7U
+#define GPIOA_ARD_D7 8U
+#define GPIOA_ARD_D8 9U
+#define GPIOA_ARD_D2 10U
+#define GPIOA_PIN11 11U
+#define GPIOA_PIN12 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_PIN15 15U
+
+#define GPIOB_ARD_A3 0U
+#define GPIOB_ACD12_IN15 0U
+#define GPIOB_PIN1 1U
+#define GPIOB_PIN2 2U
+#define GPIOB_ARD_D3 3U
+#define GPIOB_SWO 3U
+#define GPIOB_ARD_D5 4U
+#define GPIOB_ARD_D4 5U
+#define GPIOB_ARD_D10 6U
+#define GPIOB_PIN7 7U
+#define GPIOB_ARD_D15 8U
+#define GPIOB_ARD_D14 9U
+#define GPIOB_ARD_D6 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_PIN12 12U
+#define GPIOB_PIN13 13U
+#define GPIOB_PIN14 14U
+#define GPIOB_PIN15 15U
+
+#define GPIOC_ARD_A5 0U
+#define GPIOC_ACD123_IN1 0U
+#define GPIOC_ARD_A4 1U
+#define GPIOC_ACD123_IN2 1U
+#define GPIOC_PIN2 2U
+#define GPIOC_PIN3 3U
+#define GPIOC_PIN4 4U
+#define GPIOC_PIN5 5U
+#define GPIOC_PIN6 6U
+#define GPIOC_ARD_D9 7U
+#define GPIOC_PIN8 8U
+#define GPIOC_PIN9 9U
+#define GPIOC_PIN10 10U
+#define GPIOC_PIN11 11U
+#define GPIOC_PIN12 12U
+#define GPIOC_BUTTON 13U
+#define GPIOC_OSC32_IN 14U
+#define GPIOC_OSC32_OUT 15U
+
+#define GPIOD_PIN0 0U
+#define GPIOD_PIN1 1U
+#define GPIOD_PIN2 2U
+#define GPIOD_PIN3 3U
+#define GPIOD_PIN4 4U
+#define GPIOD_PIN5 5U
+#define GPIOD_PIN6 6U
+#define GPIOD_PIN7 7U
+#define GPIOD_PIN8 8U
+#define GPIOD_PIN9 9U
+#define GPIOD_PIN10 10U
+#define GPIOD_PIN11 11U
+#define GPIOD_PIN12 12U
+#define GPIOD_PIN13 13U
+#define GPIOD_PIN14 14U
+#define GPIOD_PIN15 15U
+
+#define GPIOE_PIN0 0U
+#define GPIOE_PIN1 1U
+#define GPIOE_PIN2 2U
+#define GPIOE_PIN3 3U
+#define GPIOE_PIN4 4U
+#define GPIOE_PIN5 5U
+#define GPIOE_PIN6 6U
+#define GPIOE_PIN7 7U
+#define GPIOE_PIN8 8U
+#define GPIOE_PIN9 9U
+#define GPIOE_PIN10 10U
+#define GPIOE_PIN11 11U
+#define GPIOE_PIN12 12U
+#define GPIOE_PIN13 13U
+#define GPIOE_PIN14 14U
+#define GPIOE_PIN15 15U
+
+#define GPIOF_PIN0 0U
+#define GPIOF_PIN1 1U
+#define GPIOF_PIN2 2U
+#define GPIOF_PIN3 3U
+#define GPIOF_PIN4 4U
+#define GPIOF_PIN5 5U
+#define GPIOF_PIN6 6U
+#define GPIOF_PIN7 7U
+#define GPIOF_PIN8 8U
+#define GPIOF_PIN9 9U
+#define GPIOF_PIN10 10U
+#define GPIOF_PIN11 11U
+#define GPIOF_PIN12 12U
+#define GPIOF_PIN13 13U
+#define GPIOF_PIN14 14U
+#define GPIOF_PIN15 15U
+
+#define GPIOG_PIN0 0U
+#define GPIOG_PIN1 1U
+#define GPIOG_PIN2 2U
+#define GPIOG_PIN3 3U
+#define GPIOG_PIN4 4U
+#define GPIOG_PIN5 5U
+#define GPIOG_PIN6 6U
+#define GPIOG_PIN7 7U
+#define GPIOG_PIN8 8U
+#define GPIOG_PIN9 9U
+#define GPIOG_PIN10 10U
+#define GPIOG_PIN11 11U
+#define GPIOG_PIN12 12U
+#define GPIOG_PIN13 13U
+#define GPIOG_PIN14 14U
+#define GPIOG_PIN15 15U
+
+#define GPIOH_OSC_IN 0U
+#define GPIOH_OSC_OUT 1U
+#define GPIOH_PIN2 2U
+#define GPIOH_PIN3 3U
+#define GPIOH_PIN4 4U
+#define GPIOH_PIN5 5U
+#define GPIOH_PIN6 6U
+#define GPIOH_PIN7 7U
+#define GPIOH_PIN8 8U
+#define GPIOH_PIN9 9U
+#define GPIOH_PIN10 10U
+#define GPIOH_PIN11 11U
+#define GPIOH_PIN12 12U
+#define GPIOH_PIN13 13U
+#define GPIOH_PIN14 14U
+#define GPIOH_PIN15 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U)
+#define LINE_ACD12_IN5 PAL_LINE(GPIOA, 0U)
+#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U)
+#define LINE_ACD12_IN6 PAL_LINE(GPIOA, 1U)
+#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U)
+#define LINE_USART2_TX PAL_LINE(GPIOA, 2U)
+#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U)
+#define LINE_USART2_RX PAL_LINE(GPIOA, 3U)
+#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U)
+#define LINE_ACD12_IN9 PAL_LINE(GPIOA, 4U)
+#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U)
+#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U)
+#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U)
+#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U)
+#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U)
+#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U)
+#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U)
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
+#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U)
+#define LINE_ACD12_IN15 PAL_LINE(GPIOB, 0U)
+#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U)
+#define LINE_SWO PAL_LINE(GPIOB, 3U)
+#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U)
+#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U)
+#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U)
+#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U)
+#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U)
+#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U)
+#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U)
+#define LINE_ACD123_IN1 PAL_LINE(GPIOC, 0U)
+#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U)
+#define LINE_ACD123_IN2 PAL_LINE(GPIOC, 1U)
+#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U)
+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
+#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
+#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+#define PIN_ASCR_DISABLED(n) (0U << (n))
+#define PIN_ASCR_ENABLED(n) (1U << (n))
+#define PIN_LOCKR_DISABLED(n) (0U << (n))
+#define PIN_LOCKR_ENABLED(n) (1U << (n))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - ARD_A0 ACD12_IN5 (analog).
+ * PA1 - ARD_A1 ACD12_IN6 (analog).
+ * PA2 - ARD_D1 USART2_TX (alternate 7).
+ * PA3 - ARD_D0 USART2_RX (alternate 7).
+ * PA4 - ARD_A2 ACD12_IN9 (analog).
+ * PA5 - ARD_D13 LED_GREEN (output pushpull maximum).
+ * PA6 - ARD_D12 (analog).
+ * PA7 - ARD_D11 (analog).
+ * PA8 - ARD_D7 (analog).
+ * PA9 - ARD_D8 (analog).
+ * PA10 - ARD_D2 (analog).
+ * PA11 - PIN11 (analog).
+ * PA12 - PIN12 (analog).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (analog).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_ARD_A0) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_A1) | \
+ PIN_MODE_ALTERNATE(GPIOA_ARD_D1) | \
+ PIN_MODE_ALTERNATE(GPIOA_ARD_D0) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_A2) | \
+ PIN_MODE_OUTPUT(GPIOA_ARD_D13) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_D12) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_D11) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_D7) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_D8) | \
+ PIN_MODE_ANALOG(GPIOA_ARD_D2) | \
+ PIN_MODE_ANALOG(GPIOA_PIN11) | \
+ PIN_MODE_ANALOG(GPIOA_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_ANALOG(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \
+ PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | \
+ PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D7) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D8) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
+ PIN_OSPEED_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_ARD_A0) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_A1) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_A2) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D13) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D12) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D11) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D7) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D8) | \
+ PIN_PUPDR_FLOATING(GPIOA_ARD_D2) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \
+ PIN_ODR_HIGH(GPIOA_ARD_A1) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D1) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D0) | \
+ PIN_ODR_HIGH(GPIOA_ARD_A2) | \
+ PIN_ODR_LOW(GPIOA_ARD_D13) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D12) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D11) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D7) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D8) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D2) | \
+ PIN_ODR_HIGH(GPIOA_PIN11) | \
+ PIN_ODR_HIGH(GPIOA_PIN12) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D1, 7U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D0, 7U) | \
+ PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D11, 0U))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0U))
+#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_ARD_A0) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_A1) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D1) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D0) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_A2) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D13) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D12) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D11) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D7) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D8) | \
+ PIN_ASCR_DISABLED(GPIOA_ARD_D2) | \
+ PIN_ASCR_DISABLED(GPIOA_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOA_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOA_SWDIO) | \
+ PIN_ASCR_DISABLED(GPIOA_SWCLK) | \
+ PIN_ASCR_DISABLED(GPIOA_PIN15))
+#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_ARD_A0) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_A1) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D1) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D0) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_A2) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D13) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D12) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D11) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D7) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D8) | \
+ PIN_LOCKR_DISABLED(GPIOA_ARD_D2) | \
+ PIN_LOCKR_DISABLED(GPIOA_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOA_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \
+ PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \
+ PIN_LOCKR_DISABLED(GPIOA_PIN15))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - ARD_A3 ACD12_IN15 (analog).
+ * PB1 - PIN1 (analog).
+ * PB2 - PIN2 (analog).
+ * PB3 - ARD_D3 SWO (analog).
+ * PB4 - ARD_D5 (analog).
+ * PB5 - ARD_D4 (analog).
+ * PB6 - ARD_D10 (analog).
+ * PB7 - PIN7 (analog).
+ * PB8 - ARD_D15 (analog).
+ * PB9 - ARD_D14 (analog).
+ * PB10 - ARD_D6 (analog).
+ * PB11 - PIN11 (analog).
+ * PB12 - PIN12 (analog).
+ * PB13 - PIN13 (analog).
+ * PB14 - PIN14 (analog).
+ * PB15 - PIN15 (analog).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_ARD_A3) | \
+ PIN_MODE_ANALOG(GPIOB_PIN1) | \
+ PIN_MODE_ANALOG(GPIOB_PIN2) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D3) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D5) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D4) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D10) | \
+ PIN_MODE_ANALOG(GPIOB_PIN7) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D15) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D14) | \
+ PIN_MODE_ANALOG(GPIOB_ARD_D6) | \
+ PIN_MODE_ANALOG(GPIOB_PIN11) | \
+ PIN_MODE_ANALOG(GPIOB_PIN12) | \
+ PIN_MODE_ANALOG(GPIOB_PIN13) | \
+ PIN_MODE_ANALOG(GPIOB_PIN14) | \
+ PIN_MODE_ANALOG(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D3) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_A3) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D3) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D10) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_ARD_A3) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D3) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D5) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D4) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D10) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D15) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D14) | \
+ PIN_PUPDR_FLOATING(GPIOB_ARD_D6) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_A3) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D3) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D5) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D4) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D10) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D15) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D14) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D6) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D3, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0U))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0U))
+#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_ARD_A3) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN1) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D3) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D5) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D4) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D10) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN7) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D15) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D14) | \
+ PIN_ASCR_DISABLED(GPIOB_ARD_D6) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN13) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN14) | \
+ PIN_ASCR_DISABLED(GPIOB_PIN15))
+#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_ARD_A3) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN1) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D3) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D5) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D4) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D10) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN7) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D15) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D14) | \
+ PIN_LOCKR_DISABLED(GPIOB_ARD_D6) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN13) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN14) | \
+ PIN_LOCKR_DISABLED(GPIOB_PIN15))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - ARD_A5 ACD123_IN1 (analog).
+ * PC1 - ARD_A4 ACD123_IN2 (analog).
+ * PC2 - PIN2 (analog).
+ * PC3 - PIN3 (analog).
+ * PC4 - PIN4 (analog).
+ * PC5 - PIN5 (analog).
+ * PC6 - PIN6 (analog).
+ * PC7 - ARD_D9 (analog).
+ * PC8 - PIN8 (analog).
+ * PC9 - PIN9 (analog).
+ * PC10 - PIN10 (analog).
+ * PC11 - PIN11 (analog).
+ * PC12 - PIN12 (analog).
+ * PC13 - BUTTON (input floating).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_ARD_A5) | \
+ PIN_MODE_ANALOG(GPIOC_ARD_A4) | \
+ PIN_MODE_ANALOG(GPIOC_PIN2) | \
+ PIN_MODE_ANALOG(GPIOC_PIN3) | \
+ PIN_MODE_ANALOG(GPIOC_PIN4) | \
+ PIN_MODE_ANALOG(GPIOC_PIN5) | \
+ PIN_MODE_ANALOG(GPIOC_PIN6) | \
+ PIN_MODE_ANALOG(GPIOC_ARD_D9) | \
+ PIN_MODE_ANALOG(GPIOC_PIN8) | \
+ PIN_MODE_ANALOG(GPIOC_PIN9) | \
+ PIN_MODE_ANALOG(GPIOC_PIN10) | \
+ PIN_MODE_ANALOG(GPIOC_PIN11) | \
+ PIN_MODE_ANALOG(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_D9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A5) | \
+ PIN_OSPEED_HIGH(GPIOC_ARD_A4) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOC_ARD_D9) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOC_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOC_BUTTON) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ARD_A5) | \
+ PIN_PUPDR_FLOATING(GPIOC_ARD_A4) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOC_ARD_D9) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A5) | \
+ PIN_ODR_HIGH(GPIOC_ARD_A4) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PIN3) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_ARD_D9) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_PIN10) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_PIN12) | \
+ PIN_ODR_HIGH(GPIOC_BUTTON) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_D9, 0U))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
+#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_ARD_A5) | \
+ PIN_ASCR_DISABLED(GPIOC_ARD_A4) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN3) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN5) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN6) | \
+ PIN_ASCR_DISABLED(GPIOC_ARD_D9) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN8) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN10) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOC_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOC_BUTTON) | \
+ PIN_ASCR_DISABLED(GPIOC_OSC32_IN) | \
+ PIN_ASCR_DISABLED(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_ARD_A5) | \
+ PIN_LOCKR_DISABLED(GPIOC_ARD_A4) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN3) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN5) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN6) | \
+ PIN_LOCKR_DISABLED(GPIOC_ARD_D9) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN8) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN10) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOC_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOC_BUTTON) | \
+ PIN_LOCKR_DISABLED(GPIOC_OSC32_IN) | \
+ PIN_LOCKR_DISABLED(GPIOC_OSC32_OUT))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (analog).
+ * PD1 - PIN1 (analog).
+ * PD2 - PIN2 (analog).
+ * PD3 - PIN3 (analog).
+ * PD4 - PIN4 (analog).
+ * PD5 - PIN5 (analog).
+ * PD6 - PIN6 (analog).
+ * PD7 - PIN7 (analog).
+ * PD8 - PIN8 (analog).
+ * PD9 - PIN9 (analog).
+ * PD10 - PIN10 (analog).
+ * PD11 - PIN11 (analog).
+ * PD12 - PIN12 (analog).
+ * PD13 - PIN13 (analog).
+ * PD14 - PIN14 (analog).
+ * PD15 - PIN15 (analog).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \
+ PIN_MODE_ANALOG(GPIOD_PIN1) | \
+ PIN_MODE_ANALOG(GPIOD_PIN2) | \
+ PIN_MODE_ANALOG(GPIOD_PIN3) | \
+ PIN_MODE_ANALOG(GPIOD_PIN4) | \
+ PIN_MODE_ANALOG(GPIOD_PIN5) | \
+ PIN_MODE_ANALOG(GPIOD_PIN6) | \
+ PIN_MODE_ANALOG(GPIOD_PIN7) | \
+ PIN_MODE_ANALOG(GPIOD_PIN8) | \
+ PIN_MODE_ANALOG(GPIOD_PIN9) | \
+ PIN_MODE_ANALOG(GPIOD_PIN10) | \
+ PIN_MODE_ANALOG(GPIOD_PIN11) | \
+ PIN_MODE_ANALOG(GPIOD_PIN12) | \
+ PIN_MODE_ANALOG(GPIOD_PIN13) | \
+ PIN_MODE_ANALOG(GPIOD_PIN14) | \
+ PIN_MODE_ANALOG(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))
+#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN1) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN3) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN5) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN6) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN7) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN8) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN10) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN13) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN14) | \
+ PIN_ASCR_DISABLED(GPIOD_PIN15))
+#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_PIN0) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN1) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN3) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN5) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN6) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN7) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN8) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN10) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN13) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN14) | \
+ PIN_LOCKR_DISABLED(GPIOD_PIN15))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (analog).
+ * PE1 - PIN1 (analog).
+ * PE2 - PIN2 (analog).
+ * PE3 - PIN3 (analog).
+ * PE4 - PIN4 (analog).
+ * PE5 - PIN5 (analog).
+ * PE6 - PIN6 (analog).
+ * PE7 - PIN7 (analog).
+ * PE8 - PIN8 (analog).
+ * PE9 - PIN9 (analog).
+ * PE10 - PIN10 (analog).
+ * PE11 - PIN11 (analog).
+ * PE12 - PIN12 (analog).
+ * PE13 - PIN13 (analog).
+ * PE14 - PIN14 (analog).
+ * PE15 - PIN15 (analog).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \
+ PIN_MODE_ANALOG(GPIOE_PIN1) | \
+ PIN_MODE_ANALOG(GPIOE_PIN2) | \
+ PIN_MODE_ANALOG(GPIOE_PIN3) | \
+ PIN_MODE_ANALOG(GPIOE_PIN4) | \
+ PIN_MODE_ANALOG(GPIOE_PIN5) | \
+ PIN_MODE_ANALOG(GPIOE_PIN6) | \
+ PIN_MODE_ANALOG(GPIOE_PIN7) | \
+ PIN_MODE_ANALOG(GPIOE_PIN8) | \
+ PIN_MODE_ANALOG(GPIOE_PIN9) | \
+ PIN_MODE_ANALOG(GPIOE_PIN10) | \
+ PIN_MODE_ANALOG(GPIOE_PIN11) | \
+ PIN_MODE_ANALOG(GPIOE_PIN12) | \
+ PIN_MODE_ANALOG(GPIOE_PIN13) | \
+ PIN_MODE_ANALOG(GPIOE_PIN14) | \
+ PIN_MODE_ANALOG(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
+ PIN_ODR_HIGH(GPIOE_PIN1) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_PIN3) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0U))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0U))
+#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN1) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN3) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN5) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN6) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN7) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN8) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN10) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN13) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN14) | \
+ PIN_ASCR_DISABLED(GPIOE_PIN15))
+#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_PIN0) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN1) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN3) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN5) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN6) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN7) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN8) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN10) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN13) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN14) | \
+ PIN_LOCKR_DISABLED(GPIOE_PIN15))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - PIN0 (analog).
+ * PF1 - PIN1 (analog).
+ * PF2 - PIN2 (analog).
+ * PF3 - PIN3 (analog).
+ * PF4 - PIN4 (analog).
+ * PF5 - PIN5 (analog).
+ * PF6 - PIN6 (analog).
+ * PF7 - PIN7 (analog).
+ * PF8 - PIN8 (analog).
+ * PF9 - PIN9 (analog).
+ * PF10 - PIN10 (analog).
+ * PF11 - PIN11 (analog).
+ * PF12 - PIN12 (analog).
+ * PF13 - PIN13 (analog).
+ * PF14 - PIN14 (analog).
+ * PF15 - PIN15 (analog).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \
+ PIN_MODE_ANALOG(GPIOF_PIN1) | \
+ PIN_MODE_ANALOG(GPIOF_PIN2) | \
+ PIN_MODE_ANALOG(GPIOF_PIN3) | \
+ PIN_MODE_ANALOG(GPIOF_PIN4) | \
+ PIN_MODE_ANALOG(GPIOF_PIN5) | \
+ PIN_MODE_ANALOG(GPIOF_PIN6) | \
+ PIN_MODE_ANALOG(GPIOF_PIN7) | \
+ PIN_MODE_ANALOG(GPIOF_PIN8) | \
+ PIN_MODE_ANALOG(GPIOF_PIN9) | \
+ PIN_MODE_ANALOG(GPIOF_PIN10) | \
+ PIN_MODE_ANALOG(GPIOF_PIN11) | \
+ PIN_MODE_ANALOG(GPIOF_PIN12) | \
+ PIN_MODE_ANALOG(GPIOF_PIN13) | \
+ PIN_MODE_ANALOG(GPIOF_PIN14) | \
+ PIN_MODE_ANALOG(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN2) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN7) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN9) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN11) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN12) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN14) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0U))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0U))
+#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN1) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN3) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN5) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN6) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN7) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN8) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN10) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN13) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN14) | \
+ PIN_ASCR_DISABLED(GPIOF_PIN15))
+#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_PIN0) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN1) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN3) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN5) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN6) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN7) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN8) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN10) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN13) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN14) | \
+ PIN_LOCKR_DISABLED(GPIOF_PIN15))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (analog).
+ * PG1 - PIN1 (analog).
+ * PG2 - PIN2 (analog).
+ * PG3 - PIN3 (analog).
+ * PG4 - PIN4 (analog).
+ * PG5 - PIN5 (analog).
+ * PG6 - PIN6 (analog).
+ * PG7 - PIN7 (analog).
+ * PG8 - PIN8 (analog).
+ * PG9 - PIN9 (analog).
+ * PG10 - PIN10 (analog).
+ * PG11 - PIN11 (analog).
+ * PG12 - PIN12 (analog).
+ * PG13 - PIN13 (analog).
+ * PG14 - PIN14 (analog).
+ * PG15 - PIN15 (analog).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \
+ PIN_MODE_ANALOG(GPIOG_PIN1) | \
+ PIN_MODE_ANALOG(GPIOG_PIN2) | \
+ PIN_MODE_ANALOG(GPIOG_PIN3) | \
+ PIN_MODE_ANALOG(GPIOG_PIN4) | \
+ PIN_MODE_ANALOG(GPIOG_PIN5) | \
+ PIN_MODE_ANALOG(GPIOG_PIN6) | \
+ PIN_MODE_ANALOG(GPIOG_PIN7) | \
+ PIN_MODE_ANALOG(GPIOG_PIN8) | \
+ PIN_MODE_ANALOG(GPIOG_PIN9) | \
+ PIN_MODE_ANALOG(GPIOG_PIN10) | \
+ PIN_MODE_ANALOG(GPIOG_PIN11) | \
+ PIN_MODE_ANALOG(GPIOG_PIN12) | \
+ PIN_MODE_ANALOG(GPIOG_PIN13) | \
+ PIN_MODE_ANALOG(GPIOG_PIN14) | \
+ PIN_MODE_ANALOG(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
+ PIN_ODR_HIGH(GPIOG_PIN1) | \
+ PIN_ODR_HIGH(GPIOG_PIN2) | \
+ PIN_ODR_HIGH(GPIOG_PIN3) | \
+ PIN_ODR_HIGH(GPIOG_PIN4) | \
+ PIN_ODR_HIGH(GPIOG_PIN5) | \
+ PIN_ODR_HIGH(GPIOG_PIN6) | \
+ PIN_ODR_HIGH(GPIOG_PIN7) | \
+ PIN_ODR_HIGH(GPIOG_PIN8) | \
+ PIN_ODR_HIGH(GPIOG_PIN9) | \
+ PIN_ODR_HIGH(GPIOG_PIN10) | \
+ PIN_ODR_HIGH(GPIOG_PIN11) | \
+ PIN_ODR_HIGH(GPIOG_PIN12) | \
+ PIN_ODR_HIGH(GPIOG_PIN13) | \
+ PIN_ODR_HIGH(GPIOG_PIN14) | \
+ PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN7, 0U))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0U))
+#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN1) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN3) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN5) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN6) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN7) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN8) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN10) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN13) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN14) | \
+ PIN_ASCR_DISABLED(GPIOG_PIN15))
+#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_PIN0) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN1) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN3) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN5) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN6) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN7) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN8) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN10) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN13) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN14) | \
+ PIN_LOCKR_DISABLED(GPIOG_PIN15))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (analog).
+ * PH3 - PIN3 (analog).
+ * PH4 - PIN4 (analog).
+ * PH5 - PIN5 (analog).
+ * PH6 - PIN6 (analog).
+ * PH7 - PIN7 (analog).
+ * PH8 - PIN8 (analog).
+ * PH9 - PIN9 (analog).
+ * PH10 - PIN10 (analog).
+ * PH11 - PIN11 (analog).
+ * PH12 - PIN12 (analog).
+ * PH13 - PIN13 (analog).
+ * PH14 - PIN14 (analog).
+ * PH15 - PIN15 (analog).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_ANALOG(GPIOH_PIN2) | \
+ PIN_MODE_ANALOG(GPIOH_PIN3) | \
+ PIN_MODE_ANALOG(GPIOH_PIN4) | \
+ PIN_MODE_ANALOG(GPIOH_PIN5) | \
+ PIN_MODE_ANALOG(GPIOH_PIN6) | \
+ PIN_MODE_ANALOG(GPIOH_PIN7) | \
+ PIN_MODE_ANALOG(GPIOH_PIN8) | \
+ PIN_MODE_ANALOG(GPIOH_PIN9) | \
+ PIN_MODE_ANALOG(GPIOH_PIN10) | \
+ PIN_MODE_ANALOG(GPIOH_PIN11) | \
+ PIN_MODE_ANALOG(GPIOH_PIN12) | \
+ PIN_MODE_ANALOG(GPIOH_PIN13) | \
+ PIN_MODE_ANALOG(GPIOH_PIN14) | \
+ PIN_MODE_ANALOG(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \
+ PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0U))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0U))
+#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_OSC_IN) | \
+ PIN_ASCR_DISABLED(GPIOH_OSC_OUT) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN2) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN3) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN4) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN5) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN6) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN7) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN8) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN9) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN10) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN11) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN12) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN13) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN14) | \
+ PIN_ASCR_DISABLED(GPIOH_PIN15))
+#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_OSC_IN) | \
+ PIN_LOCKR_DISABLED(GPIOH_OSC_OUT) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN2) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN3) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN4) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN5) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN6) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN7) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN8) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN9) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN10) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN11) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN12) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN13) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN14) | \
+ PIN_LOCKR_DISABLED(GPIOH_PIN15))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/board.mk b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/board.mk new file mode 100644 index 0000000..3938fc5 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L476RG/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L476RG
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/cfg/board.chcfg b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/cfg/board.chcfg new file mode 100644 index 0000000..5cdbd96 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/cfg/board.chcfg @@ -0,0 +1,1320 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- STM32L4xx board Template --> +<board + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" + xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32l4xx_board.xsd"> + <configuration_settings> + <templates_path>resources/gencfg/processors/boards/stm32l4xx/templates</templates_path> + <output_path>..</output_path> + <hal_version>5.0.x</hal_version> + </configuration_settings> + <board_name>STMicroelectronics STM32 Nucleo64-L476RG</board_name> + <board_id>ST_NUCLEO64_L476RG</board_id> + <board_functions></board_functions> + <subtype>STM32L476xx</subtype> + <clocks + HSEFrequency="8000000" + HSEBypass="true" + LSEFrequency="32768" + LSEBypass="false" + LSEDrive="3 High Drive (default)" + VDD="300" /> + <ports> + <GPIOA> + <pin0 + ID="ARD_A0 ACD12_IN5" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="ARD_A1 ACD12_IN6" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="ARD_D1 USART2_TX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="7" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="ARD_D0 USART2_RX" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="7" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="ARD_A2 ACD12_IN9" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="ARD_D13 LED_GREEN" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="ARD_D12" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="ARD_D11" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="ARD_D7" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="ARD_D8" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="ARD_D2" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="SWDIO" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="SWCLK" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullDown" + Mode="Alternate" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOA> + <GPIOB> + <pin0 + ID="ARD_A3 ACD12_IN15" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="ARD_D3 SWO" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="ARD_D5" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="ARD_D4" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="ARD_D10" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="ARD_D15" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="ARD_D14" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="ARD_D6" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOB> + <GPIOC> + <pin0 + ID="ARD_A5 ACD123_IN1" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="ARD_A4 ACD123_IN2" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="ARD_D9" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="BUTTON" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="OSC32_IN" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="OSC32_OUT" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOC> + <GPIOD> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOD> + <GPIOE> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOE> + <GPIOF> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOF> + <GPIOG> + <pin0 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOG> + <GPIOH> + <pin0 + ID="OSC_IN" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin1 + ID="OSC_OUT" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Analog" + Alternate="0" + AnalogSwitch="Disabled" + PinLock="Disabled" /> + </GPIOH> + </ports> +</board> diff --git a/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/cfg/board.fmpp b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/cfg/board.fmpp new file mode 100644 index 0000000..3c311d3 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/ST_NUCLEO64_L476RG/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../tools/ftl/processors/boards/stm32l4xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +} diff --git a/ChibiOS_20.3.2/os/hal/boards/genboard.sh b/ChibiOS_20.3.2/os/hal/boards/genboard.sh new file mode 100644 index 0000000..8e8a112 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/genboard.sh @@ -0,0 +1,17 @@ +#!/bin/bash +if [ $# -eq 1 ] +then + echo "Processing: $1" + if ! fmpp -q -C $1/cfg/board.fmpp + then + echo + echo "aborted" + exit 1 + else + echo + echo "done" + exit 0 + fi +else + echo "Usage: genboard <board_directory>" +fi diff --git a/ChibiOS_20.3.2/os/hal/boards/genboards.sh b/ChibiOS_20.3.2/os/hal/boards/genboards.sh new file mode 100644 index 0000000..91b6cc6 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/genboards.sh @@ -0,0 +1,18 @@ +#!/bin/bash +if [ $# -eq 0 ] +then + find . -name board.fmpp -exec bash genboards.sh '{}' \; +elif [ $# -eq 1 ] +then + path=$(readlink -f $(dirname $1)) + echo "Processing: $1" + cd $path + if ! fmpp -q -C board.fmpp + then + echo + echo "aborted" + exit 1 + fi +else + echo "illegal number of arguments" +fi diff --git a/ChibiOS_20.3.2/os/hal/boards/readme.txt b/ChibiOS_20.3.2/os/hal/boards/readme.txt new file mode 100644 index 0000000..c033834 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/boards/readme.txt @@ -0,0 +1,17 @@ +This directory contains the support files for various board models. If you
+want to support a new board:
+- Create a new directory under ./os/hal/boards, give it the name of your board.
+- Copy inside the new directory the files from a similar board.
+- Customize board.c, board.h and board.mk in order to correctly initialize
+ your board.
+
+The files in those board directories containing:
+- <board>/cfg/board.chcfg
+- <board>/cfg/board.fmpp
+are generated automatically, just run the "fmpp" tool from within <board>/cfg,
+the download is available here: http://fmpp.sourceforge.net, note, it
+requires Java.
+
+All board files can be batch-regenerated automatically by running the
+genboards.sh script in this same directory.
+
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c b/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c index 2b85dbd..bba3fee 100644 --- a/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c @@ -197,7 +197,7 @@ static void adc_lld_stop_adc(ADCDriver *adcp) { while (adcp->adcm->CR & ADC_CR_ADSTP)
;
}
-#if !defined(STM32H723xx) || STM32_ADC_USE_ADC3 == FALSE
+#if (STM32_ADC_USE_ADC12 == TRUE)
adcp->adcm->PCSEL = 0U;
#endif
}
@@ -406,7 +406,7 @@ void adc_lld_init(void) { #if STM32_ADC_USE_ADC3 == TRUE
rccEnableADC3(true);
rccResetADC3();
- ADC3_COMMON->CCR = STM32_ADC_ADC3_CLOCK_MODE | STM32_ADC_ADC3_PRESC;
+ ADC3_COMMON->CCR = STM32_ADC_ADC3_CLOCK_MODE;
rccDisableADC3();
#endif
#endif
@@ -538,7 +538,7 @@ void adc_lld_stop(ADCDriver *adcp) { adcp->data.bdma = NULL;
/* Resetting CCR options except default ones.*/
- adcp->adcc->CCR = STM32_ADC_ADC3_CLOCK_MODE | STM32_ADC_ADC3_PRESC;
+ adcp->adcc->CCR = STM32_ADC_ADC3_CLOCK_MODE;
rccDisableADC3();
}
#endif
@@ -639,10 +639,10 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->adcm->PCSEL = grpp->pcsel;
adcp->adcm->LTR1 = grpp->ltr1;
adcp->adcm->HTR1 = grpp->htr1;
- adcp->adcm->LTR2 = grpp->ltr2;
- adcp->adcm->HTR2 = grpp->htr2;
- adcp->adcm->LTR3 = grpp->ltr3;
- adcp->adcm->HTR3 = grpp->htr3;
+ adcp->adcm->LTR1 = grpp->ltr2;
+ adcp->adcm->HTR1 = grpp->htr2;
+ adcp->adcm->LTR1 = grpp->ltr3;
+ adcp->adcm->HTR1 = grpp->htr3;
adcp->adcm->SMPR1 = grpp->smpr[0];
adcp->adcm->SMPR2 = grpp->smpr[1];
adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
@@ -653,10 +653,10 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->adcs->PCSEL = grpp->pcsel;
adcp->adcs->LTR1 = grpp->ltr1;
adcp->adcs->HTR1 = grpp->htr1;
- adcp->adcs->LTR2 = grpp->ltr2;
- adcp->adcs->HTR2 = grpp->htr2;
- adcp->adcs->LTR3 = grpp->ltr3;
- adcp->adcs->HTR3 = grpp->htr3;
+ adcp->adcs->LTR1 = grpp->ltr2;
+ adcp->adcs->HTR1 = grpp->htr2;
+ adcp->adcs->LTR1 = grpp->ltr3;
+ adcp->adcs->HTR1 = grpp->htr3;
adcp->adcs->SMPR1 = grpp->ssmpr[0];
adcp->adcs->SMPR2 = grpp->ssmpr[1];
adcp->adcs->SQR1 = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
@@ -678,15 +678,15 @@ void adc_lld_start_conversion(ADCDriver *adcp) { #endif
{
adcp->adcm->CFGR2 = grpp->cfgr2;
-#if !defined(STM32H723xx) || STM32_ADC_USE_ADC3 == FALSE
+#if (STM32_ADC_USE_ADC12 == TRUE)
adcp->adcm->PCSEL = grpp->pcsel;
#endif
adcp->adcm->LTR1 = grpp->ltr1;
adcp->adcm->HTR1 = grpp->htr1;
- adcp->adcm->LTR2 = grpp->ltr2;
- adcp->adcm->HTR2 = grpp->htr2;
- adcp->adcm->LTR3 = grpp->ltr3;
- adcp->adcm->HTR3 = grpp->htr3;
+ adcp->adcm->LTR1 = grpp->ltr2;
+ adcp->adcm->HTR1 = grpp->htr2;
+ adcp->adcm->LTR1 = grpp->ltr3;
+ adcp->adcm->HTR1 = grpp->htr3;
adcp->adcm->SMPR1 = grpp->smpr[0];
adcp->adcm->SMPR2 = grpp->smpr[1];
adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h b/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h index 5f3cf46..2740421 100644 --- a/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h @@ -547,12 +547,6 @@ typedef union { /* Driver macros. */
/*===========================================================================*/
-#if STM32_ADC_USE_ADC12 == TRUE
-typedef ADC12_TypeDef ADC_TypeDef;
-#else
-typedef ADC3_TypeDef ADC_TypeDef;
-#endif
-
/**
* @brief Low level fields of the ADC driver structure.
*/
@@ -568,10 +562,20 @@ typedef ADC3_TypeDef ADC_TypeDef; adc_ldd_dma_reference_t data; \
/* DMA mode bit mask.*/ \
uint32_t dmamode
+#elif (STM32_ADC_USE_ADC3 == TRUE)
+#define adc_lld_driver_fields \
+ /* Pointer to the master ADCx registers block.*/ \
+ ADC3_TypeDef *adcm; \
+ /* Pointer to the slave ADCx registers block.*/ \
+ ADC_Common_TypeDef *adcc; \
+ /* Pointer to associated DMA channel.*/ \
+ adc_ldd_dma_reference_t data; \
+ /* DMA mode bit mask.*/ \
+ uint32_t dmamode
#else
#define adc_lld_driver_fields \
/* Pointer to the master ADCx registers block.*/ \
- ADC_TypeDef *adcm; \
+ ADC12_TypeDef *adcm; \
/* Pointer to the slave ADCx registers block.*/ \
ADC_Common_TypeDef *adcc; \
/* Pointer to associated DMA channel.*/ \
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c b/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c index 1b32a82..b4180d3 100644 --- a/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c @@ -283,7 +283,7 @@ static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) { if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
/* DMA errors handling.*/
- //dac_lld_stop_conversion(dacp);
+ dac_lld_stop_conversion(dacp);
_dac_isr_error_code(dacp, DAC_ERR_DMAFAILURE);
}
else {
@@ -654,52 +654,52 @@ void dac_lld_start_conversion(DACDriver *dacp) { dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
break;
-// case DAC_DHRM_12BIT_LEFT:
-// osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
-//
-// dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12L1 +
-// dacp->params->dataoffset);
-// dmamode = dacp->params->dmamode |
-// STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-// break;
-// case DAC_DHRM_8BIT_RIGHT:
-// osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
-//
-// dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8R1 +
-// dacp->params->dataoffset);
-// dmamode = dacp->params->dmamode |
-// STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
-//
-// /* In this mode the size of the buffer is halved because two samples
-// packed in a single dacsample_t element.*/
-// n = (n + 1) / 2;
-// break;
-//#if STM32_DAC_DUAL_MODE == TRUE
-// case DAC_DHRM_12BIT_RIGHT_DUAL:
-// osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
-//
-// dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12RD);
-// dmamode = dacp->params->dmamode |
-// STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
-// n /= 2;
-// break;
-// case DAC_DHRM_12BIT_LEFT_DUAL:
-// osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
-//
-// dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12LD);
-// dmamode = dacp->params->dmamode |
-// STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
-// n /= 2;
-// break;
-// case DAC_DHRM_8BIT_RIGHT_DUAL:
-// osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
-//
-// dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8RD);
-// dmamode = dacp->params->dmamode |
-// STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-// n /= 2;
-// break;
-//#endif
+ case DAC_DHRM_12BIT_LEFT:
+ osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
+
+ dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12L1 +
+ dacp->params->dataoffset);
+ dmamode = dacp->params->dmamode |
+ STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+ break;
+ case DAC_DHRM_8BIT_RIGHT:
+ osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
+
+ dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8R1 +
+ dacp->params->dataoffset);
+ dmamode = dacp->params->dmamode |
+ STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
+
+ /* In this mode the size of the buffer is halved because two samples
+ packed in a single dacsample_t element.*/
+ n = (n + 1) / 2;
+ break;
+#if STM32_DAC_DUAL_MODE == TRUE
+ case DAC_DHRM_12BIT_RIGHT_DUAL:
+ osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
+
+ dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12RD);
+ dmamode = dacp->params->dmamode |
+ STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
+ n /= 2;
+ break;
+ case DAC_DHRM_12BIT_LEFT_DUAL:
+ osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
+
+ dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12LD);
+ dmamode = dacp->params->dmamode |
+ STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
+ n /= 2;
+ break;
+ case DAC_DHRM_8BIT_RIGHT_DUAL:
+ osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
+
+ dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8RD);
+ dmamode = dacp->params->dmamode |
+ STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
+ n /= 2;
+ break;
+#endif
default:
osalDbgAssert(false, "unexpected DAC mode");
return;
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c.bak b/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c.bak deleted file mode 100644 index 02aefc8..0000000 --- a/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c.bak +++ /dev/null @@ -1,735 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file DACv1/hal_dac_lld.c
- * @brief STM32 DAC subsystem low level driver source.
- *
- * @addtogroup DAC
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_DAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/* Because ST headers naming inconsistencies.*/
-#if !defined(DAC1)
-#define DAC1 DAC
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief DAC1 CH1 driver identifier.*/
-#if STM32_DAC_USE_DAC1_CH1 || defined(__DOXYGEN__)
-DACDriver DACD1;
-#endif
-
-///** @brief DAC1 CH2 driver identifier.*/
-//#if (STM32_DAC_USE_DAC1_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
-//DACDriver DACD2;
-//#endif
-//
-///** @brief DAC2 CH1 driver identifier.*/
-//#if STM32_DAC_USE_DAC2_CH1 || defined(__DOXYGEN__)
-//DACDriver DACD3;
-//#endif
-//
-///** @brief DAC2 CH2 driver identifier.*/
-//#if (STM32_DAC_USE_DAC2_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
-//DACDriver DACD4;
-//#endif
-//
-///** @brief DAC3 CH1 driver identifier.*/
-//#if STM32_DAC_USE_DAC3_CH1 || defined(__DOXYGEN__)
-//DACDriver DACD5;
-//#endif
-//
-///** @brief DAC3 CH2 driver identifier.*/
-//#if (STM32_DAC_USE_DAC3_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
-//DACDriver DACD6;
-//#endif
-//
-///** @brief DAC4 CH1 driver identifier.*/
-//#if STM32_DAC_USE_DAC4_CH1 || defined(__DOXYGEN__)
-//DACDriver DACD7;
-//#endif
-//
-///** @brief DAC4 CH2 driver identifier.*/
-//#if (STM32_DAC_USE_DAC4_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
-//DACDriver DACD8;
-//#endif
-
-/*===========================================================================*/
-/* Driver local variables. */
-/*===========================================================================*/
-
-#if STM32_DAC_USE_DAC1_CH1 == TRUE
-static const dacparams_t dac1_ch1_params = {
- .dac = DAC1,
- .dataoffset = 0U,
- .regshift = 0U,
- .regmask = 0xFFFF0000U,
- .dmastream = STM32_DAC_DAC1_CH1_BDMA_STREAM,
-#if STM32_DMA_SUPPORTS_DMAMUX
- .peripheral = STM32_DMAMUX1_DAC1_CH1,
-#endif
- .dmamode = STM32_BDMA_CR_MSIZE_HWORD | STM32_BDMA_CR_PSIZE_WORD |
- STM32_BDMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) |
- STM32_BDMA_CR_DIR_M2P |
- STM32_BDMA_CR_MINC | STM32_BDMA_CR_TCIE | STM32_BDMA_CR_HTIE |
- STM32_BDMA_CR_TEIE | STM32_BDMA_CR_CIRC,
- .dmairqprio = STM32_DAC_DAC1_CH1_IRQ_PRIORITY
-};
-#endif
-
-//#if STM32_DAC_USE_DAC1_CH2 == TRUE
-//static const dacparams_t dac1_ch2_params = {
-// .dac = DAC1,
-// .dataoffset = CHANNEL_DATA_OFFSET,
-// .regshift = 16U,
-// .regmask = 0x0000FFFFU,
-// .dmastream = STM32_DAC_DAC1_CH2_DMA_STREAM,
-//#if STM32_DMA_SUPPORTS_DMAMUX
-// .peripheral = STM32_DMAMUX1_DAC1_CH2,
-//#endif
-// .dmamode = STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
-// STM32_DMA_CR_PL(STM32_DAC_DAC1_CH2_DMA_PRIORITY) |
-// STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
-// STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
-// STM32_DMA_CR_TCIE,
-// .dmairqprio = STM32_DAC_DAC1_CH2_IRQ_PRIORITY
-//};
-//#endif
-//
-//#if STM32_DAC_USE_DAC2_CH1 == TRUE
-//static const dacparams_t dac2_ch1_params = {
-// .dac = DAC2,
-// .dataoffset = 0U,
-// .regshift = 0U,
-// .regmask = 0xFFFF0000U,
-// .dmastream = STM32_DAC_DAC2_CH1_DMA_STREAM,
-//#if STM32_DMA_SUPPORTS_DMAMUX
-// .peripheral = STM32_DMAMUX1_DAC2_CH1,
-//#endif
-// .dmamode = STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
-// STM32_DMA_CR_PL(STM32_DAC_DAC2_CH1_DMA_PRIORITY) |
-// STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
-// STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
-// STM32_DMA_CR_TCIE,
-// .dmairqprio = STM32_DAC_DAC2_CH1_IRQ_PRIORITY
-//};
-//#endif
-//
-//#if STM32_DAC_USE_DAC2_CH2 == TRUE
-//static const dacparams_t dac2_ch2_params = {
-// .dac = DAC2,
-// .dataoffset = CHANNEL_DATA_OFFSET,
-// .regshift = 16U,
-// .regmask = 0x0000FFFFU,
-// .dmastream = STM32_DAC_DAC2_CH2_DMA_STREAM,
-//#if STM32_DMA_SUPPORTS_DMAMUX
-// .peripheral = STM32_DMAMUX1_DAC2_CH2,
-//#endif
-// .dmamode = STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
-// STM32_DMA_CR_PL(STM32_DAC_DAC2_CH2_DMA_PRIORITY) |
-// STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
-// STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
-// STM32_DMA_CR_TCIE,
-// .dmairqprio = STM32_DAC_DAC2_CH2_IRQ_PRIORITY
-//};
-//#endif
-//
-//#if STM32_DAC_USE_DAC3_CH1 == TRUE
-//static const dacparams_t dac3_ch1_params = {
-// .dac = DAC3,
-// .dataoffset = 0U,
-// .regshift = 0U,
-// .regmask = 0xFFFF0000U,
-// .dmastream = STM32_DAC_DAC3_CH1_DMA_STREAM,
-//#if STM32_DMA_SUPPORTS_DMAMUX
-// .peripheral = STM32_DMAMUX1_DAC3_CH1,
-//#endif
-// .dmamode = STM32_DMA_CR_CHSEL(DAC3_CH1_DMA_CHANNEL) |
-// STM32_DMA_CR_PL(STM32_DAC_DAC3_CH1_DMA_PRIORITY) |
-// STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
-// STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
-// STM32_DMA_CR_TCIE,
-// .dmairqprio = STM32_DAC_DAC3_CH1_IRQ_PRIORITY
-//};
-//#endif
-//
-//#if STM32_DAC_USE_DAC3_CH2 == TRUE
-//static const dacparams_t dac3_ch2_params = {
-// .dac = DAC3,
-// .dataoffset = CHANNEL_DATA_OFFSET,
-// .regshift = 16U,
-// .regmask = 0x0000FFFFU,
-// .dmastream = STM32_DAC_DAC3_CH2_DMA_STREAM,
-//#if STM32_DMA_SUPPORTS_DMAMUX
-// .peripheral = STM32_DMAMUX1_DAC3_CH2,
-//#endif
-// .dmamode = STM32_DMA_CR_CHSEL(DAC3_CH2_DMA_CHANNEL) |
-// STM32_DMA_CR_PL(STM32_DAC_DAC3_CH2_DMA_PRIORITY) |
-// STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
-// STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
-// STM32_DMA_CR_TCIE,
-// .dmairqprio = STM32_DAC_DAC3_CH2_IRQ_PRIORITY
-//};
-//#endif
-//
-//#if STM32_DAC_USE_DAC4_CH1 == TRUE
-//static const dacparams_t dac4_ch1_params = {
-// .dac = DAC4,
-// .dataoffset = 0U,
-// .regshift = 0U,
-// .regmask = 0xFFFF0000U,
-// .dmastream = STM32_DAC_DAC4_CH1_DMA_STREAM,
-//#if STM32_DMA_SUPPORTS_DMAMUX
-// .peripheral = STM32_DMAMUX1_DAC4_CH1,
-//#endif
-// .dmamode = STM32_DMA_CR_CHSEL(DAC4_CH1_DMA_CHANNEL) |
-// STM32_DMA_CR_PL(STM32_DAC_DAC4_CH1_DMA_PRIORITY) |
-// STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
-// STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
-// STM32_DMA_CR_TCIE,
-// .dmairqprio = STM32_DAC_DAC4_CH1_IRQ_PRIORITY
-//};
-//#endif
-//
-//#if STM32_DAC_USE_DAC4_CH2 == TRUE
-//static const dacparams_t dac4_ch2_params = {
-// .dac = DAC4,
-// .dataoffset = CHANNEL_DATA_OFFSET,
-// .regshift = 16U,
-// .regmask = 0x0000FFFFU,
-// .dmastream = STM32_DAC_DAC4_CH2_DMA_STREAM,
-//#if STM32_DMA_SUPPORTS_DMAMUX
-// .peripheral = STM32_DMAMUX1_DAC4_CH2,
-//#endif
-// .dmamode = STM32_DMA_CR_CHSEL(DAC4_CH2_DMA_CHANNEL) |
-// STM32_DMA_CR_PL(STM32_DAC_DAC4_CH2_DMA_PRIORITY) |
-// STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
-// STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
-// STM32_DMA_CR_TCIE,
-// .dmairqprio = STM32_DAC_DAC4_CH2_IRQ_PRIORITY
-//};
-//#endif
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Shared end/half-of-tx service routine.
- *
- * @param[in] dacp pointer to the @p DACDriver object
- * @param[in] flags pre-shifted content of the ISR register
- */
-static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
- if ((flags & STM32_BDMA_ISR_TEIF) != 0) {
- /* DMA errors handling.*/
- dac_lld_stop_conversion(dacp);
- _dac_isr_error_code(dacp, DAC_ERR_DMAFAILURE);
- }
- else {
- if ((flags & STM32_BDMA_ISR_HTIF) != 0) {
- /* Half transfer processing.*/
- _dac_isr_half_code(dacp);
- }
- if ((flags & STM32_BDMA_ISR_TCIF) != 0) {
- /* Transfer complete processing.*/
- _dac_isr_full_code(dacp);
- }
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level DAC driver initialization.
- *
- * @notapi
- */
-void dac_lld_init(void) {
-
-#if STM32_DAC_USE_DAC1_CH1
- dacObjectInit(&DACD1);
- DACD1.params = &dac1_ch1_params;
- DACD1.bdma = NULL;
-#endif
-
-//#if STM32_DAC_USE_DAC1_CH2
-// dacObjectInit(&DACD2);
-// DACD2.params = &dac1_ch2_params;
-// DACD2.dma = NULL;
-//#endif
-//
-//#if STM32_DAC_USE_DAC2_CH1
-// dacObjectInit(&DACD3);
-// DACD3.params = &dac2_ch1_params;
-// DACD3.dma = NULL;
-//#endif
-//
-//#if STM32_DAC_USE_DAC2_CH2
-// dacObjectInit(&DACD4);
-// DACD4.params = &dac2_ch2_params;
-// DACD4.dma = NULL;
-//#endif
-//
-//#if STM32_DAC_USE_DAC3_CH1
-// dacObjectInit(&DACD5);
-// DACD5.params = &dac3_ch1_params;
-// DACD5.dma = NULL;
-//#endif
-//
-//#if STM32_DAC_USE_DAC3_CH2
-// dacObjectInit(&DACD6);
-// DACD6.params = &dac3_ch2_params;
-// DACD6.dma = NULL;
-//#endif
-//
-//#if STM32_DAC_USE_DAC4_CH1
-// dacObjectInit(&DACD7);
-// DACD7.params = &dac4_ch1_params;
-// DACD7.dma = NULL;
-//#endif
-//
-//#if STM32_DAC_USE_DAC4_CH2
-// dacObjectInit(&DACD8);
-// DACD8.params = &dac4_ch2_params;
-// DACD8.dma = NULL;
-//#endif
-}
-
-/**
- * @brief Configures and activates the DAC peripheral.
- *
- * @param[in] dacp pointer to the @p DACDriver object
- *
- * @notapi
- */
-void dac_lld_start(DACDriver *dacp) {
-
- /* If the driver is in DAC_STOP state then a full initialization is
- required.*/
- if (dacp->state == DAC_STOP) {
- dacchannel_t channel = 0;
-
- /* Enabling the clock source.*/
-#if STM32_DAC_USE_DAC1_CH1
- if (&DACD1 == dacp) {
- rccEnableDAC1(true);
- }
-#endif
-
-//#if STM32_DAC_USE_DAC1_CH2
-// if (&DACD2 == dacp) {
-// rccEnableDAC1(true);
-// channel = 1;
-// }
-//#endif
-//
-//#if STM32_DAC_USE_DAC2_CH1
-// if (&DACD3 == dacp) {
-// rccEnableDAC2(true);
-// }
-//#endif
-//
-//#if STM32_DAC_USE_DAC2_CH2
-// if (&DACD4 == dacp) {
-// rccEnableDAC2(true);
-// channel = 1;
-// }
-//#endif
-//
-//#if STM32_DAC_USE_DAC3_CH1
-// if (&DACD5 == dacp) {
-// rccEnableDAC3(true);
-// }
-//#endif
-//
-//#if STM32_DAC_USE_DAC3_CH2
-// if (&DACD6 == dacp) {
-// rccEnableDAC3(true);
-// channel = 1;
-// }
-//#endif
-//
-//#if STM32_DAC_USE_DAC4_CH1
-// if (&DACD7 == dacp) {
-// rccEnableDAC4(true);
-// }
-//#endif
-//
-//#if STM32_DAC_USE_DAC4_CH2
-// if (&DACD8 == dacp) {
-// rccEnableDAC4(true);
-// channel = 1;
-// }
-//#endif
-
- /* Enabling DAC in SW triggering mode initially, initializing data to
- zero.*/
-#if STM32_DAC_DUAL_MODE == FALSE
- {
- uint32_t cr;
-
- cr = dacp->params->dac->CR;
- cr &= dacp->params->regmask;
- cr |= (DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift;
- dacp->params->dac->MCR = 2;
- dacp->params->dac->CR = cr;
- dac_lld_put_channel(dacp, channel, dacp->config->init);
- }
-#else
- if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) ||
- (dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) ||
- (dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) {
- dacp->params->dac->CR = DAC_CR_EN2 | (dacp->config->cr << 16) | DAC_CR_EN1 | dacp->config->cr;
- dac_lld_put_channel(dacp, 1U, dacp->config->init);
- }
- else {
- dacp->params->dac->CR = DAC_CR_EN1 | dacp->config->cr;
- }
- dac_lld_put_channel(dacp, channel, dacp->config->init);
-#endif
- }
-}
-
-/**
- * @brief Deactivates the DAC peripheral.
- *
- * @param[in] dacp pointer to the @p DACDriver object
- *
- * @notapi
- */
-void dac_lld_stop(DACDriver *dacp) {
-
- /* If in ready state then disables the DAC clock.*/
- if (dacp->state == DAC_READY) {
-
- /* Disabling DAC.*/
- dacp->params->dac->CR &= dacp->params->regmask;
-
-#if STM32_DAC_USE_DAC1_CH1
- if (&DACD1 == dacp) {
- if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
- rccDisableDAC1();
- }
- }
-#endif
-
-//#if STM32_DAC_USE_DAC1_CH2
-// if (&DACD2 == dacp) {
-// if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
-// rccDisableDAC1();
-// }
-// }
-//#endif
-//
-//#if STM32_DAC_USE_DAC2_CH1
-// if (&DACD3 == dacp) {
-// if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
-// rccDisableDAC2();
-// }
-// }
-//#endif
-//
-//#if STM32_DAC_USE_DAC2_CH2
-// if (&DACD4 == dacp) {
-// if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
-// rccDisableDAC2();
-// }
-// }
-//#endif
-//
-//#if STM32_DAC_USE_DAC3_CH1
-// if (&DACD5 == dacp) {
-// if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
-// rccDisableDAC3();
-// }
-// }
-//#endif
-//
-//#if STM32_DAC_USE_DAC3_CH2
-// if (&DACD6 == dacp) {
-// if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
-// rccDisableDAC3();
-// }
-// }
-//#endif
-//
-//#if STM32_DAC_USE_DAC4_CH1
-// if (&DACD7 == dacp) {
-// if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
-// rccDisableDAC4();
-// }
-// }
-//#endif
-//
-//#if STM32_DAC_USE_DAC4_CH2
-// if (&DACD8 == dacp) {
-// if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
-// rccDisableDAC4();
-// }
-// }
-//#endif
- }
-}
-
-/**
- * @brief Outputs a value directly on a DAC channel.
- *
- * @param[in] dacp pointer to the @p DACDriver object
- * @param[in] channel DAC channel number
- * @param[in] sample value to be output
- *
- * @api
- */
-void dac_lld_put_channel(DACDriver *dacp,
- dacchannel_t channel,
- dacsample_t sample) {
-
- switch (dacp->config->datamode) {
- case DAC_DHRM_12BIT_RIGHT:
-#if STM32_DAC_DUAL_MODE
- case DAC_DHRM_12BIT_RIGHT_DUAL:
-#endif
- if (channel == 0U) {
-#if STM32_DAC_DUAL_MODE
- dacp->params->dac->DHR12R1 = (uint32_t)sample;
-#else
- *(&dacp->params->dac->DHR12R1 + dacp->params->dataoffset) = (uint32_t)sample;
-#endif
- }
-#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2 || \
- STM32_HAS_DAC3_CH2 || STM32_HAS_DAC4_CH2)
- else {
- dacp->params->dac->DHR12R2 = (uint32_t)sample;
- }
-#endif
- break;
- case DAC_DHRM_12BIT_LEFT:
-#if STM32_DAC_DUAL_MODE
- case DAC_DHRM_12BIT_LEFT_DUAL:
-#endif
- if (channel == 0U) {
-#if STM32_DAC_DUAL_MODE
- dacp->params->dac->DHR12L1 = (uint32_t)sample;
-#else
- *(&dacp->params->dac->DHR12L1 + dacp->params->dataoffset) = (uint32_t)sample;
-#endif
- }
-#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2 || \
- STM32_HAS_DAC3_CH2 || STM32_HAS_DAC4_CH2)
- else {
- dacp->params->dac->DHR12L2 = (uint32_t)sample;
- }
-#endif
- break;
- case DAC_DHRM_8BIT_RIGHT:
-#if STM32_DAC_DUAL_MODE
- case DAC_DHRM_8BIT_RIGHT_DUAL:
-#endif
- if (channel == 0U) {
-#if STM32_DAC_DUAL_MODE
- dacp->params->dac->DHR8R1 = (uint32_t)sample;
-#else
- *(&dacp->params->dac->DHR8R1 + dacp->params->dataoffset) = (uint32_t)sample;
-#endif
- }
-#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2 || \
- STM32_HAS_DAC3_CH2 || STM32_HAS_DAC4_CH2)
- else {
- dacp->params->dac->DHR8R2 = (uint32_t)sample;
- }
-#endif
- break;
- default:
- osalDbgAssert(false, "unexpected DAC mode");
- break;
- }
-}
-
-/**
- * @brief Starts a DAC conversion.
- * @details Starts an asynchronous conversion operation.
- * @note In @p DAC_DHRM_8BIT_RIGHT mode the parameters passed to the
- * callback are wrong because two samples are packed in a single
- * dacsample_t element. This will not be corrected, do not rely
- * on those parameters.
- * @note In @p DAC_DHRM_8BIT_RIGHT_DUAL mode two samples are treated
- * as a single 16 bits sample and packed into a single dacsample_t
- * element. The num_channels must be set to one in the group
- * conversion configuration structure.
- *
- * @param[in] dacp pointer to the @p DACDriver object
- *
- * @notapi
- */
-void dac_lld_start_conversion(DACDriver *dacp) {
- uint32_t n, cr, dmamode;
-
- /* Number of DMA operations per buffer.*/
- n = dacp->depth * dacp->grpp->num_channels;
-
- /* Allocating the DMA channel.*/
- dacp->bdma = bdmaStreamAllocI(dacp->params->dmastream,
- dacp->params->dmairqprio,
- (stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
- (void *)dacp);
- osalDbgAssert(dacp->bdma != NULL, "unable to allocate stream");
-#if STM32_DMA_SUPPORTS_DMAMUX
- bdmaSetRequestSource(dacp->bdma, dacp->params->peripheral);
-#endif
-
- /* DMA settings depend on the chosen DAC mode.*/
- switch (dacp->config->datamode) {
- /* Sets the DAC data register */
- case DAC_DHRM_12BIT_RIGHT:
- osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
-
- bdmaStreamSetPeripheral(dacp->bdma, &dacp->params->dac->DHR12R1 +
- dacp->params->dataoffset);
- dmamode = dacp->params->dmamode |
- STM32_BDMA_CR_PSIZE_WORD | STM32_BDMA_CR_MSIZE_HWORD;
- break;
-// case DAC_DHRM_12BIT_LEFT:
-// osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
-//
-// dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12L1 +
-// dacp->params->dataoffset);
-// dmamode = dacp->params->dmamode |
-// STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-// break;
-// case DAC_DHRM_8BIT_RIGHT:
-// osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
-//
-// dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8R1 +
-// dacp->params->dataoffset);
-// dmamode = dacp->params->dmamode |
-// STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
-//
-// /* In this mode the size of the buffer is halved because two samples
-// packed in a single dacsample_t element.*/
-// n = (n + 1) / 2;
-// break;
-//#if STM32_DAC_DUAL_MODE == TRUE
-// case DAC_DHRM_12BIT_RIGHT_DUAL:
-// osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
-//
-// dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12RD);
-// dmamode = dacp->params->dmamode |
-// STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
-// n /= 2;
-// break;
-// case DAC_DHRM_12BIT_LEFT_DUAL:
-// osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
-//
-// dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12LD);
-// dmamode = dacp->params->dmamode |
-// STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
-// n /= 2;
-// break;
-// case DAC_DHRM_8BIT_RIGHT_DUAL:
-// osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
-//
-// dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8RD);
-// dmamode = dacp->params->dmamode |
-// STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
-// n /= 2;
-// break;
-//#endif
- default:
- osalDbgAssert(false, "unexpected DAC mode");
- return;
- }
-
- bdmaStreamSetMemory(dacp->bdma, dacp->samples);
- bdmaStreamSetTransactionSize(dacp->bdma, n);
- bdmaStreamSetMode(dacp->bdma, dmamode |
- STM32_BDMA_CR_TEIE |
- STM32_BDMA_CR_HTIE | STM32_BDMA_CR_TCIE);
- bdmaStreamEnable(dacp->bdma);
-
- /* DAC configuration.*/
- cr = dacp->params->dac->CR;
-
-#if STM32_DAC_DUAL_MODE == FALSE
- cr &= dacp->params->regmask;
- cr |= (DAC_CR_DMAEN1 | (dacp->grpp->trigger << DAC_CR_TSEL1_Pos) | DAC_CR_TEN1 | DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift;
-#else
- cr = DAC_CR_DMAEN1 | (dacp->grpp->trigger << DAC_CR_TSEL1_Pos) | DAC_CR_TEN1 | DAC_CR_EN1 | dacp->config->cr
- | (dacp->grpp->trigger << DAC_CR_TSEL2_Pos) | DAC_CR_TEN2 | DAC_CR_EN2 | (dacp->config->cr << 16);
-#endif
-
- dacp->params->dac->CR = cr;
-}
-
-/**
- * @brief Stops an ongoing conversion.
- * @details This function stops the currently ongoing conversion and returns
- * the driver in the @p DAC_READY state. If there was no conversion
- * being processed then the function does nothing.
- *
- * @param[in] dacp pointer to the @p DACDriver object
- *
- * @iclass
- */
-void dac_lld_stop_conversion(DACDriver *dacp) {
- uint32_t cr;
-
- /* DMA channel disabled and released.*/
- bdmaStreamDisable(dacp->bdma);
- bdmaStreamFreeI(dacp->bdma);
- dacp->bdma = NULL;
-
- cr = dacp->params->dac->CR;
-
-#if STM32_DAC_DUAL_MODE == FALSE
- cr &= dacp->params->regmask;
- cr |= (DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift;
-#else
- if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) ||
- (dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) ||
- (dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) {
- cr = DAC_CR_EN2 | (dacp->config->cr << 16) |
- DAC_CR_EN1 | dacp->config->cr;
- }
- else {
- cr = DAC_CR_EN1 | dacp->config->cr;
- }
-#endif
-
- dacp->params->dac->CR = cr;
-}
-
-#endif /* HAL_USE_DAC */
-
-/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h.bak b/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h.bak deleted file mode 100644 index 1e369ca..0000000 --- a/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h.bak +++ /dev/null @@ -1,662 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file DACv1/hal_dac_lld.h
- * @brief STM32 DAC subsystem low level driver header.
- *
- * @addtogroup DAC
- * @{
- */
-
-#ifndef HAL_DAC_LLD_H
-#define HAL_DAC_LLD_H
-
-#if HAL_USE_DAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name DAC trigger modes
- * @{
- */
-#define DAC_TRG_MASK 7U
-#define DAC_TRG(n) (n)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief Enables the DAC dual mode.
- * @note In dual mode DAC second channels cannot be accessed individually.
- */
-#if !defined(STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
-#define STM32_DAC_DUAL_MODE FALSE
-#endif
-
-/**
- * @brief DAC1 CH1 driver enable switch.
- * @details If set to @p TRUE the support for DAC1 channel 1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(STM32_DAC_USE_DAC1_CH1) || defined(__DOXYGEN__)
-#define STM32_DAC_USE_DAC1_CH1 FALSE
-#endif
-
-/**
- * @brief DAC1 CH2 driver enable switch.
- * @details If set to @p TRUE the support for DAC1 channel 2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(STM32_DAC_USE_DAC1_CH2) || defined(__DOXYGEN__)
-#define STM32_DAC_USE_DAC1_CH2 FALSE
-#endif
-
-/**
- * @brief DAC2 CH1 driver enable switch.
- * @details If set to @p TRUE the support for DAC2 channel 1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(STM32_DAC_USE_DAC2_CH1) || defined(__DOXYGEN__)
-#define STM32_DAC_USE_DAC2_CH1 FALSE
-#endif
-
-/**
- * @brief DAC2 CH2 driver enable switch.
- * @details If set to @p TRUE the support for DAC2 channel 2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(STM32_DAC_USE_DAC2_CH2) || defined(__DOXYGEN__)
-#define STM32_DAC_USE_DAC2_CH2 FALSE
-#endif
-
-/**
- * @brief DAC3 CH1 driver enable switch.
- * @details If set to @p TRUE the support for DAC3 channel 1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(STM32_DAC_USE_DAC3_CH1) || defined(__DOXYGEN__)
-#define STM32_DAC_USE_DAC3_CH1 FALSE
-#endif
-
-/**
- * @brief DAC3 CH2 driver enable switch.
- * @details If set to @p TRUE the support for DAC3 channel 2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(STM32_DAC_USE_DAC3_CH2) || defined(__DOXYGEN__)
-#define STM32_DAC_USE_DAC3_CH2 FALSE
-#endif
-
-/**
- * @brief DAC4 CH1 driver enable switch.
- * @details If set to @p TRUE the support for DAC4 channel 1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(STM32_DAC_USE_DAC4_CH1) || defined(__DOXYGEN__)
-#define STM32_DAC_USE_DAC4_CH1 FALSE
-#endif
-
-/**
- * @brief DAC4 CH2 driver enable switch.
- * @details If set to @p TRUE the support for DAC4 channel 2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(STM32_DAC_USE_DAC4_CH2) || defined(__DOXYGEN__)
-#define STM32_DAC_USE_DAC4_CH2 FALSE
-#endif
-
-/**
- * @brief DAC1 CH1 interrupt priority level setting.
- */
-#if !defined(STM32_DAC_DAC1_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
-#endif
-
-/**
- * @brief DAC1 CH2 interrupt priority level setting.
- */
-#if !defined(STM32_DAC_DAC1_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
-#endif
-
-/**
- * @brief DAC2 CH1 interrupt priority level setting.
- */
-#if !defined(STM32_DAC_DAC2_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC2_CH1_IRQ_PRIORITY 10
-#endif
-
-/**
- * @brief DAC2 CH2 interrupt priority level setting.
- */
-#if !defined(STM32_DAC_DAC2_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC2_CH2_IRQ_PRIORITY 10
-#endif
-
-/**
- * @brief DAC3 CH1 interrupt priority level setting.
- */
-#if !defined(STM32_DAC_DAC3_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC3_CH1_IRQ_PRIORITY 10
-#endif
-
-/**
- * @brief DAC3 CH2 interrupt priority level setting.
- */
-#if !defined(STM32_DAC_DAC3_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC3_CH2_IRQ_PRIORITY 10
-#endif
-
-/**
- * @brief DAC4 CH1 interrupt priority level setting.
- */
-#if !defined(STM32_DAC_DAC4_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC4_CH1_IRQ_PRIORITY 10
-#endif
-
-/**
- * @brief DAC4 CH2 interrupt priority level setting.
- */
-#if !defined(STM32_DAC_DAC4_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC4_CH2_IRQ_PRIORITY 10
-#endif
-
-/**
- * @brief DAC1 CH1 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_DAC_DAC1_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
-#endif
-
-/**
- * @brief DAC1 CH2 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_DAC_DAC1_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
-#endif
-
-/**
- * @brief DAC2 CH1 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_DAC_DAC2_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC2_CH1_DMA_PRIORITY 2
-#endif
-
-/**
- * @brief DAC2 CH2 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_DAC_DAC2_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC2_CH2_DMA_PRIORITY 2
-#endif
-
-/**
- * @brief DAC3 CH1 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_DAC_DAC3_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC3_CH1_DMA_PRIORITY 2
-#endif
-
-/**
- * @brief DAC3 CH2 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_DAC_DAC3_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC3_CH2_DMA_PRIORITY 2
-#endif
-
-/**
- * @brief DAC4 CH1 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_DAC_DAC4_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC4_CH1_DMA_PRIORITY 2
-#endif
-
-/**
- * @brief DAC4 CH2 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_DAC_DAC4_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_DAC_DAC4_CH2_DMA_PRIORITY 2
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/* Handling missing registry keys.*/
-#if !defined(STM32_HAS_DAC1_CH1)
-#define STM32_HAS_DAC1_CH1 FALSE
-#endif
-#if !defined(STM32_HAS_DAC1_CH2)
-#define STM32_HAS_DAC1_CH2 FALSE
-#endif
-#if !defined(STM32_HAS_DAC2_CH1)
-#define STM32_HAS_DAC2_CH1 FALSE
-#endif
-#if !defined(STM32_HAS_DAC2_CH2)
-#define STM32_HAS_DAC2_CH2 FALSE
-#endif
-#if !defined(STM32_HAS_DAC3_CH1)
-#define STM32_HAS_DAC3_CH1 FALSE
-#endif
-#if !defined(STM32_HAS_DAC3_CH2)
-#define STM32_HAS_DAC3_CH2 FALSE
-#endif
-#if !defined(STM32_HAS_DAC4_CH1)
-#define STM32_HAS_DAC4_CH1 FALSE
-#endif
-#if !defined(STM32_HAS_DAC4_CH2)
-#define STM32_HAS_DAC4_CH2 FALSE
-#endif
-
-#if STM32_DAC_USE_DAC1_CH1 && !STM32_HAS_DAC1_CH1
-#error "DAC1 CH1 not present in the selected device"
-#endif
-
-#if STM32_DAC_USE_DAC1_CH2 && !STM32_HAS_DAC1_CH2
-#error "DAC1 CH2 not present in the selected device"
-#endif
-
-#if STM32_DAC_USE_DAC2_CH1 && !STM32_HAS_DAC2_CH1
-#error "DAC2 CH1 not present in the selected device"
-#endif
-
-#if STM32_DAC_USE_DAC2_CH2 && !STM32_HAS_DAC2_CH2
-#error "DAC2 CH2 not present in the selected device"
-#endif
-
-#if STM32_DAC_USE_DAC3_CH1 && !STM32_HAS_DAC3_CH1
-#error "DAC3 CH1 not present in the selected device"
-#endif
-
-#if STM32_DAC_USE_DAC3_CH2 && !STM32_HAS_DAC3_CH2
-#error "DAC3 CH2 not present in the selected device"
-#endif
-
-#if STM32_DAC_USE_DAC4_CH1 && !STM32_HAS_DAC4_CH1
-#error "DAC4 CH1 not present in the selected device"
-#endif
-
-#if STM32_DAC_USE_DAC4_CH2 && !STM32_HAS_DAC4_CH2
-#error "DAC4 CH2 not present in the selected device"
-#endif
-
-#if (STM32_DAC_USE_DAC1_CH2 || STM32_DAC_USE_DAC2_CH2 || \
- STM32_DAC_USE_DAC3_CH2 || STM32_DAC_USE_DAC4_CH2) && STM32_DAC_DUAL_MODE
-#error "DACx CH2 cannot be used independently in dual mode"
-#endif
-
-#if !STM32_DAC_USE_DAC1_CH1 && !STM32_DAC_USE_DAC1_CH2 && \
- !STM32_DAC_USE_DAC2_CH1 && !STM32_DAC_USE_DAC2_CH2 && \
- !STM32_DAC_USE_DAC3_CH1 && !STM32_DAC_USE_DAC3_CH2 && \
- !STM32_DAC_USE_DAC4_CH1 && !STM32_DAC_USE_DAC4_CH2
-#error "DAC driver activated but no DAC peripheral assigned"
-#endif
-
-#if STM32_DAC_USE_DAC1_CH1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC1_CH1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to DAC1 CH1"
-#endif
-
-#if STM32_DAC_USE_DAC1_CH2 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC1_CH2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to DAC1 CH2"
-#endif
-
-#if STM32_DAC_USE_DAC2_CH1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC2_CH1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to DAC2 CH1"
-#endif
-
-#if STM32_DAC_USE_DAC2_CH2 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC2_CH2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to DAC2 CH2"
-#endif
-
-#if STM32_DAC_USE_DAC3_CH1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC3_CH1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to DAC3 CH1"
-#endif
-
-#if STM32_DAC_USE_DAC3_CH2 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC3_CH2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to DAC3 CH2"
-#endif
-
-#if STM32_DAC_USE_DAC4_CH1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC4_CH1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to DAC4 CH1"
-#endif
-
-#if STM32_DAC_USE_DAC4_CH2 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC4_CH2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to DAC4 CH2"
-#endif
-
-/* The following checks are only required when there is a DMA able to
- reassign streams to different channels.*/
-#if STM32_ADVANCED_DMA
-
-/* Check on the presence of the DMA streams settings in mcuconf.h.*/
-#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC_DAC1_CH1_BDMA_STREAM)
-#error "DAC1 CH1 BDMA stream not defined"
-#endif
-
-#if STM32_DAC_USE_DAC1_CH2 && !defined(STM32_DAC_DAC1_CH2_DMA_STREAM)
-#error "DAC1 CH2 DMA stream not defined"
-#endif
-
-#if STM32_DAC_USE_DAC2_CH1 && !defined(STM32_DAC_DAC2_CH1_DMA_STREAM)
-#error "DAC2 CH1 DMA stream not defined"
-#endif
-
-#if STM32_DAC_USE_DAC2_CH2 && !defined(STM32_DAC_DAC2_CH2_DMA_STREAM)
-#error "DAC2 CH2 DMA stream not defined"
-#endif
-
-#if STM32_DAC_USE_DAC3_CH1 && !defined(STM32_DAC_DAC3_CH1_DMA_STREAM)
-#error "DAC3 CH1 DMA stream not defined"
-#endif
-
-#if STM32_DAC_USE_DAC3_CH2 && !defined(STM32_DAC_DAC3_CH2_DMA_STREAM)
-#error "DAC3 CH2 DMA stream not defined"
-#endif
-
-#if STM32_DAC_USE_DAC4_CH1 && !defined(STM32_DAC_DAC4_CH1_DMA_STREAM)
-#error "DAC4 CH1 DMA stream not defined"
-#endif
-
-#if STM32_DAC_USE_DAC4_CH2 && !defined(STM32_DAC_DAC4_CH2_DMA_STREAM)
-#error "DAC4 CH2 DMA stream not defined"
-#endif
-
-#if STM32_DMA_SUPPORTS_DMAMUX
-
-#else /* !STM32_DMA_SUPPORTS_DMAMUX */
-
-/* Check on the validity of the assigned DMA streams.*/
-#if STM32_DAC_USE_DAC1_CH1 && \
- !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC1_CH1_DMA_STREAM, STM32_DAC1_CH1_DMA_MSK)
-#error "invalid DMA stream associated to DAC1 CH1"
-#endif
-
-#if STM32_DAC_USE_DAC1_CH2 && \
- !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC1_CH2_DMA_STREAM, STM32_DAC1_CH2_DMA_MSK)
-#error "invalid DMA stream associated to DAC1 CH2"
-#endif
-
-#if STM32_DAC_USE_DAC2_CH1 && \
- !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC2_CH1_DMA_STREAM, STM32_DAC2_CH1_DMA_MSK)
-#error "invalid DMA stream associated to DAC2 CH1"
-#endif
-
-#if STM32_DAC_USE_DAC2_CH2 && \
- !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC2_CH2_DMA_STREAM, STM32_DAC2_CH2_DMA_MSK)
-#error "invalid DMA stream associated to DAC2 CH2"
-#endif
-
-#if STM32_DAC_USE_DAC3_CH1 && \
- !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC3_CH1_DMA_STREAM, STM32_DAC3_CH1_DMA_MSK)
-#error "invalid DMA stream associated to DAC1 CH1"
-#endif
-
-#if STM32_DAC_USE_DAC3_CH2 && \
- !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC3_CH2_DMA_STREAM, STM32_DAC3_CH2_DMA_MSK)
-#error "invalid DMA stream associated to DAC1 CH2"
-#endif
-
-#if STM32_DAC_USE_DAC4_CH1 && \
- !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC4_CH1_DMA_STREAM, STM32_DAC4_CH1_DMA_MSK)
-#error "invalid DMA stream associated to DAC2 CH1"
-#endif
-
-#if STM32_DAC_USE_DAC4_CH2 && \
- !STM32_DMA_IS_VALID_ID(STM32_DAC_DAC4_CH2_DMA_STREAM, STM32_DAC4_CH2_DMA_MSK)
-#error "invalid DMA stream associated to DAC2 CH2"
-#endif
-
-#endif /* !STM32_DMA_SUPPORTS_DMAMUX */
-
-#endif /* STM32_ADVANCED_DMA */
-
-#if STM32_DAC_USE_DAC1_CH1 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC1_CH1_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to DAC1 CH1"
-#endif
-
-#if STM32_DAC_USE_DAC1_CH2 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC1_CH2_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to DAC1 CH2"
-#endif
-
-#if STM32_DAC_USE_DAC2_CH1 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC2_CH1_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to DAC2 CH1"
-#endif
-
-#if STM32_DAC_USE_DAC2_CH2 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC2_CH2_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to DAC2 CH2"
-#endif
-
-#if STM32_DAC_USE_DAC3_CH1 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC3_CH1_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to DAC3 CH1"
-#endif
-
-#if STM32_DAC_USE_DAC3_CH2 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC3_CH2_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to DAC3 CH2"
-#endif
-
-#if STM32_DAC_USE_DAC4_CH1 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC4_CH1_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to DAC4 CH1"
-#endif
-
-#if STM32_DAC_USE_DAC4_CH2 && \
- !STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC4_CH2_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to DAC4 CH2"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/**
- * @brief Max DAC channels.
- */
-#if STM32_DAC_DUAL_MODE == FALSE
-#define DAC_MAX_CHANNELS 2
-#else
-#define DAC_MAX_CHANNELS 1
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a DAC channel index.
- */
-typedef uint32_t dacchannel_t;
-
-/**
- * @brief Type representing a DAC sample.
- */
-typedef uint16_t dacsample_t;
-
-/**
- * @brief DAC channel parameters type.
- */
-typedef struct {
- /**
- * @brief Pointer to the DAC registers block.
- */
- DAC_TypeDef *dac;
- /**
- * @brief DAC data registers offset.
- */
- uint32_t dataoffset;
- /**
- * @brief DAC CR register bit offset.
- */
- uint32_t regshift;
- /**
- * @brief DAC CR register mask.
- */
- uint32_t regmask;
- /**
- * @brief Associated DMA stream.
- */
- uint32_t dmastream;
- /**
- * @brief Mode bits for the DMA.
- */
- uint32_t dmamode;
- /**
- * @brief DMA channel IRQ priority.
- */
- uint32_t dmairqprio;
-#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__)
- /**
- * @brief DMAMUX peripheral selector.
- */
- uint32_t peripheral;
-#endif
-} dacparams_t;
-
-/**
- * @brief Possible DAC failure causes.
- * @note Error codes are architecture dependent and should not relied
- * upon.
- */
-typedef enum {
- DAC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
- DAC_ERR_UNDERFLOW = 1 /**< DAC overflow condition. */
-} dacerror_t;
-
-/**
- * @brief Samples alignment and size mode.
- */
-typedef enum {
- DAC_DHRM_12BIT_RIGHT = 0,
- DAC_DHRM_12BIT_LEFT = 1,
- DAC_DHRM_8BIT_RIGHT = 2,
-#if STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
- DAC_DHRM_12BIT_RIGHT_DUAL = 3,
- DAC_DHRM_12BIT_LEFT_DUAL = 4,
- DAC_DHRM_8BIT_RIGHT_DUAL = 5
-#endif
-} dacdhrmode_t;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Low level fields of the DAC driver structure.
- */
-#define dac_lld_driver_fields \
- /* DAC channel parameters.*/ \
- const dacparams_t *params; \
- /* Associated DMA.*/ \
- const stm32_bdma_stream_t *bdma
-
-/**
- * @brief Low level fields of the DAC configuration structure.
- */
-#define dac_lld_config_fields \
- /* Initial output on DAC channels.*/ \
- dacsample_t init; \
- /* DAC data holding register mode.*/ \
- dacdhrmode_t datamode; \
- /* DAC control register lower 16 bits.*/ \
- uint32_t cr
-
-/**
- * @brief Low level fields of the DAC group configuration structure.
- */
-#define dac_lld_conversion_group_fields \
- /* DAC initialization data. This field contains the (not shifted) value \
- to be put into the TSEL field of the DAC CR register during \
- initialization. All other fields are handled internally.*/ \
- uint32_t trigger
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if STM32_DAC_USE_DAC1_CH1 && !defined(__DOXYGEN__)
-extern DACDriver DACD1;
-#endif
-
-#if STM32_DAC_USE_DAC1_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
-extern DACDriver DACD2;
-#endif
-
-#if STM32_DAC_USE_DAC2_CH1 && !defined(__DOXYGEN__)
-extern DACDriver DACD3;
-#endif
-
-#if STM32_DAC_USE_DAC2_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
-extern DACDriver DACD4;
-#endif
-
-#if STM32_DAC_USE_DAC3_CH1 && !defined(__DOXYGEN__)
-extern DACDriver DACD5;
-#endif
-
-#if STM32_DAC_USE_DAC3_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
-extern DACDriver DACD6;
-#endif
-
-#if STM32_DAC_USE_DAC4_CH1 && !defined(__DOXYGEN__)
-extern DACDriver DACD7;
-#endif
-
-#if STM32_DAC_USE_DAC4_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
-extern DACDriver DACD8;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void dac_lld_init(void);
- void dac_lld_start(DACDriver *dacp);
- void dac_lld_stop(DACDriver *dacp);
- void dac_lld_put_channel(DACDriver *dacp,
- dacchannel_t channel,
- dacsample_t sample);
- void dac_lld_start_conversion(DACDriver *dacp);
- void dac_lld_stop_conversion(DACDriver *dacp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_DAC */
-
-#endif /* HAL_DAC_LLD_H */
-
-/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h b/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h index 08add51..69a5ab6 100644 --- a/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h @@ -229,15 +229,9 @@ #define STM32_USBCLK STM32_48CLK
#elif defined(STM32H7XX)
/* Defines directly STM32_USBCLK.*/
-#if !defined(STM32H723xx)
#define rccEnableOTG_FS rccEnableUSB2_OTG_HS
#define rccDisableOTG_FS rccDisableUSB2_OTG_HS
#define rccResetOTG_FS rccResetUSB2_OTG_HS
-#else
-#define rccEnableOTG_FS rccEnableUSB1_OTG_HS
-#define rccDisableOTG_FS rccDisableUSB1_OTG_HS
-#define rccResetOTG_FS rccResetUSB1_OTG_HS
-#endif
#define rccEnableOTG_HS rccEnableUSB1_OTG_HS
#define rccDisableOTG_HS rccDisableUSB1_OTG_HS
#define rccResetOTG_HS rccResetUSB1_OTG_HS
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/hal_lld.c b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/hal_lld.c new file mode 100644 index 0000000..ab01d60 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/hal_lld.c @@ -0,0 +1,263 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32G4xx/hal_lld.c
+ * @brief STM32G4xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief CMSIS system core clock variable.
+ * @note It is declared in system_stm32g4xx.h.
+ */
+uint32_t SystemCoreClock = STM32_HCLK;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the backup domain.
+ * @note WARNING! Changing RTC clock source impossible without resetting
+ * of the whole BKP domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+ /* Reset BKP domain if different clock source selected.*/
+ if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
+ /* Backup domain reset.*/
+ RCC->BDCR = RCC_BDCR_BDRST;
+ RCC->BDCR = 0;
+ }
+
+#if STM32_LSE_ENABLED
+ /* LSE activation.*/
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Wait until LSE is stable. */
+#endif
+
+#if HAL_USE_RTC
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
+ /* Selects clock source.*/
+ RCC->BDCR |= STM32_RTCSEL;
+
+ /* RTC clock enabled.*/
+ RCC->BDCR |= RCC_BDCR_RTCEN;
+ }
+#endif /* HAL_USE_RTC */
+
+ /* Low speed output mode.*/
+ RCC->BDCR |= STM32_LSCOSEL;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+ /* Initializes the backup domain.*/
+ hal_lld_backup_domain_init();
+
+ /* DMA subsystems initialization.*/
+#if defined(STM32_DMA_REQUIRED)
+ dmaInit();
+#endif
+
+ /* IRQ subsystem initialization.*/
+ irqInit();
+
+ /* Programmable voltage detector settings.*/
+ PWR->CR2 = STM32_PWR_CR2;
+}
+
+/**
+ * @brief STM32L4xx clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+
+ /* Reset of all peripherals.
+ Note, GPIOs are not reset because initialized before this point in
+ board files.*/
+ rccResetAHB1(~0);
+ rccResetAHB2(~STM32_GPIO_EN_MASK);
+ rccResetAHB3(~0);
+ rccResetAPB1R1(~0);
+ rccResetAPB1R2(~0);
+ rccResetAPB2(~0);
+
+ /* PWR clock enable.*/
+#if defined(HAL_USE_RTC) && defined(RCC_APBENR1_RTCAPBEN)
+ rccEnableAPB1R1(RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN, false)
+#else
+ rccEnableAPB1R1(RCC_APB1ENR1_PWREN, false)
+#endif
+
+ /* Core voltage setup.*/
+ PWR->CR1 = STM32_VOS;
+ while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
+ ; /* stable. */
+
+ /* Additional PWR configurations.*/
+ PWR->CR2 = STM32_PWR_CR2;
+ PWR->CR3 = STM32_PWR_CR3;
+ PWR->CR4 = STM32_PWR_CR4;
+ PWR->CR5 = STM32_CR5BITS;
+
+#if STM32_HSI16_ENABLED
+ /* HSI activation.*/
+ RCC->CR |= RCC_CR_HSION;
+ while ((RCC->CR & RCC_CR_HSIRDY) == 0)
+ ; /* Wait until HSI16 is stable. */
+#endif
+
+#if STM32_HSI48_ENABLED
+ /* HSI activation.*/
+ RCC->CRRCR |= RCC_CRRCR_HSI48ON;
+ while ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == 0)
+ ; /* Wait until HSI48 is stable. */
+#endif
+
+#if STM32_HSE_ENABLED
+#if defined(STM32_HSE_BYPASS)
+ /* HSE Bypass.*/
+ RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#endif
+ /* HSE activation.*/
+ RCC->CR |= RCC_CR_HSEON;
+ while ((RCC->CR & RCC_CR_HSERDY) == 0)
+ ; /* Wait until HSE is stable. */
+#endif
+
+#if STM32_LSI_ENABLED
+ /* LSI activation.*/
+ RCC->CSR |= RCC_CSR_LSION;
+ while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+ ; /* Wait until LSI is stable. */
+#endif
+
+ /* Backup domain access enabled and left open.*/
+ PWR->CR1 |= PWR_CR1_DBP;
+
+#if STM32_LSE_ENABLED
+ /* LSE activation.*/
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Wait until LSE is stable. */
+#endif
+
+#if STM32_ACTIVATE_PLL
+ /* PLLM and PLLSRC are common to all PLLs.*/
+ RCC->PLLCFGR = STM32_PLLPDIV |
+ STM32_PLLR | STM32_PLLREN |
+ STM32_PLLQ | STM32_PLLQEN |
+ STM32_PLLP | STM32_PLLPEN |
+ STM32_PLLN | STM32_PLLM |
+ STM32_PLLSRC;
+#endif
+
+#if STM32_ACTIVATE_PLL
+ /* PLL activation.*/
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Waiting for PLL lock.*/
+ while ((RCC->CR & RCC_CR_PLLRDY) == 0)
+ ;
+#endif
+
+ /* Other clock-related settings (dividers, MCO etc).*/
+ RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_PPRE2 | STM32_PPRE1 |
+ STM32_HPRE;
+
+ /* CCIPR registers initialization, note.*/
+ RCC->CCIPR = STM32_ADC345SEL | STM32_ADC12SEL | STM32_CLK48SEL |
+ STM32_FDCANSEL | STM32_I2S23SEL | STM32_SAI1SEL |
+ STM32_LPTIM1SEL | STM32_I2C3SEL | STM32_I2C2SEL |
+ STM32_I2C1SEL | STM32_LPUART1SEL | STM32_UART5SEL |
+ STM32_UART4SEL | STM32_USART3SEL | STM32_USART2SEL |
+ STM32_USART1SEL;
+ RCC->CCIPR2 = STM32_QSPISEL | STM32_I2C4SEL;
+
+ /* Set flash WS's for SYSCLK source */
+ FLASH->ACR = FLASH_ACR_DBG_SWEN | FLASH_ACR_DCEN | FLASH_ACR_ICEN |
+ FLASH_ACR_PRFTEN | STM32_FLASHBITS;
+ while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
+ (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
+ }
+
+ /* Switching to the configured SYSCLK source if it is different from HSI16.*/
+#if STM32_SW != STM32_SW_HSI16
+ RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
+ /* Wait until SYSCLK is stable.*/
+ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+ ;
+#endif
+
+#endif /* STM32_NO_INIT */
+
+ /* SYSCFG clock enabled here because it is a multi-functional unit shared
+ among multiple drivers.*/
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
+}
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/hal_lld.h b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/hal_lld.h new file mode 100644 index 0000000..45bf317 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/hal_lld.h @@ -0,0 +1,1858 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32G4xx/hal_lld.h
+ * @brief STM32G4xx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - STM32_LSECLK.
+ * - STM32_LSEDRV.
+ * - STM32_LSE_BYPASS (optionally).
+ * - STM32_HSECLK.
+ * - STM32_HSE_BYPASS (optionally).
+ * .
+ * One of the following macros must also be defined:
+ * - STM32G431xx, STM32G441xx, STM32G471xx.
+ * - STM32G473xx, STM32G483xx.
+ * - STM32G474xx, STM32G484xx.
+ * - STM32GBK1CB.
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#if defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \
+ defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32G4 Access Line"
+
+#elif defined(STM32G473xx)
+#define PLATFORM_NAME "STM32G4 Performance Line"
+
+#elif defined(STM32G483xx)
+#define PLATFORM_NAME "STM32G4 Performance Line with Crypto"
+
+#elif defined(STM32G474xx)
+#define PLATFORM_NAME "STM32G4 Hi-resolution Line"
+
+#elif defined(STM32G484xx)
+#define PLATFORM_NAME "STM32G4 Hi-resolution Line with Crypto"
+
+#elif defined(STM32GBK1CB)
+#define PLATFORM_NAME "STM32G4 Mystery Line"
+
+#else
+#error "STM32G4 device not specified"
+#endif
+
+/**
+ * @brief Sub-family identifier.
+ */
+#if !defined(STM32G4XX) || defined(__DOXYGEN__)
+#define STM32G4XX
+#endif
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define STM32_HSI16CLK 16000000U /**< 16MHz internal clock. */
+#define STM32_HSI48CLK 48000000U /**< 48MHz internal clock. */
+#define STM32_LSICLK 32000U /**< Low speed internal clock. */
+/** @} */
+
+/**
+ * @name VOS field definitions
+ * @{
+ */
+#define STM32_VOS_MASK (3U << 9U) /**< Core voltage mask. */
+#define STM32_VOS_RANGE1 (1U << 9U) /**< Core voltage 1.2 Volts. */
+#define STM32_VOS_RANGE2 (2U << 9U) /**< Core voltage 1.0 Volts. */
+/** @} */
+
+/**
+ * @name RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_MASK (3U << 0U) /**< SW field mask. */
+#define STM32_SW_HSI16 (1U << 0U) /**< SYSCLK source is HSI16. */
+#define STM32_SW_HSE (2U << 0U) /**< SYSCLK source is HSE. */
+#define STM32_SW_PLLRCLK (3U << 0U) /**< SYSCLK source is PLL. */
+
+#define STM32_HPRE_MASK (15U << 4U) /**< HPRE field mask. */
+#define STM32_HPRE_FIELD(n) ((n) << 4U) /**< HPRE field value. */
+#define STM32_HPRE_DIV1 STM32_HPRE_FIELD(0U)
+#define STM32_HPRE_DIV2 STM32_HPRE_FIELD(8U)
+#define STM32_HPRE_DIV4 STM32_HPRE_FIELD(9U)
+#define STM32_HPRE_DIV8 STM32_HPRE_FIELD(10U)
+#define STM32_HPRE_DIV16 STM32_HPRE_FIELD(11U)
+#define STM32_HPRE_DIV64 STM32_HPRE_FIELD(12U)
+#define STM32_HPRE_DIV128 STM32_HPRE_FIELD(13U)
+#define STM32_HPRE_DIV256 STM32_HPRE_FIELD(14U)
+#define STM32_HPRE_DIV512 STM32_HPRE_FIELD(15U)
+
+#define STM32_PPRE1_MASK (7U << 8U) /**< PPRE1 field mask. */
+#define STM32_PPRE1_FIELD(n) ((n) << 8U) /**< PPRE1 field value. */
+#define STM32_PPRE1_DIV1 STM32_PPRE1_FIELD(0U)
+#define STM32_PPRE1_DIV2 STM32_PPRE1_FIELD(4U)
+#define STM32_PPRE1_DIV4 STM32_PPRE1_FIELD(5U)
+#define STM32_PPRE1_DIV8 STM32_PPRE1_FIELD(6U)
+#define STM32_PPRE1_DIV16 STM32_PPRE1_FIELD(7U)
+
+#define STM32_PPRE2_MASK (7U << 11U) /**< PPRE2 field mask. */
+#define STM32_PPRE2_FIELD(n) ((n) << 11U) /**< PPRE2 field value. */
+#define STM32_PPRE2_DIV1 STM32_PPRE2_FIELD(0U)
+#define STM32_PPRE2_DIV2 STM32_PPRE2_FIELD(4U)
+#define STM32_PPRE2_DIV4 STM32_PPRE2_FIELD(5U)
+#define STM32_PPRE2_DIV8 STM32_PPRE2_FIELD(6U)
+#define STM32_PPRE2_DIV16 STM32_PPRE2_FIELD(7U)
+
+#define STM32_MCOSEL_MASK (15U << 24U)/**< MCOSEL field mask. */
+#define STM32_MCOSEL_NOCLOCK (0U << 24U) /**< No clock on MCO pin. */
+#define STM32_MCOSEL_SYSCLK (1U << 24U) /**< SYSCLK on MCO pin. */
+#define STM32_MCOSEL_HSI16 (3U << 24U) /**< HSI16 clock on MCO pin. */
+#define STM32_MCOSEL_HSE (4U << 24U) /**< HSE clock on MCO pin. */
+#define STM32_MCOSEL_PLLRCLK (5U << 24U) /**< PLLR clock on MCO pin. */
+#define STM32_MCOSEL_LSI (6U << 24U) /**< LSI clock on MCO pin. */
+#define STM32_MCOSEL_LSE (7U << 24U) /**< LSE clock on MCO pin. */
+#define STM32_MCOSEL_HSI48 (8U << 24U) /**< HSI48 clock on MCO pin. */
+
+#define STM32_MCOPRE_MASK (7U << 28U) /**< MCOPRE field mask. */
+#define STM32_MCOPRE_FIELD(n) ((n) << 28U)/**< MCOPRE field value */
+#define STM32_MCOPRE_DIV1 STM32_MCOPRE_FIELD(0U)
+#define STM32_MCOPRE_DIV2 STM32_MCOPRE_FIELD(1U)
+#define STM32_MCOPRE_DIV4 STM32_MCOPRE_FIELD(2U)
+#define STM32_MCOPRE_DIV8 STM32_MCOPRE_FIELD(3U)
+#define STM32_MCOPRE_DIV16 STM32_MCOPRE_FIELD(4U)
+/** @} */
+
+/**
+ * @name RCC_PLLCFGR register bits definitions
+ * @{
+ */
+#define STM32_PLLSRC_MASK (3 << 0) /**< PLL clock source mask. */
+#define STM32_PLLSRC_NOCLOCK (0 << 0) /**< PLL clock source disabled. */
+#define STM32_PLLSRC_HSI16 (2 << 0) /**< PLL clock source is HSI16. */
+#define STM32_PLLSRC_HSE (3 << 0) /**< PLL clock source is HSE. */
+/** @} */
+
+/**
+ * @name RCC_CCIPR register bits definitions
+ * @{
+ */
+#define STM32_USART1SEL_MASK (3U << 0U) /**< USART1SEL mask. */
+#define STM32_USART1SEL_PCLK2 (0U << 0U) /**< USART1 source is PCLK2. */
+#define STM32_USART1SEL_SYSCLK (1U << 0U) /**< USART1 source is SYSCLK. */
+#define STM32_USART1SEL_HSI16 (2U << 0U) /**< USART1 source is HSI16. */
+#define STM32_USART1SEL_LSE (3U << 0U) /**< USART1 source is LSE. */
+
+#define STM32_USART2SEL_MASK (3U << 2U) /**< USART2 mask. */
+#define STM32_USART2SEL_PCLK1 (0U << 2U) /**< USART2 source is PCLK1. */
+#define STM32_USART2SEL_SYSCLK (1U << 2U) /**< USART2 source is SYSCLK. */
+#define STM32_USART2SEL_HSI16 (2U << 2U) /**< USART2 source is HSI16. */
+#define STM32_USART2SEL_LSE (3U << 2U) /**< USART2 source is LSE. */
+
+#define STM32_USART3SEL_MASK (3U << 4U) /**< USART3 mask. */
+#define STM32_USART3SEL_PCLK1 (0U << 4U) /**< USART3 source is PCLK1. */
+#define STM32_USART3SEL_SYSCLK (1U << 4U) /**< USART3 source is SYSCLK. */
+#define STM32_USART3SEL_HSI16 (2U << 4U) /**< USART3 source is HSI16. */
+#define STM32_USART3SEL_LSE (3U << 4U) /**< USART3 source is LSE. */
+
+#define STM32_UART4SEL_MASK (3U << 6U) /**< UART4 mask. */
+#define STM32_UART4SEL_PCLK1 (0U << 6U) /**< UART4 source is PCLK1. */
+#define STM32_UART4SEL_SYSCLK (1U << 6U) /**< UART4 source is SYSCLK. */
+#define STM32_UART4SEL_HSI16 (2U << 6U) /**< UART4 source is HSI16. */
+#define STM32_UART4SEL_LSE (3U << 6U) /**< UART4 source is LSE. */
+
+#define STM32_UART5SEL_MASK (3U << 8U) /**< UART5 mask. */
+#define STM32_UART5SEL_PCLK1 (0U << 8U) /**< UART5 source is PCLK1. */
+#define STM32_UART5SEL_SYSCLK (1U << 8U) /**< UART5 source is SYSCLK. */
+#define STM32_UART5SEL_HSI16 (2U << 8U) /**< UART5 source is HSI16. */
+#define STM32_UART5SEL_LSE (3U << 8U) /**< UART5 source is LSE. */
+
+#define STM32_LPUART1SEL_MASK (3U << 10U) /**< LPUART1 mask. */
+#define STM32_LPUART1SEL_PCLK1 (0U << 10U) /**< LPUART1 source is PCLK1. */
+#define STM32_LPUART1SEL_SYSCLK (1U << 10U) /**< LPUART1 source is SYSCLK. */
+#define STM32_LPUART1SEL_HSI16 (2U << 10U) /**< LPUART1 source is HSI16. */
+#define STM32_LPUART1SEL_LSE (3U << 10U) /**< LPUART1 source is LSE. */
+
+#define STM32_I2C1SEL_MASK (3U << 12U) /**< I2C1SEL mask. */
+#define STM32_I2C1SEL_PCLK1 (0U << 12U) /**< I2C1 source is PCLK1. */
+#define STM32_I2C1SEL_SYSCLK (1U << 12U) /**< I2C1 source is SYSCLK. */
+#define STM32_I2C1SEL_HSI16 (2U << 12U) /**< I2C1 source is HSI16. */
+
+#define STM32_I2C2SEL_MASK (3U << 14U) /**< I2C2SEL mask. */
+#define STM32_I2C2SEL_PCLK1 (0U << 14U) /**< I2C2 source is PCLK1. */
+#define STM32_I2C2SEL_SYSCLK (1U << 14U) /**< I2C2 source is SYSCLK. */
+#define STM32_I2C2SEL_HSI16 (2U << 14U) /**< I2C2 source is HSI16. */
+
+#define STM32_I2C3SEL_MASK (3U << 16U) /**< I2C3SEL mask. */
+#define STM32_I2C3SEL_PCLK1 (0U << 16U) /**< I2C3 source is PCLK1. */
+#define STM32_I2C3SEL_SYSCLK (1U << 16U) /**< I2C3 source is SYSCLK. */
+#define STM32_I2C3SEL_HSI16 (2U << 16U) /**< I2C3 source is HSI16. */
+
+#define STM32_LPTIM1SEL_MASK (3U << 18U) /**< LPTIM1SEL mask. */
+#define STM32_LPTIM1SEL_PCLK1 (0U << 18U) /**< LPTIM1 source is PCLK1. */
+#define STM32_LPTIM1SEL_LSI (1U << 18U) /**< LPTIM1 source is LSI. */
+#define STM32_LPTIM1SEL_HSI16 (2U << 18U) /**< LPTIM1 source is HSI16. */
+#define STM32_LPTIM1SEL_LSE (3U << 18U) /**< LPTIM1 source is LSE. */
+
+#define STM32_SAI1SEL_MASK (3U << 20U) /**< SAI1SEL mask. */
+#define STM32_SAI1SEL_SYSCLK (0U << 20U) /**< SAI1 source is SYSCLK. */
+#define STM32_SAI1SEL_PLLQCLK (1U << 20U) /**< SAI1 source is PLLQCLK. */
+#define STM32_SAI1SEL_CKIN (2U << 20U) /**< SAI1 source is CKIN. */
+#define STM32_SAI1SEL_HSI16 (3U << 20U) /**< SAI1 source is HSI16. */
+
+#define STM32_I2S23SEL_MASK (3U << 22U) /**< I2S23SEL mask. */
+#define STM32_I2S23SEL_SYSCLK (0U << 22U) /**< I2S23 source is SYSCLK. */
+#define STM32_I2S23SEL_PLLQCLK (1U << 22U) /**< I2S23 source is PLLQCLK. */
+#define STM32_I2S23SEL_CKIN (2U << 22U) /**< I2S23 source is CKIN. */
+#define STM32_I2S23SEL_HSI16 (3U << 22U) /**< I2S23 source is HSI16. */
+
+#define STM32_FDCANSEL_MASK (3U << 24U) /**< FDCANSEL mask. */
+#define STM32_FDCANSEL_HSE (0U << 24U) /**< FDCAN source is HSE. */
+#define STM32_FDCANSEL_PLLQCLK (1U << 24U) /**< FDCAN source is PLLQCLK. */
+#define STM32_FDCANSEL_PCLK1 (2U << 24U) /**< FDCAN source is PCLK1. */
+
+#define STM32_CLK48SEL_MASK (3U << 26U) /**< CLK48SEL mask. */
+#define STM32_CLK48SEL_HSI48 (0U << 26U) /**< CLK48 source is HSI48. */
+#define STM32_CLK48SEL_PLLQCLK (2U << 26U) /**< CLK48 source is PLLQCLK. */
+
+#define STM32_ADC12SEL_MASK (3U << 28U) /**< ADC12SEL mask. */
+#define STM32_ADC12SEL_NOCLK (0U << 28U) /**< ADC12 source is none. */
+#define STM32_ADC12SEL_PLLPCLK (1U << 28U) /**< ADC12 source is PLLPCLK. */
+#define STM32_ADC12SEL_SYSCLK (2U << 28U) /**< ADC12 source is SYSCLK. */
+
+#define STM32_ADC345SEL_MASK (3U << 30U) /**< ADC345SEL mask. */
+#define STM32_ADC345SEL_NOCLK (0U << 30U) /**< ADC345 source is none. */
+#define STM32_ADC345SEL_PLLPCLK (1U << 30U) /**< ADC345 source is PLLPCLK. */
+#define STM32_ADC345SEL_SYSCLK (2U << 30U) /**< ADC345 source is SYSCLK. */
+/** @} */
+
+/**
+ * @name RCC_CCIPR2 register bits definitions
+ * @{
+ */
+#define STM32_I2C4SEL_MASK (3U << 0U) /**< I2C4SEL mask. */
+#define STM32_I2C4SEL_PCLK1 (0U << 0U) /**< I2C4 source is PCLK1. */
+#define STM32_I2C4SEL_SYSCLK (1U << 0U) /**< I2C4 source is SYSCLK. */
+#define STM32_I2C4SEL_HSI16 (2U << 0U) /**< I2C4 source is HSI16. */
+
+#define STM32_QSPISEL_MASK (3U << 20U) /**< QSPISEL mask. */
+#define STM32_QSPISEL_SYSCLK (0U << 20U) /**< QSPI source is SYSCLK. */
+#define STM32_QSPISEL_HSI16 (1U << 20U) /**< QSPI source is HSI16. */
+#define STM32_QSPISEL_PLLQCLK (2U << 20U) /**< QSPI source is PLLQCLK. */
+/** @} */
+
+/**
+ * @name RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK (3U << 8U) /**< RTC source mask. */
+#define STM32_RTCSEL_NOCLOCK (0U << 8U) /**< No RTC source. */
+#define STM32_RTCSEL_LSE (1U << 8U) /**< RTC source is LSE. */
+#define STM32_RTCSEL_LSI (2U << 8U) /**< RTC source is LSI. */
+#define STM32_RTCSEL_HSEDIV (3U << 8U) /**< RTC source is HSE divided. */
+
+#define STM32_LSCOSEL_MASK (3U << 24U) /**< LSCO pin clock source. */
+#define STM32_LSCOSEL_NOCLOCK (0U << 24U) /**< No clock on LSCO pin. */
+#define STM32_LSCOSEL_LSI (1U << 24U) /**< LSI on LSCO pin. */
+#define STM32_LSCOSEL_LSE (3U << 24U) /**< LSE on LSCO pin. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Core voltage selection.
+ * @note This setting affects all the performance and clock related
+ * settings, the maximum performance is only obtainable selecting
+ * the maximum voltage.
+ */
+#if !defined(STM32_VOS) || defined(__DOXYGEN__)
+#define STM32_VOS STM32_VOS_RANGE1
+#endif
+
+/**
+ * @brief PWR CR2 register initialization value.
+ */
+#if !defined(STM32_PWR_CR2) || defined(__DOXYGEN__)
+#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
+#endif
+
+/**
+ * @brief PWR CR3 register initialization value.
+ */
+#if !defined(STM32_PWR_CR3) || defined(__DOXYGEN__)
+#define STM32_PWR_CR3 (PWR_CR3_EIWF)
+#endif
+
+/**
+ * @brief PWR CR4 register initialization value.
+ */
+#if !defined(STM32_PWR_CR4) || defined(__DOXYGEN__)
+#define STM32_PWR_CR4 (0U)
+#endif
+
+/**
+ * @brief Enables or disables the HSI16 clock source.
+ */
+#if !defined(STM32_HSI16_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI16_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the HSI48 clock source.
+ */
+#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI48_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief Main clock source selection.
+ * @note If the selected clock source is not the PLL then the PLL is not
+ * initialized and started.
+ * @note The default value is calculated for a 170MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW STM32_SW_PLLRCLK
+#endif
+
+/**
+ * @brief Clock source for the PLL.
+ * @note This setting has only effect if the PLL is selected as the
+ * system clock source.
+ * @note The default value is calculated for a 170MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC STM32_PLLSRC_HSI16
+#endif
+
+/**
+ * @brief PLLM divider value.
+ * @note The allowed values are 1..16.
+ * @note The default value is calculated for a 170MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLM_VALUE 4
+#endif
+
+/**
+ * @brief PLLN multiplier value.
+ * @note The allowed values are 8..127.
+ * @note The default value is calculated for a 170MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLN_VALUE 84
+#endif
+
+/**
+ * @brief PLLPDIV divider value or zero if disabled.
+ * @note The allowed values are 0, 2..31.
+ */
+#if !defined(STM32_PLLPDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLPDIV_VALUE 0
+#endif
+
+/**
+ * @brief PLLP divider value.
+ * @note The allowed values are 7, 17.
+ */
+#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLP_VALUE 7
+#endif
+
+/**
+ * @brief PLLQ divider value.
+ * @note The allowed values are 2, 4, 6, 8.
+ */
+#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLQ_VALUE 8
+#endif
+
+/**
+ * @brief PLLR divider value.
+ * @note The allowed values are 2, 4, 6, 8.
+ * @note The default value is calculated for a 170MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLR_VALUE 2
+#endif
+
+/**
+ * @brief AHB prescaler value.
+ * @note The default value is calculated for a 170MHz system clock from
+ * the internal 16MHz HSI clock.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1 STM32_PPRE1_DIV2
+#endif
+
+/**
+ * @brief APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2 STM32_PPRE2_DIV1
+#endif
+
+/**
+ * @brief MCO clock source.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief MCO divider setting.
+ */
+#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#endif
+
+/**
+ * @brief LSCO clock source.
+ */
+#if !defined(STM32_LSCOSEL) || defined(__DOXYGEN__)
+#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief USART1 clock source.
+ */
+#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__)
+#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
+#endif
+
+/**
+ * @brief USART2 clock source.
+ */
+#if !defined(STM32_USART2SEL) || defined(__DOXYGEN__)
+#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
+#endif
+
+/**
+ * @brief USART3 clock source.
+ */
+#if !defined(STM32_USART3SEL) || defined(__DOXYGEN__)
+#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
+#endif
+
+/**
+ * @brief UART4 clock source.
+ */
+#if !defined(STM32_UART4SEL) || defined(__DOXYGEN__)
+#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
+#endif
+
+/**
+ * @brief UART5 clock source.
+ */
+#if !defined(STM32_UART5SEL) || defined(__DOXYGEN__)
+#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
+#endif
+
+/**
+ * @brief LPUART1 clock source.
+ */
+#if !defined(STM32_LPUART1SEL) || defined(__DOXYGEN__)
+#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
+#endif
+
+/**
+ * @brief I2C1 clock source.
+ */
+#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__)
+#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
+#endif
+
+/**
+ * @brief I2C2 clock source.
+ */
+#if !defined(STM32_I2C2SEL) || defined(__DOXYGEN__)
+#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
+#endif
+
+/**
+ * @brief I2C3 clock source.
+ */
+#if !defined(STM32_I2C3SEL) || defined(__DOXYGEN__)
+#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
+#endif
+
+/**
+ * @brief I2C4 clock source.
+ */
+#if !defined(STM32_I2C4SEL) || defined(__DOXYGEN__)
+#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
+#endif
+
+/**
+ * @brief LPTIM1 clock source.
+ */
+#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__)
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
+#endif
+
+/**
+ * @brief SAI1 clock source.
+ */
+#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
+#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
+#endif
+
+/**
+ * @brief I2S23 clock source.
+ */
+#if !defined(STM32_I2S23SEL) || defined(__DOXYGEN__)
+#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
+#endif
+
+/**
+ * @brief FDCAN clock source.
+ */
+#if !defined(STM32_FDCANSEL) || defined(__DOXYGEN__)
+#define STM32_FDCANSEL STM32_FDCANSEL_HSE
+#endif
+
+/**
+ * @brief CLK48 clock source.
+ */
+#if !defined(STM32_CLK48SEL) || defined(__DOXYGEN__)
+#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
+#endif
+
+/**
+ * @brief ADC12 clock source.
+ */
+#if !defined(STM32_ADC12SEL) || defined(__DOXYGEN__)
+#define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK
+#endif
+
+/**
+ * @brief ADC34 clock source.
+ */
+#if !defined(STM32_ADC345SEL) || defined(__DOXYGEN__)
+#define STM32_ADC345SEL STM32_ADC345SEL_PLLPCLK
+#endif
+
+/**
+ * @brief QSPI clock source.
+ */
+#if !defined(STM32_QSPISEL) || defined(__DOXYGEN__)
+#define STM32_QSPISEL STM32_QSPISEL_SYSCLK
+#endif
+
+/**
+ * @brief RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32G4xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32G4xx_MCUCONF not defined"
+#endif
+
+#if defined(STM32G431xx) && !defined(STM32G431_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32G431_MCUCONF not defined"
+
+#elif defined(STM32G441xx) && !defined(STM32G441_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32G441_MCUCONF not defined"
+
+#elif defined(STM32G471xx) && !defined(STM32G471_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32G471_MCUCONF not defined"
+
+#elif defined(STM32G473xx) && !defined(STM32G473_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32G473_MCUCONF not defined"
+
+#elif defined(STM32G483xx) && !defined(STM32G473_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32G483_MCUCONF not defined"
+
+#elif defined(STM32G474xx) && !defined(STM32G474_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32G474_MCUCONF not defined"
+
+#elif defined(STM32G484xx) && !defined(STM32G484_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32G484_MCUCONF not defined"
+
+#elif defined(STM32GBK1CB) && !defined(STM32GBK1CB_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32GBK1CB_MCUCONF not defined"
+
+#endif
+
+/*
+ * Board files sanity checks.
+ */
+#if !defined(STM32_LSECLK)
+#error "STM32_LSECLK not defined in board.h"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined in board.h"
+#endif
+
+#if !defined(STM32_HSECLK)
+#error "STM32_HSECLK not defined in board.h"
+#endif
+
+/* Voltage related limits.*/
+#if (STM32_VOS == STM32_VOS_RANGE1) || defined(__DOXYGEN__)
+/**
+ * @name System Limits
+ * @{
+ */
+/**
+ * @brief Maximum SYSCLK clock frequency.
+ */
+#define STM32_SYSCLK_MAX 170000000
+
+/**
+ * @brief Maximum SYSCLK clock frequency without voltage boost.
+ */
+#define STM32_SYSCLK_MAX_NOBOOST 150000000
+
+/**
+ * @brief Maximum HSE clock frequency at current voltage setting.
+ */
+#define STM32_HSECLK_MAX 48000000
+
+/**
+ * @brief Maximum HSE clock frequency using an external source.
+ */
+#define STM32_HSECLK_BYP_MAX 48000000
+
+/**
+ * @brief Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN 8000000
+
+/**
+ * @brief Minimum HSE clock frequency using an external source.
+ */
+#define STM32_HSECLK_BYP_MIN 8000000
+
+/**
+ * @brief Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX 32768
+
+/**
+ * @brief Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_BYP_MAX 1000000
+
+/**
+ * @brief Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN 32768
+
+/**
+ * @brief Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_BYP_MIN 32768
+
+/**
+ * @brief Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX 16000000
+
+/**
+ * @brief Minimum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN 2660000
+
+/**
+ * @brief Maximum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MAX 344000000
+
+/**
+ * @brief Minimum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MIN 96000000
+
+/**
+ * @brief Maximum PLL-P output clock frequency.
+ */
+#define STM32_PLLP_MAX 170000000
+
+/**
+ * @brief Minimum PLL-P output clock frequency.
+ */
+#define STM32_PLLP_MIN 2064500
+
+/**
+ * @brief Maximum PLL-Q output clock frequency.
+ */
+#define STM32_PLLQ_MAX 170000000
+
+/**
+ * @brief Minimum PLL-Q output clock frequency.
+ */
+#define STM32_PLLQ_MIN 8000000
+
+/**
+ * @brief Maximum PLL-R output clock frequency.
+ */
+#define STM32_PLLR_MAX 170000000
+
+/**
+ * @brief Minimum PLL-R output clock frequency.
+ */
+#define STM32_PLLR_MIN 8000000
+
+/**
+ * @brief Maximum APB clock frequency.
+ */
+#define STM32_PCLK1_MAX 170000000
+
+/**
+ * @brief Maximum APB clock frequency.
+ */
+#define STM32_PCLK2_MAX 170000000
+
+/**
+ * @brief Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX 60000000
+/** @} */
+
+/**
+ * @name Flash Wait states
+ * @{
+ */
+#define STM32_0WS_THRESHOLD 20000000
+#define STM32_1WS_THRESHOLD 40000000
+#define STM32_2WS_THRESHOLD 60000000
+#define STM32_3WS_THRESHOLD 80000000
+#define STM32_4WS_THRESHOLD 100000000
+#define STM32_5WS_THRESHOLD 120000000
+#define STM32_6WS_THRESHOLD 140000000
+#define STM32_7WS_THRESHOLD 160000000
+#define STM32_8WS_THRESHOLD 170000000
+/** @} */
+
+#elif STM32_VOS == STM32_VOS_RANGE2
+#define STM32_SYSCLK_MAX 26000000
+#define STM32_SYSCLK_MAX_NOBOOST 150000000
+#define STM32_HSECLK_MAX 26000000
+#define STM32_HSECLK_BYP_MAX 26000000
+#define STM32_HSECLK_MIN 8000000
+#define STM32_HSECLK_BYP_MIN 8000000
+#define STM32_LSECLK_MAX 32768
+#define STM32_LSECLK_BYP_MAX 1000000
+#define STM32_LSECLK_MIN 32768
+#define STM32_LSECLK_BYP_MIN 32768
+#define STM32_PLLIN_MAX 16000000
+#define STM32_PLLIN_MIN 2660000
+#define STM32_PLLVCO_MAX 128000000
+#define STM32_PLLVCO_MIN 96000000
+#define STM32_PLLP_MAX 26000000
+#define STM32_PLLP_MIN 2064500
+#define STM32_PLLQ_MAX 26000000
+#define STM32_PLLQ_MIN 8000000
+#define STM32_PLLR_MAX 26000000
+#define STM32_PLLR_MIN 8000000
+#define STM32_PCLK1_MAX 26000000
+#define STM32_PCLK2_MAX 26000000
+#define STM32_ADCCLK_MAX 26000000
+
+#define STM32_0WS_THRESHOLD 8000000
+#define STM32_1WS_THRESHOLD 16000000
+#define STM32_2WS_THRESHOLD 26000000
+#define STM32_3WS_THRESHOLD 0
+#define STM32_4WS_THRESHOLD 0
+#define STM32_5WS_THRESHOLD 0
+#define STM32_6WS_THRESHOLD 0
+#define STM32_7WS_THRESHOLD 0
+#define STM32_8WS_THRESHOLD 0
+
+#else
+#error "invalid STM32_VOS value specified"
+#endif
+
+/*
+ * HSI16 related checks.
+ */
+#if STM32_HSI16_ENABLED
+#else /* !STM32_HSI16_ENABLED */
+
+ #if STM32_SW == STM32_SW_HSI16
+ #error "HSI16 not enabled, required by STM32_SW"
+ #endif
+
+ #if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSI16)
+ #error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC"
+ #endif
+
+ #if (STM32_MCOSEL == STM32_MCOSEL_HSI16) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI16))
+ #error "HSI16 not enabled, required by STM32_MCOSEL"
+ #endif
+
+ #if (STM32_USART1SEL == STM32_USART1SEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_USART1SEL"
+ #endif
+ #if (STM32_USART2SEL == STM32_USART2SEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_USART2SEL"
+ #endif
+ #if (STM32_USART3SEL == STM32_USART3SEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_USART3SEL"
+ #endif
+ #if (STM32_UART4SEL == STM32_UART4SEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_UART4SEL_HSI16"
+ #endif
+ #if (STM32_UART5SEL == STM32_UART5SEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_UART5SEL_HSI16"
+ #endif
+ #if (STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_LPUART1SEL"
+ #endif
+
+ #if (STM32_I2C1SEL == STM32_I2C1SEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_I2C1SEL"
+ #endif
+ #if (STM32_I2C2SEL == STM32_I2C2SEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_I2C2SEL"
+ #endif
+ #if (STM32_I2C3SEL == STM32_I2C3SEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_I2C3SEL"
+ #endif
+ #if (STM32_I2C4SEL == STM32_I2C4SEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_I2C4SEL"
+ #endif
+
+ #if (STM32_SAI1SEL == STM32_SAI1SEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_SAI1SEL"
+ #endif
+ #if (STM32_I2S23SEL == STM32_I2S23SEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_I2S23SEL"
+ #endif
+
+ #if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_LPTIM1SEL"
+ #endif
+
+ #if (STM32_QSPISEL == STM32_QSPISEL_HSI16)
+ #error "HSI16 not enabled, required by STM32_QSPISEL_HSI16"
+ #endif
+
+#endif /* !STM32_HSI16_ENABLED */
+
+/*
+ * HSI48 related checks.
+ */
+#if STM32_HSI48_ENABLED
+#else /* !STM32_HSI48_ENABLED */
+
+ #if STM32_MCOSEL == STM32_MCOSEL_HSI48
+ #error "HSI48 not enabled, required by STM32_MCOSEL"
+ #endif
+
+ #if STM32_CLK48SEL == STM32_CLK48SEL_HSI48
+ #error "HSI48 not enabled, required by STM32_CLK48SEL"
+ #endif
+
+#endif /* !STM32_HSI48_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+ #if STM32_HSECLK == 0
+ #error "HSE frequency not defined"
+ #else /* STM32_HSECLK != 0 */
+ #if defined(STM32_HSE_BYPASS)
+ #if (STM32_HSECLK < STM32_HSECLK_BYP_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
+ #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_BYP_MIN...STM32_HSECLK_BYP_MAX)"
+ #endif
+ #else /* !defined(STM32_HSE_BYPASS) */
+ #if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+ #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+ #endif
+ #endif /* !defined(STM32_HSE_BYPASS) */
+ #endif /* STM32_HSECLK != 0 */
+
+#else /* !STM32_HSE_ENABLED */
+
+ #if STM32_SW == STM32_SW_HSE
+ #error "HSE not enabled, required by STM32_SW"
+ #endif
+
+ #if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+ #error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+ #endif
+
+ #if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE))
+ #error "HSE not enabled, required by STM32_MCOSEL"
+ #endif
+
+ #if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+ #error "HSE not enabled, required by STM32_RTCSEL"
+ #endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+ #if STM32_RTCSEL == STM32_RTCSEL_LSI
+ #error "LSI not enabled, required by STM32_RTCSEL"
+ #endif
+
+ #if STM32_MCOSEL == STM32_MCOSEL_LSI
+ #error "LSI not enabled, required by STM32_MCOSEL"
+ #endif
+
+ #if STM32_LSCOSEL == STM32_LSCOSEL_LSI
+ #error "LSI not enabled, required by STM32_LSCOSEL"
+ #endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+ #if (STM32_LSECLK == 0)
+ #error "LSE frequency not defined"
+ #endif
+
+ #if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+ #error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+ #endif
+
+#else /* !STM32_LSE_ENABLED */
+
+ #if STM32_RTCSEL == STM32_RTCSEL_LSE
+ #error "LSE not enabled, required by STM32_RTCSEL"
+ #endif
+
+ #if STM32_MCOSEL == STM32_MCOSEL_LSE
+ #error "LSE not enabled, required by STM32_MCOSEL"
+ #endif
+
+ #if STM32_LSCOSEL == STM32_LSCOSEL_LSE
+ #error "LSE not enabled, required by STM32_LSCOSEL"
+ #endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/**
+ * @brief STM32_PLLM field.
+ */
+#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 16)) || \
+ defined(__DOXYGEN__)
+ #define STM32_PLLM ((STM32_PLLM_VALUE - 1) << 4)
+#else
+ #error "invalid STM32_PLLM_VALUE value specified"
+#endif
+
+/**
+ * @brief PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+ #define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
+ #define STM32_PLLCLKIN (STM32_HSI16CLK / STM32_PLLM_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
+ #define STM32_PLLCLKIN 0
+
+#else
+ #error "invalid STM32_PLLSRC value specified"
+#endif
+
+/*
+ * PLL input frequency range check.
+ */
+#if (STM32_PLLCLKIN != 0) && \
+ ((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX))
+ #error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/*
+ * PLL enable check.
+ */
+#if (STM32_SW == STM32_SW_PLLRCLK) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
+ (STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK) || \
+ (STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK) || \
+ (STM32_SAI1SEL == STM32_SAI1SEL_PLLQCLK) || \
+ (STM32_I2S23SEL == STM32_I2S23SEL_PLLQCLK) || \
+ (STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
+ (STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK) || \
+ (STM32_QSPISEL == STM32_QSPISEL_PLLQCLK) || \
+ defined(__DOXYGEN__)
+
+ #if STM32_PLLCLKIN == 0
+ #error "PLL activation required but no PLL clock selected"
+ #endif
+
+ /**
+ * @brief PLL activation flag.
+ */
+ #define STM32_ACTIVATE_PLL TRUE
+#else
+ #define STM32_ACTIVATE_PLL FALSE
+#endif
+
+/**
+ * @brief STM32_PLLN field.
+ */
+#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 127)) || \
+ defined(__DOXYGEN__)
+ #define STM32_PLLN (STM32_PLLN_VALUE << 8)
+#else
+ #error "invalid STM32_PLLN_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLP field.
+ */
+#if (STM32_PLLP_VALUE == 7) || defined(__DOXYGEN__)
+ #define STM32_PLLP (0 << 17)
+
+#elif STM32_PLLP_VALUE == 17
+ #define STM32_PLLP (1 << 17)
+
+#else
+ #error "invalid STM32_PLLP_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLQ field.
+ */
+#if (STM32_PLLQ_VALUE == 2) || defined(__DOXYGEN__)
+ #define STM32_PLLQ (0 << 21)
+
+#elif STM32_PLLQ_VALUE == 4
+ #define STM32_PLLQ (1 << 21)
+
+#elif STM32_PLLQ_VALUE == 6
+ #define STM32_PLLQ (2 << 21)
+
+#elif STM32_PLLQ_VALUE == 8
+ #define STM32_PLLQ (3 << 21)
+
+#else
+ #error "invalid STM32_PLLQ_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLR field.
+ */
+#if (STM32_PLLR_VALUE == 2) || defined(__DOXYGEN__)
+ #define STM32_PLLR (0 << 25)
+
+#elif STM32_PLLR_VALUE == 4
+ #define STM32_PLLR (1 << 25)
+
+#elif STM32_PLLR_VALUE == 6
+ #define STM32_PLLR (2 << 25)
+
+#elif STM32_PLLR_VALUE == 8
+ #define STM32_PLLR (3 << 25)
+
+#else
+ #error "invalid STM32_PLLR_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLPDIV field.
+ */
+#if (STM32_PLLPDIV_VALUE == 0) || \
+ ((STM32_PLLPDIV_VALUE >= 2) && (STM32_PLLPDIV_VALUE <= 31)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLPDIV (STM32_PLLPDIV_VALUE << 27)
+#else
+#error "invalid STM32_PLLPDIV_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLPEN field.
+ */
+#if (STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK) || \
+ (STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK) || \
+ defined(__DOXYGEN__)
+ #define STM32_PLLPEN (1 << 16)
+#else
+ #define STM32_PLLPEN (0 << 16)
+#endif
+
+/**
+ * @brief STM32_PLLQEN field.
+ */
+#if (STM32_QSPISEL == STM32_QSPISEL_PLLQCLK) || \
+ (STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
+ (STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK) || \
+ (STM32_SAI1SEL == STM32_SAI1SEL_PLLQCLK) || \
+ (STM32_I2S23SEL == STM32_I2S23SEL_PLLQCLK) || \
+ defined(__DOXYGEN__)
+ #define STM32_PLLQEN (1 << 20)
+#else
+ #define STM32_PLLQEN (0 << 20)
+#endif
+
+/**
+ * @brief STM32_PLLREN field.
+ */
+#if (STM32_SW == STM32_SW_PLLRCLK) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
+ defined(__DOXYGEN__)
+ #define STM32_PLLREN (1 << 24)
+#else
+ #define STM32_PLLREN (0 << 24)
+#endif
+
+/**
+ * @brief PLL VCO frequency.
+ */
+#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
+
+/*
+ * PLL VCO frequency range check.
+ */
+#if STM32_ACTIVATE_PLL && \
+ ((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX))
+ #error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLL P output clock frequency.
+ */
+#if (STM32_PLLPDIV_VALUE == 0) || defined(__DOXYGEN__)
+ #define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
+#else
+ #define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLPDIV_VALUE)
+#endif
+
+/**
+ * @brief PLL Q output clock frequency.
+ */
+#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE)
+
+/**
+ * @brief PLL R output clock frequency.
+ */
+#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE)
+
+/*
+ * PLL-P output frequency range check.
+ */
+#if STM32_ACTIVATE_PLL && \
+ ((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX))
+ #error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
+#endif
+
+/*
+ * PLL-Q output frequency range check.
+ */
+#if STM32_ACTIVATE_PLL && \
+ ((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX))
+ #error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
+#endif
+
+/*
+ * PLL-R output frequency range check.
+ */
+#if STM32_ACTIVATE_PLL && \
+ ((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX))
+ #error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
+#endif
+
+/**
+ * @brief System clock source.
+ */
+#if STM32_NO_INIT || defined(__DOXYGEN__)
+ #define STM32_SYSCLK STM32_HSI16CLK
+
+#elif (STM32_SW == STM32_SW_HSI16)
+ #define STM32_SYSCLK STM32_HSI16CLK
+
+#elif (STM32_SW == STM32_SW_HSE)
+ #define STM32_SYSCLK STM32_HSECLK
+
+#elif (STM32_SW == STM32_SW_PLLRCLK)
+ #define STM32_SYSCLK STM32_PLL_R_CLKOUT
+
+#else
+ #error "invalid STM32_SW value specified"
+#endif
+
+/*
+ * Check on the system clock.
+ */
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+ #error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+ #define STM32_HCLK (STM32_SYSCLK / 1)
+
+#elif STM32_HPRE == STM32_HPRE_DIV2
+ #define STM32_HCLK (STM32_SYSCLK / 2)
+
+#elif STM32_HPRE == STM32_HPRE_DIV4
+ #define STM32_HCLK (STM32_SYSCLK / 4)
+
+#elif STM32_HPRE == STM32_HPRE_DIV8
+ #define STM32_HCLK (STM32_SYSCLK / 8)
+
+#elif STM32_HPRE == STM32_HPRE_DIV16
+ #define STM32_HCLK (STM32_SYSCLK / 16)
+
+#elif STM32_HPRE == STM32_HPRE_DIV64
+ #define STM32_HCLK (STM32_SYSCLK / 64)
+
+#elif STM32_HPRE == STM32_HPRE_DIV128
+ #define STM32_HCLK (STM32_SYSCLK / 128)
+
+#elif STM32_HPRE == STM32_HPRE_DIV256
+ #define STM32_HCLK (STM32_SYSCLK / 256)
+
+#elif STM32_HPRE == STM32_HPRE_DIV512
+ #define STM32_HCLK (STM32_SYSCLK / 512)
+
+#else
+ #error "invalid STM32_HPRE value specified"
+#endif
+
+/*
+ * AHB frequency check.
+ */
+#if STM32_HCLK > STM32_SYSCLK_MAX
+ #error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+ #define STM32_PCLK1 (STM32_HCLK / 1)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+ #define STM32_PCLK1 (STM32_HCLK / 2)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+ #define STM32_PCLK1 (STM32_HCLK / 4)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+ #define STM32_PCLK1 (STM32_HCLK / 8)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+ #define STM32_PCLK1 (STM32_HCLK / 16)
+
+#else
+ #error "invalid STM32_PPRE1 value specified"
+#endif
+
+/*
+ * APB1 frequency check.
+ */
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+ #define STM32_PCLK2 (STM32_HCLK / 1)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+ #define STM32_PCLK2 (STM32_HCLK / 2)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+ #define STM32_PCLK2 (STM32_HCLK / 4)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+ #define STM32_PCLK2 (STM32_HCLK / 8)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+ #define STM32_PCLK2 (STM32_HCLK / 16)
+
+#else
+ #error "invalid STM32_PPRE2 value specified"
+#endif
+
+/*
+ * APB2 frequency check.
+ */
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief MCO divider clock frequency.
+ */
+#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
+ #define STM32_MCODIVCLK 0
+
+#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
+ #define STM32_MCODIVCLK STM32_SYSCLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI16
+ #define STM32_MCODIVCLK STM32_HSI16CLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_HSE
+ #define STM32_MCODIVCLK STM32_HSECLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_PLLRCLK
+ #define STM32_MCODIVCLK STM32_PLL_R_CLKOUT
+
+#elif STM32_MCOSEL == STM32_MCOSEL_LSI
+ #define STM32_MCODIVCLK STM32_LSICLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_LSE
+ #define STM32_MCODIVCLK STM32_LSECLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI48
+ #define STM32_MCODIVCLK STM32_HSI48CLK
+
+#else
+ #error "invalid STM32_MCOSEL value specified"
+#endif
+
+/**
+ * @brief MCO output pin clock frequency.
+ */
+#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
+ #define STM32_MCOCLK STM32_MCODIVCLK
+
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
+ #define STM32_MCOCLK (STM32_MCODIVCLK / 2)
+
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
+ #define STM32_MCOCLK (STM32_MCODIVCLK / 4)
+
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
+ #define STM32_MCOCLK (STM32_MCODIVCLK / 8)
+
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
+ #define STM32_MCOCLK (STM32_MCODIVCLK / 16)
+
+#else
+#error "invalid STM32_MCOPRE value specified"
+#endif
+
+/**
+ * @brief RTC clock frequency.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
+ #define STM32_RTCCLK 0
+
+#elif STM32_RTCSEL == STM32_RTCSEL_LSE
+ #define STM32_RTCCLK STM32_LSECLK
+
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+ #define STM32_RTCCLK STM32_LSICLK
+
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+ #define STM32_RTCCLK (STM32_HSECLK / 32)
+
+#else
+ #error "invalid STM32_RTCSEL value specified"
+#endif
+
+/**
+ * @brief USART1 clock frequency.
+ */
+#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__)
+ #define STM32_USART1CLK STM32_PCLK2
+
+#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
+ #define STM32_USART1CLK STM32_SYSCLK
+
+#elif STM32_USART1SEL == STM32_USART1SEL_HSI16
+ #define STM32_USART1CLK STM32_HSI16CLK
+
+#elif STM32_USART1SEL == STM32_USART1SEL_LSE
+ #define STM32_USART1CLK STM32_LSECLK
+
+#else
+ #error "invalid source selected for USART1 clock"
+#endif
+
+ /**
+ * @brief USART2 clock frequency.
+ */
+ #if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__)
+ #define STM32_USART2CLK STM32_PCLK1
+
+ #elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
+ #define STM32_USART2CLK STM32_SYSCLK
+
+ #elif STM32_USART2SEL == STM32_USART2SEL_HSI16
+ #define STM32_USART2CLK STM32_HSI16CLK
+
+ #elif STM32_USART2SEL == STM32_USART2SEL_LSE
+ #define STM32_USART2CLK STM32_LSECLK
+
+ #else
+ #error "invalid source selected for USART2 clock"
+ #endif
+
+ /**
+ * @brief USART3 clock frequency.
+ */
+ #if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__)
+ #define STM32_USART3CLK STM32_PCLK1
+
+ #elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
+ #define STM32_USART3CLK STM32_SYSCLK
+
+ #elif STM32_USART3SEL == STM32_USART3SEL_HSI16
+ #define STM32_USART3CLK STM32_HSI16CLK
+
+ #elif STM32_USART3SEL == STM32_USART3SEL_LSE
+ #define STM32_USART3CLK STM32_LSECLK
+
+ #else
+ #error "invalid source selected for USART3 clock"
+ #endif
+
+/**
+ * @brief UART4 clock frequency.
+ */
+#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__)
+ #define STM32_UART4CLK STM32_PCLK1
+
+#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK
+ #define STM32_UART4CLK STM32_SYSCLK
+
+#elif STM32_UART4SEL == STM32_UART4SEL_HSI16
+ #define STM32_UART4CLK STM32_HSI16CLK
+
+#elif STM32_UART4SEL == STM32_UART4SEL_LSE
+ #define STM32_UART4CLK STM32_LSECLK
+
+#else
+ #error "invalid source selected for UART4 clock"
+#endif
+
+/**
+ * @brief UART5 clock frequency.
+ */
+#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__)
+ #define STM32_UART5CLK STM32_PCLK1
+
+#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK
+ #define STM32_UART5CLK STM32_SYSCLK
+
+#elif STM32_UART5SEL == STM32_UART5SEL_HSI16
+ #define STM32_UART5CLK STM32_HSI16CLK
+
+#elif STM32_UART5SEL == STM32_UART5SEL_LSE
+ #define STM32_UART5CLK STM32_LSECLK
+
+#else
+ #error "invalid source selected for UART5 clock"
+#endif
+
+/**
+ * @brief LPUART1 clock frequency.
+ */
+#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN__)
+ #define STM32_LPUART1CLK STM32_PCLK1
+
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
+ #define STM32_LPUART1CLK STM32_SYSCLK
+
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
+ #define STM32_LPUART1CLK STM32_HSI16CLK
+
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
+ #define STM32_LPUART1CLK STM32_LSECLK
+
+#else
+#error "invalid source selected for LPUART1 clock"
+#endif
+
+/**
+ * @brief I2C1 clock frequency.
+ */
+#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__)
+ #define STM32_I2C1CLK STM32_PCLK1
+
+#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
+ #define STM32_I2C1CLK STM32_SYSCLK
+
+#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16
+ #define STM32_I2C1CLK STM32_HSI16CLK
+
+#else
+ #error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief I2C2 clock frequency.
+ */
+#if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN__)
+ #define STM32_I2C2CLK STM32_PCLK1
+
+#elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK
+ #define STM32_I2C2CLK STM32_SYSCLK
+
+#elif STM32_I2C2SEL == STM32_I2C2SEL_HSI16
+ #define STM32_I2C2CLK STM32_HSI16CLK
+
+#else
+ #error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief I2C3 clock frequency.
+ */
+#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__)
+ #define STM32_I2C3CLK STM32_PCLK1
+
+#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK
+ #define STM32_I2C3CLK STM32_SYSCLK
+
+#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI16
+ #define STM32_I2C3CLK STM32_HSI16CLK
+
+#else
+ #error "invalid source selected for I2C3 clock"
+#endif
+
+/**
+ * @brief I2C4 clock frequency.
+ */
+#if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK1) || defined(__DOXYGEN__)
+ #define STM32_I2C4CLK STM32_PCLK1
+
+#elif STM32_I2C4SEL == STM32_I2C4SEL_SYSCLK
+ #define STM32_I2C4CLK STM32_SYSCLK
+
+#elif STM32_I2C4SEL == STM32_I2C4SEL_HSI16
+ #define STM32_I2C4CLK STM32_HSI16CLK
+
+#else
+ #error "invalid source selected for I2C4 clock"
+#endif
+
+/**
+ * @brief LPTIM1 clock frequency.
+ */
+#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__)
+ #define STM32_LPTIM1CLK STM32_PCLK1
+
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
+ #define STM32_LPTIM1CLK STM32_LSICLK
+
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16
+ #define STM32_LPTIM1CLK STM32_HSI16CLK
+
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
+ #define STM32_LPTIM1CLK STM32_LSECLK
+
+#else
+ #error "invalid source selected for LPTIM1 clock"
+#endif
+
+/**
+ * @brief SAI1 clock frequency.
+ */
+#if (STM32_SAI1SEL == STM32_SAI1SEL_SYSCLK) || defined(__DOXYGEN__)
+ #define STM32_SAI1CLK STM32_SYSCLK
+
+#elif STM32_SAI1SEL == STM32_SAI1SEL_PLLQCLK
+ #define STM32_SAI1CLK STM32_PLL_Q_CLKOUT
+
+#elif STM32_SAI1SEL == STM32_SAI1SEL_HSI16
+ #define STM32_SAI1CLK STM32_HSI16CLK
+
+#elif STM32_SAI1SEL == STM32_SAI1SEL_CKIN
+ #define STM32_SAI1CLK 0 /* Unknown, would require a board value */
+
+#else
+ #error "invalid source selected for SAI1 clock"
+#endif
+
+/**
+ * @brief I2S23 clock frequency.
+ */
+#if (STM32_I2S23SEL == STM32_I2S23SEL_SYSCLK) || defined(__DOXYGEN__)
+ #define STM32_I2S23CLK STM32_SYSCLK
+
+#elif STM32_I2S23SEL == STM32_I2S23SEL_PLLPCLK
+ #define STM32_I2S23CLK STM32_PLL_P_CLKOUT
+
+#elif STM32_I2S23SEL == STM32_I2S23SEL_HSI16
+ #define STM32_I2S23CLK STM32_HSI16CLK
+
+#elif STM32_I2S23SEL == STM32_I2S23SEL_CKIN
+ #define STM32_I2S23CLK 0 /* Unknown, would require a board value */
+
+#else
+ #error "invalid source selected for SAI1 clock"
+#endif
+
+/**
+ * @brief FDCAN clock frequency.
+ */
+#if (STM32_FDCANSEL == STM32_FDCANSEL_HSE) || defined(__DOXYGEN__)
+ #define STM32_FDCANCLK STM32_HSECLK
+
+#elif STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK
+ #define STM32_FDCANCLK STM32_PLL_Q_CLKOUT
+
+#elif STM32_FDCANSEL == STM32_FDCANSEL_PCLK1
+ #define STM32_FDCANCLK STM32_PCLK1
+
+#else
+ #error "invalid source selected for FDCAN clock"
+#endif
+
+/**
+ * @brief 48MHz clock frequency.
+ */
+#if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__)
+ #define STM32_48CLK STM32_HSI48CLK
+
+#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK
+ #define STM32_48CLK STM32_PLL_Q_CLKOUT
+
+#else
+ #error "invalid source selected for 48MHz clock"
+#endif
+
+/**
+ * @brief ADC clock frequency.
+ */
+#if (STM32_ADC12SEL == STM32_ADC12SEL_NOCLK) || defined(__DOXYGEN__)
+ #define STM32_ADC12CLK 0
+
+#elif STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK
+ #define STM32_ADC12CLK STM32_PLL_P_CLKOUT
+
+#elif STM32_ADC12SEL == STM32_ADC12SEL_SYSCLK
+ #define STM32_ADC12CLK STM32_SYSCLK
+
+#else
+ #error "invalid source selected for ADC clock"
+#endif
+
+/**
+ * @brief ADC clock frequency.
+ */
+#if (STM32_ADC345SEL == STM32_ADC345SEL_NOCLK) || defined(__DOXYGEN__)
+ #define STM32_ADC345CLK 0
+
+#elif STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK
+ #define STM32_ADC345CLK STM32_PLL_P_CLKOUT
+
+#elif STM32_ADC345SEL == STM32_ADC345SEL_SYSCLK
+ #define STM32_ADC345CLK STM32_SYSCLK
+
+#else
+ #error "invalid source selected for ADC clock"
+#endif
+
+/**
+ * @brief TIMP1CLK clock frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+ #define STM32_TIMP1CLK (STM32_PCLK1 * 1)
+#else
+ #define STM32_TIMP1CLK (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief TIMP2CLK clock frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+ #define STM32_TIMP2CLK (STM32_PCLK2 * 1)
+#else
+ #define STM32_TIMP2CLK (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief Clock of timers connected to APB1.
+ */
+#define STM32_TIMCLK1 STM32_TIMP1CLK
+
+/**
+ * @brief Clock of timers connected to APB2.
+ */
+#define STM32_TIMCLK2 STM32_TIMP2CLK
+
+/**
+ * @brief RNG clock point.
+ */
+#define STM32_RNGCLK STM32_48CLK
+
+/**
+ * @brief USB clock point.
+ */
+#define STM32_USBCLK STM32_48CLK
+
+/**
+ * @brief Flash settings.
+ */
+#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
+ #define STM32_FLASHBITS 0
+
+#elif STM32_HCLK <= STM32_1WS_THRESHOLD
+ #define STM32_FLASHBITS FLASH_ACR_LATENCY_0WS
+
+#elif STM32_HCLK <= STM32_2WS_THRESHOLD
+ #define STM32_FLASHBITS FLASH_ACR_LATENCY_1WS
+
+#elif STM32_HCLK <= STM32_3WS_THRESHOLD
+ #define STM32_FLASHBITS FLASH_ACR_LATENCY_2WS
+
+#elif STM32_HCLK <= STM32_4WS_THRESHOLD
+ #define STM32_FLASHBITS FLASH_ACR_LATENCY_3WS
+
+#elif STM32_HCLK <= STM32_5WS_THRESHOLD
+ #define STM32_FLASHBITS FLASH_ACR_LATENCY_4WS
+
+#elif STM32_HCLK <= STM32_6WS_THRESHOLD
+ #define STM32_FLASHBITS FLASH_ACR_LATENCY_5WS
+
+#elif STM32_HCLK <= STM32_7WS_THRESHOLD
+ #define STM32_FLASHBITS FLASH_ACR_LATENCY_6WS
+
+#elif STM32_HCLK <= STM32_8WS_THRESHOLD
+ #define STM32_FLASHBITS FLASH_ACR_LATENCY_7WS
+
+#else
+ #define STM32_FLASHBITS FLASH_ACR_LATENCY_8WS
+#endif
+
+/* Frequency-dependent settings for PWR_CR5.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX_NOBOOST
+#define STM32_CR5BITS 0
+#else
+#define STM32_CR5BITS PWR_CR5_R1MODE
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "cache.h"
+#include "mpu_v7m.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_exti.h"
+#include "stm32_rcc.h"
+#include "stm32_tim.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/platform.mk b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/platform.mk new file mode 100644 index 0000000..f1d83a1 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/platform.mk @@ -0,0 +1,46 @@ +# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx/stm32_isr.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+
+# Configuration files directory
+ifeq ($(HALCONFDIR),)
+ ifeq ($(CONFDIR),)
+ HALCONFDIR = .
+ else
+ HALCONFDIR := $(CONFDIR)
+ endif
+endif
+
+HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
+
+else
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/FDCANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC)
+ALLINC += $(PLATFORMINC)
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_dmamux.h b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_dmamux.h new file mode 100644 index 0000000..f4aec57 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_dmamux.h @@ -0,0 +1,183 @@ +/*
+ ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32G4xx/stm32_dmamux.h
+ * @brief STM32G4xx DMAMUX handler header.
+ *
+ * @addtogroup STM32G4xx_DMAMUX
+ * @{
+ */
+
+#ifndef STM32_DMAMUX_H
+#define STM32_DMAMUX_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name DMAMUX1 request sources
+ * @{
+ */
+#define STM32_DMAMUX1_REQ_GEN0 1
+#define STM32_DMAMUX1_REQ_GEN1 2
+#define STM32_DMAMUX1_REQ_GEN2 3
+#define STM32_DMAMUX1_REQ_GEN3 4
+#define STM32_DMAMUX1_ADC1 5
+#define STM32_DMAMUX1_DAC1_CH1 6
+#define STM32_DMAMUX1_DAC1_CH2 7
+#define STM32_DMAMUX1_TIM6_UP 8
+#define STM32_DMAMUX1_TIM7_UP 9
+#define STM32_DMAMUX1_SPI1_RX 10
+#define STM32_DMAMUX1_SPI1_TX 11
+#define STM32_DMAMUX1_SPI2_RX 12
+#define STM32_DMAMUX1_SPI2_TX 13
+#define STM32_DMAMUX1_SPI3_RX 14
+#define STM32_DMAMUX1_SPI3_TX 15
+#define STM32_DMAMUX1_I2C1_RX 16
+#define STM32_DMAMUX1_I2C1_TX 17
+#define STM32_DMAMUX1_I2C2_RX 18
+#define STM32_DMAMUX1_I2C2_TX 19
+#define STM32_DMAMUX1_I2C3_RX 20
+#define STM32_DMAMUX1_I2C3_TX 21
+#define STM32_DMAMUX1_I2C4_RX 22
+#define STM32_DMAMUX1_I2C4_TX 23
+#define STM32_DMAMUX1_USART1_RX 24
+#define STM32_DMAMUX1_USART1_TX 25
+#define STM32_DMAMUX1_USART2_RX 26
+#define STM32_DMAMUX1_USART2_TX 27
+#define STM32_DMAMUX1_USART3_RX 28
+#define STM32_DMAMUX1_USART3_TX 29
+#define STM32_DMAMUX1_UART4_RX 30
+#define STM32_DMAMUX1_UART4_TX 31
+#define STM32_DMAMUX1_UART5_RX 32
+#define STM32_DMAMUX1_UART5_TX 33
+#define STM32_DMAMUX1_LPUART1_RX 34
+#define STM32_DMAMUX1_LPUART1_TX 35
+#define STM32_DMAMUX1_ADC2 36
+#define STM32_DMAMUX1_ADC3 37
+#define STM32_DMAMUX1_ADC4 38
+#define STM32_DMAMUX1_ADC5 39
+#define STM32_DMAMUX1_QUADSPI 40
+#define STM32_DMAMUX1_DAC2_CH1 41
+#define STM32_DMAMUX1_TIM1_CH1 42
+#define STM32_DMAMUX1_TIM1_CH2 43
+#define STM32_DMAMUX1_TIM1_CH3 44
+#define STM32_DMAMUX1_TIM1_CH4 45
+#define STM32_DMAMUX1_TIM1_UP 46
+#define STM32_DMAMUX1_TIM1_TRIG 47
+#define STM32_DMAMUX1_TIM1_COM 48
+#define STM32_DMAMUX1_TIM8_CH1 49
+#define STM32_DMAMUX1_TIM8_CH2 50
+#define STM32_DMAMUX1_TIM8_CH3 51
+#define STM32_DMAMUX1_TIM8_CH4 52
+#define STM32_DMAMUX1_TIM8_UP 53
+#define STM32_DMAMUX1_TIM8_TRIG 54
+#define STM32_DMAMUX1_TIM8_COM 55
+#define STM32_DMAMUX1_TIM2_CH1 56
+#define STM32_DMAMUX1_TIM2_CH2 57
+#define STM32_DMAMUX1_TIM2_CH3 58
+#define STM32_DMAMUX1_TIM2_CH4 59
+#define STM32_DMAMUX1_TIM2_UP 60
+#define STM32_DMAMUX1_TIM3_CH1 61
+#define STM32_DMAMUX1_TIM3_CH2 62
+#define STM32_DMAMUX1_TIM3_CH3 63
+#define STM32_DMAMUX1_TIM3_CH4 64
+#define STM32_DMAMUX1_TIM3_UP 65
+#define STM32_DMAMUX1_TIM3_TRIG 66
+#define STM32_DMAMUX1_TIM4_CH1 67
+#define STM32_DMAMUX1_TIM4_CH2 68
+#define STM32_DMAMUX1_TIM4_CH3 69
+#define STM32_DMAMUX1_TIM4_CH4 70
+#define STM32_DMAMUX1_TIM4_UP 71
+#define STM32_DMAMUX1_TIM5_CH1 72
+#define STM32_DMAMUX1_TIM5_CH2 73
+#define STM32_DMAMUX1_TIM5_CH3 74
+#define STM32_DMAMUX1_TIM5_CH4 75
+#define STM32_DMAMUX1_TIM5_UP 76
+#define STM32_DMAMUX1_TIM5_TRIG 77
+#define STM32_DMAMUX1_TIM15_CH1 78
+#define STM32_DMAMUX1_TIM15_UP 79
+#define STM32_DMAMUX1_TIM15_TRIG 80
+#define STM32_DMAMUX1_TIM15_COM 81
+#define STM32_DMAMUX1_TIM16_CH1 82
+#define STM32_DMAMUX1_TIM16_UP 83
+#define STM32_DMAMUX1_TIM17_CH1 84
+#define STM32_DMAMUX1_TIM17_UP 85
+#define STM32_DMAMUX1_TIM20_CH1 86
+#define STM32_DMAMUX1_TIM20_CH2 87
+#define STM32_DMAMUX1_TIM20_CH3 88
+#define STM32_DMAMUX1_TIM20_CH4 89
+#define STM32_DMAMUX1_TIM20_UP 90
+#define STM32_DMAMUX1_AES_IN 91
+#define STM32_DMAMUX1_AES_OUT 92
+#define STM32_DMAMUX1_TIM20_TRIG 93
+#define STM32_DMAMUX1_TIM20_COM 94
+#define STM32_DMAMUX1_HRTIM_MASTER 95
+#define STM32_DMAMUX1_HRTIM_TIMA 96
+#define STM32_DMAMUX1_HRTIM_TIMB 97
+#define STM32_DMAMUX1_HRTIM_TIMC 98
+#define STM32_DMAMUX1_HRTIM_TIMD 99
+#define STM32_DMAMUX1_HRTIM_TIME 100
+#define STM32_DMAMUX1_HRTIM_TIMF 101
+#define STM32_DMAMUX1_DAC3_CH1 102
+#define STM32_DMAMUX1_DAC3_CH2 103
+#define STM32_DMAMUX1_DAC4_CH1 104
+#define STM32_DMAMUX1_DAC4_CH2 105
+#define STM32_DMAMUX1_SPI4_RX 106
+#define STM32_DMAMUX1_SPI4_TX 107
+#define STM32_DMAMUX1_SAI1_A 108
+#define STM32_DMAMUX1_SAI1_B 109
+#define STM32_DMAMUX1_FMAC_READ 110
+#define STM32_DMAMUX1_FMAC_WRITE 111
+#define STM32_DMAMUX1_CORDIC_READ 112
+#define STM32_DMAMUX1_CORDIC_WRITE 113
+#define STM32_DMAMUX1_UCPD1_RX 114
+#define STM32_DMAMUX1_UCPD1_TX 115
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_DMAMUX_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_isr.c b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_isr.c new file mode 100644 index 0000000..44138bd --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_isr.c @@ -0,0 +1,183 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32G4xx/stm32_isr.c
+ * @brief STM32G4xx ISR handler code.
+ *
+ * @addtogroup STM32G4xx_ISR
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define exti_serve_irq(pr, channel) { \
+ \
+ if ((pr) & (1U << (channel))) { \
+ _pal_isr_code(channel); \
+ } \
+}
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#include "stm32_exti0.inc"
+#include "stm32_exti1.inc"
+#include "stm32_exti2.inc"
+#include "stm32_exti3.inc"
+#include "stm32_exti4.inc"
+#include "stm32_exti5_9.inc"
+#include "stm32_exti10_15.inc"
+#include "stm32_exti16-40_41.inc"
+#include "stm32_exti17.inc"
+#include "stm32_exti18.inc"
+#include "stm32_exti19.inc"
+#include "stm32_exti20.inc"
+#include "stm32_exti21_22-29.inc"
+#include "stm32_exti30_32.inc"
+#include "stm32_exti33.inc"
+
+#include "stm32_fdcan1.inc"
+#include "stm32_fdcan2.inc"
+#include "stm32_fdcan3.inc"
+
+#include "stm32_usart1.inc"
+#include "stm32_usart2.inc"
+#include "stm32_usart3.inc"
+#include "stm32_uart4.inc"
+#include "stm32_uart5.inc"
+#include "stm32_lpuart1.inc"
+
+#include "stm32_tim1_15_16_17.inc"
+#include "stm32_tim2.inc"
+#include "stm32_tim3.inc"
+#include "stm32_tim4.inc"
+#include "stm32_tim5.inc"
+#include "stm32_tim6.inc"
+#include "stm32_tim7.inc"
+#include "stm32_tim8.inc"
+#include "stm32_tim20.inc"
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables IRQ sources.
+ *
+ * @notapi
+ */
+void irqInit(void) {
+
+ exti0_irq_init();
+ exti1_irq_init();
+ exti2_irq_init();
+ exti3_irq_init();
+ exti4_irq_init();
+ exti5_9_irq_init();
+ exti10_15_irq_init();
+ exti16_exti40_exti41_irq_init();
+ exti17_irq_init();
+ exti18_irq_init();
+ exti19_irq_init();
+ exti21_exti22_exti29_irq_init();
+ exti30_32_irq_init();
+ exti33_irq_init();
+
+ fdcan1_irq_init();
+ fdcan2_irq_init();
+ fdcan3_irq_init();
+
+ tim1_tim15_tim16_tim17_irq_init();
+ tim2_irq_init();
+ tim3_irq_init();
+ tim4_irq_init();
+ tim5_irq_init();
+ tim6_irq_init();
+ tim7_irq_init();
+ tim8_irq_init();
+ tim20_irq_init();
+
+ usart1_irq_init();
+ usart2_irq_init();
+ usart3_irq_init();
+ uart4_irq_init();
+ uart5_irq_init();
+ lpuart1_irq_init();
+}
+
+/**
+ * @brief Disables IRQ sources.
+ *
+ * @notapi
+ */
+void irqDeinit(void) {
+
+ exti0_irq_deinit();
+ exti1_irq_deinit();
+ exti2_irq_deinit();
+ exti3_irq_deinit();
+ exti4_irq_deinit();
+ exti5_9_irq_deinit();
+ exti10_15_irq_deinit();
+ exti16_exti40_exti41_irq_deinit();
+ exti17_irq_deinit();
+ exti18_irq_deinit();
+ exti19_irq_deinit();
+ exti21_exti22_exti29_irq_deinit();
+ exti30_32_irq_deinit();
+ exti33_irq_deinit();
+
+ fdcan1_irq_deinit();
+ fdcan2_irq_deinit();
+ fdcan3_irq_deinit();
+
+ tim1_tim15_tim16_tim17_irq_deinit();
+ tim2_irq_deinit();
+ tim3_irq_deinit();
+ tim4_irq_deinit();
+ tim5_irq_deinit();
+ tim6_irq_deinit();
+ tim7_irq_deinit();
+ tim8_irq_deinit();
+ tim20_irq_deinit();
+
+ usart1_irq_deinit();
+ usart2_irq_deinit();
+ usart3_irq_deinit();
+ uart4_irq_deinit();
+ uart5_irq_deinit();
+ lpuart1_irq_deinit();
+}
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_isr.h b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_isr.h new file mode 100644 index 0000000..a785fe6 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_isr.h @@ -0,0 +1,290 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32G4xx/stm32_isr.h
+ * @brief STM32G4xx ISR handler header.
+ *
+ * @addtogroup STM32G4xx_ISR
+ * @{
+ */
+
+#ifndef STM32_ISR_H
+#define STM32_ISR_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name ISRs suppressed in standard drivers
+ * @{
+ */
+#define STM32_TIM1_SUPPRESS_ISR
+#define STM32_TIM2_SUPPRESS_ISR
+#define STM32_TIM3_SUPPRESS_ISR
+#define STM32_TIM4_SUPPRESS_ISR
+#define STM32_TIM5_SUPPRESS_ISR
+#define STM32_TIM6_SUPPRESS_ISR
+#define STM32_TIM7_SUPPRESS_ISR
+#define STM32_TIM8_SUPPRESS_ISR
+#define STM32_TIM15_SUPPRESS_ISR
+#define STM32_TIM16_SUPPRESS_ISR
+#define STM32_TIM17_SUPPRESS_ISR
+#define STM32_TIM20_SUPPRESS_ISR
+
+#define STM32_USART1_SUPPRESS_ISR
+#define STM32_USART2_SUPPRESS_ISR
+#define STM32_USART3_SUPPRESS_ISR
+#define STM32_UART4_SUPPRESS_ISR
+#define STM32_UART5_SUPPRESS_ISR
+#define STM32_LPUART1_SUPPRESS_ISR
+/** @} */
+
+/**
+ * @name ISR names and numbers
+ * @{
+ */
+/*
+ * ADC unit.
+ */
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC3_HANDLER VectorFC
+#define STM32_ADC4_HANDLER Vector134
+#define STM32_ADC5_HANDLER Vector138
+
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC3_NUMBER 47
+#define STM32_ADC4_NUMBER 61
+#define STM32_ADC5_NUMBER 62
+
+/*
+ * DMA unit.
+ */
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH8_HANDLER Vector1C0
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH6_HANDLER Vector1C4
+#define STM32_DMA2_CH7_HANDLER Vector1C8
+#define STM32_DMA2_CH8_HANDLER Vector1CC
+
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+#define STM32_DMA1_CH8_NUMBER 96
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+#define STM32_DMA2_CH6_NUMBER 97
+#define STM32_DMA2_CH7_NUMBER 98
+#define STM32_DMA2_CH8_NUMBER 99
+
+/*
+ * EXTI unit.
+ */
+#define STM32_EXTI0_HANDLER Vector58
+#define STM32_EXTI1_HANDLER Vector5C
+#define STM32_EXTI2_HANDLER Vector60
+#define STM32_EXTI3_HANDLER Vector64
+#define STM32_EXTI4_HANDLER Vector68
+#define STM32_EXTI5_9_HANDLER Vector9C
+#define STM32_EXTI10_15_HANDLER VectorE0
+#define STM32_EXTI164041_HANDLER Vector44 /* PVD PVM */
+#define STM32_EXTI17_HANDLER VectorE4 /* RTC ALARM */
+#define STM32_EXTI18_HANDLER VectorE8 /* USB WAKEUP */
+#define STM32_EXTI19_HANDLER Vector48 /* RTC TAMP CSS */
+#define STM32_EXTI20_HANDLER Vector4C /* RTC WAKEUP */
+#define STM32_EXTI212229_HANDLER Vector140 /* COMP1..3 */
+#define STM32_EXTI30_32_HANDLER Vector144 /* COMP4..6 */
+#define STM32_EXTI33_HANDLER Vector148 /* COMP7 */
+
+#define STM32_EXTI0_NUMBER 6
+#define STM32_EXTI1_NUMBER 7
+#define STM32_EXTI2_NUMBER 8
+#define STM32_EXTI3_NUMBER 9
+#define STM32_EXTI4_NUMBER 10
+#define STM32_EXTI5_9_NUMBER 23
+#define STM32_EXTI10_15_NUMBER 40
+#define STM32_EXTI164041_NUMBER 1
+#define STM32_EXTI17_NUMBER 41
+#define STM32_EXTI18_NUMBER 42
+#define STM32_EXTI19_NUMBER 2
+#define STM32_EXTI20_NUMBER 3
+#define STM32_EXTI212229_NUMBER 64
+#define STM32_EXTI30_32_NUMBER 65
+#define STM32_EXTI33_NUMBER 66
+
+/*
+ * FDCAN units.
+ */
+#define STM32_FDCAN1_IT0_HANDLER Vector94
+#define STM32_FDCAN1_IT1_HANDLER Vector98
+#define STM32_FDCAN2_IT0_HANDLER Vector198
+#define STM32_FDCAN2_IT1_HANDLER Vector19C
+#define STM32_FDCAN3_IT0_HANDLER Vector1A0
+#define STM32_FDCAN3_IT1_HANDLER Vector1A4
+
+#define STM32_FDCAN1_IT0_NUMBER 21
+#define STM32_FDCAN1_IT1_NUMBER 22
+#define STM32_FDCAN2_IT0_NUMBER 86
+#define STM32_FDCAN2_IT1_NUMBER 87
+#define STM32_FDCAN3_IT0_NUMBER 88
+#define STM32_FDCAN3_IT1_NUMBER 89
+
+/*
+ * I2C units.
+ */
+#define STM32_I2C1_EVENT_HANDLER VectorBC
+#define STM32_I2C1_ERROR_HANDLER VectorC0
+#define STM32_I2C2_EVENT_HANDLER VectorC4
+#define STM32_I2C2_ERROR_HANDLER VectorC8
+#define STM32_I2C3_EVENT_HANDLER Vector1B0
+#define STM32_I2C3_ERROR_HANDLER Vector1B4
+#define STM32_I2C4_EVENT_HANDLER Vector188
+#define STM32_I2C4_ERROR_HANDLER Vector18C
+
+#define STM32_I2C1_EVENT_NUMBER 31
+#define STM32_I2C1_ERROR_NUMBER 32
+#define STM32_I2C2_EVENT_NUMBER 33
+#define STM32_I2C2_ERROR_NUMBER 34
+#define STM32_I2C3_EVENT_NUMBER 92
+#define STM32_I2C3_ERROR_NUMBER 93
+#define STM32_I2C4_EVENT_NUMBER 82
+#define STM32_I2C4_ERROR_NUMBER 83
+
+/*
+ * QUADSPI unit.
+ */
+#define STM32_QUADSPI1_HANDLER Vector1BC
+#define STM32_QUADSPI1_NUMBER 95
+
+/*
+ * TIM units.
+ */
+#define STM32_TIM1_BRK_TIM15_HANDLER VectorA0
+#define STM32_TIM1_UP_TIM16_HANDLER VectorA4
+#define STM32_TIM1_TRGCO_TIM17_HANDLER VectorA8
+#define STM32_TIM1_CC_HANDLER VectorAC
+#define STM32_TIM2_HANDLER VectorB0
+#define STM32_TIM3_HANDLER VectorB4
+#define STM32_TIM4_HANDLER VectorB8
+#define STM32_TIM5_HANDLER Vector108
+#define STM32_TIM6_HANDLER Vector118
+#define STM32_TIM7_HANDLER Vector11C
+#define STM32_TIM8_BRK_HANDLER VectorEC
+#define STM32_TIM8_UP_HANDLER VectorF0
+#define STM32_TIM8_TRGCO_HANDLER VectorF4
+#define STM32_TIM8_CC_HANDLER VectorF8
+#define STM32_TIM20_BRK_HANDLER Vector174
+#define STM32_TIM20_UP_HANDLER Vector178
+#define STM32_TIM20_TRGCO_HANDLER Vector17C
+#define STM32_TIM20_CC_HANDLER Vector180
+
+#define STM32_TIM1_BRK_TIM15_NUMBER 24
+#define STM32_TIM1_UP_TIM16_NUMBER 25
+#define STM32_TIM1_TRGCO_TIM17_NUMBER 26
+#define STM32_TIM1_CC_NUMBER 27
+#define STM32_TIM2_NUMBER 28
+#define STM32_TIM3_NUMBER 29
+#define STM32_TIM4_NUMBER 30
+#define STM32_TIM5_NUMBER 50
+#define STM32_TIM6_NUMBER 54
+#define STM32_TIM7_NUMBER 55
+#define STM32_TIM8_BRK_NUMBER 43
+#define STM32_TIM8_UP_NUMBER 44
+#define STM32_TIM8_TRGCO_NUMBER 45
+#define STM32_TIM8_CC_NUMBER 46
+#define STM32_TIM20_BRK_NUMBER 77
+#define STM32_TIM20_UP_NUMBER 78
+#define STM32_TIM20_TRGCO_NUMBER 79
+#define STM32_TIM20_CC_NUMBER 80
+
+/*
+ * USART/UART units.
+ */
+#define STM32_USART1_HANDLER VectorD4
+#define STM32_USART2_HANDLER VectorD8
+#define STM32_USART3_HANDLER VectorDC
+#define STM32_UART4_HANDLER Vector110
+#define STM32_UART5_HANDLER Vector114
+#define STM32_LPUART1_HANDLER Vector1AC
+
+#define STM32_USART1_NUMBER 37
+#define STM32_USART2_NUMBER 38
+#define STM32_USART3_NUMBER 39
+#define STM32_UART4_NUMBER 52
+#define STM32_UART5_NUMBER 53
+#define STM32_LPUART1_NUMBER 91
+
+/*
+ * USB units.
+ */
+#define STM32_USB1_HP_HANDLER Vector8C
+#define STM32_USB1_LP_HANDLER Vector90
+#define STM32_USB1_HP_NUMBER 19
+#define STM32_USB1_LP_NUMBER 20
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void irqInit(void);
+ void irqDeinit(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_ISR_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_rcc.h b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_rcc.h new file mode 100644 index 0000000..9877f63 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_rcc.h @@ -0,0 +1,1366 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32G4xx/stm32_rcc.h
+ * @brief RCC helper driver header.
+ * @note This file requires definitions from the ST header file
+ * @p stm32g4xx.h.
+ *
+ * @addtogroup STM32G4xx_RCC
+ * @{
+ */
+#ifndef STM32_RCC_H
+#define STM32_RCC_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Generic RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the clock of one or more peripheral on the APB1 bus (R1).
+ *
+ * @param[in] mask APB1 R1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB1R1(mask, lp) { \
+ RCC->APB1ENR1 |= (mask); \
+ if (lp) \
+ RCC->APB1SMENR1 |= (mask); \
+ else \
+ RCC->APB1SMENR1 &= ~(mask); \
+ (void)RCC->APB1SMENR1; \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB1 bus (R1).
+ *
+ * @param[in] mask APB1 R1 peripherals mask
+ *
+ * @api
+ */
+#define rccDisableAPB1R1(mask) { \
+ RCC->APB1ENR1 &= ~(mask); \
+ RCC->APB1SMENR1 &= ~(mask); \
+ (void)RCC->APB1SMENR1; \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB1 bus (R1).
+ *
+ * @param[in] mask APB1 R1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB1R1(mask) { \
+ RCC->APB1RSTR1 |= (mask); \
+ RCC->APB1RSTR1 &= ~(mask); \
+ (void)RCC->APB1RSTR1; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the APB1 bus (R2).
+ *
+ * @param[in] mask APB1 R2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB1R2(mask, lp) { \
+ RCC->APB1ENR2 |= (mask); \
+ if (lp) \
+ RCC->APB1SMENR2 |= (mask); \
+ else \
+ RCC->APB1SMENR2 &= ~(mask); \
+ (void)RCC->APB1SMENR2; \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB1 bus (R2).
+ *
+ * @param[in] mask APB1 R2 peripherals mask
+ *
+ * @api
+ */
+#define rccDisableAPB1R2(mask) { \
+ RCC->APB1ENR2 &= ~(mask); \
+ RCC->APB1SMENR2 &= ~(mask); \
+ (void)RCC->APB1SMENR2; \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB1 bus (R2).
+ *
+ * @param[in] mask APB1 R2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB1R2(mask) { \
+ RCC->APB1RSTR2 |= (mask); \
+ RCC->APB1RSTR2 &= ~(mask); \
+ (void)RCC->APB1RSTR2; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB2(mask, lp) { \
+ RCC->APB2ENR |= (mask); \
+ if (lp) \
+ RCC->APB2SMENR |= (mask); \
+ else \
+ RCC->APB2SMENR &= ~(mask); \
+ (void)RCC->APB2SMENR; \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ *
+ * @api
+ */
+#define rccDisableAPB2(mask) { \
+ RCC->APB2ENR &= ~(mask); \
+ RCC->APB2SMENR &= ~(mask); \
+ (void)RCC->APB2SMENR; \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB2(mask) { \
+ RCC->APB2RSTR |= (mask); \
+ RCC->APB2RSTR &= ~(mask); \
+ (void)RCC->APB2RSTR; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB1 bus.
+ *
+ * @param[in] mask AHB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB1(mask, lp) { \
+ RCC->AHB1ENR |= (mask); \
+ if (lp) \
+ RCC->AHB1SMENR |= (mask); \
+ else \
+ RCC->AHB1SMENR &= ~(mask); \
+ (void)RCC->AHB1SMENR; \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB1 bus.
+ *
+ * @param[in] mask AHB1 peripherals mask
+ *
+ * @api
+ */
+#define rccDisableAHB1(mask) { \
+ RCC->AHB1ENR &= ~(mask); \
+ RCC->AHB1SMENR &= ~(mask); \
+ (void)RCC->AHB1SMENR; \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB1 bus.
+ *
+ * @param[in] mask AHB1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB1(mask) { \
+ RCC->AHB1RSTR |= (mask); \
+ RCC->AHB1RSTR &= ~(mask); \
+ (void)RCC->AHB1RSTR; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB2 bus.
+ *
+ * @param[in] mask AHB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB2(mask, lp) { \
+ RCC->AHB2ENR |= (mask); \
+ if (lp) \
+ RCC->AHB2SMENR |= (mask); \
+ else \
+ RCC->AHB2SMENR &= ~(mask); \
+ (void)RCC->AHB2SMENR; \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB2 bus.
+ *
+ * @param[in] mask AHB2 peripherals mask
+ *
+ * @api
+ */
+#define rccDisableAHB2(mask) { \
+ RCC->AHB2ENR &= ~(mask); \
+ RCC->AHB2SMENR &= ~(mask); \
+ (void)RCC->AHB2SMENR; \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB2 bus.
+ *
+ * @param[in] mask AHB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB2(mask) { \
+ RCC->AHB2RSTR |= (mask); \
+ RCC->AHB2RSTR &= ~(mask); \
+ (void)RCC->AHB2RSTR; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.
+ *
+ * @param[in] mask AHB3 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB3(mask, lp) { \
+ RCC->AHB3ENR |= (mask); \
+ if (lp) \
+ RCC->AHB3SMENR |= (mask); \
+ else \
+ RCC->AHB3SMENR &= ~(mask); \
+ (void)RCC->AHB3SMENR; \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
+ *
+ * @param[in] mask AHB3 peripherals mask
+ *
+ * @api
+ */
+#define rccDisableAHB3(mask) { \
+ RCC->AHB3ENR &= ~(mask); \
+ RCC->AHB3SMENR &= ~(mask); \
+ (void)RCC->AHB3SMENR; \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB3 (FSMC) bus.
+ *
+ * @param[in] mask AHB3 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB3(mask) { \
+ RCC->AHB3RSTR |= (mask); \
+ RCC->AHB3RSTR &= ~(mask); \
+ (void)RCC->AHB3RSTR; \
+}
+/** @} */
+
+/**
+ * @name ADC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the ADC1/ADC2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC12(lp) rccEnableAHB2(RCC_AHB2ENR_ADC12EN, lp)
+
+/**
+ * @brief Disables the ADC1/ADC2 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableADC12() rccDisableAHB2(RCC_AHB2ENR_ADC12EN)
+
+/**
+ * @brief Resets the ADC1/ADC2 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC12() rccResetAHB2(RCC_AHB2RSTR_ADC12RST)
+
+/**
+ * @brief Enables the ADC3/ADC4/ADC5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC345(lp) rccEnableAHB2(RCC_AHB2ENR_ADC345EN, lp)
+
+/**
+ * @brief Disables the ADC3/ADC4/ADC5 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableADC345() rccDisableAHB2(RCC_AHB2ENR_ADC345EN)
+
+/**
+ * @brief Resets the ADC3/ADC4/ADC5 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC345() rccResetAHB2(RCC_AHB2RSTR_ADC345RST)
+/** @} */
+
+/**
+ * @name DAC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC1(lp) rccEnableAHB2(RCC_AHB2ENR_DAC1EN, lp)
+
+/**
+ * @brief Disables the DAC1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableDAC1() rccDisableAHB2(RCC_AHB2ENR_DAC1EN)
+
+/**
+ * @brief Resets the DAC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC1() rccResetAHB2(RCC_AHB2RSTR_DAC1RST)
+
+/**
+ * @brief Enables the DAC2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC2(lp) rccEnableAHB2(RCC_AHB2ENR_DAC2EN, lp)
+
+/**
+ * @brief Disables the DAC2 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableDAC2() rccDisableAHB2(RCC_AHB2ENR_DAC2EN)
+
+/**
+ * @brief Resets the DAC2 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC2() rccResetAHB2(RCC_AHB2RSTR_DAC2RST)
+
+/**
+ * @brief Enables the DAC3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC3(lp) rccEnableAHB2(RCC_AHB2ENR_DAC3EN, lp)
+
+/**
+ * @brief Disables the DAC3 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableDAC3() rccDisableAHB2(RCC_AHB2ENR_DAC3EN)
+
+/**
+ * @brief Resets the DAC3 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC3() rccResetAHB2(RCC_AHB2RSTR_DAC3RST)
+
+/**
+ * @brief Enables the DAC4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC4(lp) rccEnableAHB2(RCC_AHB2ENR_DAC4EN, lp)
+
+/**
+ * @brief Disables the DAC4 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableDAC4() rccDisableAHB2(RCC_AHB2ENR_DAC4EN)
+
+/**
+ * @brief Resets the DAC4 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC4() rccResetAHB2(RCC_AHB2RSTR_DAC4RST)
+/** @} */
+
+/**
+ * @name DMA peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DMA1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
+
+/**
+ * @brief Disables the DMA1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
+
+/**
+ * @brief Resets the DMA1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
+
+/**
+ * @brief Enables the DMA2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
+
+/**
+ * @brief Disables the DMA2 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
+
+/**
+ * @brief Resets the DMA2 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
+/** @} */
+
+/**
+ * @name DMAMUX peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DMAMUX peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMAMUX(lp) rccEnableAHB1(RCC_AHB1ENR_DMAMUX1EN, lp)
+
+/**
+ * @brief Disables the DMAMUX peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableDMAMUX() rccDisableAHB1(RCC_AHB1ENR_DMAMUX1EN)
+
+/**
+ * @brief Resets the DMAMUX peripheral.
+ *
+ * @api
+ */
+#define rccResetDMAMUX() rccResetAHB1(RCC_AHB1RSTR_DMAMUX1RST)
+/** @} */
+
+/**
+ * @name FDCAN peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the FDCAN peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableFDCAN(lp) rccEnableAPB1R1(RCC_APB1ENR1_FDCANEN, lp)
+
+/**
+ * @brief Disables the FDCAN peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableFDCAN() rccDisableAPB1R1(RCC_APB1ENR1_FDCANEN)
+
+/**
+ * @brief Resets the FDCAN peripheral.
+ *
+ * @api
+ */
+#define rccResetFDCAN() rccResetAPB1R1(RCC_APB1RSTR1_FDCANRST)
+/** @} */
+
+/**
+ * @name PWR interface specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the PWR interface clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnablePWRInterface(lp) rccEnableAPB1R1(RCC_APB1ENR1_PWREN, lp)
+
+/**
+ * @brief Disables PWR interface clock.
+ *
+ * @api
+ */
+#define rccDisablePWRInterface() rccDisableAPB1R1(RCC_APB1ENR1_PWREN)
+
+/**
+ * @brief Resets the PWR interface.
+ *
+ * @api
+ */
+#define rccResetPWRInterface() rccResetAPB1R1(RCC_APB1RSTR1_PWRRST)
+/** @} */
+
+/**
+ * @name FDCAN peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the FDCAN1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableFDCAN1(lp) rccEnableAPB1R1(RCC_APB1ENR1_FDCANEN, lp)
+
+/**
+ * @brief Disables the FDCAN1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableFDCAN1() rccDisableAPB1R1(RCC_APB1ENR1_FDCANEN)
+
+/**
+ * @brief Resets the FDCAN1 peripheral.
+ *
+ * @api
+ */
+#define rccResetFDCAN1() rccResetAPB1R1(RCC_APB1RSTR1_FDCANRST)
+/** @} */
+
+/**
+ * @name I2C peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the I2C1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C1(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C1EN, lp)
+
+/**
+ * @brief Disables the I2C1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableI2C1() rccDisableAPB1R1(RCC_APB1ENR1_I2C1EN)
+
+/**
+ * @brief Resets the I2C1 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C1() rccResetAPB1R1(RCC_APB1RSTR1_I2C1RST)
+
+/**
+ * @brief Enables the I2C2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C2(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C2EN, lp)
+
+/**
+ * @brief Disables the I2C2 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableI2C2() rccDisableAPB1R1(RCC_APB1ENR1_I2C2EN)
+
+/**
+ * @brief Resets the I2C2 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C2() rccResetAPB1R1(RCC_APB1RSTR1_I2C2RST)
+
+/**
+ * @brief Enables the I2C3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C3(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C3EN, lp)
+
+/**
+ * @brief Disables the I2C3 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableI2C3() rccDisableAPB1R1(RCC_APB1ENR1_I2C3EN)
+
+/**
+ * @brief Resets the I2C3 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C3() rccResetAPB1R1(RCC_APB1RSTR1_I2C3RST)
+
+/**
+ * @brief Enables the I2C4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C4(lp) rccEnableAPB1R2(RCC_APB1ENR2_I2C4EN, lp)
+
+/**
+ * @brief Disables the I2C4 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableI2C4() rccDisableAPB1R1(RCC_APB1ENR2_I2C4EN)
+
+/**
+ * @brief Resets the I2C4 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C4() rccResetAPB1R1(RCC_APB1RSTR2_I2C4RST)
+/** @} */
+
+/**
+ * @name QUADSPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the QUADSPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
+
+/**
+ * @brief Disables the QUADSPI1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN)
+
+/**
+ * @brief Resets the QUADSPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
+/** @} */
+
+/**
+ * @name RNG peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the RNG peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableRNG(lp) rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp)
+
+/**
+ * @brief Disables the RNG peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableRNG() rccDisableAHB2(RCC_AHB2ENR_RNGEN)
+
+/**
+ * @brief Resets the RNG peripheral.
+ *
+ * @api
+ */
+#define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST)
+/** @} */
+
+/**
+ * @name SPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Disables the SPI1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
+
+/**
+ * @brief Resets the SPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
+
+/**
+ * @brief Enables the SPI2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI2(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI2EN, lp)
+
+/**
+ * @brief Disables the SPI2 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableSPI2() rccDisableAPB1R1(RCC_APB1ENR1_SPI2EN)
+
+/**
+ * @brief Resets the SPI2 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI2() rccResetAPB1R1(RCC_APB1RSTR1_SPI2RST)
+
+/**
+ * @brief Enables the SPI3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI3(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI3EN, lp)
+
+/**
+ * @brief Disables the SPI3 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableSPI3() rccDisableAPB1R1(RCC_APB1ENR1_SPI3EN)
+
+/**
+ * @brief Resets the SPI3 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI3() rccResetAPB1R1(RCC_APB1RSTR1_SPI3RST)
+
+/**
+ * @brief Enables the SPI4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp)
+
+/**
+ * @brief Disables the SPI4 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableSPI4() rccDisableAPB2(RCC_APB2ENR_SPI4EN)
+
+/**
+ * @brief Resets the SPI4 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST)
+/** @} */
+
+/**
+ * @name TIM peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the TIM1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief Disables the TIM1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
+
+/**
+ * @brief Resets the TIM1 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
+
+/**
+ * @brief Enables the TIM2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM2(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM2EN, lp)
+
+/**
+ * @brief Disables the TIM2 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM2() rccDisableAPB1R1(RCC_APB1ENR1_TIM2EN)
+
+/**
+ * @brief Resets the TIM2 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM2() rccResetAPB1R1(RCC_APB1RSTR1_TIM2RST)
+
+/**
+ * @brief Enables the TIM3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM3(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM3EN, lp)
+
+/**
+ * @brief Disables the TIM3 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM3() rccDisableAPB1R1(RCC_APB1ENR1_TIM3EN)
+
+/**
+ * @brief Resets the TIM3 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM3() rccResetAPB1R1(RCC_APB1RSTR1_TIM3RST)
+
+/**
+ * @brief Enables the TIM4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM4(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM4EN, lp)
+
+/**
+ * @brief Disables the TIM4 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM4() rccDisableAPB1R1(RCC_APB1ENR1_TIM4EN)
+
+/**
+ * @brief Resets the TIM4 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM4() rccResetAPB1R1(RCC_APB1RSTR1_TIM4RST)
+
+/**
+ * @brief Enables the TIM5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM5(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM5EN, lp)
+
+/**
+ * @brief Disables the TIM5 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM5() rccDisableAPB1R1(RCC_APB1ENR1_TIM5EN)
+
+/**
+ * @brief Resets the TIM5 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM5() rccResetAPB1R1(RCC_APB1RSTR1_TIM5RST)
+
+/**
+ * @brief Enables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM6(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM6EN, lp)
+
+/**
+ * @brief Disables the TIM6 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM6() rccDisableAPB1R1(RCC_APB1ENR1_TIM6EN)
+
+/**
+ * @brief Resets the TIM6 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM6() rccResetAPB1R1(RCC_APB1RSTR1_TIM6RST)
+
+/**
+ * @brief Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM7EN, lp)
+
+/**
+ * @brief Disables the TIM7 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM7() rccDisableAPB1R1(RCC_APB1ENR1_TIM7EN)
+
+/**
+ * @brief Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1R1(RCC_APB1RSTR1_TIM7RST)
+
+/**
+ * @brief Enables the TIM8 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief Disables the TIM8 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM8() rccDisableAPB2(RCC_APB2ENR_TIM8EN)
+
+/**
+ * @brief Resets the TIM8 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
+
+/**
+ * @brief Enables the TIM15 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Disables the TIM15 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM15() rccDisableAPB2(RCC_APB2ENR_TIM15EN)
+
+/**
+ * @brief Resets the TIM15 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
+
+/**
+ * @brief Enables the TIM16 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Disables the TIM16 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
+
+/**
+ * @brief Resets the TIM16 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
+
+/**
+ * @brief Enables the TIM17 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Disables the TIM17 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
+
+/**
+ * @brief Resets the TIM17 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
+
+/**
+ * @brief Enables the TIM20 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM20(lp) rccEnableAPB2(RCC_APB2ENR_TIM20EN, lp)
+
+/**
+ * @brief Disables the TIM20 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM20() rccDisableAPB2(RCC_APB2ENR_TIM20EN)
+
+/**
+ * @brief Resets the TIM20 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM20() rccResetAPB2(RCC_APB2RSTR_TIM20RST)
+/** @} */
+
+/**
+ * @name USART/UART peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Disables the USART1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
+
+/**
+ * @brief Enables the USART2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART2(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART2EN, lp)
+
+/**
+ * @brief Disables the USART2 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUSART2() rccDisableAPB1R1(RCC_APB1ENR1_USART2EN)
+
+/**
+ * @brief Resets the USART2 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART2() rccResetAPB1R1(RCC_APB1RSTR1_USART2RST)
+
+/**
+ * @brief Enables the USART3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART3(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART3EN, lp)
+
+/**
+ * @brief Disables the USART3 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUSART3() rccDisableAPB1R1(RCC_APB1ENR1_USART3EN)
+
+/**
+ * @brief Resets the USART3 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART3() rccResetAPB1R1(RCC_APB1RSTR1_USART3RST)
+
+/**
+ * @brief Enables the UART4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART4(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART4EN, lp)
+
+/**
+ * @brief Disables the UART4 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUART4() rccDisableAPB1R1(RCC_APB1ENR1_UART4EN)
+
+/**
+ * @brief Resets the UART4 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART4() rccResetAPB1R1(RCC_APB1RSTR1_UART4RST)
+
+/**
+ * @brief Enables the UART5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART5(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART5EN, lp)
+
+/**
+ * @brief Disables the UART5 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUART5() rccDisableAPB1R1(RCC_APB1ENR1_UART5EN)
+
+/**
+ * @brief Resets the UART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1R1(RCC_APB1RSTR1_UART5RST)
+
+/**
+ * @brief Enables the LPUART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableLPUART1(lp) rccEnableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp)
+
+/**
+ * @brief Disables the LPUART1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableLPUART1() rccDisableAPB1R2(RCC_APB1ENR2_LPUART1EN)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetLPUART1() rccResetAPB1R2(RCC_APB1RSTR2_LPUART1RST)
+/** @} */
+
+/**
+ * @name USB peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSB(lp) rccEnableAPB1R1(RCC_APB1ENR1_USBEN, lp)
+
+/**
+ * @brief Disables the USB peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUSB() rccDisableAPB1R1(RCC_APB1ENR1_USBEN)
+
+/**
+ * @brief Resets the USB peripheral.
+ *
+ * @api
+ */
+#define rccResetUSB() rccResetAPB1R1(RCC_APB1RSTR1_USBRST)
+/** @} */
+
+/**
+ * @name CRC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CRC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
+
+/**
+ * @brief Disables the CRC peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
+
+/**
+ * @brief Resets the CRC peripheral.
+ *
+ * @api
+ */
+#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_RCC_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_registry.h b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_registry.h new file mode 100644 index 0000000..f86ef00 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32G4xx/stm32_registry.h @@ -0,0 +1,524 @@ +/*
+ ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32G4xx/stm32_registry.h
+ * @brief STM32G4xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef STM32_REGISTRY_H
+#define STM32_REGISTRY_H
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name STM32G4xx capabilities
+ * @{
+ */
+
+/*===========================================================================*/
+/* Common. */
+/*===========================================================================*/
+
+/* RNG attributes.*/
+#define STM32_HAS_RNG1 TRUE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_STORAGE_SIZE 128
+#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
+#define STM32_RTC_WKUP_HANDLER Vector4C
+#define STM32_RTC_ALARM_HANDLER VectorE4
+#define STM32_RTC_TAMP_STAMP_NUMBER 2
+#define STM32_RTC_WKUP_NUMBER 3
+#define STM32_RTC_ALARM_NUMBER 41
+#define STM32_RTC_ALARM_EXTI 18
+#define STM32_RTC_TAMP_STAMP_EXTI 19
+#define STM32_RTC_WKUP_EXTI 20
+#define STM32_RTC_IRQ_ENABLE() do { \
+ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
+ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \
+ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
+} while (false)
+
+ /* Enabling RTC-related EXTI lines.*/
+#define STM32_RTC_ENABLE_ALL_EXTI() do { \
+ extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
+ EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
+ EXTI_MASK1(STM32_RTC_WKUP_EXTI), \
+ EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \
+} while (false)
+
+/* Clearing EXTI interrupts. */
+#define STM32_RTC_CLEAR_ALL_EXTI() do { \
+ extiClearGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
+ EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
+ EXTI_MASK1(STM32_RTC_WKUP_EXTI)); \
+} while (false)
+
+/* Masks used to preserve state of RTC and TAMP register reserved bits. */
+#define STM32_RTC_CR_MASK 0xE7FFFF7F
+#define STM32_RTC_PRER_MASK 0x007F7FFF
+#define STM32_TAMP_CR1_MASK 0x003C0007
+#define STM32_TAMP_CR2_MASK 0x07070007
+#define STM32_TAMP_FLTCR_MASK 0x000000FF
+#define STM32_TAMP_IER_MASK 0x003C0007
+
+#if defined(STM32G441xx) || defined(STM32G483xx) || defined(STM32G484xx) || \
+ defined(__DOXYGEN__)
+#define STM32_HAS_HASH1 TRUE
+#define STM32_HAS_CRYP1 TRUE
+#else
+#define STM32_HAS_HASH1 FALSE
+#define STM32_HAS_CRYP1 FALSE
+#endif
+
+/*===========================================================================*/
+/* STM32G473xx, STM32G4843xx, STM32G474xx, STM32G484xx. */
+/*===========================================================================*/
+
+#if defined(STM32G473xx) || defined(STM32G483xx) || \
+ defined(STM32G474xx) || defined(STM32G484xx) || \
+ defined(__DOXYGEN__)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 TRUE
+#define STM32_HAS_ADC4 TRUE
+#define STM32_HAS_ADC5 TRUE
+
+/* CAN attributes.*/
+#define STM32_HAS_FDCAN1 TRUE
+#define STM32_HAS_FDCAN2 TRUE
+#define STM32_HAS_FDCAN3 TRUE
+#define STM32_FDCAN_FLS_NBR 28U
+#define STM32_FDCAN_FLE_NBR 8U
+#define STM32_FDCAN_RF0_NBR 3U
+#define STM32_FDCAN_RF1_NBR 3U
+#define STM32_FDCAN_RB_NBR 0U
+#define STM32_FDCAN_TEF_NBR 3U
+#define STM32_FDCAN_TB_NBR 3U
+#define STM32_FDCAN_TM_NBR 0U
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_HAS_DAC2_CH1 TRUE
+#define STM32_HAS_DAC2_CH2 FALSE
+#define STM32_HAS_DAC3_CH1 TRUE
+#define STM32_HAS_DAC3_CH2 TRUE
+#define STM32_HAS_DAC4_CH1 TRUE
+#define STM32_HAS_DAC4_CH2 TRUE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_DMAMUX TRUE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+#define STM32_DMA1_NUM_CHANNELS 8
+#define STM32_DMA2_NUM_CHANNELS 8
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_HAS_CR FALSE
+#define STM32_EXTI_SEPARATE_RF FALSE
+#define STM32_EXTI_NUM_LINES 44
+#define STM32_EXTI_IMR1_MASK 0x1F840000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
+
+
+/* Flash attributes.*/
+#define STM32_FLASH_NUMBER_OF_BANKS 2
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
+ RCC_AHB2ENR_GPIOBEN | \
+ RCC_AHB2ENR_GPIOCEN | \
+ RCC_AHB2ENR_GPIODEN | \
+ RCC_AHB2ENR_GPIOEEN | \
+ RCC_AHB2ENR_GPIOFEN | \
+ RCC_AHB2ENR_GPIOGEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_HAS_I2C2 TRUE
+#define STM32_HAS_I2C3 TRUE
+#define STM32_HAS_I2C4 TRUE
+
+/* OCTOSPI attributes.*/
+#define STM32_HAS_OCTOSPI1 FALSE
+#define STM32_HAS_OCTOSPI2 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+
+/* SDMMC attributes.*/
+#define STM32_HAS_SDMMC1 FALSE
+#define STM32_HAS_SDMMC2 FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM20 TRUE
+#define STM32_TIM20_IS_32BITS FALSE
+#define STM32_TIM20_CHANNELS 6
+
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_HAS_USART2 TRUE
+#define STM32_HAS_USART3 TRUE
+#define STM32_HAS_UART4 TRUE
+#define STM32_HAS_UART5 TRUE
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* OTG/USB attributes.*/
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 1024
+#define STM32_USB_HAS_BCDR TRUE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+/* DCMI attributes.*/
+#define STM32_HAS_DCMI FALSE
+
+#endif /* defined(STM32G474xx) || defined(STM32G484xx) */
+
+/*===========================================================================*/
+/* STM32G431xx, STM32G441xx, STM32G471xx. */
+/*===========================================================================*/
+
+#if defined(STM32G431xx) || defined(STM32G441xx) || \
+ defined(__DOXYGEN__)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+#define STM32_HAS_ADC5 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_FDCAN1 TRUE
+#define STM32_HAS_FDCAN2 FALSE
+#define STM32_HAS_FDCAN3 FALSE
+#define STM32_FDCAN_FLS_NBR 28U
+#define STM32_FDCAN_FLE_NBR 8U
+#define STM32_FDCAN_RF0_NBR 3U
+#define STM32_FDCAN_RF1_NBR 3U
+#define STM32_FDCAN_RB_NBR 0U
+#define STM32_FDCAN_TEF_NBR 3U
+#define STM32_FDCAN_TB_NBR 3U
+#define STM32_FDCAN_TM_NBR 0U
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+#define STM32_HAS_DAC3_CH1 TRUE
+#define STM32_HAS_DAC3_CH2 TRUE
+#define STM32_HAS_DAC4_CH1 FALSE
+#define STM32_HAS_DAC4_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_DMAMUX TRUE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+#define STM32_DMA1_NUM_CHANNELS 6
+#define STM32_DMA2_NUM_CHANNELS 6
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_HAS_CR FALSE
+#define STM32_EXTI_SEPARATE_RF FALSE
+#define STM32_EXTI_NUM_LINES 44
+#define STM32_EXTI_IMR1_MASK 0x1F840000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
+
+
+/* Flash attributes.*/
+#define STM32_FLASH_NUMBER_OF_BANKS 2
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
+ RCC_AHB2ENR_GPIOBEN | \
+ RCC_AHB2ENR_GPIOCEN | \
+ RCC_AHB2ENR_GPIODEN | \
+ RCC_AHB2ENR_GPIOEEN | \
+ RCC_AHB2ENR_GPIOFEN | \
+ RCC_AHB2ENR_GPIOGEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_HAS_I2C2 TRUE
+#define STM32_HAS_I2C3 TRUE
+#define STM32_HAS_I2C4 FALSE
+
+/* OCTOSPI attributes.*/
+#define STM32_HAS_OCTOSPI1 FALSE
+#define STM32_HAS_OCTOSPI2 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
+/* SDMMC attributes.*/
+#define STM32_HAS_SDMMC1 FALSE
+#define STM32_HAS_SDMMC2 FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_HAS_USART2 TRUE
+#define STM32_HAS_USART3 TRUE
+#define STM32_HAS_UART4 TRUE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* OTG/USB attributes.*/
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 1024
+#define STM32_USB_HAS_BCDR TRUE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+/* DCMI attributes.*/
+#define STM32_HAS_DCMI FALSE
+
+#endif /* defined(STM32G431xx) || defined(STM32G441xx) */
+
+/** @} */
+
+#endif /* STM32_REGISTRY_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/hal_efl_lld.c b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/hal_efl_lld.c new file mode 100644 index 0000000..6ea46f8 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/hal_efl_lld.c @@ -0,0 +1,542 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_efl_lld.c
+ * @brief STM32L4xx Embedded Flash subsystem low level driver source.
+ *
+ * @addtogroup HAL_EFL
+ * @{
+ */
+
+#include <string.h>
+
+#include "hal.h"
+
+#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define STM32_FLASH_SECTOR_SIZE 2048U
+#define STM32_FLASH_LINE_SIZE 8U
+#define STM32_FLASH_LINE_MASK (STM32_FLASH_LINE_SIZE - 1U)
+
+#define FLASH_PDKEY1 0x04152637U
+#define FLASH_PDKEY2 0xFAFBFCFDU
+
+#define FLASH_KEY1 0x45670123U
+#define FLASH_KEY2 0xCDEF89ABU
+
+#define FLASH_OPTKEY1 0x08192A3BU
+#define FLASH_OPTKEY2 0x4C5D6E7FU
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief EFL1 driver identifier.
+ */
+EFlashDriver EFLD1;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+static const flash_descriptor_t efl_lld_descriptor = {
+ .attributes = FLASH_ATTR_ERASED_IS_ONE |
+ FLASH_ATTR_MEMORY_MAPPED |
+ FLASH_ATTR_ECC_CAPABLE |
+ FLASH_ATTR_ECC_ZERO_LINE_CAPABLE,
+ .page_size = STM32_FLASH_LINE_SIZE,
+ .sectors_count = STM32_FLASH_NUMBER_OF_BANKS *
+ STM32_FLASH_SECTORS_PER_BANK,
+ .sectors = NULL,
+ .sectors_size = STM32_FLASH_SECTOR_SIZE,
+ .address = (uint8_t *)0x08000000U,
+ .size = STM32_FLASH_NUMBER_OF_BANKS *
+ STM32_FLASH_SECTORS_PER_BANK *
+ STM32_FLASH_SECTOR_SIZE
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static inline void stm32_flash_lock(EFlashDriver *eflp) {
+
+ eflp->flash->CR |= FLASH_CR_LOCK;
+}
+
+static inline void stm32_flash_unlock(EFlashDriver *eflp) {
+
+ eflp->flash->KEYR |= FLASH_KEY1;
+ eflp->flash->KEYR |= FLASH_KEY2;
+}
+
+static inline void stm32_flash_enable_pgm(EFlashDriver *eflp) {
+
+ eflp->flash->CR |= FLASH_CR_PG;
+}
+
+static inline void stm32_flash_disable_pgm(EFlashDriver *eflp) {
+
+ eflp->flash->CR &= ~FLASH_CR_PG;
+}
+
+static inline void stm32_flash_clear_status(EFlashDriver *eflp) {
+
+ eflp->flash->SR = 0x0000FFFFU;
+}
+
+static inline void stm32_flash_wait_busy(EFlashDriver *eflp) {
+
+ /* Wait for busy bit clear.*/
+ while ((eflp->flash->SR & FLASH_SR_BSY) != 0U) {
+ }
+}
+
+static inline flash_error_t stm32_flash_check_errors(EFlashDriver *eflp) {
+ uint32_t sr = eflp->flash->SR;
+
+ /* Clearing error conditions.*/
+ eflp->flash->SR = sr & 0x0000FFFFU;
+
+ /* Some errors are only caught by assertion.*/
+ osalDbgAssert((sr & (FLASH_SR_FASTERR |
+ FLASH_SR_MISERR |
+ FLASH_SR_SIZERR)) == 0U, "unexpected flash error");
+
+ /* Decoding relevant errors.*/
+ if ((sr & FLASH_SR_WRPERR) != 0U) {
+ return FLASH_ERROR_HW_FAILURE;
+ }
+
+ if ((sr & (FLASH_SR_PGAERR | FLASH_SR_PROGERR | FLASH_SR_OPERR)) != 0U) {
+ return eflp->state == FLASH_PGM ? FLASH_ERROR_PROGRAM : FLASH_ERROR_ERASE;
+ }
+
+ return FLASH_NO_ERROR;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level Embedded Flash driver initialization.
+ *
+ * @notapi
+ */
+void efl_lld_init(void) {
+
+ /* Driver initialization.*/
+ eflObjectInit(&EFLD1);
+ EFLD1.flash = FLASH;
+}
+
+/**
+ * @brief Configures and activates the Embedded Flash peripheral.
+ *
+ * @param[in] eflp pointer to a @p EFlashDriver structure
+ *
+ * @notapi
+ */
+void efl_lld_start(EFlashDriver *eflp) {
+
+ stm32_flash_unlock(eflp);
+ FLASH->CR = 0x00000000U;
+}
+
+/**
+ * @brief Deactivates the Embedded Flash peripheral.
+ *
+ * @param[in] eflp pointer to a @p EFlashDriver structure
+ *
+ * @notapi
+ */
+void efl_lld_stop(EFlashDriver *eflp) {
+
+ stm32_flash_lock(eflp);
+}
+
+/**
+ * @brief Gets the flash descriptor structure.
+ *
+ * @param[in] ip pointer to a @p EFlashDriver instance
+ * @return A flash device descriptor.
+ *
+ * @notapi
+ */
+const flash_descriptor_t *efl_lld_get_descriptor(void *instance) {
+
+ (void)instance;
+
+ return &efl_lld_descriptor;
+}
+
+/**
+ * @brief Read operation.
+ *
+ * @param[in] ip pointer to a @p EFlashDriver instance
+ * @param[in] offset flash offset
+ * @param[in] n number of bytes to be read
+ * @param[out] rp pointer to the data buffer
+ * @return An error code.
+ * @retval FLASH_NO_ERROR if there is no erase operation in progress.
+ * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
+ * @retval FLASH_ERROR_READ if the read operation failed.
+ * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
+ *
+ * @notapi
+ */
+flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
+ size_t n, uint8_t *rp) {
+ EFlashDriver *devp = (EFlashDriver *)instance;
+ flash_error_t err = FLASH_NO_ERROR;
+
+ osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U));
+ osalDbgCheck((size_t)offset + n <= (size_t)efl_lld_descriptor.size);
+ osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
+ "invalid state");
+
+ /* No reading while erasing.*/
+ if (devp->state == FLASH_ERASE) {
+ return FLASH_BUSY_ERASING;
+ }
+
+ /* FLASH_READY state while the operation is performed.*/
+ devp->state = FLASH_READ;
+
+ /* Clearing error status bits.*/
+ stm32_flash_clear_status(devp);
+
+ /* Actual read implementation.*/
+ memcpy((void *)rp, (const void *)efl_lld_descriptor.address + offset, n);
+
+ /* Checking for errors after reading.*/
+ if ((devp->flash->SR & FLASH_SR_RDERR) != 0U) {
+ err = FLASH_ERROR_READ;
+ }
+
+ /* Ready state again.*/
+ devp->state = FLASH_READY;
+
+ return err;
+
+}
+
+/**
+ * @brief Program operation.
+ * @note The device supports ECC, it is only possible to write erased
+ * pages once except when writing all zeroes.
+ *
+ * @param[in] ip pointer to a @p EFlashDriver instance
+ * @param[in] offset flash offset
+ * @param[in] n number of bytes to be programmed
+ * @param[in] pp pointer to the data buffer
+ * @return An error code.
+ * @retval FLASH_NO_ERROR if there is no erase operation in progress.
+ * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
+ * @retval FLASH_ERROR_PROGRAM if the program operation failed.
+ * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
+ *
+ * @notapi
+ */
+flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
+ size_t n, const uint8_t *pp) {
+ EFlashDriver *devp = (EFlashDriver *)instance;
+ flash_error_t err = FLASH_NO_ERROR;
+
+ osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U));
+ osalDbgCheck((size_t)offset + n <= (size_t)efl_lld_descriptor.size);
+
+ osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
+ "invalid state");
+
+ /* No programming while erasing.*/
+ if (devp->state == FLASH_ERASE) {
+ return FLASH_BUSY_ERASING;
+ }
+
+ /* FLASH_PGM state while the operation is performed.*/
+ devp->state = FLASH_PGM;
+
+ /* Clearing error status bits.*/
+ stm32_flash_clear_status(devp);
+
+ /* Enabling PGM mode in the controller.*/
+ stm32_flash_enable_pgm(devp);
+
+ /* Actual program implementation.*/
+ while (n > 0U) {
+ volatile uint32_t *address;
+
+ union {
+ uint32_t w[STM32_FLASH_LINE_SIZE / sizeof (uint32_t)];
+ uint8_t b[STM32_FLASH_LINE_SIZE / sizeof (uint8_t)];
+ } line;
+
+ /* Unwritten bytes are initialized to all ones.*/
+ line.w[0] = 0xFFFFFFFFU;
+ line.w[1] = 0xFFFFFFFFU;
+
+ /* Programming address aligned to flash lines.*/
+ address = (volatile uint32_t *)(efl_lld_descriptor.address +
+ (offset & ~STM32_FLASH_LINE_MASK));
+
+ /* Copying data inside the prepared line.*/
+ do {
+ line.b[offset & STM32_FLASH_LINE_MASK] = *pp;
+ offset++;
+ n--;
+ pp++;
+ }
+ while ((n > 0U) & ((offset & STM32_FLASH_LINE_MASK) != 0U));
+
+ /* Programming line.*/
+ address[0] = line.w[0];
+ address[1] = line.w[1];
+ stm32_flash_wait_busy(devp);
+ err = stm32_flash_check_errors(devp);
+ if (err != FLASH_NO_ERROR) {
+ break;
+ }
+ }
+
+ /* Disabling PGM mode in the controller.*/
+ stm32_flash_disable_pgm(devp);
+
+ /* Ready state again.*/
+ devp->state = FLASH_READY;
+
+ return err;
+}
+
+/**
+ * @brief Starts a whole-device erase operation.
+ * @note This function only erases bank 2 if it is present. Bank 1 is not
+ * touched because it is where the program is running on.
+ * Pages on bank 1 can be individually erased.
+ *
+ * @param[in] ip pointer to a @p EFlashDriver instance
+ * @return An error code.
+ * @retval FLASH_NO_ERROR if there is no erase operation in progress.
+ * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
+ * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
+ *
+ * @notapi
+ */
+flash_error_t efl_lld_start_erase_all(void *instance) {
+ EFlashDriver *devp = (EFlashDriver *)instance;
+
+ osalDbgCheck(instance != NULL);
+ osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
+ "invalid state");
+
+ /* No erasing while erasing.*/
+ if (devp->state == FLASH_ERASE) {
+ return FLASH_BUSY_ERASING;
+ }
+
+ /* FLASH_PGM state while the operation is performed.*/
+ devp->state = FLASH_ERASE;
+
+ /* Clearing error status bits.*/
+ stm32_flash_clear_status(devp);
+
+#if defined(FLASH_CR_MER2)
+ devp->flash->CR |= FLASH_CR_MER2;
+ devp->flash->CR |= FLASH_CR_STRT;
+#endif
+
+ return FLASH_NO_ERROR;
+}
+
+/**
+ * @brief Starts an sector erase operation.
+ *
+ * @param[in] ip pointer to a @p EFlashDriver instance
+ * @param[in] sector sector to be erased
+ * @return An error code.
+ * @retval FLASH_NO_ERROR if there is no erase operation in progress.
+ * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
+ * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
+ *
+ * @notapi
+ */
+flash_error_t efl_lld_start_erase_sector(void *instance,
+ flash_sector_t sector) {
+ EFlashDriver *devp = (EFlashDriver *)instance;
+
+ osalDbgCheck(instance != NULL);
+ osalDbgCheck(sector < efl_lld_descriptor.sectors_count);
+ osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
+ "invalid state");
+
+ /* No erasing while erasing.*/
+ if (devp->state == FLASH_ERASE) {
+ return FLASH_BUSY_ERASING;
+ }
+
+ /* FLASH_PGM state while the operation is performed.*/
+ devp->state = FLASH_ERASE;
+
+ /* Clearing error status bits.*/
+ stm32_flash_clear_status(devp);
+
+ /* Enable page erase.*/
+ devp->flash->CR |= FLASH_CR_PER;
+
+#if defined(FLASH_CR_BKER)
+ /* Bank selection.*/
+ if (sector < STM32_FLASH_SECTORS_PER_BANK) {
+ /* First bank.*/
+ devp->flash->CR &= ~FLASH_CR_BKER;
+ }
+ else {
+ /* Second bank.*/
+ devp->flash->CR |= FLASH_CR_BKER;
+ }
+#endif
+
+ /* Mask off the page selection bits.*/
+ devp->flash->CR &= ~FLASH_CR_PNB;
+
+ /* Set the page selection bits.*/
+ devp->flash->CR |= sector << FLASH_CR_PNB_Pos;
+
+ /* Start the erase.*/
+ devp->flash->CR |= FLASH_CR_STRT;
+
+ return FLASH_NO_ERROR;
+}
+
+/**
+ * @brief Queries the driver for erase operation progress.
+ *
+ * @param[in] ip pointer to a @p EFlashDriver instance
+ * @param[out] msec recommended time, in milliseconds, that
+ * should be spent before calling this
+ * function again, can be @p NULL
+ * @return An error code.
+ * @retval FLASH_NO_ERROR if there is no erase operation in progress.
+ * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
+ * @retval FLASH_ERROR_ERASE if the erase operation failed.
+ * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
+ *
+ * @api
+ */
+flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) {
+ EFlashDriver *devp = (EFlashDriver *)instance;
+ flash_error_t err;
+
+ /* If there is an erase in progress then the device must be checked.*/
+ if (devp->state == FLASH_ERASE) {
+
+ /* Checking for operation in progress.*/
+ if ((devp->flash->SR & FLASH_SR_BSY) == 0U) {
+
+ /* Disabling the various erase control bits.*/
+ devp->flash->CR &= ~(FLASH_CR_MER1 |
+#if defined(FLASH_CR_MER2)
+ FLASH_CR_MER2 |
+#endif
+ FLASH_CR_PER);
+
+ /* No operation in progress, checking for errors.*/
+ err = stm32_flash_check_errors(devp);
+
+ /* Back to ready state.*/
+ devp->state = FLASH_READY;
+ }
+ else {
+ /* Recommended time before polling again, this is a simplified
+ implementation.*/
+ if (msec != NULL) {
+ *msec = (uint32_t)STM32_FLASH_WAIT_TIME_MS;
+ }
+
+ err = FLASH_BUSY_ERASING;
+ }
+ }
+ else {
+ err = FLASH_NO_ERROR;
+ }
+
+ return err;
+}
+
+/**
+ * @brief Returns the erase state of a sector.
+ *
+ * @param[in] ip pointer to a @p EFlashDriver instance
+ * @param[in] sector sector to be verified
+ * @return An error code.
+ * @retval FLASH_NO_ERROR if the sector is erased.
+ * @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
+ * @retval FLASH_ERROR_VERIFY if the verify operation failed.
+ * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
+ *
+ * @notapi
+ */
+flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) {
+ EFlashDriver *devp = (EFlashDriver *)instance;
+ uint32_t *address;
+ flash_error_t err = FLASH_NO_ERROR;
+ unsigned i;
+
+ osalDbgCheck(instance != NULL);
+ osalDbgCheck(sector < efl_lld_descriptor.sectors_count);
+ osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
+ "invalid state");
+
+ /* No verifying while erasing.*/
+ if (devp->state == FLASH_ERASE) {
+ return FLASH_BUSY_ERASING;
+ }
+
+ /* Address of the sector.*/
+ address = (uint32_t *)(efl_lld_descriptor.address +
+ flashGetSectorOffset(getBaseFlash(devp), sector));
+
+ /* FLASH_READY state while the operation is performed.*/
+ devp->state = FLASH_READ;
+
+ /* Scanning the sector space.*/
+ for (i = 0U; i < STM32_FLASH_SECTOR_SIZE / sizeof(uint32_t); i++) {
+ if (*address != 0xFFFFFFFFU) {
+ err = FLASH_ERROR_VERIFY;
+ break;
+ }
+ address++;
+ }
+
+ /* Ready state again.*/
+ devp->state = FLASH_READY;
+
+ return err;
+}
+
+#endif /* HAL_USE_EFL == TRUE */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/hal_efl_lld.h b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/hal_efl_lld.h new file mode 100644 index 0000000..774e8ae --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/hal_efl_lld.h @@ -0,0 +1,116 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_efl_lld.h
+ * @brief STM32L4xx Embedded Flash subsystem low level driver header.
+ *
+ * @addtogroup HAL_EFL
+ * @{
+ */
+
+#ifndef HAL_EFL_LLD_H
+#define HAL_EFL_LLD_H
+
+#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name STM32L4xx configuration options
+ * @{
+ */
+/**
+ * @brief Suggested wait time during erase operations polling.
+ */
+#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__)
+#define STM32_FLASH_WAIT_TIME_MS 5
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !defined(STM32_FLASH_NUMBER_OF_BANKS)
+#error "STM32_FLASH_NUMBER_OF_BANKS not defined in registry"
+#endif
+
+#if !defined(STM32_FLASH_SECTORS_PER_BANK)
+#error "STM32_FLASH_SECTORS_PER_BANK not defined in registry"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level fields of the embedded flash driver structure.
+ */
+#define efl_lld_driver_fields \
+ /* Flash registers.*/ \
+ FLASH_TypeDef *flash
+
+/**
+ * @brief Low level fields of the embedded flash configuration structure.
+ */
+#define efl_lld_config_fields \
+ /* Dummy configuration, it is not needed.*/ \
+ uint32_t dummy
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern EFlashDriver EFLD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void efl_lld_init(void);
+ void efl_lld_start(EFlashDriver *eflp);
+ void efl_lld_stop(EFlashDriver *eflp);
+ const flash_descriptor_t *efl_lld_get_descriptor(void *instance);
+ flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
+ size_t n, uint8_t *rp);
+ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
+ size_t n, const uint8_t *pp);
+ flash_error_t efl_lld_start_erase_all(void *instance);
+ flash_error_t efl_lld_start_erase_sector(void *instance,
+ flash_sector_t sector);
+ flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec);
+ flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EFL == TRUE */
+
+#endif /* HAL_EFL_LLD_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/hal_lld.c new file mode 100644 index 0000000..23e9d84 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/hal_lld.c @@ -0,0 +1,392 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx/hal_lld.c
+ * @brief STM32L4xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief CMSIS system core clock variable.
+ * @note It is declared in system_stm32f7xx.h.
+ */
+uint32_t SystemCoreClock = STM32_HCLK;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the backup domain.
+ * @note WARNING! Changing RTC clock source impossible without resetting
+ * of the whole BKP domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+ /* Reset BKP domain if different clock source selected.*/
+ if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
+ /* Backup domain reset.*/
+ RCC->BDCR = RCC_BDCR_BDRST;
+ RCC->BDCR = 0;
+ }
+
+#if STM32_LSE_ENABLED
+ /* LSE activation.*/
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Wait until LSE is stable. */
+#endif
+
+#if STM32_MSIPLL_ENABLED
+ /* MSI PLL activation depends on LSE. Reactivating and checking for
+ MSI stability.*/
+ RCC->CR |= RCC_CR_MSIPLLEN;
+ while ((RCC->CR & RCC_CR_MSIRDY) == 0)
+ ; /* Wait until MSI is stable. */
+#endif
+
+#if HAL_USE_RTC
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
+ /* Selects clock source.*/
+ RCC->BDCR |= STM32_RTCSEL;
+
+ /* RTC clock enabled.*/
+ RCC->BDCR |= RCC_BDCR_RTCEN;
+ }
+#endif /* HAL_USE_RTC */
+
+ /* Low speed output mode.*/
+ RCC->BDCR |= STM32_LSCOSEL;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+ /* Reset of all peripherals.
+ Note, GPIOs are not reset because initialized before this point in
+ board files.*/
+ rccResetAHB1(~0);
+ rccResetAHB2(~STM32_GPIO_EN_MASK);
+ rccResetAHB3(~0);
+ rccResetAPB1R1(~RCC_APB1RSTR1_PWRRST);
+ rccResetAPB1R2(~0);
+ rccResetAPB2(~0);
+
+ /* PWR clock enabled.*/
+ rccEnablePWRInterface(true);
+
+ /* Initializes the backup domain.*/
+ hal_lld_backup_domain_init();
+
+ /* DMA subsystems initialization.*/
+#if defined(STM32_DMA_REQUIRED)
+ dmaInit();
+#endif
+
+ /* IRQ subsystem initialization.*/
+ irqInit();
+
+ /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+ PWR->CR2 = PWR_CR2_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#else
+ PWR->CR2 = 0;
+#endif /* STM32_PVD_ENABLE */
+
+ /* Enabling independent VDDUSB.*/
+#if HAL_USE_USB
+ PWR->CR2 |= PWR_CR2_USV;
+#endif /* HAL_USE_USB */
+
+ /* Enabling independent VDDIO2 required by GPIOG.*/
+#if STM32_HAS_GPIOG
+ PWR->CR2 |= PWR_CR2_IOSV;
+#endif /* STM32_HAS_GPIOG */
+}
+
+/**
+ * @brief STM32L4xx clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+ /* PWR clock enable.*/
+#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR1_RTCAPBEN)
+ RCC->APB1ENR1 = RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN;
+#else
+ RCC->APB1ENR1 = RCC_APB1ENR1_PWREN;
+#endif
+
+ /* Initial clocks setup and wait for MSI stabilization, the MSI clock is
+ always enabled because it is the fall back clock when PLL the fails.
+ Trim fields are not altered from reset values.*/
+
+ /* MSIRANGE can be set only when MSI is OFF or READY.*/
+ RCC->CR = RCC_CR_MSION;
+ while ((RCC->CR & RCC_CR_MSIRDY) == 0)
+ ; /* Wait until MSI is stable. */
+
+ /* Clocking from MSI, in case MSI was not the default source.*/
+ RCC->CFGR = 0;
+ while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)
+ ; /* Wait until MSI is selected. */
+
+ /* Core voltage setup.*/
+ PWR->CR1 = STM32_VOS;
+ while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
+ ; /* stable. */
+
+#if STM32_HSI16_ENABLED
+ /* HSI activation.*/
+ RCC->CR |= RCC_CR_HSION;
+ while ((RCC->CR & RCC_CR_HSIRDY) == 0)
+ ; /* Wait until HSI16 is stable. */
+#endif
+
+#if STM32_CLOCK_HAS_HSI48
+#if STM32_HSI48_ENABLED
+ /* HSI activation.*/
+ RCC->CRRCR |= RCC_CRRCR_HSI48ON;
+ while ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == 0)
+ ; /* Wait until HSI48 is stable. */
+#endif
+#endif
+
+#if STM32_HSE_ENABLED
+#if defined(STM32_HSE_BYPASS)
+ /* HSE Bypass.*/
+ RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#endif
+ /* HSE activation.*/
+ RCC->CR |= RCC_CR_HSEON;
+ while ((RCC->CR & RCC_CR_HSERDY) == 0)
+ ; /* Wait until HSE is stable. */
+#endif
+
+#if STM32_LSI_ENABLED
+ /* LSI activation.*/
+ RCC->CSR |= RCC_CSR_LSION;
+ while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+ ; /* Wait until LSI is stable. */
+#endif
+
+ /* Backup domain access enabled and left open.*/
+ PWR->CR1 |= PWR_CR1_DBP;
+
+#if STM32_LSE_ENABLED
+ /* LSE activation.*/
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Wait until LSE is stable. */
+#endif
+
+ /* Flash setup for selected MSI speed setting.*/
+ FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
+ STM32_MSI_FLASHBITS;
+
+ /* Changing MSIRANGE to configured value.*/
+ RCC->CR |= STM32_MSIRANGE;
+
+ /* Switching from MSISRANGE to MSIRANGE.*/
+ RCC->CR |= RCC_CR_MSIRGSEL;
+ while ((RCC->CR & RCC_CR_MSIRDY) == 0)
+ ;
+
+ /* MSI is configured SYSCLK source so wait for it to be stable as well.*/
+ while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)
+ ;
+
+#if STM32_MSIPLL_ENABLED
+ /* MSI PLL (to LSE) activation */
+ RCC->CR |= RCC_CR_MSIPLLEN;
+#endif
+
+ /* Updating MSISRANGE value. MSISRANGE can be set only when MSIRGSEL is high.
+ This range is used exiting the Standby mode until MSIRGSEL is set.*/
+ RCC->CSR |= STM32_MSISRANGE;
+
+#if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1 || STM32_ACTIVATE_PLLSAI2
+ /* PLLM and PLLSRC are common to all PLLs.*/
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+ RCC->PLLCFGR = STM32_PLLPDIV | STM32_PLLR |
+ STM32_PLLREN | STM32_PLLQ |
+ STM32_PLLQEN | STM32_PLLP |
+ STM32_PLLPEN | STM32_PLLN |
+ STM32_PLLM | STM32_PLLSRC;
+#else
+ RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
+ STM32_PLLQ | STM32_PLLQEN |
+ STM32_PLLP | STM32_PLLPEN |
+ STM32_PLLN | STM32_PLLM |
+ STM32_PLLSRC;
+#endif
+#endif
+
+#if STM32_ACTIVATE_PLL
+ /* PLL activation.*/
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Waiting for PLL lock.*/
+ while ((RCC->CR & RCC_CR_PLLRDY) == 0)
+ ;
+#endif
+
+#if STM32_ACTIVATE_PLLSAI1
+ /* PLLSAI1 activation.*/
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+ RCC->PLLSAI1CFGR = STM32_PLLSAI1PDIV | STM32_PLLSAI1R |
+ STM32_PLLSAI1REN | STM32_PLLSAI1Q |
+ STM32_PLLSAI1QEN | STM32_PLLSAI1P |
+ STM32_PLLSAI1PEN | STM32_PLLSAI1N;
+#else
+ RCC->PLLSAI1CFGR = STM32_PLLSAI1R | STM32_PLLSAI1REN |
+ STM32_PLLSAI1Q | STM32_PLLSAI1QEN |
+ STM32_PLLSAI1P | STM32_PLLSAI1PEN |
+ STM32_PLLSAI1N;
+#endif
+ RCC->CR |= RCC_CR_PLLSAI1ON;
+
+ /* Waiting for PLL lock.*/
+ while ((RCC->CR & RCC_CR_PLLSAI1RDY) == 0)
+ ;
+#endif
+
+#if STM32_ACTIVATE_PLLSAI2
+ /* PLLSAI2 activation.*/
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+ RCC->PLLSAI2CFGR = STM32_PLLSAI2PDIV | STM32_PLLSAI2R |
+ STM32_PLLSAI2REN | STM32_PLLSAI2P |
+ STM32_PLLSAI2PEN | STM32_PLLSAI2N;
+#else
+ RCC->PLLSAI2CFGR = STM32_PLLSAI2R | STM32_PLLSAI2REN |
+ STM32_PLLSAI2P | STM32_PLLSAI2PEN |
+ STM32_PLLSAI2N;
+#endif
+ RCC->CR |= RCC_CR_PLLSAI2ON;
+
+ /* Waiting for PLL lock.*/
+ while ((RCC->CR & RCC_CR_PLLSAI2RDY) == 0)
+ ;
+#endif
+
+ /* Other clock-related settings (dividers, MCO etc).*/
+ RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
+ STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+
+ /* CCIPR register initialization, note, must take care of the _OFF
+ pseudo settings.*/
+ {
+ uint32_t ccipr = STM32_DFSDMSEL | STM32_SWPMI1SEL | STM32_ADCSEL |
+ STM32_CLK48SEL | STM32_LPTIM2SEL | STM32_LPTIM1SEL |
+ STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
+ STM32_UART5SEL | STM32_UART4SEL | STM32_USART3SEL |
+ STM32_USART2SEL | STM32_USART1SEL | STM32_LPUART1SEL;
+#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
+ ccipr |= STM32_SAI2SEL;
+#endif
+#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
+ ccipr |= STM32_SAI1SEL;
+#endif
+ RCC->CCIPR = ccipr;
+ }
+
+#if STM32_HAS_I2C4
+ /* CCIPR2 register initialization.*/
+ {
+ uint32_t ccipr2 = STM32_I2C4SEL;
+ RCC->CCIPR2 = ccipr2;
+ }
+#endif
+
+ /* Set flash WS's for SYSCLK source */
+ if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) {
+ FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
+ while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
+ (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
+ }
+ }
+
+ /* Switching to the configured SYSCLK source if it is different from MSI.*/
+#if (STM32_SW != STM32_SW_MSI)
+ RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
+ /* Wait until SYSCLK is stable.*/
+ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+ ;
+#endif
+
+ /* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */
+ if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) {
+ FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
+ while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
+ (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
+ }
+ }
+
+#endif /* STM32_NO_INIT */
+
+ /* SYSCFG clock enabled here because it is a multi-functional unit shared
+ among multiple drivers.*/
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
+}
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/hal_lld.h new file mode 100644 index 0000000..91a0f57 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/hal_lld.h @@ -0,0 +1,2349 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx/hal_lld.h
+ * @brief STM32L4xx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - STM32_LSECLK.
+ * - STM32_LSEDRV.
+ * - STM32_LSE_BYPASS (optionally).
+ * - STM32_HSECLK.
+ * - STM32_HSE_BYPASS (optionally).
+ * .
+ * One of the following macros must also be defined:
+ * - STM32L432xx, STM32L433xx, STM32L443xx.
+ * - STM32L471xx, STM32L475xx, STM32L476xx, STM32L496xx.
+ * - STM32L485xx, STM32L486xx, STM32L4A6xx.
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L443xx) || \
+ defined(STM32L452xx) || defined(STM32L471xx) || defined(STM32L475xx) || \
+ defined(STM32L476xx) || defined(STM32L496xx) || defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32L4xx Ultra Low Power"
+
+#elif defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx)
+#define PLATFORM_NAME "STM32L4xx Ultra Low Power with Crypto"
+
+#else
+#error "STM32L4xx device not specified"
+#endif
+
+/**
+ * @brief Sub-family identifier.
+ */
+#if !defined(STM32L4XX) || defined(__DOXYGEN__)
+#define STM32L4XX
+#endif
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define STM32_HSI16CLK 16000000 /**< 16MHz internal clock. */
+#define STM32_HSI48CLK 48000000 /**< 48MHz internal clock. */
+#define STM32_LSICLK 32000 /**< Low speed internal clock. */
+/** @} */
+
+/**
+ * @name PWR_CR1 register bits definitions
+ * @{
+ */
+#define STM32_VOS_MASK (3 << 9) /**< Core voltage mask. */
+#define STM32_VOS_RANGE1 (1 << 9) /**< Core voltage 1.2 Volts. */
+#define STM32_VOS_RANGE2 (2 << 9) /**< Core voltage 1.0 Volts. */
+/** @} */
+
+/**
+ * @name PWR_CR2 register bits definitions
+ * @{
+ */
+#define STM32_PLS_MASK (7 << 1) /**< PLS bits mask. */
+#define STM32_PLS_LEV0 (0 << 1) /**< PVD level 0. */
+#define STM32_PLS_LEV1 (1 << 1) /**< PVD level 1. */
+#define STM32_PLS_LEV2 (2 << 1) /**< PVD level 2. */
+#define STM32_PLS_LEV3 (3 << 1) /**< PVD level 3. */
+#define STM32_PLS_LEV4 (4 << 1) /**< PVD level 4. */
+#define STM32_PLS_LEV5 (5 << 1) /**< PVD level 5. */
+#define STM32_PLS_LEV6 (6 << 1) /**< PVD level 6. */
+#define STM32_PLS_EXT (7 << 1) /**< PVD level 7. */
+/** @} */
+
+/**
+ * @name RCC_CR register bits definitions
+ * @{
+ */
+#define STM32_MSIRANGE_MASK (15 << 4) /**< MSIRANGE field mask. */
+#define STM32_MSIRANGE_100K (0 << 4) /**< 100kHz nominal. */
+#define STM32_MSIRANGE_200K (1 << 4) /**< 200kHz nominal. */
+#define STM32_MSIRANGE_400K (2 << 4) /**< 400kHz nominal. */
+#define STM32_MSIRANGE_800K (3 << 4) /**< 800kHz nominal. */
+#define STM32_MSIRANGE_1M (4 << 4) /**< 1MHz nominal. */
+#define STM32_MSIRANGE_2M (5 << 4) /**< 2MHz nominal. */
+#define STM32_MSIRANGE_4M (6 << 4) /**< 4MHz nominal. */
+#define STM32_MSIRANGE_8M (7 << 4) /**< 8MHz nominal. */
+#define STM32_MSIRANGE_16M (8 << 4) /**< 16MHz nominal. */
+#define STM32_MSIRANGE_24M (9 << 4) /**< 24MHz nominal. */
+#define STM32_MSIRANGE_32M (10 << 4) /**< 32MHz nominal. */
+#define STM32_MSIRANGE_48M (11 << 4) /**< 48MHz nominal. */
+/** @} */
+
+/**
+ * @name RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_MASK (3 << 0) /**< SW field mask. */
+#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
+#define STM32_SW_HSI16 (1 << 0) /**< SYSCLK source is HSI. */
+#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
+#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */
+
+#define STM32_HPRE_MASK (15 << 4) /**< HPRE field mask. */
+#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
+#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
+#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
+#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
+#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
+#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
+#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
+#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
+#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
+
+#define STM32_PPRE1_MASK (7 << 8) /**< PPRE1 field mask. */
+#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
+#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
+#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
+#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
+#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
+
+#define STM32_PPRE2_MASK (7 << 11) /**< PPRE2 field mask. */
+#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
+#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
+#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
+#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
+#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
+
+#define STM32_STOPWUCK_MASK (1 << 15) /**< STOPWUCK field mask. */
+#define STM32_STOPWUCK_MSI (0 << 15) /**< Wakeup clock is MSI. */
+#define STM32_STOPWUCK_HSI16 (1 << 15) /**< Wakeup clock is HSI16. */
+
+#define STM32_MCOSEL_MASK (15 << 24) /**< MCOSEL field mask. */
+#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
+#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */
+#define STM32_MCOSEL_MSI (2 << 24) /**< MSI clock on MCO pin. */
+#define STM32_MCOSEL_HSI16 (3 << 24) /**< HSI16 clock on MCO pin. */
+#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */
+#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */
+#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
+#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */
+#define STM32_MCOSEL_HSI48 (8 << 24) /**< HSI48 clock on MCO pin. */
+
+#define STM32_MCOPRE_MASK (7 << 28) /**< MCOPRE field mask. */
+#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
+#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 2. */
+#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 4. */
+#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 8. */
+#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 16. */
+/** @} */
+
+/**
+ * @name RCC_PLLCFGR register bits definitions
+ * @{
+ */
+#define STM32_PLLSRC_MASK (3 << 0) /**< PLL clock source mask. */
+#define STM32_PLLSRC_NOCLOCK (0 << 0) /**< PLL clock source disabled. */
+#define STM32_PLLSRC_MSI (1 << 0) /**< PLL clock source is MSI. */
+#define STM32_PLLSRC_HSI16 (2 << 0) /**< PLL clock source is HSI16. */
+#define STM32_PLLSRC_HSE (3 << 0) /**< PLL clock source is HSE. */
+/** @} */
+
+/**
+ * @name RCC_CCIPR register bits definitions
+ * @{
+ */
+#define STM32_USART1SEL_MASK (3 << 0) /**< USART1SEL mask. */
+#define STM32_USART1SEL_PCLK2 (0 << 0) /**< USART1 source is PCLK2. */
+#define STM32_USART1SEL_SYSCLK (1 << 0) /**< USART1 source is SYSCLK. */
+#define STM32_USART1SEL_HSI16 (2 << 0) /**< USART1 source is HSI16. */
+#define STM32_USART1SEL_LSE (3 << 0) /**< USART1 source is LSE. */
+
+#define STM32_USART2SEL_MASK (3 << 2) /**< USART2 mask. */
+#define STM32_USART2SEL_PCLK1 (0 << 2) /**< USART2 source is PCLK1. */
+#define STM32_USART2SEL_SYSCLK (1 << 2) /**< USART2 source is SYSCLK. */
+#define STM32_USART2SEL_HSI16 (2 << 2) /**< USART2 source is HSI16. */
+#define STM32_USART2SEL_LSE (3 << 2) /**< USART2 source is LSE. */
+
+#define STM32_USART3SEL_MASK (3 << 4) /**< USART3 mask. */
+#define STM32_USART3SEL_PCLK1 (0 << 4) /**< USART3 source is PCLK1. */
+#define STM32_USART3SEL_SYSCLK (1 << 4) /**< USART3 source is SYSCLK. */
+#define STM32_USART3SEL_HSI16 (2 << 4) /**< USART3 source is HSI16. */
+#define STM32_USART3SEL_LSE (3 << 4) /**< USART3 source is LSE. */
+
+#define STM32_UART4SEL_MASK (3 << 6) /**< UART4 mask. */
+#define STM32_UART4SEL_PCLK1 (0 << 6) /**< UART4 source is PCLK1. */
+#define STM32_UART4SEL_SYSCLK (1 << 6) /**< UART4 source is SYSCLK. */
+#define STM32_UART4SEL_HSI16 (2 << 6) /**< UART4 source is HSI16. */
+#define STM32_UART4SEL_LSE (3 << 6) /**< UART4 source is LSE. */
+
+#define STM32_UART5SEL_MASK (3 << 8) /**< UART5 mask. */
+#define STM32_UART5SEL_PCLK1 (0 << 8) /**< UART5 source is PCLK1. */
+#define STM32_UART5SEL_SYSCLK (1 << 8) /**< UART5 source is SYSCLK. */
+#define STM32_UART5SEL_HSI16 (2 << 8) /**< UART5 source is HSI16. */
+#define STM32_UART5SEL_LSE (3 << 8) /**< UART5 source is LSE. */
+
+#define STM32_LPUART1SEL_MASK (3 << 10) /**< LPUART1 mask. */
+#define STM32_LPUART1SEL_PCLK1 (0 << 10) /**< LPUART1 source is PCLK1. */
+#define STM32_LPUART1SEL_SYSCLK (1 << 10) /**< LPUART1 source is SYSCLK. */
+#define STM32_LPUART1SEL_HSI16 (2 << 10) /**< LPUART1 source is HSI16. */
+#define STM32_LPUART1SEL_LSE (3 << 10) /**< LPUART1 source is LSE. */
+
+#define STM32_I2C1SEL_MASK (3 << 12) /**< I2C1SEL mask. */
+#define STM32_I2C1SEL_PCLK1 (0 << 12) /**< I2C1 source is PCLK1. */
+#define STM32_I2C1SEL_SYSCLK (1 << 12) /**< I2C1 source is SYSCLK. */
+#define STM32_I2C1SEL_HSI16 (2 << 12) /**< I2C1 source is HSI16. */
+
+#define STM32_I2C2SEL_MASK (3 << 14) /**< I2C2SEL mask. */
+#define STM32_I2C2SEL_PCLK1 (0 << 14) /**< I2C2 source is PCLK1. */
+#define STM32_I2C2SEL_SYSCLK (1 << 14) /**< I2C2 source is SYSCLK. */
+#define STM32_I2C2SEL_HSI16 (2 << 14) /**< I2C2 source is HSI16. */
+
+#define STM32_I2C3SEL_MASK (3 << 16) /**< I2C3SEL mask. */
+#define STM32_I2C3SEL_PCLK1 (0 << 16) /**< I2C3 source is PCLK1. */
+#define STM32_I2C3SEL_SYSCLK (1 << 16) /**< I2C3 source is SYSCLK. */
+#define STM32_I2C3SEL_HSI16 (2 << 16) /**< I2C3 source is HSI16. */
+
+#define STM32_LPTIM1SEL_MASK (3 << 18) /**< LPTIM1SEL mask. */
+#define STM32_LPTIM1SEL_PCLK1 (0 << 18) /**< LPTIM1 source is PCLK1. */
+#define STM32_LPTIM1SEL_LSI (1 << 18) /**< LPTIM1 source is LSI. */
+#define STM32_LPTIM1SEL_HSI16 (2 << 18) /**< LPTIM1 source is HSI16. */
+#define STM32_LPTIM1SEL_LSE (3 << 18) /**< LPTIM1 source is LSE. */
+
+#define STM32_LPTIM2SEL_MASK (3 << 20) /**< LPTIM2SEL mask. */
+#define STM32_LPTIM2SEL_PCLK1 (0 << 20) /**< LPTIM2 source is PCLK1. */
+#define STM32_LPTIM2SEL_LSI (1 << 20) /**< LPTIM2 source is LSI. */
+#define STM32_LPTIM2SEL_HSI16 (2 << 20) /**< LPTIM2 source is HSI16. */
+#define STM32_LPTIM2SEL_LSE (3 << 20) /**< LPTIM2 source is LSE. */
+
+#define STM32_SAI1SEL_MASK (3 << 22) /**< SAI1SEL mask. */
+#define STM32_SAI1SEL_PLLSAI1 (0 << 22) /**< SAI1 source is PLLSAI1-P. */
+#define STM32_SAI1SEL_PLLSAI2 (1 << 22) /**< SAI1 source is PLLSAI2-P. */
+#define STM32_SAI1SEL_PLL (2 << 22) /**< SAI1 source is PLL-P. */
+#define STM32_SAI1SEL_EXTCLK (3 << 22) /**< SAI1 source is external. */
+#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
+
+#define STM32_SAI2SEL_MASK (3 << 24) /**< SAI2SEL mask. */
+#define STM32_SAI2SEL_PLLSAI1 (0 << 24) /**< SAI2 source is PLLSAI1-P. */
+#define STM32_SAI2SEL_PLLSAI2 (1 << 24) /**< SAI2 source is PLLSAI2-P. */
+#define STM32_SAI2SEL_PLL (2 << 24) /**< SAI2 source is PLL-P. */
+#define STM32_SAI2SEL_EXTCLK (3 << 24) /**< SAI2 source is external. */
+#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
+
+#define STM32_CLK48SEL_MASK (3 << 26) /**< CLK48SEL mask. */
+#if !STM32_CLOCK_HAS_HSI48
+#define STM32_CLK48SEL_NOCLK (0 << 26) /**< CLK48 disabled. */
+#else
+#define STM32_CLK48SEL_HSI48 (0 << 26) /**< CLK48 source is HSI48. */
+#endif
+#define STM32_CLK48SEL_PLLSAI1 (1 << 26) /**< CLK48 source is PLLSAI1-Q. */
+#define STM32_CLK48SEL_PLL (2 << 26) /**< CLK48 source is PLL-Q. */
+#define STM32_CLK48SEL_MSI (3 << 26) /**< CLK48 source is MSI. */
+
+#define STM32_ADCSEL_MASK (3 << 28) /**< ADCSEL mask. */
+#define STM32_ADCSEL_NOCLK (0 << 28) /**< ADC clock disabled. */
+#define STM32_ADCSEL_PLLSAI1 (1 << 28) /**< ADC source is PLLSAI1-R. */
+#define STM32_ADCSEL_PLLSAI2 (2 << 28) /**< ADC source is PLLSAI2-R. */
+#define STM32_ADCSEL_SYSCLK (3 << 28) /**< ADC source is SYSCLK. */
+
+#define STM32_SWPMI1SEL_MASK (1 << 30) /**< SWPMI1SEL mask. */
+#define STM32_SWPMI1SEL_PCLK1 (0 << 30) /**< SWPMI1 source is PCLK1. */
+#define STM32_SWPMI1SEL_HSI16 (1 << 30) /**< SWPMI1 source is HSI16. */
+
+#define STM32_DFSDMSEL_MASK (1 << 31) /**< DFSDMSEL mask. */
+#define STM32_DFSDMSEL_PCLK2 (0 << 31) /**< DFSDM source is PCLK2. */
+#define STM32_DFSDMSEL_SYSCLK (1 << 31) /**< DFSDM source is SYSCLK. */
+/** @} */
+
+/**
+ * @name RCC_CCIPR2 register bits definitions
+ * @{
+ */
+#define STM32_I2C4SEL_MASK (3 << 0) /**< I2C1SEL mask. */
+#define STM32_I2C4SEL_PCLK1 (0 << 0) /**< I2C1 source is PCLK1. */
+#define STM32_I2C4SEL_SYSCLK (1 << 0) /**< I2C1 source is SYSCLK. */
+#define STM32_I2C4SEL_HSI16 (2 << 0) /**< I2C1 source is HSI16. */
+/** @} */
+
+/**
+ * @name RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */
+#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */
+#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */
+#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */
+#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
+
+#define STM32_LSCOSEL_MASK (3 << 24) /**< LSCO pin clock source. */
+#define STM32_LSCOSEL_NOCLOCK (0 << 24) /**< No clock on LSCO pin. */
+#define STM32_LSCOSEL_LSI (1 << 24) /**< LSI on LSCO pin. */
+#define STM32_LSCOSEL_LSE (3 << 24) /**< LSE on LSCO pin. */
+/** @} */
+
+/**
+ * @name RCC_CSR register bits definitions
+ * @{
+ */
+#define STM32_MSISRANGE_MASK (15 << 8) /**< MSISRANGE field mask. */
+#define STM32_MSISRANGE_1M (4 << 8) /**< 1MHz nominal. */
+#define STM32_MSISRANGE_2M (5 << 8) /**< 2MHz nominal. */
+#define STM32_MSISRANGE_4M (6 << 8) /**< 4MHz nominal. */
+#define STM32_MSISRANGE_8M (7 << 8) /**< 8MHz nominal. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Core voltage selection.
+ * @note This setting affects all the performance and clock related
+ * settings, the maximum performance is only obtainable selecting
+ * the maximum voltage.
+ */
+#if !defined(STM32_VOS) || defined(__DOXYGEN__)
+#define STM32_VOS STM32_VOS_RANGE1
+#endif
+
+/**
+ * @brief Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE FALSE
+#endif
+
+/**
+ * @brief Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief Enables or disables the HSI16 clock source.
+ */
+#if !defined(STM32_HSI16_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI16_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the HSI48 clock source.
+ */
+#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI48_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the MSI PLL on LSE clock source.
+ */
+#if !defined(STM32_MSIPLL_ENABLED) || defined(__DOXYGEN__)
+#define STM32_MSIPLL_ENABLED FALSE
+#endif
+
+/**
+ * @brief MSI frequency setting.
+ */
+#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__)
+#define STM32_MSIRANGE STM32_MSIRANGE_4M
+#endif
+
+/**
+ * @brief MSI frequency setting after standby.
+ */
+#if !defined(STM32_MSISRANGE) || defined(__DOXYGEN__)
+#define STM32_MSISRANGE STM32_MSISRANGE_4M
+#endif
+
+/**
+ * @brief Main clock source selection.
+ * @note If the selected clock source is not the PLL then the PLL is not
+ * initialized and started.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW STM32_SW_PLL
+#endif
+
+/**
+ * @brief Clock source for the PLL.
+ * @note This setting has only effect if the PLL is selected as the
+ * system clock source.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC STM32_PLLSRC_MSI
+#endif
+
+/**
+ * @brief PLLM divider value.
+ * @note The allowed values are 1..8.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLM_VALUE 1
+#endif
+
+/**
+ * @brief PLLN multiplier value.
+ * @note The allowed values are 8..86.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLN_VALUE 80
+#endif
+
+/**
+ * @brief PLLPDIV divider value or zero if disabled.
+ * @note The allowed values are 0, 2..31.
+ */
+#if !defined(STM32_PLLPDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLPDIV_VALUE 0
+#endif
+
+/**
+ * @brief PLLP divider value.
+ * @note The allowed values are 7, 17.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLP_VALUE 7
+#endif
+
+/**
+ * @brief PLLQ divider value.
+ * @note The allowed values are 2, 4, 6, 8.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLQ_VALUE 6
+#endif
+
+/**
+ * @brief PLLR divider value.
+ * @note The allowed values are 2, 4, 6, 8.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLR_VALUE 4
+#endif
+
+/**
+ * @brief AHB prescaler value.
+ * @note The default value is calculated for a 80MHz system clock from
+ * the internal 4MHz MSI clock.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1 STM32_PPRE1_DIV1
+#endif
+
+/**
+ * @brief APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2 STM32_PPRE2_DIV1
+#endif
+
+/**
+ * @brief STOPWUCK clock setting.
+ */
+#if !defined(STM32_STOPWUCK) || defined(__DOXYGEN__)
+#define STM32_STOPWUCK STM32_STOPWUCK_MSI
+#endif
+
+/**
+ * @brief MCO clock source.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief MCO divider setting.
+ */
+#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#endif
+
+/**
+ * @brief LSCO clock source.
+ */
+#if !defined(STM32_LSCOSEL) || defined(__DOXYGEN__)
+#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief PLLSAI1N multiplier value.
+ * @note The allowed values are 8..86.
+ */
+#if !defined(STM32_PLLSAI1N_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1N_VALUE 80
+#endif
+
+/**
+ * @brief PLLSAI1PDIV divider value or zero if disabled.
+ * @note The allowed values are 0, 2..31.
+ */
+#if !defined(STM32_PLLSAI1PDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1PDIV_VALUE 0
+#endif
+
+/**
+ * @brief PLLSAI1P divider value.
+ * @note The allowed values are 7, 17.
+ */
+#if !defined(STM32_PLLSAI1P_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1P_VALUE 7
+#endif
+
+/**
+ * @brief PLLSAI1Q divider value.
+ * @note The allowed values are 2, 4, 6, 8.
+ */
+#if !defined(STM32_PLLSAI1Q_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1Q_VALUE 6
+#endif
+
+/**
+ * @brief PLLSAI1R divider value.
+ * @note The allowed values are 2, 4, 6, 8.
+ */
+#if !defined(STM32_PLLSAI1R_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1R_VALUE 4
+#endif
+
+/**
+ * @brief PLLSAI2N multiplier value.
+ * @note The allowed values are 8..86.
+ */
+#if !defined(STM32_PLLSAI2N_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2N_VALUE 80
+#endif
+
+/**
+ * @brief PLLSAI2PDIV divider value or zero if disabled.
+ * @note The allowed values are 0, 2..31.
+ */
+#if !defined(STM32_PLLSAI2PDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2PDIV_VALUE 0
+#endif
+
+/**
+ * @brief PLLSAI2P divider value.
+ * @note The allowed values are 7, 17.
+ */
+#if !defined(STM32_PLLSAI2P_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2P_VALUE 7
+#endif
+
+/**
+ * @brief PLLSAI2R divider value.
+ * @note The allowed values are 2, 4, 6, 8.
+ */
+#if !defined(STM32_PLLSAI2R_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2R_VALUE 4
+#endif
+
+/**
+ * @brief USART1 clock source.
+ */
+#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__)
+#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
+#endif
+
+/**
+ * @brief USART2 clock source.
+ */
+#if !defined(STM32_USART2SEL) || defined(__DOXYGEN__)
+#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
+#endif
+
+/**
+ * @brief USART3 clock source.
+ */
+#if !defined(STM32_USART3SEL) || defined(__DOXYGEN__)
+#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
+#endif
+
+/**
+ * @brief UART4 clock source.
+ */
+#if !defined(STM32_UART4SEL) || defined(__DOXYGEN__)
+#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
+#endif
+
+/**
+ * @brief UART5 clock source.
+ */
+#if !defined(STM32_UART5SEL) || defined(__DOXYGEN__)
+#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
+#endif
+
+/**
+ * @brief LPUART1 clock source.
+ */
+#if !defined(STM32_LPUART1SEL) || defined(__DOXYGEN__)
+#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
+#endif
+
+/**
+ * @brief I2C1 clock source.
+ */
+#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__)
+#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
+#endif
+
+/**
+ * @brief I2C2 clock source.
+ */
+#if !defined(STM32_I2C2SEL) || defined(__DOXYGEN__)
+#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
+#endif
+
+/**
+ * @brief I2C3 clock source.
+ */
+#if !defined(STM32_I2C3SEL) || defined(__DOXYGEN__)
+#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
+#endif
+
+/**
+ * @brief I2C4 clock source.
+ */
+#if !defined(STM32_I2C4SEL) || defined(__DOXYGEN__)
+#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
+#endif
+
+/**
+ * @brief LPTIM1 clock source.
+ */
+#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__)
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
+#endif
+
+/**
+ * @brief LPTIM2 clock source.
+ */
+#if !defined(STM32_LPTIM2SEL) || defined(__DOXYGEN__)
+#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
+#endif
+
+/**
+ * @brief SAI1SEL value (SAI1 clock source).
+ */
+#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
+#define STM32_SAI1SEL STM32_SAI1SEL_OFF
+#endif
+
+/**
+ * @brief SAI2SEL value (SAI2 clock source).
+ */
+#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)
+#define STM32_SAI2SEL STM32_SAI2SEL_OFF
+#endif
+
+/**
+ * @brief CLK48SEL value (48MHz clock source).
+ */
+#if !defined(STM32_CLK48SEL) || defined(__DOXYGEN__)
+#define STM32_CLK48SEL STM32_CLK48SEL_PLL
+#endif
+
+/**
+ * @brief ADCSEL value (ADCs clock source).
+ */
+#if !defined(STM32_ADCSEL) || defined(__DOXYGEN__)
+#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
+#endif
+
+/**
+ * @brief SWPMI1SEL value (SWPMI clock source).
+ */
+#if !defined(STM32_SWPMI1SEL) || defined(__DOXYGEN__)
+#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
+#endif
+
+/**
+ * @brief DFSDMSEL value (DFSDM clock source).
+ */
+#if !defined(STM32_DFSDMSEL) || defined(__DOXYGEN__)
+#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
+#endif
+
+/**
+ * @brief RTC/LCD clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32L4xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32L4xx_MCUCONF not defined"
+#endif
+
+/* Only some devices have strongly checked mcuconf.h files. Others will be
+ added gradually.*/
+#if defined(STM32L432xx) && !defined(STM32L432_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32L432_MCUCONF not defined"
+#endif
+
+#if defined(STM32L433xx) && !defined(STM32L433_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32L433_MCUCONF not defined"
+#endif
+
+#if defined(STM32L476xx) && !defined(STM32L476_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32L476_MCUCONF not defined"
+#endif
+
+#if defined(STM32L486xx) && !defined(STM32L486_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32L486_MCUCONF not defined"
+#endif
+
+#if defined(STM32L496xx) && !defined(STM32L496_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32L496_MCUCONF not defined"
+#endif
+
+#if defined(STM32L4A6xx) && !defined(STM32L4A6_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32L4A6_MCUCONF not defined"
+#endif
+
+/*
+ * Board files sanity checks.
+ */
+#if !defined(STM32_LSECLK)
+#error "STM32_LSECLK not defined in board.h"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined in board.h"
+#endif
+
+#if !defined(STM32_HSECLK)
+#error "STM32_HSECLK not defined in board.h"
+#endif
+
+/* Voltage related limits.*/
+#if (STM32_VOS == STM32_VOS_RANGE1) || defined(__DOXYGEN__)
+/**
+ * @name System Limits
+ * @{
+ */
+/**
+ * @brief Maximum SYSCLK clock frequency at current voltage setting.
+ */
+#define STM32_SYSCLK_MAX 80000000
+
+/**
+ * @brief Maximum HSE clock frequency at current voltage setting.
+ */
+#define STM32_HSECLK_MAX 48000000
+
+/**
+ * @brief Maximum HSE clock frequency using an external source.
+ */
+#define STM32_HSECLK_BYP_MAX 48000000
+
+/**
+ * @brief Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN 4000000
+
+/**
+ * @brief Minimum HSE clock frequency using an external source.
+ */
+#define STM32_HSECLK_BYP_MIN 8000000
+
+/**
+ * @brief Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX 32768
+
+/**
+ * @brief Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_BYP_MAX 1000000
+
+/**
+ * @brief Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN 32768
+
+/**
+ * @brief Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_BYP_MIN 32768
+
+/**
+ * @brief Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX 16000000
+
+/**
+ * @brief Minimum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN 4000000
+
+/**
+ * @brief Maximum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MAX 344000000
+
+/**
+ * @brief Minimum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MIN 64000000
+
+/**
+ * @brief Maximum PLL-P output clock frequency.
+ */
+#define STM32_PLLP_MAX 80000000
+
+/**
+ * @brief Minimum PLL-P output clock frequency.
+ */
+#define STM32_PLLP_MIN 2064500
+
+/**
+ * @brief Maximum PLL-Q output clock frequency.
+ */
+#define STM32_PLLQ_MAX 80000000
+
+/**
+ * @brief Minimum PLL-Q output clock frequency.
+ */
+#define STM32_PLLQ_MIN 8000000
+
+/**
+ * @brief Maximum PLL-R output clock frequency.
+ */
+#define STM32_PLLR_MAX 80000000
+
+/**
+ * @brief Minimum PLL-R output clock frequency.
+ */
+#define STM32_PLLR_MIN 8000000
+
+/**
+ * @brief Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX 80000000
+
+/**
+ * @brief Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX 80000000
+
+/**
+ * @brief Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX 80000000
+/** @} */
+
+/**
+ * @name Flash Wait states
+ * @{
+ */
+#define STM32_0WS_THRESHOLD 16000000
+#define STM32_1WS_THRESHOLD 32000000
+#define STM32_2WS_THRESHOLD 48000000
+#define STM32_3WS_THRESHOLD 64000000
+/** @} */
+
+#elif STM32_VOS == STM32_VOS_RANGE2
+#define STM32_SYSCLK_MAX 26000000
+#define STM32_HSECLK_MAX 26000000
+#define STM32_HSECLK_BYP_MAX 26000000
+#define STM32_HSECLK_MIN 8000000
+#define STM32_HSECLK_BYP_MIN 8000000
+#define STM32_LSECLK_MAX 32768
+#define STM32_LSECLK_BYP_MAX 1000000
+#define STM32_LSECLK_MIN 32768
+#define STM32_LSECLK_BYP_MIN 32768
+#define STM32_PLLIN_MAX 16000000
+#define STM32_PLLIN_MIN 4000000
+#define STM32_PLLVCO_MAX 128000000
+#define STM32_PLLVCO_MIN 64000000
+#define STM32_PLLP_MAX 26000000
+#define STM32_PLLP_MIN 2064500
+#define STM32_PLLQ_MAX 26000000
+#define STM32_PLLQ_MIN 8000000
+#define STM32_PLLR_MAX 26000000
+#define STM32_PLLR_MIN 8000000
+#define STM32_PCLK1_MAX 26000000
+#define STM32_PCLK2_MAX 26000000
+#define STM32_ADCCLK_MAX 26000000
+
+#define STM32_0WS_THRESHOLD 6000000
+#define STM32_1WS_THRESHOLD 12000000
+#define STM32_2WS_THRESHOLD 18000000
+#define STM32_3WS_THRESHOLD 26000000
+
+#else
+#error "invalid STM32_VOS value specified"
+#endif
+
+/**
+ * @brief MSI frequency.
+ */
+#if STM32_MSIRANGE == STM32_MSIRANGE_100K
+#define STM32_MSICLK 100000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_200K
+#define STM32_MSICLK 200000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_400K
+#define STM32_MSICLK 400000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_800K
+#define STM32_MSICLK 800000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_1M
+#define STM32_MSICLK 1000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_2M
+#define STM32_MSICLK 2000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_4M
+#define STM32_MSICLK 4000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_8M
+#define STM32_MSICLK 8000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_16M
+#define STM32_MSICLK 16000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_24M
+#define STM32_MSICLK 24000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_32M
+#define STM32_MSICLK 32000000
+#elif STM32_MSIRANGE == STM32_MSIRANGE_48M
+#define STM32_MSICLK 48000000
+#else
+#error "invalid STM32_MSIRANGE value specified"
+#endif
+
+/**
+ * @brief MSIS frequency.
+ */
+#if STM32_MSISRANGE == STM32_MSISRANGE_1M
+#define STM32_MSISCLK 1000000
+#elif STM32_MSISRANGE == STM32_MSISRANGE_2M
+#define STM32_MSISCLK 2000000
+#elif STM32_MSISRANGE == STM32_MSISRANGE_4M
+#define STM32_MSISCLK 4000000
+#elif STM32_MSISRANGE == STM32_MSISRANGE_8M
+#define STM32_MSISCLK 8000000
+#else
+#error "invalid STM32_MSISRANGE value specified"
+#endif
+
+/*
+ * HSI16 related checks.
+ */
+#if STM32_HSI16_ENABLED
+#else /* !STM32_HSI16_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI16
+#error "HSI16 not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI16)
+#error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI16) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI16))
+#error "HSI16 not enabled, required by STM32_MCOSEL"
+#endif
+
+#if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
+ (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI16)
+#error "HSI16 not enabled, required by STM32_SAI1SEL"
+#endif
+
+#if ((STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI16)
+#error "HSI16 not enabled, required by STM32_SAI2SEL"
+#endif
+
+#if (STM32_USART1SEL == STM32_USART1SEL_HSI16)
+#error "HSI16 not enabled, required by STM32_USART1SEL"
+#endif
+#if (STM32_USART2SEL == STM32_USART2SEL_HSI16)
+#error "HSI16 not enabled, required by STM32_USART2SEL"
+#endif
+#if (STM32_USART3SEL == STM32_USART3SEL_HSI16)
+#error "HSI16 not enabled, required by STM32_USART3SEL"
+#endif
+#if (STM32_UART4SEL == STM32_UART4SEL_HSI16)
+#error "HSI16 not enabled, required by STM32_UART4SEL"
+#endif
+#if (STM32_UART5SEL == STM32_UART5SEL_HSI16)
+#error "HSI16 not enabled, required by STM32_UART5SEL"
+#endif
+#if (STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16)
+#error "HSI16 not enabled, required by STM32_LPUART1SEL"
+#endif
+
+#if (STM32_I2C1SEL == STM32_I2C1SEL_HSI16)
+#error "HSI16 not enabled, required by I2C1SEL"
+#endif
+#if (STM32_I2C2SEL == STM32_I2C2SEL_HSI16)
+#error "HSI16 not enabled, required by I2C2SEL"
+#endif
+#if (STM32_I2C3SEL == STM32_I2C3SEL_HSI16)
+#error "HSI16 not enabled, required by I2C3SEL"
+#endif
+#if (STM32_I2C4SEL == STM32_I2C4SEL_HSI16)
+#error "HSI16 not enabled, required by I2C4SEL"
+#endif
+
+#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16)
+#error "HSI16 not enabled, required by LPTIM1SEL"
+#endif
+#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16)
+#error "HSI16 not enabled, required by LPTIM2SEL"
+#endif
+
+#if (STM32_SWPMI1SEL == STM32_SWPMI1SEL_HSI16)
+#error "HSI16 not enabled, required by SWPMI1SEL"
+#endif
+#if (STM32_STOPWUCK == STM32_STOPWUCK_HSI16)
+#error "HSI16 not enabled, required by STM32_STOPWUCK"
+#endif
+
+#endif /* !STM32_HSI16_ENABLED */
+
+#if STM32_CLOCK_HAS_HSI48
+#if STM32_HSI48_ENABLED
+#else /* !STM32_HSI48_ENABLED */
+
+#if STM32_MCOSEL == STM32_MCOSEL_HSI48
+#error "HSI48 not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_CLK48SEL == STM32_CLK48SEL_HSI48
+#error "HSI48 not enabled, required by STM32_CLK48SEL"
+#endif
+#endif /* !STM32_HSI48_ENABLED */
+#endif /* STM32_CLOCK_HAS_HSI48 */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+ #if STM32_HSECLK == 0
+ #error "HSE frequency not defined"
+ #else /* STM32_HSECLK != 0 */
+ #if defined(STM32_HSE_BYPASS)
+ #if (STM32_HSECLK < STM32_HSECLK_BYP_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
+ #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_BYP_MIN...STM32_HSECLK_BYP_MAX)"
+ #endif
+ #else /* !defined(STM32_HSE_BYPASS) */
+ #if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+ #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+ #endif
+ #endif /* !defined(STM32_HSE_BYPASS) */
+ #endif /* STM32_HSECLK != 0 */
+
+ #else /* !STM32_HSE_ENABLED */
+
+ #if STM32_SW == STM32_SW_HSE
+ #error "HSE not enabled, required by STM32_SW"
+ #endif
+
+ #if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+ #error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+ #endif
+
+ #if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
+ ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE))
+ #error "HSE not enabled, required by STM32_MCOSEL"
+ #endif
+
+ #if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) | \
+ (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)
+ #error "HSE not enabled, required by STM32_SAI1SEL"
+ #endif
+
+ #if ((STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) | \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2)) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)
+ #error "HSE not enabled, required by STM32_SAI2SEL"
+ #endif
+
+ #if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+ #error "HSE not enabled, required by STM32_RTCSEL"
+ #endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+ #if STM32_RTCSEL == STM32_RTCSEL_LSI
+ #error "LSI not enabled, required by STM32_RTCSEL"
+ #endif
+
+ #if STM32_MCOSEL == STM32_MCOSEL_LSI
+ #error "LSI not enabled, required by STM32_MCOSEL"
+ #endif
+
+ #if STM32_LSCOSEL == STM32_LSCOSEL_LSI
+ #error "LSI not enabled, required by STM32_LSCOSEL"
+ #endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+ #if (STM32_LSECLK == 0)
+ #error "LSE frequency not defined"
+ #endif
+
+ #if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+ #error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+ #endif
+
+#else /* !STM32_LSE_ENABLED */
+
+ #if STM32_RTCSEL == STM32_RTCSEL_LSE
+ #error "LSE not enabled, required by STM32_RTCSEL"
+ #endif
+
+ #if STM32_MCOSEL == STM32_MCOSEL_LSE
+ #error "LSE not enabled, required by STM32_MCOSEL"
+ #endif
+
+ #if STM32_LSCOSEL == STM32_LSCOSEL_LSE
+ #error "LSE not enabled, required by STM32_LSCOSEL"
+ #endif
+
+ #if STM32_MSIPLL_ENABLED == TRUE
+ #error "LSE not enabled, required by STM32_MSIPLL_ENABLED"
+ #endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/*
+ * MSI related checks.
+ */
+#if (STM32_MSIRANGE == STM32_MSIRANGE_48M) && !STM32_MSIPLL_ENABLED
+#warning "STM32_MSIRANGE_48M should be used with STM32_MSIPLL_ENABLED"
+#endif
+
+/**
+ * @brief STM32_PLLM field.
+ */
+#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 8)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLM ((STM32_PLLM_VALUE - 1) << 4)
+#else
+#error "invalid STM32_PLLM_VALUE value specified"
+#endif
+
+/**
+ * @brief PLLs input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_MSI
+#define STM32_PLLCLKIN (STM32_MSICLK / STM32_PLLM_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
+#define STM32_PLLCLKIN (STM32_HSI16CLK / STM32_PLLM_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
+#define STM32_PLLCLKIN 0
+
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/*
+ * PLLs input frequency range check.
+ */
+#if (STM32_PLLCLKIN != 0) && \
+ ((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX))
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/*
+ * PLL enable check.
+ */
+#if (STM32_HSI48_ENABLED && (STM32_CLK48SEL == STM32_CLK48SEL_PLL)) || \
+ (STM32_SW == STM32_SW_PLL) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLL) || \
+ (STM32_SAI1SEL == STM32_SAI1SEL_PLL) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLL) || \
+ defined(__DOXYGEN__)
+
+#if STM32_PLLCLKIN == 0
+#error "PLL activation required but no PLL clock selected"
+#endif
+
+/**
+ * @brief PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL TRUE
+#else
+#define STM32_ACTIVATE_PLL FALSE
+#endif
+
+/**
+ * @brief STM32_PLLN field.
+ */
+#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 86)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLN (STM32_PLLN_VALUE << 8)
+#else
+#error "invalid STM32_PLLN_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLP field.
+ */
+#if (STM32_PLLP_VALUE == 7) || defined(__DOXYGEN__)
+#define STM32_PLLP (0 << 17)
+
+#elif STM32_PLLP_VALUE == 17
+#define STM32_PLLP (1 << 17)
+
+#else
+#error "invalid STM32_PLLP_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLQ field.
+ */
+#if (STM32_PLLQ_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLQ (0 << 21)
+
+#elif STM32_PLLQ_VALUE == 4
+#define STM32_PLLQ (1 << 21)
+
+#elif STM32_PLLQ_VALUE == 6
+#define STM32_PLLQ (2 << 21)
+
+#elif STM32_PLLQ_VALUE == 8
+#define STM32_PLLQ (3 << 21)
+
+#else
+#error "invalid STM32_PLLQ_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLR field.
+ */
+#if (STM32_PLLR_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLR (0 << 25)
+
+#elif STM32_PLLR_VALUE == 4
+#define STM32_PLLR (1 << 25)
+
+#elif STM32_PLLR_VALUE == 6
+#define STM32_PLLR (2 << 25)
+
+#elif STM32_PLLR_VALUE == 8
+#define STM32_PLLR (3 << 25)
+
+#else
+#error "invalid STM32_PLLR_VALUE value specified"
+#endif
+
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+/**
+ * @brief STM32_PLLPDIV field. (Only for STM32L496xx/4A6xx)
+ */
+#if (STM32_PLLPDIV_VALUE == 0) || \
+ ((STM32_PLLPDIV_VALUE >= 2) && (STM32_PLLPDIV_VALUE <= 31)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLPDIV (STM32_PLLPDIV_VALUE << 27)
+#else
+#error "invalid STM32_PLLPDIV_VALUE value specified"
+#endif
+#endif
+
+/**
+ * @brief STM32_PLLPEN field.
+ */
+#if (STM32_SAI1SEL == STM32_SAI1SEL_PLL) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLL) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLPEN (1 << 16)
+#else
+#define STM32_PLLPEN (0 << 16)
+#endif
+
+/**
+ * @brief STM32_PLLQEN field.
+ */
+#if (STM32_CLK48SEL == STM32_CLK48SEL_PLL) || defined(__DOXYGEN__)
+#define STM32_PLLQEN (1 << 20)
+#else
+#define STM32_PLLQEN (0 << 20)
+#endif
+
+/**
+ * @brief STM32_PLLREN field.
+ */
+#if (STM32_SW == STM32_SW_PLL) || \
+ (STM32_MCOSEL == STM32_MCOSEL_PLL) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLREN (1 << 24)
+#else
+#define STM32_PLLREN (0 << 24)
+#endif
+
+/**
+ * @brief PLL VCO frequency.
+ */
+#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
+
+/*
+ * PLL VCO frequency range check.
+ */
+#if STM32_ACTIVATE_PLL && \
+ ((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX))
+#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLL P output clock frequency.
+ */
+#if (STM32_PLLPDIV_VALUE == 0) || defined(__DOXYGEN__)
+#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
+#else
+#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLPDIV_VALUE)
+#endif
+
+/**
+ * @brief PLL Q output clock frequency.
+ */
+#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE)
+
+/**
+ * @brief PLL R output clock frequency.
+ */
+#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE)
+
+/*
+ * PLL-P output frequency range check.
+ */
+#if STM32_ACTIVATE_PLL && \
+ ((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX))
+#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
+#endif
+
+/*
+ * PLL-Q output frequency range check.
+ */
+#if STM32_ACTIVATE_PLL && \
+ ((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX))
+#error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
+#endif
+
+/*
+ * PLL-R output frequency range check.
+ */
+#if STM32_ACTIVATE_PLL && \
+ ((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX))
+#error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
+#endif
+
+/**
+ * @brief System clock source.
+ */
+#if STM32_NO_INIT || defined(__DOXYGEN__)
+#define STM32_SYSCLK STM32_MSICLK
+
+#elif (STM32_SW == STM32_SW_MSI)
+#define STM32_SYSCLK STM32_MSICLK
+
+#elif (STM32_SW == STM32_SW_HSI16)
+#define STM32_SYSCLK STM32_HSI16CLK
+
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK STM32_HSECLK
+
+#elif (STM32_SW == STM32_SW_PLL)
+#define STM32_SYSCLK STM32_PLL_R_CLKOUT
+
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK (STM32_SYSCLK / 1)
+
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK (STM32_SYSCLK / 2)
+
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK (STM32_SYSCLK / 4)
+
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK (STM32_SYSCLK / 8)
+
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK (STM32_SYSCLK / 16)
+
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK (STM32_SYSCLK / 64)
+
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK (STM32_SYSCLK / 128)
+
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK (STM32_SYSCLK / 256)
+
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK (STM32_SYSCLK / 512)
+
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/*
+ * AHB frequency check.
+ */
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1 (STM32_HCLK / 1)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1 (STM32_HCLK / 2)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1 (STM32_HCLK / 4)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1 (STM32_HCLK / 8)
+
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1 (STM32_HCLK / 16)
+
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/*
+ * APB1 frequency check.
+ */
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2 (STM32_HCLK / 1)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2 (STM32_HCLK / 2)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2 (STM32_HCLK / 4)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2 (STM32_HCLK / 8)
+
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2 (STM32_HCLK / 16)
+
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/*
+ * APB2 frequency check.
+ */
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/*
+ * PLLSAI1 enable check.
+ */
+#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \
+ (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || \
+ (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \
+ defined(__DOXYGEN__)
+
+#if STM32_PLLCLKIN == 0
+#error "PLLSAI1 activation required but no PLL clock selected"
+#endif
+
+/**
+ * @brief PLLSAI1 activation flag.
+ */
+#define STM32_ACTIVATE_PLLSAI1 TRUE
+#else
+#define STM32_ACTIVATE_PLLSAI1 FALSE
+#endif
+
+/**
+ * @brief STM32_PLLSAI1N field.
+ */
+#if ((STM32_PLLSAI1N_VALUE >= 8) && (STM32_PLLSAI1N_VALUE <= 86)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAI1N (STM32_PLLSAI1N_VALUE << 8)
+#else
+#error "invalid STM32_PLLSAI1N_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAI1P field.
+ */
+#if (STM32_PLLSAI1P_VALUE == 7) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1P (0 << 17)
+
+#elif STM32_PLLSAI1P_VALUE == 17
+#define STM32_PLLSAI1P (1 << 17)
+
+#else
+#error "invalid STM32_PLLSAI1P_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAI1Q field.
+ */
+#if (STM32_PLLSAI1Q_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1Q (0 << 21)
+
+#elif STM32_PLLSAI1Q_VALUE == 4
+#define STM32_PLLSAI1Q (1 << 21)
+
+#elif STM32_PLLSAI1Q_VALUE == 6
+#define STM32_PLLSAI1Q (2 << 21)
+
+#elif STM32_PLLSAI1Q_VALUE == 8
+#define STM32_PLLSAI1Q (3 << 21)
+
+#else
+#error "invalid STM32_PLLSAI1Q_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAI1R field.
+ */
+#if (STM32_PLLSAI1R_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1R (0 << 25)
+
+#elif STM32_PLLSAI1R_VALUE == 4
+#define STM32_PLLSAI1R (1 << 25)
+
+#elif STM32_PLLSAI1R_VALUE == 6
+#define STM32_PLLSAI1R (2 << 25)
+
+#elif STM32_PLLSAI1R_VALUE == 8
+#define STM32_PLLSAI1R (3 << 25)
+
+#else
+#error "invalid STM32_PLLSAI1R_VALUE value specified"
+#endif
+
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+/**
+ * @brief STM32_PLLSAI1PDIV field. (Only for STM32L496xx/4A6xx)
+ */
+#if ((STM32_PLLSAI1PDIV_VALUE != 1) && (STM32_PLLSAI1PDIV_VALUE <= 31)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAI1PDIV (STM32_PLLSAI1PDIV_VALUE << 27)
+#else
+#error "invalid STM32_PLLSAI1PDIV_VALUE value specified"
+#endif
+#endif
+
+/**
+ * @brief STM32_PLLSAI1PEN field.
+ */
+#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAI1PEN (1 << 16)
+#else
+#define STM32_PLLSAI1PEN (0 << 16)
+#endif
+
+/**
+ * @brief STM32_PLLSAI1QEN field.
+ */
+#if (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1QEN (1 << 20)
+#else
+#define STM32_PLLSAI1QEN (0 << 20)
+#endif
+
+/**
+ * @brief STM32_PLLSAI1REN field.
+ */
+#if (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1REN (1 << 24)
+#else
+#define STM32_PLLSAI1REN (0 << 24)
+#endif
+
+/**
+ * @brief PLLSAI1 VCO frequency.
+ */
+#define STM32_PLLSAI1VCO (STM32_PLLCLKIN * STM32_PLLSAI1N_VALUE)
+
+/*
+ * PLLSAI1 VCO frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI1 && \
+ ((STM32_PLLSAI1VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI1VCO > STM32_PLLVCO_MAX))
+#error "STM32_PLLSAI1VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLLSAI1-P output clock frequency.
+ */
+#if (STM32_PLLSAI1PDIV_VALUE == 0) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1P_VALUE)
+#else
+#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1PDIV_VALUE)
+#endif
+
+/**
+ * @brief PLLSAI1-Q output clock frequency.
+ */
+#define STM32_PLLSAI1_Q_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
+
+/**
+ * @brief PLLSAI1-R output clock frequency.
+ */
+#define STM32_PLLSAI1_R_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1R_VALUE)
+
+/*
+ * PLLSAI1-P output frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI1 && \
+ ((STM32_PLLSAI1_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI1_P_CLKOUT > STM32_PLLP_MAX))
+#error "STM32_PLLSAI1_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
+#endif
+
+/*
+ * PLLSAI1-Q output frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI1 && \
+ ((STM32_PLLSAI1_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLLSAI1_Q_CLKOUT > STM32_PLLQ_MAX))
+#error "STM32_PLLSAI1_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
+#endif
+
+/*
+ * PLLSAI1-R output frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI1 && \
+ ((STM32_PLLSAI1_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI1_R_CLKOUT > STM32_PLLR_MAX))
+#error "STM32_PLLSAI1_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
+#endif
+
+/*
+ * PLLSAI2 enable check.
+ */
+#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \
+ (STM32_ADCSEL == STM32_ADCSEL_PLLSAI2) || \
+ defined(__DOXYGEN__)
+
+#if STM32_PLLCLKIN == 0
+#error "PLLSAI2 activation required but no PLL clock selected"
+#endif
+
+/**
+ * @brief PLLSAI2 activation flag.
+ */
+#define STM32_ACTIVATE_PLLSAI2 TRUE
+#else
+#define STM32_ACTIVATE_PLLSAI2 FALSE
+#endif
+
+/**
+ * @brief STM32_PLLSAI2N field.
+ */
+#if ((STM32_PLLSAI2N_VALUE >= 8) && (STM32_PLLSAI2N_VALUE <= 86)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAI2N (STM32_PLLSAI2N_VALUE << 8)
+#else
+#error "invalid STM32_PLLSAI2N_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAI2P field.
+ */
+#if (STM32_PLLSAI2P_VALUE == 7) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2P (0 << 17)
+
+#elif STM32_PLLSAI2P_VALUE == 17
+#define STM32_PLLSAI2P (1 << 17)
+
+#else
+#error "invalid STM32_PLLSAI2P_VALUE value specified"
+#endif
+
+/**
+ * @brief STM32_PLLSAI2R field.
+ */
+#if (STM32_PLLSAI2R_VALUE == 2) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2R (0 << 25)
+
+#elif STM32_PLLSAI2R_VALUE == 4
+#define STM32_PLLSAI2R (1 << 25)
+
+#elif STM32_PLLSAI2R_VALUE == 6
+#define STM32_PLLSAI2R (2 << 25)
+
+#elif STM32_PLLSAI2R_VALUE == 8
+#define STM32_PLLSAI2R (3 << 25)
+
+#else
+#error "invalid STM32_PLLSAI2R_VALUE value specified"
+#endif
+
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+/**
+ * @brief STM32_PLLSAI2PDIV field. (Only for STM32L496xx/4A6xx)
+ */
+#if ((STM32_PLLSAI2PDIV_VALUE != 1) && (STM32_PLLSAI2PDIV_VALUE <= 31)) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAI2PDIV (STM32_PLLSAI2PDIV_VALUE << 27)
+#else
+#error "invalid STM32_PLLSAI2PDIV_VALUE value specified"
+#endif
+#endif
+
+/**
+ * @brief STM32_PLLSAI2PEN field.
+ */
+#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) || \
+ (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \
+ defined(__DOXYGEN__)
+#define STM32_PLLSAI2PEN (1 << 16)
+#else
+#define STM32_PLLSAI2PEN (0 << 16)
+#endif
+
+/**
+ * @brief STM32_PLLSAI2REN field.
+ */
+#if (STM32_ADCSEL == STM32_ADCSEL_PLLSAI2) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2REN (1 << 24)
+#else
+#define STM32_PLLSAI2REN (0 << 24)
+#endif
+
+/**
+ * @brief PLLSAI2 VCO frequency.
+ */
+#define STM32_PLLSAI2VCO (STM32_PLLCLKIN * STM32_PLLSAI2N_VALUE)
+
+/*
+ * PLLSAI2 VCO frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI2 && \
+ ((STM32_PLLSAI2VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI2VCO > STM32_PLLVCO_MAX))
+#error "STM32_PLLSAI2VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
+#endif
+
+/**
+ * @brief PLLSAI2-P output clock frequency.
+ */
+#if (STM32_PLLSAI2PDIV_VALUE == 0) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2_P_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2P_VALUE)
+#else
+#define STM32_PLLSAI2_P_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2PDIV_VALUE)
+#endif
+
+/**
+ * @brief PLLSAI2-R output clock frequency.
+ */
+#define STM32_PLLSAI2_R_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2R_VALUE)
+
+/*
+ * PLLSAI2-P output frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI2 && \
+ ((STM32_PLLSAI2_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI2_P_CLKOUT > STM32_PLLP_MAX))
+#error "STM32_PLLSAI2_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
+#endif
+
+/*
+ * PLLSAI2-R output frequency range check.
+ */
+#if STM32_ACTIVATE_PLLSAI2 && \
+ ((STM32_PLLSAI2_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI2_R_CLKOUT > STM32_PLLR_MAX))
+#error "STM32_PLLSAI2_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
+#endif
+
+/**
+ * @brief MCO divider clock frequency.
+ */
+#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_MCODIVCLK 0
+
+#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
+#define STM32_MCODIVCLK STM32_SYSCLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_MSI
+#define STM32_MCODIVCLK STM32_MSICLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI16
+#define STM32_MCODIVCLK STM32_HSI16CLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_HSE
+#define STM32_MCODIVCLK STM32_HSECLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_PLL
+#define STM32_MCODIVCLK STM32_PLL_P_CLKOUT
+
+#elif STM32_MCOSEL == STM32_MCOSEL_LSI
+#define STM32_MCODIVCLK STM32_LSICLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_LSE
+#define STM32_MCODIVCLK STM32_LSECLK
+
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI48
+#define STM32_MCODIVCLK STM32_HSI48CLK
+
+#else
+#error "invalid STM32_MCOSEL value specified"
+#endif
+
+/**
+ * @brief MCO output pin clock frequency.
+ */
+#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCOCLK STM32_MCODIVCLK
+
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
+#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
+
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
+#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
+
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
+#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
+
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
+#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
+
+#else
+#error "invalid STM32_MCOPRE value specified"
+#endif
+
+/**
+ * @brief RTC clock frequency.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_RTCCLK 0
+
+#elif STM32_RTCSEL == STM32_RTCSEL_LSE
+#define STM32_RTCCLK STM32_LSECLK
+
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK STM32_LSICLK
+
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK (STM32_HSECLK / 32)
+
+#else
+#error "invalid STM32_RTCSEL value specified"
+#endif
+
+/**
+ * @brief USART1 clock frequency.
+ */
+#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__)
+#define STM32_USART1CLK STM32_PCLK2
+#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
+#define STM32_USART1CLK STM32_SYSCLK
+#elif STM32_USART1SEL == STM32_USART1SEL_HSI16
+#define STM32_USART1CLK STM32_HSI16CLK
+#elif STM32_USART1SEL == STM32_USART1SEL_LSE
+#define STM32_USART1CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART1 clock"
+#endif
+
+/**
+ * @brief USART2 clock frequency.
+ */
+#if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_USART2CLK STM32_PCLK1
+#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
+#define STM32_USART2CLK STM32_SYSCLK
+#elif STM32_USART2SEL == STM32_USART2SEL_HSI16
+#define STM32_USART2CLK STM32_HSI16CLK
+#elif STM32_USART2SEL == STM32_USART2SEL_LSE
+#define STM32_USART2CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART2 clock"
+#endif
+
+/**
+ * @brief USART3 clock frequency.
+ */
+#if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_USART3CLK STM32_PCLK1
+#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
+#define STM32_USART3CLK STM32_SYSCLK
+#elif STM32_USART3SEL == STM32_USART3SEL_HSI16
+#define STM32_USART3CLK STM32_HSI16CLK
+#elif STM32_USART3SEL == STM32_USART3SEL_LSE
+#define STM32_USART3CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART3 clock"
+#endif
+
+/**
+ * @brief UART4 clock frequency.
+ */
+#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_UART4CLK STM32_PCLK1
+#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK
+#define STM32_UART4CLK STM32_SYSCLK
+#elif STM32_UART4SEL == STM32_UART4SEL_HSI16
+#define STM32_UART4CLK STM32_HSI16CLK
+#elif STM32_UART4SEL == STM32_UART4SEL_LSE
+#define STM32_UART4CLK STM32_LSECLK
+#else
+#error "invalid source selected for UART4 clock"
+#endif
+
+/**
+ * @brief UART5 clock frequency.
+ */
+#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_UART5CLK STM32_PCLK1
+#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK
+#define STM32_UART5CLK STM32_SYSCLK
+#elif STM32_UART5SEL == STM32_UART5SEL_HSI16
+#define STM32_UART5CLK STM32_HSI16CLK
+#elif STM32_UART5SEL == STM32_UART5SEL_LSE
+#define STM32_UART5CLK STM32_LSECLK
+#else
+#error "invalid source selected for UART5 clock"
+#endif
+
+/**
+ * @brief LPUART1 clock frequency.
+ */
+#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_LPUART1CLK STM32_PCLK1
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
+#define STM32_LPUART1CLK STM32_SYSCLK
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
+#define STM32_LPUART1CLK STM32_HSI16CLK
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
+#define STM32_LPUART1CLK STM32_LSECLK
+#else
+#error "invalid source selected for LPUART1 clock"
+#endif
+
+/**
+ * @brief I2C1 clock frequency.
+ */
+#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_I2C1CLK STM32_PCLK1
+#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
+#define STM32_I2C1CLK STM32_SYSCLK
+#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16
+#define STM32_I2C1CLK STM32_HSI16CLK
+#else
+#error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief I2C2 clock frequency.
+ */
+#if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_I2C2CLK STM32_PCLK1
+#elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK
+#define STM32_I2C2CLK STM32_SYSCLK
+#elif STM32_I2C2SEL == STM32_I2C2SEL_HSI16
+#define STM32_I2C2CLK STM32_HSI16CLK
+#else
+#error "invalid source selected for I2C2 clock"
+#endif
+
+/**
+ * @brief I2C3 clock frequency.
+ */
+#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_I2C3CLK STM32_PCLK1
+#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK
+#define STM32_I2C3CLK STM32_SYSCLK
+#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI16
+#define STM32_I2C3CLK STM32_HSI16CLK
+#else
+#error "invalid source selected for I2C3 clock"
+#endif
+
+/**
+ * @brief I2C4 clock frequency.
+ */
+#if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_I2C4CLK STM32_PCLK1
+#elif STM32_I2C4SEL == STM32_I2C4SEL_SYSCLK
+#define STM32_I2C4CLK STM32_SYSCLK
+#elif STM32_I2C4SEL == STM32_I2C4SEL_HSI16
+#define STM32_I2C4CLK STM32_HSI16CLK
+#else
+#error "invalid source selected for I2C4 clock"
+#endif
+
+/**
+ * @brief LPTIM1 clock frequency.
+ */
+#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_LPTIM1CLK STM32_PCLK1
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
+#define STM32_LPTIM1CLK STM32_LSICLK
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16
+#define STM32_LPTIM1CLK STM32_HSI16CLK
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
+#define STM32_LPTIM1CLK STM32_LSECLK
+#else
+#error "invalid source selected for LPTIM1 clock"
+#endif
+
+/**
+ * @brief LPTIM2 clock frequency.
+ */
+#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_LPTIM2CLK STM32_PCLK1
+#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI
+#define STM32_LPTIM2CLK STM32_LSICLK
+#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16
+#define STM32_LPTIM2CLK STM32_HSI16CLK
+#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSE
+#define STM32_LPTIM2CLK STM32_LSECLK
+#else
+#error "invalid source selected for LPTIM2 clock"
+#endif
+
+/**
+ * @brief 48MHz clock frequency.
+ */
+#if !STM32_CLOCK_HAS_HSI48 || defined(__DOXYGEN__)
+
+#if (STM32_CLK48SEL == STM32_CLK48SEL_NOCLK) || defined(__DOXYGEN__)
+#define STM32_48CLK 0
+#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1
+#define STM32_48CLK (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
+#elif STM32_CLK48SEL == STM32_CLK48SEL_PLL
+#define STM32_48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
+#elif STM32_CLK48SEL == STM32_CLK48SEL_MSI
+#define STM32_48CLK STM32_MSICLK
+#else
+#error "invalid source selected for 48CLK clock"
+#endif
+
+#else /* STM32_CLOCK_HAS_HSI48 */
+
+#if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__)
+#define STM32_48CLK STM32_HSI48CLK
+#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1
+#define STM32_48CLK (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
+#elif STM32_CLK48SEL == STM32_CLK48SEL_PLL
+#define STM32_48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
+#elif STM32_CLK48SEL == STM32_CLK48SEL_MSI
+#define STM32_48CLK STM32_MSICLK
+#else
+#error "invalid source selected for 48CLK clock"
+#endif
+
+#endif /* STM32_CLOCK_HAS_HSI48 */
+
+/**
+ * @brief SAI1 clock frequency.
+ */
+#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || defined(__DOXYGEN__)
+#define STM32_SAI1CLK STM32_PLLSAI1_P_CLKOUT
+#elif STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2
+#define STM32_SAI1CLK STM32_PLLSAI2_P_CLKOUT
+#elif STM32_SAI1SEL == STM32_SAI1SEL_PLL
+#define STM32_SAI1CLK STM32_PLL_P_CLKOUT
+#elif STM32_SAI1SEL == STM32_SAI1SEL_EXTCLK
+#define STM32_SAI1CLK 0 /* Unknown, would require a board value */
+#elif STM32_SAI1SEL == STM32_SAI1SEL_OFF
+#define STM32_SAI1CLK 0
+#else
+#error "invalid source selected for SAI1 clock"
+#endif
+
+/**
+ * @brief SAI2 clock frequency.
+ */
+#if (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || defined(__DOXYGEN__)
+#define STM32_SAI2CLK STM32_PLLSAI1_P_CLKOUT
+#elif STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2
+#define STM32_SAI2CLK STM32_PLLSAI2_P_CLKOUT
+#elif STM32_SAI2SEL == STM32_SAI2SEL_PLL
+#define STM32_SAI2CLK STM32_PLL_P_CLKOUT
+#elif STM32_SAI2SEL == STM32_SAI2SEL_EXTCLK
+#define STM32_SAI2CLK 0 /* Unknown, would require a board value */
+#elif STM32_SAI2SEL == STM32_SAI2SEL_OFF
+#define STM32_SAI2CLK 0
+#else
+#error "invalid source selected for SAI2 clock"
+#endif
+
+/**
+ * @brief USB clock point.
+ */
+#define STM32_USBCLK STM32_48CLK
+
+/**
+ * @brief RNG clock point.
+ */
+#define STM32_RNGCLK STM32_48CLK
+
+/**
+ * @brief ADC clock frequency.
+ */
+#if (STM32_ADCSEL == STM32_ADCSEL_NOCLK) || defined(__DOXYGEN__)
+#define STM32_ADCCLK 0
+#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI1
+#define STM32_ADCCLK STM32_PLLSAI1_R_CLKOUT
+#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI2
+#define STM32_ADCCLK STM32_PLLSAI2_R_CLKOUT
+#elif STM32_ADCSEL == STM32_ADCSEL_SYSCLK
+#define STM32_ADCCLK STM32_SYSCLK
+#else
+#error "invalid source selected for ADC clock"
+#endif
+
+/**
+ * @brief SWPMI1 clock frequency.
+ */
+#if (STM32_SWPMI1SEL == STM32_SWPMI1SEL_PCLK1) || defined(__DOXYGEN__)
+#define STM32_SWPMI1CLK STM32_PCLK1
+#elif STM32_SWPMI1SEL == STM32_SWPMI1SEL_HSI16
+#define STM32_SWPMI1CLK STM32_HSI16CLK
+#else
+#error "invalid source selected for SWPMI1 clock"
+#endif
+
+/**
+ * @brief DFSDM clock frequency.
+ */
+#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK2) || defined(__DOXYGEN__)
+#define STM32_DFSDMCLK STM32_PCLK2
+#elif STM32_DFSDMSEL == STM32_DFSDMSEL_SYSCLK
+#define STM32_DFSDMCLK STM32_SYSCLK
+#else
+#error "invalid source selected for DFSDM clock"
+#endif
+
+/**
+ * @brief SDMMC frequency.
+ */
+#define STM32_SDMMC1CLK STM32_48CLK
+
+/**
+ * @brief Clock of timers connected to APB1
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief Clock of timers connected to APB2.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief Flash settings.
+ */
+#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS FLASH_ACR_LATENCY_0WS
+
+#elif STM32_HCLK <= STM32_1WS_THRESHOLD
+#define STM32_FLASHBITS FLASH_ACR_LATENCY_1WS
+
+#elif STM32_HCLK <= STM32_2WS_THRESHOLD
+#define STM32_FLASHBITS FLASH_ACR_LATENCY_2WS
+
+#elif STM32_HCLK <= STM32_3WS_THRESHOLD
+#define STM32_FLASHBITS FLASH_ACR_LATENCY_3WS
+
+#else
+#define STM32_FLASHBITS FLASH_ACR_LATENCY_4WS
+#endif
+
+/**
+ * @brief Flash settings for MSI.
+ */
+#if (STM32_MSICLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
+#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_0WS
+
+#elif STM32_MSICLK <= STM32_1WS_THRESHOLD
+#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_1WS
+
+#elif STM32_MSICLK <= STM32_2WS_THRESHOLD
+#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_2WS
+
+#elif STM32_MSICLK <= STM32_3WS_THRESHOLD
+#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_3WS
+
+#else
+#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_4WS
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "cache.h"
+#include "mpu_v7m.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_exti.h"
+#include "stm32_rcc.h"
+#include "stm32_tim.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/platform.mk b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/platform.mk new file mode 100644 index 0000000..5426ea3 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/platform.mk @@ -0,0 +1,49 @@ +# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/stm32_isr.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_efl_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+
+# Configuration files directory
+ifeq ($(HALCONFDIR),)
+ ifeq ($(CONFDIR),)
+ HALCONFDIR = .
+ else
+ HALCONFDIR := $(CONFDIR)
+ endif
+endif
+
+HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
+
+else
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/CRYPv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC)
+ALLINC += $(PLATFORMINC)
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/platform_l432.mk b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/platform_l432.mk new file mode 100644 index 0000000..ba67f99 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/platform_l432.mk @@ -0,0 +1,47 @@ +# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/stm32_isr.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+
+# Configuration files directory
+ifeq ($(HALCONFDIR),)
+ ifeq ($(CONFDIR),)
+ HALCONFDIR = .
+ else
+ HALCONFDIR := $(CONFDIR)
+ endif
+endif
+
+HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
+
+else
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC)
+ALLINC += $(PLATFORMINC)
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/stm32_isr.c b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/stm32_isr.c new file mode 100644 index 0000000..291a6c2 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/stm32_isr.c @@ -0,0 +1,159 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx/stm32_isr.c
+ * @brief STM32L4xx ISR handler code.
+ *
+ * @addtogroup STM32L4xx_ISR
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+#define exti_serve_irq(pr, channel) { \
+ \
+ if ((pr) & (1U << (channel))) { \
+ _pal_isr_code(channel); \
+ } \
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#include "stm32_exti0.inc"
+#include "stm32_exti1.inc"
+#include "stm32_exti2.inc"
+#include "stm32_exti3.inc"
+#include "stm32_exti4.inc"
+#include "stm32_exti5_9.inc"
+#include "stm32_exti10_15.inc"
+#include "stm32_exti16-35_38.inc"
+#include "stm32_exti18.inc"
+#include "stm32_exti19.inc"
+#include "stm32_exti20.inc"
+#include "stm32_exti21_22.inc"
+
+#include "stm32_usart1.inc"
+#include "stm32_usart2.inc"
+#include "stm32_usart3.inc"
+#include "stm32_uart4.inc"
+#include "stm32_uart5.inc"
+#include "stm32_lpuart1.inc"
+
+#include "stm32_tim1_15_16_17.inc"
+#include "stm32_tim2.inc"
+#include "stm32_tim3.inc"
+#include "stm32_tim4.inc"
+#include "stm32_tim5.inc"
+#include "stm32_tim6.inc"
+#include "stm32_tim7.inc"
+#include "stm32_tim8.inc"
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables IRQ sources.
+ *
+ * @notapi
+ */
+void irqInit(void) {
+
+ exti0_irq_init();
+ exti1_irq_init();
+ exti2_irq_init();
+ exti3_irq_init();
+ exti4_irq_init();
+ exti5_9_irq_init();
+ exti10_15_irq_init();
+ exti16_exti35_38_irq_init();
+ exti18_irq_init();
+ exti19_irq_init();
+ exti21_22_irq_init();
+
+ tim1_tim15_tim16_tim17_irq_init();
+ tim2_irq_init();
+ tim3_irq_init();
+ tim4_irq_init();
+ tim5_irq_init();
+ tim6_irq_init();
+ tim7_irq_init();
+ tim8_irq_init();
+
+ usart1_irq_init();
+ usart2_irq_init();
+ usart3_irq_init();
+ uart4_irq_init();
+ uart5_irq_init();
+ lpuart1_irq_init();
+}
+
+/**
+ * @brief Disables IRQ sources.
+ *
+ * @notapi
+ */
+void irqDeinit(void) {
+
+ exti0_irq_deinit();
+ exti1_irq_deinit();
+ exti2_irq_deinit();
+ exti3_irq_deinit();
+ exti4_irq_deinit();
+ exti5_9_irq_deinit();
+ exti10_15_irq_deinit();
+ exti16_exti35_38_irq_deinit();
+ exti18_irq_deinit();
+ exti19_irq_deinit();
+ exti21_22_irq_deinit();
+
+ tim1_tim15_tim16_tim17_irq_deinit();
+ tim2_irq_deinit();
+ tim3_irq_deinit();
+ tim4_irq_deinit();
+ tim5_irq_deinit();
+ tim6_irq_deinit();
+ tim7_irq_deinit();
+ tim8_irq_deinit();
+
+ usart1_irq_deinit();
+ usart2_irq_deinit();
+ usart3_irq_deinit();
+ uart4_irq_deinit();
+ uart5_irq_deinit();
+ lpuart1_irq_deinit();
+}
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/stm32_isr.h b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/stm32_isr.h new file mode 100644 index 0000000..f4a6294 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/stm32_isr.h @@ -0,0 +1,289 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx/stm32_isr.h
+ * @brief STM32L4xx ISR handler header.
+ *
+ * @addtogroup SRM32L4xx_ISR
+ * @{
+ */
+
+#ifndef STM32_ISR_H
+#define STM32_ISR_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name ISRs suppressed in standard drivers
+ * @{
+ */
+#define STM32_TIM1_SUPPRESS_ISR
+#define STM32_TIM2_SUPPRESS_ISR
+#define STM32_TIM3_SUPPRESS_ISR
+#define STM32_TIM4_SUPPRESS_ISR
+#define STM32_TIM5_SUPPRESS_ISR
+#define STM32_TIM6_SUPPRESS_ISR
+#define STM32_TIM7_SUPPRESS_ISR
+#define STM32_TIM8_SUPPRESS_ISR
+#define STM32_TIM15_SUPPRESS_ISR
+#define STM32_TIM16_SUPPRESS_ISR
+#define STM32_TIM17_SUPPRESS_ISR
+
+#define STM32_USART1_SUPPRESS_ISR
+#define STM32_USART2_SUPPRESS_ISR
+#define STM32_USART3_SUPPRESS_ISR
+#define STM32_UART4_SUPPRESS_ISR
+#define STM32_UART5_SUPPRESS_ISR
+#define STM32_LPUART1_SUPPRESS_ISR
+/** @} */
+
+/**
+ * @name ISR names and numbers
+ * @{
+ */
+/*
+ * ADC unit.
+ */
+#define STM32_ADC1_HANDLER Vector88
+#define STM32_ADC2_HANDLER Vector88
+#define STM32_ADC3_HANDLER VectorFC
+
+#define STM32_ADC1_NUMBER 18
+#define STM32_ADC2_NUMBER 18
+#define STM32_ADC3_NUMBER 47
+
+/*
+ * CAN unit.
+ */
+#define STM32_CAN1_TX_HANDLER Vector8C
+#define STM32_CAN1_RX0_HANDLER Vector90
+#define STM32_CAN1_RX1_HANDLER Vector94
+#define STM32_CAN1_SCE_HANDLER Vector98
+#define STM32_CAN2_TX_HANDLER Vector198
+#define STM32_CAN2_RX0_HANDLER Vector19C
+#define STM32_CAN2_RX1_HANDLER Vector1A0
+#define STM32_CAN2_SCE_HANDLER Vector1A4
+
+#define STM32_CAN1_TX_NUMBER 19
+#define STM32_CAN1_RX0_NUMBER 20
+#define STM32_CAN1_RX1_NUMBER 21
+#define STM32_CAN1_SCE_NUMBER 22
+#define STM32_CAN2_TX_NUMBER 86
+#define STM32_CAN2_RX0_NUMBER 87
+#define STM32_CAN2_RX1_NUMBER 88
+#define STM32_CAN2_SCE_NUMBER 89
+
+/*
+ * DMA unit.
+ */
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH6_HANDLER Vector150
+#define STM32_DMA2_CH7_HANDLER Vector154
+
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+#define STM32_DMA2_CH6_NUMBER 68
+#define STM32_DMA2_CH7_NUMBER 69
+
+/*
+ * EXTI unit.
+ */
+#define STM32_EXTI0_HANDLER Vector58
+#define STM32_EXTI1_HANDLER Vector5C
+#define STM32_EXTI2_HANDLER Vector60
+#define STM32_EXTI3_HANDLER Vector64
+#define STM32_EXTI4_HANDLER Vector68
+#define STM32_EXTI5_9_HANDLER Vector9C
+#define STM32_EXTI10_15_HANDLER VectorE0
+#define STM32_EXTI1635_38_HANDLER Vector44 /* PVD PVM1 PVM4 */
+#define STM32_EXTI18_HANDLER VectorE4 /* RTC ALARM */
+#define STM32_EXTI19_HANDLER Vector48 /* RTC TAMP CSS */
+#define STM32_EXTI20_HANDLER Vector4C /* RTC WAKEUP */
+#define STM32_EXTI21_22_HANDLER Vector140 /* COMP1..2 */
+
+#define STM32_EXTI0_NUMBER 6
+#define STM32_EXTI1_NUMBER 7
+#define STM32_EXTI2_NUMBER 8
+#define STM32_EXTI3_NUMBER 9
+#define STM32_EXTI4_NUMBER 10
+#define STM32_EXTI5_9_NUMBER 23
+#define STM32_EXTI10_15_NUMBER 40
+#define STM32_EXTI1635_38_NUMBER 1
+#define STM32_EXTI18_NUMBER 41
+#define STM32_EXTI19_NUMBER 2
+#define STM32_EXTI20_NUMBER 3
+#define STM32_EXTI21_22_NUMBER 64
+
+/*
+ * I2C units.
+ */
+#define STM32_I2C1_EVENT_HANDLER VectorBC
+#define STM32_I2C1_ERROR_HANDLER VectorC0
+#define STM32_I2C2_EVENT_HANDLER VectorC4
+#define STM32_I2C2_ERROR_HANDLER VectorC8
+#define STM32_I2C3_EVENT_HANDLER Vector160
+#define STM32_I2C3_ERROR_HANDLER Vector164
+#define STM32_I2C4_EVENT_HANDLER Vector18C
+#define STM32_I2C4_ERROR_HANDLER Vector190
+
+#define STM32_I2C1_EVENT_NUMBER 31
+#define STM32_I2C1_ERROR_NUMBER 32
+#define STM32_I2C2_EVENT_NUMBER 33
+#define STM32_I2C2_ERROR_NUMBER 34
+#define STM32_I2C3_EVENT_NUMBER 72
+#define STM32_I2C3_ERROR_NUMBER 73
+#define STM32_I2C4_EVENT_NUMBER 83
+#define STM32_I2C4_ERROR_NUMBER 84
+
+/*
+ * QUADSPI unit.
+ */
+#define STM32_QUADSPI1_HANDLER Vector15C
+
+#define STM32_QUADSPI1_NUMBER 71
+
+/*
+ * SDMMC unit.
+ */
+#define STM32_SDMMC1_HANDLER Vector104
+
+#define STM32_SDMMC1_NUMBER 49
+
+/*
+ * TIM units.
+ */
+#define STM32_TIM1_BRK_TIM15_HANDLER VectorA0
+#define STM32_TIM1_UP_TIM16_HANDLER VectorA4
+#define STM32_TIM1_TRGCO_TIM17_HANDLER VectorA8
+#define STM32_TIM1_CC_HANDLER VectorAC
+#define STM32_TIM2_HANDLER VectorB0
+#define STM32_TIM3_HANDLER VectorB4
+#define STM32_TIM4_HANDLER VectorB8
+#define STM32_TIM5_HANDLER Vector108
+#define STM32_TIM6_HANDLER Vector118
+#define STM32_TIM7_HANDLER Vector11C
+#define STM32_TIM8_BRK_HANDLER VectorEC
+#define STM32_TIM8_UP_HANDLER VectorF0
+#define STM32_TIM8_TRGCO_HANDLER VectorF4
+#define STM32_TIM8_CC_HANDLER VectorF8
+
+#define STM32_TIM1_BRK_TIM15_NUMBER 24
+#define STM32_TIM1_UP_TIM16_NUMBER 25
+#define STM32_TIM1_TRGCO_TIM17_NUMBER 26
+#define STM32_TIM1_CC_NUMBER 27
+#define STM32_TIM2_NUMBER 28
+#define STM32_TIM3_NUMBER 29
+#define STM32_TIM4_NUMBER 30
+#define STM32_TIM5_NUMBER 50
+#define STM32_TIM6_NUMBER 54
+#define STM32_TIM7_NUMBER 55
+#define STM32_TIM8_BRK_NUMBER 43
+#define STM32_TIM8_UP_NUMBER 44
+#define STM32_TIM8_TRGCO_NUMBER 45
+#define STM32_TIM8_CC_NUMBER 46
+
+/*
+ * USART/UART units.
+ */
+#define STM32_USART1_HANDLER VectorD4
+#define STM32_USART2_HANDLER VectorD8
+#define STM32_USART3_HANDLER VectorDC
+#define STM32_UART4_HANDLER Vector110
+#define STM32_UART5_HANDLER Vector114
+#define STM32_LPUART1_HANDLER Vector158
+
+#define STM32_USART1_NUMBER 37
+#define STM32_USART2_NUMBER 38
+#define STM32_USART3_NUMBER 39
+#define STM32_UART4_NUMBER 52
+#define STM32_UART5_NUMBER 53
+#define STM32_LPUART1_NUMBER 70
+
+/*
+ * USB/OTG units.
+ */
+#define STM32_USB1_HP_HANDLER Vector14C
+#define STM32_USB1_LP_HANDLER Vector14C
+#define STM32_OTG1_HANDLER Vector14C
+
+#define STM32_USB1_HP_NUMBER 67
+#define STM32_USB1_LP_NUMBER 67
+#define STM32_OTG1_NUMBER 67
+
+/*
+ * DMA2D unit.
+ */
+#define STM32_DMA2D_HANDLER Vector1A8
+
+#define STM32_DMA2D_NUMBER 90
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void irqInit(void);
+ void irqDeinit(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_ISR_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h new file mode 100644 index 0000000..de3acfa --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h @@ -0,0 +1,1279 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx/stm32_rcc.h
+ * @brief RCC helper driver header.
+ * @note This file requires definitions from the ST header file
+ * @p stm32l4xx.h.
+ *
+ * @addtogroup STM32L4xx_RCC
+ * @{
+ */
+#ifndef STM32_RCC_H
+#define STM32_RCC_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Generic RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the clock of one or more peripheral on the APB1 bus (R1).
+ *
+ * @param[in] mask APB1 R1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB1R1(mask, lp) { \
+ RCC->APB1ENR1 |= (mask); \
+ if (lp) \
+ RCC->APB1SMENR1 |= (mask); \
+ else \
+ RCC->APB1SMENR1 &= ~(mask); \
+ (void)RCC->APB1SMENR1; \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB1 bus (R1).
+ *
+ * @param[in] mask APB1 R1 peripherals mask
+ *
+ * @api
+ */
+#define rccDisableAPB1R1(mask) { \
+ RCC->APB1ENR1 &= ~(mask); \
+ RCC->APB1SMENR1 &= ~(mask); \
+ (void)RCC->APB1SMENR1; \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB1 bus (R1).
+ *
+ * @param[in] mask APB1 R1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB1R1(mask) { \
+ RCC->APB1RSTR1 |= (mask); \
+ RCC->APB1RSTR1 &= ~(mask); \
+ (void)RCC->APB1RSTR1; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the APB1 bus (R2).
+ *
+ * @param[in] mask APB1 R2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB1R2(mask, lp) { \
+ RCC->APB1ENR2 |= (mask); \
+ if (lp) \
+ RCC->APB1SMENR2 |= (mask); \
+ else \
+ RCC->APB1SMENR2 &= ~(mask); \
+ (void)RCC->APB1SMENR2; \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB1 bus (R2).
+ *
+ * @param[in] mask APB1 R2 peripherals mask
+ *
+ * @api
+ */
+#define rccDisableAPB1R2(mask) { \
+ RCC->APB1ENR2 &= ~(mask); \
+ RCC->APB1SMENR2 &= ~(mask); \
+ (void)RCC->APB1SMENR2; \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB1 bus (R2).
+ *
+ * @param[in] mask APB1 R2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB1R2(mask) { \
+ RCC->APB1RSTR2 |= (mask); \
+ RCC->APB1RSTR2 &= ~(mask); \
+ (void)RCC->APB1RSTR2; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB2(mask, lp) { \
+ RCC->APB2ENR |= (mask); \
+ if (lp) \
+ RCC->APB2SMENR |= (mask); \
+ else \
+ RCC->APB2SMENR &= ~(mask); \
+ (void)RCC->APB2SMENR; \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ *
+ * @api
+ */
+#define rccDisableAPB2(mask) { \
+ RCC->APB2ENR &= ~(mask); \
+ RCC->APB2SMENR &= ~(mask); \
+ (void)RCC->APB2SMENR; \
+}
+
+/**
+ * @brief Resets one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask APB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB2(mask) { \
+ RCC->APB2RSTR |= (mask); \
+ RCC->APB2RSTR &= ~(mask); \
+ (void)RCC->APB2RSTR; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB1 bus.
+ *
+ * @param[in] mask AHB1 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB1(mask, lp) { \
+ RCC->AHB1ENR |= (mask); \
+ if (lp) \
+ RCC->AHB1SMENR |= (mask); \
+ else \
+ RCC->AHB1SMENR &= ~(mask); \
+ (void)RCC->AHB1SMENR; \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB1 bus.
+ *
+ * @param[in] mask AHB1 peripherals mask
+ *
+ * @api
+ */
+#define rccDisableAHB1(mask) { \
+ RCC->AHB1ENR &= ~(mask); \
+ RCC->AHB1SMENR &= ~(mask); \
+ (void)RCC->AHB1SMENR; \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB1 bus.
+ *
+ * @param[in] mask AHB1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB1(mask) { \
+ RCC->AHB1RSTR |= (mask); \
+ RCC->AHB1RSTR &= ~(mask); \
+ (void)RCC->AHB1RSTR; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB2 bus.
+ *
+ * @param[in] mask AHB2 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB2(mask, lp) { \
+ RCC->AHB2ENR |= (mask); \
+ if (lp) \
+ RCC->AHB2SMENR |= (mask); \
+ else \
+ RCC->AHB2SMENR &= ~(mask); \
+ (void)RCC->AHB2SMENR; \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB2 bus.
+ *
+ * @param[in] mask AHB2 peripherals mask
+ *
+ * @api
+ */
+#define rccDisableAHB2(mask) { \
+ RCC->AHB2ENR &= ~(mask); \
+ RCC->AHB2SMENR &= ~(mask); \
+ (void)RCC->AHB2SMENR; \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB2 bus.
+ *
+ * @param[in] mask AHB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB2(mask) { \
+ RCC->AHB2RSTR |= (mask); \
+ RCC->AHB2RSTR &= ~(mask); \
+ (void)RCC->AHB2RSTR; \
+}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.
+ *
+ * @param[in] mask AHB3 peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB3(mask, lp) { \
+ RCC->AHB3ENR |= (mask); \
+ if (lp) \
+ RCC->AHB3SMENR |= (mask); \
+ else \
+ RCC->AHB3SMENR &= ~(mask); \
+ (void)RCC->AHB3SMENR; \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
+ *
+ * @param[in] mask AHB3 peripherals mask
+ *
+ * @api
+ */
+#define rccDisableAHB3(mask) { \
+ RCC->AHB3ENR &= ~(mask); \
+ RCC->AHB3SMENR &= ~(mask); \
+ (void)RCC->AHB3SMENR; \
+}
+
+/**
+ * @brief Resets one or more peripheral on the AHB3 (FSMC) bus.
+ *
+ * @param[in] mask AHB3 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB3(mask) { \
+ RCC->AHB3RSTR |= (mask); \
+ RCC->AHB3RSTR &= ~(mask); \
+ (void)RCC->AHB3RSTR; \
+}
+/** @} */
+
+/**
+ * @name ADC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the ADC1/ADC2/ADC3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC123(lp) rccEnableAHB2(RCC_AHB2ENR_ADCEN, lp)
+
+/**
+ * @brief Disables the ADC1/ADC2/ADC3 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableADC123() rccDisableAHB2(RCC_AHB2ENR_ADCEN)
+
+/**
+ * @brief Resets the ADC1/ADC2/ADC3 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC123() rccResetAHB2(RCC_AHB2RSTR_ADCRST)
+/** @} */
+
+/**
+ * @name DAC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DAC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDAC1(lp) rccEnableAPB1R1(RCC_APB1ENR1_DAC1EN, lp)
+
+/**
+ * @brief Disables the DAC1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableDAC1() rccDisableAPB1R1(RCC_APB1ENR1_DAC1EN)
+
+/**
+ * @brief Resets the DAC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDAC1() rccResetAPB1R1(RCC_APB1RSTR1_DAC1RST)
+/** @} */
+
+/**
+ * @name DMA peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DMA1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
+
+/**
+ * @brief Disables the DMA1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
+
+/**
+ * @brief Resets the DMA1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
+
+/**
+ * @brief Enables the DMA2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
+
+/**
+ * @brief Disables the DMA2 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
+
+/**
+ * @brief Resets the DMA2 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
+/** @} */
+
+/**
+ * @name PWR interface specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the PWR interface clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnablePWRInterface(lp) rccEnableAPB1R1(RCC_APB1ENR1_PWREN, lp)
+
+/**
+ * @brief Disables PWR interface clock.
+ *
+ * @api
+ */
+#define rccDisablePWRInterface() rccDisableAPB1R1(RCC_APB1ENR1_PWREN)
+
+/**
+ * @brief Resets the PWR interface.
+ *
+ * @api
+ */
+#define rccResetPWRInterface() rccResetAPB1R1(RCC_APB1RSTR1_PWRRST)
+/** @} */
+
+/**
+ * @name CAN peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CAN1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN1(lp) rccEnableAPB1R1(RCC_APB1ENR1_CAN1EN, lp)
+
+/**
+ * @brief Disables the CAN1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableCAN1() rccDisableAPB1R1(RCC_APB1ENR1_CAN1EN)
+
+/**
+ * @brief Resets the CAN1 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN1() rccResetAPB1R1(RCC_APB1RSTR1_CAN1RST)
+
+/**
+ * @brief Enables the CAN2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN2(lp) rccEnableAPB1R1(RCC_APB1ENR1_CAN2EN, lp)
+
+/**
+ * @brief Disables the CAN2 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableCAN2() rccDisableAPB1R1(RCC_APB1ENR1_CAN2EN)
+
+/**
+ * @brief Resets the CAN2 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN2() rccResetAPB1R1(RCC_APB1RSTR1_CAN2RST)
+/** @} */
+
+/**
+ * @name I2C peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the I2C1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C1(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C1EN, lp)
+
+/**
+ * @brief Disables the I2C1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableI2C1() rccDisableAPB1R1(RCC_APB1ENR1_I2C1EN)
+
+/**
+ * @brief Resets the I2C1 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C1() rccResetAPB1R1(RCC_APB1RSTR1_I2C1RST)
+
+/**
+ * @brief Enables the I2C2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C2(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C2EN, lp)
+
+/**
+ * @brief Disables the I2C2 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableI2C2() rccDisableAPB1R1(RCC_APB1ENR1_I2C2EN)
+
+/**
+ * @brief Resets the I2C2 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C2() rccResetAPB1R1(RCC_APB1RSTR1_I2C2RST)
+
+/**
+ * @brief Enables the I2C3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C3(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C3EN, lp)
+
+/**
+ * @brief Disables the I2C3 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableI2C3() rccDisableAPB1R1(RCC_APB1ENR1_I2C3EN)
+
+/**
+ * @brief Resets the I2C3 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C3() rccResetAPB1R1(RCC_APB1RSTR1_I2C3RST)
+
+/**
+ * @brief Enables the I2C4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C4(lp) rccEnableAPB1R2(RCC_APB1ENR2_I2C4EN, lp)
+
+/**
+ * @brief Disables the I2C4 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableI2C4() rccDisableAPB1R1(RCC_APB1ENR2_I2C4EN)
+
+/**
+ * @brief Resets the I2C4 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C4() rccResetAPB1R1(RCC_APB1RSTR2_I2C4RST)
+/** @} */
+
+/**
+ * @name OTG peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
+
+/**
+ * @brief Disables the OTG_FS peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableOTG_FS() rccDisableAHB2(RCC_AHB2ENR_OTGFSEN)
+
+/**
+ * @brief Resets the OTG_FS peripheral.
+ *
+ * @api
+ */
+#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
+/** @} */
+
+/**
+ * @name QUADSPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the QUADSPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
+
+/**
+ * @brief Disables the QUADSPI1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN)
+
+/**
+ * @brief Resets the QUADSPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
+/** @} */
+
+/**
+ * @name RNG peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the RNG peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableRNG(lp) rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp)
+
+/**
+ * @brief Disables the RNG peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableRNG() rccDisableAHB2(RCC_AHB2ENR_RNGEN)
+
+/**
+ * @brief Resets the RNG peripheral.
+ *
+ * @api
+ */
+#define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST)
+/** @} */
+
+/**
+ * @name SDMMC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SDMMC1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSDMMC1(lp) rccEnableAPB2(RCC_APB2ENR_SDMMC1EN, lp)
+
+/**
+ * @brief Disables the SDMMC1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableSDMMC1() rccDisableAPB2(RCC_APB2ENR_SDMMC1EN)
+
+/**
+ * @brief Resets the SDMMC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSDMMC1() rccResetAPB2(RCC_APB2RSTR_SDMMC1RST)
+/** @} */
+
+/**
+ * @name SPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the SPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief Disables the SPI1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
+
+/**
+ * @brief Resets the SPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
+
+/**
+ * @brief Enables the SPI2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI2(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI2EN, lp)
+
+/**
+ * @brief Disables the SPI2 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableSPI2() rccDisableAPB1R1(RCC_APB1ENR1_SPI2EN)
+
+/**
+ * @brief Resets the SPI2 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI2() rccResetAPB1R1(RCC_APB1RSTR1_SPI2RST)
+
+/**
+ * @brief Enables the SPI3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI3(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI3EN, lp)
+
+/**
+ * @brief Disables the SPI3 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableSPI3() rccDisableAPB1R1(RCC_APB1ENR1_SPI3EN)
+
+/**
+ * @brief Resets the SPI3 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI3() rccResetAPB1R1(RCC_APB1RSTR1_SPI3RST)
+/** @} */
+
+/**
+ * @name TIM peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the TIM1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief Disables the TIM1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
+
+/**
+ * @brief Resets the TIM1 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
+
+/**
+ * @brief Enables the TIM2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM2(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM2EN, lp)
+
+/**
+ * @brief Disables the TIM2 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM2() rccDisableAPB1R1(RCC_APB1ENR1_TIM2EN)
+
+/**
+ * @brief Resets the TIM2 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM2() rccResetAPB1R1(RCC_APB1RSTR1_TIM2RST)
+
+/**
+ * @brief Enables the TIM3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM3(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM3EN, lp)
+
+/**
+ * @brief Disables the TIM3 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM3() rccDisableAPB1R1(RCC_APB1ENR1_TIM3EN)
+
+/**
+ * @brief Resets the TIM3 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM3() rccResetAPB1R1(RCC_APB1RSTR1_TIM3RST)
+
+/**
+ * @brief Enables the TIM4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM4(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM4EN, lp)
+
+/**
+ * @brief Disables the TIM4 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM4() rccDisableAPB1R1(RCC_APB1ENR1_TIM4EN)
+
+/**
+ * @brief Resets the TIM4 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM4() rccResetAPB1R1(RCC_APB1RSTR1_TIM4RST)
+
+/**
+ * @brief Enables the TIM5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM5(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM5EN, lp)
+
+/**
+ * @brief Disables the TIM5 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM5() rccDisableAPB1R1(RCC_APB1ENR1_TIM5EN)
+
+/**
+ * @brief Resets the TIM5 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM5() rccResetAPB1R1(RCC_APB1RSTR1_TIM5RST)
+
+/**
+ * @brief Enables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM6(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM6EN, lp)
+
+/**
+ * @brief Disables the TIM6 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM6() rccDisableAPB1R1(RCC_APB1ENR1_TIM6EN)
+
+/**
+ * @brief Resets the TIM6 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM6() rccResetAPB1R1(RCC_APB1RSTR1_TIM6RST)
+
+/**
+ * @brief Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM7EN, lp)
+
+/**
+ * @brief Disables the TIM7 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM7() rccDisableAPB1R1(RCC_APB1ENR1_TIM7EN)
+
+/**
+ * @brief Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1R1(RCC_APB1RSTR1_TIM7RST)
+
+/**
+ * @brief Enables the TIM8 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief Disables the TIM8 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM8() rccDisableAPB2(RCC_APB2ENR_TIM8EN)
+
+/**
+ * @brief Resets the TIM8 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
+
+/**
+ * @brief Enables the TIM15 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Disables the TIM15 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM15() rccDisableAPB2(RCC_APB2ENR_TIM15EN)
+
+/**
+ * @brief Resets the TIM15 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
+
+/**
+ * @brief Enables the TIM16 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Disables the TIM16 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
+
+/**
+ * @brief Resets the TIM16 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
+
+/**
+ * @brief Enables the TIM17 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Disables the TIM17 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
+
+/**
+ * @brief Resets the TIM17 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
+/** @} */
+
+/**
+ * @name USART/UART peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief Disables the USART1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
+
+/**
+ * @brief Enables the USART2 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART2(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART2EN, lp)
+
+/**
+ * @brief Disables the USART2 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUSART2() rccDisableAPB1R1(RCC_APB1ENR1_USART2EN)
+
+/**
+ * @brief Resets the USART2 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART2() rccResetAPB1R1(RCC_APB1RSTR1_USART2RST)
+
+/**
+ * @brief Enables the USART3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART3(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART3EN, lp)
+
+/**
+ * @brief Disables the USART3 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUSART3() rccDisableAPB1R1(RCC_APB1ENR1_USART3EN)
+
+/**
+ * @brief Resets the USART3 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART3() rccResetAPB1R1(RCC_APB1RSTR1_USART3RST)
+
+/**
+ * @brief Enables the UART4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART4(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART4EN, lp)
+
+/**
+ * @brief Disables the UART4 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUART4() rccDisableAPB1R1(RCC_APB1ENR1_UART4EN)
+
+/**
+ * @brief Resets the UART4 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART4() rccResetAPB1R1(RCC_APB1RSTR1_UART4RST)
+
+/**
+ * @brief Enables the UART5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART5(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART5EN, lp)
+
+/**
+ * @brief Disables the UART5 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUART5() rccDisableAPB1R1(RCC_APB1ENR1_UART5EN)
+
+/**
+ * @brief Resets the UART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1R1(RCC_APB1RSTR1_UART5RST)
+
+/**
+ * @brief Enables the LPUART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableLPUART1(lp) rccEnableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp)
+
+/**
+ * @brief Disables the LPUART1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableLPUART1() rccDisableAPB1R2(RCC_APB1ENR2_LPUART1EN)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetLPUART1() rccResetAPB1R2(RCC_APB1RSTR2_LPUART1RST)
+/** @} */
+
+/**
+ * @name USB peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSB(lp) rccEnableAPB1R1(RCC_APB1ENR1_USBFSEN, lp)
+
+/**
+ * @brief Disables the USB peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUSB() rccDisableAPB1R1(RCC_APB1ENR1_USBFSEN)
+
+/**
+ * @brief Resets the USB peripheral.
+ *
+ * @api
+ */
+#define rccResetUSB() rccResetAPB1R1(RCC_APB1RSTR1_USBFSRST)
+/** @} */
+
+/**
+ * @name CRC peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CRC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
+
+/**
+ * @brief Disables the CRC peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
+
+/**
+ * @brief Resets the CRC peripheral.
+ *
+ * @api
+ */
+#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
+/** @} */
+
+/**
+ * @name FSMC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the FSMC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp)
+
+/**
+ * @brief Disables the FSMC peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableFSMC() rccDisableAHB3(RCC_AHB3ENR_FMCEN)
+
+/**
+ * @brief Resets the FSMC peripheral.
+ *
+ * @api
+ */
+#define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_RCC_H */
+
+/** @} */
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/stm32_registry.h new file mode 100644 index 0000000..fdec353 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32L4xx/stm32_registry.h @@ -0,0 +1,1347 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx/stm32_registry.h
+ * @brief STM32L4xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef STM32_REGISTRY_H
+#define STM32_REGISTRY_H
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name STM32L4xx capabilities
+ * @{
+ */
+
+/*===========================================================================*/
+/* Common. */
+/*===========================================================================*/
+
+/* RNG attributes.*/
+#define STM32_HAS_RNG1 TRUE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_STORAGE_SIZE 128
+#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
+#define STM32_RTC_WKUP_HANDLER Vector4C
+#define STM32_RTC_ALARM_HANDLER VectorE4
+#define STM32_RTC_TAMP_STAMP_NUMBER 2
+#define STM32_RTC_WKUP_NUMBER 3
+#define STM32_RTC_ALARM_NUMBER 41
+#define STM32_RTC_ALARM_EXTI 18
+#define STM32_RTC_TAMP_STAMP_EXTI 19
+#define STM32_RTC_WKUP_EXTI 20
+#define STM32_RTC_IRQ_ENABLE() do { \
+ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
+ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \
+ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
+} while (false)
+
+#if defined(STM32L486xx) || defined(STM32L4A6xx) || \
+ defined(__DOXYGEN__)
+#define STM32_HAS_HASH1 TRUE
+#define STM32_HAS_CRYP1 TRUE
+#else
+#define STM32_HAS_HASH1 FALSE
+#define STM32_HAS_CRYP1 FALSE
+#endif
+
+/*===========================================================================*/
+/* STM32L432xx, STM32L433xx. */
+/*===========================================================================*/
+
+#if defined(STM32L432xx) || defined(STM32L433xx) || defined(__DOXYGEN__)
+
+/* Clock attributes.*/
+#define STM32_CLOCK_HAS_HSI48 TRUE
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_CAN_MAX_FILTERS 14
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_DAC1_CH1_DMA_CHN 0x00003600
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)|\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_DAC1_CH2_DMA_CHN 0x00035000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_DMAMUX FALSE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 7
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 40
+#define STM32_EXTI_IMR1_MASK 0xFF820000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
+
+/* Flash attributes.*/
+#define STM32_FLASH_NUMBER_OF_BANKS 1
+#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
+#define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/
+#endif
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD FALSE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
+ RCC_AHB2ENR_GPIOBEN | \
+ RCC_AHB2ENR_GPIOCEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_I2C1_RX_DMA_CHN 0x03500000
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_I2C1_TX_DMA_CHN 0x05300000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_QUADSPI1_DMA_CHN 0x03050000
+
+/* SDMMC attributes.*/
+#define STM32_HAS_SDMMC1 FALSE
+#define STM32_HAS_SDMMC2 FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI1_RX_DMA_CHN 0x00000410
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI1_TX_DMA_CHN 0x00004100
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S FALSE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_SPI3_RX_DMA_CHN 0x00000003
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 2
+
+#define STM32_HAS_TIM3 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART1_RX_DMA_CHN 0x02020000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_USART1_TX_DMA_CHN 0x00202000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00200000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x02000000
+
+#define STM32_HAS_LPUART1 TRUE
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 1024
+#define STM32_USB_HAS_BCDR TRUE
+
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+#endif /* defined(STM32L432xx) */
+
+/*===========================================================================*/
+/* STM32L443xx. */
+/*===========================================================================*/
+
+#if defined(STM32L443xx) || defined(__DOXYGEN__)
+
+/* Clock attributes.*/
+#define STM32_CLOCK_HAS_HSI48 TRUE
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_CAN_MAX_FILTERS 14
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_DAC1_CH1_DMA_CHN 0x00003600
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)|\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_DAC1_CH2_DMA_CHN 0x00035000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_DMAMUX FALSE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 7
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 40
+#define STM32_EXTI_IMR1_MASK 0xFF820000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
+
+/* Flash attributes.*/
+#define STM32_FLASH_NUMBER_OF_BANKS 1
+#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
+#define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/
+#endif
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD FALSE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
+ RCC_AHB2ENR_GPIOBEN | \
+ RCC_AHB2ENR_GPIOCEN | \
+ RCC_AHB2ENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_I2C1_RX_DMA_CHN 0x03500000
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_I2C1_TX_DMA_CHN 0x05300000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C2_RX_DMA_CHN 0x00030000
+#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C2_TX_DMA_CHN 0x00003000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_QUADSPI1_DMA_CHN 0x03050000
+
+/* SDMMC attributes.*/
+#define STM32_HAS_SDMMC1 TRUE
+#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SDC_SDMMC1_DMA_CHN 0x00077000
+
+#define STM32_HAS_SDMMC2 FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI1_RX_DMA_CHN 0x00000410
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI1_TX_DMA_CHN 0x00004100
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S FALSE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_SPI2_RX_DMA_CHN 0x00001000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_SPI2_TX_DMA_CHN 0x00010000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S FALSE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_SPI3_RX_DMA_CHN 0x00000003
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 2
+
+#define STM32_HAS_TIM3 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART1_RX_DMA_CHN 0x02020000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_USART1_TX_DMA_CHN 0x00202000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00200000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x02000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_USART3_RX_DMA_CHN 0x00000200
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_USART3_TX_DMA_CHN 0x00000020
+
+#define STM32_HAS_LPUART1 TRUE
+
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 1024
+#define STM32_USB_HAS_BCDR TRUE
+
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+#endif /* defined(STM32L443xx) */
+
+/*===========================================================================*/
+/* STM32L452xx. */
+/*===========================================================================*/
+
+#if defined(STM32L452xx) || defined(__DOXYGEN__)
+
+/* Clock attributes.*/
+#define STM32_CLOCK_HAS_HSI48 TRUE
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_CAN_MAX_FILTERS 14
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_DAC1_CH1_DMA_CHN 0x00003600
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_DMAMUX FALSE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 7
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 40
+#define STM32_EXTI_IMR1_MASK 0xFF820000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
+ RCC_AHB2ENR_GPIOBEN | \
+ RCC_AHB2ENR_GPIOCEN | \
+ RCC_AHB2ENR_GPIODEN | \
+ RCC_AHB2ENR_GPIOEEN | \
+ RCC_AHB2ENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_I2C1_RX_DMA_CHN 0x03500000
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_I2C1_TX_DMA_CHN 0x05300000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C2_RX_DMA_CHN 0x00030000
+#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C2_TX_DMA_CHN 0x00003000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_I2C4 TRUE
+#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_I2C4_RX_DMA_CHN 0x00000000
+#define STM32_I2C4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_I2C4_TX_DMA_CHN 0x00000000
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_QUADSPI1_DMA_CHN 0x03050000
+
+/* SDMMC attributes.*/
+#define STM32_HAS_SDMMC1 TRUE
+#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SDC_SDMMC1_DMA_CHN 0x00077000
+
+#define STM32_HAS_SDMMC2 FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI1_RX_DMA_CHN 0x00000410
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI1_TX_DMA_CHN 0x00004100
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S FALSE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_SPI2_RX_DMA_CHN 0x00001000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_SPI2_TX_DMA_CHN 0x00010000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S FALSE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_SPI3_RX_DMA_CHN 0x00000003
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 2
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM17 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART1_RX_DMA_CHN 0x02020000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_USART1_TX_DMA_CHN 0x00202000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00200000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x02000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_USART3_RX_DMA_CHN 0x00000200
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_USART3_TX_DMA_CHN 0x00000020
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART4_RX_DMA_CHN 0x00020000
+#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_UART4_TX_DMA_CHN 0x00000200
+
+#define STM32_HAS_LPUART1 TRUE
+
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 1024
+#define STM32_USB_HAS_BCDR TRUE
+
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+#endif /* defined(STM32L452xx) */
+
+/*===========================================================================*/
+/* STM32L476xx, STM32L486xx. */
+/*===========================================================================*/
+
+#if defined(STM32L476xx) || defined(STM32L486xx)
+
+/* Clock attributes.*/
+#define STM32_CLOCK_HAS_HSI48 FALSE
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_ADC3_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_CAN_MAX_FILTERS 14
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_DAC1_CH1_DMA_CHN 0x00003600
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)|\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_DAC1_CH2_DMA_CHN 0x00035000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_DMAMUX FALSE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 7
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 40
+#define STM32_EXTI_IMR1_MASK 0xFF820000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
+
+/* Flash attributes.*/
+#define STM32_FLASH_NUMBER_OF_BANKS 2
+#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
+#define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/
+#endif
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
+ RCC_AHB2ENR_GPIOBEN | \
+ RCC_AHB2ENR_GPIOCEN | \
+ RCC_AHB2ENR_GPIODEN | \
+ RCC_AHB2ENR_GPIOEEN | \
+ RCC_AHB2ENR_GPIOFEN | \
+ RCC_AHB2ENR_GPIOGEN | \
+ RCC_AHB2ENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_I2C1_RX_DMA_CHN 0x03500000
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_I2C1_TX_DMA_CHN 0x05300000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C2_RX_DMA_CHN 0x00030000
+#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C2_TX_DMA_CHN 0x00003000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_I2C4 FALSE
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_QUADSPI1_DMA_CHN 0x03050000
+
+/* SDMMC attributes.*/
+#define STM32_HAS_SDMMC1 TRUE
+#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SDC_SDMMC1_DMA_CHN 0x00077000
+
+#define STM32_HAS_SDMMC2 FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI1_RX_DMA_CHN 0x00000410
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI1_TX_DMA_CHN 0x00004100
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S FALSE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_SPI2_RX_DMA_CHN 0x00001000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_SPI2_TX_DMA_CHN 0x00010000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S FALSE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_SPI3_RX_DMA_CHN 0x00000003
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 2
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 2
+
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART1_RX_DMA_CHN 0x02020000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_USART1_TX_DMA_CHN 0x00202000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00200000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x02000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_USART3_RX_DMA_CHN 0x00000200
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_USART3_TX_DMA_CHN 0x00000020
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5)
+#define STM32_UART4_RX_DMA_CHN 0x00020000
+#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 3)
+#define STM32_UART4_TX_DMA_CHN 0x00000200
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
+#define STM32_UART5_RX_DMA_CHN 0x00000020
+#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
+#define STM32_UART5_TX_DMA_CHN 0x00000002
+
+#define STM32_HAS_LPUART1 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_SEQUENCE_WORKAROUND
+#define STM32_OTG_STEPPING 2
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 5
+
+#define STM32_HAS_OTG2 FALSE
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+#endif /* defined(STM32L476xx) */
+
+/*===========================================================================*/
+/* STM32L496xx, STM32L4A6xx. */
+/*===========================================================================*/
+
+#if defined(STM32L496xx) || defined(STM32L4A6xx)
+
+/* Clock attributes.*/
+#define STM32_CLOCK_HAS_HSI48 FALSE
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC2 TRUE
+#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_ADC2_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC3 TRUE
+#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_ADC3_DMA_CHN 0x00000000
+
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_CAN_MAX_FILTERS 14
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 TRUE
+#define STM32_HAS_CAN3 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_DAC1_CH1_DMA_CHN 0x00003600
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)|\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_DAC1_CH2_DMA_CHN 0x00035000
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA_SUPPORTS_DMAMUX FALSE
+#define STM32_DMA_SUPPORTS_CSELR TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA2_NUM_CHANNELS 7
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 40
+#define STM32_EXTI_IMR1_MASK 0xFF820000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
+
+/* Flash attributes.*/
+#define STM32_FLASH_NUMBER_OF_BANKS 2
+#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
+#define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/
+#endif
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
+ RCC_AHB2ENR_GPIOBEN | \
+ RCC_AHB2ENR_GPIOCEN | \
+ RCC_AHB2ENR_GPIODEN | \
+ RCC_AHB2ENR_GPIOEEN | \
+ RCC_AHB2ENR_GPIOFEN | \
+ RCC_AHB2ENR_GPIOGEN | \
+ RCC_AHB2ENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_I2C1_RX_DMA_CHN 0x03500000
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_I2C1_TX_DMA_CHN 0x05300000
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C2_RX_DMA_CHN 0x00030000
+#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C2_TX_DMA_CHN 0x00003000
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_I2C4 TRUE
+#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_I2C4_RX_DMA_CHN 0x00000000
+#define STM32_I2C4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_I2C4_TX_DMA_CHN 0x00000000
+
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_QUADSPI1_DMA_CHN 0x03050000
+
+/* SDMMC attributes.*/
+#define STM32_HAS_SDMMC1 TRUE
+#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_SDC_SDMMC1_DMA_CHN 0x00077000
+
+#define STM32_HAS_SDMMC2 FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_SPI1_RX_DMA_CHN 0x00000410
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4))
+#define STM32_SPI1_TX_DMA_CHN 0x00004100
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S FALSE
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_SPI2_RX_DMA_CHN 0x00001000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_SPI2_TX_DMA_CHN 0x00010000
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S FALSE
+#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
+#define STM32_SPI3_RX_DMA_CHN 0x00000003
+#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
+#define STM32_SPI3_TX_DMA_CHN 0x00000030
+
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM5 TRUE
+#define STM32_TIM5_IS_32BITS TRUE
+#define STM32_TIM5_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_USART1_RX_DMA_CHN 0x02020000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_USART1_TX_DMA_CHN 0x00202000
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00200000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x02000000
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_USART3_RX_DMA_CHN 0x00000200
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_USART3_TX_DMA_CHN 0x00000020
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5)
+#define STM32_UART4_RX_DMA_CHN 0x00020000
+#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 3)
+#define STM32_UART4_TX_DMA_CHN 0x00000200
+
+#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
+#define STM32_UART5_RX_DMA_CHN 0x00000020
+#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
+#define STM32_UART5_TX_DMA_CHN 0x00000002
+
+#define STM32_HAS_LPUART1 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
+/* USB attributes.*/
+#define STM32_OTG_STEPPING 2
+#define STM32_HAS_OTG1 TRUE
+#define STM32_OTG1_ENDPOINTS 5
+
+#define STM32_HAS_OTG2 FALSE
+#define STM32_HAS_USB FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D TRUE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+
+#endif /* defined(STM32L496xx) */
+
+/** @} */
+
+#endif /* STM32_REGISTRY_H */
+
+/** @} */
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