From 48026bb824fd2d9cfb00ecd040db6ef3a416bae9 Mon Sep 17 00:00:00 2001 From: Clyne Sullivan Date: Fri, 22 Jan 2021 21:43:36 -0500 Subject: upload initial port --- ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore.c | 54 ++ ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore.h | 208 ++++++ .../os/common/ports/ARMCMx/chcore_timer.h | 133 ++++ ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v6m.c | 155 ++++ ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v6m.h | 466 ++++++++++++ ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v7m.c | 391 ++++++++++ ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v7m.h | 790 +++++++++++++++++++++ .../ports/ARMCMx/compilers/GCC/chcoreasm_v6m.S | 154 ++++ .../ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S | 242 +++++++ .../os/common/ports/ARMCMx/compilers/GCC/chtypes.h | 97 +++ .../ports/ARMCMx/compilers/GCC/mk/port_v6m.mk | 13 + .../ports/ARMCMx/compilers/GCC/mk/port_v7m.mk | 13 + .../ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s | 156 ++++ .../ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s | 169 +++++ .../os/common/ports/ARMCMx/compilers/IAR/chtypes.h | 115 +++ .../ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s | 152 ++++ .../ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s | 167 +++++ .../common/ports/ARMCMx/compilers/RVCT/chtypes.h | 97 +++ ChibiOS_20.3.2/os/common/ports/ARMCMx/mpu.h | 228 ++++++ 19 files changed, 3800 insertions(+) create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore.c create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore.h create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_timer.h create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v6m.c create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v6m.h create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v7m.c create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v7m.h create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.S create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/chtypes.h create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/IAR/chtypes.h create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/RVCT/chtypes.h create mode 100644 ChibiOS_20.3.2/os/common/ports/ARMCMx/mpu.h (limited to 'ChibiOS_20.3.2/os/common/ports/ARMCMx') diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore.c b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore.c new file mode 100644 index 0000000..06a0ca8 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore.c @@ -0,0 +1,54 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARMCMx/chcore.c + * @brief ARM Cortex-Mx port code. + * + * @addtogroup ARMCMx_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore.h b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore.h new file mode 100644 index 0000000..b6873ee --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore.h @@ -0,0 +1,208 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARMCMx/chcore.h + * @brief ARM Cortex-Mx port macros and structures. + * + * @addtogroup ARMCMx_CORE + * @{ + */ + +#ifndef CHCORE_H +#define CHCORE_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @name Architecture and Compiler + * @{ + */ +/** + * @brief Macro defining a generic ARM architecture. + */ +#define PORT_ARCHITECTURE_ARM + +/* The following code is not processed when the file is included from an + asm module because those intrinsic macros are not necessarily defined + by the assembler too.*/ +#if !defined(_FROM_ASM_) + +/** + * @brief Compiler name and version. + */ +#if defined(__GNUC__) || defined(__DOXYGEN__) +#define PORT_COMPILER_NAME "GCC " __VERSION__ + +#elif defined(__ICCARM__) +#define PORT_COMPILER_NAME "IAR" + +#elif defined(__CC_ARM) +#define PORT_COMPILER_NAME "RVCT" + +#else +#error "unsupported compiler" +#endif + +#endif /* !defined(_FROM_ASM_) */ + +/** @} */ + +/* Inclusion of the Cortex-Mx implementation specific parameters.*/ +#include "cmparams.h" + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an alternative timer implementation. + * @details Usually the port uses a timer interface defined in the file + * @p chcore_timer.h, if this option is enabled then the file + * @p chcore_timer_alt.h is included instead. + */ +#if !defined(PORT_USE_ALT_TIMER) +#define PORT_USE_ALT_TIMER FALSE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/** + * @brief Type of stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + +/* The following declarations are there just for Doxygen documentation, the + real declarations are inside the sub-headers being specific for the + sub-architectures.*/ +#if defined(__DOXYGEN__) +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note It is implemented to match the Cortex-Mx exception context. + */ +struct port_extctx {}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switch. + */ +struct port_intctx {}; + +/** + * @brief Platform dependent part of the @p thread_t structure. + * @details In this port the structure just holds a pointer to the + * @p port_intctx structure representing the stack pointer + * at context switch time. + */ +struct port_context {}; +#endif /* defined(__DOXYGEN__) */ + +#endif /* !defined(_FROM_ASM_) */ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/** + * @brief Total priority levels. + */ +#define CORTEX_PRIORITY_LEVELS (1U << CORTEX_PRIORITY_BITS) + +/** + * @brief Minimum priority level. + * @details This minimum priority level is calculated from the number of + * priority bits supported by the specific Cortex-Mx implementation. + */ +#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) + +/** + * @brief Maximum priority level. + * @details The maximum allowed priority level is always zero. + */ +#define CORTEX_MAXIMUM_PRIORITY 0U + +/** + * @brief Priority level to priority mask conversion macro. + */ +#define CORTEX_PRIO_MASK(n) \ + ((n) << (8U - (unsigned)CORTEX_PRIORITY_BITS)) + +/** + * @brief Priority level verification macro. + */ +#define PORT_IRQ_IS_VALID_PRIORITY(n) \ + (((n) >= 0U) && ((n) < CORTEX_PRIORITY_LEVELS)) + +/** + * @brief Priority level verification macro. + */ +#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) \ + (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +/* Includes the sub-architecture-specific part.*/ +#if (CORTEX_MODEL == 0) || (CORTEX_MODEL == 1) +#include "chcore_v6m.h" +#elif (CORTEX_MODEL == 3) || (CORTEX_MODEL == 4) || (CORTEX_MODEL == 7) +#include "mpu.h" +#include "chcore_v7m.h" +#else +#error "unknown Cortex-M variant" +#endif + +#if !defined(_FROM_ASM_) + +#if CH_CFG_ST_TIMEDELTA > 0 +#if PORT_USE_ALT_TIMER == FALSE +#include "chcore_timer.h" +#else /* PORT_USE_ALT_TIMER != FALSE */ +#include "chcore_timer_alt.h" +#endif /* PORT_USE_ALT_TIMER != FALSE */ +#endif /* CH_CFG_ST_TIMEDELTA > 0 */ + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CHCORE_H */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_timer.h b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_timer.h new file mode 100644 index 0000000..80a76f9 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_timer.h @@ -0,0 +1,133 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chcore_timer.h + * @brief System timer header file. + * + * @addtogroup ARMCMx_TIMER + * @{ + */ + +#ifndef CHCORE_TIMER_H +#define CHCORE_TIMER_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void stStartAlarm(systime_t time); + void stStopAlarm(void); + void stSetAlarm(systime_t time); + systime_t stGetCounter(void); + systime_t stGetAlarm(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] time the time to be set for the first alarm + * + * @notapi + */ +static inline void port_timer_start_alarm(systime_t time) { + + stStartAlarm(time); +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void port_timer_stop_alarm(void) { + + stStopAlarm(); +} + +/** + * @brief Sets the alarm time. + * + * @param[in] time the time to be set for the next alarm + * + * @notapi + */ +static inline void port_timer_set_alarm(systime_t time) { + + stSetAlarm(time); +} + +/** + * @brief Returns the system time. + * + * @return The system time. + * + * @notapi + */ +static inline systime_t port_timer_get_time(void) { + + return stGetCounter(); +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t port_timer_get_alarm(void) { + + return stGetAlarm(); +} + +#endif /* CHCORE_TIMER_H */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v6m.c b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v6m.c new file mode 100644 index 0000000..6847a15 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v6m.c @@ -0,0 +1,155 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chcore_v6m.c + * @brief ARMv6-M architecture port code. + * + * @addtogroup ARMCMx_V6M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module interrupt handlers. */ +/*===========================================================================*/ + +#if (CORTEX_ALTERNATE_SWITCH == FALSE) || defined(__DOXYGEN__) +/** + * @brief NMI vector. + * @details The NMI vector is used for exception mode re-entering after a + * context switch. + */ +/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ +void NMI_Handler(void) { +/*lint -restore*/ + + /* The port_extctx structure is pointed by the PSP register.*/ + struct port_extctx *ctxp = (struct port_extctx *)__get_PSP(); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + + /* Writing back the modified PSP value.*/ + __set_PSP((uint32_t)ctxp); + + /* Restoring the normal interrupts status.*/ + port_unlock_from_isr(); +} +#endif /* !CORTEX_ALTERNATE_SWITCH */ + +#if (CORTEX_ALTERNATE_SWITCH == TRUE) || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + */ +/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ +void PendSV_Handler(void) { +/*lint -restore*/ + + /* The port_extctx structure is pointed by the PSP register.*/ + struct port_extctx *ctxp = (struct port_extctx *)__get_PSP(); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + + /* Writing back the modified PSP value.*/ + __set_PSP((uint32_t)ctxp); +} +#endif /* CORTEX_ALTERNATE_SWITCH */ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +/** + * @brief Port-related initialization code. + */ +void port_init(void) { + + NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV); +} + +/** + * @brief IRQ epilogue code. + * + * @param[in] lr value of the @p LR register on ISR entry + */ +void _port_irq_epilogue(uint32_t lr) { + + if (lr != 0xFFFFFFF1U) { + struct port_extctx *ectxp; + + port_lock_from_isr(); + + /* The extctx structure is pointed by the PSP register.*/ + ectxp = (struct port_extctx *)__get_PSP(); + + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + ectxp--; + + /* Writing back the modified PSP value.*/ + __set_PSP((uint32_t)ectxp); + + /* Setting up a fake XPSR register value.*/ + ectxp->xpsr = 0x01000000U; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ectxp->pc = (uint32_t)_port_switch_from_isr; + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ectxp->pc = (uint32_t)_port_exit_from_isr; + } + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switch atomic.*/ + } +} + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v6m.h b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v6m.h new file mode 100644 index 0000000..371397e --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v6m.h @@ -0,0 +1,466 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chcore_v6m.h + * @brief ARMv6-M architecture port macros and structures. + * + * @addtogroup ARMCMx_V6M_CORE + * @{ + */ + +#ifndef CHCORE_V6M_H +#define CHCORE_V6M_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @name Port Capabilities and Constants + * @{ + */ +/** + * @brief This port supports a realtime counter. + */ +#define PORT_SUPPORTS_RT FALSE + +/** + * @brief Natural alignment constant. + * @note It is the minimum alignment for pointer-size variables. + */ +#define PORT_NATURAL_ALIGN sizeof (void *) + +/** + * @brief Stack alignment constant. + * @note It is the alignment required for the stack pointer. + */ +#define PORT_STACK_ALIGN sizeof (stkalign_t) + +/** + * @brief Working Areas alignment constant. + * @note It is the alignment to be enforced for thread working areas. + */ +#define PORT_WORKING_AREA_ALIGN PORT_STACK_ALIGN +/** @} */ + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p 0, + * this handler always has the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV 0 + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * @note In this port this value is conservatively set to 64 because the + * function @p chSchDoReschedule() can have a stack frame, especially + * with compiler optimizations disabled. The value can be reduced + * when compiler optimizations are enabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 64 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief Alternate preemption method. + * @details Activating this option will make the Kernel use the PendSV + * handler for preemption instead of the NMI handler. + */ +#ifndef CORTEX_ALTERNATE_SWITCH +#define CORTEX_ALTERNATE_SWITCH FALSE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(CH_CUSTOMER_LIC_PORT_CM0) +#error "CH_CUSTOMER_LIC_PORT_CM0 not defined" +#endif + +#if CH_CUSTOMER_LIC_PORT_CM0 == FALSE +#error "ChibiOS Cortex-M0 port not licensed" +#endif + +/* Handling a GCC problem impacting ARMv6-M.*/ +#if defined(__GNUC__) && !defined(PORT_IGNORE_GCC_VERSION_CHECK) +#if ( __GNUC__ > 5 ) && ( __GNUC__ < 10 ) +#define GCC_VERSION ( __GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__ ) +#if ( __GNUC__ == 7 ) && ( GCC_VERSION >= 70500 ) +#elif ( __GNUC__ == 8 ) && ( GCC_VERSION >= 80400 ) +#elif ( __GNUC__ == 9 ) && ( GCC_VERSION >= 90300 ) +#else +#warning "This compiler has a know problem with Cortex-M0, see GCC bugs: 88167, 88656." +#endif +#endif +#endif + +/** + * @name Architecture and Compiler + * @{ + */ +#if ((CORTEX_MODEL == 0) && !defined(__CORE_CM0PLUS_H_DEPENDANT)) || \ + defined(__DOXYGEN__) +/** + * @brief Macro defining the specific ARM architecture. + */ +#define PORT_ARCHITECTURE_ARM_v6M + +/** + * @brief Name of the implemented architecture. + */ +#define PORT_ARCHITECTURE_NAME "ARMv6-M" + +/** + * @brief Name of the architecture variant. + */ +#define PORT_CORE_VARIANT_NAME "Cortex-M0" + +#elif (CORTEX_MODEL == 0) && defined(__CORE_CM0PLUS_H_DEPENDANT) +#define PORT_ARCHITECTURE_ARM_v6M +#define PORT_ARCHITECTURE_NAME "ARMv6-M" +#define PORT_CORE_VARIANT_NAME "Cortex-M0+" +#endif + +/** + * @brief Port-specific information string. + */ +#if (CORTEX_ALTERNATE_SWITCH == FALSE) || defined(__DOXYGEN__) +#define PORT_INFO "Preemption through NMI" +#else +#define PORT_INFO "Preemption through PendSV" +#endif +/** @} */ + +/** + * @brief Maximum usable priority for normal ISRs. + */ +#if (CORTEX_ALTERNATE_SWITCH == TRUE) || defined(__DOXYGEN__) +#define CORTEX_MAX_KERNEL_PRIORITY 1 +#else +#define CORTEX_MAX_KERNEL_PRIORITY 0 +#endif + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) + + /* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) +struct port_extctx { + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r12; + uint32_t lr_thd; + uint32_t pc; + uint32_t xpsr; +}; + +struct port_intctx { + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t lr; +}; + +struct port_context { + struct port_intctx *sp; +}; +#endif /* !defined(__DOXYGEN__) */ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p port_intctx structure. + */ +#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \ + (tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \ + sizeof (struct port_intctx)); \ + (tp)->ctx.sp->r4 = (uint32_t)(pf); \ + (tp)->ctx.sp->r5 = (uint32_t)(arg); \ + (tp)->ctx.sp->lr = (uint32_t)_port_thread_start; \ +} + +/** + * @brief Computes the thread working area global size. + * @note There is no need to perform alignments in this macro. + */ +#define PORT_WA_SIZE(n) (sizeof (struct port_intctx) + \ + sizeof (struct port_extctx) + \ + ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK))) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + * + * @param[in] s the name to be assigned to the stack array + * @param[in] n the stack size to be assigned to the thread + */ +#define PORT_WORKING_AREA(s, n) \ + stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#if defined(__GNUC__) || defined(__DOXYGEN__) +#define PORT_IRQ_PROLOGUE() \ + uint32_t _saved_lr = (uint32_t)__builtin_return_address(0) +#elif defined(__ICCARM__) +#define PORT_IRQ_PROLOGUE() \ + uint32_t _saved_lr = (uint32_t)__get_LR() +#elif defined(__CC_ARM) +#define PORT_IRQ_PROLOGUE() \ + uint32_t _saved_lr = (uint32_t)__return_address() +#endif + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr) + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#ifdef __cplusplus +#define PORT_IRQ_HANDLER(id) extern "C" void id(void) +#else +#define PORT_IRQ_HANDLER(id) void id(void) +#endif + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#ifdef __cplusplus +#define PORT_FAST_IRQ_HANDLER(id) extern "C" void id(void) +#else +#define PORT_FAST_IRQ_HANDLER(id) void id(void) +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if (CH_DBG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#define port_switch(ntp, otp) { \ + struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \ + if ((stkalign_t *)(r13 - 1) < (otp)->wabase) { \ + chSysHalt("stack overflow"); \ + } \ + _port_switch(ntp, otp); \ +} +#endif + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void port_init(void); + void _port_irq_epilogue(uint32_t lr); + void _port_switch(thread_t *ntp, thread_t *otp); + void _port_thread_start(void); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +/** + * @brief Returns a word encoding the current interrupts status. + * + * @return The interrupts status. + */ +static inline syssts_t port_get_irq_status(void) { + + return (syssts_t)__get_PRIMASK(); +} + +/** + * @brief Checks the interrupt status. + * + * @param[in] sts the interrupt status word + * + * @return The interrupt status. + * @retval false the word specified a disabled interrupts status. + * @retval true the word specified an enabled interrupts status. + */ +static inline bool port_irq_enabled(syssts_t sts) { + + return (sts & (syssts_t)1) == (syssts_t)0; +} + +/** + * @brief Determines the current execution context. + * + * @return The execution context. + * @retval false not running in ISR mode. + * @retval true running in ISR mode. + */ +static inline bool port_is_isr_context(void) { + + return (bool)((__get_IPSR() & 0x1FFU) != 0U); +} + +/** + * @brief Kernel-lock action. + * @details In this port this function disables interrupts globally. + */ +static inline void port_lock(void) { + + __disable_irq(); +} + +/** + * @brief Kernel-unlock action. + * @details In this port this function enables interrupts globally. + */ +static inline void port_unlock(void) { + + __enable_irq(); +} + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details In this port this function disables interrupts globally. + * @note Same as @p port_lock() in this port. + */ +static inline void port_lock_from_isr(void) { + + port_lock(); +} + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details In this port this function enables interrupts globally. + * @note Same as @p port_lock() in this port. + */ +static inline void port_unlock_from_isr(void) { + + port_unlock(); +} + +/** + * @brief Disables all the interrupt sources. + */ +static inline void port_disable(void) { + + __disable_irq(); +} + +/** + * @brief Disables the interrupt sources below kernel-level priority. + */ +static inline void port_suspend(void) { + + __disable_irq(); +} + +/** + * @brief Enables all the interrupt sources. + */ +static inline void port_enable(void) { + + __enable_irq(); +} + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +static inline void port_wait_for_interrupt(void) { + +#if CORTEX_ENABLE_WFI_IDLE == TRUE + __WFI(); +#endif +} + +#endif /* _FROM_ASM_ */ + +#endif /* CHCORE_V6M_H */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v7m.c b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v7m.c new file mode 100644 index 0000000..24c94a2 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v7m.c @@ -0,0 +1,391 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chcore_v7m.c + * @brief ARMv7-M architecture port code. + * + * @addtogroup ARMCMx_V7M_CORE + * @{ + */ + +#include + +#include "ch.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module interrupt handlers. */ +/*===========================================================================*/ + +#if (PORT_USE_SYSCALL == TRUE) || defined(__DOXYGEN__) +__attribute__((noinline)) +void port_syslock_noinline(void) { + + port_lock(); + _stats_start_measure_crit_thd(); + _dbg_check_lock(); +} + +uint32_t port_get_s_psp(void) { + + return (uint32_t)currp->ctx.syscall.psp; +} + +__attribute__((weak)) +void port_syscall(struct port_extctx *ctxp, uint32_t n) { + + (void)ctxp; + (void)n; + + chSysHalt("svc"); +} + +void port_unprivileged_jump(uint32_t pc, uint32_t psp) { + struct port_extctx *ectxp; + struct port_linkctx *lctxp; + uint32_t s_psp = __get_PSP(); + uint32_t control = __get_CONTROL(); + + /* Creating a port_extctx context for user mode entry.*/ + psp -= sizeof (struct port_extctx); + ectxp = (struct port_extctx *)psp; + + /* Initializing the user mode entry context.*/ + memset((void *)ectxp, 0, sizeof (struct port_extctx)); + ectxp->pc = pc; + ectxp->xpsr = 0x01000000U; +#if CORTEX_USE_FPU == TRUE + ectxp->fpscr = __get_FPSCR(); +#endif + + /* Creating a middle context for user mode entry.*/ + s_psp -= sizeof (struct port_linkctx); + lctxp = (struct port_linkctx *)s_psp; + + /* CONTROL and PSP values for user mode.*/ + lctxp->control = control | 1U; + lctxp->ectxp = ectxp; + + /* PSP now points to the port_linkctx structure, it will be removed + by SVC.*/ + __set_PSP(s_psp); + + asm volatile ("svc 0"); + + chSysHalt("svc"); +} +#endif + +#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) +/** + * @brief SVC vector. + * @details The SVC vector is used for exception mode re-entering after a + * context switch and, optionally, for system calls. + * @note The SVC vector is only used in advanced kernel mode. + */ +/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ +void SVC_Handler(void) { +/*lint -restore*/ + uint32_t psp = __get_PSP(); + +#if PORT_USE_SYSCALL == TRUE + uint32_t control; + /* Caller context.*/ + struct port_extctx *ectxp = (struct port_extctx *)psp; + +#if defined(__GNUC__) + chDbgAssert(((uint32_t)__builtin_return_address(0) & 4U) != 0U, + "not process"); +#endif + + /* Checking if the SVC instruction has been used from privileged or + non-privileged mode.*/ + control = __get_CONTROL(); + if ((control & 1U) != 0) { + /* From non-privileged mode, it must be handled as a syscall.*/ + uint32_t n, s_psp; + struct port_linkctx *lctxp; + struct port_extctx *newctxp; + + /* Supervisor PSP from the thread context structure.*/ + s_psp = (uint32_t)currp->ctx.syscall.psp; + + /* Pushing the port_linkctx into the supervisor stack.*/ + s_psp -= sizeof (struct port_linkctx); + lctxp = (struct port_linkctx *)s_psp; + lctxp->control = control; + lctxp->ectxp = ectxp; + + /* Enforcing privileged mode before returning.*/ + __set_CONTROL(control & ~1U); + + /* Number of the SVC instruction.*/ + n = (uint32_t)*(((const uint16_t *)ectxp->pc) - 1U) & 255U; + + /* Building an artificial return context, we need to make this + return in the syscall dispatcher in privileged mode.*/ + s_psp -= sizeof (struct port_extctx); + __set_PSP(s_psp); + newctxp = (struct port_extctx *)s_psp; + newctxp->r0 = (uint32_t)ectxp; + newctxp->r1 = n; + newctxp->pc = (uint32_t)port_syscall; + newctxp->xpsr = 0x01000000U; +#if CORTEX_USE_FPU == TRUE + newctxp->fpscr = FPU->FPDSCR; +#endif + } + else +#endif + { + /* From privileged mode, it is used for context discarding in the + preemption code.*/ + + /* Unstacking procedure, discarding the current exception context and + positioning the stack to point to the real one.*/ + psp += sizeof (struct port_extctx); + +#if CORTEX_USE_FPU == TRUE + /* Enforcing unstacking of the FP part of the context.*/ + FPU->FPCCR &= ~FPU_FPCCR_LSPACT_Msk; +#endif + +#if PORT_USE_SYSCALL == TRUE + { + /* Restoring CONTROL and the original PSP position.*/ + struct port_linkctx *lctxp = (struct port_linkctx *)psp; + __set_CONTROL((uint32_t)lctxp->control); + __set_PSP((uint32_t)lctxp->ectxp); + } +#else + + /* Restoring real position of the original stack frame.*/ + __set_PSP(psp); +#endif + + /* Restoring the normal interrupts status.*/ + port_unlock_from_isr(); + } +} +#endif /* CORTEX_SIMPLIFIED_PRIORITY == FALSE */ + +#if (CORTEX_SIMPLIFIED_PRIORITY == TRUE) || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in compact kernel mode. + */ +/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ +void PendSV_Handler(void) { +/*lint -restore*/ + uint32_t psp = __get_PSP(); + +#if CORTEX_USE_FPU + /* Enforcing unstacking of the FP part of the context.*/ + FPU->FPCCR &= ~FPU_FPCCR_LSPACT_Msk; +#endif + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + psp += sizeof (struct port_extctx); + +#if PORT_USE_SYSCALL == TRUE + { + /* Restoring previous privileges by restoring CONTROL.*/ + struct port_linkctx *lctxp = (struct port_linkctx *)psp; + __set_CONTROL((uint32_t)lctxp->control); + psp += sizeof (struct port_linkctx); + } +#endif + + /* Restoring real position of the original stack frame.*/ + __set_PSP(psp); +} +#endif /* CORTEX_SIMPLIFIED_PRIORITY == TRUE */ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +/** + * @brief Port-related initialization code. + */ +void port_init(void) { + + /* Starting in a known IRQ configuration.*/ + port_suspend(); + + /* Initializing priority grouping.*/ + NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT); + + /* DWT cycle counter enable, note, the M7 requires DWT unlocking.*/ + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; +#if CORTEX_MODEL == 7 + DWT->LAR = 0xC5ACCE55U; +#endif + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + + /* Initialization of the system vectors used by the port.*/ +#if CORTEX_SIMPLIFIED_PRIORITY == FALSE + NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL); +#endif + NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV); + +#if PORT_ENABLE_GUARD_PAGES == TRUE + { + extern stkalign_t __main_thread_stack_base__; + + /* Setting up the guard page on the main() function stack base + initially.*/ + mpuConfigureRegion(PORT_USE_GUARD_MPU_REGION, + &__main_thread_stack_base__, + MPU_RASR_ATTR_AP_NA_NA | + MPU_RASR_ATTR_NON_CACHEABLE | + MPU_RASR_SIZE_32 | + MPU_RASR_ENABLE); + } +#endif + +#if PORT_USE_SYSCALL == TRUE + /* MPU is enabled.*/ + mpuEnable(MPU_CTRL_PRIVDEFENA); +#endif +} + +#if ((CH_DBG_ENABLE_STACK_CHECK == TRUE) && \ + (PORT_ENABLE_GUARD_PAGES == TRUE)) || \ + defined(__DOXYGEN__) +/** + * @brief Setting up MPU region for the current thread. + */ +void _port_set_region(void) { + + mpuSetRegionAddress(PORT_USE_GUARD_MPU_REGION, + chThdGetSelfX()->wabase); +} +#endif + +/** + * @brief Exception exit redirection to _port_switch_from_isr(). + */ +void _port_irq_epilogue(void) { + + port_lock_from_isr(); + if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0U) { + struct port_extctx *ectxp; + uint32_t s_psp; + +#if CORTEX_USE_FPU == TRUE + /* Enforcing a lazy FPU state save by accessing the FPCSR register.*/ + (void) __get_FPSCR(); +#endif + +#if PORT_USE_SYSCALL == TRUE + { + struct port_linkctx *lctxp; + uint32_t control = __get_CONTROL(); + + /* Checking if the IRQ has been served in unprivileged mode.*/ + if ((control & 1U) != 0U) { + /* Unprivileged mode, switching to privileged mode.*/ + __set_CONTROL(control & ~1U); + + /* Switching to S-PSP taking it from the thread context.*/ + s_psp = (uint32_t)currp->ctx.syscall.psp; + + /* Pushing the middle context for returning to the original frame + and mode.*/ + s_psp = s_psp - sizeof (struct port_linkctx); + lctxp = (struct port_linkctx *)s_psp; + lctxp->control = control; + lctxp->ectxp = (struct port_extctx *)__get_PSP(); + } + else { + /* Privileged mode, we are already on S-PSP.*/ + uint32_t psp = __get_PSP(); + + /* Pushing the middle context for returning to the original frame + and mode.*/ + s_psp = psp - sizeof (struct port_linkctx); + lctxp = (struct port_linkctx *)s_psp; + lctxp->control = control; + lctxp->ectxp = (struct port_extctx *)psp; + } + } +#else + s_psp = __get_PSP(); +#endif + + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + s_psp -= sizeof (struct port_extctx); + + /* The port_extctx structure is pointed by the S-PSP register.*/ + ectxp = (struct port_extctx *)s_psp; + + /* Setting up a fake XPSR register value.*/ + ectxp->xpsr = 0x01000000U; +#if CORTEX_USE_FPU == TRUE + ectxp->fpscr = FPU->FPDSCR; +#endif + + /* Writing back the modified S-PSP value.*/ + __set_PSP(s_psp); + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ectxp->pc = (uint32_t)_port_switch_from_isr; + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ectxp->pc = (uint32_t)_port_exit_from_isr; + } + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switch atomic.*/ + return; + } + port_unlock_from_isr(); +} + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v7m.h b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v7m.h new file mode 100644 index 0000000..2c39a4f --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/chcore_v7m.h @@ -0,0 +1,790 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chcore_v7m.h + * @brief ARMv7-M architecture port macros and structures. + * + * @addtogroup ARMCMx_V7M_CORE + * @{ + */ + +#ifndef CHCORE_V7M_H +#define CHCORE_V7M_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @name Port Capabilities and Constants + * @{ + */ +/** + * @brief This port supports a realtime counter. + */ +#define PORT_SUPPORTS_RT TRUE + +/** + * @brief Natural alignment constant. + * @note It is the minimum alignment for pointer-size variables. + */ +#define PORT_NATURAL_ALIGN sizeof (void *) + +/** + * @brief Stack alignment constant. + * @note It is the alignment required for the stack pointer. + */ +#define PORT_STACK_ALIGN sizeof (stkalign_t) + +/** + * @brief Working Areas alignment constant. + * @note It is the alignment to be enforced for thread working areas. + */ +#define PORT_WORKING_AREA_ALIGN ((PORT_ENABLE_GUARD_PAGES == TRUE) ?\ + 32U : PORT_STACK_ALIGN) +/** @} */ + +/** + * @brief Disabled value for BASEPRI register. + */ +#define CORTEX_BASEPRI_DISABLED 0U + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Implements a syscall interface on SVC. + */ +#if !defined(PORT_USE_SYSCALL) || defined(__DOXYGEN__) +#define PORT_USE_SYSCALL FALSE +#endif + +/** + * @brief Number of MPU regions to be saved/restored during context switch. + * @note The first region is always region zero. + * @note The use of this option has an overhead of 8 bytes for each + * region for each thread. + * @note Allowed values are 0..4, zero means none. + */ +#if !defined(PORT_SWITCHED_REGIONS_NUMBER) || defined(__DOXYGEN__) +#define PORT_SWITCHED_REGIONS_NUMBER 0 +#endif + +/** + * @brief Enables stack overflow guard pages using MPU. + * @note This option can only be enabled if also option + * @p CH_DBG_ENABLE_STACK_CHECK is enabled. + * @note The use of this option has an overhead of 32 bytes for each + * thread. + */ +#if !defined(PORT_ENABLE_GUARD_PAGES) || defined(__DOXYGEN__) +#define PORT_ENABLE_GUARD_PAGES FALSE +#endif + +/** + * @brief MPU region to be used to stack guards. + * @note Make sure this region is not included in the + * @p PORT_SWITCHED_REGIONS_NUMBER regions range. + */ +#if !defined(PORT_USE_GUARD_MPU_REGION) || defined(__DOXYGEN__) +#define PORT_USE_GUARD_MPU_REGION MPU_REGION_7 +#endif + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * @note In this port this value is conservatively set to 64 because the + * function @p chSchDoReschedule() can have a stack frame, especially + * with compiler optimizations disabled. The value can be reduced + * when compiler optimizations are enabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__) +#define PORT_INT_REQUIRED_STACK 64 +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief FPU support in context switch. + * @details Activating this option activates the FPU support in the kernel. + */ +#if !defined(CORTEX_USE_FPU) +#define CORTEX_USE_FPU CORTEX_HAS_FPU +#elif (CORTEX_USE_FPU == TRUE) && (CORTEX_HAS_FPU == FALSE) +/* This setting requires an FPU presence check in case it is externally + redefined.*/ +#error "the selected core does not have an FPU" +#endif + +/** + * @brief Simplified priority handling flag. + * @details Activating this option makes the Kernel work in compact mode. + * In compact mode interrupts are disabled globally instead of + * raising the priority mask to some intermediate level. + */ +#if !defined(CORTEX_SIMPLIFIED_PRIORITY) +#define CORTEX_SIMPLIFIED_PRIORITY FALSE +#endif + +/** + * @brief SVCALL handler priority. + * @note The default SVCALL handler priority is defaulted to + * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the + * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts + * priority level. + */ +#if !defined(CORTEX_PRIORITY_SVCALL) +#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1U) +#elif !PORT_IRQ_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) +/* If it is externally redefined then better perform a validity check on it.*/ +#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" +#endif + +/** + * @brief NVIC PRIGROUP initialization expression. + * @details The default assigns all available priority bits as preemption + * priority with no sub-priority. + */ +#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__) +#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (PORT_SWITCHED_REGIONS_NUMBER < 0) || (PORT_SWITCHED_REGIONS_NUMBER > 4) +#error "invalid PORT_SWITCHED_REGIONS_NUMBER value" +#endif + +#if !defined(_FROM_ASM_) +/** + * @brief MPU guard page size. + */ +#if (PORT_ENABLE_GUARD_PAGES == TRUE) || defined(__DOXYGEN__) + #if CH_DBG_ENABLE_STACK_CHECK == FALSE + #error "PORT_ENABLE_GUARD_PAGES requires CH_DBG_ENABLE_STACK_CHECK" + #endif + #if __MPU_PRESENT == 0 + #error "MPU not present in current device" + #endif + #define PORT_GUARD_PAGE_SIZE 32U +#else + #define PORT_GUARD_PAGE_SIZE 0U +#endif +#endif /* !defined(_FROM_ASM_) */ + +/** + * @name Architecture and Compiler + * @{ + */ +#if (CORTEX_MODEL == 3) || defined(__DOXYGEN__) + + #if !defined(CH_CUSTOMER_LIC_PORT_CM3) + #error "CH_CUSTOMER_LIC_PORT_CM3 not defined" + #endif + + #if CH_CUSTOMER_LIC_PORT_CM3 == FALSE + #error "ChibiOS Cortex-M3 port not licensed" + #endif + +/** + * @brief Macro defining the specific ARM architecture. + */ +#define PORT_ARCHITECTURE_ARM_v7M + +/** + * @brief Name of the implemented architecture. + */ +#define PORT_ARCHITECTURE_NAME "ARMv7-M" + +/** + * @brief Name of the architecture variant. + */ +#if (PORT_ENABLE_GUARD_PAGES == FALSE) || defined(__DOXYGEN__) + #define PORT_CORE_VARIANT_NAME "Cortex-M3" +#else + #define PORT_CORE_VARIANT_NAME "Cortex-M3 (MPU)" +#endif + +#elif (CORTEX_MODEL == 4) + + #if !defined(CH_CUSTOMER_LIC_PORT_CM4) + #error "CH_CUSTOMER_LIC_PORT_CM4 not defined" + #endif + + #if CH_CUSTOMER_LIC_PORT_CM4 == FALSE + #error "ChibiOS Cortex-M4 port not licensed" + #endif + + #define PORT_ARCHITECTURE_ARM_v7ME + #define PORT_ARCHITECTURE_NAME "ARMv7E-M" + #if CORTEX_USE_FPU + #if PORT_ENABLE_GUARD_PAGES == FALSE + #define PORT_CORE_VARIANT_NAME "Cortex-M4F" + #else + #define PORT_CORE_VARIANT_NAME "Cortex-M4F (MPU)" + #endif + #else + #if PORT_ENABLE_GUARD_PAGES == FALSE + #define PORT_CORE_VARIANT_NAME "Cortex-M4" + #else + #define PORT_CORE_VARIANT_NAME "Cortex-M4 (MPU)" + #endif + #endif + +#elif (CORTEX_MODEL == 7) + + #if !defined(CH_CUSTOMER_LIC_PORT_CM7) + #error "CH_CUSTOMER_LIC_PORT_CM7 not defined" + #endif + + #if CH_CUSTOMER_LIC_PORT_CM7 == FALSE + #error "ChibiOS Cortex-M7 port not licensed" + #endif + +#define PORT_ARCHITECTURE_ARM_v7ME + #define PORT_ARCHITECTURE_NAME "ARMv7E-M" + #if CORTEX_USE_FPU + #if PORT_ENABLE_GUARD_PAGES == FALSE + #define PORT_CORE_VARIANT_NAME "Cortex-M7F" + #else + #define PORT_CORE_VARIANT_NAME "Cortex-M7F (MPU)" + #endif + #else + #if PORT_ENABLE_GUARD_PAGES == FALSE + #define PORT_CORE_VARIANT_NAME "Cortex-M7" + #else + #define PORT_CORE_VARIANT_NAME "Cortex-M7 (MPU)" + #endif + #endif +#endif + +/** + * @brief Port-specific information string. + */ +#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) +#define PORT_INFO "Advanced kernel mode" +#else +#define PORT_INFO "Compact kernel mode" +#endif +/** @} */ + +#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) +/** + * @brief Maximum usable priority for normal ISRs. + */ +#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1U) + +/** + * @brief BASEPRI level within kernel lock. + */ +#define CORTEX_BASEPRI_KERNEL \ + CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY) +#else + +#define CORTEX_MAX_KERNEL_PRIORITY 0U +#endif + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to + * @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the + * highest priority that cannot preempt the kernel. + */ +#define CORTEX_PRIORITY_PENDSV CORTEX_MAX_KERNEL_PRIORITY + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/* The documentation of the following declarations is in chconf.h in order + to not have duplicated structure names into the documentation.*/ +#if !defined(__DOXYGEN__) +struct port_extctx { + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r12; + uint32_t lr_thd; + uint32_t pc; + uint32_t xpsr; +#if CORTEX_USE_FPU + uint32_t s0; + uint32_t s1; + uint32_t s2; + uint32_t s3; + uint32_t s4; + uint32_t s5; + uint32_t s6; + uint32_t s7; + uint32_t s8; + uint32_t s9; + uint32_t s10; + uint32_t s11; + uint32_t s12; + uint32_t s13; + uint32_t s14; + uint32_t s15; + uint32_t fpscr; + uint32_t reserved; +#endif /* CORTEX_USE_FPU */ +}; + +#if (PORT_USE_SYSCALL == TRUE) || defined(__DOXYGEN__) +/** + * @brief Link context structure. + * @details This structure is used when there is the need to save extra + * context information that is not part of the registers stacked + * in HW. + */ +struct port_linkctx { + uint32_t control; + struct port_extctx *ectxp; +}; +#endif + +struct port_intctx { +#if (PORT_SWITCHED_REGIONS_NUMBER > 0) || defined(__DOXYGEN__) + struct { + uint32_t rbar; + uint32_t rasr; + } regions[PORT_SWITCHED_REGIONS_NUMBER]; +#endif +#if CORTEX_USE_FPU + uint32_t s16; + uint32_t s17; + uint32_t s18; + uint32_t s19; + uint32_t s20; + uint32_t s21; + uint32_t s22; + uint32_t s23; + uint32_t s24; + uint32_t s25; + uint32_t s26; + uint32_t s27; + uint32_t s28; + uint32_t s29; + uint32_t s30; + uint32_t s31; +#endif /* CORTEX_USE_FPU */ + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t lr; +}; + +struct port_context { + struct port_intctx *sp; +#if (PORT_USE_SYSCALL == TRUE) || defined(__DOXYGEN__) + struct { + uint32_t psp; + const void *p; + } syscall; +#endif +}; +#endif /* !defined(__DOXYGEN__) */ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/* By default threads have no syscall context information.*/ +#if (PORT_USE_SYSCALL == TRUE) || defined(__DOXYGEN__) +#define __PORT_SETUP_CONTEXT_SYSCALL(tp, wtop) \ + (tp)->ctx.syscall.psp = (uint32_t)(wtop); \ + (tp)->ctx.syscall.p = NULL; +#else +#define __PORT_SETUP_CONTEXT_SYSCALL(tp, wtop) +#endif + +/* By default threads have all regions disabled.*/ +#if (PORT_SWITCHED_REGIONS_NUMBER == 0) || defined(__DOXYGEN__) +#define __PORT_SETUP_CONTEXT_MPU(tp) +#elif (PORT_SWITCHED_REGIONS_NUMBER == 1) || defined(__DOXYGEN__) +#define __PORT_SETUP_CONTEXT_MPU(tp) \ + (tp)->ctx.sp->regions[0].rbar = 0U; \ + (tp)->ctx.sp->regions[0].rasr = 0U +#elif (PORT_SWITCHED_REGIONS_NUMBER == 2) || defined(__DOXYGEN__) +#define __PORT_SETUP_CONTEXT_MPU(tp) \ + (tp)->ctx.sp->regions[0].rbar = 0U; \ + (tp)->ctx.sp->regions[0].rasr = 0U; \ + (tp)->ctx.sp->regions[1].rbar = 0U; \ + (tp)->ctx.sp->regions[1].rasr = 0U +#elif (PORT_SWITCHED_REGIONS_NUMBER == 3) || defined(__DOXYGEN__) +#define __PORT_SETUP_CONTEXT_MPU(tp) \ + (tp)->ctx.sp->regions[0].rbar = 0U; \ + (tp)->ctx.sp->regions[0].rasr = 0U; \ + (tp)->ctx.sp->regions[1].rbar = 0U; \ + (tp)->ctx.sp->regions[1].rasr = 0U; \ + (tp)->ctx.sp->regions[2].rbar = 0U; \ + (tp)->ctx.sp->regions[2].rasr = 0U +#elif (PORT_SWITCHED_REGIONS_NUMBER == 4) || defined(__DOXYGEN__) +#define __PORT_SETUP_CONTEXT_MPU(tp) \ + (tp)->ctx.sp->regions[0].rbar = 0U; \ + (tp)->ctx.sp->regions[0].rasr = 0U; \ + (tp)->ctx.sp->regions[1].rbar = 0U; \ + (tp)->ctx.sp->regions[1].rasr = 0U; \ + (tp)->ctx.sp->regions[2].rbar = 0U; \ + (tp)->ctx.sp->regions[2].rasr = 0U; \ + (tp)->ctx.sp->regions[3].rbar = 0U; \ + (tp)->ctx.sp->regions[3].rasr = 0U +#else +#endif + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p port_intctx structure. + */ +#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \ + (tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \ + sizeof (struct port_intctx)); \ + (tp)->ctx.sp->r4 = (uint32_t)(pf); \ + (tp)->ctx.sp->r5 = (uint32_t)(arg); \ + (tp)->ctx.sp->lr = (uint32_t)_port_thread_start; \ + __PORT_SETUP_CONTEXT_MPU(tp); \ + __PORT_SETUP_CONTEXT_SYSCALL(tp, wtop); \ +} + +// __PORT_SETUP_CONTEXT_MPU(tp) + +/** + * @brief Computes the thread working area global size. + * @note There is no need to perform alignments in this macro. + */ +#define PORT_WA_SIZE(n) ((size_t)PORT_GUARD_PAGE_SIZE + \ + sizeof (struct port_intctx) + \ + sizeof (struct port_extctx) + \ + (size_t)(n) + \ + (size_t)PORT_INT_REQUIRED_STACK) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + * + * @param[in] s the name to be assigned to the stack array + * @param[in] n the stack size to be assigned to the thread + */ +#if (PORT_ENABLE_GUARD_PAGES == FALSE) || defined(__DOXYGEN__) +#define PORT_WORKING_AREA(s, n) \ + stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)] +#else +#define PORT_WORKING_AREA(s, n) \ + ALIGNED_VAR(32) stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)] +#endif + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#ifdef __cplusplus +#define PORT_IRQ_HANDLER(id) extern "C" void id(void) +#else +#define PORT_IRQ_HANDLER(id) void id(void) +#endif + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#ifdef __cplusplus +#define PORT_FAST_IRQ_HANDLER(id) extern "C" void id(void) +#else +#define PORT_FAST_IRQ_HANDLER(id) void id(void) +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if (CH_DBG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__) +#define port_switch(ntp, otp) _port_switch(ntp, otp) +#else +#if PORT_ENABLE_GUARD_PAGES == FALSE +#define port_switch(ntp, otp) { \ + struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \ + if ((stkalign_t *)(r13 - 1) < (otp)->wabase) { \ + chSysHalt("stack overflow"); \ + } \ + _port_switch(ntp, otp); \ +} +#else +#define port_switch(ntp, otp) { \ + _port_switch(ntp, otp); \ + \ + /* Setting up the guard page for the switched-in thread.*/ \ + mpuSetRegionAddress(PORT_USE_GUARD_MPU_REGION, \ + chThdGetSelfX()->wabase); \ +} +#endif +#endif + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void port_init(void); + void _port_irq_epilogue(void); + void _port_switch(thread_t *ntp, thread_t *otp); + void _port_thread_start(void); + void _port_switch_from_isr(void); + void _port_exit_from_isr(void); +#if PORT_USE_SYSCALL == TRUE + void port_unprivileged_jump(uint32_t pc, uint32_t psp); +#endif +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +/** + * @brief Returns a word encoding the current interrupts status. + * + * @return The interrupts status. + */ +__STATIC_FORCEINLINE syssts_t port_get_irq_status(void) { + syssts_t sts; + +#if CORTEX_SIMPLIFIED_PRIORITY == FALSE + sts = (syssts_t)__get_BASEPRI(); +#else /* CORTEX_SIMPLIFIED_PRIORITY */ + sts = (syssts_t)__get_PRIMASK(); +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + return sts; +} + +/** + * @brief Checks the interrupt status. + * + * @param[in] sts the interrupt status word + * + * @return The interrupt status. + * @retval false the word specified a disabled interrupts status. + * @retval true the word specified an enabled interrupts status. + */ +__STATIC_FORCEINLINE bool port_irq_enabled(syssts_t sts) { + +#if CORTEX_SIMPLIFIED_PRIORITY == FALSE + return sts == (syssts_t)CORTEX_BASEPRI_DISABLED; +#else /* CORTEX_SIMPLIFIED_PRIORITY */ + return (sts & (syssts_t)1) == (syssts_t)0; +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ +} + +/** + * @brief Determines the current execution context. + * + * @return The execution context. + * @retval false not running in ISR mode. + * @retval true running in ISR mode. + */ +__STATIC_FORCEINLINE bool port_is_isr_context(void) { + + return (bool)((__get_IPSR() & 0x1FFU) != 0U); +} + +/** + * @brief Kernel-lock action. + * @details In this port this function raises the base priority to kernel + * level. + */ +__STATIC_FORCEINLINE void port_lock(void) { + +#if CORTEX_SIMPLIFIED_PRIORITY == FALSE +#if defined(__CM7_REV) +#if __CM7_REV <= 1 + __disable_irq(); +#endif +#endif + __set_BASEPRI(CORTEX_BASEPRI_KERNEL); +#if defined(__CM7_REV) +#if __CM7_REV <= 1 + __enable_irq(); +#endif +#endif +#else /* CORTEX_SIMPLIFIED_PRIORITY */ + __disable_irq(); +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ +} + +/** + * @brief Kernel-unlock action. + * @details In this port this function lowers the base priority to user + * level. + */ +__STATIC_FORCEINLINE void port_unlock(void) { + +#if CORTEX_SIMPLIFIED_PRIORITY == FALSE + __set_BASEPRI(CORTEX_BASEPRI_DISABLED); +#else /* CORTEX_SIMPLIFIED_PRIORITY */ + __enable_irq(); +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ +} + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details In this port this function raises the base priority to kernel + * level. + * @note Same as @p port_lock() in this port. + */ +__STATIC_FORCEINLINE void port_lock_from_isr(void) { + + port_lock(); +} + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details In this port this function lowers the base priority to user + * level. + * @note Same as @p port_unlock() in this port. + */ +__STATIC_FORCEINLINE void port_unlock_from_isr(void) { + + port_unlock(); +} + +/** + * @brief Disables all the interrupt sources. + * @note In this port it disables all the interrupt sources by raising + * the priority mask to level 0. + */ +__STATIC_FORCEINLINE void port_disable(void) { + + __disable_irq(); +} + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note In this port it raises/lowers the base priority to kernel level. + */ +__STATIC_FORCEINLINE void port_suspend(void) { + +#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) + __set_BASEPRI(CORTEX_BASEPRI_KERNEL); + __enable_irq(); +#else + __disable_irq(); +#endif +} + +/** + * @brief Enables all the interrupt sources. + * @note In this port it lowers the base priority to user level. + */ +__STATIC_FORCEINLINE void port_enable(void) { + +#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__) + __set_BASEPRI(CORTEX_BASEPRI_DISABLED); +#endif + __enable_irq(); +} + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +__STATIC_FORCEINLINE void port_wait_for_interrupt(void) { + +#if CORTEX_ENABLE_WFI_IDLE == TRUE + __WFI(); +#endif +} + +/** + * @brief Returns the current value of the realtime counter. + * + * @return The realtime counter value. + */ +__STATIC_FORCEINLINE rtcnt_t port_rt_get_counter_value(void) { + + return DWT->CYCCNT; +} + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CHCORE_V7M_H */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.S b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.S new file mode 100644 index 0000000..115559e --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.S @@ -0,0 +1,154 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file compilers/GCC/chcoreasm_v6m.S + * @brief ARMv6-M architecture port low level code. + * + * @addtogroup ARMCMx_GCC_CORE + * @{ + */ + +#if !defined(FALSE) || defined(__DOXYGEN__) +#define FALSE 0 +#endif + +#if !defined(TRUE) || defined(__DOXYGEN__) +#define TRUE 1 +#endif + +#define _FROM_ASM_ +#include "chlicense.h" +#include "chconf.h" +#include "chcore.h" + +#if !defined(__DOXYGEN__) + +/* + * RTOS-specific context offset. + */ +#if defined(_CHIBIOS_RT_CONF_) +#define CONTEXT_OFFSET 12 +#elif defined(_CHIBIOS_NIL_CONF_) +#define CONTEXT_OFFSET 0 +#else +#error "invalid chconf.h" +#endif + + .set SCB_ICSR, 0xE000ED04 + .set ICSR_PENDSVSET, 0x10000000 + .set ICSR_NMIPENDSET, 0x80000000 + + .cpu cortex-m0 + .fpu softvfp + + .thumb + .text + +/*--------------------------------------------------------------------------* + * Performs a context switch between two threads. + *--------------------------------------------------------------------------*/ + .thumb_func + .globl _port_switch +_port_switch: + push {r4, r5, r6, r7, lr} + mov r4, r8 + mov r5, r9 + mov r6, r10 + mov r7, r11 + push {r4, r5, r6, r7} + + mov r3, sp + str r3, [r1, #CONTEXT_OFFSET] + ldr r3, [r0, #CONTEXT_OFFSET] + mov sp, r3 + + pop {r4, r5, r6, r7} + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + pop {r4, r5, r6, r7, pc} + +/*--------------------------------------------------------------------------* + * Start a thread by invoking its work function. + * + * Threads execution starts here, the code leaves the system critical zone + * and then jumps into the thread function passed in register R4. The + * register R5 contains the thread parameter. The function chThdExit() is + * called on thread function return. + *--------------------------------------------------------------------------*/ + .thumb_func + .globl _port_thread_start +_port_thread_start: +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + bl _stats_stop_measure_crit_thd +#endif + cpsie i + mov r0, r5 + blx r4 + movs r0, #0 /* MSG_OK */ + bl chThdExit +_zombies: b _zombies + +/*--------------------------------------------------------------------------* + * Post-IRQ switch code. + * + * Exception handlers return here for context switching. + *--------------------------------------------------------------------------*/ + .thumb_func + .globl _port_switch_from_isr +_port_switch_from_isr: +#if CH_DBG_STATISTICS + bl _stats_start_measure_crit_thd +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + bl _stats_stop_measure_crit_thd +#endif + .globl _port_exit_from_isr +_port_exit_from_isr: + ldr r2, .L2 + ldr r3, .L3 + str r3, [r2, #0] +#if CORTEX_ALTERNATE_SWITCH + cpsie i +#endif +.L1: b .L1 + + .align 2 +.L2: .word SCB_ICSR +#if CORTEX_ALTERNATE_SWITCH +.L3: .word ICSR_PENDSVSET +#else +.L3: .word ICSR_NMIPENDSET +#endif + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S new file mode 100644 index 0000000..0833de6 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S @@ -0,0 +1,242 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file compilers/GCC/chcoreasm_v7m.S + * @brief ARMv7-M architecture port low level code. + * + * @addtogroup ARMCMx_GCC_CORE + * @{ + */ + +#if !defined(FALSE) || defined(__DOXYGEN__) +#define FALSE 0 +#endif + +#if !defined(TRUE) || defined(__DOXYGEN__) +#define TRUE 1 +#endif + +#define _FROM_ASM_ +#include "chlicense.h" +#include "chconf.h" +#include "chcore.h" + +#if !defined(__DOXYGEN__) + +/* + * RTOS-specific context offset. + */ +#if defined(_CHIBIOS_RT_CONF_) +#define CONTEXT_OFFSET 12 +#elif defined(_CHIBIOS_NIL_CONF_) +#define CONTEXT_OFFSET 0 +#else +#error "invalid chconf.h" +#endif + +/* MPU-related constants.*/ +#define MPU_RBAR 0xE000ED9C + +/* Other constants.*/ +#define SCB_ICSR 0xE000ED04 +#define ICSR_PENDSVSET 0x10000000 + + .syntax unified + .cpu cortex-m4 +#if CORTEX_USE_FPU + .fpu fpv4-sp-d16 +#else + .fpu softvfp +#endif + + .thumb + .text + +/*--------------------------------------------------------------------------* + * Performs a context switch between two threads. + *--------------------------------------------------------------------------*/ + .thumb_func + .globl _port_switch +_port_switch: + push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +#if CORTEX_USE_FPU + /* Saving FPU context.*/ + vpush {s16-s31} +#endif + +#if PORT_SWITCHED_REGIONS_NUMBER > 0 + /* Saving MPU context.*/ + ldr r2, =MPU_RBAR +#if PORT_SWITCHED_REGIONS_NUMBER >= 1 + mov r3, #0 + str r3, [r2, #-4] /* RNR */ + ldm r2, {r4, r5} /* RBAR, RASR */ +#endif +#if PORT_SWITCHED_REGIONS_NUMBER >= 2 + add r3, #1 + str r3, [r2, #-4] /* RNR */ + ldm r2, {r6, r7} /* RBAR, RASR */ +#endif +#if PORT_SWITCHED_REGIONS_NUMBER >= 3 + add r3, #1 + str r3, [r2, #-4] /* RNR */ + ldm r2, {r8, r9} /* RBAR, RASR */ +#endif +#if PORT_SWITCHED_REGIONS_NUMBER >= 4 + add r3, #1 + str r3, [r2, #-4] /* RNR */ + ldm r2, {r10, r11} /* RBAR, RASR */ +#endif +#if PORT_SWITCHED_REGIONS_NUMBER == 1 + push {r4, r5} +#endif +#if PORT_SWITCHED_REGIONS_NUMBER == 2 + push {r4, r5, r6, r7} +#endif +#if PORT_SWITCHED_REGIONS_NUMBER == 3 + push {r4, r5, r6, r7, r8, r9} +#endif +#if PORT_SWITCHED_REGIONS_NUMBER == 4 + push {r4, r5, r6, r7, r8, r9, r10, r11} +#endif +#endif + + str sp, [r1, #CONTEXT_OFFSET] +#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) && \ + ((CORTEX_MODEL == 3) || (CORTEX_MODEL == 4)) + /* Workaround for ARM errata 752419, only applied if + condition exists for it to be triggered.*/ + ldr r3, [r0, #CONTEXT_OFFSET] + mov sp, r3 +#else + ldr sp, [r0, #CONTEXT_OFFSET] +#endif + +#if PORT_SWITCHED_REGIONS_NUMBER > 0 + /* Restoring MPU context.*/ +#if PORT_SWITCHED_REGIONS_NUMBER == 1 + pop {r4, r5} +#endif +#if PORT_SWITCHED_REGIONS_NUMBER == 2 + pop {r4, r5, r6, r7} +#endif +#if PORT_SWITCHED_REGIONS_NUMBER == 3 + pop {r4, r5, r6, r7, r8, r9} +#endif +#if PORT_SWITCHED_REGIONS_NUMBER == 4 + pop {r4, r5, r6, r7, r8, r9, r10, r11} +#endif +#if PORT_SWITCHED_REGIONS_NUMBER >= 1 + mov r3, #0 + str r3, [r2, #-4] /* RNR */ + stm r2, {r4, r5} /* RBAR, RASR */ +#endif +#if PORT_SWITCHED_REGIONS_NUMBER >= 2 + add r3, #1 + str r3, [r2, #-4] /* RNR */ + stm r2, {r6, r7} /* RBAR, RASR */ +#endif +#if PORT_SWITCHED_REGIONS_NUMBER >= 3 + add r3, #1 + str r3, [r2, #-4] /* RNR */ + stm r2, {r8, r9} /* RBAR, RASR */ +#endif +#if PORT_SWITCHED_REGIONS_NUMBER >= 4 + add r3, #1 + str r3, [r2, #-4] /* RNR */ + stm r2, {r10, r11} /* RBAR, RASR */ +#endif +#endif + +#if CORTEX_USE_FPU + /* Restoring FPU context.*/ + vpop {s16-s31} +#endif + pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + +/*--------------------------------------------------------------------------* + * Start a thread by invoking its work function. + * + * Threads execution starts here, the code leaves the system critical zone + * and then jumps into the thread function passed in register R4. The + * register R5 contains the thread parameter. The function chThdExit() is + * called on thread function return. + *--------------------------------------------------------------------------*/ + .thumb_func + .globl _port_thread_start +_port_thread_start: +#if CH_DBG_ENABLE_STACK_CHECK && PORT_ENABLE_GUARD_PAGES + bl _port_set_region +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + bl _stats_stop_measure_crit_thd +#endif +#if CORTEX_SIMPLIFIED_PRIORITY + cpsie i +#else + movs r3, #0 /* CORTEX_BASEPRI_DISABLED */ + msr BASEPRI, r3 +#endif + mov r0, r5 + blx r4 + movs r0, #0 /* MSG_OK */ + bl chThdExit +_zombies: b _zombies + +/*--------------------------------------------------------------------------* + * Post-IRQ switch code. + * + * Exception handlers return here for context switching. + *--------------------------------------------------------------------------*/ + .thumb_func + .globl _port_switch_from_isr +_port_switch_from_isr: +#if CH_DBG_STATISTICS + bl _stats_start_measure_crit_thd +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + bl _stats_stop_measure_crit_thd +#endif + .globl _port_exit_from_isr +_port_exit_from_isr: +#if CORTEX_SIMPLIFIED_PRIORITY + movw r3, #:lower16:SCB_ICSR + movt r3, #:upper16:SCB_ICSR + mov r2, ICSR_PENDSVSET + str r2, [r3, #0] + cpsie i +#else /* !CORTEX_SIMPLIFIED_PRIORITY */ + svc #0 +#endif /* !CORTEX_SIMPLIFIED_PRIORITY */ +.L1: b .L1 + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/chtypes.h b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/chtypes.h new file mode 100644 index 0000000..de95804 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/chtypes.h @@ -0,0 +1,97 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARMCMx/compilers/GCC/chtypes.h + * @brief ARM Cortex-Mx port system types. + * + * @addtogroup ARMCMx_GCC_CORE + * @{ + */ + +#ifndef CHTYPES_H +#define CHTYPES_H + +#include +#include +#include + +/** + * @name Kernel types + * @{ + */ +typedef uint32_t rtcnt_t; /**< Realtime counter. */ +typedef uint64_t rttime_t; /**< Realtime accumulator. */ +typedef uint32_t syssts_t; /**< System status word. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter.*/ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Numeric event identifier. */ +typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ +typedef uint32_t eventflags_t; /**< Mask of event flags. */ +typedef int32_t cnt_t; /**< Generic signed counter. */ +typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ +/** @} */ + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Makes functions not inlineable. + * @note If the compiler does not support such attribute then some + * time-dependent services could be degraded. + */ +#define NOINLINE __attribute__((noinline)) + +/** + * @brief Optimized thread function declaration macro. + */ +#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg) + +/** + * @brief Packed variable specifier. + */ +#define PACKED_VAR __attribute__((packed)) + +/** + * @brief Memory alignment enforcement for variables. + */ +#define ALIGNED_VAR(n) __attribute__((aligned(n))) + +/** + * @brief Size of a pointer. + * @note To be used where the sizeof operator cannot be used, preprocessor + * expressions for example. + */ +#define SIZEOF_PTR 4 + +/** + * @brief True if alignment is low-high in current architecture. + */ +#define REVERSE_ORDER 1 + +#endif /* CHTYPES_H */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk new file mode 100644 index 0000000..1fefa04 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk @@ -0,0 +1,13 @@ +# List of the ChibiOS/RT Cortex-M0 STM32F0xx port files. +PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/chcore.c \ + $(CHIBIOS)/os/common/ports/ARMCMx/chcore_v6m.c + +PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.S + +PORTINC = $(CHIBIOS)/os/common/ports/ARMCMx \ + $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC + +# Shared variables +ALLXASMSRC += $(PORTASM) +ALLCSRC += $(PORTSRC) +ALLINC += $(PORTINC) diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk new file mode 100644 index 0000000..fb89795 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk @@ -0,0 +1,13 @@ +# List of the ChibiOS/RT ARMv7M generic port files. +PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/chcore.c \ + $(CHIBIOS)/os/common/ports/ARMCMx/chcore_v7m.c + +PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S + +PORTINC = $(CHIBIOS)/os/common/ports/ARMCMx \ + $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC + +# Shared variables +ALLXASMSRC += $(PORTASM) +ALLCSRC += $(PORTSRC) +ALLINC += $(PORTINC) diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s new file mode 100644 index 0000000..ff9c591 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s @@ -0,0 +1,156 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file compilers/IAR/chcoreasm_v6m.s + * @brief ARMv6-M architecture port low level code. + * + * @addtogroup ARMCMx_IAR_CORE + * @{ + */ + +#if !defined(FALSE) || defined(__DOXYGEN__) +#define FALSE 0 +#endif + +#if !defined(TRUE) || defined(__DOXYGEN__) +#define TRUE 1 +#endif + +#define _FROM_ASM_ +#include "chlicense.h" +#include "chconf.h" +#include "chcore.h" + +#if !defined(__DOXYGEN__) + +/* + * RTOS-specific context offset. + */ +#if defined(_CHIBIOS_RT_CONF_) +#define CONTEXT_OFFSET 12 +#elif defined(_CHIBIOS_NIL_CONF_) +#define CONTEXT_OFFSET 0 +#else +#error "invalid chconf.h" +#endif + + MODULE ?chcoreasm_v6m + + AAPCS INTERWORK, VFP_COMPATIBLE + PRESERVE8 + +SCB_ICSR SET 0xE000ED04 + + SECTION .text:CODE:NOROOT(2) + + EXTERN chThdExit + EXTERN chSysHalt + EXTERN chSchDoReschedule +#if CH_DBG_STATISTICS + EXTERN _stats_start_measure_crit_thd + EXTERN _stats_stop_measure_crit_thd +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + EXTERN _dbg_check_unlock + EXTERN _dbg_check_lock +#endif + + THUMB + +/* + * Performs a context switch between two threads. + */ + PUBLIC _port_switch +_port_switch: + push {r4, r5, r6, r7, lr} + mov r4, r8 + mov r5, r9 + mov r6, r10 + mov r7, r11 + push {r4, r5, r6, r7} + mov r3, sp + str r3, [r1, #CONTEXT_OFFSET] + ldr r3, [r0, #CONTEXT_OFFSET] + mov sp, r3 + pop {r4, r5, r6, r7} + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + pop {r4, r5, r6, r7, pc} + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + PUBLIC _port_thread_start +_port_thread_start: +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + bl _stats_stop_measure_crit_thd +#endif + cpsie i + mov r0, r5 + blx r4 + movs r0, #0 /* MSG_OK */ + bl chThdExit +_zombies: b _zombies + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + PUBLIC _port_switch_from_isr + PUBLIC _port_exit_from_isr +_port_switch_from_isr: +#if CH_DBG_STATISTICS + bl _stats_start_measure_crit_thd +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + bl _stats_stop_measure_crit_thd +#endif +_port_exit_from_isr: + ldr r2, =SCB_ICSR + movs r3, #128 +#if CORTEX_ALTERNATE_SWITCH + lsls r3, r3, #21 + str r3, [r2, #0] + cpsie i +#else + lsls r3, r3, #24 + str r3, [r2, #0] +#endif +waithere: + b waithere + + END + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s new file mode 100644 index 0000000..af8eca8 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s @@ -0,0 +1,169 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file compilers/IAR/chcoreasm_v7m.s + * @brief ARMv7-M architecture port low level code. + * + * @addtogroup ARMCMx_IAR_CORE + * @{ + */ + +#if !defined(FALSE) || defined(__DOXYGEN__) +#define FALSE 0 +#endif + +#if !defined(TRUE) || defined(__DOXYGEN__) +#define TRUE 1 +#endif + +#define _FROM_ASM_ +#include "chlicense.h" +#include "chconf.h" +#include "chcore.h" + +#if !defined(__DOXYGEN__) + +/* + * RTOS-specific context offset. + */ +#if defined(_CHIBIOS_RT_CONF_) +#define CONTEXT_OFFSET 12 +#elif defined(_CHIBIOS_NIL_CONF_) +#define CONTEXT_OFFSET 0 +#else +#error "invalid chconf.h" +#endif + + MODULE ?chcoreasm_v7m + + AAPCS INTERWORK, VFP_COMPATIBLE + PRESERVE8 + +SCB_ICSR SET 0xE000ED04 +ICSR_PENDSVSET SET 0x10000000 + + SECTION .text:CODE:NOROOT(2) + + EXTERN chThdExit + EXTERN chSchDoReschedule +#if CH_DBG_ENABLE_STACK_CHECK && PORT_ENABLE_GUARD_PAGES + EXTERN _port_set_region +#endif +#if CH_DBG_STATISTICS + EXTERN _stats_start_measure_crit_thd + EXTERN _stats_stop_measure_crit_thd +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + EXTERN _dbg_check_unlock + EXTERN _dbg_check_lock +#endif + + THUMB + +/* + * Performs a context switch between two threads. + */ + PUBLIC _port_switch +_port_switch: + push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +#if CORTEX_USE_FPU + vpush {s16-s31} +#endif + + str sp, [r1, #CONTEXT_OFFSET] +#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) && \ + ((CORTEX_MODEL == 3) || (CORTEX_MODEL == 4)) + /* Workaround for ARM errata 752419, only applied if + condition exists for it to be triggered.*/ + ldr r3, [r0, #CONTEXT_OFFSET] + mov sp, r3 +#else + ldr sp, [r0, #CONTEXT_OFFSET] +#endif + +#if CORTEX_USE_FPU + vpop {s16-s31} +#endif + pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + PUBLIC _port_thread_start +_port_thread_start: +#if CH_DBG_ENABLE_STACK_CHECK && PORT_ENABLE_GUARD_PAGES + bl _port_set_region +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + bl _stats_stop_measure_crit_thd +#endif +#if CORTEX_SIMPLIFIED_PRIORITY + cpsie i +#else + movs r3, #0 /* CORTEX_BASEPRI_DISABLED */ + msr BASEPRI, r3 +#endif + mov r0, r5 + blx r4 + movs r0, #0 /* MSG_OK */ + bl chThdExit +_zombies: b _zombies + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + PUBLIC _port_switch_from_isr + PUBLIC _port_exit_from_isr +_port_switch_from_isr: +#if CH_DBG_STATISTICS + bl _stats_start_measure_crit_thd +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + bl _stats_stop_measure_crit_thd +#endif +_port_exit_from_isr: +#if CORTEX_SIMPLIFIED_PRIORITY + mov r3, #LWRD SCB_ICSR + movt r3, #HWRD SCB_ICSR + mov r2, #ICSR_PENDSVSET + str r2, [r3] + cpsie i +#else + svc #0 +#endif +.L3: b .L3 + + END + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/IAR/chtypes.h b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/IAR/chtypes.h new file mode 100644 index 0000000..2bd376d --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/IAR/chtypes.h @@ -0,0 +1,115 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARMCMx/compilers/IAR/chtypes.h + * @brief ARM Cortex-Mx port system types. + * + * @addtogroup ARMCMx_IAR_CORE + * @{ + */ + +#ifndef CHTYPES_H +#define CHTYPES_H + +#include +#include +#include + +/** + * @name Common constants + */ +/** + * @brief Generic 'false' boolean constant. + */ +#if !defined(FALSE) || defined(__DOXYGEN__) +#define FALSE 0 +#endif + +/** + * @brief Generic 'true' boolean constant. + */ +#if !defined(TRUE) || defined(__DOXYGEN__) +#define TRUE (!FALSE) +#endif +/** @} */ + +/** + * @name Kernel types + * @{ + */ +typedef uint32_t rtcnt_t; /**< Realtime counter. */ +typedef uint64_t rttime_t; /**< Realtime accumulator. */ +typedef uint32_t syssts_t; /**< System status word. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter.*/ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Numeric event identifier. */ +typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ +typedef uint32_t eventflags_t; /**< Mask of event flags. */ +typedef int32_t cnt_t; /**< Generic signed counter. */ +typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ +/** @} */ + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Makes functions not inlineable. + * @note If the compiler does not support such attribute then some + * time-dependent services could be degraded. + */ +#define NOINLINE _Pragma("inline=never") + +/** + * @brief Optimized thread function declaration macro. + */ +#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg) + +/** + * @brief Packed variable specifier. + */ +#define PACKED_VAR __packed + +/** + * @brief Memory alignment enforcement for variables. + */ +#define ALIGNED_VAR(n) _Pragma(__CH_STRINGIFY(data_alignment=n)) + +/** + * @brief Size of a pointer. + * @note To be used where the sizeof operator cannot be used, preprocessor + * expressions for example. + */ +#define SIZEOF_PTR 4 + +/** + * @brief True if alignment is low-high in current architecture. + */ +#define REVERSE_ORDER 1 + +#endif /* CHTYPES_H */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s new file mode 100644 index 0000000..5784935 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s @@ -0,0 +1,152 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file compilers/RVCT/chcoreasm_v6m.s + * @brief ARMv6-M architecture port low level code. + * + * @addtogroup ARMCMx_RVCT_CORE + * @{ + */ + +#if !defined(FALSE) || defined(__DOXYGEN__) +#define FALSE 0 +#endif + +#if !defined(TRUE) || defined(__DOXYGEN__) +#define TRUE 1 +#endif + +#define _FROM_ASM_ +#include "chlicense.h" +#include "chconf.h" +#include "chcore.h" + +#if !defined(__DOXYGEN__) + +/* + * RTOS-specific context offset. + */ +#if defined(_CHIBIOS_RT_CONF_) +#define CONTEXT_OFFSET 12 +#elif defined(_CHIBIOS_NIL_CONF_) +#define CONTEXT_OFFSET 0 +#else +#error "invalid chconf.h" +#endif + +SCB_ICSR EQU 0xE000ED04 + + PRESERVE8 + THUMB + AREA |.text|, CODE, READONLY + + IMPORT chThdExit + IMPORT chSchDoReschedule +#if CH_DBG_STATISTICS + IMPORT _stats_start_measure_crit_thd + IMPORT _stats_stop_measure_crit_thd +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + IMPORT _dbg_check_unlock + IMPORT _dbg_check_lock +#endif + +/* + * Performs a context switch between two threads. + */ + EXPORT _port_switch +_port_switch PROC + push {r4, r5, r6, r7, lr} + mov r4, r8 + mov r5, r9 + mov r6, r10 + mov r7, r11 + push {r4, r5, r6, r7} + mov r3, sp + str r3, [r1, #CONTEXT_OFFSET] + ldr r3, [r0, #CONTEXT_OFFSET] + mov sp, r3 + pop {r4, r5, r6, r7} + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + pop {r4, r5, r6, r7, pc} + ENDP + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + EXPORT _port_thread_start +_port_thread_start PROC +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + bl _stats_stop_measure_crit_thd +#endif + cpsie i + mov r0, r5 + blx r4 + movs r0, #0 /* MSG_OK */ + bl chThdExit +_zombies b _zombies + ENDP + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + EXPORT _port_switch_from_isr + EXPORT _port_exit_from_isr +_port_switch_from_isr PROC +#if CH_DBG_STATISTICS + bl _stats_start_measure_crit_thd +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + bl _stats_stop_measure_crit_thd +#endif +_port_exit_from_isr + ldr r2, =SCB_ICSR + movs r3, #128 +#if CORTEX_ALTERNATE_SWITCH + lsls r3, r3, #21 + str r3, [r2, #0] + cpsie i +#else + lsls r3, r3, #24 + str r3, [r2, #0] +#endif +waithere b waithere + ENDP + + END + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s new file mode 100644 index 0000000..2fa01c3 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s @@ -0,0 +1,167 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file compilers/RVCT/chcoreasm_v7m.s + * @brief ARMv7-M architecture port low level code. + * + * @addtogroup ARMCMx_RVCT_CORE + * @{ + */ + +#if !defined(FALSE) || defined(__DOXYGEN__) +#define FALSE 0 +#endif + +#if !defined(TRUE) || defined(__DOXYGEN__) +#define TRUE 1 +#endif + +#define _FROM_ASM_ +#include "chlicense.h" +#include "chconf.h" +#include "chcore.h" + +#if !defined(__DOXYGEN__) + +/* + * RTOS-specific context offset. + */ +#if defined(_CHIBIOS_RT_CONF_) +#define CONTEXT_OFFSET 12 +#elif defined(_CHIBIOS_NIL_CONF_) +#define CONTEXT_OFFSET 0 +#else +#error "invalid chconf.h" +#endif + +SCB_ICSR EQU 0xE000ED04 +ICSR_PENDSVSET EQU 0x10000000 + + PRESERVE8 + THUMB + AREA |.text|, CODE, READONLY + + IMPORT chThdExit + IMPORT chSchDoReschedule +#if CH_DBG_ENABLE_STACK_CHECK && PORT_ENABLE_GUARD_PAGES + IMPORT _port_set_region +#endif +#if CH_DBG_STATISTICS + IMPORT _stats_start_measure_crit_thd + IMPORT _stats_stop_measure_crit_thd +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + IMPORT _dbg_check_unlock + IMPORT _dbg_check_lock +#endif + +/* + * Performs a context switch between two threads. + */ + EXPORT _port_switch +_port_switch PROC + push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +#if CORTEX_USE_FPU + vpush {s16-s31} +#endif + + str sp, [r1, #CONTEXT_OFFSET] +#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) && \ + ((CORTEX_MODEL == 3) || (CORTEX_MODEL == 4)) + /* Workaround for ARM errata 752419, only applied if + condition exists for it to be triggered.*/ + ldr r3, [r0, #CONTEXT_OFFSET] + mov sp, r3 +#else + ldr sp, [r0, #CONTEXT_OFFSET] +#endif + +#if CORTEX_USE_FPU + vpop {s16-s31} +#endif + pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + ENDP + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + EXPORT _port_thread_start +_port_thread_start PROC +#if CH_DBG_ENABLE_STACK_CHECK && PORT_ENABLE_GUARD_PAGES + bl _port_set_region +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + bl _stats_stop_measure_crit_thd +#endif +#if CORTEX_SIMPLIFIED_PRIORITY + cpsie i +#else + movs r3, #0 /* CORTEX_BASEPRI_DISABLED */ + msr BASEPRI, r3 +#endif + mov r0, r5 + blx r4 + movs r0, #0 /* MSG_OK */ + bl chThdExit +_zombies b _zombies + ENDP + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + EXPORT _port_switch_from_isr + EXPORT _port_exit_from_isr +_port_switch_from_isr PROC +#if CH_DBG_STATISTICS + bl _stats_start_measure_crit_thd +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + bl _stats_stop_measure_crit_thd +#endif +_port_exit_from_isr +#if CORTEX_SIMPLIFIED_PRIORITY + mov r3, #SCB_ICSR :AND: 0xFFFF + movt r3, #SCB_ICSR :SHR: 16 + mov r2, #ICSR_PENDSVSET + str r2, [r3, #0] + cpsie i +#else + svc #0 +#endif +waithere b waithere + ENDP + + END + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/RVCT/chtypes.h b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/RVCT/chtypes.h new file mode 100644 index 0000000..fbda597 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/compilers/RVCT/chtypes.h @@ -0,0 +1,97 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARMCMx/compilers/RVCT/chtypes.h + * @brief ARM Cortex-Mx port system types. + * + * @addtogroup ARMCMx_RVCT_CORE + * @{ + */ + +#ifndef CHTYPES_H +#define CHTYPES_H + +#include +#include +#include + +/** + * @name Kernel types + * @{ + */ +typedef uint32_t rtcnt_t; /**< Realtime counter. */ +typedef uint64_t rttime_t; /**< Realtime accumulator. */ +typedef uint32_t syssts_t; /**< System status word. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter.*/ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Numeric event identifier. */ +typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ +typedef uint32_t eventflags_t; /**< Mask of event flags. */ +typedef int32_t cnt_t; /**< Generic signed counter. */ +typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ +/** @} */ + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Makes functions not inlineable. + * @note If the compiler does not support such attribute then some + * time-dependent services could be degraded. + */ +#define NOINLINE __attribute__((noinline)) + +/** + * @brief Optimized thread function declaration macro. + */ +#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg) + +/** + * @brief Packed variable specifier. + */ +#define PACKED_VAR __packed + +/** + * @brief Memory alignment enforcement for variables. + */ +#define ALIGNED_VAR(n) __attribute__((aligned(n))) + +/** + * @brief Size of a pointer. + * @note To be used where the sizeof operator cannot be used, preprocessor + * expressions for example. + */ +#define SIZEOF_PTR 4 + +/** + * @brief True if alignment is low-high in current architecture. + */ +#define REVERSE_ORDER 1 + +#endif /* CHTYPES_H */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/ports/ARMCMx/mpu.h b/ChibiOS_20.3.2/os/common/ports/ARMCMx/mpu.h new file mode 100644 index 0000000..850be91 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/ports/ARMCMx/mpu.h @@ -0,0 +1,228 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file common/ARMCMx/mpu.h + * @brief Cortex-Mx MPU support macros and structures. + * + * @addtogroup COMMON_ARMCMx_MPU + * @{ + */ + +#ifndef MPU_H +#define MPU_H + +/* Other layers may include another header named mpu_v7m.h which is perfectly + compatible, doing a check here to avoid name conflicts.*/ +#ifndef MPUV7M_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name MPU registers definitions + * @{ + */ +#define MPU_TYPE_SEPARATED (1U << 0U) +#define MPU_TYPE_DREGION(n) (((n) >> 8U) & 255U) +#define MPU_TYPE_IREGION(n) (((n) >> 16U) & 255U) + +#define MPU_CTRL_ENABLE (1U << 0U) +#define MPU_CTRL_HFNMIENA (1U << 1U) +#define MPU_CTRL_PRIVDEFENA (1U << 2U) + +#define MPU_RNR_REGION_MASK (255U << 0U) +#define MPU_RNR_REGION(n) ((n) << 0U) + +#define MPU_RBAR_REGION_MASK (15U << 0U) +#define MPU_RBAR_REGION(n) ((n) << 0U) +#define MPU_RBAR_VALID (1U << 4U) +#define MPU_RBAR_ADDR_MASK 0xFFFFFFE0U +#define MPU_RBAR_ADDR(n) ((n) << 5U) + +#define MPU_RASR_ENABLE (1U << 0U) +#define MPU_RASR_SIZE_MASK (31U << 1U) +#define MPU_RASR_SIZE(n) ((n) << 1U) +#define MPU_RASR_SIZE_32 MPU_RASR_SIZE(4U) +#define MPU_RASR_SIZE_64 MPU_RASR_SIZE(5U) +#define MPU_RASR_SIZE_128 MPU_RASR_SIZE(6U) +#define MPU_RASR_SIZE_256 MPU_RASR_SIZE(7U) +#define MPU_RASR_SIZE_512 MPU_RASR_SIZE(8U) +#define MPU_RASR_SIZE_1K MPU_RASR_SIZE(9U) +#define MPU_RASR_SIZE_2K MPU_RASR_SIZE(10U) +#define MPU_RASR_SIZE_4K MPU_RASR_SIZE(11U) +#define MPU_RASR_SIZE_8K MPU_RASR_SIZE(12U) +#define MPU_RASR_SIZE_16K MPU_RASR_SIZE(13U) +#define MPU_RASR_SIZE_32K MPU_RASR_SIZE(14U) +#define MPU_RASR_SIZE_64K MPU_RASR_SIZE(15U) +#define MPU_RASR_SIZE_128K MPU_RASR_SIZE(16U) +#define MPU_RASR_SIZE_256K MPU_RASR_SIZE(17U) +#define MPU_RASR_SIZE_512K MPU_RASR_SIZE(18U) +#define MPU_RASR_SIZE_1M MPU_RASR_SIZE(19U) +#define MPU_RASR_SIZE_2M MPU_RASR_SIZE(20U) +#define MPU_RASR_SIZE_4M MPU_RASR_SIZE(21U) +#define MPU_RASR_SIZE_8M MPU_RASR_SIZE(22U) +#define MPU_RASR_SIZE_16M MPU_RASR_SIZE(23U) +#define MPU_RASR_SIZE_32M MPU_RASR_SIZE(24U) +#define MPU_RASR_SIZE_64M MPU_RASR_SIZE(25U) +#define MPU_RASR_SIZE_128M MPU_RASR_SIZE(26U) +#define MPU_RASR_SIZE_256M MPU_RASR_SIZE(27U) +#define MPU_RASR_SIZE_512M MPU_RASR_SIZE(28U) +#define MPU_RASR_SIZE_1G MPU_RASR_SIZE(29U) +#define MPU_RASR_SIZE_2G MPU_RASR_SIZE(30U) +#define MPU_RASR_SIZE_4G MPU_RASR_SIZE(31U) +#define MPU_RASR_SRD_MASK (255U << 8U) +#define MPU_RASR_SRD(n) ((n) << 8U) +#define MPU_RASR_SRD_ALL (0U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB0 (1U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB1 (2U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB2 (4U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB3 (8U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB4 (16U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB5 (32U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB6 (64U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB7 (128U << 8U) +#define MPU_RASR_ATTR_B (1U << 16U) +#define MPU_RASR_ATTR_C (1U << 17U) +#define MPU_RASR_ATTR_S (1U << 18U) +#define MPU_RASR_ATTR_TEX_MASK (7U << 19U) +#define MPU_RASR_ATTR_TEX(n) ((n) << 19U) +#define MPU_RASR_ATTR_AP_MASK (7U << 24U) +#define MPU_RASR_ATTR_AP(n) ((n) << 24U) +#define MPU_RASR_ATTR_AP_NA_NA (0U << 24U) +#define MPU_RASR_ATTR_AP_RW_NA (1U << 24U) +#define MPU_RASR_ATTR_AP_RW_RO (2U << 24U) +#define MPU_RASR_ATTR_AP_RW_RW (3U << 24U) +#define MPU_RASR_ATTR_AP_RO_NA (5U << 24U) +#define MPU_RASR_ATTR_AP_RO_RO (6U << 24U) +#define MPU_RASR_ATTR_XN (1U << 28U) +/** @} */ + +/** + * @name Region attributes + * @{ + */ +#define MPU_RASR_ATTR_STRONGLY_ORDERED (MPU_RASR_ATTR_TEX(0)) +#define MPU_RASR_ATTR_SHARED_DEVICE (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B) +#define MPU_RASR_ATTR_CACHEABLE_WT_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_C) +#define MPU_RASR_ATTR_CACHEABLE_WB_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C) +#define MPU_RASR_ATTR_NON_CACHEABLE (MPU_RASR_ATTR_TEX(1)) +#define MPU_RASR_ATTR_CACHEABLE_WB_WA (MPU_RASR_ATTR_TEX(1) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C) +#define MPU_RASR_ATTR_NON_SHARED_DEVICE (MPU_RASR_ATTR_TEX(2)) +/** @} */ + +/** + * @name Region identifiers + * @{ + */ +#define MPU_REGION_0 0U +#define MPU_REGION_1 1U +#define MPU_REGION_2 2U +#define MPU_REGION_3 3U +#define MPU_REGION_4 4U +#define MPU_REGION_5 5U +#define MPU_REGION_6 6U +#define MPU_REGION_7 7U +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Enables the MPU. + * @note MEMFAULENA is enabled in SCB_SHCSR. + * + * @param[in] ctrl MPU control modes as defined in @p MPU_CTRL register, + * the enable bit is enforced + * + * @api + */ +#define mpuEnable(ctrl) { \ + MPU->CTRL = ((uint32_t)ctrl) | MPU_CTRL_ENABLE; \ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; \ +} + +/** + * @brief Disables the MPU. + * @note MEMFAULENA is disabled in SCB_SHCSR. + * + * @api + */ +#define mpuDisable() { \ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; \ + MPU->CTRL = 0; \ +} + +/** + * @brief Configures an MPU region. + * + * @param[in] region the region number + * @param[in] address start address of the region, note, there are alignment + * constraints + * @param[in] attribs attributes mask as defined in @p MPU_RASR register + * + * @api + */ +#define mpuConfigureRegion(region, addr, attribs) { \ + MPU->RNR = ((uint32_t)region); \ + MPU->RBAR = ((uint32_t)addr); \ + MPU->RASR = ((uint32_t)attribs); \ +} + +/** + * @brief Changes an MPU region base address. + * + * @param[in] region the region number + * @param[in] address start address of the region, note, there are alignment + * constraints + * + * @api + */ +#define mpuSetRegionAddress(region, addr) { \ + MPU->RNR = ((uint32_t)region); \ + MPU->RBAR = ((uint32_t)addr); \ +} + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* MPUV7M_H */ + +#endif /* MPU_H */ + +/** @} */ -- cgit v1.2.3