From 48026bb824fd2d9cfb00ecd040db6ef3a416bae9 Mon Sep 17 00:00:00 2001 From: Clyne Sullivan Date: Fri, 22 Jan 2021 21:43:36 -0500 Subject: upload initial port --- .../common/startup/e200/devices/SPC564Axx/boot.S | 357 +++++++++++++++++++++ .../common/startup/e200/devices/SPC564Axx/boot.h | 242 ++++++++++++++ .../common/startup/e200/devices/SPC564Axx/intc.h | 93 ++++++ .../startup/e200/devices/SPC564Axx/ppcparams.h | 83 +++++ 4 files changed, 775 insertions(+) create mode 100644 ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.S create mode 100644 ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.h create mode 100644 ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/intc.h create mode 100644 ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/ppcparams.h (limited to 'ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx') diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.S b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.S new file mode 100644 index 0000000..cd20b66 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.S @@ -0,0 +1,357 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC564Axx/boot.s + * @brief SPC564Axx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if defined(__HIGHTEC__) +#define se_bge bge +#endif + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + +#if BOOT_USE_VLE + .long 0x015A0000 +#else + .long 0x005A0000 +#endif + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + e_bl _coreinit +#endif + e_bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + e_lis r4, __ram_reloc_start__@h + e_or2i r4, __ram_reloc_start__@l + e_lis r5, __ram_reloc_dest__@h + e_or2i r5, __ram_reloc_dest__@l + e_lis r6, __ram_reloc_end__@h + e_or2i r6, r6, __ram_reloc_end__@l +.relloop: + se_cmpl r4, r6 + se_bge .relend + se_lwz r7, 0(r4) + se_addi r4, 4 + se_stw r7, 0(r5) + se_addi r5, 4 + se_b .relloop +.relend: + e_lis r3, _boot_address@h + e_or2i r3, _boot_address@l + mtctr r3 + se_bctrl +#else + e_b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_ramcode: + tlbwe + se_isync + se_blr + + .align 2 +_coreinit: + /* + * Invalidating all TLBs except TLB1. + */ + e_lis r3, 0 + mtspr 625, r3 /* MAS1 */ + mtspr 626, r3 /* MAS2 */ + mtspr 627, r3 /* MAS3 */ + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h + mtspr 624, r3 /* MAS0 */ + tlbwe + + /* + * TLB0 allocated to internal RAM. + */ + e_lis r3, TLB0_MAS0@h + mtspr 624, r3 /* MAS0 */ + e_lis r3, TLB0_MAS1@h + e_or2i r3, TLB0_MAS1@l + mtspr 625, r3 /* MAS1 */ + e_lis r3, TLB0_MAS2@h + e_or2i r3, TLB0_MAS2@l + mtspr 626, r3 /* MAS2 */ + e_lis r3, TLB0_MAS3@h + e_or2i r3, TLB0_MAS3@l + mtspr 627, r3 /* MAS3 */ + tlbwe + + /* + * TLB2 allocated to internal Peripherals Bridge A. + */ + e_lis r3, TLB2_MAS0@h + mtspr 624, r3 /* MAS0 */ + e_lis r3, TLB2_MAS1@h + e_or2i r3, TLB2_MAS1@l + mtspr 625, r3 /* MAS1 */ + e_lis r3, TLB2_MAS2@h + e_or2i r3, TLB2_MAS2@l + mtspr 626, r3 /* MAS2 */ + e_lis r3, TLB2_MAS3@h + e_or2i r3, TLB2_MAS3@l + mtspr 627, r3 /* MAS3 */ + tlbwe + + /* + * TLB3 allocated to internal Peripherals Bridge B. + */ + e_lis r3, TLB3_MAS0@h + mtspr 624, r3 /* MAS0 */ + e_lis r3, TLB3_MAS1@h + e_or2i r3, TLB3_MAS1@l + mtspr 625, r3 /* MAS1 */ + e_lis r3, TLB3_MAS2@h + e_or2i r3, TLB3_MAS2@l + mtspr 626, r3 /* MAS2 */ + e_lis r3, TLB3_MAS3@h + e_or2i r3, TLB3_MAS3@l + mtspr 627, r3 /* MAS3 */ + tlbwe + + /* + * TLB4 allocated to on-platform peripherals. + */ + e_lis r3, TLB4_MAS0@h + mtspr 624, r3 /* MAS0 */ + e_lis r3, TLB4_MAS1@h + e_or2i r3, TLB4_MAS1@l + mtspr 625, r3 /* MAS1 */ + e_lis r3, TLB4_MAS2@h + e_or2i r3, TLB4_MAS2@l + mtspr 626, r3 /* MAS2 */ + e_lis r3, TLB4_MAS3@h + e_or2i r3, TLB4_MAS3@l + mtspr 627, r3 /* MAS3 */ + tlbwe + + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor r0, r0, r0 + xor r1, r1, r1 + xor r2, r2, r2 + xor r3, r3, r3 + xor r4, r4, r4 + xor r5, r5, r5 + xor r6, r6, r6 + xor r7, r7, r7 + xor r8, r8, r8 + xor r9, r9, r9 + xor r10, r10, r10 + xor r11, r11, r11 + xor r12, r12, r12 + xor r13, r13, r13 + xor r14, r14, r14 + xor r15, r15, r15 + xor r16, r16, r16 + xor r17, r17, r17 + xor r18, r18, r18 + xor r19, r19, r19 + xor r20, r20, r20 + xor r21, r21, r21 + xor r22, r22, r22 + xor r23, r23, r23 + xor r24, r24, r24 + xor r25, r25, r25 + xor r26, r26, r26 + xor r27, r27, r27 + xor r28, r28, r28 + xor r29, r29, r29 + xor r30, r30, r30 + xor r31, r31, r31 + e_lis r4, __ram_start__@h + e_or2i r4, __ram_start__@l + e_lis r5, __ram_end__@h + e_or2i r5, __ram_end__@l +.cleareccloop: + se_cmpl r4, r5 + se_bge .cleareccend + e_stmw r16, 0(r4) + e_addi r4, r4, 64 + se_b .cleareccloop +.cleareccend: + + /* + * *Finally* the TLB1 is re-allocated to flash, note, the final phase + * is executed from RAM. + */ + e_lis r3, TLB1_MAS0@h + mtspr 624, r3 /* MAS0 */ + e_lis r3, TLB1_MAS1@h + e_or2i r3, TLB1_MAS1@l + mtspr 625, r3 /* MAS1 */ + e_lis r3, TLB1_MAS2@h + e_or2i r3, TLB1_MAS2@l + mtspr 626, r3 /* MAS2 */ + e_lis r3, TLB1_MAS3@h + e_or2i r3, TLB1_MAS3@l + mtspr 627, r3 /* MAS3 */ + mflr r4 + e_lis r6, _ramcode@h + e_or2i r6, _ramcode@l + e_lis r7, 0x40010000@h + mtctr r7 + se_lwz r3, 0(r6) + se_stw r3, 0(r7) + se_lwz r3, 4(r6) + se_stw r3, 4(r7) + se_lwz r3, 8(r6) + se_stw r3, 8(r7) + se_bctrl + mtlr r4 + + /* + * Branch prediction enabled. + */ + e_li r3, BOOT_BUCSR_DEFAULT + mtspr 1013, r3 /* BUCSR */ + + /* + * Cache invalidated and then enabled. + */ + e_li r3, LICSR1_ICINV + mtspr 1011, r3 /* LICSR1 */ +.inv: mfspr r3, 1011 /* LICSR1 */ + e_and2i. r3, LICSR1_ICINV + se_bne .inv + e_lis r3, BOOT_LICSR1_DEFAULT@h + e_or2i r3, BOOT_LICSR1_DEFAULT@l + mtspr 1011, r3 /* LICSR1 */ + + se_blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ + .align 2 +_ivinit: + /* MSR initialization.*/ + e_lis r3, BOOT_MSR_DEFAULT@h + e_or2i r3, BOOT_MSR_DEFAULT@l + mtMSR r3 + + /* IVPR initialization.*/ + e_lis r3, __ivpr_base__@h + e_or2i r3, __ivpr_base__@l + mtIVPR r3 + + /* IVORs initialization.*/ + e_lis r3, _unhandled_exception@h + e_or2i r3, _unhandled_exception@l + + mtspr 400, r3 /* IVOR0-15 */ + mtspr 401, r3 + mtspr 402, r3 + mtspr 403, r3 + mtspr 404, r3 + mtspr 405, r3 + mtspr 406, r3 + mtspr 407, r3 + mtspr 408, r3 + mtspr 409, r3 + mtspr 410, r3 + mtspr 411, r3 + mtspr 412, r3 + mtspr 413, r3 + mtspr 414, r3 + mtspr 415, r3 + mtspr 528, r3 /* IVOR32-34 */ + mtspr 529, r3 + mtspr 530, r3 + + se_blr + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _unhandled_exception + .type _unhandled_exception, @function +_unhandled_exception: + se_b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.h new file mode 100644 index 0000000..fb07f22 --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/boot.h @@ -0,0 +1,242 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file boot.h + * @brief Boot parameters for the SPC564Axx. + * @{ + */ + +#ifndef BOOT_H +#define BOOT_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @name MASx registers definitions + * @{ + */ +#define MAS0_TBLMAS_TBL 0x10000000 +#define MAS0_ESEL_MASK 0x000F0000 +#define MAS0_ESEL(n) ((n) << 16) + +#define MAS1_VALID 0x80000000 +#define MAS1_IPROT 0x40000000 +#define MAS1_TID_MASK 0x00FF0000 +#define MAS1_TS 0x00001000 +#define MAS1_TSISE_MASK 0x00000F80 +#define MAS1_TSISE_1K 0x00000000 +#define MAS1_TSISE_2K 0x00000080 +#define MAS1_TSISE_4K 0x00000100 +#define MAS1_TSISE_8K 0x00000180 +#define MAS1_TSISE_16K 0x00000200 +#define MAS1_TSISE_32K 0x00000280 +#define MAS1_TSISE_64K 0x00000300 +#define MAS1_TSISE_128K 0x00000380 +#define MAS1_TSISE_256K 0x00000400 +#define MAS1_TSISE_512K 0x00000480 +#define MAS1_TSISE_1M 0x00000500 +#define MAS1_TSISE_2M 0x00000580 +#define MAS1_TSISE_4M 0x00000600 +#define MAS1_TSISE_8M 0x00000680 +#define MAS1_TSISE_16M 0x00000700 +#define MAS1_TSISE_32M 0x00000780 +#define MAS1_TSISE_64M 0x00000800 +#define MAS1_TSISE_128M 0x00000880 +#define MAS1_TSISE_256M 0x00000900 +#define MAS1_TSISE_512M 0x00000980 +#define MAS1_TSISE_1G 0x00000A00 +#define MAS1_TSISE_2G 0x00000A80 +#define MAS1_TSISE_4G 0x00000B00 + +#define MAS2_EPN_MASK 0xFFFFFC00 +#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK) +#define MAS2_EBOOK 0x00000000 +#define MAS2_VLE 0x00000020 +#define MAS2_W 0x00000010 +#define MAS2_I 0x00000008 +#define MAS2_M 0x00000004 +#define MAS2_G 0x00000002 +#define MAS2_E 0x00000001 + +#define MAS3_RPN_MASK 0xFFFFFC00 +#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK) +#define MAS3_U0 0x00000200 +#define MAS3_U1 0x00000100 +#define MAS3_U2 0x00000080 +#define MAS3_U3 0x00000040 +#define MAS3_UX 0x00000020 +#define MAS3_SX 0x00000010 +#define MAS3_UW 0x00000008 +#define MAS3_SW 0x00000004 +#define MAS3_UR 0x00000002 +#define MAS3_SR 0x00000001 +/** @} */ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BPRED_MASK 0x00000006 +#define BUCSR_BPRED_0 0x00000000 +#define BUCSR_BPRED_1 0x00000002 +#define BUCSR_BPRED_2 0x00000004 +#define BUCSR_BPRED_3 0x00000006 +#define BUCSR_BALLOC_MASK 0x00000030 +#define BUCSR_BALLOC_0 0x00000000 +#define BUCSR_BALLOC_1 0x00000010 +#define BUCSR_BALLOC_2 0x00000020 +#define BUCSR_BALLOC_3 0x00000030 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name LICSR1 registers definitions + * @{ + */ +#define LICSR1_ICE 0x00000001 +#define LICSR1_ICINV 0x00000002 +#define LICSR1_ICORG 0x00000010 +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_UCLE 0x04000000 +#define MSR_SPE 0x02000000 +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_FP 0x00002000 +#define MSR_ME 0x00001000 +#define MSR_FE0 0x00000800 +#define MSR_DE 0x00000200 +#define MSR_FE1 0x00000100 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/* + * TLB default settings. + */ +#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0)) +#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K) +#define TLB0_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE) +#define TLB0_MAS3 (MAS3_RPN(0x40000000) | \ + MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ + MAS3_UR | MAS3_SR) + +#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1)) +#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M) +#define TLB1_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE) +#define TLB1_MAS3 (MAS3_RPN(0x00000000) | \ + MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ + MAS3_UR | MAS3_SR) + +#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2)) +#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I) +#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3)) +#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I) +#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4)) +#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB4_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I) +#define TLB4_MAS3 (MAS3_RPN(0xFFF00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +/* + * BUCSR default settings. + */ +#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \ + BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI) +#endif + +/* + * LICSR1 default settings. + */ +#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG) +#endif + +/* + * MSR default settings. + */ +#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME) +#endif + +/* + * Boot default settings. + */ +#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) +#define BOOT_PERFORM_CORE_INIT 1 +#endif + +/* + * VLE mode default settings. + */ +#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) +#define BOOT_USE_VLE 1 +#endif + +/* + * RAM relocation flag. + */ +#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) +#define BOOT_RELOCATE_IN_RAM 0 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* BOOT_H */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/intc.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/intc.h new file mode 100644 index 0000000..d30418f --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/intc.h @@ -0,0 +1,93 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC564Axx/intc.h + * @brief SPC564Axx INTC module header. + * + * @addtogroup INTC + * @{ + */ + +#ifndef INTC_H +#define INTC_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @name INTC addresses + * @{ + */ +#define INTC_BASE 0xFFF48000 +#define INTC_IACKR_ADDR (INTC_BASE + 0x10) +#define INTC_EOIR_ADDR (INTC_BASE + 0x18) +/** @} */ + +/** + * @brief INTC priority levels. + */ +#define INTC_PRIORITY_LEVELS 16U + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/** + * @name INTC-related macros + * @{ + */ +#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0))) +#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t))))) +#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t))))) +#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t))))) +#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t))))) +/** @} */ + +/** + * @brief Core selection macros for PSR register. + */ +#define INTC_PSR_CORE0 0x00 + +/** + * @brief PSR register content helper + */ +#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* INTC_H */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/ppcparams.h b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/ppcparams.h new file mode 100644 index 0000000..cf598fd --- /dev/null +++ b/ChibiOS_20.3.2/os/common/startup/e200/devices/SPC564Axx/ppcparams.h @@ -0,0 +1,83 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC564Axx/ppcparams.h + * @brief PowerPC parameters for the SPC564Axx. + * + * @defgroup PPC_SPC564Axx SPC564Axx Specific Parameters + * @ingroup PPC_SPECIFIC + * @details This file contains the PowerPC specific parameters for the + * SPC564Axx platform. + * @{ + */ + +#ifndef PPCPARAMS_H +#define PPCPARAMS_H + +/** + * @brief Family identification macro. + */ +#define PPC_SPC564Axx + +/** + * @brief PPC core model. + */ +#define PPC_VARIANT PPC_VARIANT_e200z4 + +/** + * @brief Number of cores. + */ +#define PPC_CORE_NUMBER 1 + +/** + * @brief Number of writable bits in IVPR register. + */ +#define PPC_IVPR_BITS 16 + +/** + * @brief IVORx registers support. + */ +#define PPC_SUPPORTS_IVORS TRUE + +/** + * @brief Book E instruction set support. + */ +#define PPC_SUPPORTS_BOOKE TRUE + +/** + * @brief VLE instruction set support. + */ +#define PPC_SUPPORTS_VLE TRUE + +/** + * @brief Supports VLS Load/Store Multiple Volatile instructions. + */ +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER TRUE + +/** + * @brief Number of interrupt sources. + */ +#define PPC_NUM_VECTORS 486 + +#endif /* PPCPARAMS_H */ + +/** @} */ -- cgit v1.2.3