From 48026bb824fd2d9cfb00ecd040db6ef3a416bae9 Mon Sep 17 00:00:00 2001 From: Clyne Sullivan Date: Fri, 22 Jan 2021 21:43:36 -0500 Subject: upload initial port --- ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/cache.h | 160 +++++++++++++++ .../os/hal/ports/common/ARMCMx/mpu_v7m.h | 228 +++++++++++++++++++++ ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/nvic.c | 114 +++++++++++ ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/nvic.h | 88 ++++++++ 4 files changed, 590 insertions(+) create mode 100644 ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/cache.h create mode 100644 ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/mpu_v7m.h create mode 100644 ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/nvic.c create mode 100644 ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/nvic.h (limited to 'ChibiOS_20.3.2/os/hal/ports/common') diff --git a/ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/cache.h b/ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/cache.h new file mode 100644 index 0000000..52a92e7 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/cache.h @@ -0,0 +1,160 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file common/ARMCMx/cache.h + * @brief Cortex-Mx cache support macros and structures. + * + * @addtogroup COMMON_ARMCMx_CACHE + * @{ + */ + +#ifndef CACHE_H +#define CACHE_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#if defined(__DCACHE_PRESENT) || defined(__DOXYGEN__) +/** + * @brief Data cache line size, zero if there is no data cache. + */ +#define CACHE_LINE_SIZE 32U +#else +#define CACHE_LINE_SIZE 0U +#endif + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +#if defined(__DCACHE_PRESENT) || defined(__DOXYGEN__) +#if (__DCACHE_PRESENT != 0) || defined(__DOXYGEN__) +/** + * @brief Aligns the specified size to a multiple of cache line size. + * @note This macros assumes that the size of the type @p t is a power of + * two and not greater than @p CACHE_LINE_SIZE. + * + * @param[in] t type of the buffer element + * @param[in] n number of buffer elements + */ +#define CACHE_SIZE_ALIGN(t, n) \ + ((((((n) * sizeof (t)) - 1U) | (CACHE_LINE_SIZE - 1U)) + 1U) / sizeof (t)) + +/** + * @brief Invalidates the data cache lines overlapping a memory buffer. + * @details This function is meant to make sure that data written in + * data cache is invalidated. + * @note On devices without data cache this function does nothing. + * @note The function does not consider the lower 5 bits of addresses, + * the buffers are meant to be aligned to a 32 bytes boundary or + * adjacent data can be invalidated as side effect. + * + * @param[in] saddr start address of the DMA buffer + * @param[in] n size of the DMA buffer in bytes + * + * @api + */ +#define cacheBufferInvalidate(saddr, n) { \ + uint8_t *start = (uint8_t *)(saddr); \ + uint8_t *end = start + (size_t)(n); \ + __DSB(); \ + while (start < end) { \ + SCB->DCIMVAC = (uint32_t)start; \ + start += CACHE_LINE_SIZE; \ + } \ + __DSB(); \ + __ISB(); \ +} + +/** + * @brief Flushes the data cache lines overlapping a DMA buffer. + * @details This function is meant to make sure that data written in + * data cache is flushed to RAM. + * @note On devices without data cache this function does nothing. + * @note The function does not consider the lower 5 bits of addresses, + * the buffers are meant to be aligned to a 32 bytes boundary or + * adjacent data can be flushed as side effect. + * + * @param[in] saddr start address of the DMA buffer + * @param[in] n size of the DMA buffer in bytes + * + * @api + */ +#define cacheBufferFlush(saddr, n) { \ + uint8_t *start = (uint8_t *)(saddr); \ + uint8_t *end = start + (size_t)(n); \ + __DSB(); \ + while (start < end) { \ + SCB->DCCIMVAC = (uint32_t)start; \ + start += CACHE_LINE_SIZE; \ + } \ + __DSB(); \ + __ISB(); \ +} + +#else /* __DCACHE_PRESENT == 0 */ +#define cacheBufferInvalidate(addr, size) { \ + (void)(addr); \ + (void)(size); \ +} +#define cacheBufferFlush(addr, size) { \ + (void)(addr); \ + (void)(size); \ +} +#endif + +#else /* !defined(__DCACHE_PRESENT) */ +#define CACHE_SIZE_ALIGN(t, n) (n) + +#define cacheBufferInvalidate(addr, size) { \ + (void)(addr); \ + (void)(size); \ +} +#define cacheBufferFlush(addr, size) { \ + (void)(addr); \ + (void)(size); \ +} +#endif + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* CACHE_H */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/mpu_v7m.h b/ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/mpu_v7m.h new file mode 100644 index 0000000..11e691a --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/mpu_v7m.h @@ -0,0 +1,228 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file common/ARMCMx/mpu_v7m.h + * @brief ARMv7-M MPU support macros and structures. + * + * @addtogroup COMMON_ARMCMx_MPUv7M + * @{ + */ + +#ifndef MPUV7M_H +#define MPUV7M_H + +/* Other layers may include another header named mpu.h which is perfectly + compatible, doing a check here to avoid name conflicts.*/ +#ifndef MPU_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name MPU registers definitions + * @{ + */ +#define MPU_TYPE_SEPARATED (1U << 0U) +#define MPU_TYPE_DREGION(n) (((n) >> 8U) & 255U) +#define MPU_TYPE_IREGION(n) (((n) >> 16U) & 255U) + +#define MPU_CTRL_ENABLE (1U << 0U) +#define MPU_CTRL_HFNMIENA (1U << 1U) +#define MPU_CTRL_PRIVDEFENA (1U << 2U) + +#define MPU_RNR_REGION_MASK (255U << 0U) +#define MPU_RNR_REGION(n) ((n) << 0U) + +#define MPU_RBAR_REGION_MASK (15U << 0U) +#define MPU_RBAR_REGION(n) ((n) << 0U) +#define MPU_RBAR_VALID (1U << 4U) +#define MPU_RBAR_ADDR_MASK 0xFFFFFFE0U +#define MPU_RBAR_ADDR(n) ((n) << 5U) + +#define MPU_RASR_ENABLE (1U << 0U) +#define MPU_RASR_SIZE_MASK (31U << 1U) +#define MPU_RASR_SIZE(n) ((n) << 1U) +#define MPU_RASR_SIZE_32 MPU_RASR_SIZE(4U) +#define MPU_RASR_SIZE_64 MPU_RASR_SIZE(5U) +#define MPU_RASR_SIZE_128 MPU_RASR_SIZE(6U) +#define MPU_RASR_SIZE_256 MPU_RASR_SIZE(7U) +#define MPU_RASR_SIZE_512 MPU_RASR_SIZE(8U) +#define MPU_RASR_SIZE_1K MPU_RASR_SIZE(9U) +#define MPU_RASR_SIZE_2K MPU_RASR_SIZE(10U) +#define MPU_RASR_SIZE_4K MPU_RASR_SIZE(11U) +#define MPU_RASR_SIZE_8K MPU_RASR_SIZE(12U) +#define MPU_RASR_SIZE_16K MPU_RASR_SIZE(13U) +#define MPU_RASR_SIZE_32K MPU_RASR_SIZE(14U) +#define MPU_RASR_SIZE_64K MPU_RASR_SIZE(15U) +#define MPU_RASR_SIZE_128K MPU_RASR_SIZE(16U) +#define MPU_RASR_SIZE_256K MPU_RASR_SIZE(17U) +#define MPU_RASR_SIZE_512K MPU_RASR_SIZE(18U) +#define MPU_RASR_SIZE_1M MPU_RASR_SIZE(19U) +#define MPU_RASR_SIZE_2M MPU_RASR_SIZE(20U) +#define MPU_RASR_SIZE_4M MPU_RASR_SIZE(21U) +#define MPU_RASR_SIZE_8M MPU_RASR_SIZE(22U) +#define MPU_RASR_SIZE_16M MPU_RASR_SIZE(23U) +#define MPU_RASR_SIZE_32M MPU_RASR_SIZE(24U) +#define MPU_RASR_SIZE_64M MPU_RASR_SIZE(25U) +#define MPU_RASR_SIZE_128M MPU_RASR_SIZE(26U) +#define MPU_RASR_SIZE_256M MPU_RASR_SIZE(27U) +#define MPU_RASR_SIZE_512M MPU_RASR_SIZE(28U) +#define MPU_RASR_SIZE_1G MPU_RASR_SIZE(29U) +#define MPU_RASR_SIZE_2G MPU_RASR_SIZE(30U) +#define MPU_RASR_SIZE_4G MPU_RASR_SIZE(31U) +#define MPU_RASR_SRD_MASK (255U << 8U) +#define MPU_RASR_SRD(n) ((n) << 8U) +#define MPU_RASR_SRD_ALL (0U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB0 (1U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB1 (2U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB2 (4U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB3 (8U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB4 (16U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB5 (32U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB6 (64U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB7 (128U << 8U) +#define MPU_RASR_ATTR_B (1U << 16U) +#define MPU_RASR_ATTR_C (1U << 17U) +#define MPU_RASR_ATTR_S (1U << 18U) +#define MPU_RASR_ATTR_TEX_MASK (7U << 19U) +#define MPU_RASR_ATTR_TEX(n) ((n) << 19U) +#define MPU_RASR_ATTR_AP_MASK (7U << 24U) +#define MPU_RASR_ATTR_AP(n) ((n) << 24U) +#define MPU_RASR_ATTR_AP_NA_NA (0U << 24U) +#define MPU_RASR_ATTR_AP_RW_NA (1U << 24U) +#define MPU_RASR_ATTR_AP_RW_RO (2U << 24U) +#define MPU_RASR_ATTR_AP_RW_RW (3U << 24U) +#define MPU_RASR_ATTR_AP_RO_NA (5U << 24U) +#define MPU_RASR_ATTR_AP_RO_RO (6U << 24U) +#define MPU_RASR_ATTR_XN (1U << 28U) +/** @} */ + +/** + * @name Region attributes + * @{ + */ +#define MPU_RASR_ATTR_STRONGLY_ORDERED (MPU_RASR_ATTR_TEX(0)) +#define MPU_RASR_ATTR_SHARED_DEVICE (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B) +#define MPU_RASR_ATTR_CACHEABLE_WT_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_C) +#define MPU_RASR_ATTR_CACHEABLE_WB_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C) +#define MPU_RASR_ATTR_NON_CACHEABLE (MPU_RASR_ATTR_TEX(1)) +#define MPU_RASR_ATTR_CACHEABLE_WB_WA (MPU_RASR_ATTR_TEX(1) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C) +#define MPU_RASR_ATTR_NON_SHARED_DEVICE (MPU_RASR_ATTR_TEX(2)) +/** @} */ + +/** + * @name Region identifiers + * @{ + */ +#define MPU_REGION_0 0U +#define MPU_REGION_1 1U +#define MPU_REGION_2 2U +#define MPU_REGION_3 3U +#define MPU_REGION_4 4U +#define MPU_REGION_5 5U +#define MPU_REGION_6 6U +#define MPU_REGION_7 7U +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Enables the MPU. + * @note MEMFAULENA is enabled in SCB_SHCSR. + * + * @param[in] ctrl MPU control modes as defined in @p MPU_CTRL register, + * the enable bit is enforced + * + * @api + */ +#define mpuEnable(ctrl) { \ + MPU->CTRL = ((uint32_t)ctrl) | MPU_CTRL_ENABLE; \ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; \ +} + +/** + * @brief Disables the MPU. + * @note MEMFAULENA is disabled in SCB_SHCSR. + * + * @api + */ +#define mpuDisable() { \ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; \ + MPU->CTRL = 0; \ +} + +/** + * @brief Configures an MPU region. + * + * @param[in] region the region number + * @param[in] address start address of the region, note, there are alignment + * constraints + * @param[in] attribs attributes mask as defined in @p MPU_RASR register + * + * @api + */ +#define mpuConfigureRegion(region, addr, attribs) { \ + MPU->RNR = ((uint32_t)region); \ + MPU->RBAR = ((uint32_t)addr); \ + MPU->RASR = ((uint32_t)attribs); \ +} + +/** + * @brief Changes an MPU region base address. + * + * @param[in] region the region number + * @param[in] address start address of the region, note, there are alignment + * constraints + * + * @api + */ +#define mpuSetRegionAddress(region, addr) { \ + MPU->RNR = ((uint32_t)region); \ + MPU->RBAR = ((uint32_t)addr); \ +} + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* MPU_H */ + +#endif /* MPUV7M_H */ + +/** @} */ diff --git a/ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/nvic.c b/ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/nvic.c new file mode 100644 index 0000000..b30c564 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/nvic.c @@ -0,0 +1,114 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file common/ARMCMx/nvic.c + * @brief Cortex-Mx NVIC support code. + * + * @addtogroup COMMON_ARMCMx_NVIC + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Sets the priority of an interrupt handler and enables it. + * + * @param[in] n the interrupt number + * @param[in] prio the interrupt priority + */ +void nvicEnableVector(uint32_t n, uint32_t prio) { + +#if defined(__CORE_CM0_H_GENERIC) || defined(__CORE_CM0PLUS_H_GENERIC) + NVIC->IP[_IP_IDX(n)] = (NVIC->IP[_IP_IDX(n)] & ~(0xFFU << _BIT_SHIFT(n))) | + (NVIC_PRIORITY_MASK(prio) << _BIT_SHIFT(n)); +#else + NVIC->IP[n] = NVIC_PRIORITY_MASK(prio); +#endif + NVIC->ICPR[n >> 5U] = 1U << (n & 0x1FU); + NVIC->ISER[n >> 5U] = 1U << (n & 0x1FU); +} + +/** + * @brief Disables an interrupt handler. + * + * @param[in] n the interrupt number + */ +void nvicDisableVector(uint32_t n) { + + NVIC->ICER[n >> 5U] = 1U << (n & 0x1FU); +#if defined(__CORE_CM0_H_GENERIC) || defined(__CORE_CM0PLUS_H_GENERIC) + NVIC->IP[_IP_IDX(n)] = NVIC->IP[_IP_IDX(n)] & ~(0xFFU << _BIT_SHIFT(n)); +#else + NVIC->IP[n] = 0U; +#endif +} + +/** + * @brief Changes the priority of a system handler. + * + * @param[in] handler the system handler number + * @param[in] prio the system handler priority + */ +void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio) { + + osalDbgCheck(handler < 12U); + +#if defined(__CORE_CM0_H_GENERIC) + SCB->SHP[_SHP_IDX(handler)] = (SCB->SHP[_SHP_IDX(handler)] & ~(0xFFU << _BIT_SHIFT(handler))) | + (NVIC_PRIORITY_MASK(prio) << _BIT_SHIFT(handler)); +#elif defined(__CORE_CM7_H_GENERIC) + SCB->SHPR[handler] = NVIC_PRIORITY_MASK(prio); +#else + SCB->SHP[handler] = NVIC_PRIORITY_MASK(prio); +#endif +} + +/** + * @brief Clears a pending interrupt source. + * + * @param[in] n the interrupt number + */ +void nvicClearPending(uint32_t n) { + + NVIC->ICPR[n >> 5] = 1 << (n & 0x1F); +} + +/** @} */ diff --git a/ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/nvic.h b/ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/nvic.h new file mode 100644 index 0000000..88e32a3 --- /dev/null +++ b/ChibiOS_20.3.2/os/hal/ports/common/ARMCMx/nvic.h @@ -0,0 +1,88 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file common/ARMCMx/nvic.h + * @brief Cortex-Mx NVIC support macros and structures. + * + * @addtogroup COMMON_ARMCMx_NVIC + * @{ + */ + +#ifndef NVIC_H +#define NVIC_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name System vectors numbers + * @{ + */ +#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */ +#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */ +#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */ +#define HANDLER_RESERVED_3 3 +#define HANDLER_RESERVED_4 4 +#define HANDLER_RESERVED_5 5 +#define HANDLER_RESERVED_6 6 +#define HANDLER_SVCALL 7 /**< SVCALL vector id. */ +#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */ +#define HANDLER_RESERVED_9 9 +#define HANDLER_PENDSV 10 /**< PENDSV vector id. */ +#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Priority level to priority mask conversion macro. + */ +#define NVIC_PRIORITY_MASK(prio) ((prio) << (8U - (unsigned)__NVIC_PRIO_BITS)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void nvicEnableVector(uint32_t n, uint32_t prio); + void nvicDisableVector(uint32_t n); + void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio); + void nvicClearPending(uint32_t n); +#ifdef __cplusplus +} +#endif + +#endif /* NVIC_H */ + +/** @} */ -- cgit v1.2.3