From 564e20975b670d4bee1de525e9a25c33730fd7c2 Mon Sep 17 00:00:00 2001 From: Clyne Sullivan Date: Sat, 23 Jan 2021 09:59:11 -0500 Subject: untested port cleanup; add sclock; up cpu to 480M --- ChibiOS_20.3.2/os/hal/ports/STM32/STM32H7xx/hal_lld.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'ChibiOS_20.3.2/os/hal') diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32H7xx/hal_lld.h index b1b9a42..af36372 100644 --- a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32H7xx/hal_lld.h +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32H7xx/hal_lld.h @@ -1821,8 +1821,8 @@ /** * @brief PLL1 DIVP field. */ -#if ((STM32_PLL1_DIVP_VALUE >= 2) && (STM32_PLL1_DIVP_VALUE <= 128) && \ - ((STM32_PLL1_DIVP_VALUE & 1U) == 0U)) || \ +#if ((STM32_PLL1_DIVP_VALUE >= 1) && (STM32_PLL1_DIVP_VALUE <= 128) && \ + ((STM32_PLL1_DIVP_VALUE & 1U) == 0U || STM32_PLL1_DIVP_VALUE == 1)) || \ defined(__DOXYGEN__) #define STM32_PLL1_DIVP ((STM32_PLL1_DIVP_VALUE - 1U) << 9U) #else -- cgit v1.2.3