From e132d52adf52b91cc44741c9d13c178219d7a5f5 Mon Sep 17 00:00:00 2001 From: Clyne Sullivan Date: Sun, 24 Jan 2021 13:16:20 -0500 Subject: error recv. draft; add trig/math funcs --- source/cordic.cpp | 94 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 source/cordic.cpp (limited to 'source/cordic.cpp') diff --git a/source/cordic.cpp b/source/cordic.cpp new file mode 100644 index 0000000..2a44015 --- /dev/null +++ b/source/cordic.cpp @@ -0,0 +1,94 @@ +#include "cordic.hpp" +#include "hal.h" + +namespace math { + +void init() +{ + RCC->AHB2ENR |= RCC_AHB2ENR_CORDICEN; +} + +static void prepare() { + while (CORDIC->CSR & CORDIC_CSR_RRDY) + asm("mov r0, %0" :: "r" (CORDIC->RDATA)); +} +static uint32_t dtoq(double in) { + double res = in * 0x7FFFFFFF; + int32_t resi = res; + return resi; +} +static double qtod(uint32_t in) { + int32_t ini = in; + double res = ini; + return res / 0x7FFFFFFF; +} + +__attribute__((naked)) +double mod(double n, double) { + asm("vdiv.f64 d2, d0, d1;" + "vrintz.f64 d2;" + "vmul.f64 d1, d1, d2;" + "vsub.f64 d0, d0, d1;" + "bx lr"); + return n; +} + +double cos(double x) { + x = (mod(x, 2 * math::PI) - math::PI) / math::PI; + prepare(); + CORDIC->CSR = CORDIC_CSR_NARGS | CORDIC_CSR_NRES | + (6 << CORDIC_CSR_PRECISION_Pos) | + (0 << CORDIC_CSR_FUNC_Pos); + + auto in = dtoq(x); + CORDIC->WDATA = in; + CORDIC->WDATA = in & 0x7FFFFFFF; + while (!(CORDIC->CSR & CORDIC_CSR_RRDY)); + + double cosx = qtod(CORDIC->RDATA) / x; + in = CORDIC->RDATA; + return cosx; +} + +double sin(double x) { + x = (mod(x, 2 * math::PI) - math::PI) / math::PI; + prepare(); + CORDIC->CSR = CORDIC_CSR_NARGS | CORDIC_CSR_NRES | + (6 << CORDIC_CSR_PRECISION_Pos) | + (1 << CORDIC_CSR_FUNC_Pos); + + auto in = dtoq(x); + CORDIC->WDATA = in; + CORDIC->WDATA = in & 0x7FFFFFFF; + while (!(CORDIC->CSR & CORDIC_CSR_RRDY)); + + double sinx = qtod(CORDIC->RDATA) / x; + in = CORDIC->RDATA; + return sinx; +} + +double tan(double x) { + x = (mod(x, 2 * math::PI) - math::PI) / math::PI; + prepare(); + CORDIC->CSR = CORDIC_CSR_NARGS | CORDIC_CSR_NRES | + (6 << CORDIC_CSR_PRECISION_Pos) | + (1 << CORDIC_CSR_FUNC_Pos); + + auto in = dtoq(x); + CORDIC->WDATA = in; + CORDIC->WDATA = in & 0x7FFFFFFF; + while (!(CORDIC->CSR & CORDIC_CSR_RRDY)); + + double sinx = qtod(CORDIC->RDATA) / x; + double tanx = sinx * x / qtod(CORDIC->RDATA); + return tanx; +} + +__attribute__((naked)) +double sqrt(double x) { + asm("vsqrt.f64 d0, d0; bx lr"); + return x; +} + +} + -- cgit v1.2.3 From 1a14ef827ed99a814b00d8ea4b98b8633582b945 Mon Sep 17 00:00:00 2001 From: Clyne Sullivan Date: Mon, 25 Jan 2021 18:13:51 -0500 Subject: fix trig funcs; idle sleep w/ button to wake for debug --- Makefile | 374 +++++++++++++++++++++++++++--------------------------- source/cordic.cpp | 62 +++++---- source/main.cpp | 14 ++ 3 files changed, 236 insertions(+), 214 deletions(-) (limited to 'source/cordic.cpp') diff --git a/Makefile b/Makefile index e560cfc..efb47ad 100644 --- a/Makefile +++ b/Makefile @@ -1,187 +1,187 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 --specs=nosys.specs -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -std=c++17 -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data. -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# Linker extra options here. -ifeq ($(USE_LDOPT),) - USE_LDOPT = -endif - -# Enable this if you want link time optimizations (LTO). -ifeq ($(USE_LTO),) - USE_LTO = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# If enabled, this option makes the build process faster by not compiling -# modules not used in the current configuration. -ifeq ($(USE_SMART_BUILD),) - USE_SMART_BUILD = yes -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Stack size to be allocated to the Cortex-M process stack. This stack is -# the stack used by the main() thread. -ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 -endif - -# Stack size to the allocated to the Cortex-M main/exceptions stack. This -# stack is used for processing interrupts and exceptions. -ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x400 -endif - -# Enables the use of FPU (no, softfp, hard). -ifeq ($(USE_FPU),) - USE_FPU = hard -endif - -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-d16 -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, target, sources and paths -# - -# Define project name here -PROJECT = ch - -# Target settings. -MCU = cortex-m7 - -# Imported source files and paths. -CHIBIOS := ./ChibiOS_20.3.2 -CONFDIR := ./cfg -BUILDDIR := ./build -DEPDIR := ./.dep - -# Licensing files. -include $(CHIBIOS)/os/license/license.mk -# Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk -# HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/platform.mk -include ./board/board.mk -include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk -# RTOS files (optional). -include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk -# Other files (optional). -#include $(CHIBIOS)/test/lib/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk - -# Define linker script file here -LDSCRIPT= STM32H723xG.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(ALLCSRC) - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = $(ALLCPPSRC) - -# List ASM source files here. -ASMSRC = $(ALLASMSRC) - -# List ASM with preprocessor source files here. -ASMXSRC = $(ALLXASMSRC) - -# Inclusion directories. -INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) - -# Define C warning options here. -CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes - -# Define C++ warning options here. -CPPWARN = -Wall -Wextra -Wundef - -# -# Project, target, sources and paths -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = -DCORTEX_ENABLE_WFI_IDLE=FALSE -DPORT_USE_SYSCALL=TRUE - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - -############################################################################## -# Common rules -# - -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk -include $(RULESPATH)/arm-none-eabi.mk -include $(RULESPATH)/rules.mk - -# -# Common rules -############################################################################## - -############################################################################## -# Custom rules -# - -# -# Custom rules -############################################################################## +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 --specs=nosys.specs +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -std=c++17 -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = hard +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m7 + +# Imported source files and paths. +CHIBIOS := ./ChibiOS_20.3.2 +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/platform.mk +include ./board/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/test/lib/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here +LDSCRIPT= STM32H723xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DCORTEX_ENABLE_WFI_IDLE=TRUE -DPORT_USE_SYSCALL=TRUE + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/source/cordic.cpp b/source/cordic.cpp index 2a44015..4852563 100644 --- a/source/cordic.cpp +++ b/source/cordic.cpp @@ -12,71 +12,79 @@ static void prepare() { while (CORDIC->CSR & CORDIC_CSR_RRDY) asm("mov r0, %0" :: "r" (CORDIC->RDATA)); } -static uint32_t dtoq(double in) { - double res = in * 0x7FFFFFFF; - int32_t resi = res; - return resi; + +static uint32_t dtoq(double) { + uint32_t res; + asm("vcvt.s32.f64 d0, d0, #31;" + "vmov %0, r5, d0" + : "=r" (res)); + return res; } -static double qtod(uint32_t in) { - int32_t ini = in; - double res = ini; - return res / 0x7FFFFFFF; +__attribute__((naked)) +static double qtod(uint32_t) { + asm("eor r1, r1;" + "vmov d0, r0, r1;" + "vcvt.f64.s32 d0, d0, #31;" + "bx lr"); + return 0; } - __attribute__((naked)) -double mod(double n, double) { +double mod(double, double) { asm("vdiv.f64 d2, d0, d1;" "vrintz.f64 d2;" "vmul.f64 d1, d1, d2;" "vsub.f64 d0, d0, d1;" "bx lr"); - return n; + return 0; } double cos(double x) { - x = (mod(x, 2 * math::PI) - math::PI) / math::PI; + x = mod(x, 2 * math::PI) / math::PI; + auto input = dtoq(x > 1. ? x - 2 : x); + prepare(); CORDIC->CSR = CORDIC_CSR_NARGS | CORDIC_CSR_NRES | (6 << CORDIC_CSR_PRECISION_Pos) | (0 << CORDIC_CSR_FUNC_Pos); - auto in = dtoq(x); - CORDIC->WDATA = in; - CORDIC->WDATA = in & 0x7FFFFFFF; + CORDIC->WDATA = input; + CORDIC->WDATA = input; while (!(CORDIC->CSR & CORDIC_CSR_RRDY)); double cosx = qtod(CORDIC->RDATA) / x; - in = CORDIC->RDATA; + [[maybe_unused]] auto sinx = CORDIC->RDATA; return cosx; } double sin(double x) { - x = (mod(x, 2 * math::PI) - math::PI) / math::PI; + x = mod(x, 2 * math::PI) / math::PI; + auto input = dtoq(x > 1. ? x - 2 : x); + prepare(); CORDIC->CSR = CORDIC_CSR_NARGS | CORDIC_CSR_NRES | (6 << CORDIC_CSR_PRECISION_Pos) | (1 << CORDIC_CSR_FUNC_Pos); - auto in = dtoq(x); - CORDIC->WDATA = in; - CORDIC->WDATA = in & 0x7FFFFFFF; + CORDIC->WDATA = input; + CORDIC->WDATA = input; while (!(CORDIC->CSR & CORDIC_CSR_RRDY)); double sinx = qtod(CORDIC->RDATA) / x; - in = CORDIC->RDATA; + [[maybe_unused]] auto cosx = CORDIC->RDATA; return sinx; } double tan(double x) { - x = (mod(x, 2 * math::PI) - math::PI) / math::PI; + x = mod(x, 2 * math::PI) / math::PI; + auto input = dtoq(x > 1. ? x - 2 : x); + prepare(); CORDIC->CSR = CORDIC_CSR_NARGS | CORDIC_CSR_NRES | (6 << CORDIC_CSR_PRECISION_Pos) | (1 << CORDIC_CSR_FUNC_Pos); - auto in = dtoq(x); - CORDIC->WDATA = in; - CORDIC->WDATA = in & 0x7FFFFFFF; + CORDIC->WDATA = input; + CORDIC->WDATA = input; while (!(CORDIC->CSR & CORDIC_CSR_RRDY)); double sinx = qtod(CORDIC->RDATA) / x; @@ -85,9 +93,9 @@ double tan(double x) { } __attribute__((naked)) -double sqrt(double x) { +double sqrt(double) { asm("vsqrt.f64 d0, d0; bx lr"); - return x; + return 0.; } } diff --git a/source/main.cpp b/source/main.cpp index a682cfe..97612f4 100644 --- a/source/main.cpp +++ b/source/main.cpp @@ -75,6 +75,8 @@ int main() halInit(); chSysInit(); + palSetLineMode(LINE_BUTTON, PAL_MODE_INPUT); + // Enable FPU SCB->CPACR |= 0xF << 20; @@ -353,6 +355,18 @@ THD_FUNCTION(Thread1, arg) palClearLine(led); chThdSleepMilliseconds(delay); + if (run_status == RunStatus::Idle && palReadLine(LINE_BUTTON)) { + palSetLine(LINE_LED_RED); + palSetLine(LINE_LED_YELLOW); + asm("cpsid i"); + while (!palReadLine(LINE_BUTTON)) + asm("nop"); + asm("cpsie i"); + palClearLine(LINE_LED_RED); + palClearLine(LINE_LED_YELLOW); + chThdSleepMilliseconds(500); + } + if (auto err = EM.hasError(); err ^ erroron) { erroron = err; if (err) -- cgit v1.2.3 From 1a7d45b9130251119874df8b15424ec41306d8f2 Mon Sep 17 00:00:00 2001 From: Clyne Sullivan Date: Wed, 10 Mar 2021 19:42:18 -0500 Subject: support H7 and L4; use second ADC for input --- Makefile | 39 +- STM32L476xG.ld | 116 ++++ board/board.c | 266 -------- board/board.h | 1642 ----------------------------------------------- board/board.mk | 12 +- board/board_h7.c | 266 ++++++++ board/board_l4.c | 281 ++++++++ board/h7/board.h | 1642 +++++++++++++++++++++++++++++++++++++++++++++++ board/l4/board.h | 1505 +++++++++++++++++++++++++++++++++++++++++++ cfg/mcuconf.h | 490 +------------- cfg/mcuconf_h7.h | 483 ++++++++++++++ cfg/mcuconf_l4.h | 360 +++++++++++ gui/stmdsp.cpp | 10 +- gui/stmdsp.hpp | 11 +- gui/wxmain.cpp | 78 ++- source/adc.cpp | 157 +++-- source/adc.hpp | 7 +- source/cordic.cpp | 18 +- source/cordic.hpp | 3 +- source/main.cpp | 97 ++- source/samplebuffer.hpp | 3 +- source/sclock.cpp | 8 + source/usbcfg.c | 4 + 23 files changed, 5015 insertions(+), 2483 deletions(-) create mode 100644 STM32L476xG.ld delete mode 100644 board/board.c delete mode 100644 board/board.h create mode 100644 board/board_h7.c create mode 100644 board/board_l4.c create mode 100644 board/h7/board.h create mode 100644 board/l4/board.h create mode 100644 cfg/mcuconf_h7.h create mode 100644 cfg/mcuconf_l4.h (limited to 'source/cordic.cpp') diff --git a/Makefile b/Makefile index c680ac8..24bda87 100644 --- a/Makefile +++ b/Makefile @@ -3,6 +3,9 @@ # NOTE: Can be overridden externally. # +# Set the target platform, either L4, G4, or H7 +TARGET_PLATFORM = L4 + # Compiler options here. ifeq ($(USE_OPT),) USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 --specs=nosys.specs @@ -55,13 +58,13 @@ endif # Stack size to be allocated to the Cortex-M process stack. This stack is # the stack used by the main() thread. ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x1000 + USE_PROCESS_STACKSIZE = 1024 endif # Stack size to the allocated to the Cortex-M main/exceptions stack. This # stack is used for processing interrupts and exceptions. ifeq ($(USE_EXCEPTIONS_STACKSIZE),) - USE_EXCEPTIONS_STACKSIZE = 0x1000 + USE_EXCEPTIONS_STACKSIZE = 2048 endif # Enables the use of FPU (no, softfp, hard). @@ -71,8 +74,13 @@ endif # FPU-related options. ifeq ($(USE_FPU_OPT),) +ifeq ($(TARGET_PLATFORM),H7) USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-d16 endif +ifeq ($(TARGET_PLATFORM),L4) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif +endif # # Architecture or project specific options @@ -86,7 +94,11 @@ endif PROJECT = ch # Target settings. -MCU = cortex-m7 +ifeq ($(TARGET_PLATFORM),H7) + MCU = cortex-m7 +else + MCU = cortex-m4 +endif # Imported source files and paths. CHIBIOS := ./ChibiOS_20.3.2 @@ -97,10 +109,18 @@ DEPDIR := ./.dep # Licensing files. include $(CHIBIOS)/os/license/license.mk # Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk +ifeq ($(TARGET_PLATFORM),H7) + include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk +else + include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk +endif # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/platform.mk +ifeq ($(TARGET_PLATFORM),H7) + include $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/platform.mk +else + include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk +endif include ./board/board.mk include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk # RTOS files (optional). @@ -114,7 +134,11 @@ include $(CHIBIOS)/tools/mk/autobuild.mk #include $(CHIBIOS)/test/oslib/oslib_test.mk # Define linker script file here -LDSCRIPT= STM32H723xG.ld +ifeq ($(TARGET_PLATFORM),H7) + LDSCRIPT = STM32H723xG.ld +else + LDSCRIPT = STM32L476xG.ld +endif # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -150,7 +174,8 @@ CPPWARN = -Wall -Wextra -Wundef -pedantic -Wno-volatile # List all user C define here, like -D_DEBUG=1 UDEFS = -DCORTEX_ENABLE_WFI_IDLE=TRUE \ -DPORT_USE_SYSCALL=TRUE \ - -DPORT_USE_GUARD_MPU_REGION=MPU_REGION_0 + -DPORT_USE_GUARD_MPU_REGION=MPU_REGION_0 \ + -DTARGET_PLATFORM_$(TARGET_PLATFORM) # Define ASM defines here UADEFS = diff --git a/STM32L476xG.ld b/STM32L476xG.ld new file mode 100644 index 0000000..b3a332d --- /dev/null +++ b/STM32L476xG.ld @@ -0,0 +1,116 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32L476xG memory setup. + * A total of 1MB of flash is available. + * Firmware uses first 510K, then 2K after is used for unprivileged code. + * A total of 128K of RAM is available. + * SRAM2 (32K) is used for ELF binary loading. + * 32K of SRAM1 is used for system RAM. + * 48K is used for ADC and DAC buffers. + * 16K is used for unprivileged data (incl. 8K stack). + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000, len = 510K /* Flash bank 1 (reduced from 1M to 510K) */ + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 32K /* SRAM (actual total = 96K) */ + ram1 (wx) : org = 0x20008000, len = 48K /* ADC/DAC buffers (16K * 3) */ + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x10000000, len = 32K /* User algorithm */ + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 + flashc (rx) : org = 0x0807F800, len = 2K /* Unprivileged firmware */ + ramc (wx) : org = 0x20014000, len = 16K /* Unprivileged data */ +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +SECTIONS +{ + .convdata : ALIGN(4) + { + *(.convdata) + . = ALIGN(4); + } > ramc + + /*.stacks : ALIGN(4) + { + *(.stacks) + . = ALIGN(4); + } > ram5*/ + + .convcode : ALIGN(4) + { + *(.convcode) + . = ALIGN(4); + } > flashc +} + + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/board/board.c b/board/board.c deleted file mode 100644 index 2868726..0000000 --- a/board/board.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#include "hal.h" -#include "stm32_gpio.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB4(STM32_GPIO_EN_MASK); - rccEnableAHB4(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* CHTODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* CHTODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* CHTODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* CHTODO: Fill the implementation.*/ - return false; -} -#endif - -/** - * @brief Board-specific initialization code. - * @note You can add your board-specific code here. - */ -void boardInit(void) { - -} diff --git a/board/board.h b/board/board.h deleted file mode 100644 index 58ba40e..0000000 --- a/board/board.h +++ /dev/null @@ -1,1642 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Setup for STMicroelectronics STM32 Nucleo144-H743ZI board. - */ - -/* - * Board identifier. - */ -#define BOARD_ST_NUCLEO144_H743ZI -#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-H743ZI" - -/* - * Ethernet PHY type. - */ -#define BOARD_PHY_ID MII_LAN8742A_ID -#define BOARD_PHY_RMII - -/* - * Board oscillators-related settings. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 32768U -#endif - -#define STM32_LSEDRV (3U << 3U) - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 8000000U -#endif - -#define STM32_HSE_BYPASS - -/* - * MCU type as defined in the ST header. - */ -#define STM32H723xx - -/* - * IO pins assignments. - */ -#define GPIOA_PIN0 0U -#define GPIOA_RMII_REF_CLK 1U -#define GPIOA_RMII_MDIO 2U -#define GPIOA_PIN3 3U -#define GPIOA_PIN4 4U -#define GPIOA_PIN5 5U -#define GPIOA_PIN6 6U -#define GPIOA_RMII_CRS_DV 7U -#define GPIOA_USB_SOF 8U -#define GPIOA_MCO1 8U -#define GPIOA_USB_VBUS 9U -#define GPIOA_USB_ID 10U -#define GPIOA_USB_DM 11U -#define GPIOA_USB_DP 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_T_JTDI 15U - -#define GPIOB_LED1 0U -#define GPIOB_LED_GREEN 0U -#define GPIOB_LED 0U -#define GPIOB_PIN1 1U -#define GPIOB_PIN2 2U -#define GPIOB_SWO 3U -#define GPIOB_PIN4 4U -#define GPIOB_PIN5 5U -#define GPIOB_PIN6 6U -#define GPIOB_PIN7 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_RMII_TXD1 13U -#define GPIOB_LED3 14U -#define GPIOB_LED_RED 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_RMII_MDC 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_RMII_RXD0 4U -#define GPIOC_RMII_RXD1 5U -#define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U -#define GPIOC_PIN8 8U -#define GPIOC_PIN9 9U -#define GPIOC_PIN10 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_BUTTON 13U -#define GPIOC_OSC32_IN 14U -#define GPIOC_OSC32_OUT 15U - -#define GPIOD_PIN0 0U -#define GPIOD_PIN1 1U -#define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_USART3_RX 8U -#define GPIOD_STLK_RX 8U -#define GPIOD_USART3_TX 9U -#define GPIOD_STLK_TX 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOE_PIN0 0U -#define GPIOE_LED2 1U -#define GPIOE_LED_YELLOW 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_PIN7 7U -#define GPIOE_PIN8 8U -#define GPIOE_PIN9 9U -#define GPIOE_PIN10 10U -#define GPIOE_PIN11 11U -#define GPIOE_PIN12 12U -#define GPIOE_PIN13 13U -#define GPIOE_PIN14 14U -#define GPIOE_PIN15 15U - -#define GPIOF_PIN0 0U -#define GPIOF_PIN1 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U -#define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U - -#define GPIOG_PIN0 0U -#define GPIOG_PIN1 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_PIN4 4U -#define GPIOG_PIN5 5U -#define GPIOG_USB_FS_PWR_EN 6U -#define GPIOG_USB_FS_OVCR 7U -#define GPIOG_PIN8 8U -#define GPIOG_PIN9 9U -#define GPIOG_PIN10 10U -#define GPIOG_RMII_TX_EN 11U -#define GPIOG_PIN12 12U -#define GPIOG_RMII_TXD0 13U -#define GPIOG_PIN14 14U -#define GPIOG_PIN15 15U - -#define GPIOH_OSC_IN 0U -#define GPIOH_OSC_OUT 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_PIN5 5U -#define GPIOH_PIN6 6U -#define GPIOH_PIN7 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -#define GPIOI_PIN0 0U -#define GPIOI_PIN1 1U -#define GPIOI_PIN2 2U -#define GPIOI_PIN3 3U -#define GPIOI_PIN4 4U -#define GPIOI_PIN5 5U -#define GPIOI_PIN6 6U -#define GPIOI_PIN7 7U -#define GPIOI_PIN8 8U -#define GPIOI_PIN9 9U -#define GPIOI_PIN10 10U -#define GPIOI_PIN11 11U -#define GPIOI_PIN12 12U -#define GPIOI_PIN13 13U -#define GPIOI_PIN14 14U -#define GPIOI_PIN15 15U - -#define GPIOJ_PIN0 0U -#define GPIOJ_PIN1 1U -#define GPIOJ_PIN2 2U -#define GPIOJ_PIN3 3U -#define GPIOJ_PIN4 4U -#define GPIOJ_PIN5 5U -#define GPIOJ_PIN6 6U -#define GPIOJ_PIN7 7U -#define GPIOJ_PIN8 8U -#define GPIOJ_PIN9 9U -#define GPIOJ_PIN10 10U -#define GPIOJ_PIN11 11U -#define GPIOJ_PIN12 12U -#define GPIOJ_PIN13 13U -#define GPIOJ_PIN14 14U -#define GPIOJ_PIN15 15U - -#define GPIOK_PIN0 0U -#define GPIOK_PIN1 1U -#define GPIOK_PIN2 2U -#define GPIOK_PIN3 3U -#define GPIOK_PIN4 4U -#define GPIOK_PIN5 5U -#define GPIOK_PIN6 6U -#define GPIOK_PIN7 7U -#define GPIOK_PIN8 8U -#define GPIOK_PIN9 9U -#define GPIOK_PIN10 10U -#define GPIOK_PIN11 11U -#define GPIOK_PIN12 12U -#define GPIOK_PIN13 13U -#define GPIOK_PIN14 14U -#define GPIOK_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_RMII_REF_CLK PAL_LINE(GPIOA, 1U) -#define LINE_RMII_MDIO PAL_LINE(GPIOA, 2U) -#define LINE_RMII_CRS_DV PAL_LINE(GPIOA, 7U) -#define LINE_USB_SOF PAL_LINE(GPIOA, 8U) -#define LINE_MCO1 PAL_LINE(GPIOA, 8U) -#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U) -#define LINE_USB_ID PAL_LINE(GPIOA, 10U) -#define LINE_USB_DM PAL_LINE(GPIOA, 11U) -#define LINE_USB_DP PAL_LINE(GPIOA, 12U) -#define LINE_SWDIO PAL_LINE(GPIOA, 13U) -#define LINE_SWCLK PAL_LINE(GPIOA, 14U) -#define LINE_T_JTDI PAL_LINE(GPIOA, 15U) -#define LINE_LED1 PAL_LINE(GPIOB, 0U) -#define LINE_LED_GREEN PAL_LINE(GPIOB, 0U) -#define LINE_LED PAL_LINE(GPIOB, 0U) -#define LINE_SWO PAL_LINE(GPIOB, 3U) -#define LINE_LED2 PAL_LINE(GPIOE, 1U) -#define LINE_LED_YELLOW PAL_LINE(GPIOE, 1U) -#define LINE_RMII_TXD1 PAL_LINE(GPIOB, 13U) -#define LINE_LED3 PAL_LINE(GPIOB, 14U) -#define LINE_LED_RED PAL_LINE(GPIOB, 14U) -#define LINE_RMII_MDC PAL_LINE(GPIOC, 1U) -#define LINE_RMII_RXD0 PAL_LINE(GPIOC, 4U) -#define LINE_RMII_RXD1 PAL_LINE(GPIOC, 5U) -#define LINE_BUTTON PAL_LINE(GPIOC, 13U) -#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) -#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) -#define LINE_USART3_RX PAL_LINE(GPIOD, 8U) -#define LINE_STLK_RX PAL_LINE(GPIOD, 8U) -#define LINE_USART3_TX PAL_LINE(GPIOD, 9U) -#define LINE_STLK_TX PAL_LINE(GPIOD, 9U) -#define LINE_USB_FS_PWR_EN PAL_LINE(GPIOG, 6U) -#define LINE_USB_FS_OVCR PAL_LINE(GPIOG, 7U) -#define LINE_RMII_TX_EN PAL_LINE(GPIOG, 11U) -#define LINE_RMII_TXD0 PAL_LINE(GPIOG, 13U) -#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) -#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - PIN0 (input pullup). - * PA1 - RMII_REF_CLK (alternate 11). - * PA2 - RMII_MDIO (alternate 11). - * PA3 - PIN3 (input pullup). - * PA4 - PIN4 (input pullup). - * PA5 - PIN5 (input pullup). - * PA6 - PIN6 (input pullup). - * PA7 - RMII_CRS_DV (alternate 11). - * PA8 - USB_SOF MCO1 (alternate 10). - * PA9 - USB_VBUS (analog). - * PA10 - USB_ID (alternate 10). - * PA11 - USB_DM (alternate 10). - * PA12 - USB_DP (alternate 10). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - T_JTDI (alternate 0). - */ -#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \ - PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\ - PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \ - PIN_MODE_INPUT(GPIOA_PIN3) | \ - PIN_MODE_INPUT(GPIOA_PIN4) | \ - PIN_MODE_INPUT(GPIOA_PIN5) | \ - PIN_MODE_INPUT(GPIOA_PIN6) | \ - PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) |\ - PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \ - PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \ - PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \ - PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \ - PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_ALTERNATE(GPIOA_T_JTDI)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\ - PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) |\ - PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_T_JTDI)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \ - PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \ - PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \ - PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \ - PIN_OSPEED_HIGH(GPIOA_RMII_CRS_DV) | \ - PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \ - PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \ - PIN_OSPEED_HIGH(GPIOA_USB_ID) | \ - PIN_OSPEED_HIGH(GPIOA_USB_DM) | \ - PIN_OSPEED_HIGH(GPIOA_USB_DP) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_HIGH(GPIOA_T_JTDI)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\ - PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOA_RMII_CRS_DV) | \ - PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \ - PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \ - PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \ - PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \ - PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \ - PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ - PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ - PIN_PUPDR_PULLUP(GPIOA_T_JTDI)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ - PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \ - PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \ - PIN_ODR_HIGH(GPIOA_PIN3) | \ - PIN_ODR_HIGH(GPIOA_PIN4) | \ - PIN_ODR_HIGH(GPIOA_PIN5) | \ - PIN_ODR_HIGH(GPIOA_PIN6) | \ - PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) | \ - PIN_ODR_HIGH(GPIOA_USB_SOF) | \ - PIN_ODR_HIGH(GPIOA_USB_VBUS) | \ - PIN_ODR_HIGH(GPIOA_USB_ID) | \ - PIN_ODR_HIGH(GPIOA_USB_DM) | \ - PIN_ODR_HIGH(GPIOA_USB_DP) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_T_JTDI)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \ - PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) | \ - PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOA_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \ - PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \ - PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \ - PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \ - PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_T_JTDI, 0U)) - -/* - * GPIOB setup: - * - * PB0 - LED1 LED_GREEN LED (output pushpull maximum). - * PB1 - PIN1 (input pullup). - * PB2 - PIN2 (input pullup). - * PB3 - SWO (alternate 0). - * PB4 - PIN4 (input pullup). - * PB5 - PIN5 (input pullup). - * PB6 - PIN6 (input pullup). - * PB7 - PIN7 (input pullup). - * PB8 - PIN8 (input pullup). - * PB9 - PIN9 (input pullup). - * PB10 - PIN10 (input pullup). - * PB11 - PIN11 (input pullup). - * PB12 - PIN12 (input pullup). - * PB13 - RMII_TXD1 (alternate 11). - * PB14 - LED3 LED_RED (output pushpull maximum). - * PB15 - PIN15 (input pullup). - */ -#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_LED1) | \ - PIN_MODE_INPUT(GPIOB_PIN1) | \ - PIN_MODE_INPUT(GPIOB_PIN2) | \ - PIN_MODE_ALTERNATE(GPIOB_SWO) | \ - PIN_MODE_INPUT(GPIOB_PIN4) | \ - PIN_MODE_INPUT(GPIOB_PIN5) | \ - PIN_MODE_INPUT(GPIOB_PIN6) | \ - PIN_MODE_INPUT(GPIOB_PIN7) | \ - PIN_MODE_INPUT(GPIOB_PIN8) | \ - PIN_MODE_INPUT(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_ALTERNATE(GPIOB_RMII_TXD1) | \ - PIN_MODE_OUTPUT(GPIOB_LED3) | \ - PIN_MODE_INPUT(GPIOB_PIN15)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_LED1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_RMII_TXD1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_LED1) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN1) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN2) | \ - PIN_OSPEED_HIGH(GPIOB_SWO) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN9) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN10) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN12) | \ - PIN_OSPEED_HIGH(GPIOB_RMII_TXD1) | \ - PIN_OSPEED_HIGH(GPIOB_LED3) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_LED1) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOB_SWO) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOB_RMII_TXD1) | \ - PIN_PUPDR_FLOATING(GPIOB_LED3) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_LED1) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_SWO) | \ - PIN_ODR_HIGH(GPIOB_PIN4) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_PIN6) | \ - PIN_ODR_HIGH(GPIOB_PIN7) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_RMII_TXD1) | \ - PIN_ODR_LOW(GPIOB_LED3) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_LED1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOB_SWO, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN7, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOB_RMII_TXD1, 11U) | \ - PIN_AFIO_AF(GPIOB_LED3, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (input pullup). - * PC1 - RMII_MDC (alternate 11). - * PC2 - PIN2 (input pullup). - * PC3 - PIN3 (input pullup). - * PC4 - RMII_RXD0 (alternate 11). - * PC5 - RMII_RXD1 (alternate 11). - * PC6 - PIN6 (input pullup). - * PC7 - PIN7 (input pullup). - * PC8 - PIN8 (input pullup). - * PC9 - PIN9 (input pullup). - * PC10 - PIN10 (input pullup). - * PC11 - PIN11 (input pullup). - * PC12 - PIN12 (input pullup). - * PC13 - BUTTON (input floating). - * PC14 - OSC32_IN (input floating). - * PC15 - OSC32_OUT (input floating). - */ -#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ - PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \ - PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \ - PIN_MODE_INPUT(GPIOC_PIN6) | \ - PIN_MODE_INPUT(GPIOC_PIN7) | \ - PIN_MODE_INPUT(GPIOC_PIN8) | \ - PIN_MODE_INPUT(GPIOC_PIN9) | \ - PIN_MODE_INPUT(GPIOC_PIN10) | \ - PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_INPUT(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_BUTTON) | \ - PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ - PIN_MODE_INPUT(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | \ - PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \ - PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN6) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN7) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN8) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN9) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN10) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \ - PIN_OSPEED_HIGH(GPIOC_BUTTON) | \ - PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \ - PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \ - PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_RMII_MDC) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \ - PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_BUTTON) | \ - PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ - PIN_ODR_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) | \ - PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) - -/* - * GPIOD setup: - * - * PD0 - PIN0 (input pullup). - * PD1 - PIN1 (input pullup). - * PD2 - PIN2 (input pullup). - * PD3 - PIN3 (input pullup). - * PD4 - PIN4 (input pullup). - * PD5 - PIN5 (input pullup). - * PD6 - PIN6 (input pullup). - * PD7 - PIN7 (input pullup). - * PD8 - USART3_RX STLK_RX (alternate 7). - * PD9 - USART3_TX STLK_TX (alternate 7). - * PD10 - PIN10 (input pullup). - * PD11 - PIN11 (input pullup). - * PD12 - PIN12 (input pullup). - * PD13 - PIN13 (input pullup). - * PD14 - PIN14 (input pullup). - * PD15 - PIN15 (input pullup). - */ -#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ - PIN_MODE_INPUT(GPIOD_PIN1) | \ - PIN_MODE_INPUT(GPIOD_PIN2) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_INPUT(GPIOD_PIN4) | \ - PIN_MODE_INPUT(GPIOD_PIN5) | \ - PIN_MODE_INPUT(GPIOD_PIN6) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \ - PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \ - PIN_MODE_INPUT(GPIOD_PIN10) | \ - PIN_MODE_INPUT(GPIOD_PIN11) | \ - PIN_MODE_INPUT(GPIOD_PIN12) | \ - PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_INPUT(GPIOD_PIN14) | \ - PIN_MODE_INPUT(GPIOD_PIN15)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \ - PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN1) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN6) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \ - PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN12) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN13) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN14) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN15)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \ - PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN15)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ - PIN_ODR_HIGH(GPIOD_PIN1) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_PIN6) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_USART3_RX) | \ - PIN_ODR_HIGH(GPIOD_USART3_TX) | \ - PIN_ODR_HIGH(GPIOD_PIN10) | \ - PIN_ODR_HIGH(GPIOD_PIN11) | \ - PIN_ODR_HIGH(GPIOD_PIN12) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_PIN14) | \ - PIN_ODR_HIGH(GPIOD_PIN15)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \ - PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \ - PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN15, 0U)) - -/* - * GPIOE setup: - * - * PE0 - PIN0 (input pullup). - * PE1 - PIN1 (input pullup). - * PE2 - PIN2 (input pullup). - * PE3 - PIN3 (input pullup). - * PE4 - PIN4 (input pullup). - * PE5 - PIN5 (input pullup). - * PE6 - PIN6 (input pullup). - * PE7 - PIN7 (input pullup). - * PE8 - PIN8 (input pullup). - * PE9 - PIN9 (input pullup). - * PE10 - PIN10 (input pullup). - * PE11 - PIN11 (input pullup). - * PE12 - PIN12 (input pullup). - * PE13 - PIN13 (input pullup). - * PE14 - PIN14 (input pullup). - * PE15 - PIN15 (input pullup). - */ -#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ - PIN_MODE_OUTPUT(GPIOE_LED2) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_INPUT(GPIOE_PIN7) | \ - PIN_MODE_INPUT(GPIOE_PIN8) | \ - PIN_MODE_INPUT(GPIOE_PIN9) | \ - PIN_MODE_INPUT(GPIOE_PIN10) | \ - PIN_MODE_INPUT(GPIOE_PIN11) | \ - PIN_MODE_INPUT(GPIOE_PIN12) | \ - PIN_MODE_INPUT(GPIOE_PIN13) | \ - PIN_MODE_INPUT(GPIOE_PIN14) | \ - PIN_MODE_INPUT(GPIOE_PIN15)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_LED2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | \ - PIN_OSPEED_HIGH(GPIOE_LED2) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN7) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN8) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN9) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN10) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN12) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN13) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN14) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN15)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOE_LED2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN15)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ - PIN_ODR_LOW(GPIOE_LED2) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_PIN7) | \ - PIN_ODR_HIGH(GPIOE_PIN8) | \ - PIN_ODR_HIGH(GPIOE_PIN9) | \ - PIN_ODR_HIGH(GPIOE_PIN10) | \ - PIN_ODR_HIGH(GPIOE_PIN11) | \ - PIN_ODR_HIGH(GPIOE_PIN12) | \ - PIN_ODR_HIGH(GPIOE_PIN13) | \ - PIN_ODR_HIGH(GPIOE_PIN14) | \ - PIN_ODR_HIGH(GPIOE_PIN15)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOE_LED2, 0U)) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN7, 0U) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN15, 0U)) - -/* - * GPIOF setup: - * - * PF0 - PIN0 (input pullup). - * PF1 - PIN1 (input pullup). - * PF2 - PIN2 (input pullup). - * PF3 - PIN3 (input pullup). - * PF4 - PIN4 (input pullup). - * PF5 - PIN5 (input pullup). - * PF6 - PIN6 (input pullup). - * PF7 - PIN7 (input pullup). - * PF8 - PIN8 (input pullup). - * PF9 - PIN9 (input pullup). - * PF10 - PIN10 (input pullup). - * PF11 - PIN11 (input pullup). - * PF12 - PIN12 (input pullup). - * PF13 - PIN13 (input pullup). - * PF14 - PIN14 (input pullup). - * PF15 - PIN15 (input pullup). - */ -#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ - PIN_MODE_INPUT(GPIOF_PIN1) | \ - PIN_MODE_INPUT(GPIOF_PIN2) | \ - PIN_MODE_INPUT(GPIOF_PIN3) | \ - PIN_MODE_INPUT(GPIOF_PIN4) | \ - PIN_MODE_INPUT(GPIOF_PIN5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_INPUT(GPIOF_PIN12) | \ - PIN_MODE_INPUT(GPIOF_PIN13) | \ - PIN_MODE_INPUT(GPIOF_PIN14) | \ - PIN_MODE_INPUT(GPIOF_PIN15)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_PIN0) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN1) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN7) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN8) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN9) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN10) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN12) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN13) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN14) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN15)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN15)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ - PIN_ODR_HIGH(GPIOF_PIN1) | \ - PIN_ODR_HIGH(GPIOF_PIN2) | \ - PIN_ODR_HIGH(GPIOF_PIN3) | \ - PIN_ODR_HIGH(GPIOF_PIN4) | \ - PIN_ODR_HIGH(GPIOF_PIN5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_PIN12) | \ - PIN_ODR_HIGH(GPIOF_PIN13) | \ - PIN_ODR_HIGH(GPIOF_PIN14) | \ - PIN_ODR_HIGH(GPIOF_PIN15)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOF_PIN15, 0U)) - -/* - * GPIOG setup: - * - * PG0 - PIN0 (input pullup). - * PG1 - PIN1 (input pullup). - * PG2 - PIN2 (input pullup). - * PG3 - PIN3 (input pullup). - * PG4 - PIN4 (input pullup). - * PG5 - PIN5 (input pullup). - * PG6 - USB_FS_PWR_EN (output pushpull minimum). - * PG7 - USB_FS_OVCR (input floating). - * PG8 - PIN8 (input pullup). - * PG9 - PIN9 (input pullup). - * PG10 - PIN10 (input pullup). - * PG11 - RMII_TX_EN (alternate 11). - * PG12 - PIN12 (input pullup). - * PG13 - RMII_TXD0 (alternate 11). - * PG14 - PIN14 (input pullup). - * PG15 - PIN15 (input pullup). - */ -#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ - PIN_MODE_INPUT(GPIOG_PIN1) | \ - PIN_MODE_INPUT(GPIOG_PIN2) | \ - PIN_MODE_INPUT(GPIOG_PIN3) | \ - PIN_MODE_INPUT(GPIOG_PIN4) | \ - PIN_MODE_INPUT(GPIOG_PIN5) | \ - PIN_MODE_OUTPUT(GPIOG_USB_FS_PWR_EN) | \ - PIN_MODE_INPUT(GPIOG_USB_FS_OVCR) | \ - PIN_MODE_INPUT(GPIOG_PIN8) | \ - PIN_MODE_INPUT(GPIOG_PIN9) | \ - PIN_MODE_INPUT(GPIOG_PIN10) | \ - PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \ - PIN_MODE_INPUT(GPIOG_PIN12) | \ - PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \ - PIN_MODE_INPUT(GPIOG_PIN14) | \ - PIN_MODE_INPUT(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOG_USB_FS_PWR_EN) |\ - PIN_OTYPE_PUSHPULL(GPIOG_USB_FS_OVCR) |\ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOG_USB_FS_PWR_EN) |\ - PIN_OSPEED_VERYLOW(GPIOG_USB_FS_OVCR) |\ - PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \ - PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \ - PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN15)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOG_USB_FS_PWR_EN) |\ - PIN_PUPDR_FLOATING(GPIOG_USB_FS_OVCR) |\ - PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ - PIN_ODR_HIGH(GPIOG_PIN1) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_PIN4) | \ - PIN_ODR_HIGH(GPIOG_PIN5) | \ - PIN_ODR_LOW(GPIOG_USB_FS_PWR_EN) | \ - PIN_ODR_HIGH(GPIOG_USB_FS_OVCR) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \ - PIN_ODR_HIGH(GPIOG_PIN12) | \ - PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOG_USB_FS_PWR_EN, 0U) | \ - PIN_AFIO_AF(GPIOG_USB_FS_OVCR, 0U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) | \ - PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0U)) - -/* - * GPIOH setup: - * - * PH0 - OSC_IN (input floating). - * PH1 - OSC_OUT (input floating). - * PH2 - PIN2 (input pullup). - * PH3 - PIN3 (input pullup). - * PH4 - PIN4 (input pullup). - * PH5 - PIN5 (input pullup). - * PH6 - PIN6 (input pullup). - * PH7 - PIN7 (input pullup). - * PH8 - PIN8 (input pullup). - * PH9 - PIN9 (input pullup). - * PH10 - PIN10 (input pullup). - * PH11 - PIN11 (input pullup). - * PH12 - PIN12 (input pullup). - * PH13 - PIN13 (input pullup). - * PH14 - PIN14 (input pullup). - * PH15 - PIN15 (input pullup). - */ -#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ - PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOH_PIN2) | \ - PIN_MODE_INPUT(GPIOH_PIN3) | \ - PIN_MODE_INPUT(GPIOH_PIN4) | \ - PIN_MODE_INPUT(GPIOH_PIN5) | \ - PIN_MODE_INPUT(GPIOH_PIN6) | \ - PIN_MODE_INPUT(GPIOH_PIN7) | \ - PIN_MODE_INPUT(GPIOH_PIN8) | \ - PIN_MODE_INPUT(GPIOH_PIN9) | \ - PIN_MODE_INPUT(GPIOH_PIN10) | \ - PIN_MODE_INPUT(GPIOH_PIN11) | \ - PIN_MODE_INPUT(GPIOH_PIN12) | \ - PIN_MODE_INPUT(GPIOH_PIN13) | \ - PIN_MODE_INPUT(GPIOH_PIN14) | \ - PIN_MODE_INPUT(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_PIN7) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN7, 0U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) - -/* - * GPIOI setup: - * - * PI0 - PIN0 (input pullup). - * PI1 - PIN1 (input pullup). - * PI2 - PIN2 (input pullup). - * PI3 - PIN3 (input pullup). - * PI4 - PIN4 (input pullup). - * PI5 - PIN5 (input pullup). - * PI6 - PIN6 (input pullup). - * PI7 - PIN7 (input pullup). - * PI8 - PIN8 (input pullup). - * PI9 - PIN9 (input pullup). - * PI10 - PIN10 (input pullup). - * PI11 - PIN11 (input pullup). - * PI12 - PIN12 (input pullup). - * PI13 - PIN13 (input pullup). - * PI14 - PIN14 (input pullup). - * PI15 - PIN15 (input pullup). - */ -#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ - PIN_MODE_INPUT(GPIOI_PIN1) | \ - PIN_MODE_INPUT(GPIOI_PIN2) | \ - PIN_MODE_INPUT(GPIOI_PIN3) | \ - PIN_MODE_INPUT(GPIOI_PIN4) | \ - PIN_MODE_INPUT(GPIOI_PIN5) | \ - PIN_MODE_INPUT(GPIOI_PIN6) | \ - PIN_MODE_INPUT(GPIOI_PIN7) | \ - PIN_MODE_INPUT(GPIOI_PIN8) | \ - PIN_MODE_INPUT(GPIOI_PIN9) | \ - PIN_MODE_INPUT(GPIOI_PIN10) | \ - PIN_MODE_INPUT(GPIOI_PIN11) | \ - PIN_MODE_INPUT(GPIOI_PIN12) | \ - PIN_MODE_INPUT(GPIOI_PIN13) | \ - PIN_MODE_INPUT(GPIOI_PIN14) | \ - PIN_MODE_INPUT(GPIOI_PIN15)) -#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) -#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN15)) -#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN15)) -#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ - PIN_ODR_HIGH(GPIOI_PIN1) | \ - PIN_ODR_HIGH(GPIOI_PIN2) | \ - PIN_ODR_HIGH(GPIOI_PIN3) | \ - PIN_ODR_HIGH(GPIOI_PIN4) | \ - PIN_ODR_HIGH(GPIOI_PIN5) | \ - PIN_ODR_HIGH(GPIOI_PIN6) | \ - PIN_ODR_HIGH(GPIOI_PIN7) | \ - PIN_ODR_HIGH(GPIOI_PIN8) | \ - PIN_ODR_HIGH(GPIOI_PIN9) | \ - PIN_ODR_HIGH(GPIOI_PIN10) | \ - PIN_ODR_HIGH(GPIOI_PIN11) | \ - PIN_ODR_HIGH(GPIOI_PIN12) | \ - PIN_ODR_HIGH(GPIOI_PIN13) | \ - PIN_ODR_HIGH(GPIOI_PIN14) | \ - PIN_ODR_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN7, 0U)) -#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN15, 0U)) - -/* - * GPIOJ setup: - * - * PJ0 - PIN0 (input pullup). - * PJ1 - PIN1 (input pullup). - * PJ2 - PIN2 (input pullup). - * PJ3 - PIN3 (input pullup). - * PJ4 - PIN4 (input pullup). - * PJ5 - PIN5 (input pullup). - * PJ6 - PIN6 (input pullup). - * PJ7 - PIN7 (input pullup). - * PJ8 - PIN8 (input pullup). - * PJ9 - PIN9 (input pullup). - * PJ10 - PIN10 (input pullup). - * PJ11 - PIN11 (input pullup). - * PJ12 - PIN12 (input pullup). - * PJ13 - PIN13 (input pullup). - * PJ14 - PIN14 (input pullup). - * PJ15 - PIN15 (input pullup). - */ -#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \ - PIN_MODE_INPUT(GPIOJ_PIN1) | \ - PIN_MODE_INPUT(GPIOJ_PIN2) | \ - PIN_MODE_INPUT(GPIOJ_PIN3) | \ - PIN_MODE_INPUT(GPIOJ_PIN4) | \ - PIN_MODE_INPUT(GPIOJ_PIN5) | \ - PIN_MODE_INPUT(GPIOJ_PIN6) | \ - PIN_MODE_INPUT(GPIOJ_PIN7) | \ - PIN_MODE_INPUT(GPIOJ_PIN8) | \ - PIN_MODE_INPUT(GPIOJ_PIN9) | \ - PIN_MODE_INPUT(GPIOJ_PIN10) | \ - PIN_MODE_INPUT(GPIOJ_PIN11) | \ - PIN_MODE_INPUT(GPIOJ_PIN12) | \ - PIN_MODE_INPUT(GPIOJ_PIN13) | \ - PIN_MODE_INPUT(GPIOJ_PIN14) | \ - PIN_MODE_INPUT(GPIOJ_PIN15)) -#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOJ_PIN15)) -#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN1) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN12) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN13) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN14) | \ - PIN_OSPEED_VERYLOW(GPIOJ_PIN15)) -#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLUP(GPIOJ_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOJ_PIN15)) -#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \ - PIN_ODR_HIGH(GPIOJ_PIN1) | \ - PIN_ODR_HIGH(GPIOJ_PIN2) | \ - PIN_ODR_HIGH(GPIOJ_PIN3) | \ - PIN_ODR_HIGH(GPIOJ_PIN4) | \ - PIN_ODR_HIGH(GPIOJ_PIN5) | \ - PIN_ODR_HIGH(GPIOJ_PIN6) | \ - PIN_ODR_HIGH(GPIOJ_PIN7) | \ - PIN_ODR_HIGH(GPIOJ_PIN8) | \ - PIN_ODR_HIGH(GPIOJ_PIN9) | \ - PIN_ODR_HIGH(GPIOJ_PIN10) | \ - PIN_ODR_HIGH(GPIOJ_PIN11) | \ - PIN_ODR_HIGH(GPIOJ_PIN12) | \ - PIN_ODR_HIGH(GPIOJ_PIN13) | \ - PIN_ODR_HIGH(GPIOJ_PIN14) | \ - PIN_ODR_HIGH(GPIOJ_PIN15)) -#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN7, 0U)) -#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOJ_PIN15, 0U)) - -/* - * GPIOK setup: - * - * PK0 - PIN0 (input pullup). - * PK1 - PIN1 (input pullup). - * PK2 - PIN2 (input pullup). - * PK3 - PIN3 (input pullup). - * PK4 - PIN4 (input pullup). - * PK5 - PIN5 (input pullup). - * PK6 - PIN6 (input pullup). - * PK7 - PIN7 (input pullup). - * PK8 - PIN8 (input pullup). - * PK9 - PIN9 (input pullup). - * PK10 - PIN10 (input pullup). - * PK11 - PIN11 (input pullup). - * PK12 - PIN12 (input pullup). - * PK13 - PIN13 (input pullup). - * PK14 - PIN14 (input pullup). - * PK15 - PIN15 (input pullup). - */ -#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ - PIN_MODE_INPUT(GPIOK_PIN1) | \ - PIN_MODE_INPUT(GPIOK_PIN2) | \ - PIN_MODE_INPUT(GPIOK_PIN3) | \ - PIN_MODE_INPUT(GPIOK_PIN4) | \ - PIN_MODE_INPUT(GPIOK_PIN5) | \ - PIN_MODE_INPUT(GPIOK_PIN6) | \ - PIN_MODE_INPUT(GPIOK_PIN7) | \ - PIN_MODE_INPUT(GPIOK_PIN8) | \ - PIN_MODE_INPUT(GPIOK_PIN9) | \ - PIN_MODE_INPUT(GPIOK_PIN10) | \ - PIN_MODE_INPUT(GPIOK_PIN11) | \ - PIN_MODE_INPUT(GPIOK_PIN12) | \ - PIN_MODE_INPUT(GPIOK_PIN13) | \ - PIN_MODE_INPUT(GPIOK_PIN14) | \ - PIN_MODE_INPUT(GPIOK_PIN15)) -#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) -#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \ - PIN_OSPEED_VERYLOW(GPIOK_PIN15)) -#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLUP(GPIOK_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOK_PIN15)) -#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ - PIN_ODR_HIGH(GPIOK_PIN1) | \ - PIN_ODR_HIGH(GPIOK_PIN2) | \ - PIN_ODR_HIGH(GPIOK_PIN3) | \ - PIN_ODR_HIGH(GPIOK_PIN4) | \ - PIN_ODR_HIGH(GPIOK_PIN5) | \ - PIN_ODR_HIGH(GPIOK_PIN6) | \ - PIN_ODR_HIGH(GPIOK_PIN7) | \ - PIN_ODR_HIGH(GPIOK_PIN8) | \ - PIN_ODR_HIGH(GPIOK_PIN9) | \ - PIN_ODR_HIGH(GPIOK_PIN10) | \ - PIN_ODR_HIGH(GPIOK_PIN11) | \ - PIN_ODR_HIGH(GPIOK_PIN12) | \ - PIN_ODR_HIGH(GPIOK_PIN13) | \ - PIN_ODR_HIGH(GPIOK_PIN14) | \ - PIN_ODR_HIGH(GPIOK_PIN15)) -#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN7, 0U)) -#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOK_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/board/board.mk b/board/board.mk index b410cdb..f6df51a 100644 --- a/board/board.mk +++ b/board/board.mk @@ -1,8 +1,16 @@ # List of all the board related files. -BOARDSRC = ./board/board.c +ifeq ($(TARGET_PLATFORM),H7) + BOARDSRC = ./board/board_h7.c +else + BOARDSRC = ./board/board_l4.c +endif # Required include directories -BOARDINC = ./board +ifeq ($(TARGET_PLATFORM),H7) + BOARDINC = ./board/h7 +else + BOARDINC = ./board/l4 +endif # Shared variables ALLCSRC += $(BOARDSRC) diff --git a/board/board_h7.c b/board/board_h7.c new file mode 100644 index 0000000..2868726 --- /dev/null +++ b/board/board_h7.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB4(STM32_GPIO_EN_MASK); + rccEnableAHB4(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* CHTODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* CHTODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* CHTODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* CHTODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. + */ +void boardInit(void) { + +} diff --git a/board/board_l4.c b/board/board_l4.c new file mode 100644 index 0000000..cd16e43 --- /dev/null +++ b/board/board_l4.c @@ -0,0 +1,281 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; + uint32_t ascr; + uint32_t lockr; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR, + VAL_GPIOA_LOCKR}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR, + VAL_GPIOB_LOCKR}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR, + VAL_GPIOC_LOCKR}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR, + VAL_GPIOD_LOCKR}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR, + VAL_GPIOE_LOCKR}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR, + VAL_GPIOF_LOCKR}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR, + VAL_GPIOG_LOCKR}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR, + VAL_GPIOH_LOCKR}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR, + VAL_GPIOI_LOCKR}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR, + VAL_GPIOJ_LOCKR}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR, + VAL_GPIOK_LOCKR} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->ASCR = config->ascr; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; + gpiop->LOCKR = config->lockr; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB2(STM32_GPIO_EN_MASK); + rccEnableAHB2(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* CHTODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* CHTODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* CHTODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* CHTODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. + */ +void boardInit(void) { + +} diff --git a/board/h7/board.h b/board/h7/board.h new file mode 100644 index 0000000..58ba40e --- /dev/null +++ b/board/h7/board.h @@ -0,0 +1,1642 @@ +/* + ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for STMicroelectronics STM32 Nucleo144-H743ZI board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_NUCLEO144_H743ZI +#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-H743ZI" + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_LAN8742A_ID +#define BOARD_PHY_RMII + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +#define STM32_HSE_BYPASS + +/* + * MCU type as defined in the ST header. + */ +#define STM32H723xx + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_RMII_REF_CLK 1U +#define GPIOA_RMII_MDIO 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_RMII_CRS_DV 7U +#define GPIOA_USB_SOF 8U +#define GPIOA_MCO1 8U +#define GPIOA_USB_VBUS 9U +#define GPIOA_USB_ID 10U +#define GPIOA_USB_DM 11U +#define GPIOA_USB_DP 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_T_JTDI 15U + +#define GPIOB_LED1 0U +#define GPIOB_LED_GREEN 0U +#define GPIOB_LED 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_SWO 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_RMII_TXD1 13U +#define GPIOB_LED3 14U +#define GPIOB_LED_RED 14U +#define GPIOB_PIN15 15U + +#define GPIOC_PIN0 0U +#define GPIOC_RMII_MDC 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_RMII_RXD0 4U +#define GPIOC_RMII_RXD1 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_BUTTON 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_USART3_RX 8U +#define GPIOD_STLK_RX 8U +#define GPIOD_USART3_TX 9U +#define GPIOD_STLK_TX 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOE_PIN0 0U +#define GPIOE_LED2 1U +#define GPIOE_LED_YELLOW 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +#define GPIOF_PIN0 0U +#define GPIOF_PIN1 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN8 8U +#define GPIOF_PIN9 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +#define GPIOG_PIN0 0U +#define GPIOG_PIN1 1U +#define GPIOG_PIN2 2U +#define GPIOG_PIN3 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_USB_FS_PWR_EN 6U +#define GPIOG_USB_FS_OVCR 7U +#define GPIOG_PIN8 8U +#define GPIOG_PIN9 9U +#define GPIOG_PIN10 10U +#define GPIOG_RMII_TX_EN 11U +#define GPIOG_PIN12 12U +#define GPIOG_RMII_TXD0 13U +#define GPIOG_PIN14 14U +#define GPIOG_PIN15 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +#define GPIOJ_PIN0 0U +#define GPIOJ_PIN1 1U +#define GPIOJ_PIN2 2U +#define GPIOJ_PIN3 3U +#define GPIOJ_PIN4 4U +#define GPIOJ_PIN5 5U +#define GPIOJ_PIN6 6U +#define GPIOJ_PIN7 7U +#define GPIOJ_PIN8 8U +#define GPIOJ_PIN9 9U +#define GPIOJ_PIN10 10U +#define GPIOJ_PIN11 11U +#define GPIOJ_PIN12 12U +#define GPIOJ_PIN13 13U +#define GPIOJ_PIN14 14U +#define GPIOJ_PIN15 15U + +#define GPIOK_PIN0 0U +#define GPIOK_PIN1 1U +#define GPIOK_PIN2 2U +#define GPIOK_PIN3 3U +#define GPIOK_PIN4 4U +#define GPIOK_PIN5 5U +#define GPIOK_PIN6 6U +#define GPIOK_PIN7 7U +#define GPIOK_PIN8 8U +#define GPIOK_PIN9 9U +#define GPIOK_PIN10 10U +#define GPIOK_PIN11 11U +#define GPIOK_PIN12 12U +#define GPIOK_PIN13 13U +#define GPIOK_PIN14 14U +#define GPIOK_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_RMII_REF_CLK PAL_LINE(GPIOA, 1U) +#define LINE_RMII_MDIO PAL_LINE(GPIOA, 2U) +#define LINE_RMII_CRS_DV PAL_LINE(GPIOA, 7U) +#define LINE_USB_SOF PAL_LINE(GPIOA, 8U) +#define LINE_MCO1 PAL_LINE(GPIOA, 8U) +#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U) +#define LINE_USB_ID PAL_LINE(GPIOA, 10U) +#define LINE_USB_DM PAL_LINE(GPIOA, 11U) +#define LINE_USB_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_T_JTDI PAL_LINE(GPIOA, 15U) +#define LINE_LED1 PAL_LINE(GPIOB, 0U) +#define LINE_LED_GREEN PAL_LINE(GPIOB, 0U) +#define LINE_LED PAL_LINE(GPIOB, 0U) +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_LED2 PAL_LINE(GPIOE, 1U) +#define LINE_LED_YELLOW PAL_LINE(GPIOE, 1U) +#define LINE_RMII_TXD1 PAL_LINE(GPIOB, 13U) +#define LINE_LED3 PAL_LINE(GPIOB, 14U) +#define LINE_LED_RED PAL_LINE(GPIOB, 14U) +#define LINE_RMII_MDC PAL_LINE(GPIOC, 1U) +#define LINE_RMII_RXD0 PAL_LINE(GPIOC, 4U) +#define LINE_RMII_RXD1 PAL_LINE(GPIOC, 5U) +#define LINE_BUTTON PAL_LINE(GPIOC, 13U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) +#define LINE_USART3_RX PAL_LINE(GPIOD, 8U) +#define LINE_STLK_RX PAL_LINE(GPIOD, 8U) +#define LINE_USART3_TX PAL_LINE(GPIOD, 9U) +#define LINE_STLK_TX PAL_LINE(GPIOD, 9U) +#define LINE_USB_FS_PWR_EN PAL_LINE(GPIOG, 6U) +#define LINE_USB_FS_OVCR PAL_LINE(GPIOG, 7U) +#define LINE_RMII_TX_EN PAL_LINE(GPIOG, 11U) +#define LINE_RMII_TXD0 PAL_LINE(GPIOG, 13U) +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - PIN0 (input pullup). + * PA1 - RMII_REF_CLK (alternate 11). + * PA2 - RMII_MDIO (alternate 11). + * PA3 - PIN3 (input pullup). + * PA4 - PIN4 (input pullup). + * PA5 - PIN5 (input pullup). + * PA6 - PIN6 (input pullup). + * PA7 - RMII_CRS_DV (alternate 11). + * PA8 - USB_SOF MCO1 (alternate 10). + * PA9 - USB_VBUS (analog). + * PA10 - USB_ID (alternate 10). + * PA11 - USB_DM (alternate 10). + * PA12 - USB_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - T_JTDI (alternate 0). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \ + PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\ + PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) |\ + PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \ + PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_ALTERNATE(GPIOA_T_JTDI)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) |\ + PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_T_JTDI)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \ + PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_CRS_DV) | \ + PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \ + PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \ + PIN_OSPEED_HIGH(GPIOA_USB_ID) | \ + PIN_OSPEED_HIGH(GPIOA_USB_DM) | \ + PIN_OSPEED_HIGH(GPIOA_USB_DP) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_T_JTDI)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\ + PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOA_RMII_CRS_DV) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_T_JTDI)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ + PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \ + PIN_ODR_HIGH(GPIOA_PIN3) | \ + PIN_ODR_HIGH(GPIOA_PIN4) | \ + PIN_ODR_HIGH(GPIOA_PIN5) | \ + PIN_ODR_HIGH(GPIOA_PIN6) | \ + PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) | \ + PIN_ODR_HIGH(GPIOA_USB_SOF) | \ + PIN_ODR_HIGH(GPIOA_USB_VBUS) | \ + PIN_ODR_HIGH(GPIOA_USB_ID) | \ + PIN_ODR_HIGH(GPIOA_USB_DM) | \ + PIN_ODR_HIGH(GPIOA_USB_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_T_JTDI)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \ + PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \ + PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_T_JTDI, 0U)) + +/* + * GPIOB setup: + * + * PB0 - LED1 LED_GREEN LED (output pushpull maximum). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - SWO (alternate 0). + * PB4 - PIN4 (input pullup). + * PB5 - PIN5 (input pullup). + * PB6 - PIN6 (input pullup). + * PB7 - PIN7 (input pullup). + * PB8 - PIN8 (input pullup). + * PB9 - PIN9 (input pullup). + * PB10 - PIN10 (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - RMII_TXD1 (alternate 11). + * PB14 - LED3 LED_RED (output pushpull maximum). + * PB15 - PIN15 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_LED1) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOB_RMII_TXD1) | \ + PIN_MODE_OUTPUT(GPIOB_LED3) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_LED1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_RMII_TXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_LED1) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN2) | \ + PIN_OSPEED_HIGH(GPIOB_SWO) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN12) | \ + PIN_OSPEED_HIGH(GPIOB_RMII_TXD1) | \ + PIN_OSPEED_HIGH(GPIOB_LED3) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_LED1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOB_RMII_TXD1) | \ + PIN_PUPDR_FLOATING(GPIOB_LED3) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_LED1) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_PIN4) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_PIN6) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_PIN9) | \ + PIN_ODR_HIGH(GPIOB_PIN10) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_RMII_TXD1) | \ + PIN_ODR_LOW(GPIOB_LED3) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_LED1, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOB_SWO, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOB_RMII_TXD1, 11U) | \ + PIN_AFIO_AF(GPIOB_LED3, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0U)) + +/* + * GPIOC setup: + * + * PC0 - PIN0 (input pullup). + * PC1 - RMII_MDC (alternate 11). + * PC2 - PIN2 (input pullup). + * PC3 - PIN3 (input pullup). + * PC4 - RMII_RXD0 (alternate 11). + * PC5 - RMII_RXD1 (alternate 11). + * PC6 - PIN6 (input pullup). + * PC7 - PIN7 (input pullup). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - PIN10 (input pullup). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - BUTTON (input floating). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_BUTTON) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN3) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \ + PIN_OSPEED_HIGH(GPIOC_BUTTON) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ + PIN_ODR_HIGH(GPIOC_RMII_MDC) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_PIN7) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_BUTTON) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN7, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - USART3_RX STLK_RX (alternate 7). + * PD9 - USART3_TX STLK_TX (alternate 7). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - PIN12 (input pullup). + * PD13 - PIN13 (input pullup). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_USART3_RX) | \ + PIN_ODR_HIGH(GPIOD_USART3_TX) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \ + PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0U)) + +/* + * GPIOE setup: + * + * PE0 - PIN0 (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - PIN7 (input pullup). + * PE8 - PIN8 (input pullup). + * PE9 - PIN9 (input pullup). + * PE10 - PIN10 (input pullup). + * PE11 - PIN11 (input pullup). + * PE12 - PIN12 (input pullup). + * PE13 - PIN13 (input pullup). + * PE14 - PIN14 (input pullup). + * PE15 - PIN15 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_OUTPUT(GPIOE_LED2) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LED2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | \ + PIN_OSPEED_HIGH(GPIOE_LED2) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOE_LED2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_LOW(GPIOE_LED2) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOE_LED2, 0U)) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0U) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0U)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input pullup). + * PF1 - PIN1 (input pullup). + * PF2 - PIN2 (input pullup). + * PF3 - PIN3 (input pullup). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF8 - PIN8 (input pullup). + * PF9 - PIN9 (input pullup). + * PF10 - PIN10 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - PIN12 (input pullup). + * PF13 - PIN13 (input pullup). + * PF14 - PIN14 (input pullup). + * PF15 - PIN15 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0U)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input pullup). + * PG1 - PIN1 (input pullup). + * PG2 - PIN2 (input pullup). + * PG3 - PIN3 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - USB_FS_PWR_EN (output pushpull minimum). + * PG7 - USB_FS_OVCR (input floating). + * PG8 - PIN8 (input pullup). + * PG9 - PIN9 (input pullup). + * PG10 - PIN10 (input pullup). + * PG11 - RMII_TX_EN (alternate 11). + * PG12 - PIN12 (input pullup). + * PG13 - RMII_TXD0 (alternate 11). + * PG14 - PIN14 (input pullup). + * PG15 - PIN15 (input pullup). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_OUTPUT(GPIOG_USB_FS_PWR_EN) | \ + PIN_MODE_INPUT(GPIOG_USB_FS_OVCR) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \ + PIN_MODE_INPUT(GPIOG_PIN14) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_USB_FS_PWR_EN) |\ + PIN_OTYPE_PUSHPULL(GPIOG_USB_FS_OVCR) |\ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOG_USB_FS_PWR_EN) |\ + PIN_OSPEED_VERYLOW(GPIOG_USB_FS_OVCR) |\ + PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOG_USB_FS_PWR_EN) |\ + PIN_PUPDR_FLOATING(GPIOG_USB_FS_OVCR) |\ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_LOW(GPIOG_USB_FS_PWR_EN) | \ + PIN_ODR_HIGH(GPIOG_USB_FS_OVCR) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_USB_FS_PWR_EN, 0U) | \ + PIN_AFIO_AF(GPIOG_USB_FS_OVCR, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + +/* + * GPIOJ setup: + * + * PJ0 - PIN0 (input pullup). + * PJ1 - PIN1 (input pullup). + * PJ2 - PIN2 (input pullup). + * PJ3 - PIN3 (input pullup). + * PJ4 - PIN4 (input pullup). + * PJ5 - PIN5 (input pullup). + * PJ6 - PIN6 (input pullup). + * PJ7 - PIN7 (input pullup). + * PJ8 - PIN8 (input pullup). + * PJ9 - PIN9 (input pullup). + * PJ10 - PIN10 (input pullup). + * PJ11 - PIN11 (input pullup). + * PJ12 - PIN12 (input pullup). + * PJ13 - PIN13 (input pullup). + * PJ14 - PIN14 (input pullup). + * PJ15 - PIN15 (input pullup). + */ +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \ + PIN_MODE_INPUT(GPIOJ_PIN1) | \ + PIN_MODE_INPUT(GPIOJ_PIN2) | \ + PIN_MODE_INPUT(GPIOJ_PIN3) | \ + PIN_MODE_INPUT(GPIOJ_PIN4) | \ + PIN_MODE_INPUT(GPIOJ_PIN5) | \ + PIN_MODE_INPUT(GPIOJ_PIN6) | \ + PIN_MODE_INPUT(GPIOJ_PIN7) | \ + PIN_MODE_INPUT(GPIOJ_PIN8) | \ + PIN_MODE_INPUT(GPIOJ_PIN9) | \ + PIN_MODE_INPUT(GPIOJ_PIN10) | \ + PIN_MODE_INPUT(GPIOJ_PIN11) | \ + PIN_MODE_INPUT(GPIOJ_PIN12) | \ + PIN_MODE_INPUT(GPIOJ_PIN13) | \ + PIN_MODE_INPUT(GPIOJ_PIN14) | \ + PIN_MODE_INPUT(GPIOJ_PIN15)) +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN15)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN15)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLUP(GPIOJ_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN15)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \ + PIN_ODR_HIGH(GPIOJ_PIN1) | \ + PIN_ODR_HIGH(GPIOJ_PIN2) | \ + PIN_ODR_HIGH(GPIOJ_PIN3) | \ + PIN_ODR_HIGH(GPIOJ_PIN4) | \ + PIN_ODR_HIGH(GPIOJ_PIN5) | \ + PIN_ODR_HIGH(GPIOJ_PIN6) | \ + PIN_ODR_HIGH(GPIOJ_PIN7) | \ + PIN_ODR_HIGH(GPIOJ_PIN8) | \ + PIN_ODR_HIGH(GPIOJ_PIN9) | \ + PIN_ODR_HIGH(GPIOJ_PIN10) | \ + PIN_ODR_HIGH(GPIOJ_PIN11) | \ + PIN_ODR_HIGH(GPIOJ_PIN12) | \ + PIN_ODR_HIGH(GPIOJ_PIN13) | \ + PIN_ODR_HIGH(GPIOJ_PIN14) | \ + PIN_ODR_HIGH(GPIOJ_PIN15)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN7, 0U)) +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN15, 0U)) + +/* + * GPIOK setup: + * + * PK0 - PIN0 (input pullup). + * PK1 - PIN1 (input pullup). + * PK2 - PIN2 (input pullup). + * PK3 - PIN3 (input pullup). + * PK4 - PIN4 (input pullup). + * PK5 - PIN5 (input pullup). + * PK6 - PIN6 (input pullup). + * PK7 - PIN7 (input pullup). + * PK8 - PIN8 (input pullup). + * PK9 - PIN9 (input pullup). + * PK10 - PIN10 (input pullup). + * PK11 - PIN11 (input pullup). + * PK12 - PIN12 (input pullup). + * PK13 - PIN13 (input pullup). + * PK14 - PIN14 (input pullup). + * PK15 - PIN15 (input pullup). + */ +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ + PIN_MODE_INPUT(GPIOK_PIN1) | \ + PIN_MODE_INPUT(GPIOK_PIN2) | \ + PIN_MODE_INPUT(GPIOK_PIN3) | \ + PIN_MODE_INPUT(GPIOK_PIN4) | \ + PIN_MODE_INPUT(GPIOK_PIN5) | \ + PIN_MODE_INPUT(GPIOK_PIN6) | \ + PIN_MODE_INPUT(GPIOK_PIN7) | \ + PIN_MODE_INPUT(GPIOK_PIN8) | \ + PIN_MODE_INPUT(GPIOK_PIN9) | \ + PIN_MODE_INPUT(GPIOK_PIN10) | \ + PIN_MODE_INPUT(GPIOK_PIN11) | \ + PIN_MODE_INPUT(GPIOK_PIN12) | \ + PIN_MODE_INPUT(GPIOK_PIN13) | \ + PIN_MODE_INPUT(GPIOK_PIN14) | \ + PIN_MODE_INPUT(GPIOK_PIN15)) +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLUP(GPIOK_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN15)) +#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ + PIN_ODR_HIGH(GPIOK_PIN1) | \ + PIN_ODR_HIGH(GPIOK_PIN2) | \ + PIN_ODR_HIGH(GPIOK_PIN3) | \ + PIN_ODR_HIGH(GPIOK_PIN4) | \ + PIN_ODR_HIGH(GPIOK_PIN5) | \ + PIN_ODR_HIGH(GPIOK_PIN6) | \ + PIN_ODR_HIGH(GPIOK_PIN7) | \ + PIN_ODR_HIGH(GPIOK_PIN8) | \ + PIN_ODR_HIGH(GPIOK_PIN9) | \ + PIN_ODR_HIGH(GPIOK_PIN10) | \ + PIN_ODR_HIGH(GPIOK_PIN11) | \ + PIN_ODR_HIGH(GPIOK_PIN12) | \ + PIN_ODR_HIGH(GPIOK_PIN13) | \ + PIN_ODR_HIGH(GPIOK_PIN14) | \ + PIN_ODR_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN7, 0U)) +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN15, 0U)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/board/l4/board.h b/board/l4/board.h new file mode 100644 index 0000000..ff42cd1 --- /dev/null +++ b/board/l4/board.h @@ -0,0 +1,1505 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for STMicroelectronics STM32 Nucleo64-L476RG board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_NUCLEO64_L476RG +#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-L476RG" + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +#define STM32_HSE_BYPASS + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32L476xx + +/* + * IO pins assignments. + */ +#define GPIOA_ARD_A0 0U +#define GPIOA_ACD12_IN5 0U +#define GPIOA_ARD_A1 1U +#define GPIOA_ACD12_IN6 1U +#define GPIOA_ARD_D1 2U +#define GPIOA_USART2_TX 2U +#define GPIOA_ARD_D0 3U +#define GPIOA_USART2_RX 3U +#define GPIOA_ARD_A2 4U +#define GPIOA_ACD12_IN9 4U +#define GPIOA_ARD_D13 5U +#define GPIOA_LED_GREEN 5U +#define GPIOA_ARD_D12 6U +#define GPIOA_ARD_D11 7U +#define GPIOA_ARD_D7 8U +#define GPIOA_ARD_D8 9U +#define GPIOA_ARD_D2 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_PIN15 15U + +#define GPIOB_ARD_A3 0U +#define GPIOB_ACD12_IN15 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_ARD_D3 3U +#define GPIOB_SWO 3U +#define GPIOB_ARD_D5 4U +#define GPIOB_ARD_D4 5U +#define GPIOB_ARD_D10 6U +#define GPIOB_PIN7 7U +#define GPIOB_ARD_D15 8U +#define GPIOB_ARD_D14 9U +#define GPIOB_ARD_D6 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_ARD_A5 0U +#define GPIOC_ACD123_IN1 0U +#define GPIOC_ARD_A4 1U +#define GPIOC_ACD123_IN2 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_ARD_D9 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_BUTTON 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOE_PIN0 0U +#define GPIOE_PIN1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +#define GPIOF_PIN0 0U +#define GPIOF_PIN1 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN8 8U +#define GPIOF_PIN9 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +#define GPIOG_PIN0 0U +#define GPIOG_PIN1 1U +#define GPIOG_PIN2 2U +#define GPIOG_PIN3 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_PIN6 6U +#define GPIOG_PIN7 7U +#define GPIOG_PIN8 8U +#define GPIOG_PIN9 9U +#define GPIOG_PIN10 10U +#define GPIOG_PIN11 11U +#define GPIOG_PIN12 12U +#define GPIOG_PIN13 13U +#define GPIOG_PIN14 14U +#define GPIOG_PIN15 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U) +#define LINE_ACD12_IN5 PAL_LINE(GPIOA, 0U) +#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) +#define LINE_ACD12_IN6 PAL_LINE(GPIOA, 1U) +#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U) +#define LINE_USART2_TX PAL_LINE(GPIOA, 2U) +#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U) +#define LINE_USART2_RX PAL_LINE(GPIOA, 3U) +#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U) +#define LINE_ACD12_IN9 PAL_LINE(GPIOA, 4U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) +#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) +#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) +#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U) +#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U) +#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U) +#define LINE_ACD12_IN15 PAL_LINE(GPIOB, 0U) +#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U) +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U) +#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U) +#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U) +#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) +#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) +#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U) +#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U) +#define LINE_ACD123_IN1 PAL_LINE(GPIOC, 0U) +#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U) +#define LINE_ACD123_IN2 PAL_LINE(GPIOC, 1U) +#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U) +#define LINE_BUTTON PAL_LINE(GPIOC, 13U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) +#define PIN_ASCR_DISABLED(n) (0U << (n)) +#define PIN_ASCR_ENABLED(n) (1U << (n)) +#define PIN_LOCKR_DISABLED(n) (0U << (n)) +#define PIN_LOCKR_ENABLED(n) (1U << (n)) + +/* + * GPIOA setup: + * + * PA0 - ARD_A0 ACD12_IN5 (analog). + * PA1 - ARD_A1 ACD12_IN6 (analog). + * PA2 - ARD_D1 USART2_TX (alternate 7). + * PA3 - ARD_D0 USART2_RX (alternate 7). + * PA4 - ARD_A2 ACD12_IN9 (analog). + * PA5 - ARD_D13 LED_GREEN (output pushpull maximum). + * PA6 - ARD_D12 (analog). + * PA7 - ARD_D11 (analog). + * PA8 - ARD_D7 (analog). + * PA9 - ARD_D8 (analog). + * PA10 - ARD_D2 (analog). + * PA11 - PIN11 (analog). + * PA12 - PIN12 (analog). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - PIN15 (analog). + */ +#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_ARD_A0) | \ + PIN_MODE_ANALOG(GPIOA_ARD_A1) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D1) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D0) | \ + PIN_MODE_ANALOG(GPIOA_ARD_A2) | \ + PIN_MODE_OUTPUT(GPIOA_ARD_D13) | \ + PIN_MODE_ANALOG(GPIOA_ARD_D12) | \ + PIN_MODE_ANALOG(GPIOA_ARD_D11) | \ + PIN_MODE_ANALOG(GPIOA_ARD_D7) | \ + PIN_MODE_ANALOG(GPIOA_ARD_D8) | \ + PIN_MODE_ANALOG(GPIOA_ARD_D2) | \ + PIN_MODE_ANALOG(GPIOA_PIN11) | \ + PIN_MODE_ANALOG(GPIOA_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_ANALOG(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ + PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | \ + PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D7) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D8) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \ + PIN_OSPEED_HIGH(GPIOA_PIN11) | \ + PIN_OSPEED_HIGH(GPIOA_PIN12) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_ARD_A0) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_A1) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_A2) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D13) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D12) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D11) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D7) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D8) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D2) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ + PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \ + PIN_ODR_HIGH(GPIOA_ARD_A1) | \ + PIN_ODR_HIGH(GPIOA_ARD_D1) | \ + PIN_ODR_HIGH(GPIOA_ARD_D0) | \ + PIN_ODR_HIGH(GPIOA_ARD_A2) | \ + PIN_ODR_LOW(GPIOA_ARD_D13) | \ + PIN_ODR_HIGH(GPIOA_ARD_D12) | \ + PIN_ODR_HIGH(GPIOA_ARD_D11) | \ + PIN_ODR_HIGH(GPIOA_ARD_D7) | \ + PIN_ODR_HIGH(GPIOA_ARD_D8) | \ + PIN_ODR_HIGH(GPIOA_ARD_D2) | \ + PIN_ODR_HIGH(GPIOA_PIN11) | \ + PIN_ODR_HIGH(GPIOA_PIN12) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D1, 7U) | \ + PIN_AFIO_AF(GPIOA_ARD_D0, 7U) | \ + PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D11, 0U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0U)) +#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_ARD_A0) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_A1) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D1) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D0) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_A2) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D13) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D12) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D11) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D7) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D8) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D2) | \ + PIN_ASCR_DISABLED(GPIOA_PIN11) | \ + PIN_ASCR_DISABLED(GPIOA_PIN12) | \ + PIN_ASCR_DISABLED(GPIOA_SWDIO) | \ + PIN_ASCR_DISABLED(GPIOA_SWCLK) | \ + PIN_ASCR_DISABLED(GPIOA_PIN15)) +#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_ARD_A0) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_A1) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D1) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D0) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_A2) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D13) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D12) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D11) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D7) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D8) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D2) | \ + PIN_LOCKR_DISABLED(GPIOA_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOA_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \ + PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \ + PIN_LOCKR_DISABLED(GPIOA_PIN15)) + +/* + * GPIOB setup: + * + * PB0 - ARD_A3 ACD12_IN15 (analog). + * PB1 - PIN1 (analog). + * PB2 - PIN2 (analog). + * PB3 - ARD_D3 SWO (analog). + * PB4 - ARD_D5 (analog). + * PB5 - ARD_D4 (analog). + * PB6 - ARD_D10 (analog). + * PB7 - PIN7 (analog). + * PB8 - ARD_D15 (analog). + * PB9 - ARD_D14 (analog). + * PB10 - ARD_D6 (analog). + * PB11 - PIN11 (analog). + * PB12 - PIN12 (analog). + * PB13 - PIN13 (analog). + * PB14 - PIN14 (analog). + * PB15 - PIN15 (analog). + */ +#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_ARD_A3) | \ + PIN_MODE_ANALOG(GPIOB_PIN1) | \ + PIN_MODE_ANALOG(GPIOB_PIN2) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D3) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D5) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D4) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D10) | \ + PIN_MODE_ANALOG(GPIOB_PIN7) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D15) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D14) | \ + PIN_MODE_ANALOG(GPIOB_ARD_D6) | \ + PIN_MODE_ANALOG(GPIOB_PIN11) | \ + PIN_MODE_ANALOG(GPIOB_PIN12) | \ + PIN_MODE_ANALOG(GPIOB_PIN13) | \ + PIN_MODE_ANALOG(GPIOB_PIN14) | \ + PIN_MODE_ANALOG(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOB_PIN1) | \ + PIN_OSPEED_HIGH(GPIOB_PIN2) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D3) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOB_PIN7) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOB_PIN11) | \ + PIN_OSPEED_HIGH(GPIOB_PIN12) | \ + PIN_OSPEED_HIGH(GPIOB_PIN13) | \ + PIN_OSPEED_HIGH(GPIOB_PIN14) | \ + PIN_OSPEED_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_ARD_A3) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D3) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D5) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D4) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D10) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D15) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D14) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D6) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_A3) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_HIGH(GPIOB_ARD_D3) | \ + PIN_ODR_HIGH(GPIOB_ARD_D5) | \ + PIN_ODR_HIGH(GPIOB_ARD_D4) | \ + PIN_ODR_HIGH(GPIOB_ARD_D10) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_ARD_D15) | \ + PIN_ODR_HIGH(GPIOB_ARD_D14) | \ + PIN_ODR_HIGH(GPIOB_ARD_D6) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D3, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0U)) +#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_ARD_A3) | \ + PIN_ASCR_DISABLED(GPIOB_PIN1) | \ + PIN_ASCR_DISABLED(GPIOB_PIN2) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D3) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D5) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D4) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D10) | \ + PIN_ASCR_DISABLED(GPIOB_PIN7) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D15) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D14) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D6) | \ + PIN_ASCR_DISABLED(GPIOB_PIN11) | \ + PIN_ASCR_DISABLED(GPIOB_PIN12) | \ + PIN_ASCR_DISABLED(GPIOB_PIN13) | \ + PIN_ASCR_DISABLED(GPIOB_PIN14) | \ + PIN_ASCR_DISABLED(GPIOB_PIN15)) +#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_ARD_A3) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D3) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D5) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D4) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D10) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D15) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D14) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D6) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOB_PIN15)) + +/* + * GPIOC setup: + * + * PC0 - ARD_A5 ACD123_IN1 (analog). + * PC1 - ARD_A4 ACD123_IN2 (analog). + * PC2 - PIN2 (analog). + * PC3 - PIN3 (analog). + * PC4 - PIN4 (analog). + * PC5 - PIN5 (analog). + * PC6 - PIN6 (analog). + * PC7 - ARD_D9 (analog). + * PC8 - PIN8 (analog). + * PC9 - PIN9 (analog). + * PC10 - PIN10 (analog). + * PC11 - PIN11 (analog). + * PC12 - PIN12 (analog). + * PC13 - BUTTON (input floating). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_ARD_A5) | \ + PIN_MODE_ANALOG(GPIOC_ARD_A4) | \ + PIN_MODE_ANALOG(GPIOC_PIN2) | \ + PIN_MODE_ANALOG(GPIOC_PIN3) | \ + PIN_MODE_ANALOG(GPIOC_PIN4) | \ + PIN_MODE_ANALOG(GPIOC_PIN5) | \ + PIN_MODE_ANALOG(GPIOC_PIN6) | \ + PIN_MODE_ANALOG(GPIOC_ARD_D9) | \ + PIN_MODE_ANALOG(GPIOC_PIN8) | \ + PIN_MODE_ANALOG(GPIOC_PIN9) | \ + PIN_MODE_ANALOG(GPIOC_PIN10) | \ + PIN_MODE_ANALOG(GPIOC_PIN11) | \ + PIN_MODE_ANALOG(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_BUTTON) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A5) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN2) | \ + PIN_OSPEED_HIGH(GPIOC_PIN3) | \ + PIN_OSPEED_HIGH(GPIOC_PIN4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN5) | \ + PIN_OSPEED_HIGH(GPIOC_PIN6) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D9) | \ + PIN_OSPEED_HIGH(GPIOC_PIN8) | \ + PIN_OSPEED_HIGH(GPIOC_PIN9) | \ + PIN_OSPEED_HIGH(GPIOC_PIN10) | \ + PIN_OSPEED_HIGH(GPIOC_PIN11) | \ + PIN_OSPEED_HIGH(GPIOC_PIN12) | \ + PIN_OSPEED_HIGH(GPIOC_BUTTON) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ARD_A5) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_A4) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_D9) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A5) | \ + PIN_ODR_HIGH(GPIOC_ARD_A4) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_ARD_D9) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_BUTTON) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_D9, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) +#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_ARD_A5) | \ + PIN_ASCR_DISABLED(GPIOC_ARD_A4) | \ + PIN_ASCR_DISABLED(GPIOC_PIN2) | \ + PIN_ASCR_DISABLED(GPIOC_PIN3) | \ + PIN_ASCR_DISABLED(GPIOC_PIN4) | \ + PIN_ASCR_DISABLED(GPIOC_PIN5) | \ + PIN_ASCR_DISABLED(GPIOC_PIN6) | \ + PIN_ASCR_DISABLED(GPIOC_ARD_D9) | \ + PIN_ASCR_DISABLED(GPIOC_PIN8) | \ + PIN_ASCR_DISABLED(GPIOC_PIN9) | \ + PIN_ASCR_DISABLED(GPIOC_PIN10) | \ + PIN_ASCR_DISABLED(GPIOC_PIN11) | \ + PIN_ASCR_DISABLED(GPIOC_PIN12) | \ + PIN_ASCR_DISABLED(GPIOC_BUTTON) | \ + PIN_ASCR_DISABLED(GPIOC_OSC32_IN) | \ + PIN_ASCR_DISABLED(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_ARD_A5) | \ + PIN_LOCKR_DISABLED(GPIOC_ARD_A4) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOC_ARD_D9) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOC_BUTTON) | \ + PIN_LOCKR_DISABLED(GPIOC_OSC32_IN) | \ + PIN_LOCKR_DISABLED(GPIOC_OSC32_OUT)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (analog). + * PD1 - PIN1 (analog). + * PD2 - PIN2 (analog). + * PD3 - PIN3 (analog). + * PD4 - PIN4 (analog). + * PD5 - PIN5 (analog). + * PD6 - PIN6 (analog). + * PD7 - PIN7 (analog). + * PD8 - PIN8 (analog). + * PD9 - PIN9 (analog). + * PD10 - PIN10 (analog). + * PD11 - PIN11 (analog). + * PD12 - PIN12 (analog). + * PD13 - PIN13 (analog). + * PD14 - PIN14 (analog). + * PD15 - PIN15 (analog). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \ + PIN_MODE_ANALOG(GPIOD_PIN1) | \ + PIN_MODE_ANALOG(GPIOD_PIN2) | \ + PIN_MODE_ANALOG(GPIOD_PIN3) | \ + PIN_MODE_ANALOG(GPIOD_PIN4) | \ + PIN_MODE_ANALOG(GPIOD_PIN5) | \ + PIN_MODE_ANALOG(GPIOD_PIN6) | \ + PIN_MODE_ANALOG(GPIOD_PIN7) | \ + PIN_MODE_ANALOG(GPIOD_PIN8) | \ + PIN_MODE_ANALOG(GPIOD_PIN9) | \ + PIN_MODE_ANALOG(GPIOD_PIN10) | \ + PIN_MODE_ANALOG(GPIOD_PIN11) | \ + PIN_MODE_ANALOG(GPIOD_PIN12) | \ + PIN_MODE_ANALOG(GPIOD_PIN13) | \ + PIN_MODE_ANALOG(GPIOD_PIN14) | \ + PIN_MODE_ANALOG(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ + PIN_OSPEED_HIGH(GPIOD_PIN1) | \ + PIN_OSPEED_HIGH(GPIOD_PIN2) | \ + PIN_OSPEED_HIGH(GPIOD_PIN3) | \ + PIN_OSPEED_HIGH(GPIOD_PIN4) | \ + PIN_OSPEED_HIGH(GPIOD_PIN5) | \ + PIN_OSPEED_HIGH(GPIOD_PIN6) | \ + PIN_OSPEED_HIGH(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_PIN8) | \ + PIN_OSPEED_HIGH(GPIOD_PIN9) | \ + PIN_OSPEED_HIGH(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_PIN11) | \ + PIN_OSPEED_HIGH(GPIOD_PIN12) | \ + PIN_OSPEED_HIGH(GPIOD_PIN13) | \ + PIN_OSPEED_HIGH(GPIOD_PIN14) | \ + PIN_OSPEED_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0U)) +#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \ + PIN_ASCR_DISABLED(GPIOD_PIN1) | \ + PIN_ASCR_DISABLED(GPIOD_PIN2) | \ + PIN_ASCR_DISABLED(GPIOD_PIN3) | \ + PIN_ASCR_DISABLED(GPIOD_PIN4) | \ + PIN_ASCR_DISABLED(GPIOD_PIN5) | \ + PIN_ASCR_DISABLED(GPIOD_PIN6) | \ + PIN_ASCR_DISABLED(GPIOD_PIN7) | \ + PIN_ASCR_DISABLED(GPIOD_PIN8) | \ + PIN_ASCR_DISABLED(GPIOD_PIN9) | \ + PIN_ASCR_DISABLED(GPIOD_PIN10) | \ + PIN_ASCR_DISABLED(GPIOD_PIN11) | \ + PIN_ASCR_DISABLED(GPIOD_PIN12) | \ + PIN_ASCR_DISABLED(GPIOD_PIN13) | \ + PIN_ASCR_DISABLED(GPIOD_PIN14) | \ + PIN_ASCR_DISABLED(GPIOD_PIN15)) +#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN15)) + +/* + * GPIOE setup: + * + * PE0 - PIN0 (analog). + * PE1 - PIN1 (analog). + * PE2 - PIN2 (analog). + * PE3 - PIN3 (analog). + * PE4 - PIN4 (analog). + * PE5 - PIN5 (analog). + * PE6 - PIN6 (analog). + * PE7 - PIN7 (analog). + * PE8 - PIN8 (analog). + * PE9 - PIN9 (analog). + * PE10 - PIN10 (analog). + * PE11 - PIN11 (analog). + * PE12 - PIN12 (analog). + * PE13 - PIN13 (analog). + * PE14 - PIN14 (analog). + * PE15 - PIN15 (analog). + */ +#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \ + PIN_MODE_ANALOG(GPIOE_PIN1) | \ + PIN_MODE_ANALOG(GPIOE_PIN2) | \ + PIN_MODE_ANALOG(GPIOE_PIN3) | \ + PIN_MODE_ANALOG(GPIOE_PIN4) | \ + PIN_MODE_ANALOG(GPIOE_PIN5) | \ + PIN_MODE_ANALOG(GPIOE_PIN6) | \ + PIN_MODE_ANALOG(GPIOE_PIN7) | \ + PIN_MODE_ANALOG(GPIOE_PIN8) | \ + PIN_MODE_ANALOG(GPIOE_PIN9) | \ + PIN_MODE_ANALOG(GPIOE_PIN10) | \ + PIN_MODE_ANALOG(GPIOE_PIN11) | \ + PIN_MODE_ANALOG(GPIOE_PIN12) | \ + PIN_MODE_ANALOG(GPIOE_PIN13) | \ + PIN_MODE_ANALOG(GPIOE_PIN14) | \ + PIN_MODE_ANALOG(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ + PIN_OSPEED_HIGH(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_PIN2) | \ + PIN_OSPEED_HIGH(GPIOE_PIN3) | \ + PIN_OSPEED_HIGH(GPIOE_PIN4) | \ + PIN_OSPEED_HIGH(GPIOE_PIN5) | \ + PIN_OSPEED_HIGH(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_PIN7) | \ + PIN_OSPEED_HIGH(GPIOE_PIN8) | \ + PIN_OSPEED_HIGH(GPIOE_PIN9) | \ + PIN_OSPEED_HIGH(GPIOE_PIN10) | \ + PIN_OSPEED_HIGH(GPIOE_PIN11) | \ + PIN_OSPEED_HIGH(GPIOE_PIN12) | \ + PIN_OSPEED_HIGH(GPIOE_PIN13) | \ + PIN_OSPEED_HIGH(GPIOE_PIN14) | \ + PIN_OSPEED_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0U)) +#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \ + PIN_ASCR_DISABLED(GPIOE_PIN1) | \ + PIN_ASCR_DISABLED(GPIOE_PIN2) | \ + PIN_ASCR_DISABLED(GPIOE_PIN3) | \ + PIN_ASCR_DISABLED(GPIOE_PIN4) | \ + PIN_ASCR_DISABLED(GPIOE_PIN5) | \ + PIN_ASCR_DISABLED(GPIOE_PIN6) | \ + PIN_ASCR_DISABLED(GPIOE_PIN7) | \ + PIN_ASCR_DISABLED(GPIOE_PIN8) | \ + PIN_ASCR_DISABLED(GPIOE_PIN9) | \ + PIN_ASCR_DISABLED(GPIOE_PIN10) | \ + PIN_ASCR_DISABLED(GPIOE_PIN11) | \ + PIN_ASCR_DISABLED(GPIOE_PIN12) | \ + PIN_ASCR_DISABLED(GPIOE_PIN13) | \ + PIN_ASCR_DISABLED(GPIOE_PIN14) | \ + PIN_ASCR_DISABLED(GPIOE_PIN15)) +#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN15)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (analog). + * PF1 - PIN1 (analog). + * PF2 - PIN2 (analog). + * PF3 - PIN3 (analog). + * PF4 - PIN4 (analog). + * PF5 - PIN5 (analog). + * PF6 - PIN6 (analog). + * PF7 - PIN7 (analog). + * PF8 - PIN8 (analog). + * PF9 - PIN9 (analog). + * PF10 - PIN10 (analog). + * PF11 - PIN11 (analog). + * PF12 - PIN12 (analog). + * PF13 - PIN13 (analog). + * PF14 - PIN14 (analog). + * PF15 - PIN15 (analog). + */ +#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \ + PIN_MODE_ANALOG(GPIOF_PIN1) | \ + PIN_MODE_ANALOG(GPIOF_PIN2) | \ + PIN_MODE_ANALOG(GPIOF_PIN3) | \ + PIN_MODE_ANALOG(GPIOF_PIN4) | \ + PIN_MODE_ANALOG(GPIOF_PIN5) | \ + PIN_MODE_ANALOG(GPIOF_PIN6) | \ + PIN_MODE_ANALOG(GPIOF_PIN7) | \ + PIN_MODE_ANALOG(GPIOF_PIN8) | \ + PIN_MODE_ANALOG(GPIOF_PIN9) | \ + PIN_MODE_ANALOG(GPIOF_PIN10) | \ + PIN_MODE_ANALOG(GPIOF_PIN11) | \ + PIN_MODE_ANALOG(GPIOF_PIN12) | \ + PIN_MODE_ANALOG(GPIOF_PIN13) | \ + PIN_MODE_ANALOG(GPIOF_PIN14) | \ + PIN_MODE_ANALOG(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ + PIN_OSPEED_HIGH(GPIOF_PIN1) | \ + PIN_OSPEED_HIGH(GPIOF_PIN2) | \ + PIN_OSPEED_HIGH(GPIOF_PIN3) | \ + PIN_OSPEED_HIGH(GPIOF_PIN4) | \ + PIN_OSPEED_HIGH(GPIOF_PIN5) | \ + PIN_OSPEED_HIGH(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_PIN7) | \ + PIN_OSPEED_HIGH(GPIOF_PIN8) | \ + PIN_OSPEED_HIGH(GPIOF_PIN9) | \ + PIN_OSPEED_HIGH(GPIOF_PIN10) | \ + PIN_OSPEED_HIGH(GPIOF_PIN11) | \ + PIN_OSPEED_HIGH(GPIOF_PIN12) | \ + PIN_OSPEED_HIGH(GPIOF_PIN13) | \ + PIN_OSPEED_HIGH(GPIOF_PIN14) | \ + PIN_OSPEED_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0U)) +#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \ + PIN_ASCR_DISABLED(GPIOF_PIN1) | \ + PIN_ASCR_DISABLED(GPIOF_PIN2) | \ + PIN_ASCR_DISABLED(GPIOF_PIN3) | \ + PIN_ASCR_DISABLED(GPIOF_PIN4) | \ + PIN_ASCR_DISABLED(GPIOF_PIN5) | \ + PIN_ASCR_DISABLED(GPIOF_PIN6) | \ + PIN_ASCR_DISABLED(GPIOF_PIN7) | \ + PIN_ASCR_DISABLED(GPIOF_PIN8) | \ + PIN_ASCR_DISABLED(GPIOF_PIN9) | \ + PIN_ASCR_DISABLED(GPIOF_PIN10) | \ + PIN_ASCR_DISABLED(GPIOF_PIN11) | \ + PIN_ASCR_DISABLED(GPIOF_PIN12) | \ + PIN_ASCR_DISABLED(GPIOF_PIN13) | \ + PIN_ASCR_DISABLED(GPIOF_PIN14) | \ + PIN_ASCR_DISABLED(GPIOF_PIN15)) +#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN15)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (analog). + * PG1 - PIN1 (analog). + * PG2 - PIN2 (analog). + * PG3 - PIN3 (analog). + * PG4 - PIN4 (analog). + * PG5 - PIN5 (analog). + * PG6 - PIN6 (analog). + * PG7 - PIN7 (analog). + * PG8 - PIN8 (analog). + * PG9 - PIN9 (analog). + * PG10 - PIN10 (analog). + * PG11 - PIN11 (analog). + * PG12 - PIN12 (analog). + * PG13 - PIN13 (analog). + * PG14 - PIN14 (analog). + * PG15 - PIN15 (analog). + */ +#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \ + PIN_MODE_ANALOG(GPIOG_PIN1) | \ + PIN_MODE_ANALOG(GPIOG_PIN2) | \ + PIN_MODE_ANALOG(GPIOG_PIN3) | \ + PIN_MODE_ANALOG(GPIOG_PIN4) | \ + PIN_MODE_ANALOG(GPIOG_PIN5) | \ + PIN_MODE_ANALOG(GPIOG_PIN6) | \ + PIN_MODE_ANALOG(GPIOG_PIN7) | \ + PIN_MODE_ANALOG(GPIOG_PIN8) | \ + PIN_MODE_ANALOG(GPIOG_PIN9) | \ + PIN_MODE_ANALOG(GPIOG_PIN10) | \ + PIN_MODE_ANALOG(GPIOG_PIN11) | \ + PIN_MODE_ANALOG(GPIOG_PIN12) | \ + PIN_MODE_ANALOG(GPIOG_PIN13) | \ + PIN_MODE_ANALOG(GPIOG_PIN14) | \ + PIN_MODE_ANALOG(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) +#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \ + PIN_ASCR_DISABLED(GPIOG_PIN1) | \ + PIN_ASCR_DISABLED(GPIOG_PIN2) | \ + PIN_ASCR_DISABLED(GPIOG_PIN3) | \ + PIN_ASCR_DISABLED(GPIOG_PIN4) | \ + PIN_ASCR_DISABLED(GPIOG_PIN5) | \ + PIN_ASCR_DISABLED(GPIOG_PIN6) | \ + PIN_ASCR_DISABLED(GPIOG_PIN7) | \ + PIN_ASCR_DISABLED(GPIOG_PIN8) | \ + PIN_ASCR_DISABLED(GPIOG_PIN9) | \ + PIN_ASCR_DISABLED(GPIOG_PIN10) | \ + PIN_ASCR_DISABLED(GPIOG_PIN11) | \ + PIN_ASCR_DISABLED(GPIOG_PIN12) | \ + PIN_ASCR_DISABLED(GPIOG_PIN13) | \ + PIN_ASCR_DISABLED(GPIOG_PIN14) | \ + PIN_ASCR_DISABLED(GPIOG_PIN15)) +#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN15)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (analog). + * PH3 - PIN3 (analog). + * PH4 - PIN4 (analog). + * PH5 - PIN5 (analog). + * PH6 - PIN6 (analog). + * PH7 - PIN7 (analog). + * PH8 - PIN8 (analog). + * PH9 - PIN9 (analog). + * PH10 - PIN10 (analog). + * PH11 - PIN11 (analog). + * PH12 - PIN12 (analog). + * PH13 - PIN13 (analog). + * PH14 - PIN14 (analog). + * PH15 - PIN15 (analog). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_ANALOG(GPIOH_PIN2) | \ + PIN_MODE_ANALOG(GPIOH_PIN3) | \ + PIN_MODE_ANALOG(GPIOH_PIN4) | \ + PIN_MODE_ANALOG(GPIOH_PIN5) | \ + PIN_MODE_ANALOG(GPIOH_PIN6) | \ + PIN_MODE_ANALOG(GPIOH_PIN7) | \ + PIN_MODE_ANALOG(GPIOH_PIN8) | \ + PIN_MODE_ANALOG(GPIOH_PIN9) | \ + PIN_MODE_ANALOG(GPIOH_PIN10) | \ + PIN_MODE_ANALOG(GPIOH_PIN11) | \ + PIN_MODE_ANALOG(GPIOH_PIN12) | \ + PIN_MODE_ANALOG(GPIOH_PIN13) | \ + PIN_MODE_ANALOG(GPIOH_PIN14) | \ + PIN_MODE_ANALOG(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) +#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_OSC_IN) | \ + PIN_ASCR_DISABLED(GPIOH_OSC_OUT) | \ + PIN_ASCR_DISABLED(GPIOH_PIN2) | \ + PIN_ASCR_DISABLED(GPIOH_PIN3) | \ + PIN_ASCR_DISABLED(GPIOH_PIN4) | \ + PIN_ASCR_DISABLED(GPIOH_PIN5) | \ + PIN_ASCR_DISABLED(GPIOH_PIN6) | \ + PIN_ASCR_DISABLED(GPIOH_PIN7) | \ + PIN_ASCR_DISABLED(GPIOH_PIN8) | \ + PIN_ASCR_DISABLED(GPIOH_PIN9) | \ + PIN_ASCR_DISABLED(GPIOH_PIN10) | \ + PIN_ASCR_DISABLED(GPIOH_PIN11) | \ + PIN_ASCR_DISABLED(GPIOH_PIN12) | \ + PIN_ASCR_DISABLED(GPIOH_PIN13) | \ + PIN_ASCR_DISABLED(GPIOH_PIN14) | \ + PIN_ASCR_DISABLED(GPIOH_PIN15)) +#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_OSC_IN) | \ + PIN_LOCKR_DISABLED(GPIOH_OSC_OUT) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN15)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/cfg/mcuconf.h b/cfg/mcuconf.h index c6a254b..0d4d5c1 100644 --- a/cfg/mcuconf.h +++ b/cfg/mcuconf.h @@ -1,483 +1,7 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32H7xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32H7xx_MCUCONF -#define STM32H723_MCUCONF -#define STM32H725_MCUCONF -//#define STM32H743_MCUCONF - -/* - * General settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_TARGET_CORE 1 - -/* - * Memory attributes settings. - */ -#define STM32_NOCACHE_MPU_REGION MPU_REGION_1 -#define STM32_NOCACHE_SRAM1_SRAM2 FALSE -#define STM32_NOCACHE_SRAM3 FALSE -#define STM32_NOCACHE_ALLSRAM TRUE - -/* - * PWR system settings. - * Reading STM32 Reference Manual is required, settings in PWR_CR3 are - * very critical. - * Register constants are taken from the ST header. - */ -#define STM32_VOS STM32_VOS_SCALE1 -#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0) -#define STM32_PWR_CR2 (PWR_CR2_BREN) -#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN) -#define STM32_PWR_CPUCR 0 - -/* - * Clock tree static settings. - * Reading STM32 Reference Manual is required. - */ -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_CSI_ENABLED FALSE -#define STM32_HSI48_ENABLED TRUE -#define STM32_HSE_ENABLED FALSE -#define STM32_LSE_ENABLED FALSE -#define STM32_HSIDIV STM32_HSIDIV_DIV8 // HSI = 8MHz - -/* - * PLLs static settings. - * Reading STM32 Reference Manual is required. - */ -#define STM32_PLLSRC STM32_PLLSRC_HSI_CK -#define STM32_PLLCFGR_MASK ~0 -#define STM32_PLL1_ENABLED TRUE -#define STM32_PLL1_P_ENABLED TRUE -#define STM32_PLL1_Q_ENABLED FALSE -#define STM32_PLL1_R_ENABLED FALSE -#define STM32_PLL1_DIVM_VALUE 4 // 8 / 4 = 2MHz -#define STM32_PLL1_DIVN_VALUE 240 // = 2 * 240 -#define STM32_PLL1_FRACN_VALUE 0 -#define STM32_PLL1_DIVP_VALUE 1 // = 480MHz -#define STM32_PLL1_DIVQ_VALUE 16 -#define STM32_PLL1_DIVR_VALUE 8 -#define STM32_PLL2_ENABLED TRUE // PLL2 adjusted by adc.cpp -#define STM32_PLL2_P_ENABLED TRUE -#define STM32_PLL2_Q_ENABLED FALSE -#define STM32_PLL2_R_ENABLED FALSE -#define STM32_PLL2_DIVM_VALUE 4 -#define STM32_PLL2_DIVN_VALUE 80 -#define STM32_PLL2_FRACN_VALUE 0 -#define STM32_PLL2_DIVP_VALUE 20 -#define STM32_PLL2_DIVQ_VALUE 8 -#define STM32_PLL2_DIVR_VALUE 8 -#define STM32_PLL3_ENABLED FALSE -#define STM32_PLL3_P_ENABLED FALSE -#define STM32_PLL3_Q_ENABLED FALSE -#define STM32_PLL3_R_ENABLED FALSE -#define STM32_PLL3_DIVM_VALUE 4 -#define STM32_PLL3_DIVN_VALUE 400 -#define STM32_PLL3_FRACN_VALUE 0 -#define STM32_PLL3_DIVP_VALUE 8 -#define STM32_PLL3_DIVQ_VALUE 8 -#define STM32_PLL3_DIVR_VALUE 8 - -/* - * Core clocks dynamic settings (can be changed at runtime). - * Reading STM32 Reference Manual is required. - */ -#define STM32_SW STM32_SW_PLL1_P_CK -#define STM32_RTCSEL STM32_RTCSEL_LSI_CK -#define STM32_D1CPRE STM32_D1CPRE_DIV1 -#define STM32_D1HPRE STM32_D1HPRE_DIV2 // /2 = 240MHz -#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2 -#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2 -#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2 -#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2 - -/* - * Peripherals clocks static settings. - * Reading STM32 Reference Manual is required. - */ -#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK -#define STM32_MCO1PRE_VALUE 4 -#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK -#define STM32_MCO2PRE_VALUE 4 -#define STM32_TIMPRE_ENABLE TRUE -#define STM32_HRTIMSEL 0 -#define STM32_STOPKERWUCK 0 -#define STM32_STOPWUCK 0 -#define STM32_RTCPRE_VALUE 8 -#define STM32_CKPERSEL STM32_CKPERSEL_HSI_CK -#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK -//#define STM32_OCTOSPISEL STM32_OCTOSPISEL_HCLK -//#define STM32_FMCSEL STM32_OCTOSPISEL_HCLK -#define STM32_SWPSEL STM32_SWPSEL_PCLK1 -#define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK -#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 -#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK -#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2 -#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK -//#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK -#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK -#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 -#define STM32_CECSEL STM32_CECSEL_LSE_CK -#define STM32_USBSEL STM32_USBSEL_HSI48_CK -#define STM32_I2C1235SEL STM32_I2C1235SEL_PCLK1 -#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK -#define STM32_USART16910SEL STM32_USART16910SEL_PCLK2 -#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1 -#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4 -#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK -#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK -#define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK -#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4 -#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4 -#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4 -#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4 - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 6 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_21_PRIORITY 6 - -#define STM32_IRQ_FDCAN1_PRIORITY 10 -#define STM32_IRQ_FDCAN2_PRIORITY 10 - -#define STM32_IRQ_MDMA_PRIORITY 9 - -#define STM32_IRQ_QUADSPI1_PRIORITY 10 - -#define STM32_IRQ_SDMMC1_PRIORITY 9 -#define STM32_IRQ_SDMMC2_PRIORITY 9 - -#define STM32_IRQ_TIM1_UP_PRIORITY 7 -#define STM32_IRQ_TIM1_CC_PRIORITY 7 -#define STM32_IRQ_TIM2_PRIORITY 7 -#define STM32_IRQ_TIM3_PRIORITY 7 -#define STM32_IRQ_TIM4_PRIORITY 7 -#define STM32_IRQ_TIM5_PRIORITY 7 -#define STM32_IRQ_TIM6_PRIORITY 7 -#define STM32_IRQ_TIM7_PRIORITY 7 -#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 -#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 -#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 -#define STM32_IRQ_TIM8_CC_PRIORITY 7 -#define STM32_IRQ_TIM15_PRIORITY 7 -#define STM32_IRQ_TIM16_PRIORITY 7 -#define STM32_IRQ_TIM17_PRIORITY 7 - -#define STM32_IRQ_USART1_PRIORITY 12 -#define STM32_IRQ_USART2_PRIORITY 12 -#define STM32_IRQ_USART3_PRIORITY 12 -#define STM32_IRQ_UART4_PRIORITY 12 -#define STM32_IRQ_UART5_PRIORITY 12 -#define STM32_IRQ_USART6_PRIORITY 12 -#define STM32_IRQ_UART7_PRIORITY 12 -#define STM32_IRQ_UART8_PRIORITY 12 -#define STM32_IRQ_LPUART1_PRIORITY 12 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_DUAL_MODE FALSE -#define STM32_ADC_COMPACT_SAMPLES FALSE -#define STM32_ADC_USE_ADC12 FALSE -#define STM32_ADC_USE_ADC3 TRUE -#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY -#define STM32_ADC_ADC12_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_ADC12_IRQ_PRIORITY 5 -#define STM32_ADC_ADC3_IRQ_PRIORITY 5 -#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 -#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_ADCCK -#define STM32_ADC_ADC3_PRESC (5 << ADC_CCR_PRESC_Pos) // /10 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_FDCAN1 FALSE -#define STM32_CAN_USE_FDCAN2 FALSE - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 TRUE -#define STM32_DAC_USE_DAC1_CH2 TRUE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 TRUE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM13 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_USE_TIM15 FALSE -#define STM32_GPT_USE_TIM16 FALSE -#define STM32_GPT_USE_TIM17 FALSE - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_USE_I2C4 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY -#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C4_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_I2C4_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM12 FALSE -#define STM32_ICU_USE_TIM13 FALSE -#define STM32_ICU_USE_TIM14 FALSE -#define STM32_ICU_USE_TIM15 FALSE -#define STM32_ICU_USE_TIM16 FALSE -#define STM32_ICU_USE_TIM17 FALSE - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM12 FALSE -#define STM32_PWM_USE_TIM13 FALSE -#define STM32_PWM_USE_TIM14 FALSE -#define STM32_PWM_USE_TIM15 FALSE -#define STM32_PWM_USE_TIM16 FALSE -#define STM32_PWM_USE_TIM17 FALSE - -/* - * RTC driver system settings. - */ -#define STM32_RTC_PRESA_VALUE 32 -#define STM32_RTC_PRESS_VALUE 1024 -#define STM32_RTC_CR_INIT 0 -#define STM32_RTC_TAMPCR_INIT 0 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_USE_SDMMC1 FALSE -#define STM32_SDC_USE_SDMMC2 FALSE -#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000000 -#define STM32_SDC_SDMMC_READ_TIMEOUT 1000000 -#define STM32_SDC_SDMMC_CLOCK_DELAY 10 -#define STM32_SDC_SDMMC_PWRSAV TRUE - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 FALSE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_USE_SPI5 FALSE -#define STM32_SPI_USE_SPI6 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY -#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI5_DMA_PRIORITY 1 -#define STM32_SPI_SPI6_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_SPI5_IRQ_PRIORITY 10 -#define STM32_SPI_SPI6_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * TRNG driver system settings. - */ -#define STM32_TRNG_USE_RNG1 FALSE - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USE_UART7 FALSE -#define STM32_UART_USE_UART8 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_UART7_DMA_PRIORITY 0 -#define STM32_UART_UART8_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 TRUE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_HOST_WAKEUP_DURATION 2 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -/* - * WSPI driver system settings. - */ -#define STM32_WSPI_USE_QUADSPI1 FALSE -#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 -#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY -#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1 -#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure") - -#endif /* MCUCONF_H */ +#if defined(TARGET_PLATFORM_L4) +#include "mcuconf_l4.h" +#elif defined(TARGET_PLATFORM_H7) +#include "mcuconf_h7.h" +#elif defined(TARGET_PLATFORM_G4) +#include "mcuconf_g4.h" +#endif diff --git a/cfg/mcuconf_h7.h b/cfg/mcuconf_h7.h new file mode 100644 index 0000000..c6a254b --- /dev/null +++ b/cfg/mcuconf_h7.h @@ -0,0 +1,483 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32H7xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32H7xx_MCUCONF +#define STM32H723_MCUCONF +#define STM32H725_MCUCONF +//#define STM32H743_MCUCONF + +/* + * General settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_TARGET_CORE 1 + +/* + * Memory attributes settings. + */ +#define STM32_NOCACHE_MPU_REGION MPU_REGION_1 +#define STM32_NOCACHE_SRAM1_SRAM2 FALSE +#define STM32_NOCACHE_SRAM3 FALSE +#define STM32_NOCACHE_ALLSRAM TRUE + +/* + * PWR system settings. + * Reading STM32 Reference Manual is required, settings in PWR_CR3 are + * very critical. + * Register constants are taken from the ST header. + */ +#define STM32_VOS STM32_VOS_SCALE1 +#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0) +#define STM32_PWR_CR2 (PWR_CR2_BREN) +#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN) +#define STM32_PWR_CPUCR 0 + +/* + * Clock tree static settings. + * Reading STM32 Reference Manual is required. + */ +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_CSI_ENABLED FALSE +#define STM32_HSI48_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_HSIDIV STM32_HSIDIV_DIV8 // HSI = 8MHz + +/* + * PLLs static settings. + * Reading STM32 Reference Manual is required. + */ +#define STM32_PLLSRC STM32_PLLSRC_HSI_CK +#define STM32_PLLCFGR_MASK ~0 +#define STM32_PLL1_ENABLED TRUE +#define STM32_PLL1_P_ENABLED TRUE +#define STM32_PLL1_Q_ENABLED FALSE +#define STM32_PLL1_R_ENABLED FALSE +#define STM32_PLL1_DIVM_VALUE 4 // 8 / 4 = 2MHz +#define STM32_PLL1_DIVN_VALUE 240 // = 2 * 240 +#define STM32_PLL1_FRACN_VALUE 0 +#define STM32_PLL1_DIVP_VALUE 1 // = 480MHz +#define STM32_PLL1_DIVQ_VALUE 16 +#define STM32_PLL1_DIVR_VALUE 8 +#define STM32_PLL2_ENABLED TRUE // PLL2 adjusted by adc.cpp +#define STM32_PLL2_P_ENABLED TRUE +#define STM32_PLL2_Q_ENABLED FALSE +#define STM32_PLL2_R_ENABLED FALSE +#define STM32_PLL2_DIVM_VALUE 4 +#define STM32_PLL2_DIVN_VALUE 80 +#define STM32_PLL2_FRACN_VALUE 0 +#define STM32_PLL2_DIVP_VALUE 20 +#define STM32_PLL2_DIVQ_VALUE 8 +#define STM32_PLL2_DIVR_VALUE 8 +#define STM32_PLL3_ENABLED FALSE +#define STM32_PLL3_P_ENABLED FALSE +#define STM32_PLL3_Q_ENABLED FALSE +#define STM32_PLL3_R_ENABLED FALSE +#define STM32_PLL3_DIVM_VALUE 4 +#define STM32_PLL3_DIVN_VALUE 400 +#define STM32_PLL3_FRACN_VALUE 0 +#define STM32_PLL3_DIVP_VALUE 8 +#define STM32_PLL3_DIVQ_VALUE 8 +#define STM32_PLL3_DIVR_VALUE 8 + +/* + * Core clocks dynamic settings (can be changed at runtime). + * Reading STM32 Reference Manual is required. + */ +#define STM32_SW STM32_SW_PLL1_P_CK +#define STM32_RTCSEL STM32_RTCSEL_LSI_CK +#define STM32_D1CPRE STM32_D1CPRE_DIV1 +#define STM32_D1HPRE STM32_D1HPRE_DIV2 // /2 = 240MHz +#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2 +#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2 +#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2 +#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2 + +/* + * Peripherals clocks static settings. + * Reading STM32 Reference Manual is required. + */ +#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK +#define STM32_MCO1PRE_VALUE 4 +#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK +#define STM32_MCO2PRE_VALUE 4 +#define STM32_TIMPRE_ENABLE TRUE +#define STM32_HRTIMSEL 0 +#define STM32_STOPKERWUCK 0 +#define STM32_STOPWUCK 0 +#define STM32_RTCPRE_VALUE 8 +#define STM32_CKPERSEL STM32_CKPERSEL_HSI_CK +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK +//#define STM32_OCTOSPISEL STM32_OCTOSPISEL_HCLK +//#define STM32_FMCSEL STM32_OCTOSPISEL_HCLK +#define STM32_SWPSEL STM32_SWPSEL_PCLK1 +#define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK +#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 +#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK +#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2 +#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK +//#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK +#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE_CK +#define STM32_USBSEL STM32_USBSEL_HSI48_CK +#define STM32_I2C1235SEL STM32_I2C1235SEL_PCLK1 +#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK +#define STM32_USART16910SEL STM32_USART16910SEL_PCLK2 +#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1 +#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4 +#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK +#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK +#define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK +#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4 +#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4 +#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4 + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 6 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_21_PRIORITY 6 + +#define STM32_IRQ_FDCAN1_PRIORITY 10 +#define STM32_IRQ_FDCAN2_PRIORITY 10 + +#define STM32_IRQ_MDMA_PRIORITY 9 + +#define STM32_IRQ_QUADSPI1_PRIORITY 10 + +#define STM32_IRQ_SDMMC1_PRIORITY 9 +#define STM32_IRQ_SDMMC2_PRIORITY 9 + +#define STM32_IRQ_TIM1_UP_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 +#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 +#define STM32_IRQ_TIM15_PRIORITY 7 +#define STM32_IRQ_TIM16_PRIORITY 7 +#define STM32_IRQ_TIM17_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 +#define STM32_IRQ_UART7_PRIORITY 12 +#define STM32_IRQ_UART8_PRIORITY 12 +#define STM32_IRQ_LPUART1_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_DUAL_MODE FALSE +#define STM32_ADC_COMPACT_SAMPLES FALSE +#define STM32_ADC_USE_ADC12 FALSE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 +#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_ADCCK +#define STM32_ADC_ADC3_PRESC (5 << ADC_CCR_PRESC_Pos) // /10 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_FDCAN1 FALSE +#define STM32_CAN_USE_FDCAN2 FALSE + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 TRUE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 TRUE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM13 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_USE_TIM15 FALSE +#define STM32_GPT_USE_TIM16 FALSE +#define STM32_GPT_USE_TIM17 FALSE + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY +#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM12 FALSE +#define STM32_ICU_USE_TIM13 FALSE +#define STM32_ICU_USE_TIM14 FALSE +#define STM32_ICU_USE_TIM15 FALSE +#define STM32_ICU_USE_TIM16 FALSE +#define STM32_ICU_USE_TIM17 FALSE + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM12 FALSE +#define STM32_PWM_USE_TIM13 FALSE +#define STM32_PWM_USE_TIM14 FALSE +#define STM32_PWM_USE_TIM15 FALSE +#define STM32_PWM_USE_TIM16 FALSE +#define STM32_PWM_USE_TIM17 FALSE + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_RTC_CR_INIT 0 +#define STM32_RTC_TAMPCR_INIT 0 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_USE_SDMMC2 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC_PWRSAV TRUE + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY +#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * TRNG driver system settings. + */ +#define STM32_TRNG_USE_RNG1 FALSE + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 TRUE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_HOST_WAKEUP_DURATION 2 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +/* + * WSPI driver system settings. + */ +#define STM32_WSPI_USE_QUADSPI1 FALSE +#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 +#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY +#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1 +#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure") + +#endif /* MCUCONF_H */ diff --git a/cfg/mcuconf_l4.h b/cfg/mcuconf_l4.h new file mode 100644 index 0000000..438e0be --- /dev/null +++ b/cfg/mcuconf_l4.h @@ -0,0 +1,360 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32L4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define STM32L4xx_MCUCONF +#define STM32L476_MCUCONF +//#define STM32L432_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_RANGE1 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI16_ENABLED FALSE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_MSIPLL_ENABLED FALSE +#define STM32_MSIRANGE STM32_MSIRANGE_8M +#define STM32_MSISRANGE STM32_MSISRANGE_4M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_MSI +#define STM32_PLLM_VALUE 2 +#define STM32_PLLN_VALUE 72 +#define STM32_PLLP_VALUE 7 +#define STM32_PLLQ_VALUE 6 +#define STM32_PLLR_VALUE 4 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_STOPWUCK STM32_STOPWUCK_MSI +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK +#define STM32_PLLSAI1N_VALUE 24 +#define STM32_PLLSAI1P_VALUE 7 +#define STM32_PLLSAI1Q_VALUE 2 +#define STM32_PLLSAI1R_VALUE 4 +#define STM32_PLLSAI2N_VALUE 24 +#define STM32_PLLSAI2P_VALUE 7 +#define STM32_PLLSAI2R_VALUE 8 + +/* + * Peripherals clock sources. + */ +#define STM32_USART1SEL STM32_USART1SEL_SYSCLK +#define STM32_USART2SEL STM32_USART2SEL_SYSCLK +#define STM32_USART3SEL STM32_USART3SEL_SYSCLK +#define STM32_UART4SEL STM32_UART4SEL_SYSCLK +#define STM32_UART5SEL STM32_UART5SEL_SYSCLK +#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK +#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK +#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK +#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 +#define STM32_ADCSEL STM32_ADCSEL_PLLSAI2 +#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 +#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2 +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI1635_38_PRIORITY 6 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_22_PRIORITY 15 + +#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_LPUART1_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_DUAL_MODE FALSE +#define STM32_ADC_COMPACT_SAMPLES FALSE +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_ADCCK +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV10 + +//#define ADC123_PRESC_VALUE 1 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 TRUE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 TRUE +#define STM32_GPT_USE_TIM7 TRUE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM15 FALSE +#define STM32_GPT_USE_TIM16 FALSE +#define STM32_GPT_USE_TIM17 FALSE + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM15 FALSE +#define STM32_ICU_USE_TIM16 FALSE +#define STM32_ICU_USE_TIM17 FALSE + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM15 FALSE +#define STM32_PWM_USE_TIM16 FALSE +#define STM32_PWM_USE_TIM17 FALSE + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_RTC_CR_INIT 0 +#define STM32_RTC_TAMPCR_INIT 0 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_LPUART1 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_LPUART1_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * TRNG driver system settings. + */ +#define STM32_TRNG_USE_RNG1 FALSE + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#ifdef STM32L476_MCUCONF +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#else +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 +#endif // STM32L476_MCUCONF + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +/* + * WSPI driver system settings. + */ +#define STM32_WSPI_USE_QUADSPI1 FALSE +#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) + +#endif /* MCUCONF_H */ diff --git a/gui/stmdsp.cpp b/gui/stmdsp.cpp index 5ea18af..2293c71 100644 --- a/gui/stmdsp.cpp +++ b/gui/stmdsp.cpp @@ -31,8 +31,16 @@ namespace stmdsp { if (m_serial.isOpen()) { m_serial.write("i"); - if (m_serial.read(6) != "stmdsp") + if (auto id = m_serial.read(7); id.starts_with("stmdsp")) { + if (id.back() == 'h') + m_platform = platform::H7; + else if (id.back() == 'l') + m_platform = platform::L4; + else + m_serial.close(); + } else { m_serial.close(); + } } } diff --git a/gui/stmdsp.hpp b/gui/stmdsp.hpp index a22a55d..d56a1ab 100644 --- a/gui/stmdsp.hpp +++ b/gui/stmdsp.hpp @@ -39,6 +39,13 @@ namespace stmdsp using adcsample_t = uint16_t; using dacsample_t = uint16_t; + enum class platform { + Unknown, + H7, + L4, + G4 + }; + class device { public: @@ -52,8 +59,7 @@ namespace stmdsp return m_serial.isOpen(); } - //std::vector sample(unsigned long int count = 1); - + auto get_platform() const { return m_platform; } void continuous_set_buffer_size(unsigned int size); unsigned int get_buffer_size() const { return m_buffer_size; } void set_sample_rate(unsigned int id); @@ -76,6 +82,7 @@ namespace stmdsp private: serial::Serial m_serial; + platform m_platform = platform::Unknown; unsigned int m_buffer_size = SAMPLES_MAX; bool m_is_siggening = false; }; diff --git a/gui/wxmain.cpp b/gui/wxmain.cpp index e5f0d4d..d020bef 100644 --- a/gui/wxmain.cpp +++ b/gui/wxmain.cpp @@ -46,10 +46,10 @@ static const std::array srateNums { 96000 }; -static const char *makefile_text = R"make( +static const char *makefile_text_h7 = R"make( all: @arm-none-eabi-g++ -x c++ -Os -fno-exceptions -fno-rtti \ - -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 -mtune=cortex-m7 \ + -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 -mtune=cortex-m7 \ -nostartfiles \ -Wl,-Ttext-segment=0x00000000 -Wl,-zmax-page-size=512 -Wl,-eprocess_data_entry \ $0 -o $0.o @@ -61,8 +61,23 @@ all: $0.o arm-none-eabi-size $0.o )make"; +static const char *makefile_text_l4 = R"make( +all: + @arm-none-eabi-g++ -x c++ -Os -fno-exceptions -fno-rtti \ + -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mtune=cortex-m4 \ + -nostartfiles \ + -Wl,-Ttext-segment=0x10000000 -Wl,-zmax-page-size=512 -Wl,-eprocess_data_entry \ + $0 -o $0.o + @cp $0.o $0.orig.o + @arm-none-eabi-strip -s -S --strip-unneeded $0.o + @arm-none-eabi-objcopy --remove-section .ARM.attributes \ + --remove-section .comment \ + --remove-section .noinit \ + $0.o + arm-none-eabi-size $0.o +)make"; -static const char *file_header = R"cpp( +static const char *file_header_h7 = R"cpp( #include using adcsample_t = uint16_t; @@ -103,18 +118,63 @@ return 0; } __attribute__((naked)) auto sqrt(double x) { -asm("vmov.f64 r1, r2, d0;" - "mov r0, #3;" +asm("vsqrt.f64 d0, d0; bx lr"); +return 0; +} + +// End stmdspgui header code + +)cpp"; +static const char *file_header_l4 = R"cpp( +#include + +using adcsample_t = uint16_t; +constexpr unsigned int SIZE = $0; +adcsample_t *process_data(adcsample_t *samples, unsigned int size); +extern "C" void process_data_entry() +{ + ((void (*)())process_data)(); +} + +constexpr float PI = 3.14159265358979L; +__attribute__((naked)) +auto sin(float x) { +asm("vmov.f32 r1, s0;" + "eor r0, r0;" + "svc 1;" + "vmov.f32 s0, r1;" + "bx lr"); +return 0; +} +__attribute__((naked)) +auto cos(float x) { +asm("vmov.f32 r1, s0;" + "mov r0, #1;" "svc 1;" - "vmov.f64 d0, r1, r2;" + "vmov.f32 s0, r1;" + "bx lr"); +return 0; +} +__attribute__((naked)) +auto tan(double x) { +asm("vmov.f32 r1, s0;" + "mov r0, #2;" + "svc 1;" + "vmov.f32 s0, r1;" "bx lr"); return 0; } +__attribute__((naked)) +auto sqrt(float) { +asm("vsqrt.f32 s0, s0; bx lr"); +return 0; +} // End stmdspgui header code )cpp"; + static const char *file_content = R"cpp(adcsample_t *process_data(adcsample_t *samples, unsigned int size) { @@ -416,14 +476,16 @@ wxString MainFrame::compileEditorCode() m_temp_file_name = wxFileName::CreateTempFileName("stmdspgui"); wxFile file (m_temp_file_name, wxFile::write); - wxString file_text (file_header); + wxString file_text (m_device->get_platform() == stmdsp::platform::L4 ? file_header_l4 + : file_header_h7); file_text.Replace("$0", std::to_string(m_device ? m_device->get_buffer_size() : stmdsp::SAMPLES_MAX)); file.Write(wxString(file_text) + m_text_editor->GetText()); file.Close(); wxFile makefile (m_temp_file_name + "make", wxFile::write); - wxString make_text (makefile_text); + wxString make_text (m_device->get_platform() == stmdsp::platform::L4 ? makefile_text_l4 + : makefile_text_h7); make_text.Replace("$0", m_temp_file_name); makefile.Write(make_text); makefile.Close(); diff --git a/source/adc.cpp b/source/adc.cpp index b0c0312..b9fe34c 100644 --- a/source/adc.cpp +++ b/source/adc.cpp @@ -11,11 +11,26 @@ #include "adc.hpp" +#if defined(TARGET_PLATFORM_L4) +ADCDriver *ADC::m_driver = &ADCD1; +ADCDriver *ADC::m_driver2 = &ADCD3; +#else ADCDriver *ADC::m_driver = &ADCD3; +//ADCDriver *ADC::m_driver2 = &ADCD1; // TODO +#endif const ADCConfig ADC::m_config = { .difsel = 0, +#if defined(TARGET_PLATFORM_H7) .calibration = 0, +#endif +}; + +const ADCConfig ADC::m_config2 = { + .difsel = 0, +#if defined(TARGET_PLATFORM_H7) + .calibration = 0, +#endif }; ADCConversionGroup ADC::m_group_config = { @@ -25,11 +40,19 @@ ADCConversionGroup ADC::m_group_config = { .error_cb = nullptr, .cfgr = ADC_CFGR_EXTEN_RISING | ADC_CFGR_EXTSEL_SRC(13), /* TIM6_TRGO */ .cfgr2 = ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSS_0, // Oversampling 2x +#if defined(TARGET_PLATFORM_H7) .ccr = 0, .pcsel = 0, - .ltr1 = 0, .htr1 = 0x0FFF, - .ltr2 = 0, .htr2 = 0x0FFF, - .ltr3 = 0, .htr3 = 0x0FFF, + .ltr1 = 0, .htr1 = 4095, + .ltr2 = 0, .htr2 = 4095, + .ltr3 = 0, .htr3 = 4095, +#else + .tr1 = ADC_TR(0, 4095), + .tr2 = ADC_TR(0, 4095), + .tr3 = ADC_TR(0, 4095), + .awd2cr = 0, + .awd3cr = 0, +#endif .smpr = { ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_12P5), 0 }, @@ -39,54 +62,55 @@ ADCConversionGroup ADC::m_group_config = { }, }; -std::array, 6> ADC::m_rate_presets = {{ - // Rate PLL N PLL P - {/* 8k */ 80, 20}, - {/* 16k */ 80, 10}, - {/* 20k */ 80, 8}, - {/* 32k */ 80, 5}, - {/* 48k */ 96, 4}, - {/* 96k */ 288, 10} -}}; +static bool readAltDone = false; +static void readAltCallback(ADCDriver *) +{ + readAltDone = true; +} +ADCConversionGroup ADC::m_group_config2 = { + .circular = false, + .num_channels = 1, + .end_cb = readAltCallback, + .error_cb = nullptr, + .cfgr = ADC_CFGR_EXTEN_RISING | ADC_CFGR_EXTSEL_SRC(13), /* TIM6_TRGO */ + .cfgr2 = ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSS_0, // Oversampling 2x +#if defined(TARGET_PLATFORM_H7) + .ccr = 0, + .pcsel = 0, + .ltr1 = 0, .htr1 = 4095, + .ltr2 = 0, .htr2 = 4095, + .ltr3 = 0, .htr3 = 4095, +#else + .tr1 = ADC_TR(0, 4095), + .tr2 = ADC_TR(0, 4095), + .tr3 = ADC_TR(0, 4095), + .awd2cr = 0, + .awd3cr = 0, +#endif + .smpr = { + ADC_SMPR1_SMP_AN1(ADC_SMPR_SMP_12P5), 0 + }, + .sqr = { + ADC_SQR1_SQ1_N(ADC_CHANNEL_IN1), + 0, 0, 0 + }, +}; adcsample_t *ADC::m_current_buffer = nullptr; size_t ADC::m_current_buffer_size = 0; ADC::Operation ADC::m_operation = nullptr; -//static const ADCConfig m_config2 = {}; -//ADCConversionGroup m_group_config2 = { -// .circular = false, -// .num_channels = 1, -// .end_cb = nullptr, -// .error_cb = nullptr, -// .cfgr = 0, -// .cfgr2 = 0, -// .ccr = 0, -// .pcsel = 0, -// .ltr1 = 0, .htr1 = 0x0FFF, -// .ltr2 = 0, .htr2 = 0x0FFF, -// .ltr3 = 0, .htr3 = 0x0FFF, -// .smpr = { -// ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_12P5), 0 -// }, -// .sqr = { -// ADC_SQR1_SQ1_N(ADC_CHANNEL_IN10), -// 0, 0, 0 -// }, -//}; - void ADC::begin() { +#if defined(TARGET_PLATFORM_H7) palSetPadMode(GPIOF, 3, PAL_MODE_INPUT_ANALOG); - - //palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG); - //adcStart(&ADCD1, &m_config2); - //adcsample_t val = 0; - //adcConvert(&ADCD1, &m_group_config2, &val, 1); - //adcStop(&ADCD1); +#else + palSetPadMode(GPIOA, 0, PAL_MODE_INPUT_ANALOG); // Algorithm in + palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG); // Potentiometer 1 +#endif adcStart(m_driver, &m_config); - adcSTM32EnableVREF(m_driver); + adcStart(m_driver2, &m_config2); } void ADC::start(adcsample_t *buffer, size_t count, Operation operation) @@ -109,8 +133,32 @@ void ADC::stop() m_operation = nullptr; } +adcsample_t ADC::readAlt(unsigned int id) +{ + if (id != 0) + return 0; + static adcsample_t result[32] = {}; + readAltDone = false; + adcStartConversion(m_driver2, &m_group_config2, result, 32); + while (!readAltDone) + ; + adcStopConversion(m_driver2); + return result[0]; +} + void ADC::setRate(SClock::Rate rate) { +#if defined(TARGET_PLATFORM_H7) + std::array, 6> m_rate_presets = {{ + // Rate PLL N PLL P + {/* 8k */ 80, 20}, + {/* 16k */ 80, 10}, + {/* 20k */ 80, 8}, + {/* 32k */ 80, 5}, + {/* 48k */ 96, 4}, + {/* 96k */ 288, 10} + }}; + auto& preset = m_rate_presets[static_cast(rate)]; auto pllbits = (preset[0] << RCC_PLL2DIVR_N2_Pos) | (preset[1] << RCC_PLL2DIVR_P2_Pos); @@ -131,6 +179,33 @@ void ADC::setRate(SClock::Rate rate) : ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_2P5); adcStart(m_driver, &m_config); +#elif defined(TARGET_PLATFORM_L4) + std::array, 6> m_rate_presets = {{ + // Rate PLLSAI2N R OVERSAMPLE + {/* 8k */ 16, 3, 1}, + {/* 16k */ 32, 3, 1}, + {/* 20k */ 40, 3, 1}, + {/* 32k */ 64, 3, 1}, + {/* 48k */ 24, 3, 0}, + {/* 96k */ 48, 3, 0} + }}; + + auto& preset = m_rate_presets[static_cast(rate)]; + auto pllnr = (preset[0] << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + (preset[1] << RCC_PLLSAI2CFGR_PLLSAI2R_Pos); + bool oversample = preset[2] != 0; + + // Adjust PLLSAI2 + RCC->CR &= ~(RCC_CR_PLLSAI2ON); + while ((RCC->CR & RCC_CR_PLLSAI2RDY) == RCC_CR_PLLSAI2RDY); + RCC->PLLSAI2CFGR = (RCC->PLLSAI2CFGR & ~(RCC_PLLSAI2CFGR_PLLSAI2N_Msk | RCC_PLLSAI2CFGR_PLLSAI2R_Msk)) | pllnr; + RCC->CR |= RCC_CR_PLLSAI2ON; + while ((RCC->CR & RCC_CR_PLLSAI2RDY) != RCC_CR_PLLSAI2RDY); + + // Set 2x oversampling + m_group_config.cfgr2 = oversample ? ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_0 | ADC_CFGR2_OVSS_1 : 0; + m_group_config2.cfgr2 = oversample ? ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_0 | ADC_CFGR2_OVSS_1 : 0; +#endif } void ADC::setOperation(ADC::Operation operation) diff --git a/source/adc.hpp b/source/adc.hpp index d9a435a..24a7fff 100644 --- a/source/adc.hpp +++ b/source/adc.hpp @@ -27,16 +27,19 @@ public: static void start(adcsample_t *buffer, size_t count, Operation operation); static void stop(); + static adcsample_t readAlt(unsigned int id); + static void setRate(SClock::Rate rate); static void setOperation(Operation operation); private: static ADCDriver *m_driver; + static ADCDriver *m_driver2; static const ADCConfig m_config; + static const ADCConfig m_config2; static ADCConversionGroup m_group_config; - - static std::array, 6> m_rate_presets; + static ADCConversionGroup m_group_config2; static adcsample_t *m_current_buffer; static size_t m_current_buffer_size; diff --git a/source/cordic.cpp b/source/cordic.cpp index 4852563..d2997f2 100644 --- a/source/cordic.cpp +++ b/source/cordic.cpp @@ -1,7 +1,8 @@ #include "cordic.hpp" #include "hal.h" -namespace math { +namespace cordic { +#if !defined(TARGET_PLATFORM_L4) void init() { @@ -92,11 +93,16 @@ double tan(double x) { return tanx; } -__attribute__((naked)) -double sqrt(double) { - asm("vsqrt.f64 d0, d0; bx lr"); - return 0.; -} +#else // L4 + +void init() {} + +double mod(double, double) { return 0; } + +double cos(double) { return 0; } +double sin(double) { return 0; } +double tan(double) { return 0; } +#endif } diff --git a/source/cordic.hpp b/source/cordic.hpp index 755fddb..5c52fe4 100644 --- a/source/cordic.hpp +++ b/source/cordic.hpp @@ -1,7 +1,7 @@ #ifndef CORDIC_HPP_ #define CORDIC_HPP_ -namespace math { +namespace cordic { constexpr double PI = 3.1415926535L; void init(); @@ -11,7 +11,6 @@ namespace math { double cos(double x); double sin(double x); double tan(double x); - double sqrt(double x); } #endif // CORDIC_HPP_ diff --git a/source/main.cpp b/source/main.cpp index 6e58510..0ec69b8 100644 --- a/source/main.cpp +++ b/source/main.cpp @@ -26,7 +26,7 @@ static_assert(sizeof(dacsample_t) == sizeof(uint16_t)); #include -constexpr unsigned int MAX_ELF_FILE_SIZE = 8 * 1024; +constexpr unsigned int MAX_ELF_FILE_SIZE = 16 * 1024; enum class RunStatus : char { @@ -50,13 +50,15 @@ static msg_t conversionMBBuffer[2]; static MAILBOX_DECL(conversionMB, conversionMBBuffer, 2); // Thread for LED status and wakeup hold +#if defined(TARGET_PLATFORM_H7) __attribute__((section(".stacks"))) -static THD_WORKING_AREA(monitorThreadWA, 4096); -/*extern "C"*/static THD_FUNCTION(monitorThread, arg); +static THD_WORKING_AREA(monitorThreadWA, 1024); +static THD_FUNCTION(monitorThread, arg); +#endif // Thread for managing the conversion task __attribute__((section(".stacks"))) -static THD_WORKING_AREA(conversionThreadMonitorWA, 4096); +static THD_WORKING_AREA(conversionThreadMonitorWA, 1024); static THD_FUNCTION(conversionThreadMonitor, arg); static thread_t *conversionThreadHandle = nullptr; @@ -64,8 +66,14 @@ static thread_t *conversionThreadHandle = nullptr; __attribute__((section(".stacks"))) static THD_WORKING_AREA(conversionThreadWA, 128); // All we do is enter unprivileged mode. static THD_FUNCTION(conversionThread, arg); +constexpr unsigned int conversionThreadUPWASize = +#if defined(TARGET_PLATFORM_H7) + 62 * 1024; +#else + 15 * 1024; +#endif __attribute__((section(".convdata"))) -static THD_WORKING_AREA(conversionThreadUPWA, 62 * 1024); +static THD_WORKING_AREA(conversionThreadUPWA, conversionThreadUPWASize); __attribute__((section(".convdata"))) static thread_t *conversionThreadMonitorHandle = nullptr; @@ -75,12 +83,19 @@ static THD_WORKING_AREA(communicationThreadWA, 4096); static THD_FUNCTION(communicationThread, arg); static time_measurement_t conversion_time_measurement; +#if defined(TARGET_PLATFORM_H7) __attribute__((section(".convdata"))) static SampleBuffer samplesIn (reinterpret_cast(0x38000000)); // 16k __attribute__((section(".convdata"))) static SampleBuffer samplesOut (reinterpret_cast(0x30004000)); // 16k - static SampleBuffer samplesSigGen (reinterpret_cast(0x30000000)); // 16k +#else +__attribute__((section(".convdata"))) +static SampleBuffer samplesIn (reinterpret_cast(0x20008000)); // 16k +__attribute__((section(".convdata"))) +static SampleBuffer samplesOut (reinterpret_cast(0x2000C000)); // 16k +static SampleBuffer samplesSigGen (reinterpret_cast(0x20010000)); // 16k +#endif static unsigned char elf_file_store[MAX_ELF_FILE_SIZE]; __attribute__((section(".convdata"))) @@ -108,16 +123,18 @@ int main() DAC::begin(); SClock::begin(); USBSerial::begin(); - math::init(); + cordic::init(); SClock::setRate(SClock::Rate::R32K); ADC::setRate(SClock::Rate::R32K); chTMObjectInit(&conversion_time_measurement); +#if defined(TARGET_PLATFORM_H7) chThdCreateStatic( monitorThreadWA, sizeof(monitorThreadWA), LOWPRIO, monitorThread, nullptr); +#endif conversionThreadMonitorHandle = chThdCreateStatic( conversionThreadMonitorWA, sizeof(conversionThreadMonitorWA), NORMALPRIO + 1, @@ -126,7 +143,8 @@ int main() conversionThreadWA, sizeof(conversionThreadWA), HIGHPRIO, conversionThread, - reinterpret_cast(reinterpret_cast(conversionThreadUPWA) + 62 * 1024)); + reinterpret_cast(reinterpret_cast(conversionThreadUPWA) + + conversionThreadUPWASize)); chThdCreateStatic( communicationThreadWA, sizeof(communicationThreadWA), NORMALPRIO, @@ -222,7 +240,11 @@ THD_FUNCTION(communicationThread, arg) // 'i' - Sends an identifying string to confirm that this is the stmdsp device. case 'i': - USBSerial::write(reinterpret_cast("stmdsp"), 6); +#if defined(TARGET_PLATFORM_H7) + USBSerial::write(reinterpret_cast("stmdsph"), 7); +#else + USBSerial::write(reinterpret_cast("stmdspl"), 7); +#endif break; // 'I' - Sends the current run status. @@ -370,11 +392,13 @@ THD_FUNCTION(conversionThread, stack) reinterpret_cast(stack)); } +#if defined(TARGET_PLATFORM_H7) THD_FUNCTION(monitorThread, arg) { (void)arg; - bool erroron = false; + palSetLineMode(LINE_BUTTON, PAL_MODE_INPUT_PULLUP); + while (1) { bool isidle = run_status == RunStatus::Idle; auto led = isidle ? LINE_LED_GREEN : LINE_LED_YELLOW; @@ -399,6 +423,7 @@ THD_FUNCTION(monitorThread, arg) chThdSleepMilliseconds(500); } + static bool erroron = false; if (auto err = EM.hasError(); err ^ erroron) { erroron = err; if (err) @@ -408,6 +433,7 @@ THD_FUNCTION(monitorThread, arg) } } } +#endif void conversion_unprivileged_main() { @@ -439,24 +465,45 @@ void conversion_unprivileged_main() void mpu_setup() { // Set up MPU for user algorithm - // Region 2: Data for algorithm manager thread +#if defined(TARGET_PLATFORM_H7) + // Region 2: Data for algorithm thread + // Region 3: Code for algorithm thread + // Region 4: User algorithm code mpuConfigureRegion(MPU_REGION_2, 0x20000000, MPU_RASR_ATTR_AP_RW_RW | MPU_RASR_ATTR_NON_CACHEABLE | MPU_RASR_SIZE_64K | MPU_RASR_ENABLE); - // Region 3: Code for algorithm manager thread mpuConfigureRegion(MPU_REGION_3, 0x0807F800, MPU_RASR_ATTR_AP_RO_RO | MPU_RASR_ATTR_NON_CACHEABLE | MPU_RASR_SIZE_2K | MPU_RASR_ENABLE); - // Region 4: Algorithm code mpuConfigureRegion(MPU_REGION_4, 0x00000000, MPU_RASR_ATTR_AP_RW_RW | MPU_RASR_ATTR_NON_CACHEABLE | MPU_RASR_SIZE_64K | MPU_RASR_ENABLE); +#else + // Region 2: Data for algorithm thread and ADC/DAC buffers + // Region 3: Code for algorithm thread + // Region 4: User algorithm code + mpuConfigureRegion(MPU_REGION_2, + 0x20008000, + MPU_RASR_ATTR_AP_RW_RW | MPU_RASR_ATTR_NON_CACHEABLE | + MPU_RASR_SIZE_128K| + MPU_RASR_ENABLE); + mpuConfigureRegion(MPU_REGION_3, + 0x0807F800, + MPU_RASR_ATTR_AP_RO_RO | MPU_RASR_ATTR_NON_CACHEABLE | + MPU_RASR_SIZE_2K | + MPU_RASR_ENABLE); + mpuConfigureRegion(MPU_REGION_4, + 0x10000000, + MPU_RASR_ATTR_AP_RW_RW | MPU_RASR_ATTR_NON_CACHEABLE | + MPU_RASR_SIZE_32K | + MPU_RASR_ENABLE); +#endif } void conversion_abort() @@ -523,19 +570,28 @@ void port_syscall(struct port_extctx *ctxp, uint32_t n) case 1: { using mathcall = void (*)(); - static mathcall funcs[4] = { - reinterpret_cast(math::sin), - reinterpret_cast(math::cos), - reinterpret_cast(math::tan), - reinterpret_cast(math::sqrt), + static mathcall funcs[3] = { + reinterpret_cast(cordic::sin), + reinterpret_cast(cordic::cos), + reinterpret_cast(cordic::tan), }; +#if defined(PLATFORM_H7) asm("vmov.f64 d0, %0, %1" :: "r" (ctxp->r1), "r" (ctxp->r2)); - if (ctxp->r0 < 4) { + if (ctxp->r0 < 3) { funcs[ctxp->r0](); asm("vmov.f64 %0, %1, d0" : "=r" (ctxp->r1), "=r" (ctxp->r2)); } else { asm("eor r0, r0; vmov.f64 d0, r0, r0"); } +#else + asm("vmov.f32 s0, %0" :: "r" (ctxp->r1)); + if (ctxp->r0 < 3) { + funcs[ctxp->r0](); + asm("vmov.f32 %0, s0" : "=r" (ctxp->r1)); + } else { + asm("eor r0, r0; vmov.f32 s0, r0"); + } +#endif } break; case 2: @@ -551,6 +607,9 @@ void port_syscall(struct port_extctx *ctxp, uint32_t n) conversion_time_measurement.last -= measurement_overhead; } break; + case 3: + ctxp->r0 = ADC::readAlt(0); + break; default: while (1); break; diff --git a/source/samplebuffer.hpp b/source/samplebuffer.hpp index bed52bf..6d17d2a 100644 --- a/source/samplebuffer.hpp +++ b/source/samplebuffer.hpp @@ -6,8 +6,7 @@ using Sample = uint16_t; -// Gives 8000 (8192) samples total (algorithm works with max 4096). -constexpr unsigned int MAX_SAMPLE_BUFFER_BYTESIZE = 16384; +constexpr unsigned int MAX_SAMPLE_BUFFER_BYTESIZE = sizeof(Sample) * 8192; constexpr unsigned int MAX_SAMPLE_BUFFER_SIZE = MAX_SAMPLE_BUFFER_BYTESIZE / sizeof(Sample); class SampleBuffer diff --git a/source/sclock.cpp b/source/sclock.cpp index 795274d..198c684 100644 --- a/source/sclock.cpp +++ b/source/sclock.cpp @@ -5,19 +5,27 @@ unsigned int SClock::m_div = 1; unsigned int SClock::m_runcount = 0; const GPTConfig SClock::m_timer_config = { +#if defined(TARGET_PLATFORM_H7) .frequency = 4800000, +#else + .frequency = 36000000, +#endif .callback = nullptr, .cr2 = TIM_CR2_MMS_1, /* TRGO */ .dier = 0 }; const std::array SClock::m_rate_divs = {{ +#if defined(TARGET_PLATFORM_H7) /* 8k */ 600, /* 16k */ 300, /* 20k */ 240, /* 32k */ 150, /* 48k */ 100, /* 96k */ 50 +#else + 4500, 2250, 1800, 1125, 750, 375 +#endif }}; void SClock::begin() diff --git a/source/usbcfg.c b/source/usbcfg.c index 051fcd5..b726e23 100644 --- a/source/usbcfg.c +++ b/source/usbcfg.c @@ -335,7 +335,11 @@ const USBConfig usbcfg = { * Serial over USB driver configuration. */ const SerialUSBConfig serusbcfg = { +#if defined(TARGET_PLATFORM_H7) &USBD2, +#else + &USBD1, +#endif USBD1_DATA_REQUEST_EP, USBD1_DATA_AVAILABLE_EP, USBD1_INTERRUPT_REQUEST_EP -- cgit v1.2.3 From a4f1482a8b23d5f761f60d6f3821c84190d89e2f Mon Sep 17 00:00:00 2001 From: Clyne Sullivan Date: Sun, 21 Mar 2021 16:33:08 -0400 Subject: add pot. support; L4 trig; eagle schematic draft --- Makefile | 6 +- eagle/addon.sch | 8761 +++++++++++++++++++++++++++++++++++++++++++++++++++++ gui/wxmain.cpp | 19 +- source/cordic.cpp | 17 +- source/cordic.hpp | 8 + 5 files changed, 8803 insertions(+), 8 deletions(-) create mode 100644 eagle/addon.sch (limited to 'source/cordic.cpp') diff --git a/Makefile b/Makefile index 24bda87..360811d 100644 --- a/Makefile +++ b/Makefile @@ -187,7 +187,11 @@ UINCDIR = ULIBDIR = # List all user libraries here -ULIBS = +ifeq ($(TARGET_PLATFORM),L4) + ULIBS = -lm +else + ULIBS = +endif # # End of user section diff --git a/eagle/addon.sch b/eagle/addon.sch new file mode 100644 index 0000000..813a718 --- /dev/null +++ b/eagle/addon.sch @@ -0,0 +1,8761 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Schematic Sheet Drawing Frames</b><p> +These drawing frames use the following global attributes:<p> +<table width="380" border="1" cellpadding="1" cellspacing="1" bordercolor="#000000"> + <tr> + <td width="81" bgcolor="#33CCFF"><strong>Attribute</strong></td> + <td width="289" bgcolor="#33CCFF"><strong>Description</strong></td> + </tr> + <tr> + <td>>COMPANY</td> + <td>Compay name title</td> + </tr> + <tr> + <td>>REV</td> + <td>Drawn by user name</td> + </tr> + <tr> + <td>>CHECKED</td> + <td>Checked by user name</td> + </tr> + <tr> + <td>>DATE</td> + <td>Drawing origination/release date</td> + </tr> + <tr> + <td>>DRGNO</td> + <td>Drawing number text string</td> + </tr> +</table> +<p> +<author>Robert E. Starr, Jr. (http://www.bobstarr.net)</author> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>SHEET +REV +TITLE +DRG +o +>DRAWING_NAME +N +DATE +>LAST_DATE_TIME +2019 +C +ISSUE +DRAWN +CHECKED +DATE +>COMPANY +FILE: +PAGE: +>DRAWN +>CHECKED +>DATE +>DRGNO +>REV + + + + + + + + + + + + + + + + + + + + + + + + + + +REV +DATE +APPROVED + + + + + + +PROPRIETARY +THIS DRAWING CONTAINS CONFIDENTIAL INFORMATION. ANY REPRODUCTION IN +PART OR WHOLE IS STRICTLY PROHIBITED WITHOUT WRITTEN PERMISSION! + + + + +<b>FRAME</b><p> +US ANSI-A, 8.5x11" + + + + + + + + + + + + + + + + + +<b>Simple Pin Header Connectors</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>PIN HEADER</b> - 0.1" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>PIN HEADER</b> - 2MM" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>PIN HEADER</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +.Designator + + +>Value +>Name + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +.Designator + + +>Value +>Name + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>Value + + + + +* +>Name + + + + + + + + + + + + + + + + + +>Value + + + + + + + + +>Name + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + +A +>Name +>Value +>Value + + + + + + + + + + + +B +>Name +>Value +>Value + + + + + + + + +>Name +>Value +>Value + + + + + + + + + + + + + + + + + + + + + + + + +>Name +>Value + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>Name +>Value + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>R/C MASTER! - v1.19 (10/25/2011)</b><p> +<p>This library is a collection of SMD and through hole resistors and capacitors by various manufacturers. Some of these include types from Panasonic, Kemet, BC Components and others. Many of the packages were adapted from <b>rcl.lbr</b> and <b>cap-pan40.lbr</b> and have been renamed and grouped in a more logical form.</p><p>Silkscreen elements are a minimum of 8 mils in width with larger components using 10 mil widths. Most of the SMD components have text sizes of 0 .04" and thru-hole components are 0.05" in size. A text ratio of 14 is used in both cases. Where practical, the elements are aligned on a 12.5 mil or 6.25 mil grid depending on the pad size and spacing.</p> +<p><h4>All capacitors are grouped by the following naming conventions:</h4></p> +<table width="380" border="1" bordercolor="#000000"> + <tr> + <td width="81" bgcolor="#33CCFF"><div align="center"><strong>Prefix</strong></div></td> + <td width="289" bgcolor="#33CCFF"><div align="center"><strong>Description</strong></div></td> + </tr> + <tr> + <td><div align="center">CBP_</div></td> + <td><div align="center">Bipolar Electrolytic Types</div></td> + </tr> + <tr> + <td><div align="center">CCA_</div></td> + <td><div align="center">Chip Cap Array Types</div></td> + </tr> + <tr> + <td><div align="center">CP_</div></td> + <td><div align="center">Polarized Electrolytic/Tantalum Types</div></td> + </tr> + <tr> + <td><div align="center">C_</div></td> + <td><div align="center">Non-Polarized Film / Chip Types</div></td> + </tr> + <tr> + <td><div align="center">FB_</div></td> + <td><div align="center">Simple Ferrite Bead Types</div></td> + </tr> + <tr> + <td><div align="center">L_</div></td> + <td><div align="center">Simple Chip Inductors</div></td> + </tr> + <tr> + <td><div align="center">R_</div></td> + <td><div align="center">Resistor Types</div></td> + </tr> +</table> +<p> +As a general guideline, SMD resistors are typically rated as follows:<p> +0402 = 1/16 watt<br> +0603 = 1/10 watt<br> +0805 = 1/8 watt<br> +1206 = 1/4 watt<br> +2010 = 1/2 watt<br> +2512 = 1 watt<br><p> +<author>THIS LIBRARY IS PROVIDED AS IS AND WITHOUT WARRANTY OF ANY KIND, EXPRESSED OR IMPLIED.<br>Copyright (C) 2007-2008, Bob Starr<br> +<a href="http://www.bobstarr.net">http://www.bobstarr.net</a> +</author> + + +<b>SMD RESISTOR</b><p> +0402, grid 0.00625 inch + + + + + + + + +>NAME +>VALUE + + + + + +<b>SMD RESISTOR</b><p> +0603, grid 0.00625 inch + + + + + + + + +>NAME +>VALUE + + + + + +<b>SMD RESISTOR</b><p> +0805, grid 0.0125 inch + + + + + + + + +>NAME +>VALUE + + + + + +<b>SMD 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POINT</b> - Keystone<p> +miniature test point, 40 mil hole, 0.1" diameter<p> +Keystone 5000 Series + +>NAME +>LABEL + + + + +<b>TEST POINT</b> - Keystone<p> +compact/multi-purpose test point, 63 mil hole, 0.125" diameter<p> +Keystone 5000 Series + +>NAME +>LABEL + + + + +<b>TEST POINT</b> - Keystone<p> +Universal Horizontal Test Jack<p> +Keystone 6054-6059 Series + + + + + + +>NAME +>LABEL + + + + + + + + + + + + + + + + +>NAME + + + + + +<b>TEST POINT PAD</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>R/C MASTER-SMD! - v1.14 (03/30/2013)</b><p> +<p>This library is a collection of SMD ONLY resistors and capacitors by various manufacturers. The pad sizes, spacing and silkscreen widths have been tweaked for use in dense fine pitch layouts where space, alignment and precision are critical. In general these components are designed for routing in grid increments of 5 mils</p> +<p>* Silkscreen line elements are a minimum of 8 mils in width. All components have text sizes of 0.032" or 0.04".</p> +<p>* A silkscreen text values use a ratio of 18 in all cases.</p> +<p>* ALL PADS AND PART OUTLINES ARE SNAPPED TO A 5 MIL GRID!</p> +<p>* See ULP script <b>migrate-rc-master.ulp</b> to auto-migrate parts from <b>rcl.lbr</b></h4>.</p> +<p><h4>All components are prefixed using the following conventions:</h4></p><br> +<table width="380" border="1" bordercolor="#000000"> + <tr> + <td width="81" bgcolor="#33CCFF"><div align="center"><strong>Prefix</strong></div></td> + <td width="289" bgcolor="#33CCFF"><div align="center"><strong>Description</strong></div></td> + </tr> + <tr> + <td><div align="center">CBP_</div></td> + <td><div align="center">Bipolar Electrolytic Types</div></td> + </tr> + <tr> + <td><div align="center">CCA_</div></td> + <td><div align="center">Chip Cap Array Types</div></td> + </tr> + <tr> + <td><div align="center">CP_</div></td> + <td><div align="center">Polarized Electrolytic/Tantalum Types</div></td> + </tr> + <tr> + <td><div align="center">C_</div></td> + <td><div align="center">Non-Polarized Film / Chip Types</div></td> + </tr> + <tr> + <td><div align="center">FB_</div></td> + <td><div align="center">Simple Ferrite Bead Types</div></td> + </tr> + <tr> + <td><div align="center">L_</div></td> + <td><div align="center">Simple Chip Inductors</div></td> + </tr> + <tr> + <td><div align="center">R_</div></td> + <td><div align="center">Resistor Types</div></td> + </tr> +</table> +<p> +As a general guideline, SMD resistors are typically rated as follows:<p> +0402 = 1/16 watt<br> +0603 = 1/10 watt<br> +0805 = 1/8 watt<br> +1206 = 1/4 watt<br> +2010 = 1/2 watt<br> +2512 = 1 watt<br><p> +<author>THIS LIBRARY IS PROVIDED AS IS AND WITHOUT WARRANTY OF ANY KIND, EXPRESSED OR IMPLIED.<br>Copyright (C) 2007-2008, Bob Starr<br> +<a href="http://www.bobstarr.net">http://www.bobstarr.net</a> +</author> + + +<b>CAP</b> - 0603 + + + + + + + + +>NAME +>VALUE + + + + + + + + + +<b>CAP</b> - 1812 + + + + + + + + +>NAME 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b/gui/wxmain.cpp @@ -122,6 +122,12 @@ asm("vsqrt.f64 d0, d0; bx lr"); return 0; } +auto readalt() { +adcsample_t s; +asm("svc 3; mov %0, r0" : "=&r"(s)); +return s; +} + // End stmdspgui header code )cpp"; @@ -156,7 +162,7 @@ asm("vmov.f32 r1, s0;" return 0; } __attribute__((naked)) -auto tan(double x) { +auto tan(float x) { asm("vmov.f32 r1, s0;" "mov r0, #2;" "svc 1;" @@ -170,6 +176,12 @@ asm("vsqrt.f32 s0, s0; bx lr"); return 0; } +auto readalt() { +adcsample_t s; +asm("push {r4-r6}; svc 3; mov %0, r0; pop {r4-r6}" : "=&r"(s)); +return s; +} + // End stmdspgui header code )cpp"; @@ -472,6 +484,11 @@ void MainFrame::prepareEditor() wxString MainFrame::compileEditorCode() { + if (m_device == nullptr) { + m_status_bar->SetStatusText("Need device connected to compile."); + return ""; + } + if (m_temp_file_name.IsEmpty()) m_temp_file_name = wxFileName::CreateTempFileName("stmdspgui"); diff --git a/source/cordic.cpp b/source/cordic.cpp index d2997f2..29ee068 100644 --- a/source/cordic.cpp +++ b/source/cordic.cpp @@ -1,8 +1,8 @@ #include "cordic.hpp" #include "hal.h" -namespace cordic { #if !defined(TARGET_PLATFORM_L4) +namespace cordic { void init() { @@ -93,16 +93,21 @@ double tan(double x) { return tanx; } +} #else // L4 +#include +namespace cordic { void init() {} -double mod(double, double) { return 0; } +float mod(float a, float b) { + return a - (b * std::floor(a / b)); +} -double cos(double) { return 0; } -double sin(double) { return 0; } -double tan(double) { return 0; } +float cos(float x) { return std::cos(x); } +float sin(float x) { return std::sin(x); } +float tan(float x) { return std::tan(x); } -#endif } +#endif diff --git a/source/cordic.hpp b/source/cordic.hpp index 5c52fe4..5d640cc 100644 --- a/source/cordic.hpp +++ b/source/cordic.hpp @@ -6,11 +6,19 @@ namespace cordic { void init(); +#if !defined(TARGET_PLATFORM_L4) double mod(double n, double d); double cos(double x); double sin(double x); double tan(double x); +#else + float mod(float n, float d); + + float cos(float x); + float sin(float x); + float tan(float x); +#endif } #endif // CORDIC_HPP_ -- cgit v1.2.3