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authorClyne Sullivan <clyne@bitgloo.com>2025-01-30 17:06:15 -0500
committerClyne Sullivan <clyne@bitgloo.com>2025-01-30 17:06:15 -0500
commitea84e2a1a4bdf3f46aa3789ed3f7e96c673d7c2c (patch)
tree212a3e9cdc582480e9c904444c972b2de4bbee46 /Core/Src/stm32u0xx_it.c
parent88ea3cc0ef9ac4b9f951388916dfe2c970e09a5e (diff)
idle signaling; 5mW draw
Diffstat (limited to 'Core/Src/stm32u0xx_it.c')
-rw-r--r--Core/Src/stm32u0xx_it.c13
1 files changed, 0 insertions, 13 deletions
diff --git a/Core/Src/stm32u0xx_it.c b/Core/Src/stm32u0xx_it.c
index 2539ba0..78ec492 100644
--- a/Core/Src/stm32u0xx_it.c
+++ b/Core/Src/stm32u0xx_it.c
@@ -169,19 +169,6 @@ void DMA1_Channel2_3_IRQHandler(void)
/* USER CODE END DMA1_Channel2_3_IRQn 1 */
}
-/**
- * @brief This function handles DMAMUX_OVR_IT + DMA1 channel 4 to 7 + DMA2 channel 1 to 5.
- */
-void DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler(void)
-{
- /* USER CODE BEGIN DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQn 0 */
-
- /* USER CODE END DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQn 0 */
- /* USER CODE BEGIN DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQn 1 */
-
- /* USER CODE END DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQn 1 */
-}
-
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */