initial commit

6 files changed, 483 insertions, 0 deletions

diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/CMakeLists.txt b/Drivers/CMSIS/NN/Source/ActivationFunctions/CMakeLists.txt
new file mode 100644
index 0000000..67c3f79
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/CMakeLists.txt
@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2019-2021 Arm Limited.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the License); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an AS IS BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+file(GLOB SRC "./*_s8.c")
+target_sources(cmsis-nn PRIVATE ${SRC})
diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c
new file mode 100644
index 0000000..cb8a08f
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_nn_activations_q15.c
+ * Description:  Q15 neural network activation function using direct table look-up
+ *
+ * $Date:        09. October 2020
+ * $Revision:    V.1.0.1
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nn_tables.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup Acti
+ * @{
+ */
+
+/**
+ * @brief neural network activation function using direct table look-up
+ *
+ * @note  Refer header file for details.
+ *
+ */
+
+void arm_nn_activations_direct_q15(q15_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type)
+{
+    uint16_t i = size;
+    q15_t *pIn = data;
+    q15_t *pOut = data;
+    uint16_t shift_size = 8 + 3 - int_width;
+    uint32_t bit_mask = 0x7FF >> int_width;
+    uint32_t full_frac = bit_mask + 1;
+    const q15_t *lookup_table;
+
+    switch (type)
+    {
+    case ARM_SIGMOID:
+        lookup_table = sigmoidTable_q15;
+        break;
+    case ARM_TANH:
+    default:
+        lookup_table = tanhTable_q15;
+        break;
+    }
+
+    while (i)
+    {
+        q15_t out;
+        q15_t in = *pIn++;
+        q15_t frac = (uint32_t)in & bit_mask;
+        q15_t value = lookup_table[(uint8_t)(in >> shift_size)];
+        if ((in >> shift_size) != 0x7f)
+        {
+            q15_t value2 = lookup_table[(uint8_t)(1 + ((uint8_t)(in >> shift_size)))];
+            /* doing the interpolation here for better accuracy */
+            out = ((q31_t)(full_frac - frac) * value + (q31_t)value2 * frac) >> shift_size;
+        }
+        else
+        {
+            /* the largest positive value does not have a right side for linear interpolation */
+            out = value;
+        }
+
+        *pOut++ = out;
+        i--;
+    }
+}
+
+/**
+ * @} end of Acti group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c
new file mode 100644
index 0000000..72a0b15
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_nn_activations_q7.c
+ * Description:  Q7 neural network activation function using direct table look-up
+ *
+ * $Date:        09. October 2020
+ * $Revision:    V.1.0.1
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nn_tables.h"
+#include "arm_nnfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup Acti
+ * @{
+ */
+
+/**
+ * @brief Q7 neural network activation function using direct table look-up
+ * @param[in,out]   data        pointer to input
+ * @param[in]       size        number of elements
+ * @param[in]       int_width   bit-width of the integer part, assume to be smaller than 3
+ * @param[in]       type        type of activation functions
+ *
+ * @details
+ *
+ * This is the direct table look-up approach.
+ *
+ * Assume here the integer part of the fixed-point is <= 3.
+ * More than 3 just not making much sense, makes no difference with
+ * saturation followed by any of these activation functions.
+ */
+
+void arm_nn_activations_direct_q7(q7_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type)
+{
+    uint16_t i = size;
+    q7_t *pIn = data;
+    q7_t *pOut = data;
+    q7_t in;
+    q7_t out;
+    uint16_t shift_size = 3 - int_width;
+    const q7_t *lookup_table;
+    switch (type)
+    {
+    case ARM_SIGMOID:
+        lookup_table = sigmoidTable_q7;
+        break;
+    case ARM_TANH:
+    default:
+        lookup_table = tanhTable_q7;
+        break;
+    }
+    while (i)
+    {
+        in = *pIn++;
+        out = lookup_table[(uint8_t)(in >> shift_size)];
+        *pOut++ = out;
+        i--;
+    }
+}
+
+/**
+ * @} end of Acti group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu6_s8.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu6_s8.c
new file mode 100644
index 0000000..a460b30
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu6_s8.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_relu6_s8.c
+ * Description:  Basic s8 version of ReLU6
+ *
+ * $Date:        09. October 2020
+ * $Revision:    V.1.0.1
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nnfunctions.h"
+#include "arm_nnsupportfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup Acti
+ * @{
+ */
+
+/*
+ *  Basic ReLU6 function
+ *
+ * Refer to header file for details.
+ *
+ */
+
+void arm_relu6_s8(q7_t *data, uint16_t size)
+{
+    int32_t i;
+
+    for (i = 0; i < size; i++)
+    {
+        int32_t ip = data[i];
+
+        ip = MAX(ip, 0);
+        data[i] = MIN(ip, 6);
+    }
+}
+
+/**
+ * @} end of Acti group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c
new file mode 100644
index 0000000..1d4ea4e
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_relu_q15.c
+ * Description:  Q15 version of ReLU
+ *
+ * $Date:        20. July 2021
+ * $Revision:    V.1.0.2
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nnfunctions.h"
+#include "arm_nnsupportfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup Acti
+ * @{
+ */
+
+/**
+ * @brief Q15 RELU function
+ * @param[in,out]   data        pointer to input
+ * @param[in]       size        number of elements
+ *
+ * @details
+ *
+ * Optimized relu with QSUB instructions.
+ *
+ */
+
+void arm_relu_q15(q15_t *data, uint16_t size)
+{
+
+#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI)
+    /* Run the following code for M cores with DSP extension */
+
+    uint16_t i = size >> 1;
+    q15_t *input = data;
+    q15_t *output = data;
+    q31_t in;
+    q31_t buf;
+    q31_t mask;
+
+    while (i)
+    {
+        in = arm_nn_read_q15x2_ia((const q15_t **)&input);
+
+        /* extract the first bit */
+        buf = __ROR(in & 0x80008000, 15);
+
+        /* if MSB=1, mask will be 0xFF, 0x0 otherwise */
+        mask = __QSUB16(0x00000000, buf);
+
+        arm_nn_write_q15x2_ia(&output, in & (~mask));
+        i--;
+    }
+
+    if (size & 0x1)
+    {
+        if (*input < 0)
+        {
+            *input = 0;
+        }
+        input++;
+    }
+#else
+    /* Run the following code as reference implementation for M cores without DSP extension */
+    uint16_t i;
+
+    for (i = 0; i < size; i++)
+    {
+        if (data[i] < 0)
+            data[i] = 0;
+    }
+
+#endif /* ARM_MATH_DSP */
+}
+
+/**
+ * @} end of Acti group
+ */
diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c
new file mode 100644
index 0000000..a3163cd
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_relu_q7.c
+ * Description:  Q7 version of ReLU
+ *
+ * $Date:        20. July 2021
+ * $Revision:    V.1.1.3
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nnfunctions.h"
+#include "arm_nnsupportfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup Acti
+ * @{
+ */
+
+/**
+ * @brief Q7 RELU function
+ * @param[in,out]   data        pointer to input
+ * @param[in]       size        number of elements
+ *
+ * @details
+ *
+ * Optimized relu with QSUB instructions.
+ *
+ */
+
+void arm_relu_q7(q7_t *data, uint16_t size)
+{
+
+#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI)
+    /* Run the following code for M cores with DSP extension */
+
+    uint16_t i = size >> 2;
+    q7_t *input = data;
+    q7_t *output = data;
+    q31_t in;
+    q31_t buf;
+    q31_t mask;
+
+    while (i)
+    {
+        in = arm_nn_read_q7x4_ia((const q7_t **)&input);
+
+        /* extract the first bit */
+        buf = (int32_t)__ROR((uint32_t)in & 0x80808080, 7);
+
+        /* if MSB=1, mask will be 0xFF, 0x0 otherwise */
+        mask = __QSUB8(0x00000000, buf);
+
+        arm_nn_write_q7x4_ia(&output, in & (~mask));
+
+        i--;
+    }
+
+    i = size & 0x3;
+    while (i)
+    {
+        if (*input < 0)
+        {
+            *input = 0;
+        }
+        input++;
+        i--;
+    }
+
+#else
+    /* Run the following code as reference implementation for cores without DSP extension */
+
+    uint16_t i;
+
+    for (i = 0; i < size; i++)
+    {
+        if (data[i] < 0)
+            data[i] = 0;
+    }
+
+#endif
+}
+
+/**
+ * @} end of Acti group
+ */