diff options
Diffstat (limited to 'ChibiOS_16.1.5/community/os/common')
47 files changed, 12877 insertions, 0 deletions
diff --git a/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/k20x5.h b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/k20x5.h new file mode 100644 index 0000000..c309f04 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/k20x5.h @@ -0,0 +1,305 @@ +/* + * Copyright (C) 2014-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _K20x5_H_ +#define _K20x5_H_ + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ****************/ + InitialSP_IRQn = -15, + InitialPC_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + +/****** K20x Specific Interrupt Numbers ***********************/ + DMA0_IRQn = 0, // Vector40 + DMA1_IRQn = 1, // Vector44 + DMA2_IRQn = 2, // Vector48 + DMA3_IRQn = 3, // Vector4C + DMAError_IRQn = 4, // Vector50 + DMA_IRQn = 5, // Vector54 + FlashMemComplete_IRQn = 6, // Vector58 + FlashMemReadCollision_IRQn = 7, // Vector5C + LowVoltageWarning_IRQn = 8, // Vector60 + LLWU_IRQn = 9, // Vector64 + WDOG_IRQn = 10, // Vector68 + I2C0_IRQn = 11, // Vector6C + SPI0_IRQn = 12, // Vector70 + I2S0_IRQn = 13, // Vector74 + I2S1_IRQn = 14, // Vector78 + UART0LON_IRQn = 15, // Vector7C + UART0Status_IRQn = 16, // Vector80 + UART0Error_IRQn = 17, // Vector84 + UART1Status_IRQn = 18, // Vector88 + UART1Error_IRQn = 19, // Vector8C + UART2Status_IRQn = 20, // Vector90 + UART2Error_IRQn = 21, // Vector94 + ADC0_IRQn = 22, // Vector98 + CMP0_IRQn = 23, // Vector9C + CMP1_IRQn = 24, // VectorA0 + FTM0_IRQn = 25, // VectorA4 + FTM1_IRQn = 26, // VectorA8 + CMT_IRQn = 27, // VectorAC + RTCAlarm_IRQn = 28, // VectorB0 + RTCSeconds_IRQn = 29, // VectorB4 + PITChannel0_IRQn = 30, // VectorB8 + PITChannel1_IRQn = 31, // VectorBC + PITChannel2_IRQn = 32, // VectorC0 + PITChannel3_IRQn = 33, // VectorC4 + PDB_IRQn = 34, // VectorC8 + USB_OTG_IRQn = 35, // VectorCC + USBChargerDetect_IRQn = 36, // VectorD0 + TSI_IRQn = 37, // VectorD4 + MCG_IRQn = 38, // VectorD8 + LPTMR0_IRQn = 39, // VectorDC + PINA_IRQn = 40, // VectorE0 + PINB_IRQn = 41, // VectorE4 + PINC_IRQn = 42, // VectorE8 + PIND_IRQn = 43, // VectorEC + PINE_IRQn = 44, // VectorF0 + SoftInitInt_IRQn = 45, // VectorF4 +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/** + * @brief K20x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __FPU_PRESENT 0 +#define __MPU_PRESENT 0 +#define __NVIC_PRIO_BITS 4 +#define __Vendor_SysTickConfig 0 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ + +#include "k20xx.h" + +typedef struct +{ + __IO uint32_t SOPT1; + __IO uint32_t SOPT1CFG; + uint32_t RESERVED0[1023]; + __IO uint32_t SOPT2; + uint32_t RESERVED1[1]; + __IO uint32_t SOPT4; + __IO uint32_t SOPT5; + uint32_t RESERVED2[1]; + __IO uint32_t SOPT7; + uint32_t RESERVED3[2]; + __I uint32_t SDID; + uint32_t RESERVED4[3]; + __IO uint32_t SCGC4; + __IO uint32_t SCGC5; + __IO uint32_t SCGC6; + __IO uint32_t SCGC7; + __IO uint32_t CLKDIV1; + __IO uint32_t CLKDIV2; + __I uint32_t FCFG1; + __I uint32_t FCFG2; + __I uint32_t UIDH; + __I uint32_t UIDMH; + __I uint32_t UIDML; + __I uint32_t UIDL; +} SIM_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ +#define DMA_BASE ((uint32_t)0x40008000) +#define FTFL_BASE ((uint32_t)0x40020000) +#define DMAMUX_BASE ((uint32_t)0x40021000) +#define SPI0_BASE ((uint32_t)0x4002C000) +#define PIT_BASE ((uint32_t)0x40037000) +#define FTM0_BASE ((uint32_t)0x40038000) +#define FTM1_BASE ((uint32_t)0x40039000) +#define ADC0_BASE ((uint32_t)0x4003B000) +#define VBAT_BASE ((uint32_t)0x4003E000) +#define LPTMR0_BASE ((uint32_t)0x40040000) +#define SRF_BASE ((uint32_t)0x40041000) +#define TSI0_BASE ((uint32_t)0x40045000) +#define SIM_BASE ((uint32_t)0x40047000) +#define PORTA_BASE ((uint32_t)0x40049000) +#define PORTB_BASE ((uint32_t)0x4004A000) +#define PORTC_BASE ((uint32_t)0x4004B000) +#define PORTD_BASE ((uint32_t)0x4004C000) +#define PORTE_BASE ((uint32_t)0x4004D000) +#define WDOG_BASE ((uint32_t)0x40052000) +#define MCG_BASE ((uint32_t)0x40064000) +#define OSC0_BASE ((uint32_t)0x40065000) +#define I2C0_BASE ((uint32_t)0x40066000) +#define UART0_BASE ((uint32_t)0x4006A000) +#define UART1_BASE ((uint32_t)0x4006B000) +#define UART2_BASE ((uint32_t)0x4006C000) +#define USBOTG_BASE ((uint32_t)0x40072000) +#define LLWU_BASE ((uint32_t)0x4007C000) +#define PMC_BASE ((uint32_t)0x4007D000) +#define GPIOA_BASE ((uint32_t)0x400FF000) +#define GPIOB_BASE ((uint32_t)0x400FF040) +#define GPIOC_BASE ((uint32_t)0x400FF080) +#define GPIOD_BASE ((uint32_t)0x400FF0C0) +#define GPIOE_BASE ((uint32_t)0x400FF100) + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define FTFL ((FTFL_TypeDef *) FTFL_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define PIT ((PIT_TypeDef *) PIT_BASE) +#define FTM0 ((FTM_TypeDef *) FTM0_BASE) +#define FTM1 ((FTM_TypeDef *) FTM1_BASE) +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define VBAT ((volatile uint8_t *)VBAT_BASE) /* 32 bytes */ +#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) +#define SYSTEM_REGISTER_FILE ((volatile uint8_t *)SRF_BASE) /* 32 bytes */ +#define TSI0 ((TSI_TypeDef *) TSI0_BASE) +#define SIM ((SIM_TypeDef *) SIM_BASE) +#define LLWU ((LLWU_TypeDef *) LLWU_BASE) +#define PMC ((PMC_TypeDef *) PMC_BASE) +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) +#define PORTD ((PORT_TypeDef *) PORTD_BASE) +#define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define WDOG ((WDOG_TypeDef *) WDOG_BASE) +#define USB0 ((USBOTG_TypeDef *) USBOTG_BASE) +#define MCG ((MCG_TypeDef *) MCG_BASE) +#define OSC0 ((OSC_TypeDef *) OSC0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define UART0 ((UART_TypeDef *) UART0_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ +/********* Bits definition for SIM_SOPT1 register *************/ +#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ +#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ +#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ +#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x3 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ +#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ +#define SIM_SOPT1_RAMSIZE_SHIFT 12 +#define SIM_SOPT1_RAMSIZE_MASK ((uint32_t)((uint32_t)0xf << SIM_SOPT1_RAMSIZE_SHIFT)) +#define SIM_SOPT1_RAMSIZE(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_RAMSIZE_SHIFT) & SIM_SOPT1_RAMSIZE_MASK)) + +/******* Bits definition for SIM_SOPT1CFG register ************/ +#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ +#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ +#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ + +/******* Bits definition for SIM_SOPT2 register ************/ +#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ +#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */ +#define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000) +#define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800) +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 +#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x7 << SIM_SOPT2_CLKOUTSEL_SHIFT)) +#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) +#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ + +/******* Bits definition for SIM_SCGC4 register ************/ +#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */ +#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ +#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ +#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ +#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */ +#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */ +#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ +#define SIM_SCGC4_CMT ((uint32_t)0x00000004) /*!< CMT Clock Gate Control */ +#define SIM_SCGC4_EMW ((uint32_t)0x00000002) /*!< EWM Clock Gate Control */ + +/******* Bits definition for SIM_SCGC5 register ************/ +#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ +#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ +#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ +#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ +#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ +#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */ +#define SIM_SCGC5_LPTIMER ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ +#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ +#define SIM_SCGC6_FTM1 ((uint32_t)0x02000000) /*!< FTM1 Clock Gate Control */ +#define SIM_SCGC6_FTM0 ((uint32_t)0x01000000) /*!< FTM0 Clock Gate Control */ +#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ +#define SIM_SCGC6_PDB ((uint32_t)0x00400000) /*!< PDB Clock Gate Control */ +#define SIM_SCGC6_USBDCD ((uint32_t)0x00200000) /*!< USB DCD Clock Gate Control */ +#define SIM_SCGC6_CRC ((uint32_t)0x00040000) /*!< Low Power Timer Access Control */ +#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< CRC Clock Gate Control */ +#define SIM_SCGC6_SPI0 ((uint32_t)0x00001000) /*!< SPI0 Clock Gate Control */ +#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ +#define SIM_SCGC6_FTFL ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC7_DMA ((uint32_t)0x00000002) /*!< DMA Clock Gate Control */ + +/****** Bits definition for SIM_CLKDIV1 register ***********/ +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 +#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV1_SHIFT)) +#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) +#define SIM_CLKDIV1_OUTDIV2_SHIFT 24 +#define SIM_CLKDIV1_OUTDIV2_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV2_SHIFT)) +#define SIM_CLKDIV1_OUTDIV2(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV2_SHIFT) & SIM_CLKDIV1_OUTDIV2_MASK)) +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 +#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV1_OUTDIV4_SHIFT)) +#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) + +/****** Bits definition for SIM_CLKDIV2 register ***********/ +#define SIM_CLKDIV2_USBDIV_SHIFT 1 +#define SIM_CLKDIV2_USBDIV_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV2_USBDIV_SHIFT)) +#define SIM_CLKDIV2_USBDIV(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV2_USBDIV_SHIFT) & SIM_CLKDIV2_USBDIV_MASK)) +#define SIM_CLKDIV2_USBFRAC ((uint32_t)0x00000001) + +#endif diff --git a/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/k20x7.h b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/k20x7.h new file mode 100644 index 0000000..87a4e52 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/k20x7.h @@ -0,0 +1,362 @@ +/* + * Copyright (C) 2014-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _K20x7_H_ +#define _K20x7_H_ + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ****************/ + InitialSP_IRQn = -15, + InitialPC_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + +/****** K20x Specific Interrupt Numbers ***********************/ + DMA0_IRQn = 0, // Vector40 + DMA1_IRQn = 1, // Vector44 + DMA2_IRQn = 2, // Vector48 + DMA3_IRQn = 3, // Vector4C + DMA4_IRQn = 4, // Vector50 + DMA5_IRQn = 5, // Vector54 + DMA6_IRQn = 6, // Vector58 + DMA7_IRQn = 7, // Vector5C + DMA8_IRQn = 8, // Vector60 + DMA9_IRQn = 9, // Vector64 + DMA10_IRQn = 10, // Vector68 + DMA11_IRQn = 11, // Vector6C + DMA12_IRQn = 12, // Vector70 + DMA13_IRQn = 13, // Vector74 + DMA14_IRQn = 14, // Vector78 + DMA15_IRQn = 15, // Vector7C + DMAError_IRQn = 16, // Vector80 + //~ DMA_IRQn = 17, // Vector84 + FlashMemComplete_IRQn = 18, // Vector88 + FlashMemReadCollision_IRQn = 19, // Vector8C + LowVoltageWarning_IRQn = 20, // Vector90 + LLWU_IRQn = 21, // Vector94 + WDOG_IRQn = 22, // Vector98 + I2C0_IRQn = 24, // VectorA0 + I2C1_IRQn = 25, // VectorA4 + SPI0_IRQn = 26, // VectorA8 + SPI1_IRQn = 27, // VectorAC + CANMessage_IRQn = 29, // VectorB4 + CANBusOff = 30, // VectorB8 + CANError = 31, // VectorBC + CANTxWarning = 32, // VectorC0 + CANRxWarning = 33, // VectorC4 + CANWakeUp = 34, // VectorC8 + I2S0Tx_IRQn = 35, // VectorCC + I2S1Rx_IRQn = 36, // VectorD0 + UART0LON_IRQn = 44, // VectorF0 + UART0Status_IRQn = 45, // VectorF4 + UART0Error_IRQn = 46, // VectorF8 + UART1Status_IRQn = 47, // VectorFC + UART1Error_IRQn = 48, // Vector100 + UART2Status_IRQn = 49, // Vector104 + UART2Error_IRQn = 50, // Vector108 + ADC0_IRQn = 57, // Vector124 + ADC1_IRQn = 58, // Vector128 + CMP0_IRQn = 59, // Vector12C + CMP1_IRQn = 60, // Vector130 + CMP2_IRQn = 61, // Vector134 + FTM0_IRQn = 62, // Vector138 + FTM1_IRQn = 63, // Vector13C + FTM2_IRQn = 64, // Vector140 + CMT_IRQn = 65, // Vector144 + RTCAlarm_IRQn = 66, // Vector148 + RTCSeconds_IRQn = 67, // Vector14C + PITChannel0_IRQn = 68, // Vector150 + PITChannel1_IRQn = 69, // Vector154 + PITChannel2_IRQn = 70, // Vector158 + PITChannel3_IRQn = 71, // Vector15C + PDB_IRQn = 72, // Vector160 + USB_OTG_IRQn = 73, // Vector164 + USBChargerDetect_IRQn = 74, // Vector168 + DAC0_IRQn = 81, // Vector184 + TSI_IRQn = 83, // Vector18C + MCG_IRQn = 84, // Vector190 + LPTMR0_IRQn = 85, // Vector194 + PINA_IRQn = 87, // Vector19C + PINB_IRQn = 88, // Vector1A0 + PINC_IRQn = 89, // Vector1A4 + PIND_IRQn = 90, // Vector1A8 + PINE_IRQn = 91, // Vector1AC + SoftInitInt_IRQn = 94, // Vector1B8 +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/** + * @brief K20x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __FPU_PRESENT 0 +#define __MPU_PRESENT 0 +#define __NVIC_PRIO_BITS 4 +#define __Vendor_SysTickConfig 0 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ + +#include "k20xx.h" + +typedef struct +{ + __IO uint32_t SOPT1; + __IO uint32_t SOPT1CFG; + uint32_t RESERVED0[1023]; + __IO uint32_t SOPT2; + uint32_t RESERVED1[1]; + __IO uint32_t SOPT4; + __IO uint32_t SOPT5; + uint32_t RESERVED2[1]; + __IO uint32_t SOPT7; + uint32_t RESERVED3[2]; + __I uint32_t SDID; + uint32_t RESERVED4[1]; + __IO uint32_t SCGC2; + __IO uint32_t SCGC3; + __IO uint32_t SCGC4; + __IO uint32_t SCGC5; + __IO uint32_t SCGC6; + __IO uint32_t SCGC7; + __IO uint32_t CLKDIV1; + __IO uint32_t CLKDIV2; + __I uint32_t FCFG1; + __I uint32_t FCFG2; + __I uint32_t UIDH; + __I uint32_t UIDMH; + __I uint32_t UIDML; + __I uint32_t UIDL; +} SIM_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ +#define AXBS_BASE ((uint32_t)0x40004000) // +#define DMA_BASE ((uint32_t)0x40008000) +#define FTFL_BASE ((uint32_t)0x40020000) +#define DMAMUX_BASE ((uint32_t)0x40021000) +#define FCAN0_BASE ((uint32_t)0x40024000) // +#define SPI0_BASE ((uint32_t)0x4002C000) +#define SPI1_BASE ((uint32_t)0x4002D000) // +#define I2S0_BASE ((uint32_t)0x4002F000) // +#define USBDCD_BASE ((uint32_t)0x40035000) // +#define PDB_BASE ((uint32_t)0x40036000) // +#define PIT_BASE ((uint32_t)0x40037000) +#define FTM0_BASE ((uint32_t)0x40038000) +#define FTM1_BASE ((uint32_t)0x40039000) +#define ADC0_BASE ((uint32_t)0x4003B000) +#define RTC_BASE ((uint32_t)0x4003D000) // +#define VBAT_BASE ((uint32_t)0x4003E000) +#define LPTMR0_BASE ((uint32_t)0x40040000) +#define SRF_BASE ((uint32_t)0x40041000) +#define TSI0_BASE ((uint32_t)0x40045000) +#define SIM_BASE ((uint32_t)0x40047000) +#define PORTA_BASE ((uint32_t)0x40049000) +#define PORTB_BASE ((uint32_t)0x4004A000) +#define PORTC_BASE ((uint32_t)0x4004B000) +#define PORTD_BASE ((uint32_t)0x4004C000) +#define PORTE_BASE ((uint32_t)0x4004D000) +#define WDOG_BASE ((uint32_t)0x40052000) +#define EWDOG_BASE ((uint32_t)0x40061000) // +#define CMT_BASE ((uint32_t)0x40062000) // +#define MCG_BASE ((uint32_t)0x40064000) +#define OSC0_BASE ((uint32_t)0x40065000) +#define I2C0_BASE ((uint32_t)0x40066000) +#define I2C1_BASE ((uint32_t)0x40067000) // +#define UART0_BASE ((uint32_t)0x4006A000) +#define UART1_BASE ((uint32_t)0x4006B000) +#define UART2_BASE ((uint32_t)0x4006C000) +#define USBOTG_BASE ((uint32_t)0x40072000) +#define CMP0_BASE ((uint32_t)0x40073000) // +#define VREF_BASE ((uint32_t)0x40074000) // +#define LLWU_BASE ((uint32_t)0x4007C000) +#define PMC_BASE ((uint32_t)0x4007D000) +#define SMC_BASE ((uint32_t)0x4007E000) // +#define RCM_BASE ((uint32_t)0x4007F000) // +#define FTM2_BASE ((uint32_t)0x400B8000) // +#define ADC1_BASE ((uint32_t)0x400BB000) // +#define DAC0_BASE ((uint32_t)0x400CC000) // +#define GPIOA_BASE ((uint32_t)0x400FF000) +#define GPIOB_BASE ((uint32_t)0x400FF040) +#define GPIOC_BASE ((uint32_t)0x400FF080) +#define GPIOD_BASE ((uint32_t)0x400FF0C0) +#define GPIOE_BASE ((uint32_t)0x400FF100) + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define FTFL ((FTFL_TypeDef *) FTFL_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define PIT ((PIT_TypeDef *) PIT_BASE) +#define FTM0 ((FTM_TypeDef *) FTM0_BASE) +#define FTM1 ((FTM_TypeDef *) FTM1_BASE) +#define FTM2 ((FTM_TypeDef *) FTM2_BASE) +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define VBAT ((volatile uint8_t *)VBAT_BASE) /* 32 bytes */ +#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) +#define SYSTEM_REGISTER_FILE ((volatile uint8_t *)SRF_BASE) /* 32 bytes */ +#define TSI0 ((TSI_TypeDef *) TSI0_BASE) +#define SIM ((SIM_TypeDef *) SIM_BASE) +#define LLWU ((LLWU_TypeDef *) LLWU_BASE) +#define PMC ((PMC_TypeDef *) PMC_BASE) +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) +#define PORTD ((PORT_TypeDef *) PORTD_BASE) +#define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define WDOG ((WDOG_TypeDef *) WDOG_BASE) +#define USB0 ((USBOTG_TypeDef *) USBOTG_BASE) +#define MCG ((MCG_TypeDef *) MCG_BASE) +#define OSC0 ((OSC_TypeDef *) OSC0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define UART0 ((UART_TypeDef *) UART0_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ +/********* Bits definition for SIM_SOPT1 register *************/ +#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ +#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ +#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ +#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x3 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ +#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ +#define SIM_SOPT1_RAMSIZE_SHIFT 12 +#define SIM_SOPT1_RAMSIZE_MASK ((uint32_t)((uint32_t)0xf << SIM_SOPT1_RAMSIZE_SHIFT)) +#define SIM_SOPT1_RAMSIZE(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_RAMSIZE_SHIFT) & SIM_SOPT1_RAMSIZE_MASK)) + +/******* Bits definition for SIM_SOPT1CFG register ************/ +#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ +#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ +#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ + +/******* Bits definition for SIM_SOPT2 register ************/ +#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ +#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */ +#define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000) +#define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800) +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 +#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x7 << SIM_SOPT2_CLKOUTSEL_SHIFT)) +#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) +#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ + +/******* Bits definition for SIM_SCGC2 register ************/ +#define SIM_SCGC2_DAC0 ((uint32_t)0x00001000) /*!< DAC0 Clock Gate Control */ + +/******* Bits definition for SIM_SCGC3 register ************/ +#define SIM_SCGC3_ADC1 ((uint32_t)0x08000000) /*!< ADC1 Clock Gate Control */ +#define SIM_SCGC3_FTM2 ((uint32_t)0x01000000) /*!< FTM2 Clock Gate Control */ + +/******* Bits definition for SIM_SCGC4 register ************/ +#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */ +#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ +#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ +#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ +#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */ +#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */ +#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */ +#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ +#define SIM_SCGC4_CMT ((uint32_t)0x00000004) /*!< CMT Clock Gate Control */ +#define SIM_SCGC4_EMW ((uint32_t)0x00000002) /*!< EWM Clock Gate Control */ + +/******* Bits definition for SIM_SCGC5 register ************/ +#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ +#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ +#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ +#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ +#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ +#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */ +#define SIM_SCGC5_LPTIMER ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ +#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ +#define SIM_SCGC6_FTM1 ((uint32_t)0x02000000) /*!< FTM1 Clock Gate Control */ +#define SIM_SCGC6_FTM0 ((uint32_t)0x01000000) /*!< FTM0 Clock Gate Control */ +#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ +#define SIM_SCGC6_PDB ((uint32_t)0x00400000) /*!< PDB Clock Gate Control */ +#define SIM_SCGC6_USBDCD ((uint32_t)0x00200000) /*!< USB DCD Clock Gate Control */ +#define SIM_SCGC6_CRC ((uint32_t)0x00040000) /*!< Low Power Timer Access Control */ +#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< CRC Clock Gate Control */ +#define SIM_SCGC6_SPI1 ((uint32_t)0x00002000) /*!< SPI1 Clock Gate Control */ +#define SIM_SCGC6_SPI0 ((uint32_t)0x00001000) /*!< SPI0 Clock Gate Control */ +#define SIM_SCGC6_FCAN0 ((uint32_t)0x00000010) /*!< FlexCAN 0 Clock Gate Control */ +#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ +#define SIM_SCGC6_FTFL ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC7_DMA ((uint32_t)0x00000002) /*!< DMA Clock Gate Control */ + +/****** Bits definition for SIM_CLKDIV1 register ***********/ +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 +#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV1_SHIFT)) +#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) +#define SIM_CLKDIV1_OUTDIV2_SHIFT 24 +#define SIM_CLKDIV1_OUTDIV2_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV2_SHIFT)) +#define SIM_CLKDIV1_OUTDIV2(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV2_SHIFT) & SIM_CLKDIV1_OUTDIV2_MASK)) +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 +#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV1_OUTDIV4_SHIFT)) +#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) + +/****** Bits definition for SIM_CLKDIV2 register ***********/ +#define SIM_CLKDIV2_USBDIV_SHIFT 1 +#define SIM_CLKDIV2_USBDIV_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV2_USBDIV_SHIFT)) +#define SIM_CLKDIV2_USBDIV(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV2_USBDIV_SHIFT) & SIM_CLKDIV2_USBDIV_MASK)) +#define SIM_CLKDIV2_USBFRAC ((uint32_t)0x00000001) + +#endif diff --git a/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/k20xx.h b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/k20xx.h new file mode 100644 index 0000000..38855aa --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/k20xx.h @@ -0,0 +1,2319 @@ +/* + * Copyright (C) 2014-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _K20xx_H_ +#define _K20xx_H_ + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ + +/* Device dependent */ + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/** + * @brief K20x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __MPU_PRESENT 0 +#define __NVIC_PRIO_BITS 4 +#define __Vendor_SysTickConfig 0 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ + +/* Device dependent +typedef struct +{ + __IO uint32_t SOPT1; + __IO uint32_t SOPT1CFG; + uint32_t RESERVED0[1023]; + __IO uint32_t SOPT2; + uint32_t RESERVED1[1]; + __IO uint32_t SOPT4; + __IO uint32_t SOPT5; + uint32_t RESERVED2[1]; + __IO uint32_t SOPT7; + uint32_t RESERVED3[2]; + __I uint32_t SDID; + uint32_t RESERVED4[3]; + __IO uint32_t SCGC4; + __IO uint32_t SCGC5; + __IO uint32_t SCGC6; + __IO uint32_t SCGC7; + __IO uint32_t CLKDIV1; + __IO uint32_t CLKDIV2; + __I uint32_t FCFG1; + __I uint32_t FCFG2; + __I uint32_t UIDH; + __I uint32_t UIDMH; + __I uint32_t UIDML; + __I uint32_t UIDL; +} SIM_TypeDef; +*/ + +typedef struct +{ + __IO uint8_t PE1; + __IO uint8_t PE2; + __IO uint8_t PE3; + __IO uint8_t PE4; + __IO uint8_t ME; + __IO uint8_t F1; + __IO uint8_t F2; + __I uint8_t F3; + __IO uint8_t FILT1; + __IO uint8_t FILT2; +} LLWU_TypeDef; + +typedef struct +{ + __IO uint32_t PCR[32]; + __O uint32_t GPCLR; + __O uint32_t GPCHR; + uint32_t RESERVED0[6]; + __IO uint32_t ISFR; +} PORT_TypeDef; + +typedef struct +{ + __IO uint8_t C1; + __IO uint8_t C2; + __IO uint8_t C3; + __IO uint8_t C4; + __IO uint8_t C5; + __IO uint8_t C6; + __I uint8_t S; + uint8_t RESERVED0[1]; + __IO uint8_t SC; + uint8_t RESERVED1[1]; + __IO uint8_t ATCVH; + __IO uint8_t ATCVL; + __IO uint8_t C7; + __IO uint8_t C8; +} MCG_TypeDef; + +typedef struct +{ + __IO uint8_t CR; +} OSC_TypeDef; + +typedef struct { + uint32_t SADDR; /* TCD Source Address */ + uint16_t SOFF; /* TCD Signed Source Address Offset */ + uint16_t ATTR; /* TCD Transfer Attributes */ + union { + uint32_t NBYTES_MLNO; /* TCD Minor Byte Count (Minor Loop Disabled) */ + uint32_t NBYTES_MLOFFNO; /* TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ + uint32_t NBYTES_MLOFFYES; /* TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ + }; + uint32_t SLAST; /* TCD Last Source Address Adjustment */ + uint32_t DADDR; /* TCD Destination Address */ + uint16_t DOFF; /* TCD Signed Destination Address Offset */ + union { + uint16_t CITER_ELINKNO; /* TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ + uint16_t CITER_ELINKYES; /* TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ + }; + uint32_t DLASTSGA; /* TCD Last Destination Address Adjustment/Scatter Gather Address */ + uint16_t CSR; /* TCD Control and Status */ + union { + uint16_t BITER_ELINKNO; /* TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ + uint16_t BITER_ELINKYES; /* TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ + }; +} DMA_TCD_TypeDef; + +/** DMA - Peripheral register structure */ +typedef struct { + __IO uint32_t CR; /* Control Register */ + __IO uint32_t ES; /* Error Status Register */ + __IO uint8_t RESERVED_0[4]; + __IO uint32_t ERQ; /* Enable Request Register */ + __IO uint8_t RESERVED_1[4]; + __IO uint32_t EEI; /* Enable Error Interrupt Register */ + __IO uint8_t CEEI; /* Clear Enable Error Interrupt Register */ + __IO uint8_t SEEI; /* Set Enable Error Interrupt Register */ + __IO uint8_t CERQ; /* Clear Enable Request Register */ + __IO uint8_t SERQ; /* Set Enable Request Register */ + __IO uint8_t CDNE; /* Clear DONE Status Bit Register */ + __IO uint8_t SSRT; /* Set START Bit Register */ + __IO uint8_t CERR; /* Clear Error Register */ + __IO uint8_t CINT; /* Clear Interrupt Request Register */ + __IO uint8_t RESERVED_2[4]; + __IO uint32_t INT; /* Interrupt Request Register */ + __IO uint8_t RESERVED_3[4]; + __IO uint32_t ERR; /* Error Register */ + __IO uint8_t RESERVED_4[4]; + __IO uint32_t HRS; /* Hardware Request Status Register */ + __IO uint8_t RESERVED_5[200]; + __IO uint8_t DCHPRI3; /* Channel 3 Priority Register */ + __IO uint8_t DCHPRI2; /* Channel 2 Priority Register */ + __IO uint8_t DCHPRI1; /* Channel 1 Priority Register */ + __IO uint8_t DCHPRI0; /* Channel 0 Priority Register */ + __IO uint8_t RESERVED_6[3836]; + DMA_TCD_TypeDef TCD[4]; +} DMA_TypeDef; + +typedef struct +{ + __IO uint8_t CHCFG[4]; +} DMAMUX_TypeDef; + +/** PIT - Peripheral register structure */ +typedef struct { + __IO uint32_t MCR; /* PIT Module Control Register */ + uint8_t RESERVED0[252]; + struct PIT_CHANNEL { + __IO uint32_t LDVAL; /* Timer Load Value Register */ + __IO uint32_t CVAL; /* Current Timer Value Register */ + __IO uint32_t TCTRL; /* Timer Control Register */ + __IO uint32_t TFLG; /* Timer Flag Register */ + } CHANNEL[4]; +} PIT_TypeDef; + +typedef struct +{ + __IO uint32_t SC; /* Status and Control */ + __IO uint32_t CNT; /* Counter */ + __IO uint32_t MOD; /* Modulo */ + struct FTM_Channel { + __IO uint32_t CnSC; /* Channel Status and Control */ + __IO uint32_t CnV; /* Channel Value */ + } CHANNEL[8]; + __IO uint32_t CNTIN; /* Counter Initial Value */ + __IO uint32_t STATUS; /* Capture and Compare Status */ + __IO uint32_t MODE; /* Features Mode Selection */ + __IO uint32_t SYNC; /* Synchronization */ + __IO uint32_t OUTINIT; /* Initial State for Channels Output */ + __IO uint32_t OUTMASK; /* Output Mask */ + __IO uint32_t COMBINE; /* Function for Linked Channels */ + __IO uint32_t DEADTIME; /* Deadtime Insertion Control */ + __IO uint32_t EXTTRIG; /* FTM External Trigger */ + __IO uint32_t POL; /* Channels Polarity */ + __IO uint32_t FMS; /* Fault Mode Status */ + __IO uint32_t FILTER; /* Input Capture Filter Control */ + __IO uint32_t FLTCTRL; /* Fault Control */ + __IO uint32_t QDCTRL; /* Quadrature Decode Control and Status */ + __IO uint32_t CONF; /* Configuration */ + __IO uint32_t FTLPOL; /* FTM Fault Input Polarity */ + __IO uint32_t SYNCONF; /* Synchronization Configuration */ + __IO uint32_t INVCTRL; /* FTM Inverting Control */ + __IO uint32_t SWOCTRL; /* FTM Software Output Control */ + __IO uint32_t PWMLOAD; /* FTM PWM Load */ +} FTM_TypeDef; + +typedef struct +{ + __IO uint32_t SC1A; // offset: 0x00 + __IO uint32_t SC1B; // offset: 0x04 + __IO uint32_t CFG1; // offset: 0x08 + __IO uint32_t CFG2; // offset: 0x0C + __I uint32_t RA; // offset: 0x10 + __I uint32_t RB; // offset: 0x14 + __IO uint32_t CV1; // offset: 0x18 + __IO uint32_t CV2; // offset: 0x1C + __IO uint32_t SC2; // offset: 0x20 + __IO uint32_t SC3; // offset: 0x24 + __IO uint32_t OFS; // offset: 0x28 + __IO uint32_t PG; // offset: 0x2C + __IO uint32_t MG; // offset: 0x30 + __IO uint32_t CLPD; // offset: 0x34 + __IO uint32_t CLPS; // offset: 0x38 + __IO uint32_t CLP4; // offset: 0x3C + __IO uint32_t CLP3; // offset: 0x40 + __IO uint32_t CLP2; // offset: 0x44 + __IO uint32_t CLP1; // offset: 0x48 + __IO uint32_t CLP0; // offset: 0x4C + uint32_t RESERVED0[1]; // offset: 0x50 + __IO uint32_t CLMD; // offset: 0x54 + __IO uint32_t CLMS; // offset: 0x58 + __IO uint32_t CLM4; // offset: 0x5C + __IO uint32_t CLM3; // offset: 0x60 + __IO uint32_t CLM2; // offset: 0x64 + __IO uint32_t CLM1; // offset: 0x68 + __IO uint32_t CLM0; // offset: 0x6C +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; + __IO uint32_t PSR; + __IO uint32_t CMR; + __I uint32_t CNR; +} LPTMR_TypeDef; + +typedef struct +{ + __IO uint32_t GENCS; + __IO uint32_t DATA; + __IO uint32_t TSHD; +} TSI_TypeDef; + +typedef struct +{ + __IO uint32_t PDOR; + __IO uint32_t PSOR; + __IO uint32_t PCOR; + __IO uint32_t PTOR; + __IO uint32_t PDIR; + __IO uint32_t PDDR; +} GPIO_TypeDef; + +/** SPI - Peripheral register structure */ +typedef struct { + __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */ + uint32_t RESERVED0[1]; + __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ + __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ + }; + uint32_t RESERVED1[6]; + __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */ + __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ + union { /* offset: 0x34 */ + __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */ + __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ + }; + __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */ + __I uint32_t TXFR[4]; /**< DSPI Transmit FIFO Registers, offset: 0x3C */ + uint32_t RESERVED2[12]; + __I uint32_t RXFR[4]; /**< DSPI Receive FIFO Registers, offset: 0x7C */ +} SPI_TypeDef; + +typedef struct +{ + __IO uint8_t A1; + __IO uint8_t F; + __IO uint8_t C1; + __IO uint8_t S; + __IO uint8_t D; + __IO uint8_t C2; + __IO uint8_t FLT; + __IO uint8_t RA; + __IO uint8_t SMB; + __IO uint8_t A2; + __IO uint8_t SLTH; + __IO uint8_t SLTL; +} I2C_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __I uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t MA1; + __IO uint8_t MA2; + __IO uint8_t C4; + __IO uint8_t C5; + __I uint8_t ED; + __IO uint8_t MODEM; + __IO uint8_t IR; + uint8_t RESERVED0[1]; + __IO uint8_t PFIFO; + __IO uint8_t CFIFO; + __IO uint8_t SFIFO; + __IO uint8_t TWFIFO; + __I uint8_t TCFIFO; + __IO uint8_t RWFIFO; + __I uint8_t RCFIFO; + uint8_t RESERVED1[1]; + __IO uint8_t C7816; + __IO uint8_t IE7816; + __IO uint8_t IS7816; + union { + __IO uint8_t WP7816T0; + __IO uint8_t WP7816T1; + }; + __IO uint8_t WN7816; + __IO uint8_t WF7816; + __IO uint8_t ET7816; + __IO uint8_t TL7816; + uint8_t RESERVED2[2]; + __IO uint8_t C6; + __IO uint8_t PCTH; + __IO uint8_t PCTL; + __IO uint8_t B1T; + __IO uint8_t SDTH; + __IO uint8_t SDTL; + __IO uint8_t PRE; + __IO uint8_t TPL; + __IO uint8_t IE; + __IO uint8_t WB; + __IO uint8_t S3; + __IO uint8_t S4; + __I uint8_t RPL; + __I uint8_t RPREL; + __IO uint8_t CPW; + __IO uint8_t RIDT; + __IO uint8_t TIDT; +} UART_TypeDef; + +typedef struct +{ + __IO uint8_t LVDSC1; + __IO uint8_t LVDSC2; + __IO uint8_t REGSC; +} PMC_TypeDef; + +typedef struct +{ + __IO uint16_t STCTRLH; + __IO uint16_t STCTRLL; + __IO uint16_t TOVALH; + __IO uint16_t TOVALL; + __IO uint16_t WINH; + __IO uint16_t WINL; + __IO uint16_t REFRESH; + __IO uint16_t UNLOCK; + __IO uint16_t TMROUTH; + __IO uint16_t TMROUTL; + __IO uint16_t RSTCNT; + __IO uint16_t PRESC; +} WDOG_TypeDef; + +typedef struct { + __I uint8_t PERID; // 0x00 + uint8_t RESERVED0[3]; + __I uint8_t IDCOMP; // 0x04 + uint8_t RESERVED1[3]; + __I uint8_t REV; // 0x08 + uint8_t RESERVED2[3]; + __I uint8_t ADDINFO; // 0x0C + uint8_t RESERVED3[3]; + __IO uint8_t OTGISTAT; // 0x10 + uint8_t RESERVED4[3]; + __IO uint8_t OTGICR; // 0x14 + uint8_t RESERVED5[3]; + __IO uint8_t OTGSTAT; // 0x18 + uint8_t RESERVED6[3]; + __IO uint8_t OTGCTL; // 0x1C + uint8_t RESERVED7[99]; + __IO uint8_t ISTAT; // 0x80 + uint8_t RESERVED8[3]; + __IO uint8_t INTEN; // 0x84 + uint8_t RESERVED9[3]; + __IO uint8_t ERRSTAT; // 0x88 + uint8_t RESERVED10[3]; + __IO uint8_t ERREN; // 0x8C + uint8_t RESERVED11[3]; + __I uint8_t STAT; // 0x90 + uint8_t RESERVED12[3]; + __IO uint8_t CTL; // 0x94 + uint8_t RESERVED13[3]; + __IO uint8_t ADDR; // 0x98 + uint8_t RESERVED14[3]; + __IO uint8_t BDTPAGE1; // 0x9C + uint8_t RESERVED15[3]; + __IO uint8_t FRMNUML; // 0xA0 + uint8_t RESERVED16[3]; + __IO uint8_t FRMNUMH; // 0xA4 + uint8_t RESERVED17[3]; + __IO uint8_t TOKEN; // 0xA8 + uint8_t RESERVED18[3]; + __IO uint8_t SOFTHLD; // 0xAC + uint8_t RESERVED19[3]; + __IO uint8_t BDTPAGE2; // 0xB0 + uint8_t RESERVED20[3]; + __IO uint8_t BDTPAGE3; // 0xB4 + uint8_t RESERVED21[11]; + struct { + __IO uint8_t V; // 0xC0 + uint8_t RESERVED[3]; + } ENDPT[16]; + __IO uint8_t USBCTRL; // 0x100 + uint8_t RESERVED22[3]; + __I uint8_t OBSERVE; // 0x104 + uint8_t RESERVED23[3]; + __IO uint8_t CONTROL; // 0x108 + uint8_t RESERVED24[3]; + __IO uint8_t USBTRC0; // 0x10C + uint8_t RESERVED25[7]; + __IO uint8_t USBFRMADJUST; // 0x114 +} USBOTG_TypeDef; + +typedef struct +{ + __IO uint8_t FSTAT; + __IO uint8_t FCNFG; + __I uint8_t FSEC; + __I uint8_t FOPT; + __IO uint8_t FCCOB3; + __IO uint8_t FCCOB2; + __IO uint8_t FCCOB1; + __IO uint8_t FCCOB0; + __IO uint8_t FCCOB7; + __IO uint8_t FCCOB6; + __IO uint8_t FCCOB5; + __IO uint8_t FCCOB4; + __IO uint8_t FCCOBB; + __IO uint8_t FCCOBA; + __IO uint8_t FCCOB9; + __IO uint8_t FCCOB8; + __IO uint8_t FPROT3; + __IO uint8_t FPROT2; + __IO uint8_t FPROT1; + __IO uint8_t FPROT0; + uint8_t RESERVED0[2]; + __IO uint8_t FEPROT; + __IO uint8_t FDPROT; +} FTFL_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ + + /* Device dependent */ + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ + + /* Device dependent */ + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ + + /* Device dependent */ + +/****************************************************************/ +/* */ +/* Low-Leakage Wakeup Unit (LLWU) */ +/* */ +/****************************************************************/ +/********** Bits definition for LLWU_PE1 register *************/ +#define LLWU_PE1_WUPE3_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P3 (shift) */ +#define LLWU_PE1_WUPE3_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE3_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P3 (mask) */ +#define LLWU_PE1_WUPE3(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE3_SHIFT) & LLWU_PE1_WUPE3_MASK)) /*!< Wakeup Pin Enable for LLWU_P3 */ +#define LLWU_PE1_WUPE2_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P2 (shift) */ +#define LLWU_PE1_WUPE2_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE2_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P2 (mask) */ +#define LLWU_PE1_WUPE2(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE2_SHIFT) & LLWU_PE1_WUPE2_MASK)) /*!< Wakeup Pin Enable for LLWU_P2 */ +#define LLWU_PE1_WUPE1_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P1 (shift) */ +#define LLWU_PE1_WUPE1_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE1_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P1 (mask) */ +#define LLWU_PE1_WUPE1(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE1_SHIFT) & LLWU_PE1_WUPE1_MASK)) /*!< Wakeup Pin Enable for LLWU_P1 */ +#define LLWU_PE1_WUPE0_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P0 (shift) */ +#define LLWU_PE1_WUPE0_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE0_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P0 (mask) */ +#define LLWU_PE1_WUPE0(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE0_SHIFT) & LLWU_PE1_WUPE0_MASK)) /*!< Wakeup Pin Enable for LLWU_P0 */ + +/********** Bits definition for LLWU_PE2 register *************/ +#define LLWU_PE2_WUPE7_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P7 (shift) */ +#define LLWU_PE2_WUPE7_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE7_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P7 (mask) */ +#define LLWU_PE2_WUPE7(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE7_SHIFT) & LLWU_PE2_WUPE7_MASK)) /*!< Wakeup Pin Enable for LLWU_P7 */ +#define LLWU_PE2_WUPE6_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P6 (shift) */ +#define LLWU_PE2_WUPE6_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE6_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P6 (mask) */ +#define LLWU_PE2_WUPE6(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE6_SHIFT) & LLWU_PE2_WUPE6_MASK)) /*!< Wakeup Pin Enable for LLWU_P6 */ +#define LLWU_PE2_WUPE5_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P5 (shift) */ +#define LLWU_PE2_WUPE5_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE5_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P5 (mask) */ +#define LLWU_PE2_WUPE5(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE5_SHIFT) & LLWU_PE2_WUPE5_MASK)) /*!< Wakeup Pin Enable for LLWU_P5 */ +#define LLWU_PE2_WUPE4_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P4 (shift) */ +#define LLWU_PE2_WUPE4_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE4_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P4 (mask) */ +#define LLWU_PE2_WUPE4(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE4_SHIFT) & LLWU_PE2_WUPE4_MASK)) /*!< Wakeup Pin Enable for LLWU_P4 */ + +/********** Bits definition for LLWU_PE3 register *************/ +#define LLWU_PE3_WUPE11_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P11 (shift) */ +#define LLWU_PE3_WUPE11_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE11_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P11 (mask) */ +#define LLWU_PE3_WUPE11(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE11_SHIFT) & LLWU_PE3_WUPE11_MASK)) /*!< Wakeup Pin Enable for LLWU_P11 */ +#define LLWU_PE3_WUPE10_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P10 (shift) */ +#define LLWU_PE3_WUPE10_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE10_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P10 (mask) */ +#define LLWU_PE3_WUPE10(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE10_SHIFT) & LLWU_PE3_WUPE10_MASK)) /*!< Wakeup Pin Enable for LLWU_P10 */ +#define LLWU_PE3_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P9 (shift) */ +#define LLWU_PE3_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P9 (mask) */ +#define LLWU_PE3_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE13_SHIFT) & LLWU_PE3_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P9 */ +#define LLWU_PE3_WUPE8_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P8 (shift) */ +#define LLWU_PE3_WUPE8_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE8_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P8 (mask) */ +#define LLWU_PE3_WUPE8(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE8_SHIFT) & LLWU_PE3_WUPE8_MASK)) /*!< Wakeup Pin Enable for LLWU_P8 */ + +/********** Bits definition for LLWU_PE4 register *************/ +#define LLWU_PE4_WUPE15_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P15 (shift) */ +#define LLWU_PE4_WUPE15_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE15_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P15 (mask) */ +#define LLWU_PE4_WUPE15(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE15_SHIFT) & LLWU_PE4_WUPE15_MASK)) /*!< Wakeup Pin Enable for LLWU_P15 */ +#define LLWU_PE4_WUPE14_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P14 (shift) */ +#define LLWU_PE4_WUPE14_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE14_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P14 (mask) */ +#define LLWU_PE4_WUPE14(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE14_SHIFT) & LLWU_PE4_WUPE14_MASK)) /*!< Wakeup Pin Enable for LLWU_P14 */ +#define LLWU_PE4_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P13 (shift) */ +#define LLWU_PE4_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P13 (mask) */ +#define LLWU_PE4_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE13_SHIFT) & LLWU_PE4_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P13 */ +#define LLWU_PE4_WUPE12_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P12 (shift) */ +#define LLWU_PE4_WUPE12_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE12_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P12 (mask) */ +#define LLWU_PE4_WUPE12(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE12_SHIFT) & LLWU_PE4_WUPE12_MASK)) /*!< Wakeup Pin Enable for LLWU_P12 */ + +/********** Bits definition for LLWU_ME register *************/ +#define LLWU_ME_WUME7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Module Enable for Module 7 */ +#define LLWU_ME_WUME6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Module Enable for Module 6 */ +#define LLWU_ME_WUME5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Module Enable for Module 5 */ +#define LLWU_ME_WUME4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Module Enable for Module 4 */ +#define LLWU_ME_WUME3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Module Enable for Module 3 */ +#define LLWU_ME_WUME2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Module Enable for Module 2 */ +#define LLWU_ME_WUME1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Module Enable for Module 1 */ +#define LLWU_ME_WUME0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Module Enable for Module 0 */ + +/********** Bits definition for LLWU_F1 register *************/ +#define LLWU_F1_WUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P7 */ +#define LLWU_F1_WUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P6 */ +#define LLWU_F1_WUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P5 */ +#define LLWU_F1_WUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P4 */ +#define LLWU_F1_WUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P3 */ +#define LLWU_F1_WUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P2 */ +#define LLWU_F1_WUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P1 */ +#define LLWU_F1_WUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P0 */ + +/********** Bits definition for LLWU_F2 register *************/ +#define LLWU_F2_WUF15 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P15 */ +#define LLWU_F2_WUF14 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P14 */ +#define LLWU_F2_WUF13 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P13 */ +#define LLWU_F2_WUF12 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P12 */ +#define LLWU_F2_WUF11 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P11 */ +#define LLWU_F2_WUF10 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P10 */ +#define LLWU_F2_WUF9 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P9 */ +#define LLWU_F2_WUF8 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P8 */ + +/********** Bits definition for LLWU_F3 register *************/ +#define LLWU_F3_MWUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for Module 7 */ +#define LLWU_F3_MWUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for Module 6 */ +#define LLWU_F3_MWUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for Module 5 */ +#define LLWU_F3_MWUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for Module 4 */ +#define LLWU_F3_MWUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for Module 3 */ +#define LLWU_F3_MWUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for Module 2 */ +#define LLWU_F3_MWUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for Module 1 */ +#define LLWU_F3_MWUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for Module 0 */ + +/********** Bits definition for LLWU_FILT1 register *************/ +#define LLWU_FILT1_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ +#define LLWU_FILT1_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ +#define LLWU_FILT1_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT1_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ +#define LLWU_FILT1_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTE_SHIFT) & LLWU_FILT1_FILTE_MASK)) /*!< Digital Filter on External Pin */ +#define LLWU_FILT1_FILTE_DISABLED LLWU_FILT1_FILTE(0) /*!< Filter disabled */ +#define LLWU_FILT1_FILTE_POSEDGE LLWU_FILT1_FILTE(1) /*!< Filter posedge detect enabled */ +#define LLWU_FILT1_FILTE_NEGEDGE LLWU_FILT1_FILTE(2) /*!< Filter negedge detect enabled */ +#define LLWU_FILT1_FILTE_ANYEDGE LLWU_FILT1_FILTE(3) /*!< Filter any edge detect enabled */ +#define LLWU_FILT1_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ +#define LLWU_FILT1_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT1_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ +#define LLWU_FILT1_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTSEL_SHIFT) & LLWU_FILT1_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ + +/********** Bits definition for LLWU_FILT2 register *************/ +#define LLWU_FILT2_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ +#define LLWU_FILT2_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ +#define LLWU_FILT2_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT2_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ +#define LLWU_FILT2_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTE_SHIFT) & LLWU_FILT2_FILTE_MASK)) /*!< Digital Filter on External Pin */ +#define LLWU_FILT2_FILTE_DISABLED LLWU_FILT2_FILTE(0) /*!< Filter disabled */ +#define LLWU_FILT2_FILTE_POSEDGE LLWU_FILT2_FILTE(1) /*!< Filter posedge detect enabled */ +#define LLWU_FILT2_FILTE_NEGEDGE LLWU_FILT2_FILTE(2) /*!< Filter negedge detect enabled */ +#define LLWU_FILT2_FILTE_ANYEDGE LLWU_FILT2_FILTE(3) /*!< Filter any edge detect enabled */ +#define LLWU_FILT2_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ +#define LLWU_FILT2_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT2_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ +#define LLWU_FILT2_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTSEL_SHIFT) & LLWU_FILT2_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ + +/****************************************************************/ +/* */ +/* Port Control and interrupts (PORT) */ +/* */ +/****************************************************************/ +/******** Bits definition for PORTx_PCRn register *************/ +#define PORTx_PCRn_ISF ((uint32_t)0x01000000) /*!< Interrupt Status Flag */ +#define PORTx_PCRn_IRQC_SHIFT 16 +#define PORTx_PCRn_IRQC_MASK ((uint32_t)((uint32_t)0xF << PORTx_PCRn_IRQC_SHIFT)) +#define PORTx_PCRn_IRQC(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_IRQC_SHIFT) & PORTx_PCRn_IRQC_MASK)) +#define PORTx_PCRn_LK ((uint32_t)0x00008000) /*!< Lock Register */ +#define PORTx_PCRn_MUX_SHIFT 8 /*!< Pin Mux Control (shift) */ +#define PORTx_PCRn_MUX_MASK ((uint32_t)((uint32_t)0x7 << PORTx_PCRn_MUX_SHIFT)) /*!< Pin Mux Control (mask) */ +#define PORTx_PCRn_MUX(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_MUX_SHIFT) & PORTx_PCRn_MUX_MASK)) /*!< Pin Mux Control */ +#define PORTx_PCRn_DSE ((uint32_t)0x00000040) /*!< Drive Strength Enable */ +#define PORTx_PCRn_ODE ((uint32_t)0x00000020) /*!< Open Drain Enable */ +#define PORTx_PCRn_PFE ((uint32_t)0x00000010) /*!< Passive Filter Enable */ +#define PORTx_PCRn_SRE ((uint32_t)0x00000004) /*!< Slew Rate Enable */ +#define PORTx_PCRn_PE ((uint32_t)0x00000002) /*!< Pull Enable */ +#define PORTx_PCRn_PS ((uint32_t)0x00000001) /*!< Pull Select */ + +/****************************************************************/ +/* */ +/* Oscillator (OSC) */ +/* */ +/****************************************************************/ +/*********** Bits definition for OSC_CR register **************/ +#define OSC_CR_ERCLKEN ((uint8_t)0x80) /*!< External Reference Enable */ +#define OSC_CR_EREFSTEN ((uint8_t)0x20) /*!< External Reference Stop Enable */ +#define OSC_CR_SC2P ((uint8_t)0x08) /*!< Oscillator 2pF Capacitor Load Configure */ +#define OSC_CR_SC4P ((uint8_t)0x04) /*!< Oscillator 4pF Capacitor Load Configure */ +#define OSC_CR_SC8P ((uint8_t)0x02) /*!< Oscillator 8pF Capacitor Load Configure */ +#define OSC_CR_SC16P ((uint8_t)0x01) /*!< Oscillator 16pF Capacitor Load Configure */ + +/****************************************************************/ +/* */ +/* Direct Memory Access (DMA) */ +/* */ +/****************************************************************/ +/* ---------------------------------------------------------------------------- + -- DMA - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros + * @{ + */ + + +/* DMA - Register accessors */ +#define DMA_CR_REG(base) ((base)->CR) +#define DMA_ES_REG(base) ((base)->ES) +#define DMA_ERQ_REG(base) ((base)->ERQ) +#define DMA_EEI_REG(base) ((base)->EEI) +#define DMA_CEEI_REG(base) ((base)->CEEI) +#define DMA_SEEI_REG(base) ((base)->SEEI) +#define DMA_CERQ_REG(base) ((base)->CERQ) +#define DMA_SERQ_REG(base) ((base)->SERQ) +#define DMA_CDNE_REG(base) ((base)->CDNE) +#define DMA_SSRT_REG(base) ((base)->SSRT) +#define DMA_CERR_REG(base) ((base)->CERR) +#define DMA_CINT_REG(base) ((base)->CINT) +#define DMA_INT_REG(base) ((base)->INT) +#define DMA_ERR_REG(base) ((base)->ERR) +#define DMA_HRS_REG(base) ((base)->HRS) +#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) +#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) +#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) +#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) +#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) +#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) +#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) +#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) +#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) +#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) +#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) +#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) +#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) +#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) +#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) +#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) +#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) +#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) +#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) + +/*! + * @} + */ /* end of group DMA_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define DMA_CR_EDBG_MASK 0x2u +#define DMA_CR_EDBG_SHIFT 1 +#define DMA_CR_ERCA_MASK 0x4u +#define DMA_CR_ERCA_SHIFT 2 +#define DMA_CR_HOE_MASK 0x10u +#define DMA_CR_HOE_SHIFT 4 +#define DMA_CR_HALT_MASK 0x20u +#define DMA_CR_HALT_SHIFT 5 +#define DMA_CR_CLM_MASK 0x40u +#define DMA_CR_CLM_SHIFT 6 +#define DMA_CR_EMLM_MASK 0x80u +#define DMA_CR_EMLM_SHIFT 7 +#define DMA_CR_ECX_MASK 0x10000u +#define DMA_CR_ECX_SHIFT 16 +#define DMA_CR_CX_MASK 0x20000u +#define DMA_CR_CX_SHIFT 17 +/* ES Bit Fields */ +#define DMA_ES_DBE_MASK 0x1u +#define DMA_ES_DBE_SHIFT 0 +#define DMA_ES_SBE_MASK 0x2u +#define DMA_ES_SBE_SHIFT 1 +#define DMA_ES_SGE_MASK 0x4u +#define DMA_ES_SGE_SHIFT 2 +#define DMA_ES_NCE_MASK 0x8u +#define DMA_ES_NCE_SHIFT 3 +#define DMA_ES_DOE_MASK 0x10u +#define DMA_ES_DOE_SHIFT 4 +#define DMA_ES_DAE_MASK 0x20u +#define DMA_ES_DAE_SHIFT 5 +#define DMA_ES_SOE_MASK 0x40u +#define DMA_ES_SOE_SHIFT 6 +#define DMA_ES_SAE_MASK 0x80u +#define DMA_ES_SAE_SHIFT 7 +#define DMA_ES_ERRCHN_MASK 0xF00u +#define DMA_ES_ERRCHN_SHIFT 8 +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK) +#define DMA_ES_CPE_MASK 0x4000u +#define DMA_ES_CPE_SHIFT 14 +#define DMA_ES_ECX_MASK 0x10000u +#define DMA_ES_ECX_SHIFT 16 +#define DMA_ES_VLD_MASK 0x80000000u +#define DMA_ES_VLD_SHIFT 31 +/* ERQ Bit Fields */ +#define DMA_ERQ_ERQ0_MASK 0x1u +#define DMA_ERQ_ERQ0_SHIFT 0 +#define DMA_ERQ_ERQ1_MASK 0x2u +#define DMA_ERQ_ERQ1_SHIFT 1 +#define DMA_ERQ_ERQ2_MASK 0x4u +#define DMA_ERQ_ERQ2_SHIFT 2 +#define DMA_ERQ_ERQ3_MASK 0x8u +#define DMA_ERQ_ERQ3_SHIFT 3 +/* EEI Bit Fields */ +#define DMA_EEI_EEI0_MASK 0x1u +#define DMA_EEI_EEI0_SHIFT 0 +#define DMA_EEI_EEI1_MASK 0x2u +#define DMA_EEI_EEI1_SHIFT 1 +#define DMA_EEI_EEI2_MASK 0x4u +#define DMA_EEI_EEI2_SHIFT 2 +#define DMA_EEI_EEI3_MASK 0x8u +#define DMA_EEI_EEI3_SHIFT 3 +/* CEEI Bit Fields */ +#define DMA_CEEI_CEEI_MASK 0xFu +#define DMA_CEEI_CEEI_SHIFT 0 +#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK) +#define DMA_CEEI_CAEE_MASK 0x40u +#define DMA_CEEI_CAEE_SHIFT 6 +#define DMA_CEEI_NOP_MASK 0x80u +#define DMA_CEEI_NOP_SHIFT 7 +/* SEEI Bit Fields */ +#define DMA_SEEI_SEEI_MASK 0xFu +#define DMA_SEEI_SEEI_SHIFT 0 +#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK) +#define DMA_SEEI_SAEE_MASK 0x40u +#define DMA_SEEI_SAEE_SHIFT 6 +#define DMA_SEEI_NOP_MASK 0x80u +#define DMA_SEEI_NOP_SHIFT 7 +/* CERQ Bit Fields */ +#define DMA_CERQ_CERQ_MASK 0xFu +#define DMA_CERQ_CERQ_SHIFT 0 +#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK) +#define DMA_CERQ_CAER_MASK 0x40u +#define DMA_CERQ_CAER_SHIFT 6 +#define DMA_CERQ_NOP_MASK 0x80u +#define DMA_CERQ_NOP_SHIFT 7 +/* SERQ Bit Fields */ +#define DMA_SERQ_SERQ_MASK 0xFu +#define DMA_SERQ_SERQ_SHIFT 0 +#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK) +#define DMA_SERQ_SAER_MASK 0x40u +#define DMA_SERQ_SAER_SHIFT 6 +#define DMA_SERQ_NOP_MASK 0x80u +#define DMA_SERQ_NOP_SHIFT 7 +/* CDNE Bit Fields */ +#define DMA_CDNE_CDNE_MASK 0xFu +#define DMA_CDNE_CDNE_SHIFT 0 +#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK) +#define DMA_CDNE_CADN_MASK 0x40u +#define DMA_CDNE_CADN_SHIFT 6 +#define DMA_CDNE_NOP_MASK 0x80u +#define DMA_CDNE_NOP_SHIFT 7 +/* SSRT Bit Fields */ +#define DMA_SSRT_SSRT_MASK 0xFu +#define DMA_SSRT_SSRT_SHIFT 0 +#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK) +#define DMA_SSRT_SAST_MASK 0x40u +#define DMA_SSRT_SAST_SHIFT 6 +#define DMA_SSRT_NOP_MASK 0x80u +#define DMA_SSRT_NOP_SHIFT 7 +/* CERR Bit Fields */ +#define DMA_CERR_CERR_MASK 0xFu +#define DMA_CERR_CERR_SHIFT 0 +#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK) +#define DMA_CERR_CAEI_MASK 0x40u +#define DMA_CERR_CAEI_SHIFT 6 +#define DMA_CERR_NOP_MASK 0x80u +#define DMA_CERR_NOP_SHIFT 7 +/* CINT Bit Fields */ +#define DMA_CINT_CINT_MASK 0xFu +#define DMA_CINT_CINT_SHIFT 0 +#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK) +#define DMA_CINT_CAIR_MASK 0x40u +#define DMA_CINT_CAIR_SHIFT 6 +#define DMA_CINT_NOP_MASK 0x80u +#define DMA_CINT_NOP_SHIFT 7 +/* INT Bit Fields */ +#define DMA_INT_INT0_MASK 0x1u +#define DMA_INT_INT0_SHIFT 0 +#define DMA_INT_INT1_MASK 0x2u +#define DMA_INT_INT1_SHIFT 1 +#define DMA_INT_INT2_MASK 0x4u +#define DMA_INT_INT2_SHIFT 2 +#define DMA_INT_INT3_MASK 0x8u +#define DMA_INT_INT3_SHIFT 3 +/* ERR Bit Fields */ +#define DMA_ERR_ERR0_MASK 0x1u +#define DMA_ERR_ERR0_SHIFT 0 +#define DMA_ERR_ERR1_MASK 0x2u +#define DMA_ERR_ERR1_SHIFT 1 +#define DMA_ERR_ERR2_MASK 0x4u +#define DMA_ERR_ERR2_SHIFT 2 +#define DMA_ERR_ERR3_MASK 0x8u +#define DMA_ERR_ERR3_SHIFT 3 +/* HRS Bit Fields */ +#define DMA_HRS_HRS0_MASK 0x1u +#define DMA_HRS_HRS0_SHIFT 0 +#define DMA_HRS_HRS1_MASK 0x2u +#define DMA_HRS_HRS1_SHIFT 1 +#define DMA_HRS_HRS2_MASK 0x4u +#define DMA_HRS_HRS2_SHIFT 2 +#define DMA_HRS_HRS3_MASK 0x8u +#define DMA_HRS_HRS3_SHIFT 3 +/* DCHPRI3 Bit Fields */ +#define DMA_DCHPRI3_CHPRI_MASK 0xFu +#define DMA_DCHPRI3_CHPRI_SHIFT 0 +#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK) +#define DMA_DCHPRI3_DPA_MASK 0x40u +#define DMA_DCHPRI3_DPA_SHIFT 6 +#define DMA_DCHPRI3_ECP_MASK 0x80u +#define DMA_DCHPRI3_ECP_SHIFT 7 +/* DCHPRI2 Bit Fields */ +#define DMA_DCHPRI2_CHPRI_MASK 0xFu +#define DMA_DCHPRI2_CHPRI_SHIFT 0 +#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK) +#define DMA_DCHPRI2_DPA_MASK 0x40u +#define DMA_DCHPRI2_DPA_SHIFT 6 +#define DMA_DCHPRI2_ECP_MASK 0x80u +#define DMA_DCHPRI2_ECP_SHIFT 7 +/* DCHPRI1 Bit Fields */ +#define DMA_DCHPRI1_CHPRI_MASK 0xFu +#define DMA_DCHPRI1_CHPRI_SHIFT 0 +#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK) +#define DMA_DCHPRI1_DPA_MASK 0x40u +#define DMA_DCHPRI1_DPA_SHIFT 6 +#define DMA_DCHPRI1_ECP_MASK 0x80u +#define DMA_DCHPRI1_ECP_SHIFT 7 +/* DCHPRI0 Bit Fields */ +#define DMA_DCHPRI0_CHPRI_MASK 0xFu +#define DMA_DCHPRI0_CHPRI_SHIFT 0 +#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK) +#define DMA_DCHPRI0_DPA_MASK 0x40u +#define DMA_DCHPRI0_DPA_SHIFT 6 +#define DMA_DCHPRI0_ECP_MASK 0x80u +#define DMA_DCHPRI0_ECP_SHIFT 7 +/* SADDR Bit Fields */ +#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu +#define DMA_SADDR_SADDR_SHIFT 0 +#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK) +/* SOFF Bit Fields */ +#define DMA_SOFF_SOFF_MASK 0xFFFFu +#define DMA_SOFF_SOFF_SHIFT 0 +#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK) +/* ATTR Bit Fields */ +#define DMA_ATTR_DSIZE_MASK 0x7u +#define DMA_ATTR_DSIZE_SHIFT 0 +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK) +#define DMA_ATTR_DMOD_MASK 0xF8u +#define DMA_ATTR_DMOD_SHIFT 3 +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK) +#define DMA_ATTR_SSIZE_MASK 0x700u +#define DMA_ATTR_SSIZE_SHIFT 8 +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK) +#define DMA_ATTR_SMOD_MASK 0xF800u +#define DMA_ATTR_SMOD_SHIFT 11 +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK) +/* NBYTES_MLNO Bit Fields */ +#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu +#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0 +#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK) +/* NBYTES_MLOFFNO Bit Fields */ +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu +#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0 +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK) +#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u +#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30 +#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u +#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31 +/* NBYTES_MLOFFYES Bit Fields */ +#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu +#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0 +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u +#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10 +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u +#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30 +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u +#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31 +/* SLAST Bit Fields */ +#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu +#define DMA_SLAST_SLAST_SHIFT 0 +#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK) +/* DADDR Bit Fields */ +#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu +#define DMA_DADDR_DADDR_SHIFT 0 +#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK) +/* DOFF Bit Fields */ +#define DMA_DOFF_DOFF_MASK 0xFFFFu +#define DMA_DOFF_DOFF_SHIFT 0 +#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK) +/* CITER_ELINKNO Bit Fields */ +#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu +#define DMA_CITER_ELINKNO_CITER_SHIFT 0 +#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK) +#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u +#define DMA_CITER_ELINKNO_ELINK_SHIFT 15 +/* CITER_ELINKYES Bit Fields */ +#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu +#define DMA_CITER_ELINKYES_CITER_SHIFT 0 +#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK) +#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u +#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9 +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK) +#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u +#define DMA_CITER_ELINKYES_ELINK_SHIFT 15 +/* DLAST_SGA Bit Fields */ +#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu +#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0 +#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK) +/* CSR Bit Fields */ +#define DMA_CSR_START_MASK 0x1u +#define DMA_CSR_START_SHIFT 0 +#define DMA_CSR_INTMAJOR_MASK 0x2u +#define DMA_CSR_INTMAJOR_SHIFT 1 +#define DMA_CSR_INTHALF_MASK 0x4u +#define DMA_CSR_INTHALF_SHIFT 2 +#define DMA_CSR_DREQ_MASK 0x8u +#define DMA_CSR_DREQ_SHIFT 3 +#define DMA_CSR_ESG_MASK 0x10u +#define DMA_CSR_ESG_SHIFT 4 +#define DMA_CSR_MAJORELINK_MASK 0x20u +#define DMA_CSR_MAJORELINK_SHIFT 5 +#define DMA_CSR_ACTIVE_MASK 0x40u +#define DMA_CSR_ACTIVE_SHIFT 6 +#define DMA_CSR_DONE_MASK 0x80u +#define DMA_CSR_DONE_SHIFT 7 +#define DMA_CSR_MAJORLINKCH_MASK 0xF00u +#define DMA_CSR_MAJORLINKCH_SHIFT 8 +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK) +#define DMA_CSR_BWC_MASK 0xC000u +#define DMA_CSR_BWC_SHIFT 14 +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK) +/* BITER_ELINKNO Bit Fields */ +#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu +#define DMA_BITER_ELINKNO_BITER_SHIFT 0 +#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK) +#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u +#define DMA_BITER_ELINKNO_ELINK_SHIFT 15 +/* BITER_ELINKYES Bit Fields */ +#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu +#define DMA_BITER_ELINKYES_BITER_SHIFT 0 +#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK) +#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u +#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9 +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK) +#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u +#define DMA_BITER_ELINKYES_ELINK_SHIFT 15 + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA base pointer */ +#define DMA_BASE_PTR ((DMA_MemMapPtr)0x40008000u) +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA_BASE_PTR } + +/* ---------------------------------------------------------------------------- + -- DMA - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros + * @{ + */ + + +/* DMA - Register instance definitions */ +/* DMA */ +#define DMA_CR DMA_CR_REG(DMA_BASE_PTR) +#define DMA_ES DMA_ES_REG(DMA_BASE_PTR) +#define DMA_ERQ DMA_ERQ_REG(DMA_BASE_PTR) +#define DMA_EEI DMA_EEI_REG(DMA_BASE_PTR) +#define DMA_CEEI DMA_CEEI_REG(DMA_BASE_PTR) +#define DMA_SEEI DMA_SEEI_REG(DMA_BASE_PTR) +#define DMA_CERQ DMA_CERQ_REG(DMA_BASE_PTR) +#define DMA_SERQ DMA_SERQ_REG(DMA_BASE_PTR) +#define DMA_CDNE DMA_CDNE_REG(DMA_BASE_PTR) +#define DMA_SSRT DMA_SSRT_REG(DMA_BASE_PTR) +#define DMA_CERR DMA_CERR_REG(DMA_BASE_PTR) +#define DMA_CINT DMA_CINT_REG(DMA_BASE_PTR) +#define DMA_INT DMA_INT_REG(DMA_BASE_PTR) +#define DMA_ERR DMA_ERR_REG(DMA_BASE_PTR) +#define DMA_HRS DMA_HRS_REG(DMA_BASE_PTR) +#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA_BASE_PTR) +#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA_BASE_PTR) +#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA_BASE_PTR) +#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA_BASE_PTR) +#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_CSR DMA_CSR_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,0) +#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_CSR DMA_CSR_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,1) +#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_CSR DMA_CSR_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,2) +#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_CSR DMA_CSR_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,3) + +/* DMA - Register array accessors */ +#define DMA_SADDR(index) DMA_SADDR_REG(DMA_BASE_PTR,index) +#define DMA_SOFF(index) DMA_SOFF_REG(DMA_BASE_PTR,index) +#define DMA_ATTR(index) DMA_ATTR_REG(DMA_BASE_PTR,index) +#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,index) +#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,index) +#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,index) +#define DMA_SLAST(index) DMA_SLAST_REG(DMA_BASE_PTR,index) +#define DMA_DADDR(index) DMA_DADDR_REG(DMA_BASE_PTR,index) +#define DMA_DOFF(index) DMA_DOFF_REG(DMA_BASE_PTR,index) +#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,index) +#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,index) +#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA_BASE_PTR,index) +#define DMA_CSR(index) DMA_CSR_REG(DMA_BASE_PTR,index) +#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,index) +#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,index) + +/****************************************************************/ +/* */ +/* Direct Memory Access Multiplexer (DMAMUX) */ +/* */ +/****************************************************************/ +/******** Bits definition for DMAMUX_CHCFGn register **********/ +#define DMAMUX_CHCFGn_ENBL ((uint8_t)((uint8_t)1 << 7)) /*!< DMA Channel Enable */ +#define DMAMUX_CHCFGn_TRIG ((uint8_t)((uint8_t)1 << 6)) /*!< DMA Channel Trigger Enable */ +#define DMAMUX_CHCFGn_SOURCE_SHIFT 0 /*!< DMA Channel Source (Slot) (shift) */ +#define DMAMUX_CHCFGn_SOURCE_MASK ((uint8_t)((uint8_t)0x3F << DMAMUX_CHCFGn_SOURCE_SHIFT)) /*!< DMA Channel Source (Slot) (mask) */ +#define DMAMUX_CHCFGn_SOURCE(x) ((uint8_t)(((uint8_t)(x) << DMAMUX_CHCFGn_SOURCE_SHIFT) & DMAMUX_CHCFGn_SOURCE_MASK)) /*!< DMA Channel Source (Slot) */ + +/****************************************************************/ +/* */ +/* FlexTimer Module (FTM) */ +/* */ +/****************************************************************/ + +/* SC Bit Fields */ +#define FTM_SC_PS_MASK 0x7u +#define FTM_SC_PS_SHIFT 0 +#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK) +#define FTM_SC_CLKS_MASK 0x18u +#define FTM_SC_CLKS_SHIFT 3 +#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK) +#define FTM_SC_CPWMS 0x20u +#define FTM_SC_TOIE 0x40u +#define FTM_SC_TOF 0x80u +/* CNT Bit Fields */ +#define FTM_CNT_COUNT_MASK 0xFFFFu +#define FTM_CNT_COUNT_SHIFT 0 +#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK) +/* MOD Bit Fields */ +#define FTM_MOD_MOD_MASK 0xFFFFu +#define FTM_MOD_MOD_SHIFT 0 +#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK) +/* CnSC Bit Fields */ +#define FTM_CnSC_DMA 0x1u +#define FTM_CnSC_ELSA 0x4u +#define FTM_CnSC_ELSB 0x8u +#define FTM_CnSC_MSA 0x10u +#define FTM_CnSC_MSB 0x20u +#define FTM_CnSC_CHIE 0x40u +#define FTM_CnSC_CHF 0x80u +/* CnV Bit Fields */ +#define FTM_CnV_VAL_MASK 0xFFFFu +#define FTM_CnV_VAL_SHIFT 0 +#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK) +/* CNTIN Bit Fields */ +#define FTM_CNTIN_INIT_MASK 0xFFFFu +#define FTM_CNTIN_INIT_SHIFT 0 +#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK) +/* STATUS Bit Fields */ +#define FTM_STATUS_CH0F_MASK 0x1u +#define FTM_STATUS_CH0F_SHIFT 0 +#define FTM_STATUS_CH1F_MASK 0x2u +#define FTM_STATUS_CH1F_SHIFT 1 +#define FTM_STATUS_CH2F_MASK 0x4u +#define FTM_STATUS_CH2F_SHIFT 2 +#define FTM_STATUS_CH3F_MASK 0x8u +#define FTM_STATUS_CH3F_SHIFT 3 +#define FTM_STATUS_CH4F_MASK 0x10u +#define FTM_STATUS_CH4F_SHIFT 4 +#define FTM_STATUS_CH5F_MASK 0x20u +#define FTM_STATUS_CH5F_SHIFT 5 +#define FTM_STATUS_CH6F_MASK 0x40u +#define FTM_STATUS_CH6F_SHIFT 6 +#define FTM_STATUS_CH7F_MASK 0x80u +#define FTM_STATUS_CH7F_SHIFT 7 +/* MODE Bit Fields */ +#define FTM_MODE_FTMEN_MASK 0x1u +#define FTM_MODE_FTMEN_SHIFT 0 +#define FTM_MODE_INIT_MASK 0x2u +#define FTM_MODE_INIT_SHIFT 1 +#define FTM_MODE_WPDIS_MASK 0x4u +#define FTM_MODE_WPDIS_SHIFT 2 +#define FTM_MODE_PWMSYNC_MASK 0x8u +#define FTM_MODE_PWMSYNC_SHIFT 3 +#define FTM_MODE_CAPTEST_MASK 0x10u +#define FTM_MODE_CAPTEST_SHIFT 4 +#define FTM_MODE_FAULTM_MASK 0x60u +#define FTM_MODE_FAULTM_SHIFT 5 +#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK) +#define FTM_MODE_FAULTIE_MASK 0x80u +#define FTM_MODE_FAULTIE_SHIFT 7 +/* SYNC Bit Fields */ +#define FTM_SYNC_CNTMIN_MASK 0x1u +#define FTM_SYNC_CNTMIN_SHIFT 0 +#define FTM_SYNC_CNTMAX_MASK 0x2u +#define FTM_SYNC_CNTMAX_SHIFT 1 +#define FTM_SYNC_REINIT_MASK 0x4u +#define FTM_SYNC_REINIT_SHIFT 2 +#define FTM_SYNC_SYNCHOM_MASK 0x8u +#define FTM_SYNC_SYNCHOM_SHIFT 3 +#define FTM_SYNC_TRIG0_MASK 0x10u +#define FTM_SYNC_TRIG0_SHIFT 4 +#define FTM_SYNC_TRIG1_MASK 0x20u +#define FTM_SYNC_TRIG1_SHIFT 5 +#define FTM_SYNC_TRIG2_MASK 0x40u +#define FTM_SYNC_TRIG2_SHIFT 6 +#define FTM_SYNC_SWSYNC_MASK 0x80u +#define FTM_SYNC_SWSYNC_SHIFT 7 +/* OUTINIT Bit Fields */ +#define FTM_OUTINIT_CH0OI_MASK 0x1u +#define FTM_OUTINIT_CH0OI_SHIFT 0 +#define FTM_OUTINIT_CH1OI_MASK 0x2u +#define FTM_OUTINIT_CH1OI_SHIFT 1 +#define FTM_OUTINIT_CH2OI_MASK 0x4u +#define FTM_OUTINIT_CH2OI_SHIFT 2 +#define FTM_OUTINIT_CH3OI_MASK 0x8u +#define FTM_OUTINIT_CH3OI_SHIFT 3 +#define FTM_OUTINIT_CH4OI_MASK 0x10u +#define FTM_OUTINIT_CH4OI_SHIFT 4 +#define FTM_OUTINIT_CH5OI_MASK 0x20u +#define FTM_OUTINIT_CH5OI_SHIFT 5 +#define FTM_OUTINIT_CH6OI_MASK 0x40u +#define FTM_OUTINIT_CH6OI_SHIFT 6 +#define FTM_OUTINIT_CH7OI_MASK 0x80u +#define FTM_OUTINIT_CH7OI_SHIFT 7 +/* OUTMASK Bit Fields */ +#define FTM_OUTMASK_CH0OM_MASK 0x1u +#define FTM_OUTMASK_CH0OM_SHIFT 0 +#define FTM_OUTMASK_CH1OM_MASK 0x2u +#define FTM_OUTMASK_CH1OM_SHIFT 1 +#define FTM_OUTMASK_CH2OM_MASK 0x4u +#define FTM_OUTMASK_CH2OM_SHIFT 2 +#define FTM_OUTMASK_CH3OM_MASK 0x8u +#define FTM_OUTMASK_CH3OM_SHIFT 3 +#define FTM_OUTMASK_CH4OM_MASK 0x10u +#define FTM_OUTMASK_CH4OM_SHIFT 4 +#define FTM_OUTMASK_CH5OM_MASK 0x20u +#define FTM_OUTMASK_CH5OM_SHIFT 5 +#define FTM_OUTMASK_CH6OM_MASK 0x40u +#define FTM_OUTMASK_CH6OM_SHIFT 6 +#define FTM_OUTMASK_CH7OM_MASK 0x80u +#define FTM_OUTMASK_CH7OM_SHIFT 7 +/* COMBINE Bit Fields */ +#define FTM_COMBINE_COMBINE0_MASK 0x1u +#define FTM_COMBINE_COMBINE0_SHIFT 0 +#define FTM_COMBINE_COMP0_MASK 0x2u +#define FTM_COMBINE_COMP0_SHIFT 1 +#define FTM_COMBINE_DECAPEN0_MASK 0x4u +#define FTM_COMBINE_DECAPEN0_SHIFT 2 +#define FTM_COMBINE_DECAP0_MASK 0x8u +#define FTM_COMBINE_DECAP0_SHIFT 3 +#define FTM_COMBINE_DTEN0_MASK 0x10u +#define FTM_COMBINE_DTEN0_SHIFT 4 +#define FTM_COMBINE_SYNCEN0_MASK 0x20u +#define FTM_COMBINE_SYNCEN0_SHIFT 5 +#define FTM_COMBINE_FAULTEN0_MASK 0x40u +#define FTM_COMBINE_FAULTEN0_SHIFT 6 +#define FTM_COMBINE_COMBINE1_MASK 0x100u +#define FTM_COMBINE_COMBINE1_SHIFT 8 +#define FTM_COMBINE_COMP1_MASK 0x200u +#define FTM_COMBINE_COMP1_SHIFT 9 +#define FTM_COMBINE_DECAPEN1_MASK 0x400u +#define FTM_COMBINE_DECAPEN1_SHIFT 10 +#define FTM_COMBINE_DECAP1_MASK 0x800u +#define FTM_COMBINE_DECAP1_SHIFT 11 +#define FTM_COMBINE_DTEN1_MASK 0x1000u +#define FTM_COMBINE_DTEN1_SHIFT 12 +#define FTM_COMBINE_SYNCEN1_MASK 0x2000u +#define FTM_COMBINE_SYNCEN1_SHIFT 13 +#define FTM_COMBINE_FAULTEN1_MASK 0x4000u +#define FTM_COMBINE_FAULTEN1_SHIFT 14 +#define FTM_COMBINE_COMBINE2_MASK 0x10000u +#define FTM_COMBINE_COMBINE2_SHIFT 16 +#define FTM_COMBINE_COMP2_MASK 0x20000u +#define FTM_COMBINE_COMP2_SHIFT 17 +#define FTM_COMBINE_DECAPEN2_MASK 0x40000u +#define FTM_COMBINE_DECAPEN2_SHIFT 18 +#define FTM_COMBINE_DECAP2_MASK 0x80000u +#define FTM_COMBINE_DECAP2_SHIFT 19 +#define FTM_COMBINE_DTEN2_MASK 0x100000u +#define FTM_COMBINE_DTEN2_SHIFT 20 +#define FTM_COMBINE_SYNCEN2_MASK 0x200000u +#define FTM_COMBINE_SYNCEN2_SHIFT 21 +#define FTM_COMBINE_FAULTEN2_MASK 0x400000u +#define FTM_COMBINE_FAULTEN2_SHIFT 22 +#define FTM_COMBINE_COMBINE3_MASK 0x1000000u +#define FTM_COMBINE_COMBINE3_SHIFT 24 +#define FTM_COMBINE_COMP3_MASK 0x2000000u +#define FTM_COMBINE_COMP3_SHIFT 25 +#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u +#define FTM_COMBINE_DECAPEN3_SHIFT 26 +#define FTM_COMBINE_DECAP3_MASK 0x8000000u +#define FTM_COMBINE_DECAP3_SHIFT 27 +#define FTM_COMBINE_DTEN3_MASK 0x10000000u +#define FTM_COMBINE_DTEN3_SHIFT 28 +#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u +#define FTM_COMBINE_SYNCEN3_SHIFT 29 +#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u +#define FTM_COMBINE_FAULTEN3_SHIFT 30 +/* DEADTIME Bit Fields */ +#define FTM_DEADTIME_DTVAL_MASK 0x3Fu +#define FTM_DEADTIME_DTVAL_SHIFT 0 +#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK) +#define FTM_DEADTIME_DTPS_MASK 0xC0u +#define FTM_DEADTIME_DTPS_SHIFT 6 +#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK) +/* EXTTRIG Bit Fields */ +#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u +#define FTM_EXTTRIG_CH2TRIG_SHIFT 0 +#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u +#define FTM_EXTTRIG_CH3TRIG_SHIFT 1 +#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u +#define FTM_EXTTRIG_CH4TRIG_SHIFT 2 +#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u +#define FTM_EXTTRIG_CH5TRIG_SHIFT 3 +#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u +#define FTM_EXTTRIG_CH0TRIG_SHIFT 4 +#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u +#define FTM_EXTTRIG_CH1TRIG_SHIFT 5 +#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u +#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6 +#define FTM_EXTTRIG_TRIGF_MASK 0x80u +#define FTM_EXTTRIG_TRIGF_SHIFT 7 +/* POL Bit Fields */ +#define FTM_POL_POL0_MASK 0x1u +#define FTM_POL_POL0_SHIFT 0 +#define FTM_POL_POL1_MASK 0x2u +#define FTM_POL_POL1_SHIFT 1 +#define FTM_POL_POL2_MASK 0x4u +#define FTM_POL_POL2_SHIFT 2 +#define FTM_POL_POL3_MASK 0x8u +#define FTM_POL_POL3_SHIFT 3 +#define FTM_POL_POL4_MASK 0x10u +#define FTM_POL_POL4_SHIFT 4 +#define FTM_POL_POL5_MASK 0x20u +#define FTM_POL_POL5_SHIFT 5 +#define FTM_POL_POL6_MASK 0x40u +#define FTM_POL_POL6_SHIFT 6 +#define FTM_POL_POL7_MASK 0x80u +#define FTM_POL_POL7_SHIFT 7 +/* FMS Bit Fields */ +#define FTM_FMS_FAULTF0_MASK 0x1u +#define FTM_FMS_FAULTF0_SHIFT 0 +#define FTM_FMS_FAULTF1_MASK 0x2u +#define FTM_FMS_FAULTF1_SHIFT 1 +#define FTM_FMS_FAULTF2_MASK 0x4u +#define FTM_FMS_FAULTF2_SHIFT 2 +#define FTM_FMS_FAULTF3_MASK 0x8u +#define FTM_FMS_FAULTF3_SHIFT 3 +#define FTM_FMS_FAULTIN_MASK 0x20u +#define FTM_FMS_FAULTIN_SHIFT 5 +#define FTM_FMS_WPEN_MASK 0x40u +#define FTM_FMS_WPEN_SHIFT 6 +#define FTM_FMS_FAULTF_MASK 0x80u +#define FTM_FMS_FAULTF_SHIFT 7 +/* FILTER Bit Fields */ +#define FTM_FILTER_CH0FVAL_MASK 0xFu +#define FTM_FILTER_CH0FVAL_SHIFT 0 +#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK) +#define FTM_FILTER_CH1FVAL_MASK 0xF0u +#define FTM_FILTER_CH1FVAL_SHIFT 4 +#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK) +#define FTM_FILTER_CH2FVAL_MASK 0xF00u +#define FTM_FILTER_CH2FVAL_SHIFT 8 +#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK) +#define FTM_FILTER_CH3FVAL_MASK 0xF000u +#define FTM_FILTER_CH3FVAL_SHIFT 12 +#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK) +/* FLTCTRL Bit Fields */ +#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u +#define FTM_FLTCTRL_FAULT0EN_SHIFT 0 +#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u +#define FTM_FLTCTRL_FAULT1EN_SHIFT 1 +#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u +#define FTM_FLTCTRL_FAULT2EN_SHIFT 2 +#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u +#define FTM_FLTCTRL_FAULT3EN_SHIFT 3 +#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u +#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4 +#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u +#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5 +#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u +#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6 +#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u +#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7 +#define FTM_FLTCTRL_FFVAL_MASK 0xF00u +#define FTM_FLTCTRL_FFVAL_SHIFT 8 +#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK) +/* QDCTRL Bit Fields */ +#define FTM_QDCTRL_QUADEN_MASK 0x1u +#define FTM_QDCTRL_QUADEN_SHIFT 0 +#define FTM_QDCTRL_TOFDIR_MASK 0x2u +#define FTM_QDCTRL_TOFDIR_SHIFT 1 +#define FTM_QDCTRL_QUADIR_MASK 0x4u +#define FTM_QDCTRL_QUADIR_SHIFT 2 +#define FTM_QDCTRL_QUADMODE_MASK 0x8u +#define FTM_QDCTRL_QUADMODE_SHIFT 3 +#define FTM_QDCTRL_PHBPOL_MASK 0x10u +#define FTM_QDCTRL_PHBPOL_SHIFT 4 +#define FTM_QDCTRL_PHAPOL_MASK 0x20u +#define FTM_QDCTRL_PHAPOL_SHIFT 5 +#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u +#define FTM_QDCTRL_PHBFLTREN_SHIFT 6 +#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u +#define FTM_QDCTRL_PHAFLTREN_SHIFT 7 +/* CONF Bit Fields */ +#define FTM_CONF_NUMTOF_MASK 0x1Fu +#define FTM_CONF_NUMTOF_SHIFT 0 +#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK) +#define FTM_CONF_BDMMODE_MASK 0xC0u +#define FTM_CONF_BDMMODE_SHIFT 6 +#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK) +#define FTM_CONF_GTBEEN_MASK 0x200u +#define FTM_CONF_GTBEEN_SHIFT 9 +#define FTM_CONF_GTBEOUT_MASK 0x400u +#define FTM_CONF_GTBEOUT_SHIFT 10 +/* FLTPOL Bit Fields */ +#define FTM_FLTPOL_FLT0POL_MASK 0x1u +#define FTM_FLTPOL_FLT0POL_SHIFT 0 +#define FTM_FLTPOL_FLT1POL_MASK 0x2u +#define FTM_FLTPOL_FLT1POL_SHIFT 1 +#define FTM_FLTPOL_FLT2POL_MASK 0x4u +#define FTM_FLTPOL_FLT2POL_SHIFT 2 +#define FTM_FLTPOL_FLT3POL_MASK 0x8u +#define FTM_FLTPOL_FLT3POL_SHIFT 3 +/* SYNCONF Bit Fields */ +#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u +#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0 +#define FTM_SYNCONF_CNTINC_MASK 0x4u +#define FTM_SYNCONF_CNTINC_SHIFT 2 +#define FTM_SYNCONF_INVC_MASK 0x10u +#define FTM_SYNCONF_INVC_SHIFT 4 +#define FTM_SYNCONF_SWOC_MASK 0x20u +#define FTM_SYNCONF_SWOC_SHIFT 5 +#define FTM_SYNCONF_SYNCMODE_MASK 0x80u +#define FTM_SYNCONF_SYNCMODE_SHIFT 7 +#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u +#define FTM_SYNCONF_SWRSTCNT_SHIFT 8 +#define FTM_SYNCONF_SWWRBUF_MASK 0x200u +#define FTM_SYNCONF_SWWRBUF_SHIFT 9 +#define FTM_SYNCONF_SWOM_MASK 0x400u +#define FTM_SYNCONF_SWOM_SHIFT 10 +#define FTM_SYNCONF_SWINVC_MASK 0x800u +#define FTM_SYNCONF_SWINVC_SHIFT 11 +#define FTM_SYNCONF_SWSOC_MASK 0x1000u +#define FTM_SYNCONF_SWSOC_SHIFT 12 +#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u +#define FTM_SYNCONF_HWRSTCNT_SHIFT 16 +#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u +#define FTM_SYNCONF_HWWRBUF_SHIFT 17 +#define FTM_SYNCONF_HWOM_MASK 0x40000u +#define FTM_SYNCONF_HWOM_SHIFT 18 +#define FTM_SYNCONF_HWINVC_MASK 0x80000u +#define FTM_SYNCONF_HWINVC_SHIFT 19 +#define FTM_SYNCONF_HWSOC_MASK 0x100000u +#define FTM_SYNCONF_HWSOC_SHIFT 20 +/* INVCTRL Bit Fields */ +#define FTM_INVCTRL_INV0EN_MASK 0x1u +#define FTM_INVCTRL_INV0EN_SHIFT 0 +#define FTM_INVCTRL_INV1EN_MASK 0x2u +#define FTM_INVCTRL_INV1EN_SHIFT 1 +#define FTM_INVCTRL_INV2EN_MASK 0x4u +#define FTM_INVCTRL_INV2EN_SHIFT 2 +#define FTM_INVCTRL_INV3EN_MASK 0x8u +#define FTM_INVCTRL_INV3EN_SHIFT 3 +/* SWOCTRL Bit Fields */ +#define FTM_SWOCTRL_CH0OC_MASK 0x1u +#define FTM_SWOCTRL_CH0OC_SHIFT 0 +#define FTM_SWOCTRL_CH1OC_MASK 0x2u +#define FTM_SWOCTRL_CH1OC_SHIFT 1 +#define FTM_SWOCTRL_CH2OC_MASK 0x4u +#define FTM_SWOCTRL_CH2OC_SHIFT 2 +#define FTM_SWOCTRL_CH3OC_MASK 0x8u +#define FTM_SWOCTRL_CH3OC_SHIFT 3 +#define FTM_SWOCTRL_CH4OC_MASK 0x10u +#define FTM_SWOCTRL_CH4OC_SHIFT 4 +#define FTM_SWOCTRL_CH5OC_MASK 0x20u +#define FTM_SWOCTRL_CH5OC_SHIFT 5 +#define FTM_SWOCTRL_CH6OC_MASK 0x40u +#define FTM_SWOCTRL_CH6OC_SHIFT 6 +#define FTM_SWOCTRL_CH7OC_MASK 0x80u +#define FTM_SWOCTRL_CH7OC_SHIFT 7 +#define FTM_SWOCTRL_CH0OCV_MASK 0x100u +#define FTM_SWOCTRL_CH0OCV_SHIFT 8 +#define FTM_SWOCTRL_CH1OCV_MASK 0x200u +#define FTM_SWOCTRL_CH1OCV_SHIFT 9 +#define FTM_SWOCTRL_CH2OCV_MASK 0x400u +#define FTM_SWOCTRL_CH2OCV_SHIFT 10 +#define FTM_SWOCTRL_CH3OCV_MASK 0x800u +#define FTM_SWOCTRL_CH3OCV_SHIFT 11 +#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u +#define FTM_SWOCTRL_CH4OCV_SHIFT 12 +#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u +#define FTM_SWOCTRL_CH5OCV_SHIFT 13 +#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u +#define FTM_SWOCTRL_CH6OCV_SHIFT 14 +#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u +#define FTM_SWOCTRL_CH7OCV_SHIFT 15 +/* PWMLOAD Bit Fields */ +#define FTM_PWMLOAD_CH0SEL_MASK 0x1u +#define FTM_PWMLOAD_CH0SEL_SHIFT 0 +#define FTM_PWMLOAD_CH1SEL_MASK 0x2u +#define FTM_PWMLOAD_CH1SEL_SHIFT 1 +#define FTM_PWMLOAD_CH2SEL_MASK 0x4u +#define FTM_PWMLOAD_CH2SEL_SHIFT 2 +#define FTM_PWMLOAD_CH3SEL_MASK 0x8u +#define FTM_PWMLOAD_CH3SEL_SHIFT 3 +#define FTM_PWMLOAD_CH4SEL_MASK 0x10u +#define FTM_PWMLOAD_CH4SEL_SHIFT 4 +#define FTM_PWMLOAD_CH5SEL_MASK 0x20u +#define FTM_PWMLOAD_CH5SEL_SHIFT 5 +#define FTM_PWMLOAD_CH6SEL_MASK 0x40u +#define FTM_PWMLOAD_CH6SEL_SHIFT 6 +#define FTM_PWMLOAD_CH7SEL_MASK 0x80u +#define FTM_PWMLOAD_CH7SEL_SHIFT 7 +#define FTM_PWMLOAD_LDOK_MASK 0x200u +#define FTM_PWMLOAD_LDOK_SHIFT 9 + +/****************************************************************/ +/* */ +/* Periodic Interrupt Timer (PIT) */ +/* */ +/****************************************************************/ +/* MCR Bit Fields */ +#define PIT_MCR_FRZ 0x1u +#define PIT_MCR_MDIS 0x2u +/* LDVALn Bit Fields */ +#define PIT_LDVALn_TSV_MASK 0xFFFFFFFFu +#define PIT_LDVALn_TSV_SHIFT 0 +#define PIT_LDVALn_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK) +/* CVALn Bit Fields */ +#define PIT_CVALn_TVL_MASK 0xFFFFFFFFu +#define PIT_CVALn_TVL_SHIFT 0 +#define PIT_CVALn_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK) +/* TCTRLn Bit Fields */ +#define PIT_TCTRLn_TEN 0x1u +#define PIT_TCTRLn_TIE 0x2u +/* TFLGn Bit Fields */ +#define PIT_TFLGn_TIF 0x1u + +/****************************************************************/ +/* */ +/* Analog-to-Digital Converter (ADC) */ +/* */ +/****************************************************************/ +/*********** Bits definition for ADCx_SC1n register ***********/ +#define ADCx_SC1n_COCO ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Complete Flag */ +#define ADCx_SC1n_AIEN ((uint32_t)((uint32_t)1 << 6)) /*!< Interrupt Enable */ +#define ADCx_SC1n_DIFF ((uint32_t)((uint32_t)1 << 5)) /*!< Differential Mode Enable */ +#define ADCx_SC1n_ADCH_SHIFT 0 /*!< Input channel select (shift) */ +#define ADCx_SC1n_ADCH_MASK ((uint32_t)((uint32_t)0x1F << ADCx_SC1n_ADCH_SHIFT)) /*!< Input channel select (mask) */ +#define ADCx_SC1n_ADCH(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC1n_ADCH_SHIFT) & ADCx_SC1n_ADCH_MASK)) /*!< Input channel select */ + +/*********** Bits definition for ADCx_CFG1 register ***********/ +#define ADCx_CFG1_ADLPC ((uint32_t)((uint32_t)1 << 7)) /*!< Low-Power Configuration */ +#define ADCx_CFG1_ADIV_SHIFT 5 /*!< Clock Divide Select (shift) */ +#define ADCx_CFG1_ADIV_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADIV_SHIFT)) /*!< Clock Divide Select (mask) */ +#define ADCx_CFG1_ADIV(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADIV_SHIFT) & ADCx_CFG1_ADIV_MASK)) /*!< Clock Divide Select */ +#define ADCx_CFG1_ADLSMP ((uint32_t)((uint32_t)1 << 4)) /*!< Sample time configuration */ +#define ADCx_CFG1_MODE_SHIFT 2 /*!< Conversion mode (resolution) selection (shift) */ +#define ADCx_CFG1_MODE_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_MODE_SHIFT)) /*!< Conversion mode (resolution) selection (mask) */ +#define ADCx_CFG1_MODE(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_MODE_SHIFT) & ADCx_CFG1_MODE_MASK)) /*!< Conversion mode (resolution) selection */ +#define ADCx_CFG1_ADICLK_SHIFT 0 /*!< Input Clock Select (shift) */ +#define ADCx_CFG1_ADICLK_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADICLK_SHIFT)) /*!< Input Clock Select (mask) */ +#define ADCx_CFG1_ADICLK(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADICLK_SHIFT) & ADCx_CFG1_ADICLK_MASK)) /*!< Input Clock Select */ + +/*********** Bits definition for ADCx_CFG2 register ***********/ +#define ADCx_CFG2_MUXSEL ((uint32_t)((uint32_t)1 << 4)) /*!< ADC Mux Select */ +#define ADCx_CFG2_ADACKEN ((uint32_t)((uint32_t)1 << 3)) /*!< Asynchronous Clock Output Enable */ +#define ADCx_CFG2_ADHSC ((uint32_t)((uint32_t)1 << 2)) /*!< High-Speed Configuration */ +#define ADCx_CFG2_ADLSTS_SHIFT 0 /*!< Long Sample Time Select (shift) */ +#define ADCx_CFG2_ADLSTS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG2_ADLSTS_SHIFT)) /*!< Long Sample Time Select (mask) */ +#define ADCx_CFG2_ADLSTS(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG2_ADLSTS_SHIFT) & ADCx_CFG2_ADLSTS_MASK)) /*!< Long Sample Time Select */ + +/*********** Bits definition for ADCx_SC2 register ***********/ +#define ADCx_SC2_ADACT ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Active */ +#define ADCx_SC2_ADTRG ((uint32_t)((uint32_t)1 << 6)) /*!< Conversion Trigger Select */ +#define ADCx_SC2_ACFE ((uint32_t)((uint32_t)1 << 5)) /*!< Compare Function Enable */ +#define ADCx_SC2_ACFGT ((uint32_t)((uint32_t)1 << 4)) /*!< Compare Function Greater Than Enable */ +#define ADCx_SC2_ACREN ((uint32_t)((uint32_t)1 << 3)) /*!< Compare Function Range Enable */ +#define ADCx_SC2_DMAEN ((uint32_t)((uint32_t)1 << 2)) /*!< DMA Enable */ +#define ADCx_SC2_REFSEL_SHIFT 0 /*!< Voltage Reference Selection (shift) */ +#define ADCx_SC2_REFSEL_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC2_REFSEL_SHIFT)) /*!< Voltage Reference Selection (mask) */ +#define ADCx_SC2_REFSEL(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC2_REFSEL_SHIFT) & ADCx_SC2_REFSEL_MASK)) /*!< Voltage Reference Selection */ + +/*********** Bits definition for ADCx_SC3 register ***********/ +#define ADCx_SC3_CAL ((uint32_t)((uint32_t)1 << 7)) /*!< Calibration */ +#define ADCx_SC3_CALF ((uint32_t)((uint32_t)1 << 6)) /*!< Calibration Failed Flag */ +#define ADCx_SC3_ADCO ((uint32_t)((uint32_t)1 << 3)) /*!< Continuous Conversion Enable */ +#define ADCx_SC3_AVGE ((uint32_t)((uint32_t)1 << 2)) /*!< Hardware Average Enable */ +#define ADCx_SC3_AVGS_SHIFT 0 /*!< Hardware Average Select (shift) */ +#define ADCx_SC3_AVGS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC3_AVGS_SHIFT)) /*!< Hardware Average Select (mask) */ +#define ADCx_SC3_AVGS(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC3_AVGS_SHIFT) & ADCx_SC3_AVGS_MASK)) /*!< Hardware Average Select */ + +/****************************************************************/ +/* */ +/* Low-Power Timer (LPTMR) */ +/* */ +/****************************************************************/ +/********** Bits definition for LPTMRx_CSR register ***********/ +#define LPTMRx_CSR_TCF ((uint32_t)((uint32_t)1 << 7)) /*!< Timer Compare Flag */ +#define LPTMRx_CSR_TIE ((uint32_t)((uint32_t)1 << 6)) /*!< Timer Interrupt Enable */ +#define LPTMRx_CSR_TPS_SHIFT 4 /*!< Timer Pin Select (shift) */ +#define LPTMRx_CSR_TPS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_CSR_TPS_SHIFT)) /*!< Timer Pin Select (mask) */ +#define LPTMRx_CSR_TPS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CSR_TPS_SHIFT) & LPTMRx_CSR_TPS_MASK)) /*!< Timer Pin Select */ +#define LPTMRx_CSR_TPP ((uint32_t)((uint32_t)1 << 3)) /*!< Timer Pin Polarity */ +#define LPTMRx_CSR_TFC ((uint32_t)((uint32_t)1 << 2)) /*!< Timer Free-Running Counter */ +#define LPTMRx_CSR_TMS ((uint32_t)((uint32_t)1 << 1)) /*!< Timer Mode Select */ +#define LPTMRx_CSR_TEN ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Enable */ + +/********** Bits definition for LPTMRx_PSR register ***********/ +#define LPTMRx_PSR_PRESCALE_SHIFT 3 /*!< Prescale Value (shift) */ +#define LPTMRx_PSR_PRESCALE_MASK ((uint32_t)((uint32_t)0x0F << LPTMRx_PSR_PRESCALE_SHIFT)) /*!< Prescale Value (mask) */ +#define LPTMRx_PSR_PRESCALE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PRESCALE_SHIFT) & LPTMRx_PSR_PRESCALE_MASK)) /*!< Prescale Value */ +#define LPTMRx_PSR_PBYP ((uint32_t)((uint32_t)1 << 2)) /*!< Prescaler Bypass */ +#define LPTMRx_PSR_PCS_SHIFT 0 /*!< Prescaler Clock Select (shift) */ +#define LPTMRx_PSR_PCS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_PSR_PCS_SHIFT)) /*!< Prescaler Clock Select (mask) */ +#define LPTMRx_PSR_PCS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PCS_SHIFT) & LPTMRx_PSR_PCS_MASK)) /*!< Prescaler Clock Select */ + +/********** Bits definition for LPTMRx_CMR register ***********/ +#define LPTMRx_CMR_COMPARE_SHIFT 0 /*!< Compare Value (shift) */ +#define LPTMRx_CMR_COMPARE_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CMR_COMPARE_SHIFT)) /*!< Compare Value (mask) */ +#define LPTMRx_CMR_COMPARE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CMR_COMPARE_SHIFT) & LPTMRx_CMR_COMPARE_MASK)) /*!< Compare Value */ + +/********** Bits definition for LPTMRx_CNR register ***********/ +#define LPTMRx_CNR_COUNTER_SHIFT 0 /*!< Counter Value (shift) */ +#define LPTMRx_CNR_COUNTER_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CNR_COUNTER_SHIFT)) /*!< Counter Value (mask) */ +#define LPTMRx_CNR_COUNTER(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CNR_COUNTER_SHIFT) & LPTMRx_CNR_COUNTER_MASK)) /*!< Counter Value */ + +/****************************************************************/ +/* */ +/* Touch Sensing Input (TSI) */ +/* */ +/****************************************************************/ +/********** Bits definition for TSIx_GENCS register ***********/ +#define TSIx_GENCS_OUTRGF ((uint32_t)((uint32_t)1 << 31)) /*!< Out of Range Flag */ +#define TSIx_GENCS_ESOR ((uint32_t)((uint32_t)1 << 28)) /*!< End-of-scan/Out-of-Range Interrupt Selection */ +#define TSIx_GENCS_MODE_SHIFT 24 /*!< TSI analog modes setup and status bits (shift) */ +#define TSIx_GENCS_MODE_MASK ((uint32_t)((uint32_t)0x0F << TSIx_GENCS_MODE_SHIFT)) /*!< TSI analog modes setup and status bits (mask) */ +#define TSIx_GENCS_MODE(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_MODE_SHIFT) & TSIx_GENCS_MODE_MASK)) /*!< TSI analog modes setup and status bits */ +#define TSIx_GENCS_REFCHRG_SHIFT 21 /*!< Reference oscillator charge/discharge current (shift) */ +#define TSIx_GENCS_REFCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_REFCHRG_SHIFT)) /*!< Reference oscillator charge/discharge current (mask) */ +#define TSIx_GENCS_REFCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_REFCHRG_SHIFT) & TSIx_GENCS_REFCHRG_MASK)) /*!< Reference oscillator charge/discharge current */ +#define TSIx_GENCS_DVOLT_SHIFT 19 /*!< Oscillator voltage rails (shift) */ +#define TSIx_GENCS_DVOLT_MASK ((uint32_t)((uint32_t)0x03 << TSIx_GENCS_DVOLT_SHIFT)) /*!< Oscillator voltage rails (mask) */ +#define TSIx_GENCS_DVOLT(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_DVOLT_SHIFT) & TSIx_GENCS_DVOLT_MASK)) /*!< Oscillator voltage rails */ +#define TSIx_GENCS_EXTCHRG_SHIFT 16 /*!< Electrode oscillator charge/discharge current (shift) */ +#define TSIx_GENCS_EXTCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_EXTCHRG_SHIFT)) /*!< Electrode oscillator charge/discharge current (mask) */ +#define TSIx_GENCS_EXTCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_EXTCHRG_SHIFT) & TSIx_GENCS_EXTCHRG_MASK)) /*!< Electrode oscillator charge/discharge current */ +#define TSIx_GENCS_PS_SHIFT 13 /*!< Electrode oscillator prescaler (shift) */ +#define TSIx_GENCS_PS_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_PS_SHIFT)) /*!< Electrode oscillator prescaler (mask) */ +#define TSIx_GENCS_PS(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_PS_SHIFT) & TSIx_GENCS_PS_MASK)) /*!< Electrode oscillator prescaler */ +#define TSIx_GENCS_NSCN_SHIFT 8 /*!< Number of scans per electrode minus 1 (shift) */ +#define TSIx_GENCS_NSCN_MASK ((uint32_t)((uint32_t)0x1F << TSIx_GENCS_NSCN_SHIFT)) /*!< Number of scans per electrode minus 1 (mask) */ +#define TSIx_GENCS_NSCN(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_NSCN_SHIFT) & TSIx_GENCS_NSCN_MASK)) /*!< Number of scans per electrode minus 1 */ +#define TSIx_GENCS_TSIEN ((uint32_t)((uint32_t)1 << 7)) /*!< TSI Module Enable */ +#define TSIx_GENCS_TSIIEN ((uint32_t)((uint32_t)1 << 6)) /*!< TSI Interrupt Enable */ +#define TSIx_GENCS_STPE ((uint32_t)((uint32_t)1 << 5)) /*!< TSI STOP Enable */ +#define TSIx_GENCS_STM ((uint32_t)((uint32_t)1 << 4)) /*!< Scan Trigger Mode (0=software; 1=hardware) */ +#define TSIx_GENCS_SCNIP ((uint32_t)((uint32_t)1 << 3)) /*!< Scan in Progress Status */ +#define TSIx_GENCS_EOSF ((uint32_t)((uint32_t)1 << 2)) /*!< End of Scan Flag */ +#define TSIx_GENCS_CURSW ((uint32_t)((uint32_t)1 << 1)) /*!< Swap electrode and reference current sources */ + +/********** Bits definition for TSIx_DATA register ************/ +#define TSIx_DATA_TSICH_SHIFT 28 /*!< Specify channel to be measured (shift) */ +#define TSIx_DATA_TSICH_MASK ((uint32_t)((uint32_t)0x0F << TSIx_DATA_TSICH_SHIFT)) /*!< Specify channel to be measured (mask) */ +#define TSIx_DATA_TSICH(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICH_SHIFT) & TSIx_DATA_TSICH_MASK)) /*!< Specify channel to be measured */ +#define TSIx_DATA_DMAEN ((uint32_t)((uint32_t)1 << 23)) /*!< DMA Transfer Enabled */ +#define TSIx_DATA_SWTS ((uint32_t)((uint32_t)1 << 22)) /*!< Software Trigger Start */ +#define TSIx_DATA_TSICNT_SHIFT 0 /*!< TSI Conversion Counter Value (shift) */ +#define TSIx_DATA_TSICNT_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_DATA_TSICNT_SHIFT)) /*!< TSI Conversion Counter Value (mask) */ +#define TSIx_DATA_TSICNT(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICNT_SHIFT) & TSIx_DATA_TSICNT_MASK)) /*!< TSI Conversion Counter Value */ + +/********** Bits definition for TSIx_TSHD register ************/ +#define TSIx_TSHD_THRESH_SHIFT 16 /*!< TSI Wakeup Channel High-Threshold (shift) */ +#define TSIx_TSHD_THRESH_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESH_SHIFT)) /*!< TSI Wakeup Channel High-Threshold (mask) */ +#define TSIx_TSHD_THRESH(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESH_SHIFT) & TSIx_TSHD_THRESH_MASK)) /*!< TSI Wakeup Channel High-Threshold */ +#define TSIx_TSHD_THRESL_SHIFT 0 /*!< TSI Wakeup Channel Low-Threshold (shift) */ +#define TSIx_TSHD_THRESL_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESL_SHIFT)) /*!< TSI Wakeup Channel Low-Threshold (mask) */ +#define TSIx_TSHD_THRESL(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESL_SHIFT) & TSIx_TSHD_THRESL_MASK)) /*!< TSI Wakeup Channel Low-Threshold */ + +/****************************************************************/ +/* */ +/* Multipurpose Clock Generator (MCG) */ +/* */ +/****************************************************************/ +/*********** Bits definition for MCG_C1 register **************/ +#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */ +#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x3 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */ +#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */ +#define MCG_C1_CLKS_FLLPLL MCG_C1_CLKS(0) /*!< Select output of FLL or PLL, depending on PLLS control bit */ +#define MCG_C1_CLKS_IRCLK MCG_C1_CLKS(1) /*!< Select internal reference clock */ +#define MCG_C1_CLKS_ERCLK MCG_C1_CLKS(2) /*!< Select external reference clock */ +#define MCG_C1_FRDIV_SHIFT 3 /*!< FLL External Reference Divider (shift) */ +#define MCG_C1_FRDIV_MASK ((uint8_t)((uint8_t)0x7 << MCG_C1_FRDIV_SHIFT)) /*!< FLL External Reference Divider (mask) */ +#define MCG_C1_FRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_FRDIV_SHIFT) & MCG_C1_FRDIV_MASK)) /*!< FLL External Reference Divider */ +#define MCG_C1_IREFS ((uint8_t)0x04) /*!< Internal Reference Select (0=ERCLK; 1=slow IRCLK) */ +#define MCG_C1_IRCLKEN ((uint8_t)0x02) /*!< Internal Reference Clock Enable */ +#define MCG_C1_IREFSTEN ((uint8_t)0x01) /*!< Internal Reference Stop Enable */ + +/*********** Bits definition for MCG_C2 register **************/ +#define MCG_C2_LOCRE0 ((uint8_t)0x80) /*!< Loss of Clock Reset Enable */ +#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */ +#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x3 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */ +#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */ +#define MCG_C2_HGO0 ((uint8_t)0x08) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */ +#define MCG_C2_EREFS0 ((uint8_t)0x04) /*!< External Reference Select (0=clock; 1=oscillator) */ +#define MCG_C2_LP ((uint8_t)0x02) /*!< Low Power Select (1=FLL/PLL disabled in bypass modes) */ +#define MCG_C2_IRCS ((uint8_t)0x01) /*!< Internal Reference Clock Select (0=slow; 1=fast) */ + +/*********** Bits definition for MCG_C4 register **************/ +#define MCG_C4_DMX32 ((uint8_t)0x80) /*!< DCO Maximum Frequency with 32.768 kHz Reference */ +#define MCG_C4_DRST_DRS_SHIFT 5 /*!< DCO Range Select (shift) */ +#define MCG_C4_DRST_DRS_MASK ((uint8_t)((uint8_t)0x3 << MCG_C4_DRST_DRS_SHIFT)) /*!< DCO Range Select (mask) */ +#define MCG_C4_DRST_DRS(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_DRST_DRS_SHIFT) & MCG_C4_DRST_DRS_MASK)) /*!< DCO Range Select */ +#define MCG_C4_FCTRIM_SHIFT 1 /*!< Fast Internal Reference Clock Trim Setting (shift) */ +#define MCG_C4_FCTRIM_MASK ((uint8_t)((uint8_t)0xF << MCG_C4_FCTRIM_SHIFT)) /*!< Fast Internal Reference Clock Trim Setting (mask) */ +#define MCG_C4_FCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_FCTRIM_SHIFT) & MCG_C4_FCTRIM_MASK)) /*!< Fast Internal Reference Clock Trim Setting */ +#define MCG_C4_SCFTRIM ((uint8_t)0x01) /*!< Slow Internal Reference Clock Fine Trim */ + +/*********** Bits definition for MCG_C5 register **************/ +#define MCG_C5_PLLCLKEN0 ((uint8_t)0x40) /*!< PLL Clock Enable */ +#define MCG_C5_PLLSTEN0 ((uint8_t)0x20) /*!< PLL Stop Enable */ +#define MCG_C5_PRDIV0_MASK ((uint8_t)0x1F) /*!< PLL External Reference Divider (mask) */ +#define MCG_C5_PRDIV0(x) ((uint8_t)((uint8_t)(x) & MCG_C5_PRDIV0_MASK)) /*!< PLL External Reference Divider */ + +/*********** Bits definition for MCG_C6 register **************/ +#define MCG_C6_LOLIE0 ((uint8_t)0x80) /*!< Loss of Lock Interrupt Enable */ +#define MCG_C6_PLLS ((uint8_t)0x40) /*!< PLL Select */ +#define MCG_C6_CME0 ((uint8_t)0x20) /*!< Clock Monitor Enable */ +#define MCG_C6_VDIV0_MASK ((uint8_t)0x1F) /*!< VCO 0 Divider (mask) */ +#define MCG_C6_VDIV0(x) ((uint8_t)((uint8_t)(x) & MCG_C6_VDIV0_MASK)) /*!< VCO 0 Divider */ + +/************ Bits definition for MCG_S register **************/ +#define MCG_S_LOLS ((uint8_t)0x80) /*!< Loss of Lock Status */ +#define MCG_S_LOCK0 ((uint8_t)0x40) /*!< Lock Status */ +#define MCG_S_PLLST ((uint8_t)0x20) /*!< PLL Select Status */ +#define MCG_S_IREFST ((uint8_t)0x10) /*!< Internal Reference Status */ +#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */ +#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x3 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */ +#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */ +#define MCG_S_CLKST_FLL MCG_S_CLKST(0) /*!< Output of the FLL is selected */ +#define MCG_S_CLKST_IRCLK MCG_S_CLKST(1) /*!< Internal reference clock is selected */ +#define MCG_S_CLKST_ERCLK MCG_S_CLKST(2) /*!< External reference clock is selected */ +#define MCG_S_CLKST_PLL MCG_S_CLKST(3) /*!< Output of the PLL is selected */ +#define MCG_S_OSCINIT0 ((uint8_t)0x02) /*!< OSC Initialization */ +#define MCG_S_IRCST ((uint8_t)0x01) /*!< Internal Reference Clock Status */ + +/************ Bits definition for MCG_SC register **************/ +#define MCG_SC_ATME ((uint8_t)0x80) /*!< Automatic Trim Machine Enable */ +#define MCG_SC_ATMS ((uint8_t)0x40) /*!< Automatic Trim Machine Select */ +#define MCG_SC_ATMF ((uint8_t)0x20) /*!< Automatic Trim Machine Fail Flag */ +#define MCG_SC_FLTPRSRV ((uint8_t)0x10) /*!< FLL Filter Preserve Enable */ +#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */ +#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x7 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */ +#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */ +#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */ +#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */ +#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */ +#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */ +#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */ +#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */ +#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */ +#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */ +#define MCG_SC_LOCS0 ((uint8_t)0x01) /*!< OSC0 Loss of Clock Status */ + +/************ Bits definition for MCG_C7 register **************/ +#define MCG_C7_OSCSEL ((uint8_t)0x01) /*!< MCG OSC Clock Select */ + +/************ Bits definition for MCG_C8 register **************/ +#define MCG_C8_LOCRE1 ((uint8_t)0x80) /*!< PLL Loss of Clock Reset Enable */ +#define MCG_C8_LOLRE ((uint8_t)0x40) /*!< PLL Loss of Lock Reset Enable */ +#define MCG_C8_CME1 ((uint8_t)0x20) /*!< PLL Clock Monitor Enable */ +#define MCG_C8_LOCS1 ((uint8_t)0x01) /*!< RTC Loss of Clock Status */ + +/****************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/****************************************************************/ + +/*********** Bits definition for SPIx_MCR register *************/ +#define SPIx_MCR_MSTR ((uint32_t)0x80000000) // Master/Slave Mode Select +#define SPIx_MCR_CONT_SCKE ((uint32_t)0x40000000) // Continuous SCK Enable +#define SPIx_MCR_DCONF(n) (((n) & 3) << 28) // DSPI Configuration +#define SPIx_MCR_FRZ ((uint32_t)0x08000000) // Freeze +#define SPIx_MCR_MTFE ((uint32_t)0x04000000) // Modified Timing Format Enable +#define SPIx_MCR_ROOE ((uint32_t)0x01000000) // Receive FIFO Overflow Overwrite Enable +#define SPIx_MCR_PCSIS(n) (((n) & 0x1F) << 16) // Peripheral Chip Select x Inactive State +#define SPIx_MCR_DOZE ((uint32_t)0x00008000) // Doze Enable +#define SPIx_MCR_MDIS ((uint32_t)0x00004000) // Module Disable +#define SPIx_MCR_DIS_TXF ((uint32_t)0x00002000) // Disable Transmit FIFO +#define SPIx_MCR_DIS_RXF ((uint32_t)0x00001000) // Disable Receive FIFO +#define SPIx_MCR_CLR_TXF ((uint32_t)0x00000800) // Clear the TX FIFO and counter +#define SPIx_MCR_CLR_RXF ((uint32_t)0x00000400) // Clear the RX FIFO and counter +#define SPIx_MCR_SMPL_PT(n) (((n) & 3) << 8) // Sample Point +#define SPIx_MCR_HALT ((uint32_t)0x00000001) // Halt + +/*********** Bits definition for SPIx_TCR register *************/ +#define SPIx_TCR_TCNT(n) (((n) & 0xffff) << 16) // DSPI Transfer Count Register + +/*********** Bits definition for SPIx_CTARn register *************/ +#define SPIx_CTARn_DBR ((uint32_t)0x80000000) // Double Baud Rate +#define SPIx_CTARn_FMSZ_SHIFT 27 // Frame Size Shift +#define SPIx_CTARn_FMSZ_MASK 0xF // Frame Size Mask +#define SPIx_CTARn_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1) +#define SPIx_CTARn_CPOL ((uint32_t)0x04000000) // Clock Polarity +#define SPIx_CTARn_CPHA ((uint32_t)0x02000000) // Clock Phase +#define SPIx_CTARn_LSBFE ((uint32_t)0x01000000) // LSB First +#define SPIx_CTARn_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler +#define SPIx_CTARn_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler +#define SPIx_CTARn_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler +#define SPIx_CTARn_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler +#define SPIx_CTARn_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler +#define SPIx_CTARn_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler +#define SPIx_CTARn_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler +#define SPIx_CTARn_BR(n) (((n) & 15) << 0) // Baud Rate Scaler + + +/*********** Bits definition for SPIx_CTARn_SLAVE register *************/ +#define SPIx_CTARn_SLAVE_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1) +#define SPIx_CTARn_SLAVE_CPOL ((uint32_t)0x04000000) // Clock Polarity +#define SPIx_CTARn_SLAVE_CPHA ((uint32_t)0x02000000) // Clock Phase + +/*********** Bits definition for SPIx_SR register *************/ +#define SPIx_SR_TCF ((uint32_t)0x80000000) // Transfer Complete Flag +#define SPIx_SR_TXRXS ((uint32_t)0x40000000) // TX and RX Status +#define SPIx_SR_EOQF ((uint32_t)0x10000000) // End of Queue Flag +#define SPIx_SR_TFUF ((uint32_t)0x08000000) // Transmit FIFO Underflow Flag +#define SPIx_SR_TFFF ((uint32_t)0x02000000) // Transmit FIFO Fill Flag +#define SPIx_SR_RFOF ((uint32_t)0x00080000) // Receive FIFO Overflow Flag +#define SPIx_SR_RFDF ((uint32_t)0x00020000) // Receive FIFO Drain Flag +#define SPIx_SR_TXCTR (((n) & 15) << 12) // TX FIFO Counter +#define SPIx_SR_TXNXPTR (((n) & 15) << 8) // Transmit Next Pointer +#define SPIx_SR_RXCTR (((n) & 15) << 4) // RX FIFO Counter +#define SPIx_SR_POPNXTPTR ((n) & 15) // POP Next Pointer + +/*********** Bits definition for SPIx_SR register *************/ +#define SPIx_RSER_TCF_RE ((uint32_t)0x80000000) // Transmission Complete Request Enable +#define SPIx_RSER_EOQF_RE ((uint32_t)0x10000000) // DSPI Finished Request Request Enable +#define SPIx_RSER_TFUF_RE ((uint32_t)0x08000000) // Transmit FIFO Underflow Request Enable +#define SPIx_RSER_TFFF_RE ((uint32_t)0x02000000) // Transmit FIFO Fill Request Enable +#define SPIx_RSER_TFFF_DIRS ((uint32_t)0x01000000) // Transmit FIFO FIll Dma or Interrupt Request Select +#define SPIx_RSER_RFOF_RE ((uint32_t)0x00080000) // Receive FIFO Overflow Request Enable +#define SPIx_RSER_RFDF_RE ((uint32_t)0x00020000) // Receive FIFO Drain Request Enable +#define SPIx_RSER_RFDF_DIRS ((uint32_t)0x00010000) // Receive FIFO Drain DMA or Interrupt Request Select + +/*********** Bits definition for SPIx_PUSHR register *************/ +#define SPIx_PUSHR_CONT ((uint32_t)0x80000000) // Continuous Peripheral Chip Select Enable +#define SPIx_PUSHR_CTAS(n) (((n) & 7) << 28) // Clock and Transfer Attributes Select +#define SPIx_PUSHR_EOQ ((uint32_t)0x08000000) // End Of Queue +#define SPIx_PUSHR_CTCNT ((uint32_t)0x04000000) // Clear Transfer Counter +#define SPIx_PUSHR_PCS(n) (((n) & 31) << 16) // Peripheral Chip Select +#define SPIx_PUSHR_TXDATA(n) ((n) & 0xffff) // Transmit Data + +/*********** Bits definition for SPIx_PUSHR_SLAVE register *************/ +#define SPIx_PUSHR_SLAVE_TXDATA(n) (((n) & 0xffff) << 0) // Transmit Data in slave mode + +/*********** Bits definition for SPIx_POPR register *************/ +#define SPIx_POPR_RXDATA(n) (((n) & 0xffff) << 16) // Received Data + +/*********** Bits definition for SPIx_TXFRn register *************/ +#define SPIx_TXFRn_TXCMD_TXDATA (((n) & 0xffff) << 16) // Transmit Command (in master mode) +#define SPIx_TXFRn_TXDATA(n) (((n) & 0xffff) << 0) // Transmit Data + +/*********** Bits definition for SPIx_RXFRn register *************/ +#define SPIx_RXFRn_RXDATA(n) (((n) & 0xffff) << 0) // Receive Data + +/****************************************************************/ +/* */ +/* Inter-Integrated Circuit (I2C) */ +/* */ +/****************************************************************/ +/*********** Bits definition for I2Cx_A1 register *************/ +#define I2Cx_A1_AD ((uint8_t)0xFE) /*!< Address [7:1] */ + +#define I2Cx_A1_AD_SHIT 1 + +/*********** Bits definition for I2Cx_F register **************/ +#define I2Cx_F_MULT ((uint8_t)0xC0) /*!< Multiplier factor */ +#define I2Cx_F_ICR ((uint8_t)0x3F) /*!< Clock rate */ + +#define I2Cx_F_MULT_SHIFT 5 + +/*********** Bits definition for I2Cx_C1 register *************/ +#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ +#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ +#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ +#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ +#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ +#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ +#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ +#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ + +/*********** Bits definition for I2Cx_S register **************/ +#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ +#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ +#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ +#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ +#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ +#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ +#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ +#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ + +/*********** Bits definition for I2Cx_D register **************/ +#define I2Cx_D_DATA ((uint8_t)0xFF) /*!< Data */ + +/*********** Bits definition for I2Cx_C2 register *************/ +#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ +#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ +#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ +#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ +#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ +#define I2Cx_C2_AD_10_8 ((uint8_t)0x03) /*!< Slave Address [10:8] */ + +/*********** Bits definition for I2Cx_FLT register ************/ +#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ +#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ +#define I2Cx_FLT_STOPIE ((uint8_t)0x20) /*!< I2C Bus Stop Interrupt Enable */ +#define I2Cx_FLT_FLT ((uint8_t)0x1F) /*!< I2C Programmable Filter Factor */ + +/*********** Bits definition for I2Cx_RA register *************/ +#define I2Cx_RA_RAD ((uint8_t)0xFE) /*!< Range Slave Address */ + +#define I2Cx_RA_RAD_SHIFT 1 + +/*********** Bits definition for I2Cx_SMB register ************/ +#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ +#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ +#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ +#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ +#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ +#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ +#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ +#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ + +/*********** Bits definition for I2Cx_A2 register *************/ +#define I2Cx_A2_SAD ((uint8_t)0xFE) /*!< SMBus Address */ + +#define I2Cx_A2_SAD_SHIFT 1 + +/*********** Bits definition for I2Cx_SLTH register ***********/ +#define I2Cx_SLTH_SSLT ((uint8_t)0xFF) /*!< MSB of SCL low timeout value */ + +/*********** Bits definition for I2Cx_SLTL register ***********/ +#define I2Cx_SLTL_SSLT ((uint8_t)0xFF) /*!< LSB of SCL low timeout value */ + +/****************************************************************/ +/* */ +/* Universal Asynchronous Receiver/Transmitter (UART) */ +/* */ +/****************************************************************/ +/********* Bits definition for UARTx_BDH register *************/ +#define UARTx_BDH_LBKDIE ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Enable */ +#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RxD Input Active Edge Interrupt Enable */ +#define UARTx_BDH_SBR_MASK ((uint8_t)0x1F) +#define UARTx_BDH_SBR(x) ((uint8_t)((uint8_t)(x) & UARTx_BDH_SBR_MASK)) /*!< Baud Rate Modulo Divisor */ + +/********* Bits definition for UARTx_BDL register *************/ +#define UARTx_BDL_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDL_SBR_MASK ((uint8_t)((uint8_t)0xFF << UARTx_BDL_SBR_SHIFT)) +#define UARTx_BDL_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDL_SBR_SHIFT) & UARTx_BDL_SBR_MASK)) + +/********* Bits definition for UARTx_C1 register **************/ +#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ +#define UARTx_C1_DOZEEN ((uint8_t)0x40) /*!< Doze Enable */ +#define UARTx_C1_UARTSWAI ((uint8_t)0x40) /*!< UART Stops in Wait Mode */ +#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */ +#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */ +#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */ +#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */ +#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */ +#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */ + +/********* Bits definition for UARTx_C2 register **************/ +#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */ +#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */ +#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */ +#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */ +#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */ +#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */ +#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */ +#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */ + +/********* Bits definition for UARTx_S1 register **************/ +#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */ +#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */ +#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */ +#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */ +#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */ +#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */ +#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */ +#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */ + +/********* Bits definition for UARTx_S2 register **************/ +#define UARTx_S2_LBKDIF ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Flag */ +#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */ +#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */ +#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */ +#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */ +#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */ +#define UARTx_S2_LBKDE ((uint8_t)0x02) /*!< LIN Break Detect Enable */ +#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */ + +/********* Bits definition for UARTx_C3 register **************/ +#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */ +#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */ +#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */ +#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */ +#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */ +#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */ +#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */ +#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */ + +/********* Bits definition for UARTx_D register ***************/ +#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ + +/********* Bits definition for UARTx_MA1 register *************/ +#define UARTx_MA1_MA ((uint8_t)0xFF) /*!< Match Address */ + +/********* Bits definition for UARTx_MA2 register *************/ +#define UARTx_MA2_MA ((uint8_t)0xFF) /*!< Match Address */ + +/********* Bits definition for UARTx_C4 register **************/ +#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ +#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */ +#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */ +#define UARTx_C4_BRFA_MASK ((uint8_t)0x1F) +#define UARTx_C4_BRFA(x) ((uint8_t)((uint8_t)(x) & UARTx_C4_BRFA_MASK)) /*!< Baud Rate Fine Adjust */ + +/********* Bits definition for UARTx_C5 register **************/ +#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */ +#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */ +#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */ +#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */ + +/******* Bits definition for UARTx_CFIFO register ************/ +#define UARTx_CFIFO_TXFLUSH ((uint8_t)0x80) /*!< Transmit FIFO/Buffer Flush */ +#define UARTx_CFIFO_RXFLUSH ((uint8_t)0x40) /*!< Receive FIFO/Buffer Flush */ +#define UARTx_CFIFO_RXOFE ((uint8_t)0x04) /*!< Receive FIFO Overflow Interrupt Enable */ +#define UARTx_CFIFO_TXOFE ((uint8_t)0x02) /*!< Transmit FIFO Overflow Interrupt Enable */ +#define UARTx_CFIFO_RXUFE ((uint8_t)0x01) /*!< Receive FIFO Underflow Interrupt Enable */ + +/******* Bits definition for UARTx_PFIFO register ************/ +#define UARTx_PFIFO_TXFE ((uint8_t)0x80) /*!< Transmit FIFO Enable */ +#define UARTx_PFIFO_TXFIFOSIZE_SHIFT 4 +#define UARTx_PFIFO_TXFIFOSIZE_MASK ((uint8_t)((uint8_t)0x7 << UARTx_PFIFO_TXFIFOSIZE_SHIFT)) +#define UARTx_PFIFO_TXFIFOSIZE(x) ((uint8_t)(((uint8_t)(x) << UARTx_PFIFO_TXFIFOSIZE_SHIFT) & UARTx_PFIFO_TXFIFOSIZE_MASK)) /*!< Transmit FIFO Buffer depth */ +#define UARTx_PFIFO_RXFE ((uint8_t)0x08) /*!< Receive FIFOh */ +#define UARTx_PFIFO_RXFIFOSIZE_SHIFT 0 +#define UARTx_PFIFO_RXFIFOSIZE_MASK ((uint8_t)((uint8_t)0x7 << UARTx_PFIFO_RXFIFOSIZE_SHIFT)) +#define UARTx_PFIFO_RXFIFOSIZE(x) ((uint8_t)(((uint8_t)(x) << UARTx_PFIFO_RXFIFOSIZE_SHIFT) & UARTx_PFIFO_RXFIFOSIZE_MASK)) /*!< Receive FIFO Buffer depth */ + +/****************************************************************/ +/* */ +/* Power Management Controller (PMC) */ +/* */ +/****************************************************************/ +/********* Bits definition for PMC_LVDSC1 register *************/ +#define PMC_LVDSC1_LVDF ((uint8_t)0x80) /*!< Low-Voltage Detect Flag */ +#define PMC_LVDSC1_LVDACK ((uint8_t)0x40) /*!< Low-Voltage Detect Acknowledge */ +#define PMC_LVDSC1_LVDIE ((uint8_t)0x20) /*!< Low-Voltage Detect Interrupt Enable */ +#define PMC_LVDSC1_LVDRE ((uint8_t)0x10) /*!< Low-Voltage Detect Reset Enable */ +#define PMC_LVDSC1_LVDV_MASK ((uint8_t)0x3) /*!< Low-Voltage Detect Voltage Select */ +#define PMC_LVDSC1_LVDV_SHIFT 0 +#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) +/********* Bits definition for PMC_LVDSC1 register *************/ +#define PMC_LVDSC2_LVWF ((uint8_t)0x80) /*!< Low-Voltage Warning Flag */ +#define PMC_LVDSC2_LVWACK ((uint8_t)0x40) /*!< Low-Voltage Warning Acknowledge */ +#define PMC_LVDSC2_LVWIE ((uint8_t)0x20) /*!< Low-Voltage Warning Interrupt Enable */ +#define PMC_LVDSC2_LVWV_MASK 0x3 /*!< Low-Voltage Warning Voltage Select */ +#define PMC_LVDSC2_LVWV_SHIFT 0 +#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) +/********* Bits definition for PMC_REGSC register *************/ +#define PMC_REGSC_BGEN ((uint8_t)0x10) /*!< Bandgap Enable In VLPx Operation */ +#define PMC_REGSC_ACKISO ((uint8_t)0x8) /*!< Acknowledge Isolation */ +#define PMC_REGSC_REGONS ((uint8_t)0x4) /*!< Regulator In Run Regulation Status */ +#define PMC_REGSC_BGBE ((uint8_t)0x1) /*!< Bandgap Buffer Enable */ + +/****************************************************************/ +/* */ +/* Watchdog */ +/* */ +/****************************************************************/ +/******** Bits definition for WDOG_STCTRLH register ***********/ +#define WDOG_STCTRLH_DISTESTWDOG ((uint16_t)0x4000) +#define WDOG_STCTRLH_BYTESEL_1_0 ((uint16_t)0x3000) +#define WDOG_STCTRLH_TESTSEL ((uint16_t)0x0800) +#define WDOG_STCTRLH_TESTWDOG ((uint16_t)0x0400) +#define WDOG_STCTRLH_WAITEN ((uint16_t)0x0080) +#define WDOG_STCTRLH_STOPEN ((uint16_t)0x0040) +#define WDOG_STCTRLH_DBGEN ((uint16_t)0x0020) +#define WDOG_STCTRLH_ALLOWUPDATE ((uint16_t)0x0010) +#define WDOG_STCTRLH_WINEN ((uint16_t)0x0008) +#define WDOG_STCTRLH_IRQRSTEN ((uint16_t)0x0004) +#define WDOG_STCTRLH_CLKSRC ((uint16_t)0x0002) +#define WDOG_STCTRLH_WDOGEN ((uint16_t)0x0001) + +/******** Bits definition for WDOG_STCTRLL register ***********/ +#define WDOG_STCTRLL_INTFLG ((uint16_t)0x8000) + +/********* Bits definition for WDOG_PRESC register ************/ +#define WDOG_PRESC_PRESCVAL ((uint16_t)0x0700) + +/****************************************************************/ +/* */ +/* USB OTG */ +/* */ +/****************************************************************/ + +/******** Bits definition for USBx_ADDINFO register ***********/ +#define USBx_ADDINFO_IEHOST ((uint8_t)0x01) /*!< Host mode operation? */ +#define USBx_ADDINFO_IRQNUM_SHIFT 6 /*!< Assigned Interrupt Request Number */ +#define USBx_ADDINFO_IRQNUM_MASK ((uint8_t)((uint8_t)0x1F << USBx_ADDINFO_IRQNUM_SHIFT)) + +/******** Bits definition for USBx_OTGISTAT register **********/ +#define USBx_OTGISTAT_IDCHG ((uint8_t)0x80) /*!< Change in the ID Signal from the USB connector is sensed. */ +#define USBx_OTGISTAT_ONEMSEC ((uint8_t)0x40) /*!< Set when the 1 millisecond timer expires. */ +#define USBx_OTGISTAT_LINE_STATE_CHG ((uint8_t)0x20) /*!< Set when the USB line state changes. */ +#define USBx_OTGISTAT_SESSVLDCHG ((uint8_t)0x08) /*!< Set when a change in VBUS is detected indicating a session valid or a session no longer valid. */ +#define USBx_OTGISTAT_B_SESS_CHG ((uint8_t)0x04) /*!< Set when a change in VBUS is detected on a B device. */ +#define USBx_OTGISTAT_AVBUSCHG ((uint8_t)0x01) /*!< Set when a change in VBUS is detected on an A device. */ + +/******** Bits definition for USBx_OTGICR register ************/ +#define USBx_OTGICR_IDEN ((uint8_t)0x80) /*!< ID Interrupt Enable */ +#define USBx_OTGICR_ONEMSECEN ((uint8_t)0x40) /*!< One Millisecond Interrupt Enable */ +#define USBx_OTGICR_LINESTATEEN ((uint8_t)0x20) /*!< Line State Change Interrupt Enable */ +#define USBx_OTGICR_SESSVLDEN ((uint8_t)0x08) /*!< Session Valid Interrupt Enable */ +#define USBx_OTGICR_BSESSEN ((uint8_t)0x04) /*!< B Session END Interrupt Enable */ +#define USBx_OTGICR_AVBUSEN ((uint8_t)0x01) /*!< A VBUS Valid Interrupt Enable */ + +/******** Bits definition for USBx_OTGSTAT register ***********/ +#define USBx_OTGSTAT_ID ((uint8_t)0x80) /*!< Indicates the current state of the ID pin on the USB connector */ +#define USBx_OTGSTAT_ONEMSECEN ((uint8_t)0x40) /*!< This bit is reserved for the 1ms count, but it is not useful to software. */ +#define USBx_OTGSTAT_LINESTATESTABLE ((uint8_t)0x20) /*!< Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 millisecond. */ +#define USBx_OTGSTAT_SESS_VLD ((uint8_t)0x08) /*!< Session Valid */ +#define USBx_OTGSTAT_BSESSEND ((uint8_t)0x04) /*!< B Session End */ +#define USBx_OTGSTAT_AVBUSVLD ((uint8_t)0x01) /*!< A VBUS Valid */ + +/******** Bits definition for USBx_OTGCTL register ************/ +#define USBx_OTGCTL_DPHIGH ((uint8_t)0x80) /*!< D+ Data Line pullup resistor enable */ +#define USBx_OTGCTL_DPLOW ((uint8_t)0x20) /*!< D+ Data Line pull-down resistor enable */ +#define USBx_OTGCTL_DMLOW ((uint8_t)0x10) /*!< D– Data Line pull-down resistor enable */ +#define USBx_OTGCTL_OTGEN ((uint8_t)0x04) /*!< On-The-Go pullup/pulldown resistor enable */ + +/******** Bits definition for USBx_ISTAT register *************/ +#define USBx_ISTAT_STALL ((uint8_t)0x80) /*!< Stall interrupt */ +#define USBx_ISTAT_ATTACH ((uint8_t)0x40) /*!< Attach interrupt */ +#define USBx_ISTAT_RESUME ((uint8_t)0x20) /*!< Signal remote wakeup on the bus */ +#define USBx_ISTAT_SLEEP ((uint8_t)0x10) /*!< Detected bus idle for 3ms */ +#define USBx_ISTAT_TOKDNE ((uint8_t)0x08) /*!< Completed processing of current token */ +#define USBx_ISTAT_SOFTOK ((uint8_t)0x04) /*!< Received start of frame */ +#define USBx_ISTAT_ERROR ((uint8_t)0x02) /*!< Error (must check ERRSTAT!) */ +#define USBx_ISTAT_USBRST ((uint8_t)0x01) /*!< USB reset detected */ + +/******** Bits definition for USBx_INTEN register ***************/ +#define USBx_INTEN_STALLEN ((uint8_t)0x80) /*!< STALL interrupt enable */ +#define USBx_INTEN_ATTACHEN ((uint8_t)0x40) /*!< ATTACH interrupt enable */ +#define USBx_INTEN_RESUMEEN ((uint8_t)0x20) /*!< RESUME interrupt enable */ +#define USBx_INTEN_SLEEPEN ((uint8_t)0x10) /*!< SLEEP interrupt enable */ +#define USBx_INTEN_TOKDNEEN ((uint8_t)0x08) /*!< TOKDNE interrupt enable */ +#define USBx_INTEN_SOFTOKEN ((uint8_t)0x04) /*!< SOFTOK interrupt enable */ +#define USBx_INTEN_ERROREN ((uint8_t)0x02) /*!< ERROR interrupt enable */ +#define USBx_INTEN_USBRSTEN ((uint8_t)0x01) /*!< USBRST interrupt enable */ + +/******** Bits definition for USBx_ERRSTAT register ***********/ +#define USBx_ERRSTAT_BTSERR ((uint8_t)0x80) /*!< Bit stuff error detected */ +#define USBx_ERRSTAT_DMAERR ((uint8_t)0x20) /*!< DMA request was not given */ +#define USBx_ERRSTAT_BTOERR ((uint8_t)0x10) /*!< BUS turnaround timeout error */ +#define USBx_ERRSTAT_DFN8 ((uint8_t)0x08) /*!< Received data not 8-bit sized */ +#define USBx_ERRSTAT_CRC16 ((uint8_t)0x04) /*!< Packet with CRC16 error */ +#define USBx_ERRSTAT_CRC5EOF ((uint8_t)0x02) /*!< CRC5 (device) or EOF (host) error */ +#define USBx_ERRSTAT_PIDERR ((uint8_t)0x01) /*!< PID check field fail */ + +/******** Bits definition for USBx_STAT register *************/ +#define USBx_STAT_ENDP_MASK ((uint8_t)0xF0) /*!< Endpoint address mask*/ +#define USBx_STAT_ENDP_SHIFT ((uint8_t)0x04) /*!< Endpoint address shift*/ +#define USBx_STAT_TX_MASK ((uint8_t)0x08) /*!< Transmit indicator mask*/ +#define USBx_STAT_TX_SHIFT ((uint8_t)0x03) /*!< Transmit indicator shift*/ +#define USBx_STAT_ODD_MASK ((uint8_t)0x04) /*!< EVEN/ODD bank indicator mask*/ +#define USBx_STAT_ODD_SHIFT ((uint8_t)0x02) /*!< EVEN/ODD bank indicator shift */ + +/******** Bits definition for USBx_CTL register *****************/ +#define USBx_CTL_JSTATE ((uint8_t)0x80) /*!< Live USB differential receiver JSTATE signal */ +#define USBx_CTL_SE0 ((uint8_t)0x40) /*!< Live USB single ended zero signal */ +#define USBx_CTL_TXSUSPENDTOKENBUS ((uint8_t)0x20) /*!< */ +#define USBx_CTL_RESET ((uint8_t)0x10) /*!< Generates an USB reset signal (host mode) */ +#define USBx_CTL_HOSTMODEEN ((uint8_t)0x08) /*!< Operate in Host mode */ +#define USBx_CTL_RESUME ((uint8_t)0x04) /*!< Executes resume signaling */ +#define USBx_CTL_ODDRST ((uint8_t)0x02) /*!< Reset all BDT ODD ping/pong bits */ +#define USBx_CTL_USBENSOFEN ((uint8_t)0x01) /*!< USB Enable! */ + +/******** Bits definition for USBx_ADDR register ****************/ +#define USBx_ADDR_LSEN ((uint8_t)0x80) /*!< Low Speed Enable bit */ +#define USBx_ADDR_ADDR_SHIFT 0 /*!< USB Address */ +#define USBx_ADDR_ADDR_MASK ((uint8_t)0x7F) /*!< USB Address */ + +/******** Bits definition for USBx_ENDPTn register **************/ +#define USBx_ENDPTn_HOSTWOHUB ((uint8_t)0x80) +#define USBx_ENDPTn_RETRYDIS ((uint8_t)0x40) +#define USBx_ENDPTn_EPCTLDIS ((uint8_t)0x10) /*!< Disables control transfers */ +#define USBx_ENDPTn_EPRXEN ((uint8_t)0x08) /*!< Enable RX transfers */ +#define USBx_ENDPTn_EPTXEN ((uint8_t)0x04) /*!< Enable TX transfers */ +#define USBx_ENDPTn_EPSTALL ((uint8_t)0x02) /*!< Endpoint is called and in STALL */ +#define USBx_ENDPTn_EPHSHK ((uint8_t)0x01) /*!< Enable handshaking during transaction */ + +/******** Bits definition for USBx_USBCTRL register *************/ +#define USBx_USBCTRL_SUSP ((uint8_t)0x80) /*!< USB transceiver in suspend state */ +#define USBx_USBCTRL_PDE ((uint8_t)0x40) /*!< Enable weak pull-downs */ + +/******** Bits definition for USBx_OBSERVE register *************/ +#define USBx_OBSERVE_DPPU ((uint8_t)0x80) /*!< Provides observability of the D+ Pullup . signal output from the USB OTG module */ +#define USBx_OBSERVE_DPPD ((uint8_t)0x40) /*!< Provides observability of the D+ Pulldown . signal output from the USB OTG module */ +#define USBx_OBSERVE_DMPD ((uint8_t)0x10) /*!< Provides observability of the D- Pulldown signal output from the USB OTG module */ + +/******** Bits definition for USBx_CONTROL register *************/ +#define USBx_CONTROL_DPPULLUPNONOTG ((uint8_t)0x10) /*!< Control pull-ups in device mode */ + +/******** Bits definition for USBx_USBTRC0 register *************/ +#define USBx_USBTRC0_USBRESET ((uint8_t)0x80) /*!< USB reset */ +#define USBx_USBTRC0_USBRESMEN ((uint8_t)0x20) /*!< Asynchronous resume interrupt enable */ +#define USBx_USBTRC0_SYNC_DET ((uint8_t)0x02) /*!< Synchronous USB interrupt detect */ +#define USBx_USBTRC0_USB_RESUME_INT ((uint8_t)0x01) /*!< USB asynchronous interrupt */ + +/****************************************************************/ +/* */ +/* Flash Memory Module (FTFL) */ +/* */ +/****************************************************************/ +/********** Bits definition for FTFL_FSTAT register ***********/ +#define FTFL_FSTAT_CCIF ((uint8_t)0x80) /*!< Command Complete Interrupt Flag */ +#define FTFL_FSTAT_RDCOLERR ((uint8_t)0x40) /*!< Flash Read Collision Error Flag */ +#define FTFL_FSTAT_ACCERR ((uint8_t)0x20) /*!< Flash Access Error Flag */ +#define FTFL_FSTAT_FPVIOL ((uint8_t)0x10) /*!< Flash Protection Violation Flag */ +#define FTFL_FSTAT_MGSTAT0 ((uint8_t)0x01) /*!< Memory Controller Command Completion Status Flag */ + +/********** Bits definition for FTFL_FCNFG register ***********/ +#define FTFL_FCNFG_CCIE ((uint8_t)0x80) /*!< Command Complete Interrupt Enable */ +#define FTFL_FCNFG_RDCOLLIE ((uint8_t)0x40) /*!< Read Collision Error Interrupt Enable */ +#define FTFL_FCNFG_ERSAREQ ((uint8_t)0x20) /*!< Erase All Request */ +#define FTFL_FCNFG_ERSSUSP ((uint8_t)0x10) /*!< Erase Suspend */ +#define FTFL_FCNFG_PFLSH ((uint8_t)0x04) /*!< Flash memory configuration */ +#define FTFL_FCNFG_RAMRDY ((uint8_t)0x02) /*!< RAM Ready */ +#define FTFL_FCNFG_EEERDY ((uint8_t)0x01) /*!< EEPROM backup data has been copied to the FlexRAM and is therefore available for read access */ + +/********** Bits definition for FTFL_FSEC register ************/ +#define FTFL_FSEC_KEYEN_MASK ((uint8_t)0xC0) /*!< Backdoor Key Security Enable */ +#define FTFL_FSEC_MEEN_MASK ((uint8_t)0x30) /*!< Mass Erase Enable Bits */ +#define FTFL_FSEC_FSLACC_MASK ((uint8_t)0x0C) /*!< Freescale Failure Analysis Access Code */ +#define FTFL_FSEC_SEC_MASK ((uint8_t)0x03) /*!< Flash Security */ +#define FTFL_FSEC_KEYEN_ENABLED ((uint8_t)0x80) +#define FTFL_FSEC_MEEN_DISABLED ((uint8_t)0x20) +#define FTFL_FSEC_SEC_UNSECURE ((uint8_t)0x02) + +/********** Bits definition for FTFL_FOPT register ************/ +#define FTFL_FOPT_NMI_DIS ((uint8_t)0x04) /*!< Enables/disables control for the NMI function */ +#define FTFL_FOPT_EZPORT_DIS ((uint8_t)0x02) /*!< EzPort operation */ +#define FTFL_FOPT_LPBOOT ((uint8_t)0x01) /*!< Normal/low-power boot*/ + +#endif diff --git a/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl25z.h b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl25z.h new file mode 100644 index 0000000..2f907e1 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl25z.h @@ -0,0 +1,1100 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _KL25Z_H_ +#define _KL25Z_H_ + +/** + * @brief KL2x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __MPU_PRESENT 0 +#define __VTOR_PRESENT 1 +#define __NVIC_PRIO_BITS 2 +#define __Vendor_SysTickConfig 0 + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ****************/ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + +/****** KL2x Specific Interrupt Numbers ***********************/ + DMA0_IRQn = 0, + DMA1_IRQn = 1, + DMA2_IRQn = 2, + DMA3_IRQn = 3, + Reserved0_IRQn = 4, + FTFA_IRQn = 5, + PMC_IRQn = 6, + LLWU_IRQn = 7, + I2C0_IRQn = 8, + I2C1_IRQn = 9, + SPI0_IRQn = 10, + SPI1_IRQn = 11, + UART0_IRQn = 12, + UART1_IRQn = 13, + UART2_IRQn = 14, + ADC0_IRQn = 15, + CMP0_IRQn = 16, + TPM0_IRQn = 17, + TPM1_IRQn = 18, + TPM2_IRQn = 19, + RTC0_IRQn = 20, + RTC1_IRQn = 21, + PIT_IRQn = 22, + Reserved1_IRQn = 23, + USB_OTG_IRQn = 24, + DAC0_IRQn = 25, + TSI0_IRQn = 26, + MCG_IRQn = 27, + LPTMR0_IRQn = 28, + Reserved2_IRQn = 29, + PINA_IRQn = 30, + PIND_IRQn = 31, +} IRQn_Type; + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +typedef struct +{ + __IO uint8_t C1; + __IO uint8_t C2; + __IO uint8_t C3; + __IO uint8_t C4; + __IO uint8_t C5; + __IO uint8_t C6; + __I uint8_t S; + uint8_t RESERVED0[1]; + __IO uint8_t SC; + uint8_t RESERVED1[1]; + __IO uint8_t ATCVH; + __IO uint8_t ATCVL; + __IO uint8_t C7; + __IO uint8_t C8; + __IO uint8_t C9; + __IO uint8_t C10; +} MCG_TypeDef; + +typedef struct +{ + __IO uint32_t SC; + __IO uint32_t CNT; + __IO uint32_t MOD; + struct { // Channels + __IO uint32_t SC; + __IO uint32_t V; + } C[6]; + uint32_t RESERVED0[5]; + __IO uint32_t STATUS; + uint32_t RESERVED1[12]; + __IO uint32_t CONF; +} TPM_TypeDef; + +typedef struct +{ + __IO uint32_t GENCS; + __IO uint32_t DATA; + __IO uint32_t TSHD; +} TSI_TypeDef; + +typedef struct +{ + __IO uint8_t C1; + __IO uint8_t C2; + __IO uint8_t BR; + __IO uint8_t S; + uint8_t RESERVED0[1]; + __IO uint8_t D; + uint8_t RESERVED1[1]; + __IO uint8_t M; +} SPI_TypeDef; + +typedef struct +{ + __IO uint8_t A1; + __IO uint8_t F; + __IO uint8_t C1; + __IO uint8_t S; + __IO uint8_t D; + __IO uint8_t C2; + __IO uint8_t FLT; + __IO uint8_t RA; + __IO uint8_t SMB; + __IO uint8_t A2; + __IO uint8_t SLTH; + __IO uint8_t SLTL; +} I2C_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __I uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t C4; +} UART_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __IO uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t MA1; + __IO uint8_t MA2; + __IO uint8_t C4; + __IO uint8_t C5; +} UARTLP_TypeDef; + +typedef struct { + __I uint8_t PERID; // 0x00 + uint8_t RESERVED0[3]; + __I uint8_t IDCOMP; // 0x04 + uint8_t RESERVED1[3]; + __I uint8_t REV; // 0x08 + uint8_t RESERVED2[3]; + __I uint8_t ADDINFO; // 0x0C + uint8_t RESERVED3[3]; + __IO uint8_t OTGISTAT; // 0x10 + uint8_t RESERVED4[3]; + __IO uint8_t OTGICR; // 0x14 + uint8_t RESERVED5[3]; + __IO uint8_t OTGSTAT; // 0x18 + uint8_t RESERVED6[3]; + __IO uint8_t OTGCTL; // 0x1C + uint8_t RESERVED7[99]; + __IO uint8_t ISTAT; // 0x80 + uint8_t RESERVED8[3]; + __IO uint8_t INTEN; // 0x84 + uint8_t RESERVED9[3]; + __IO uint8_t ERRSTAT; // 0x88 + uint8_t RESERVED10[3]; + __IO uint8_t ERREN; // 0x8C + uint8_t RESERVED11[3]; + __I uint8_t STAT; // 0x90 + uint8_t RESERVED12[3]; + __IO uint8_t CTL; // 0x94 + uint8_t RESERVED13[3]; + __IO uint8_t ADDR; // 0x98 + uint8_t RESERVED14[3]; + __IO uint8_t BDTPAGE1; // 0x9C + uint8_t RESERVED15[3]; + __IO uint8_t FRMNUML; // 0xA0 + uint8_t RESERVED16[3]; + __IO uint8_t FRMNUMH; // 0xA4 + uint8_t RESERVED17[3]; + __IO uint8_t TOKEN; // 0xA8 + uint8_t RESERVED18[3]; + __IO uint8_t SOFTHLD; // 0xAC + uint8_t RESERVED19[3]; + __IO uint8_t BDTPAGE2; // 0xB0 + uint8_t RESERVED20[3]; + __IO uint8_t BDTPAGE3; // 0xB4 + uint8_t RESERVED21[11]; + struct { + __IO uint8_t V; // 0xC0 + uint8_t RESERVED[3]; + } ENDPT[16]; + __IO uint8_t USBCTRL; // 0x100 + uint8_t RESERVED22[3]; + __I uint8_t OBSERVE; // 0x104 + uint8_t RESERVED23[3]; + __IO uint8_t CONTROL; // 0x108 + uint8_t RESERVED24[3]; + __IO uint8_t USBTRC0; // 0x10C + uint8_t RESERVED25[7]; + __IO uint8_t USBFRMADJUST; // 0x114 +} USBOTG_TypeDef; + +typedef struct +{ + __I uint8_t SRS0; + __I uint8_t SRS1; + uint8_t RESERVED0[2]; + __IO uint8_t RPFC; + __IO uint8_t RPFW; +} RCM_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ +#define DMA_BASE ((uint32_t)0x40008100) +#define FTFA_BASE ((uint32_t)0x40020000) +#define DMAMUX_BASE ((uint32_t)0x40021000) +#define PIT_BASE ((uint32_t)0x40037000) +#define TPM0_BASE ((uint32_t)0x40038000) +#define TPM1_BASE ((uint32_t)0x40039000) +#define TPM2_BASE ((uint32_t)0x4003A000) +#define ADC0_BASE ((uint32_t)0x4003B000) +#define RTC_BASE ((uint32_t)0x4003D000) +#define DAC0_BASE ((uint32_t)0x4003F000) +#define LPTMR0_BASE ((uint32_t)0x40040000) +#define TSI0_BASE ((uint32_t)0x40045000) +#define SIM_BASE ((uint32_t)0x40047000) +#define PORTA_BASE ((uint32_t)0x40049000) +#define PORTB_BASE ((uint32_t)0x4004A000) +#define PORTC_BASE ((uint32_t)0x4004B000) +#define PORTD_BASE ((uint32_t)0x4004C000) +#define PORTE_BASE ((uint32_t)0x4004D000) +#define MCG_BASE ((uint32_t)0x40064000) +#define OSC0_BASE ((uint32_t)0x40065000) +#define I2C0_BASE ((uint32_t)0x40066000) +#define I2C1_BASE ((uint32_t)0x40067000) +#define UART0_BASE ((uint32_t)0x4006A000) +#define UART1_BASE ((uint32_t)0x4006B000) +#define UART2_BASE ((uint32_t)0x4006C000) +#define USBOTG_BASE ((uint32_t)0x40072000) +#define CMP_BASE ((uint32_t)0x40073000) +#define SPI0_BASE ((uint32_t)0x40076000) +#define SPI1_BASE ((uint32_t)0x40077000) +#define LLWU_BASE ((uint32_t)0x4007C000) +#define PMC_BASE ((uint32_t)0x4007D000) +#define SMC_BASE ((uint32_t)0x4007E000) +#define RCM_BASE ((uint32_t)0x4007F000) +#define GPIOA_BASE ((uint32_t)0x400FF000) +#define GPIOB_BASE ((uint32_t)0x400FF040) +#define GPIOC_BASE ((uint32_t)0x400FF080) +#define GPIOD_BASE ((uint32_t)0x400FF0C0) +#define GPIOE_BASE ((uint32_t)0x400FF100) +#define MCM_BASE ((uint32_t)0xF0003000) + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define FTFA ((FTFA_TypeDef *) FTFA_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define PIT ((PIT_TypeDef *) PIT_BASE) +#define TPM0 ((TPM_TypeDef *) TPM0_BASE) +#define TPM1 ((TPM_TypeDef *) TPM1_BASE) +#define TPM2 ((TPM_TypeDef *) TPM2_BASE) +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define RTC0 ((RTC_TypeDef *) RTC0_BASE) +#define DAC0 ((DAC_TypeDef *) DAC0_BASE) +#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) +#define TSI0 ((TSI_TypeDef *) TSI0_BASE) +#define SIM ((SIM_TypeDef *) SIM_BASE) +#define LLWU ((LLWU_TypeDef *) LLWU_BASE) +#define PMC ((PMC_TypeDef *) PMC_BASE) +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) +#define PORTD ((PORT_TypeDef *) PORTD_BASE) +#define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define USB0 ((USBOTG_TypeDef *) USBOTG_BASE) +#define CMP ((CMP_TypeDef *) CMP_BASE) +#define MCG ((MCG_TypeDef *) MCG_BASE) +#define OSC0 ((OSC_TypeDef *) OSC0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define UART0 ((UARTLP_TypeDef *) UART0_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define SMC ((SMC_TypeDef *) SMC_BASE) +#define RCM ((RCM_TypeDef *) RCM_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define MCM ((MCM_TypeDef *) MCM_BASE) + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ +/********* Bits definition for SIM_SOPT1 register *************/ +#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ +#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ +#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ +#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ +#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ + +/******* Bits definition for SIM_SOPT1CFG register ************/ +#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ +#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ +#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ + +/******* Bits definition for SIM_SOPT2 register ************/ +#define SIM_SOPT2_UART0SRC_SHIFT 26 /*!< UART0 clock source select (shift) */ +#define SIM_SOPT2_UART0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_UART0SRC_SHIFT)) /*!< UART0 clock source select (mask) */ +#define SIM_SOPT2_UART0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_UART0SRC_SHIFT) & SIM_SOPT2_UART0SRC_MASK)) /*!< UART0 clock source select */ +#define SIM_SOPT2_TPMSRC_SHIFT 24 /*!< TPM clock source select (shift) */ +#define SIM_SOPT2_TPMSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_TPMSRC_SHIFT)) /*!< TPM clock source select (mask) */ +#define SIM_SOPT2_TPMSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_TPMSRC_SHIFT) & SIM_SOPT2_TPMSRC_MASK)) /*!< TPM clock source select */ +#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ +#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */ +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 /*!< CLKOUT select (shift) */ +#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x07 << SIM_SOPT2_CLKOUTSEL_SHIFT)) /*!< CLKOUT select (mask) */ +#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) /*!< CLKOUT select */ +#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ + +/******* Bits definition for SIM_SOPT4 register ************/ +#define SIM_SOPT4_TPM2CLKSEL ((uint32_t)0x04000000) /*!< TPM2 External Clock Pin Select */ +#define SIM_SOPT4_TPM1CLKSEL ((uint32_t)0x02000000) /*!< TPM1 External Clock Pin Select */ +#define SIM_SOPT4_TPM0CLKSEL ((uint32_t)0x01000000) /*!< TPM0 External Clock Pin Select */ +#define SIM_SOPT4_TPM2CH0SRC ((uint32_t)0x00100000) /*!< TPM2 channel 0 input capture source select */ +#define SIM_SOPT4_TPM1CH0SRC ((uint32_t)0x00040000) /*!< TPM1 channel 0 input capture source select */ + +/******* Bits definition for SIM_SOPT5 register ************/ +#define SIM_SOPT5_UART2ODE ((uint32_t)0x00040000) /*!< UART2 Open Drain Enable */ +#define SIM_SOPT5_UART1ODE ((uint32_t)0x00020000) /*!< UART1 Open Drain Enable */ +#define SIM_SOPT5_UART0ODE ((uint32_t)0x00010000) /*!< UART0 Open Drain Enable */ +#define SIM_SOPT5_UART1RXSRC ((uint32_t)0x00000040) /*!< UART1 receive data source select */ +#define SIM_SOPT5_UART1TXSRC_SHIFT 4 /*!< UART1 transmit data source select (shift) */ +#define SIM_SOPT5_UART1TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_UART1TXSRC_SHIFT)) /*!< UART1 transmit data source select (mask) */ +#define SIM_SOPT5_UART1TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_UART1TXSRC_SHIFT) & SIM_SOPT5_UART1TXSRC_MASK)) /*!< UART1 transmit data source select */ +#define SIM_SOPT5_UART0RXSRC ((uint32_t)0x00000040) /*!< UART0 receive data source select */ +#define SIM_SOPT5_UART0TXSRC_SHIFT 0 /*!< UART0 transmit data source select (shift) */ +#define SIM_SOPT5_UART0TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_UART0TXSRC_SHIFT)) /*!< UART0 transmit data source select (mask) */ +#define SIM_SOPT5_UART0TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_UART0TXSRC_SHIFT) & SIM_SOPT5_UART0TXSRC_MASK)) /*!< UART0 transmit data source select */ + +/******* Bits definition for SIM_SOPT7 register ************/ +#define SIM_SOPT7_ADC0ALTTRGEN ((uint32_t)0x00000080) /*!< ADC0 Alternate Trigger Enable */ +#define SIM_SOPT7_ADC0PRETRGSEL ((uint32_t)0x00000010) /*!< ADC0 Pretrigger Select */ +#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 /*!< ADC0 Trigger Select (shift) */ +#define SIM_SOPT7_ADC0TRGSEL_MASK ((uint32_t)((uint32_t)0x0F << SIM_SOPT7_ADC0TRGSEL_SHIFT)) /*!< ADC0 Trigger Select (mask) */ +#define SIM_SOPT7_ADC0TRGSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT7_ADC0TRGSEL_SHIFT) & SIM_SOPT7_ADC0TRGSEL_MASK)) /*!< ADC0 Trigger Select */ + +/******** Bits definition for SIM_SDID register ************/ +#define SIM_SDID_FAMID_SHIFT 28 /*!< Kinetis family ID (shift) */ +#define SIM_SDID_FAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_FAMID_SHIFT)) /*!< Kinetis family ID (mask) */ +#define SIM_SDID_SUBFAMID_SHIFT 24 /*!< Kinetis Sub-Family ID (shift) */ +#define SIM_SDID_SUBFAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SUBFAMID_SHIFT)) /*!< Kinetis Sub-Family ID (mask) */ +#define SIM_SDID_SERIESID_SHIFT 20 /*!< Kinetis Series ID (shift) */ +#define SIM_SDID_SERIESID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SERIESID_SHIFT)) /*!< Kinetis Series ID (mask) */ +#define SIM_SDID_SRAMSIZE_SHIFT 16 /*!< System SRAM Size (shift) */ +#define SIM_SDID_SRAMSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SRAMSIZE_SHIFT)) /*!< System SRAM Size (mask) */ +#define SIM_SDID_REVID_SHIFT 12 /*!< Device revision number (shift) */ +#define SIM_SDID_REVID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_REVID_SHIFT)) /*!< Device revision number (mask) */ +#define SIM_SDID_DIEID_SHIFT 7 /*!< Device die number (shift) */ +#define SIM_SDID_DIEID_MASK ((uint32_t)((uint32_t)0x1F << SIM_SDID_DIEID_SHIFT)) /*!< Device die number (mask) */ +#define SIM_SDID_PINID_SHIFT 0 /*!< Pincount identification (shift) */ +#define SIM_SDID_PINID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_PINID_SHIFT)) /*!< Pincount identification (mask) */ + +/******* Bits definition for SIM_SCGC4 register ************/ +#define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) /*!< SPI1 Clock Gate Control */ +#define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) /*!< SPI0 Clock Gate Control */ +#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ +#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ +#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ +#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */ +#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */ +#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */ +#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ + +/******* Bits definition for SIM_SCGC5 register ************/ +#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ +#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ +#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ +#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ +#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ +#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */ +#define SIM_SCGC5_LPTMR ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC6_DAC0 ((uint32_t)0x80000000) /*!< DAC0 Clock Gate Control */ +#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ +#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ +#define SIM_SCGC6_TPM2 ((uint32_t)0x04000000) /*!< TPM2 Clock Gate Control */ +#define SIM_SCGC6_TPM1 ((uint32_t)0x02000000) /*!< TPM1 Clock Gate Control */ +#define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) /*!< TPM0 Clock Gate Control */ +#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ +#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ +#define SIM_SCGC6_FTF ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ + +/******* Bits definition for SIM_SCGC7 register ************/ +#define SIM_SCGC7_DMA ((uint32_t)0x00000100) /*!< DMA Clock Gate Control */ + +/****** Bits definition for SIM_CLKDIV1 register ***********/ +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 /*!< Clock 1 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0x0F << SIM_CLKDIV1_OUTDIV1_SHIFT)) /*!< Clock 1 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) /*!< Clock 1 output divider value */ +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 /*!< Clock 4 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x07 << SIM_CLKDIV1_OUTDIV4_SHIFT)) /*!< Clock 4 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) /*!< Clock 4 output divider value */ + +/******* Bits definition for SIM_FCFG1 register ************/ +#define SIM_FCFG1_PFSIZE_SHIFT 24 /*!< Program Flash Size (shift) */ +#define SIM_FCFG1_PFSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_FCFG1_PFSIZE_SHIFT)) /*!< Program Flash Size (mask) */ +#define SIM_FCFG1_FLASHDOZE ((uint32_t)0x00000002) /*!< Flash Doze */ +#define SIM_FCFG1_FLASHDIS ((uint32_t)0x00000001) /*!< Flash Disable */ + +/******* Bits definition for SIM_FCFG2 register ************/ +#define SIM_FCFG2_MAXADDR0_SHIFT 24 /*!< Max address block (shift) */ +#define SIM_FCFG2_MAXADDR0_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR0_SHIFT)) /*!< Max address block (mask) */ + +/******* Bits definition for SIM_UIDMH register ************/ +#define SIM_UIDMH_UID_MASK ((uint32_t)0x0000FFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDML register ************/ +#define SIM_UIDML_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDL register *************/ +#define SIM_UIDL_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_COPC register *************/ +#define SIM_COPC_COPT_SHIFT 2 /*!< COP Watchdog Timeout (shift) */ +#define SIM_COPC_COPT_MASK ((uint32_t)((uint32_t)0x03 << SIM_COPC_COPT_SHIFT)) /*!< COP Watchdog Timeout (mask) */ +#define SIM_COPC_COPT(x) ((uint32_t)(((uint32_t)(x) << SIM_COPC_COPT_SHIFT) & SIM_COPC_COPT_MASK)) /*!< COP Watchdog Timeout */ +#define SIM_COPC_COPCLKS ((uint32_t)0x00000002) /*!< COP Clock Select */ +#define SIM_COPC_COPW ((uint32_t)0x00000001) /*!< COP windowed mode */ + +/******* Bits definition for SIM_SRVCOP register ***********/ +#define SIM_SRVCOP_SRVCOP_SHIFT 0 /*!< Sevice COP Register (shift) */ +#define SIM_SRVCOP_SRVCOP_MASK ((uint32_t)((uint32_t)0xFF << SIM_SRVCOP_SRVCOP_SHIFT)) /*!< Sevice COP Register (mask) */ +#define SIM_SRVCOP_SRVCOP(x) ((uint32_t)(((uint32_t)(x) << SIM_SRVCOP_SRVCOP_SHIFT) & SIM_SRVCOP_SRVCOP_MASK)) /*!< Sevice COP Register */ + +/****************************************************************/ +/* */ +/* Low-Leakage Wakeup Unit (LLWU) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Port Control and interrupts (PORT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Oscillator (OSC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access (DMA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access Multiplexer (DMAMUX) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Periodic Interrupt Timer (PIT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Analog-to-Digital Converter (ADC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Low-Power Timer (LPTMR) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Touch Sensing Input (TSI) */ +/* */ +/****************************************************************/ +/********** Bits definition for TSIx_GENCS register ***********/ +#define TSIx_GENCS_OUTRGF ((uint32_t)((uint32_t)1 << 31)) /*!< Out of Range Flag */ +#define TSIx_GENCS_ESOR ((uint32_t)((uint32_t)1 << 28)) /*!< End-of-scan/Out-of-Range Interrupt Selection */ +#define TSIx_GENCS_MODE_SHIFT 24 /*!< TSI analog modes setup and status bits (shift) */ +#define TSIx_GENCS_MODE_MASK ((uint32_t)((uint32_t)0x0F << TSIx_GENCS_MODE_SHIFT)) /*!< TSI analog modes setup and status bits (mask) */ +#define TSIx_GENCS_MODE(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_MODE_SHIFT) & TSIx_GENCS_MODE_MASK)) /*!< TSI analog modes setup and status bits */ +#define TSIx_GENCS_REFCHRG_SHIFT 21 /*!< Reference oscillator charge/discharge current (shift) */ +#define TSIx_GENCS_REFCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_REFCHRG_SHIFT)) /*!< Reference oscillator charge/discharge current (mask) */ +#define TSIx_GENCS_REFCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_REFCHRG_SHIFT) & TSIx_GENCS_REFCHRG_MASK)) /*!< Reference oscillator charge/discharge current */ +#define TSIx_GENCS_DVOLT_SHIFT 19 /*!< Oscillator voltage rails (shift) */ +#define TSIx_GENCS_DVOLT_MASK ((uint32_t)((uint32_t)0x03 << TSIx_GENCS_DVOLT_SHIFT)) /*!< Oscillator voltage rails (mask) */ +#define TSIx_GENCS_DVOLT(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_DVOLT_SHIFT) & TSIx_GENCS_DVOLT_MASK)) /*!< Oscillator voltage rails */ +#define TSIx_GENCS_EXTCHRG_SHIFT 16 /*!< Electrode oscillator charge/discharge current (shift) */ +#define TSIx_GENCS_EXTCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_EXTCHRG_SHIFT)) /*!< Electrode oscillator charge/discharge current (mask) */ +#define TSIx_GENCS_EXTCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_EXTCHRG_SHIFT) & TSIx_GENCS_EXTCHRG_MASK)) /*!< Electrode oscillator charge/discharge current */ +#define TSIx_GENCS_PS_SHIFT 13 /*!< Electrode oscillator prescaler (shift) */ +#define TSIx_GENCS_PS_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_PS_SHIFT)) /*!< Electrode oscillator prescaler (mask) */ +#define TSIx_GENCS_PS(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_PS_SHIFT) & TSIx_GENCS_PS_MASK)) /*!< Electrode oscillator prescaler */ +#define TSIx_GENCS_NSCN_SHIFT 8 /*!< Number of scans per electrode minus 1 (shift) */ +#define TSIx_GENCS_NSCN_MASK ((uint32_t)((uint32_t)0x1F << TSIx_GENCS_NSCN_SHIFT)) /*!< Number of scans per electrode minus 1 (mask) */ +#define TSIx_GENCS_NSCN(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_NSCN_SHIFT) & TSIx_GENCS_NSCN_MASK)) /*!< Number of scans per electrode minus 1 */ +#define TSIx_GENCS_TSIEN ((uint32_t)((uint32_t)1 << 7)) /*!< TSI Module Enable */ +#define TSIx_GENCS_TSIIEN ((uint32_t)((uint32_t)1 << 6)) /*!< TSI Interrupt Enable */ +#define TSIx_GENCS_STPE ((uint32_t)((uint32_t)1 << 5)) /*!< TSI STOP Enable */ +#define TSIx_GENCS_STM ((uint32_t)((uint32_t)1 << 4)) /*!< Scan Trigger Mode (0=software; 1=hardware) */ +#define TSIx_GENCS_SCNIP ((uint32_t)((uint32_t)1 << 3)) /*!< Scan in Progress Status */ +#define TSIx_GENCS_EOSF ((uint32_t)((uint32_t)1 << 2)) /*!< End of Scan Flag */ +#define TSIx_GENCS_CURSW ((uint32_t)((uint32_t)1 << 1)) /*!< Swap electrode and reference current sources */ + +/********** Bits definition for TSIx_DATA register ************/ +#define TSIx_DATA_TSICH_SHIFT 28 /*!< Specify channel to be measured (shift) */ +#define TSIx_DATA_TSICH_MASK ((uint32_t)((uint32_t)0x0F << TSIx_DATA_TSICH_SHIFT)) /*!< Specify channel to be measured (mask) */ +#define TSIx_DATA_TSICH(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICH_SHIFT) & TSIx_DATA_TSICH_MASK)) /*!< Specify channel to be measured */ +#define TSIx_DATA_DMAEN ((uint32_t)((uint32_t)1 << 23)) /*!< DMA Transfer Enabled */ +#define TSIx_DATA_SWTS ((uint32_t)((uint32_t)1 << 22)) /*!< Software Trigger Start */ +#define TSIx_DATA_TSICNT_SHIFT 0 /*!< TSI Conversion Counter Value (shift) */ +#define TSIx_DATA_TSICNT_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_DATA_TSICNT_SHIFT)) /*!< TSI Conversion Counter Value (mask) */ +#define TSIx_DATA_TSICNT(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICNT_SHIFT) & TSIx_DATA_TSICNT_MASK)) /*!< TSI Conversion Counter Value */ + +/********** Bits definition for TSIx_TSHD register ************/ +#define TSIx_TSHD_THRESH_SHIFT 16 /*!< TSI Wakeup Channel High-Threshold (shift) */ +#define TSIx_TSHD_THRESH_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESH_SHIFT)) /*!< TSI Wakeup Channel High-Threshold (mask) */ +#define TSIx_TSHD_THRESH(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESH_SHIFT) & TSIx_TSHD_THRESH_MASK)) /*!< TSI Wakeup Channel High-Threshold */ +#define TSIx_TSHD_THRESL_SHIFT 0 /*!< TSI Wakeup Channel Low-Threshold (shift) */ +#define TSIx_TSHD_THRESL_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESL_SHIFT)) /*!< TSI Wakeup Channel Low-Threshold (mask) */ +#define TSIx_TSHD_THRESL(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESL_SHIFT) & TSIx_TSHD_THRESL_MASK)) /*!< TSI Wakeup Channel Low-Threshold */ + +/****************************************************************/ +/* */ +/* Multipurpose Clock Generator (MCG) */ +/* */ +/****************************************************************/ +/*********** Bits definition for MCG_C1 register **************/ +#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */ +#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */ +#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */ +#define MCG_C1_CLKS_FLLPLL MCG_C1_CLKS(0) /*!< Select output of FLL or PLL, depending on PLLS control bit */ +#define MCG_C1_CLKS_IRCLK MCG_C1_CLKS(1) /*!< Select internal reference clock */ +#define MCG_C1_CLKS_ERCLK MCG_C1_CLKS(2) /*!< Select external reference clock */ +#define MCG_C1_FRDIV_SHIFT 3 /*!< FLL External Reference Divider (shift) */ +#define MCG_C1_FRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_C1_FRDIV_SHIFT)) /*!< FLL External Reference Divider (mask) */ +#define MCG_C1_FRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_FRDIV_SHIFT) & MCG_C1_FRDIV_MASK)) /*!< FLL External Reference Divider */ +#define MCG_C1_IREFS ((uint8_t)((uint8_t)1 << 2)) /*!< Internal Reference Select (0=ERCLK; 1=slow IRCLK) */ +#define MCG_C1_IRCLKEN ((uint8_t)((uint8_t)1 << 1)) /*!< Internal Reference Clock Enable */ +#define MCG_C1_IREFSTEN ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Stop Enable */ + +/*********** Bits definition for MCG_C2 register **************/ +#define MCG_C2_LOCRE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Clock Reset Enable */ +#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */ +#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x03 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */ +#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */ +#define MCG_C2_HGO0 ((uint8_t)((uint8_t)1 << 3)) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */ +#define MCG_C2_EREFS0 ((uint8_t)((uint8_t)1 << 2)) /*!< External Reference Select (0=clock; 1=oscillator) */ +#define MCG_C2_LP ((uint8_t)((uint8_t)1 << 1)) /*!< Low Power Select (1=FLL/PLL disabled in bypass modes) */ +#define MCG_C2_IRCS ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Select (0=slow; 1=fast) */ + +/*********** Bits definition for MCG_C3 register **************/ +#define MCG_C3_SCTRIM_SHIFT 0 /*!< Slow Internal Reference Clock Trim Setting (shift) */ +#define MCG_C3_SCTRIM_MASK ((uint8_t)((uint8_t)0xFF << MCG_C3_SCTRIM_SHIFT)) /*!< Slow Internal Reference Clock Trim Setting (mask) */ +#define MCG_C3_SCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C3_SCTRIM_SHIFT) & MCG_C3_SCTRIM_MASK)) /*!< Slow Internal Reference Clock Trim Setting */ + +/*********** Bits definition for MCG_C4 register **************/ +#define MCG_C4_DMX32 ((uint8_t)((uint8_t)1 << 7)) /*!< DCO Maximum Frequency with 32.768 kHz Reference */ +#define MCG_C4_DRST_DRS_SHIFT 5 /*!< DCO Range Select (shift) */ +#define MCG_C4_DRST_DRS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C4_DRST_DRS_SHIFT)) /*!< DCO Range Select (mask) */ +#define MCG_C4_DRST_DRS(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_DRST_DRS_SHIFT) & MCG_C4_DRST_DRS_MASK)) /*!< DCO Range Select */ +#define MCG_C4_FCTRIM_SHIFT 1 /*!< Fast Internal Reference Clock Trim Setting (shift) */ +#define MCG_C4_FCTRIM_MASK ((uint8_t)((uint8_t)0x0F << MCG_C4_FCTRIM_SHIFT)) /*!< Fast Internal Reference Clock Trim Setting (mask) */ +#define MCG_C4_FCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_FCTRIM_SHIFT) & MCG_C4_FCTRIM_MASK)) /*!< Fast Internal Reference Clock Trim Setting */ +#define MCG_C4_SCFTRIM ((uint8_t)((uint8_t)1 << 0)) /*!< Slow Internal Reference Clock Fine Trim */ + +/*********** Bits definition for MCG_C5 register **************/ +#define MCG_C5_PLLCLKEN0 ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Clock Enable */ +#define MCG_C5_PLLSTEN0 ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Stop Enable */ +#define MCG_C5_PRDIV0_SHIFT 0 /*!< PLL External Reference Divider (shift) */ +#define MCG_C5_PRDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C5_PRDIV0_SHIFT)) /*!< PLL External Reference Divider (mask) */ +#define MCG_C5_PRDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C5_PRDIV0_SHIFT) & MCG_C5_PRDIV0_MASK)) /*!< PLL External Reference Divider */ + +/*********** Bits definition for MCG_C6 register **************/ +#define MCG_C6_LOLIE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Interrupt Enable */ +#define MCG_C6_PLLS ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Select */ +#define MCG_C6_CME0 ((uint8_t)((uint8_t)1 << 5)) /*!< Clock Monitor Enable */ +#define MCG_C6_VDIV0_SHIFT 0 /*!< VCO 0 Divider (shift) */ +#define MCG_C6_VDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C6_VDIV0_SHIFT)) /*!< VCO 0 Divider (mask) */ +#define MCG_C6_VDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C6_VDIV0_SHIFT) & MCG_C6_VDIV0_MASK)) /*!< VCO 0 Divider */ + +/************ Bits definition for MCG_S register **************/ +#define MCG_S_LOLS ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Status */ +#define MCG_S_LOCK0 ((uint8_t)((uint8_t)1 << 6)) /*!< Lock Status */ +#define MCG_S_PLLST ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Select Status */ +#define MCG_S_IREFST ((uint8_t)((uint8_t)1 << 4)) /*!< Internal Reference Status */ +#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */ +#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x03 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */ +#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */ +#define MCG_S_CLKST_FLL MCG_S_CLKST(0) /*!< Output of the FLL is selected */ +#define MCG_S_CLKST_IRCLK MCG_S_CLKST(1) /*!< Internal reference clock is selected */ +#define MCG_S_CLKST_ERCLK MCG_S_CLKST(2) /*!< External reference clock is selected */ +#define MCG_S_CLKST_PLL MCG_S_CLKST(3) /*!< Output of the PLL is selected */ +#define MCG_S_OSCINIT0 ((uint8_t)((uint8_t)1 << 1)) /*!< OSC Initialization */ +#define MCG_S_IRCST ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Status */ + +/************ Bits definition for MCG_SC register **************/ +#define MCG_SC_ATME ((uint8_t)((uint8_t)1 << 7)) /*!< Automatic Trim Machine Enable */ +#define MCG_SC_ATMS ((uint8_t)((uint8_t)1 << 6)) /*!< Automatic Trim Machine Select */ +#define MCG_SC_ATMF ((uint8_t)((uint8_t)1 << 5)) /*!< Automatic Trim Machine Fail Flag */ +#define MCG_SC_FLTPRSRV ((uint8_t)((uint8_t)1 << 4) /*!< FLL Filter Preserve Enable */ +#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */ +#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */ +#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */ +#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */ +#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */ +#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */ +#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */ +#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */ +#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */ +#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */ +#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */ +#define MCG_SC_LOCS0 ((uint8_t)((uint8_t)1 << 0) /*!< OSC0 Loss of Clock Status */ + +/*********** Bits definition for MCG_ATCVH register ************/ +#define MCG_ATCVH_ATCVH_SHIFT 0 /*!< MCG Auto Trim Compare Value High Register (shift) */ +#define MCG_ATCVH_ATCVH_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVH_ATCVH_SHIFT)) /*!< MCG Auto Trim Compare Value High Register (mask) */ +#define MCG_ATCVH_ATCVH(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVH_ATCVH_SHIFT) & MCG_ATCVH_ATCVH_MASK)) /*!< MCG Auto Trim Compare Value High Register */ + +/*********** Bits definition for MCG_ATCVL register ************/ +#define MCG_ATCVL_ATCVL_SHIFT 0 /*!< MCG Auto Trim Compare Value Low Register (shift) */ +#define MCG_ATCVL_ATCVL_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVL_ATCVL_SHIFT)) /*!< MCG Auto Trim Compare Value Low Register (mask) */ +#define MCG_ATCVL_ATCVL(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVL_ATCVL_SHIFT) & MCG_ATCVL_ATCVL_MASK)) /*!< MCG Auto Trim Compare Value Low Register */ + +/************ Bits definition for MCG_C7 register **************/ +/* All MCG_C7 bits are reserved on the KL25Z. */ + +/************ Bits definition for MCG_C8 register **************/ +#define MCG_C8_LOLRE ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Loss of Lock Reset Enable */ + +/************ Bits definition for MCG_C9 register **************/ +/* All MCG_C9 bits are reserved on the KL25Z. */ + +/************ Bits definition for MCG_C10 register *************/ +/* All MCG_C10 bits are reserved on the KL25Z. */ + + +/****************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/****************************************************************/ +/*********** Bits definition for SPIx_C1 register *************/ +#define SPIx_C1_SPIE ((uint8_t)0x80) /*!< SPI Interrupt Enable */ +#define SPIx_C1_SPE ((uint8_t)0x40) /*!< SPI System Enable */ +#define SPIx_C1_SPTIE ((uint8_t)0x20) /*!< SPI Transmit Interrupt Enable */ +#define SPIx_C1_MSTR ((uint8_t)0x10) /*!< Master/Slave Mode Select */ +#define SPIx_C1_CPOL ((uint8_t)0x08) /*!< Clock Polarity */ +#define SPIx_C1_CPHA ((uint8_t)0x04) /*!< Clock Phase */ +#define SPIx_C1_SSOE ((uint8_t)0x02) /*!< Slave Select Output Enable */ +#define SPIx_C1_LSBFE ((uint8_t)0x01) /*!< LSB First */ + +/*********** Bits definition for SPIx_C2 register *************/ +#define SPIx_C2_SPMIE ((uint8_t)0x80) /*!< SPI Match Interrupt Enable */ +#define SPIx_C2_TXDMAE ((uint8_t)0x20) /*!< Transmit DMA Enable */ +#define SPIx_C2_MODFEN ((uint8_t)0x10) /*!< Master Mode-Fault Function Enable */ +#define SPIx_C2_BIDIROE ((uint8_t)0x08) /*!< Bidirectional Mode Output Enable */ +#define SPIx_C2_RXDMAE ((uint8_t)0x04) /*!< Receive DMA Enable */ +#define SPIx_C2_SPISWAI ((uint8_t)0x02) /*!< SPI Stop in Wait Mode */ +#define SPIx_C2_SPC0 ((uint8_t)0x01) /*!< SPI Pin Control 0 */ + +/*********** Bits definition for SPIx_BR register *************/ +#define SPIx_BR_SPPR_SHIFT 4 /*!< SPI Baud rate Prescaler Divisor */ +#define SPIx_BR_SPPR_MASK ((uint8_t)((uint8_t)0x7 << SPIx_BR_SPPR_SHIFT)) +#define SPIx_BR_SPPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPPR_SHIFT) & SPIx_BR_SPPR_MASK)) +#define SPIx_BR_SPR_SHIFT 0 /*!< SPI Baud rate Divisor */ +#define SPIx_BR_SPR_MASK ((uint8_t)((uint8_t)0x0F << SPIx_BR_SPR_SHIFT)) +#define SPIx_BR_SPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPR_SHIFT) & SPIx_BR_SPR_MASK)) + +/*********** Bits definition for SPIx_S register **************/ +#define SPIx_S_SPRF ((uint8_t)0x80) /*!< SPI Read Buffer Full Flag */ +#define SPIx_S_SPMF ((uint8_t)0x40) /*!< SPI Match Flag */ +#define SPIx_S_SPTEF ((uint8_t)0x20) /*!< SPI Transmit Buffer Empty Flag */ +#define SPIx_S_MODF ((uint8_t)0x10) /*!< Master Mode Fault Flag */ + +/*********** Bits definition for SPIx_D register **************/ +#define SPIx_D_DATA_SHIFT 0 /*!< Data */ +#define SPIx_D_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_D_DATA_SHIFT)) +#define SPIx_D_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_D_DATA_SHIFT) & SPIx_D_DATA_MASK)) + +/*********** Bits definition for SPIx_M register **************/ +#define SPIx_M_DATA_SHIFT 0 /*!< SPI HW Compare value for Match */ +#define SPIx_M_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_M_DATA_SHIFT)) +#define SPIx_M_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_M_DATA_SHIFT) & SPIx_M_DATA_MASK)) + +/****************************************************************/ +/* */ +/* Inter-Integrated Circuit (I2C): Device dependent part */ +/* */ +/****************************************************************/ +/*********** Bits definition for I2Cx_FLT register ************/ +#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ +#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ +#define I2Cx_FLT_STOPIE ((uint8_t)0x20) /*!< I2C Bus Stop Interrupt Enable */ +#define I2Cx_FLT_FLT_SHIFT 0 /*!< I2C Programmable Filter Factor */ +#define I2Cx_FLT_FLT_MASK ((uint8_t)((uint8_t)0x1F << I2Cx_FLT_FLT_SHIFT)) +#define I2Cx_FLT_FLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_FLT_FLT_SHIFT) & I2Cx_FLT_FLT_MASK)) + +/****************************************************************/ +/* */ +/* Universal Asynchronous Receiver/Transmitter (UART) */ +/* */ +/****************************************************************/ +/********* Bits definition for UARTx_BDH register *************/ +#define UARTx_BDH_LBKDIE ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Enable */ +#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RX Input Active Edge Interrupt Enable */ +#define UARTx_BDH_SBNS ((uint8_t)0x20) /*!< Stop Bit Number Select */ +#define UARTx_BDH_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDH_SBR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_BDH_SBR_SHIFT)) +#define UARTx_BDH_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDH_SBR_SHIFT) & UARTx_BDH_SBR_MASK)) + +/********* Bits definition for UARTx_BDL register *************/ +#define UARTx_BDL_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDL_SBR_MASK ((uint8_t)((uint8_t)0xFF << UARTx_BDL_SBR_SHIFT)) +#define UARTx_BDL_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDL_SBR_SHIFT) & UARTx_BDL_SBR_MASK)) + +/********* Bits definition for UARTx_C1 register **************/ +#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ +#define UARTx_C1_DOZEEN ((uint8_t)0x40) /*!< Doze Enable */ +#define UARTx_C1_UARTSWAI ((uint8_t)0x40) /*!< UART Stops in Wait Mode */ +#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */ +#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */ +#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */ +#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */ +#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */ +#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */ + +/********* Bits definition for UARTx_C2 register **************/ +#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */ +#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */ +#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */ +#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */ +#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */ +#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */ +#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */ +#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */ + +/********* Bits definition for UARTx_S1 register **************/ +#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */ +#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */ +#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */ +#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */ +#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */ +#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */ +#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */ +#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */ + +/********* Bits definition for UARTx_S2 register **************/ +#define UARTx_S2_LBKDIF ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Flag */ +#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */ +#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */ +#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */ +#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */ +#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */ +#define UARTx_S2_LBKDE ((uint8_t)0x02) /*!< LIN Break Detect Enable */ +#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */ + +/********* Bits definition for UARTx_C3 register **************/ +#define UARTx_C3_R8T9 ((uint8_t)0x80) /*!< Receive Bit 8 / Transmit Bit 9 */ +#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */ +#define UARTx_C3_R9T8 ((uint8_t)0x40) /*!< Receive Bit 9 / Transmit Bit 8 */ +#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */ +#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */ +#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */ +#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */ +#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */ +#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */ +#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */ + +/********* Bits definition for UARTx_D register ***************/ +#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ +#define UARTx_D_RT_SHIFT 0 +#define UARTx_D_RT_MASK ((uint8_t)0xFF) + +/********* Bits definition for UARTx_MA1 register *************/ +#define UARTx_MA1_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA1_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA1_MA_SHIFT)) +#define UARTx_MA1_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA1_MA_SHIFT) & UARTx_MA1_MA_MASK)) + +/********* Bits definition for UARTx_MA2 register *************/ +#define UARTx_MA2_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA2_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA2_MA_SHIFT)) +#define UARTx_MA2_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA2_MA_SHIFT) & UARTx_MA2_MA_MASK)) + +/********* Bits definition for UARTx_C4 register **************/ +#define UARTx_C4_TDMAS ((uint8_t)0x80) /*!< Transmitter DMA Select */ +#define UARTx_C4_RDMAS ((uint8_t)0x20) /*!< Receiver Full DMA Select */ +#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ +#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */ +#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */ +#define UARTx_C4_OSR_SHIFT 0 /*!< Over Sampling Ratio */ +#define UARTx_C4_OSR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_C4_OSR_SHIFT)) +#define UARTx_C4_OSR(x) ((uint8_t)(((uint8_t)(x) << UARTx_C4_OSR_SHIFT) & UARTx_C4_OSR_MASK)) + +/********* Bits definition for UARTx_C5 register **************/ +#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */ +#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */ +#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */ +#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */ + +/****************************************************************/ +/* */ +/* Power Management Controller (PMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Timer/PWM Module (TPM) */ +/* */ +/****************************************************************/ +/********** Bits definition for TPMx_SC register ***************/ +#define TPMx_SC_DMA ((uint32_t)0x100) /*!< DMA Enable */ +#define TPMx_SC_TOF ((uint32_t)0x80) /*!< Timer Overflow Flag */ +#define TPMx_SC_TOIE ((uint32_t)0x40) /*!< Timer Overflow Interrupt Enable */ +#define TPMx_SC_CPWMS ((uint32_t)0x20) /*!< Center-aligned PWM Select */ +#define TPMx_SC_CMOD_SHIFT 3 /*!< Clock Mode Selection */ +#define TPMx_SC_CMOD_MASK ((uint32_t)((uint32_t)0x3 << TPMx_SC_CMOD_SHIFT)) +#define TPMx_SC_CMOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_CMOD_SHIFT) & TPMx_SC_CMOD_MASK)) +#define TPMx_SC_PS_SHIFT 0 /*!< Prescale Factor Selection */ +#define TPMx_SC_PS_MASK ((uint32_t)((uint32_t)0x7 << TPMx_SC_PS_SHIFT)) +#define TPMx_SC_PS(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_PS_SHIFT) & TPMx_SC_PS_MASK)) + +#define TPMx_SC_CMOD_DISABLE TPMx_SC_CMOD(0) +#define TPMx_SC_CMOD_LPTPM_CLK TPMx_SC_CMOD(1) +#define TPMx_SC_CMOD_LPTPM_EXTCLK TPMx_SC_CMOD(2) + +/********** Bits definition for TPMx_CNT register **************/ +#define TPMx_CNT_COUNT_SHIFT 0 /*!< Counter Value */ +#define TPMx_CNT_COUNT_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CNT_COUNT_SHIFT)) +#define TPMx_CNT_COUNT(x) ((uint32_t)(((uint32_t)(x) << TPMx_CNT_COUNT_SHIFT) & TPMx_CNT_COUNT_MASK)) + +/********** Bits definition for TPMx_MOD register **************/ +#define TPMx_MOD_MOD_SHIFT 0 /*!< Modulo Value */ +#define TPMx_MOD_MOD_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_MOD_MOD_SHIFT)) +#define TPMx_MOD_MOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_MOD_MOD_SHIFT) & TPMx_MOD_MOD_MASK)) + +/********** Bits definition for TPMx_CnSC register *************/ +#define TPMx_CnSC_CHF ((uint32_t)0x80) /*!< Channel Flag */ +#define TPMx_CnSC_CHIE ((uint32_t)0x40) /*!< Channel Interrupt Enable */ +#define TPMx_CnSC_MSB ((uint32_t)0x20) /*!< Channel Mode Select */ +#define TPMx_CnSC_MSA ((uint32_t)0x10) /*!< Channel Mode Select */ +#define TPMx_CnSC_ELSB ((uint32_t)0x8) /*!< Edge or Level Select */ +#define TPMx_CnSC_ELSA ((uint32_t)0x4) /*!< Edge or Level Select */ +#define TPMx_CnSC_DMA ((uint32_t)0x1) /*!< DMA Enable */ + +/********** Bits definition for TPMx_CnV register **************/ +#define TPMx_CnV_VAL_SHIFT 0 /*!< Channel Value */ +#define TPMx_CnV_VAL_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CnV_VAL_SHIFT)) +#define TPMx_CnV_VAL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CnV_VAL_SHIFT) & TPMx_CnV_VAL_MASK)) + +/********* Bits definition for TPMx_STATUS register ************/ +#define TPMx_STATUS_TOF ((uint32_t)0x100) /*!< Timer Overflow Flag */ +#define TPMx_STATUS_CH5F ((uint32_t)0x20) /*!< Channel 5 Flag */ +#define TPMx_STATUS_CH4F ((uint32_t)0x10) /*!< Channel 4 Flag */ +#define TPMx_STATUS_CH3F ((uint32_t)0x8) /*!< Channel 3 Flag */ +#define TPMx_STATUS_CH2F ((uint32_t)0x4) /*!< Channel 2 Flag */ +#define TPMx_STATUS_CH1F ((uint32_t)0x2) /*!< Channel 1 Flag */ +#define TPMx_STATUS_CH0F ((uint32_t)0x1) /*!< Channel 0 Flag */ + +/********** Bits definition for TPMx_CONF register *************/ +#define TPMx_CONF_TRGSEL_SHIFT 24 /*!< Trigger Select */ +#define TPMx_CONF_TRGSEL_MASK ((uint32_t)((uint32_t)0xF << TPMx_CONF_TRGSEL_SHIFT)) +#define TPMx_CONF_TRGSEL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_TRGSEL_SHIFT) & TPMx_CONF_TRGSEL_MASK)) +#define TPMx_CONF_CROT ((uint32_t)0x40000) /*!< Counter Reload On Trigger */ +#define TPMx_CONF_CSOO ((uint32_t)0x20000) /*!< Counter Stop On Overflow */ +#define TPMx_CONF_CSOT ((uint32_t)0x10000) /*!< Counter Start on Trigger */ +#define TPMx_CONF_GTBEEN ((uint32_t)0x200) /*!< Global time base enable */ +#define TPMx_CONF_DBGMODE_SHIFT 6 /*!< Debug Mode */ +#define TPMx_CONF_DBGMODE_MASK ((uint32_t)((uint32_t)0x3 << TPMx_CONF_DBGMODE_SHIFT)) +#define TPMx_CONF_DBGMODE(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_DBGMODE_SHIFT) & TPMx_CONF_DBGMODE_MASK)) +#define TPMx_CONF_DOZEEN ((uint32_t)0x20) /*!< Doze Enable */ + +#define TPMx_CONF_DBGMODE_CONT TPMx_CONF_DBGMODE(3) +#define TPMx_CONF_DBGMODE_PAUSE TPMx_CONF_DBGMODE(0) + +/****************************************************************/ +/* */ +/* USB OTG: device dependent parts */ +/* */ +/****************************************************************/ +/******** Bits definition for USBx_ADDINFO register ***********/ +#define USBx_ADDINFO_IRQNUM_SHIFT 6 /*!< Assigned Interrupt Request Number */ +#define USBx_ADDINFO_IRQNUM_MASK ((uint8_t)((uint8_t)0x1F << USBx_ADDINFO_IRQNUM_SHIFT)) + +/******** Bits definition for USBx_OTGISTAT register **********/ +#define USBx_OTGISTAT_IDCHG ((uint8_t)0x80) /*!< Change in the ID Signal from the USB connector is sensed. */ +#define USBx_OTGISTAT_ONEMSEC ((uint8_t)0x40) /*!< Set when the 1 millisecond timer expires. */ +#define USBx_OTGISTAT_LINE_STATE_CHG ((uint8_t)0x20) /*!< Set when the USB line state changes. */ +#define USBx_OTGISTAT_SESSVLDCHG ((uint8_t)0x08) /*!< Set when a change in VBUS is detected indicating a session valid or a session no longer valid. */ +#define USBx_OTGISTAT_B_SESS_CHG ((uint8_t)0x04) /*!< Set when a change in VBUS is detected on a B device. */ +#define USBx_OTGISTAT_AVBUSCHG ((uint8_t)0x01) /*!< Set when a change in VBUS is detected on an A device. */ + +/******** Bits definition for USBx_OTGICR register ************/ +#define USBx_OTGICR_IDEN ((uint8_t)0x80) /*!< ID Interrupt Enable */ +#define USBx_OTGICR_ONEMSECEN ((uint8_t)0x40) /*!< One Millisecond Interrupt Enable */ +#define USBx_OTGICR_LINESTATEEN ((uint8_t)0x20) /*!< Line State Change Interrupt Enable */ +#define USBx_OTGICR_SESSVLDEN ((uint8_t)0x08) /*!< Session Valid Interrupt Enable */ +#define USBx_OTGICR_BSESSEN ((uint8_t)0x04) /*!< B Session END Interrupt Enable */ +#define USBx_OTGICR_AVBUSEN ((uint8_t)0x01) /*!< A VBUS Valid Interrupt Enable */ + +/******** Bits definition for USBx_OTGSTAT register ***********/ +#define USBx_OTGSTAT_ID ((uint8_t)0x80) /*!< Indicates the current state of the ID pin on the USB connector */ +#define USBx_OTGSTAT_ONEMSECEN ((uint8_t)0x40) /*!< This bit is reserved for the 1ms count, but it is not useful to software. */ +#define USBx_OTGSTAT_LINESTATESTABLE ((uint8_t)0x20) /*!< Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 millisecond. */ +#define USBx_OTGSTAT_SESS_VLD ((uint8_t)0x08) /*!< Session Valid */ +#define USBx_OTGSTAT_BSESSEND ((uint8_t)0x04) /*!< B Session End */ +#define USBx_OTGSTAT_AVBUSVLD ((uint8_t)0x01) /*!< A VBUS Valid */ + +/******** Bits definition for USBx_OTGCTL register ************/ +#define USBx_OTGCTL_DPLOW ((uint8_t)0x20) /*!< D+ Data Line pull-down resistor enable */ +#define USBx_OTGCTL_DMLOW ((uint8_t)0x10) /*!< D– Data Line pull-down resistor enable */ +#define USBx_OTGCTL_OTGEN ((uint8_t)0x04) /*!< On-The-Go pullup/pulldown resistor enable */ + +/******** Bits definition for USBx_ISTAT register *************/ +#define USBx_ISTAT_ATTACH ((uint8_t)0x40) /*!< Attach interrupt */ + +/******** Bits definition for USBx_INTEN register ***************/ +#define USBx_INTEN_ATTACHEN ((uint8_t)0x40) /*!< ATTACH interrupt enable */ + +/******** Bits definition for USBx_CTL register *****************/ +#define USBx_CTL_RESET ((uint8_t)0x10) /*!< Generates an USB reset signal (host mode) */ +#define USBx_CTL_HOSTMODEEN ((uint8_t)0x08) /*!< Operate in Host mode */ +#define USBx_CTL_RESUME ((uint8_t)0x04) /*!< Executes resume signaling */ + +/******** Bits definition for USBx_ADDR register ****************/ +#define USBx_ADDR_LSEN ((uint8_t)0x80) /*!< Low Speed Enable bit */ + +/******** Bits definition for USBx_TOKEN register ***************/ +#define USBx_TOKEN_TOKENPID_SHIFT 4 /*!< Contains the token type executed by the USB module. */ +#define USBx_TOKEN_TOKENPID_MASK ((uint8_t)((uint8_t)0x0F << USBx_TOKEN_TOKENPID_SHIFT)) +#define USBx_TOKEN_TOKENPID(x) ((uint8_t)(((uint8_t)(x) << USBx_TOKEN_TOKENPID_SHIFT) & USBx_TOKEN_TOKENPID_MASK)) +#define USBx_TOKEN_TOKENENDPT_SHIFT 0 /*!< Holds the Endpoint address for the token command. */ +#define USBx_TOKEN_TOKENENDPT_MASK ((uint8_t)((uint8_t)0x0F << USBx_TOKEN_TOKENENDPT_SHIFT)) +#define USBx_TOKEN_TOKENENDPT(x) ((uint8_t)(((uint8_t)(x) << USBx_TOKEN_TOKENENDPT_SHIFT) & USBx_TOKEN_TOKENENDPT_MASK)) +#define USBx_TOKEN_TOKENPID_OUT 0x1 +#define USBx_TOKEN_TOKENPID_IN 0x9 +#define USBx_TOKEN_TOKENPID_SETUP 0xD + +/******** Bits definition for USBx_ENDPTn register **************/ +#define USBx_ENDPTn_HOSTWOHUB ((uint8_t)0x80) +#define USBx_ENDPTn_RETRYDIS ((uint8_t)0x40) + +/****************************************************************/ +/* */ +/* Reset Control Module (RCM) */ +/* */ +/****************************************************************/ + +/* Only device independent parts */ + +/****************************************************************/ +/* */ +/* System Mode Controller (SMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Digital-to-Analog Converter (DAC) */ +/* */ +/****************************************************************/ + +/* Mostly Device independent */ + +#define DACx_C1_DACBFMD_SHIFT 2 /*!< DAC Buffer Work Mode Select */ +#define DACx_C1_DACBFMD_MASK ((uint8_t)((uint8_t)0x01 << DACx_C1_DACBFMD_ SHIFT)) +#define DACx_C1_DACBFMD(x) ((uint8_t)(((uint8_t)(x) << DACx_C1_DACBFMD_SHIFT) & DACx_C1_DACBFMD_MASK)) + +#define DACx_C1_DACBFMD_MODE_NORMAL 0 +#define DACx_C1_DACBFMD_MODE_OTS 1 + +/****************************************************************/ +/* */ +/* Real Time Clock (RTC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Comparator (CMP) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Flash Memory Module (FTFA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +#endif /* _KL25Z_H_ */ diff --git a/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl26z.h b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl26z.h new file mode 100644 index 0000000..eefcfd6 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl26z.h @@ -0,0 +1,1169 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _KL26Z_H_ +#define _KL26Z_H_ + +/** + * @brief KL2x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __MPU_PRESENT 0 +#define __VTOR_PRESENT 1 +#define __NVIC_PRIO_BITS 2 +#define __Vendor_SysTickConfig 0 + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ****************/ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + +/****** KL2x Specific Interrupt Numbers ***********************/ + DMA0_IRQn = 0, + DMA1_IRQn = 1, + DMA2_IRQn = 2, + DMA3_IRQn = 3, + Reserved0_IRQn = 4, + FTFA_IRQn = 5, + PMC_IRQn = 6, + LLWU_IRQn = 7, + I2C0_IRQn = 8, + I2C1_IRQn = 9, + SPI0_IRQn = 10, + SPI1_IRQn = 11, + UART0_IRQn = 12, + UART1_IRQn = 13, + UART2_IRQn = 14, + ADC0_IRQn = 15, + CMP0_IRQn = 16, + TPM0_IRQn = 17, + TPM1_IRQn = 18, + TPM2_IRQn = 19, + RTC0_IRQn = 20, + RTC1_IRQn = 21, + PIT_IRQn = 22, + I2S0_IRQn = 23, + USB_OTG_IRQn = 24, + DAC0_IRQn = 25, + TSI0_IRQn = 26, + MCG_IRQn = 27, + LPTMR0_IRQn = 28, + Reserved2_IRQn = 29, + PINA_IRQn = 30, + PINCD_IRQn = 31, +} IRQn_Type; + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +typedef struct +{ + __IO uint8_t C1; + __IO uint8_t C2; + __IO uint8_t C3; + __IO uint8_t C4; + __IO uint8_t C5; + __IO uint8_t C6; + __I uint8_t S; + uint8_t RESERVED0[1]; + __IO uint8_t SC; + uint8_t RESERVED1[1]; + __IO uint8_t ATCVH; + __IO uint8_t ATCVL; + __IO uint8_t C7; + __IO uint8_t C8; + __IO uint8_t C9; + __IO uint8_t C10; +} MCG_TypeDef; + +typedef struct +{ + __IO uint32_t SC; + __IO uint32_t CNT; + __IO uint32_t MOD; + struct { // Channels + __IO uint32_t SC; + __IO uint32_t V; + } C[6]; + uint32_t RESERVED0[5]; + __IO uint32_t STATUS; + uint32_t RESERVED1[12]; + __IO uint32_t CONF; +} TPM_TypeDef; + +typedef struct +{ + __IO uint32_t GENCS; + __IO uint32_t DATA; + __IO uint32_t TSHD; +} TSI_TypeDef; + +typedef struct +{ + __IO uint8_t S; + __IO uint8_t BR; + __IO uint8_t C2; + __IO uint8_t C1; + __IO uint8_t ML; + __IO uint8_t MH; + __IO uint8_t DL; + __IO uint8_t DH; + uint8_t RESERVED0[2]; + __IO uint8_t CI; + __IO uint8_t C3; +} SPI_TypeDef; + +typedef struct +{ + __IO uint8_t A1; + __IO uint8_t F; + __IO uint8_t C1; + __IO uint8_t S; /* Denoted 'S1' in datasheet. */ + __IO uint8_t D; + __IO uint8_t C2; + __IO uint8_t FLT; + __IO uint8_t RA; + __IO uint8_t SMB; + __IO uint8_t A2; + __IO uint8_t SLTH; + __IO uint8_t SLTL; +} I2C_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __I uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t C4; +} UART_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __IO uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t MA1; + __IO uint8_t MA2; + __IO uint8_t C4; + __IO uint8_t C5; +} UARTLP_TypeDef; + +typedef struct { + __I uint8_t PERID; // 0x00 + uint8_t RESERVED0[3]; + __I uint8_t IDCOMP; // 0x04 + uint8_t RESERVED1[3]; + __I uint8_t REV; // 0x08 + uint8_t RESERVED2[3]; + __I uint8_t ADDINFO; // 0x0C + uint8_t RESERVED3[3]; + __IO uint8_t OTGISTAT; // 0x10 + uint8_t RESERVED4[3]; + __IO uint8_t OTGICR; // 0x14 + uint8_t RESERVED5[3]; + __IO uint8_t OTGSTAT; // 0x18 + uint8_t RESERVED6[3]; + __IO uint8_t OTGCTL; // 0x1C + uint8_t RESERVED7[99]; + __IO uint8_t ISTAT; // 0x80 + uint8_t RESERVED8[3]; + __IO uint8_t INTEN; // 0x84 + uint8_t RESERVED9[3]; + __IO uint8_t ERRSTAT; // 0x88 + uint8_t RESERVED10[3]; + __IO uint8_t ERREN; // 0x8C + uint8_t RESERVED11[3]; + __I uint8_t STAT; // 0x90 + uint8_t RESERVED12[3]; + __IO uint8_t CTL; // 0x94 + uint8_t RESERVED13[3]; + __IO uint8_t ADDR; // 0x98 + uint8_t RESERVED14[3]; + __IO uint8_t BDTPAGE1; // 0x9C + uint8_t RESERVED15[3]; + __IO uint8_t FRMNUML; // 0xA0 + uint8_t RESERVED16[3]; + __IO uint8_t FRMNUMH; // 0xA4 + uint8_t RESERVED17[3]; + __IO uint8_t TOKEN; // 0xA8 + uint8_t RESERVED18[3]; + __IO uint8_t SOFTHLD; // 0xAC + uint8_t RESERVED19[3]; + __IO uint8_t BDTPAGE2; // 0xB0 + uint8_t RESERVED20[3]; + __IO uint8_t BDTPAGE3; // 0xB4 + uint8_t RESERVED21[11]; + struct { + __IO uint8_t V; // 0xC0 + uint8_t RESERVED[3]; + } ENDPT[16]; + __IO uint8_t USBCTRL; // 0x100 + uint8_t RESERVED22[3]; + __I uint8_t OBSERVE; // 0x104 + uint8_t RESERVED23[3]; + __IO uint8_t CONTROL; // 0x108 + uint8_t RESERVED24[3]; + __IO uint8_t USBTRC0; // 0x10C + uint8_t RESERVED25[7]; + __IO uint8_t USBFRMADJUST; // 0x114 +} USBOTG_TypeDef; + +typedef struct +{ + __I uint8_t SRS0; + __I uint8_t SRS1; + uint8_t RESERVED0[2]; + __IO uint8_t RPFC; + __IO uint8_t RPFW; +} RCM_TypeDef; + +typedef struct { + __IO uint32_t TCSR; // 0x00 + uint32_t RESERVED0[1]; + __IO uint32_t TCR2; // 0x08 + __IO uint32_t TCR3; // 0x0C + __IO uint32_t TCR4; // 0x10 + __IO uint32_t TCR5; // 0x14 + uint32_t RESERVED1[2]; + __O uint32_t TDR0; // 0x20 + uint32_t RESERVED2[15]; + __IO uint32_t TMR; // 0x60 + uint32_t RESERVED3[7]; + __IO uint32_t RCSR; // 0x80 + uint32_t RESERVED4[1]; + __IO uint32_t RCR2; // 0x88 + __IO uint32_t RCR3; // 0x8C + __IO uint32_t RCR4; // 0x90 + __IO uint32_t RCR5; // 0x94 + uint32_t RESERVED5[2]; + __I uint32_t RDR0; // 0xA0 + uint32_t RESERVED6[15]; + __IO uint32_t RMR; // 0xE0 + uint32_t RESERVED7[7]; + __IO uint32_t MCR; // 0x100 +} I2S_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ +#define DMA_BASE ((uint32_t)0x40008100) +#define FTFA_BASE ((uint32_t)0x40020000) +#define DMAMUX_BASE ((uint32_t)0x40021000) +#define I2S0_BASE ((uint32_t)0x4002F000) // TODO: registers not implemented +#define PIT_BASE ((uint32_t)0x40037000) +#define TPM0_BASE ((uint32_t)0x40038000) +#define TPM1_BASE ((uint32_t)0x40039000) +#define TPM2_BASE ((uint32_t)0x4003A000) +#define ADC0_BASE ((uint32_t)0x4003B000) +#define RTC_BASE ((uint32_t)0x4003D000) +#define DAC0_BASE ((uint32_t)0x4003F000) +#define LPTMR0_BASE ((uint32_t)0x40040000) +#define TSI0_BASE ((uint32_t)0x40045000) +#define SIM_BASE ((uint32_t)0x40047000) +#define PORTA_BASE ((uint32_t)0x40049000) +#define PORTB_BASE ((uint32_t)0x4004A000) +#define PORTC_BASE ((uint32_t)0x4004B000) +#define PORTD_BASE ((uint32_t)0x4004C000) +#define PORTE_BASE ((uint32_t)0x4004D000) +#define MCG_BASE ((uint32_t)0x40064000) +#define OSC0_BASE ((uint32_t)0x40065000) +#define I2C0_BASE ((uint32_t)0x40066000) +#define I2C1_BASE ((uint32_t)0x40067000) +#define UART0_BASE ((uint32_t)0x4006A000) +#define UART1_BASE ((uint32_t)0x4006B000) +#define UART2_BASE ((uint32_t)0x4006C000) +#define USBOTG_BASE ((uint32_t)0x40072000) +#define CMP_BASE ((uint32_t)0x40073000) +#define SPI0_BASE ((uint32_t)0x40076000) +#define SPI1_BASE ((uint32_t)0x40077000) +#define LLWU_BASE ((uint32_t)0x4007C000) +#define PMC_BASE ((uint32_t)0x4007D000) +#define SMC_BASE ((uint32_t)0x4007E000) +#define RCM_BASE ((uint32_t)0x4007F000) +#define GPIOA_BASE ((uint32_t)0x400FF000) +#define GPIOB_BASE ((uint32_t)0x400FF040) +#define GPIOC_BASE ((uint32_t)0x400FF080) +#define GPIOD_BASE ((uint32_t)0x400FF0C0) +#define GPIOE_BASE ((uint32_t)0x400FF100) +#define MCM_BASE ((uint32_t)0xF0003000) + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define FTFA ((FTFA_TypeDef *) FTFA_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define I2S0 ((I2S_TypeDef *) I2S0_BASE) +#define PIT ((PIT_TypeDef *) PIT_BASE) +#define TPM0 ((TPM_TypeDef *) TPM0_BASE) +#define TPM1 ((TPM_TypeDef *) TPM1_BASE) +#define TPM2 ((TPM_TypeDef *) TPM2_BASE) +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define RTC0 ((RTC_TypeDef *) RTC0_BASE) +#define DAC0 ((DAC_TypeDef *) DAC0_BASE) +#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) +#define TSI0 ((TSI_TypeDef *) TSI0_BASE) +#define SIM ((SIM_TypeDef *) SIM_BASE) +#define LLWU ((LLWU_TypeDef *) LLWU_BASE) +#define PMC ((PMC_TypeDef *) PMC_BASE) +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) +#define PORTD ((PORT_TypeDef *) PORTD_BASE) +#define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define USB0 ((USBOTG_TypeDef *) USBOTG_BASE) +#define CMP ((CMP_TypeDef *) CMP_BASE) +#define MCG ((MCG_TypeDef *) MCG_BASE) +#define OSC0 ((OSC_TypeDef *) OSC0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define UART0 ((UARTLP_TypeDef *) UART0_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define SMC ((SMC_TypeDef *) SMC_BASE) +#define RCM ((RCM_TypeDef *) RCM_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define MCM ((MCM_TypeDef *) MCM_BASE) + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ +/********* Bits definition for SIM_SOPT1 register *************/ +#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ +#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ +#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ +#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ +#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ + +/******* Bits definition for SIM_SOPT1CFG register ************/ +#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ +#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ +#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ + +/******* Bits definition for SIM_SOPT2 register ************/ +#define SIM_SOPT2_UART0SRC_SHIFT 26 /*!< UART0 clock source select (shift) */ +#define SIM_SOPT2_UART0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_UART0SRC_SHIFT)) /*!< UART0 clock source select (mask) */ +#define SIM_SOPT2_UART0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_UART0SRC_SHIFT) & SIM_SOPT2_UART0SRC_MASK)) /*!< UART0 clock source select */ +#define SIM_SOPT2_TPMSRC_SHIFT 24 /*!< TPM clock source select (shift) */ +#define SIM_SOPT2_TPMSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_TPMSRC_SHIFT)) /*!< TPM clock source select (mask) */ +#define SIM_SOPT2_TPMSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_TPMSRC_SHIFT) & SIM_SOPT2_TPMSRC_MASK)) /*!< TPM clock source select */ +#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ +#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */ +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 /*!< CLKOUT select (shift) */ +#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x07 << SIM_SOPT2_CLKOUTSEL_SHIFT)) /*!< CLKOUT select (mask) */ +#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) /*!< CLKOUT select */ +#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ + +/******* Bits definition for SIM_SOPT4 register ************/ +#define SIM_SOPT4_TPM2CLKSEL ((uint32_t)0x04000000) /*!< TPM2 External Clock Pin Select */ +#define SIM_SOPT4_TPM1CLKSEL ((uint32_t)0x02000000) /*!< TPM1 External Clock Pin Select */ +#define SIM_SOPT4_TPM0CLKSEL ((uint32_t)0x01000000) /*!< TPM0 External Clock Pin Select */ +#define SIM_SOPT4_TPM2CH0SRC ((uint32_t)0x00100000) /*!< TPM2 channel 0 input capture source select */ +#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18 /*!< TPM1 channel 0 input capture source select (shift) */ +#define SIM_SOPT4_TPM1CH0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT4_TPM1CH0SRC_SHIFT)) /*!< TPM1 channel 0 input capture source select (mask) */ +#define SIM_SOPT4_TPM1CH0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT4_TPM1CH0SRC_SHIFT) & SIM_SOPT4_TPM1CH0SRC_MASK)) /*!< TPM1 channel 0 input capture source select */ + +/******* Bits definition for SIM_SOPT5 register ************/ +#define SIM_SOPT5_UART2ODE ((uint32_t)0x00040000) /*!< UART2 Open Drain Enable */ +#define SIM_SOPT5_UART1ODE ((uint32_t)0x00020000) /*!< UART1 Open Drain Enable */ +#define SIM_SOPT5_UART0ODE ((uint32_t)0x00010000) /*!< UART0 Open Drain Enable */ +#define SIM_SOPT5_UART1RXSRC ((uint32_t)0x00000040) /*!< UART1 receive data source select */ +#define SIM_SOPT5_UART1TXSRC_SHIFT 4 /*!< UART1 transmit data source select (shift) */ +#define SIM_SOPT5_UART1TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_UART1TXSRC_SHIFT)) /*!< UART1 transmit data source select (mask) */ +#define SIM_SOPT5_UART1TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_UART1TXSRC_SHIFT) & SIM_SOPT5_UART1TXSRC_MASK)) /*!< UART1 transmit data source select */ +#define SIM_SOPT5_UART0RXSRC ((uint32_t)0x00000040) /*!< UART0 receive data source select */ +#define SIM_SOPT5_UART0TXSRC_SHIFT 0 /*!< UART0 transmit data source select (shift) */ +#define SIM_SOPT5_UART0TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_UART0TXSRC_SHIFT)) /*!< UART0 transmit data source select (mask) */ +#define SIM_SOPT5_UART0TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_UART0TXSRC_SHIFT) & SIM_SOPT5_UART0TXSRC_MASK)) /*!< UART0 transmit data source select */ + +/******* Bits definition for SIM_SOPT7 register ************/ +#define SIM_SOPT7_ADC0ALTTRGEN ((uint32_t)0x00000080) /*!< ADC0 Alternate Trigger Enable */ +#define SIM_SOPT7_ADC0PRETRGSEL ((uint32_t)0x00000010) /*!< ADC0 Pretrigger Select */ +#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 /*!< ADC0 Trigger Select (shift) */ +#define SIM_SOPT7_ADC0TRGSEL_MASK ((uint32_t)((uint32_t)0x0F << SIM_SOPT7_ADC0TRGSEL_SHIFT)) /*!< ADC0 Trigger Select (mask) */ +#define SIM_SOPT7_ADC0TRGSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT7_ADC0TRGSEL_SHIFT) & SIM_SOPT7_ADC0TRGSEL_MASK)) /*!< ADC0 Trigger Select */ + +/******** Bits definition for SIM_SDID register ************/ +#define SIM_SDID_FAMID_SHIFT 28 /*!< Kinetis family ID (shift) */ +#define SIM_SDID_FAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_FAMID_SHIFT)) /*!< Kinetis family ID (mask) */ +#define SIM_SDID_SUBFAMID_SHIFT 24 /*!< Kinetis Sub-Family ID (shift) */ +#define SIM_SDID_SUBFAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SUBFAMID_SHIFT)) /*!< Kinetis Sub-Family ID (mask) */ +#define SIM_SDID_SERIESID_SHIFT 20 /*!< Kinetis Series ID (shift) */ +#define SIM_SDID_SERIESID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SERIESID_SHIFT)) /*!< Kinetis Series ID (mask) */ +#define SIM_SDID_SRAMSIZE_SHIFT 16 /*!< System SRAM Size (shift) */ +#define SIM_SDID_SRAMSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SRAMSIZE_SHIFT)) /*!< System SRAM Size (mask) */ +#define SIM_SDID_REVID_SHIFT 12 /*!< Device revision number (shift) */ +#define SIM_SDID_REVID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_REVID_SHIFT)) /*!< Device revision number (mask) */ +#define SIM_SDID_DIEID_SHIFT 7 /*!< Device die number (shift) */ +#define SIM_SDID_DIEID_MASK ((uint32_t)((uint32_t)0x1F << SIM_SDID_DIEID_SHIFT)) /*!< Device die number (mask) */ +#define SIM_SDID_PINID_SHIFT 0 /*!< Pincount identification (shift) */ +#define SIM_SDID_PINID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_PINID_SHIFT)) /*!< Pincount identification (mask) */ + +/******* Bits definition for SIM_SCGC4 register ************/ +#define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) /*!< SPI1 Clock Gate Control */ +#define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) /*!< SPI0 Clock Gate Control */ +#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ +#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ +#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ +#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */ +#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */ +#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */ +#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ + +/******* Bits definition for SIM_SCGC5 register ************/ +#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ +#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ +#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ +#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ +#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ +#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */ +#define SIM_SCGC5_LPTMR ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC6_DAC0 ((uint32_t)0x80000000) /*!< DAC0 Clock Gate Control */ +#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ +#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ +#define SIM_SCGC6_TPM2 ((uint32_t)0x04000000) /*!< TPM2 Clock Gate Control */ +#define SIM_SCGC6_TPM1 ((uint32_t)0x02000000) /*!< TPM1 Clock Gate Control */ +#define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) /*!< TPM0 Clock Gate Control */ +#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ +#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< I2S0 Clock Gate Control */ +#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ +#define SIM_SCGC6_FTF ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ + +/******* Bits definition for SIM_SCGC7 register ************/ +#define SIM_SCGC7_DMA ((uint32_t)0x00000100) /*!< DMA Clock Gate Control */ + +/****** Bits definition for SIM_CLKDIV1 register ***********/ +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 /*!< Clock 1 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0x0F << SIM_CLKDIV1_OUTDIV1_SHIFT)) /*!< Clock 1 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) /*!< Clock 1 output divider value */ +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 /*!< Clock 4 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x07 << SIM_CLKDIV1_OUTDIV4_SHIFT)) /*!< Clock 4 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) /*!< Clock 4 output divider value */ + +/******* Bits definition for SIM_FCFG1 register ************/ +#define SIM_FCFG1_PFSIZE_SHIFT 24 /*!< Program Flash Size (shift) */ +#define SIM_FCFG1_PFSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_FCFG1_PFSIZE_SHIFT)) /*!< Program Flash Size (mask) */ +#define SIM_FCFG1_FLASHDOZE ((uint32_t)0x00000002) /*!< Flash Doze */ +#define SIM_FCFG1_FLASHDIS ((uint32_t)0x00000001) /*!< Flash Disable */ + +/******* Bits definition for SIM_FCFG2 register ************/ +#define SIM_FCFG2_MAXADDR0_SHIFT 24 /*!< Max address lock (shift) */ +#define SIM_FCFG2_MAXADDR0_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR0_SHIFT)) /*!< Max address lock (mask) */ +#define SIM_FCFG2_MAXADDR1_SHIFT 16 /*!< Max address lock (block 1) (shift) */ +#define SIM_FCFG2_MAXADDR1_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR1_SHIFT)) /*!< Max address lock (block 1) (mask) */ + +/******* Bits definition for SIM_UIDMH register ************/ +#define SIM_UIDMH_UID_MASK ((uint32_t)0x0000FFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDML register ************/ +#define SIM_UIDML_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDL register *************/ +#define SIM_UIDL_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_COPC register *************/ +#define SIM_COPC_COPT_SHIFT 2 /*!< COP Watchdog Timeout (shift) */ +#define SIM_COPC_COPT_MASK ((uint32_t)((uint32_t)0x03 << SIM_COPC_COPT_SHIFT)) /*!< COP Watchdog Timeout (mask) */ +#define SIM_COPC_COPT(x) ((uint32_t)(((uint32_t)(x) << SIM_COPC_COPT_SHIFT) & SIM_COPC_COPT_MASK)) /*!< COP Watchdog Timeout */ +#define SIM_COPC_COPCLKS ((uint32_t)0x00000002) /*!< COP Clock Select */ +#define SIM_COPC_COPW ((uint32_t)0x00000001) /*!< COP windowed mode */ + +/******* Bits definition for SIM_SRVCOP register ***********/ +#define SIM_SRVCOP_SRVCOP_SHIFT 0 /*!< Sevice COP Register (shift) */ +#define SIM_SRVCOP_SRVCOP_MASK ((uint32_t)((uint32_t)0xFF << SIM_SRVCOP_SRVCOP_SHIFT)) /*!< Sevice COP Register (mask) */ +#define SIM_SRVCOP_SRVCOP(x) ((uint32_t)(((uint32_t)(x) << SIM_SRVCOP_SRVCOP_SHIFT) & SIM_SRVCOP_SRVCOP_MASK)) /*!< Sevice COP Register */ + + +/****************************************************************/ +/* */ +/* Low-Leakage Wakeup Unit (LLWU) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Port Control and interrupts (PORT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Oscillator (OSC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access (DMA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access Multiplexer (DMAMUX) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Periodic Interrupt Timer (PIT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Analog-to-Digital Converter (ADC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Low-Power Timer (LPTMR) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Touch Sensing Input (TSI) */ +/* */ +/****************************************************************/ +/********** Bits definition for TSIx_GENCS register ***********/ +#define TSIx_GENCS_OUTRGF ((uint32_t)((uint32_t)1 << 31)) /*!< Out of Range Flag */ +#define TSIx_GENCS_ESOR ((uint32_t)((uint32_t)1 << 28)) /*!< End-of-scan/Out-of-Range Interrupt Selection */ +#define TSIx_GENCS_MODE_SHIFT 24 /*!< TSI analog modes setup and status bits (shift) */ +#define TSIx_GENCS_MODE_MASK ((uint32_t)((uint32_t)0x0F << TSIx_GENCS_MODE_SHIFT)) /*!< TSI analog modes setup and status bits (mask) */ +#define TSIx_GENCS_MODE(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_MODE_SHIFT) & TSIx_GENCS_MODE_MASK)) /*!< TSI analog modes setup and status bits */ +#define TSIx_GENCS_REFCHRG_SHIFT 21 /*!< Reference oscillator charge/discharge current (shift) */ +#define TSIx_GENCS_REFCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_REFCHRG_SHIFT)) /*!< Reference oscillator charge/discharge current (mask) */ +#define TSIx_GENCS_REFCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_REFCHRG_SHIFT) & TSIx_GENCS_REFCHRG_MASK)) /*!< Reference oscillator charge/discharge current */ +#define TSIx_GENCS_DVOLT_SHIFT 19 /*!< Oscillator voltage rails (shift) */ +#define TSIx_GENCS_DVOLT_MASK ((uint32_t)((uint32_t)0x03 << TSIx_GENCS_DVOLT_SHIFT)) /*!< Oscillator voltage rails (mask) */ +#define TSIx_GENCS_DVOLT(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_DVOLT_SHIFT) & TSIx_GENCS_DVOLT_MASK)) /*!< Oscillator voltage rails */ +#define TSIx_GENCS_EXTCHRG_SHIFT 16 /*!< Electrode oscillator charge/discharge current (shift) */ +#define TSIx_GENCS_EXTCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_EXTCHRG_SHIFT)) /*!< Electrode oscillator charge/discharge current (mask) */ +#define TSIx_GENCS_EXTCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_EXTCHRG_SHIFT) & TSIx_GENCS_EXTCHRG_MASK)) /*!< Electrode oscillator charge/discharge current */ +#define TSIx_GENCS_PS_SHIFT 13 /*!< Electrode oscillator prescaler (shift) */ +#define TSIx_GENCS_PS_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_PS_SHIFT)) /*!< Electrode oscillator prescaler (mask) */ +#define TSIx_GENCS_PS(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_PS_SHIFT) & TSIx_GENCS_PS_MASK)) /*!< Electrode oscillator prescaler */ +#define TSIx_GENCS_NSCN_SHIFT 8 /*!< Number of scans per electrode minus 1 (shift) */ +#define TSIx_GENCS_NSCN_MASK ((uint32_t)((uint32_t)0x1F << TSIx_GENCS_NSCN_SHIFT)) /*!< Number of scans per electrode minus 1 (mask) */ +#define TSIx_GENCS_NSCN(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_NSCN_SHIFT) & TSIx_GENCS_NSCN_MASK)) /*!< Number of scans per electrode minus 1 */ +#define TSIx_GENCS_TSIEN ((uint32_t)((uint32_t)1 << 7)) /*!< TSI Module Enable */ +#define TSIx_GENCS_TSIIEN ((uint32_t)((uint32_t)1 << 6)) /*!< TSI Interrupt Enable */ +#define TSIx_GENCS_STPE ((uint32_t)((uint32_t)1 << 5)) /*!< TSI STOP Enable */ +#define TSIx_GENCS_STM ((uint32_t)((uint32_t)1 << 4)) /*!< Scan Trigger Mode (0=software; 1=hardware) */ +#define TSIx_GENCS_SCNIP ((uint32_t)((uint32_t)1 << 3)) /*!< Scan in Progress Status */ +#define TSIx_GENCS_EOSF ((uint32_t)((uint32_t)1 << 2)) /*!< End of Scan Flag */ +#define TSIx_GENCS_CURSW ((uint32_t)((uint32_t)1 << 1)) /*!< Swap electrode and reference current sources */ + +/********** Bits definition for TSIx_DATA register ************/ +#define TSIx_DATA_TSICH_SHIFT 28 /*!< Specify channel to be measured (shift) */ +#define TSIx_DATA_TSICH_MASK ((uint32_t)((uint32_t)0x0F << TSIx_DATA_TSICH_SHIFT)) /*!< Specify channel to be measured (mask) */ +#define TSIx_DATA_TSICH(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICH_SHIFT) & TSIx_DATA_TSICH_MASK)) /*!< Specify channel to be measured */ +#define TSIx_DATA_DMAEN ((uint32_t)((uint32_t)1 << 23)) /*!< DMA Transfer Enabled */ +#define TSIx_DATA_SWTS ((uint32_t)((uint32_t)1 << 22)) /*!< Software Trigger Start */ +#define TSIx_DATA_TSICNT_SHIFT 0 /*!< TSI Conversion Counter Value (shift) */ +#define TSIx_DATA_TSICNT_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_DATA_TSICNT_SHIFT)) /*!< TSI Conversion Counter Value (mask) */ +#define TSIx_DATA_TSICNT(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICNT_SHIFT) & TSIx_DATA_TSICNT_MASK)) /*!< TSI Conversion Counter Value */ + +/********** Bits definition for TSIx_TSHD register ************/ +#define TSIx_TSHD_THRESH_SHIFT 16 /*!< TSI Wakeup Channel High-Threshold (shift) */ +#define TSIx_TSHD_THRESH_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESH_SHIFT)) /*!< TSI Wakeup Channel High-Threshold (mask) */ +#define TSIx_TSHD_THRESH(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESH_SHIFT) & TSIx_TSHD_THRESH_MASK)) /*!< TSI Wakeup Channel High-Threshold */ +#define TSIx_TSHD_THRESL_SHIFT 0 /*!< TSI Wakeup Channel Low-Threshold (shift) */ +#define TSIx_TSHD_THRESL_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESL_SHIFT)) /*!< TSI Wakeup Channel Low-Threshold (mask) */ +#define TSIx_TSHD_THRESL(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESL_SHIFT) & TSIx_TSHD_THRESL_MASK)) /*!< TSI Wakeup Channel Low-Threshold */ + +/****************************************************************/ +/* */ +/* Multipurpose Clock Generator (MCG) */ +/* */ +/****************************************************************/ +/*********** Bits definition for MCG_C1 register **************/ +#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */ +#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */ +#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */ +#define MCG_C1_CLKS_FLLPLL MCG_C1_CLKS(0) /*!< Select output of FLL or PLL, depending on PLLS control bit */ +#define MCG_C1_CLKS_IRCLK MCG_C1_CLKS(1) /*!< Select internal reference clock */ +#define MCG_C1_CLKS_ERCLK MCG_C1_CLKS(2) /*!< Select external reference clock */ +#define MCG_C1_FRDIV_SHIFT 3 /*!< FLL External Reference Divider (shift) */ +#define MCG_C1_FRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_C1_FRDIV_SHIFT)) /*!< FLL External Reference Divider (mask) */ +#define MCG_C1_FRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_FRDIV_SHIFT) & MCG_C1_FRDIV_MASK)) /*!< FLL External Reference Divider */ +#define MCG_C1_IREFS ((uint8_t)((uint8_t)1 << 2)) /*!< Internal Reference Select (0=ERCLK; 1=slow IRCLK) */ +#define MCG_C1_IRCLKEN ((uint8_t)((uint8_t)1 << 1)) /*!< Internal Reference Clock Enable */ +#define MCG_C1_IREFSTEN ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Stop Enable */ + +/*********** Bits definition for MCG_C2 register **************/ +#define MCG_C2_LOCRE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Clock Reset Enable */ +#define MCG_C2_FCFTRIM ((uint8_t)((uint8_t)1 << 6)) /*!< Loss of Clock Reset Enable */ +#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */ +#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x03 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */ +#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */ +#define MCG_C2_HGO0 ((uint8_t)((uint8_t)1 << 3)) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */ +#define MCG_C2_EREFS0 ((uint8_t)((uint8_t)1 << 2)) /*!< External Reference Select (0=clock; 1=oscillator) */ +#define MCG_C2_LP ((uint8_t)((uint8_t)1 << 1)) /*!< Low Power Select (1=FLL/PLL disabled in bypass modes) */ +#define MCG_C2_IRCS ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Select (0=slow; 1=fast) */ + +/*********** Bits definition for MCG_C3 register **************/ +#define MCG_C3_SCTRIM_SHIFT 0 /*!< Slow Internal Reference Clock Trim Setting (shift) */ +#define MCG_C3_SCTRIM_MASK ((uint8_t)((uint8_t)0xFF << MCG_C3_SCTRIM_SHIFT)) /*!< Slow Internal Reference Clock Trim Setting (mask) */ +#define MCG_C3_SCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C3_SCTRIM_SHIFT) & MCG_C3_SCTRIM_MASK)) /*!< Slow Internal Reference Clock Trim Setting */ + +/*********** Bits definition for MCG_C4 register **************/ +#define MCG_C4_DMX32 ((uint8_t)((uint8_t)1 << 7)) /*!< DCO Maximum Frequency with 32.768 kHz Reference */ +#define MCG_C4_DRST_DRS_SHIFT 5 /*!< DCO Range Select (shift) */ +#define MCG_C4_DRST_DRS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C4_DRST_DRS_SHIFT)) /*!< DCO Range Select (mask) */ +#define MCG_C4_DRST_DRS(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_DRST_DRS_SHIFT) & MCG_C4_DRST_DRS_MASK)) /*!< DCO Range Select */ +#define MCG_C4_FCTRIM_SHIFT 1 /*!< Fast Internal Reference Clock Trim Setting (shift) */ +#define MCG_C4_FCTRIM_MASK ((uint8_t)((uint8_t)0x0F << MCG_C4_FCTRIM_SHIFT)) /*!< Fast Internal Reference Clock Trim Setting (mask) */ +#define MCG_C4_FCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_FCTRIM_SHIFT) & MCG_C4_FCTRIM_MASK)) /*!< Fast Internal Reference Clock Trim Setting */ +#define MCG_C4_SCFTRIM ((uint8_t)((uint8_t)1 << 0)) /*!< Slow Internal Reference Clock Fine Trim */ + +/*********** Bits definition for MCG_C5 register **************/ +#define MCG_C5_PLLCLKEN0 ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Clock Enable */ +#define MCG_C5_PLLSTEN0 ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Stop Enable */ +#define MCG_C5_PRDIV0_SHIFT 0 /*!< PLL External Reference Divider (shift) */ +#define MCG_C5_PRDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C5_PRDIV0_SHIFT)) /*!< PLL External Reference Divider (mask) */ +#define MCG_C5_PRDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C5_PRDIV0_SHIFT) & MCG_C5_PRDIV0_MASK)) /*!< PLL External Reference Divider */ + +/*********** Bits definition for MCG_C6 register **************/ +#define MCG_C6_LOLIE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Interrupt Enable */ +#define MCG_C6_PLLS ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Select */ +#define MCG_C6_CME0 ((uint8_t)((uint8_t)1 << 5)) /*!< Clock Monitor Enable */ +#define MCG_C6_VDIV0_SHIFT 0 /*!< VCO 0 Divider (shift) */ +#define MCG_C6_VDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C6_VDIV0_SHIFT)) /*!< VCO 0 Divider (mask) */ +#define MCG_C6_VDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C6_VDIV0_SHIFT) & MCG_C6_VDIV0_MASK)) /*!< VCO 0 Divider */ + +/************ Bits definition for MCG_S register **************/ +#define MCG_S_LOLS ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Status */ +#define MCG_S_LOCK0 ((uint8_t)((uint8_t)1 << 6)) /*!< Lock Status */ +#define MCG_S_PLLST ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Select Status */ +#define MCG_S_IREFST ((uint8_t)((uint8_t)1 << 4)) /*!< Internal Reference Status */ +#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */ +#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x03 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */ +#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */ +#define MCG_S_CLKST_FLL MCG_S_CLKST(0) /*!< Output of the FLL is selected */ +#define MCG_S_CLKST_IRCLK MCG_S_CLKST(1) /*!< Internal reference clock is selected */ +#define MCG_S_CLKST_ERCLK MCG_S_CLKST(2) /*!< External reference clock is selected */ +#define MCG_S_CLKST_PLL MCG_S_CLKST(3) /*!< Output of the PLL is selected */ +#define MCG_S_OSCINIT0 ((uint8_t)((uint8_t)1 << 1)) /*!< OSC Initialization */ +#define MCG_S_IRCST ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Status */ + +/************ Bits definition for MCG_SC register **************/ +#define MCG_SC_ATME ((uint8_t)((uint8_t)1 << 7)) /*!< Automatic Trim Machine Enable */ +#define MCG_SC_ATMS ((uint8_t)((uint8_t)1 << 6)) /*!< Automatic Trim Machine Select */ +#define MCG_SC_ATMF ((uint8_t)((uint8_t)1 << 5)) /*!< Automatic Trim Machine Fail Flag */ +#define MCG_SC_FLTPRSRV ((uint8_t)((uint8_t)1 << 4) /*!< FLL Filter Preserve Enable */ +#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */ +#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */ +#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */ +#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */ +#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */ +#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */ +#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */ +#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */ +#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */ +#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */ +#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */ +#define MCG_SC_LOCS0 ((uint8_t)((uint8_t)1 << 0) /*!< OSC0 Loss of Clock Status */ + +/*********** Bits definition for MCG_ATCVH register ************/ +#define MCG_ATCVH_ATCVH_SHIFT 0 /*!< MCG Auto Trim Compare Value High Register (shift) */ +#define MCG_ATCVH_ATCVH_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVH_ATCVH_SHIFT)) /*!< MCG Auto Trim Compare Value High Register (mask) */ +#define MCG_ATCVH_ATCVH(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVH_ATCVH_SHIFT) & MCG_ATCVH_ATCVH_MASK)) /*!< MCG Auto Trim Compare Value High Register */ + +/*********** Bits definition for MCG_ATCVL register ************/ +#define MCG_ATCVL_ATCVL_SHIFT 0 /*!< MCG Auto Trim Compare Value Low Register (shift) */ +#define MCG_ATCVL_ATCVL_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVL_ATCVL_SHIFT)) /*!< MCG Auto Trim Compare Value Low Register (mask) */ +#define MCG_ATCVL_ATCVL(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVL_ATCVL_SHIFT) & MCG_ATCVL_ATCVL_MASK)) /*!< MCG Auto Trim Compare Value Low Register */ + +/************ Bits definition for MCG_C7 register **************/ +#define MCG_C7_OSCSEL ((uint8_t)((uint8_t)1 << 0) + +/************ Bits definition for MCG_C8 register **************/ +#define MCG_C8_LOLRE ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Loss of Lock Reset Enable */ + +/************ Bits definition for MCG_C9 register **************/ +/* All MCG_C9 bits are reserved on the KL26Z. */ + +/************ Bits definition for MCG_C10 register *************/ +/* All MCG_C10 bits are reserved on the KL26Z. */ + + +/****************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/****************************************************************/ + +/*********** Bits definition for SPIx_S register **************/ +#define SPIx_S_SPRF ((uint8_t)0x80) /*!< SPI Read Buffer Full Flag */ +#define SPIx_S_SPMF ((uint8_t)0x40) /*!< SPI Match Flag */ +#define SPIx_S_SPTEF ((uint8_t)0x20) /*!< SPI Transmit Buffer Empty Flag */ +#define SPIx_S_MODF ((uint8_t)0x10) /*!< Master Mode Fault Flag */ +#define SPIx_S_RNFULLF ((uint8_t)0x08) /*!< Receive FIFO nearly full flag */ +#define SPIx_S_TNEAREF ((uint8_t)0x04) /*!< Transmit FIFO nearly empty flag */ +#define SPIx_S_TXFULLF ((uint8_t)0x02) /*!< Transmit FIFO full flag */ +#define SPIx_S_RFIFOEF ((uint8_t)0x01) /*!< SPI read FIFO empty flag */ + +/*********** Bits definition for SPIx_BR register *************/ +#define SPIx_BR_SPPR_SHIFT 4 /*!< SPI Baud rate Prescaler Divisor */ +#define SPIx_BR_SPPR_MASK ((uint8_t)((uint8_t)0x7 << SPIx_BR_SPPR_SHIFT)) +#define SPIx_BR_SPPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPPR_SHIFT) & SPIx_BR_SPPR_MASK)) +#define SPIx_BR_SPR_SHIFT 0 /*!< SPI Baud rate Divisor */ +#define SPIx_BR_SPR_MASK ((uint8_t)((uint8_t)0x0F << SPIx_BR_SPR_SHIFT)) +#define SPIx_BR_SPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPR_SHIFT) & SPIx_BR_SPR_MASK)) + +/*********** Bits definition for SPIx_C2 register *************/ +#define SPIx_C2_SPMIE ((uint8_t)0x80) /*!< SPI Match Interrupt Enable */ +#define SPIx_C2_SPIMODE ((uint8_t)0x40) /*!< SPI 8-bit or 16-bit mode */ +#define SPIx_C2_TXDMAE ((uint8_t)0x20) /*!< Transmit DMA Enable */ +#define SPIx_C2_MODFEN ((uint8_t)0x10) /*!< Master Mode-Fault Function Enable */ +#define SPIx_C2_BIDIROE ((uint8_t)0x08) /*!< Bidirectional Mode Output Enable */ +#define SPIx_C2_RXDMAE ((uint8_t)0x04) /*!< Receive DMA Enable */ +#define SPIx_C2_SPISWAI ((uint8_t)0x02) /*!< SPI Stop in Wait Mode */ +#define SPIx_C2_SPC0 ((uint8_t)0x01) /*!< SPI Pin Control 0 */ + +/*********** Bits definition for SPIx_C1 register *************/ +#define SPIx_C1_SPIE ((uint8_t)0x80) /*!< SPI Interrupt Enable */ +#define SPIx_C1_SPE ((uint8_t)0x40) /*!< SPI System Enable */ +#define SPIx_C1_SPTIE ((uint8_t)0x20) /*!< SPI Transmit Interrupt Enable */ +#define SPIx_C1_MSTR ((uint8_t)0x10) /*!< Master/Slave Mode Select */ +#define SPIx_C1_CPOL ((uint8_t)0x08) /*!< Clock Polarity */ +#define SPIx_C1_CPHA ((uint8_t)0x04) /*!< Clock Phase */ +#define SPIx_C1_SSOE ((uint8_t)0x02) /*!< Slave Select Output Enable */ +#define SPIx_C1_LSBFE ((uint8_t)0x01) /*!< LSB First */ + +/*********** Bits definition for SPIx_ML register *************/ +#define SPIx_ML_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - low byte */ +#define SPIx_ML_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_ML_DATA_SHIFT)) +#define SPIx_ML_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_ML_DATA_SHIFT) & SPIx_ML_DATA_MASK)) + +/*********** Bits definition for SPIx_MH register *************/ +#define SPIx_MH_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - high byte */ +#define SPIx_MH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_MH_DATA_SHIFT)) +#define SPIx_MH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_MH_DATA_SHIFT) & SPIx_MH_DATA_MASK)) + +/*********** Bits definition for SPIx_DL register *************/ +#define SPIx_DL_DATA_SHIFT 0 /*!< Data - low byte */ +#define SPIx_DL_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DL_DATA_SHIFT)) +#define SPIx_DL_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DL_DATA_SHIFT) & SPIx_DL_DATA_MASK)) + +/*********** Bits definition for SPIx_DH register *************/ +#define SPIx_DH_DATA_SHIFT 0 /*!< Data - high byte */ +#define SPIx_DH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DH_DATA_SHIFT)) +#define SPIx_DH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DH_DATA_SHIFT) & SPIx_DH_DATA_MASK)) + +/*********** Bits definition for SPIx_CI register *************/ +#define SPIx_CI_TXFERR ((uint8_t)0x80) /*!< Transmit FIFO error flag */ +#define SPIx_CI_RXFERR ((uint8_t)0x40) /*!< Receive FIFO error flag */ +#define SPIx_CI_TXFOF ((uint8_t)0x20) /*!< Transmit FIFO overflow flag */ +#define SPIx_CI_RXFOF ((uint8_t)0x10) /*!< Receive FIFO overflow flag */ +#define SPIx_CI_TNEAREFCI ((uint8_t)0x08) /*!< Transmit FIFO nearly empty flag clear interrupt */ +#define SPIx_CI_RNFULLFCI ((uint8_t)0x04) /*!< Receive FIFO nearly full flag clear interrupt */ +#define SPIx_CI_SPTEFCI ((uint8_t)0x02) /*!< Transmit FIFO empty flag clear interrupt */ +#define SPIx_CI_SPRFCI ((uint8_t)0x01) /*!< Receive FIFO full flag clear interrupt */ + +/*********** Bits definition for SPIx_C3 register *************/ +#define SPIx_C3_TNEAREF_MARK ((uint8_t)0x20) /*!< Transmit FIFO nearly empty watermark */ +#define SPIx_C3_RNFULLF_MARK ((uint8_t)0x10) /*!< Receive FIFO nearly full watermark */ +#define SPIx_C3_INTCLR ((uint8_t)0x08) /*!< Interrupt clearing mechanism select */ +#define SPIx_C3_TNEARIEN ((uint8_t)0x04) /*!< Transmit FIFO nearly empty interrupt enable */ +#define SPIx_C3_RNFULLIEN ((uint8_t)0x02) /*!< Receive FIFO nearly full interrupt enable */ +#define SPIx_C3_FIFOMODE ((uint8_t)0x01) /*!< FIFO mode enable */ + +/****************************************************************/ +/* */ +/* Inter-Integrated Circuit (I2C): Device dependent part */ +/* */ +/****************************************************************/ +/*********** Bits definition for I2Cx_FLT register ************/ +#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ +#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ +#define I2Cx_FLT_STOPIE ((uint8_t)0x20) /*!< I2C Bus Stop Interrupt Enable */ +#define I2Cx_FLT_FLT_SHIFT 0 /*!< I2C Programmable Filter Factor */ +#define I2Cx_FLT_FLT_MASK ((uint8_t)((uint8_t)0x1F << I2Cx_FLT_FLT_SHIFT)) +#define I2Cx_FLT_FLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_FLT_FLT_SHIFT) & I2Cx_FLT_FLT_MASK)) + +/****************************************************************/ +/* */ +/* Universal Asynchronous Receiver/Transmitter (UART) */ +/* */ +/****************************************************************/ +/********* Bits definition for UARTx_BDH register *************/ +#define UARTx_BDH_LBKDIE ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Enable */ +#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RX Input Active Edge Interrupt Enable */ +#define UARTx_BDH_SBNS ((uint8_t)0x20) /*!< Stop Bit Number Select */ +#define UARTx_BDH_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDH_SBR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_BDH_SBR_SHIFT)) +#define UARTx_BDH_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDH_SBR_SHIFT) & UARTx_BDH_SBR_MASK)) + +/********* Bits definition for UARTx_BDL register *************/ +#define UARTx_BDL_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDL_SBR_MASK ((uint8_t)((uint8_t)0xFF << UARTx_BDL_SBR_SHIFT)) +#define UARTx_BDL_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDL_SBR_SHIFT) & UARTx_BDL_SBR_MASK)) + +/********* Bits definition for UARTx_C1 register **************/ +#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ +#define UARTx_C1_DOZEEN ((uint8_t)0x40) /*!< Doze Enable */ +#define UARTx_C1_UARTSWAI ((uint8_t)0x40) /*!< UART Stops in Wait Mode */ +#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */ +#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */ +#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */ +#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */ +#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */ +#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */ + +/********* Bits definition for UARTx_C2 register **************/ +#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */ +#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */ +#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */ +#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */ +#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */ +#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */ +#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */ +#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */ + +/********* Bits definition for UARTx_S1 register **************/ +#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */ +#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */ +#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */ +#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */ +#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */ +#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */ +#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */ +#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */ + +/********* Bits definition for UARTx_S2 register **************/ +#define UARTx_S2_LBKDIF ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Flag */ +#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */ +#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */ +#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */ +#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */ +#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */ +#define UARTx_S2_LBKDE ((uint8_t)0x02) /*!< LIN Break Detect Enable */ +#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */ + +/********* Bits definition for UARTx_C3 register **************/ +#define UARTx_C3_R8T9 ((uint8_t)0x80) /*!< Receive Bit 8 / Transmit Bit 9 */ +#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */ +#define UARTx_C3_R9T8 ((uint8_t)0x40) /*!< Receive Bit 9 / Transmit Bit 8 */ +#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */ +#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */ +#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */ +#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */ +#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */ +#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */ +#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */ + +/********* Bits definition for UARTx_D register ***************/ +#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ +#define UARTx_D_RT_SHIFT 0 +#define UARTx_D_RT_MASK ((uint8_t)0xFF) + +/********* Bits definition for UARTx_MA1 register *************/ +#define UARTx_MA1_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA1_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA1_MA_SHIFT)) +#define UARTx_MA1_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA1_MA_SHIFT) & UARTx_MA1_MA_MASK)) + +/********* Bits definition for UARTx_MA2 register *************/ +#define UARTx_MA2_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA2_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA2_MA_SHIFT)) +#define UARTx_MA2_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA2_MA_SHIFT) & UARTx_MA2_MA_MASK)) + +/********* Bits definition for UARTx_C4 register **************/ +#define UARTx_C4_TDMAS ((uint8_t)0x80) /*!< Transmitter DMA Select */ +#define UARTx_C4_RDMAS ((uint8_t)0x20) /*!< Receiver Full DMA Select */ +#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ +#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */ +#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */ +#define UARTx_C4_OSR_SHIFT 0 /*!< Over Sampling Ratio */ +#define UARTx_C4_OSR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_C4_OSR_SHIFT)) +#define UARTx_C4_OSR(x) ((uint8_t)(((uint8_t)(x) << UARTx_C4_OSR_SHIFT) & UARTx_C4_OSR_MASK)) + +/********* Bits definition for UARTx_C5 register **************/ +#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */ +#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */ +#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */ +#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */ + +/****************************************************************/ +/* */ +/* Power Management Controller (PMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Timer/PWM Module (TPM) */ +/* */ +/****************************************************************/ +/********** Bits definition for TPMx_SC register ***************/ +#define TPMx_SC_DMA ((uint32_t)0x100) /*!< DMA Enable */ +#define TPMx_SC_TOF ((uint32_t)0x80) /*!< Timer Overflow Flag */ +#define TPMx_SC_TOIE ((uint32_t)0x40) /*!< Timer Overflow Interrupt Enable */ +#define TPMx_SC_CPWMS ((uint32_t)0x20) /*!< Center-aligned PWM Select */ +#define TPMx_SC_CMOD_SHIFT 3 /*!< Clock Mode Selection */ +#define TPMx_SC_CMOD_MASK ((uint32_t)((uint32_t)0x3 << TPMx_SC_CMOD_SHIFT)) +#define TPMx_SC_CMOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_CMOD_SHIFT) & TPMx_SC_CMOD_MASK)) +#define TPMx_SC_PS_SHIFT 0 /*!< Prescale Factor Selection */ +#define TPMx_SC_PS_MASK ((uint32_t)((uint32_t)0x7 << TPMx_SC_PS_SHIFT)) +#define TPMx_SC_PS(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_PS_SHIFT) & TPMx_SC_PS_MASK)) + +#define TPMx_SC_CMOD_DISABLE TPMx_SC_CMOD(0) +#define TPMx_SC_CMOD_LPTPM_CLK TPMx_SC_CMOD(1) +#define TPMx_SC_CMOD_LPTPM_EXTCLK TPMx_SC_CMOD(2) + +/********** Bits definition for TPMx_CNT register **************/ +#define TPMx_CNT_COUNT_SHIFT 0 /*!< Counter Value */ +#define TPMx_CNT_COUNT_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CNT_COUNT_SHIFT)) +#define TPMx_CNT_COUNT(x) ((uint32_t)(((uint32_t)(x) << TPMx_CNT_COUNT_SHIFT) & TPMx_CNT_COUNT_MASK)) + +/********** Bits definition for TPMx_MOD register **************/ +#define TPMx_MOD_MOD_SHIFT 0 /*!< Modulo Value */ +#define TPMx_MOD_MOD_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_MOD_MOD_SHIFT)) +#define TPMx_MOD_MOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_MOD_MOD_SHIFT) & TPMx_MOD_MOD_MASK)) + +/********** Bits definition for TPMx_CnSC register *************/ +#define TPMx_CnSC_CHF ((uint32_t)0x80) /*!< Channel Flag */ +#define TPMx_CnSC_CHIE ((uint32_t)0x40) /*!< Channel Interrupt Enable */ +#define TPMx_CnSC_MSB ((uint32_t)0x20) /*!< Channel Mode Select */ +#define TPMx_CnSC_MSA ((uint32_t)0x10) /*!< Channel Mode Select */ +#define TPMx_CnSC_ELSB ((uint32_t)0x8) /*!< Edge or Level Select */ +#define TPMx_CnSC_ELSA ((uint32_t)0x4) /*!< Edge or Level Select */ +#define TPMx_CnSC_DMA ((uint32_t)0x1) /*!< DMA Enable */ + +/********** Bits definition for TPMx_CnV register **************/ +#define TPMx_CnV_VAL_SHIFT 0 /*!< Channel Value */ +#define TPMx_CnV_VAL_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CnV_VAL_SHIFT)) +#define TPMx_CnV_VAL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CnV_VAL_SHIFT) & TPMx_CnV_VAL_MASK)) + +/********* Bits definition for TPMx_STATUS register ************/ +#define TPMx_STATUS_TOF ((uint32_t)0x100) /*!< Timer Overflow Flag */ +#define TPMx_STATUS_CH5F ((uint32_t)0x20) /*!< Channel 5 Flag */ +#define TPMx_STATUS_CH4F ((uint32_t)0x10) /*!< Channel 4 Flag */ +#define TPMx_STATUS_CH3F ((uint32_t)0x8) /*!< Channel 3 Flag */ +#define TPMx_STATUS_CH2F ((uint32_t)0x4) /*!< Channel 2 Flag */ +#define TPMx_STATUS_CH1F ((uint32_t)0x2) /*!< Channel 1 Flag */ +#define TPMx_STATUS_CH0F ((uint32_t)0x1) /*!< Channel 0 Flag */ + +/********** Bits definition for TPMx_CONF register *************/ +#define TPMx_CONF_TRGSEL_SHIFT 24 /*!< Trigger Select */ +#define TPMx_CONF_TRGSEL_MASK ((uint32_t)((uint32_t)0xF << TPMx_CONF_TRGSEL_SHIFT)) +#define TPMx_CONF_TRGSEL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_TRGSEL_SHIFT) & TPMx_CONF_TRGSEL_MASK)) +#define TPMx_CONF_CROT ((uint32_t)0x40000) /*!< Counter Reload On Trigger */ +#define TPMx_CONF_CSOO ((uint32_t)0x20000) /*!< Counter Stop On Overflow */ +#define TPMx_CONF_CSOT ((uint32_t)0x10000) /*!< Counter Start on Trigger */ +#define TPMx_CONF_GTBEEN ((uint32_t)0x200) /*!< Global time base enable */ +#define TPMx_CONF_DBGMODE_SHIFT 6 /*!< Debug Mode */ +#define TPMx_CONF_DBGMODE_MASK ((uint32_t)((uint32_t)0x3 << TPMx_CONF_DBGMODE_SHIFT)) +#define TPMx_CONF_DBGMODE(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_DBGMODE_SHIFT) & TPMx_CONF_DBGMODE_MASK)) +#define TPMx_CONF_DOZEEN ((uint32_t)0x20) /*!< Doze Enable */ + +/****************************************************************/ +/* */ +/* USB OTG: device dependent parts */ +/* */ +/****************************************************************/ +/******** Bits definition for USBx_ADDINFO register ***********/ +#define USBx_ADDINFO_IRQNUM_SHIFT 6 /*!< Assigned Interrupt Request Number */ +#define USBx_ADDINFO_IRQNUM_MASK ((uint8_t)((uint8_t)0x1F << USBx_ADDINFO_IRQNUM_SHIFT)) + +/******** Bits definition for USBx_OTGISTAT register **********/ +#define USBx_OTGISTAT_IDCHG ((uint8_t)0x80) /*!< Change in the ID Signal from the USB connector is sensed. */ +#define USBx_OTGISTAT_ONEMSEC ((uint8_t)0x40) /*!< Set when the 1 millisecond timer expires. */ +#define USBx_OTGISTAT_LINE_STATE_CHG ((uint8_t)0x20) /*!< Set when the USB line state changes. */ +#define USBx_OTGISTAT_SESSVLDCHG ((uint8_t)0x08) /*!< Set when a change in VBUS is detected indicating a session valid or a session no longer valid. */ +#define USBx_OTGISTAT_B_SESS_CHG ((uint8_t)0x04) /*!< Set when a change in VBUS is detected on a B device. */ +#define USBx_OTGISTAT_AVBUSCHG ((uint8_t)0x01) /*!< Set when a change in VBUS is detected on an A device. */ + +/******** Bits definition for USBx_OTGICR register ************/ +#define USBx_OTGICR_IDEN ((uint8_t)0x80) /*!< ID Interrupt Enable */ +#define USBx_OTGICR_ONEMSECEN ((uint8_t)0x40) /*!< One Millisecond Interrupt Enable */ +#define USBx_OTGICR_LINESTATEEN ((uint8_t)0x20) /*!< Line State Change Interrupt Enable */ +#define USBx_OTGICR_SESSVLDEN ((uint8_t)0x08) /*!< Session Valid Interrupt Enable */ +#define USBx_OTGICR_BSESSEN ((uint8_t)0x04) /*!< B Session END Interrupt Enable */ +#define USBx_OTGICR_AVBUSEN ((uint8_t)0x01) /*!< A VBUS Valid Interrupt Enable */ + +/******** Bits definition for USBx_OTGSTAT register ***********/ +#define USBx_OTGSTAT_ID ((uint8_t)0x80) /*!< Indicates the current state of the ID pin on the USB connector */ +#define USBx_OTGSTAT_ONEMSECEN ((uint8_t)0x40) /*!< This bit is reserved for the 1ms count, but it is not useful to software. */ +#define USBx_OTGSTAT_LINESTATESTABLE ((uint8_t)0x20) /*!< Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 millisecond. */ +#define USBx_OTGSTAT_SESS_VLD ((uint8_t)0x08) /*!< Session Valid */ +#define USBx_OTGSTAT_BSESSEND ((uint8_t)0x04) /*!< B Session End */ +#define USBx_OTGSTAT_AVBUSVLD ((uint8_t)0x01) /*!< A VBUS Valid */ + +/******** Bits definition for USBx_OTGCTL register ************/ +#define USBx_OTGCTL_DPLOW ((uint8_t)0x20) /*!< D+ Data Line pull-down resistor enable */ +#define USBx_OTGCTL_DMLOW ((uint8_t)0x10) /*!< D– Data Line pull-down resistor enable */ +#define USBx_OTGCTL_OTGEN ((uint8_t)0x04) /*!< On-The-Go pullup/pulldown resistor enable */ + +/******** Bits definition for USBx_ISTAT register *************/ +#define USBx_ISTAT_ATTACH ((uint8_t)0x40) /*!< Attach interrupt */ + +/******** Bits definition for USBx_INTEN register ***************/ +#define USBx_INTEN_ATTACHEN ((uint8_t)0x40) /*!< ATTACH interrupt enable */ + +/******** Bits definition for USBx_CTL register *****************/ +#define USBx_CTL_RESET ((uint8_t)0x10) /*!< Generates an USB reset signal (host mode) */ +#define USBx_CTL_HOSTMODEEN ((uint8_t)0x08) /*!< Operate in Host mode */ +#define USBx_CTL_RESUME ((uint8_t)0x04) /*!< Executes resume signaling */ + +/******** Bits definition for USBx_ADDR register ****************/ +#define USBx_ADDR_LSEN ((uint8_t)0x80) /*!< Low Speed Enable bit */ + +/******** Bits definition for USBx_TOKEN register ***************/ +#define USBx_TOKEN_TOKENPID_SHIFT 4 /*!< Contains the token type executed by the USB module. */ +#define USBx_TOKEN_TOKENPID_MASK ((uint8_t)((uint8_t)0x0F << USBx_TOKEN_TOKENPID_SHIFT)) +#define USBx_TOKEN_TOKENPID(x) ((uint8_t)(((uint8_t)(x) << USBx_TOKEN_TOKENPID_SHIFT) & USBx_TOKEN_TOKENPID_MASK)) +#define USBx_TOKEN_TOKENENDPT_SHIFT 0 /*!< Holds the Endpoint address for the token command. */ +#define USBx_TOKEN_TOKENENDPT_MASK ((uint8_t)((uint8_t)0x0F << USBx_TOKEN_TOKENENDPT_SHIFT)) +#define USBx_TOKEN_TOKENENDPT(x) ((uint8_t)(((uint8_t)(x) << USBx_TOKEN_TOKENENDPT_SHIFT) & USBx_TOKEN_TOKENENDPT_MASK)) +#define USBx_TOKEN_TOKENPID_OUT 0x1 +#define USBx_TOKEN_TOKENPID_IN 0x9 +#define USBx_TOKEN_TOKENPID_SETUP 0xD + +/******** Bits definition for USBx_ENDPTn register **************/ +#define USBx_ENDPTn_HOSTWOHUB ((uint8_t)0x80) +#define USBx_ENDPTn_RETRYDIS ((uint8_t)0x40) + +/****************************************************************/ +/* */ +/* Reset Control Module (RCM) */ +/* */ +/****************************************************************/ + +/* Only device independent parts */ + +/****************************************************************/ +/* */ +/* System Mode Controller (SMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Digital-to-Analog Converter (DAC) */ +/* */ +/****************************************************************/ + +/* Mostly Device independent */ + +#define DACx_C1_DACBFMD_SHIFT 2 /*!< DAC Buffer Work Mode Select */ +#define DACx_C1_DACBFMD_MASK ((uint8_t)((uint8_t)0x01 << DACx_C1_DACBFMD_ SHIFT)) +#define DACx_C1_DACBFMD(x) ((uint8_t)(((uint8_t)(x) << DACx_C1_DACBFMD_SHIFT) & DACx_C1_DACBFMD_MASK)) + +#define DACx_C1_DACBFMD_MODE_NORMAL 0 +#define DACx_C1_DACBFMD_MODE_OTS 1 + +/****************************************************************/ +/* */ +/* Real Time Clock (RTC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Comparator (CMP) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Flash Memory Module (FTFA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +#endif /* _KL26Z_H_ */ diff --git a/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl27zxx.h b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl27zxx.h new file mode 100644 index 0000000..894e172 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl27zxx.h @@ -0,0 +1,1229 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _KL27ZXX_H_ +#define _KL27ZXX_H_ + +/** + * @brief KL2x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __MPU_PRESENT 0 +#define __VTOR_PRESENT 1 +#define __NVIC_PRIO_BITS 2 +#define __Vendor_SysTickConfig 0 + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ****************/ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + +/****** KL2x Specific Interrupt Numbers ***********************/ + DMA0_IRQn = 0, + DMA1_IRQn = 1, + DMA2_IRQn = 2, + DMA3_IRQn = 3, + Reserved0_IRQn = 4, + FTFA_IRQn = 5, + PMC_IRQn = 6, + LLWU_IRQn = 7, + I2C0_IRQn = 8, + I2C1_IRQn = 9, + SPI0_IRQn = 10, + SPI1_IRQn = 11, + LPUART0_IRQn = 12, + LPUART1_IRQn = 13, + UART2_IRQn = 14, + ADC0_IRQn = 15, + CMP0_IRQn = 16, + TPM0_IRQn = 17, + TPM1_IRQn = 18, + TPM2_IRQn = 19, + RTC0_IRQn = 20, + RTC1_IRQn = 21, + PIT_IRQn = 22, + Reserved1_IRQn = 23, + USB_IRQn = 24, + Reserved5_IRQn = 25, + Reserved2_IRQn = 26, + Reserved3_IRQn = 27, + LPTMR0_IRQn = 28, + Reserved4_IRQn = 29, + PINA_IRQn = 30, + PINBCDE_IRQn = 31, +} IRQn_Type; + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +typedef struct +{ + __IO uint8_t C1; + __IO uint8_t C2; + uint8_t RESERVED0[4]; + __I uint8_t S; + uint8_t RESERVED1[1]; + __IO uint8_t SC; + uint8_t RESERVED2[15]; + __IO uint8_t MC; +} MCGLite_TypeDef; + +typedef struct +{ + __IO uint32_t SC; + __IO uint32_t CNT; + __IO uint32_t MOD; + struct { // Channels + __IO uint32_t SC; + __IO uint32_t V; + } C[6]; + uint32_t RESERVED0[5]; + __IO uint32_t STATUS; + uint32_t RESERVED1[7]; + __IO uint32_t POL; + uint32_t RESERVED2[4]; + __IO uint32_t CONF; +} TPM_TypeDef; + +typedef struct +{ + __IO uint8_t S; + __IO uint8_t BR; + __IO uint8_t C2; + __IO uint8_t C1; + __IO uint8_t ML; + __IO uint8_t MH; + __IO uint8_t DL; + __IO uint8_t DH; + uint8_t RESERVED0[2]; + __IO uint8_t CI; + __IO uint8_t C3; +} SPI_TypeDef; + +typedef struct +{ + __IO uint8_t A1; + __IO uint8_t F; + __IO uint8_t C1; + __IO uint8_t S; + __IO uint8_t D; + __IO uint8_t C2; + __IO uint8_t FLT; + __IO uint8_t RA; + __IO uint8_t SMB; + __IO uint8_t A2; + __IO uint8_t SLTH; + __IO uint8_t SLTL; + __IO uint8_t S2; +} I2C_TypeDef; + +typedef struct +{ + __IO uint32_t BAUD; + __IO uint32_t STAT; + __IO uint32_t CTRL; + __IO uint32_t DATA; + __IO uint32_t MATCH; +} LPUART_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __I uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t MA1; + __IO uint8_t MA2; + __IO uint8_t C4; + __IO uint8_t C5; +} UART_TypeDef; + +typedef struct +{ + __I uint32_t VERID; + __I uint32_t PARAM; + __IO uint32_t CTRL; + uint32_t RESERVED0[1]; + __IO uint32_t SHIFTSTAT; + __IO uint32_t SHIFTERR; + __IO uint32_t TIMSTAT; + uint32_t RESERVED1[1]; + __IO uint32_t SHIFTSIEN; + __IO uint32_t SHIFTEIEN; + __IO uint32_t TIMIEN; + uint32_t RESERVED2[1]; + __IO uint32_t SHIFTSDEN; + uint32_t RESERVED3[19]; + __IO uint32_t SHIFTCTL[4]; + uint32_t RESERVED4[28]; + __IO uint32_t SHIFTCFG[4]; + uint32_t RESERVED5[60]; + __IO uint32_t SHIFTBUF[4]; + uint32_t RESERVED6[28]; + __IO uint32_t SHIFTBUFBIS[4]; + uint32_t RESERVED7[28]; + __IO uint32_t SHIFTBUFBYS[4]; + uint32_t RESERVED8[28]; + __IO uint32_t SHIFTBUFBBS[4]; + uint32_t RESERVED9[28]; + __IO uint32_t TIMCTL[4]; + uint32_t RESERVED10[28]; + __IO uint32_t TIMCFG[4]; + uint32_t RESERVED11[28]; + __IO uint32_t TIMCMP[4]; +} FlexIO_TypeDef; + +typedef struct +{ + __IO uint8_t TRM; + __IO uint8_t SC; +} VREF_TypeDef; + +typedef struct { + __I uint8_t PERID; // 0x00 + uint8_t RESERVED0[3]; + __I uint8_t IDCOMP; // 0x04 + uint8_t RESERVED1[3]; + __I uint8_t REV; // 0x08 + uint8_t RESERVED2[3]; + __I uint8_t ADDINFO; // 0x0C + uint8_t RESERVED7[115]; + __IO uint8_t ISTAT; // 0x80 + uint8_t RESERVED8[3]; + __IO uint8_t INTEN; // 0x84 + uint8_t RESERVED9[3]; + __IO uint8_t ERRSTAT; // 0x88 + uint8_t RESERVED10[3]; + __IO uint8_t ERREN; // 0x8C + uint8_t RESERVED11[3]; + __I uint8_t STAT; // 0x90 + uint8_t RESERVED12[3]; + __IO uint8_t CTL; // 0x94 + uint8_t RESERVED13[3]; + __IO uint8_t ADDR; // 0x98 + uint8_t RESERVED14[3]; + __IO uint8_t BDTPAGE1; // 0x9C + uint8_t RESERVED15[3]; + __IO uint8_t FRMNUML; // 0xA0 + uint8_t RESERVED16[3]; + __IO uint8_t FRMNUMH; // 0xA4 + uint8_t RESERVED17[11]; + __IO uint8_t BDTPAGE2; // 0xB0 + uint8_t RESERVED20[3]; + __IO uint8_t BDTPAGE3; // 0xB4 + uint8_t RESERVED21[11]; + struct { + __IO uint8_t V; // 0xC0 + uint8_t RESERVED[3]; + } ENDPT[16]; + __IO uint8_t USBCTRL; // 0x100 + uint8_t RESERVED22[3]; + __I uint8_t OBSERVE; // 0x104 + uint8_t RESERVED23[3]; + __IO uint8_t CONTROL; // 0x108 + uint8_t RESERVED24[3]; + __IO uint8_t USBTRC0; // 0x10C + uint8_t RESERVED25[7]; + __IO uint8_t USBFRMADJUST; // 0x114 + uint8_t RESERVED26[15]; + __IO uint8_t KEEP_ALIVE_CTRL; // 0x124 + uint8_t RESERVED30[3]; + __IO uint8_t KEEP_ALIVE_WKCTRL; // 0x128 + uint8_t RESERVED31[23] + __IO uint8_t CLK_RECOVER_CTRL; // 0x140 + uint8_t RESERVED27[3]; + __IO uint8_t CLK_RECOVER_IRC_EN; // 0x144 + uint8_t RESERVED28[15]; + __IO uint8_t CLK_RECOVER_INT_EN; // 0x154 + uint8_t RESERVED29[7]; + __IO uint8_t CLK_RECOVER_INT_STATUS; // 0x15c +} USBFS_TypeDef; + +typedef struct +{ + __I uint8_t SRS0; + __I uint8_t SRS1; + uint8_t RESERVED0[2]; + __IO uint8_t RPFC; + __IO uint8_t RPFW; + __IO uint8_t FM; + __IO uint8_t MR; + __IO uint8_t SSRS0; + __IO uint8_t SSRS1; +} RCM_TypeDef; + +typedef struct +{ + __IO uint32_t DATA; + __IO uint32_t GPOLY; + __IO uint32_t CTRL; +} CRC_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ +#define DMA_BASE ((uint32_t)0x40008100) +#define FTFA_BASE ((uint32_t)0x40020000) +#define DMAMUX_BASE ((uint32_t)0x40021000) +#define CRC_BASE ((uint32_t)0x40032000) +#define PIT_BASE ((uint32_t)0x40037000) +#define LPTPM0_BASE ((uint32_t)0x40038000) +#define LPTPM1_BASE ((uint32_t)0x40039000) +#define LPTPM2_BASE ((uint32_t)0x4003A000) +#define ADC0_BASE ((uint32_t)0x4003B000) +#define RTC_BASE ((uint32_t)0x4003D000) +#define LPTMR0_BASE ((uint32_t)0x40040000) +#define SRF_BASE ((uint32_t)0x40041000) +#define SIM_BASE ((uint32_t)0x40047000) +#define PORTA_BASE ((uint32_t)0x40049000) +#define PORTB_BASE ((uint32_t)0x4004A000) +#define PORTC_BASE ((uint32_t)0x4004B000) +#define PORTD_BASE ((uint32_t)0x4004C000) +#define PORTE_BASE ((uint32_t)0x4004D000) +#define LPUART0_BASE ((uint32_t)0x40054000) +#define LPUART1_BASE ((uint32_t)0x40055000) +#define FLEXIO_BASE ((uint32_t)0x4005F000) // TODO: register defs +#define MCGLITE_BASE ((uint32_t)0x40064000) +#define OSC0_BASE ((uint32_t)0x40065000) +#define I2C0_BASE ((uint32_t)0x40066000) +#define I2C1_BASE ((uint32_t)0x40067000) +#define UART2_BASE ((uint32_t)0x4006C000) +#define USBFS_BASE ((uint32_t)0x40072000) +#define CMP_BASE ((uint32_t)0x40073000) +#define VREF_BASE ((uint32_t)0x40074000) +#define SPI0_BASE ((uint32_t)0x40076000) +#define SPI1_BASE ((uint32_t)0x40077000) +#define LLWU_BASE ((uint32_t)0x4007C000) +#define PMC_BASE ((uint32_t)0x4007D000) +#define SMC_BASE ((uint32_t)0x4007E000) +#define RCM_BASE ((uint32_t)0x4007F000) +#define USB_RAM_BASE ((uint32_t)0x400FE000) +#define GPIOA_BASE ((uint32_t)0x400FF000) +#define GPIOB_BASE ((uint32_t)0x400FF040) +#define GPIOC_BASE ((uint32_t)0x400FF080) +#define GPIOD_BASE ((uint32_t)0x400FF0C0) +#define GPIOE_BASE ((uint32_t)0x400FF100) +#define MCM_BASE ((uint32_t)0xF0003000) + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define FTFA ((FTFA_TypeDef *) FTFA_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define PIT ((PIT_TypeDef *) PIT_BASE) +#define TPM0 ((TPM_TypeDef *) LPTPM0_BASE) +#define TPM1 ((TPM_TypeDef *) LPTPM1_BASE) +#define TPM2 ((TPM_TypeDef *) LPTPM2_BASE) +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define RTC0 ((RTC_TypeDef *) RTC0_BASE) +#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) +#define TSI0 ((TSI_TypeDef *) TSI0_BASE) +#define SIM ((SIM_TypeDef *) SIM_BASE) +#define LLWU ((LLWU_TypeDef *) LLWU_BASE) +#define PMC ((PMC_TypeDef *) PMC_BASE) +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) +#define PORTD ((PORT_TypeDef *) PORTD_BASE) +#define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define USB0 ((USBFS_TypeDef *) USBFS_BASE) +#define CMP ((CMP_TypeDef *) CMP_BASE) +#define VREF ((VREF_TypeDef *) VREF_BASE) +#define MCG ((MCGLite_TypeDef *) MCGLITE_BASE) +#define OSC0 ((OSC_TypeDef *) OSC0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define LPUART0 ((LPUART_TypeDef *) LPUART0_BASE) +#define LPUART1 ((LPUART_TypeDef *) LPUART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define FLEXIO ((FlexIO_TypeDef *) FLEXIO_BASE) +#define SMC ((SMC_TypeDef *) SMC_BASE) +#define RCM ((RCM_TypeDef *) RCM_BASE) +#define SYSTEM_REGISTER_FILE ((volatile uint8_t *) SRF_BASE) /* 32 bytes */ +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define MCM ((MCM_TypeDef *) MCM_BASE) +#define USB_RAM ((volatile uint8_t *) USB_RAM_BASE) /* 512 bytes */ + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ +/********* Bits definition for SIM_SOPT1 register *************/ +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ +#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ +#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ +#define SIM_SOPT1_OSC32KOUT_SHIFT 16 /*!< 32K oscillator clock output (shift) */ +#define SIM_SOPT1_OSC32KOUT_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock output (mask) */ +#define SIM_SOPT1_OSC32KOUT(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock output */ + +/******* Bits definition for SIM_SOPT2 register ************/ +#define SIM_SOPT2_LPUART1SRC_SHIFT 28 /*!< LPUART1 clock source select (shift) */ +#define SIM_SOPT2_LPUART1SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_LPUART1SRC_SHIFT)) /*!< LPUART1 clock source select (mask) */ +#define SIM_SOPT2_LPUART1SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_LPUART1SRC_SHIFT) & SIM_SOPT2_LPUART1SRC_MASK)) /*!< LPUART1 clock source select */ +#define SIM_SOPT2_LPUART0SRC_SHIFT 26 /*!< LPUART0 clock source select (shift) */ +#define SIM_SOPT2_LPUART0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_LPUART0SRC_SHIFT)) /*!< LPUART0 clock source select (mask) */ +#define SIM_SOPT2_LPUART0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_LPUART0SRC_SHIFT) & SIM_SOPT2_LPUART0SRC_MASK)) /*!< UART0 clock source select */ +#define SIM_SOPT2_TPMSRC_SHIFT 24 /*!< TPM clock source select (shift) */ +#define SIM_SOPT2_TPMSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_TPMSRC_SHIFT)) /*!< TPM clock source select (mask) */ +#define SIM_SOPT2_TPMSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_TPMSRC_SHIFT) & SIM_SOPT2_TPMSRC_MASK)) /*!< TPM clock source select */ +#define SIM_SOPT2_FLEXIOSRC_SHIFT 22 /*!< FlexIO Module Clock Source Select (shift) */ +#define SIM_SOPT2_FLEXIOSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_FLEXIO_SHIFT)) /*!< FlexIO Module Clock Source Select (mask) */ +#define SIM_SOPT2_FLEXIOSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_FLEXIO_SHIFT) & SIM_SOPT2_FLEXIO_MASK)) /*!< FlexIO Module Clock Source Select */ +#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 /*!< CLKOUT select (shift) */ +#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x07 << SIM_SOPT2_CLKOUTSEL_SHIFT)) /*!< CLKOUT select (mask) */ +#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) /*!< CLKOUT select */ +#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ + +/******* Bits definition for SIM_SOPT4 register ************/ +#define SIM_SOPT4_TPM2CLKSEL ((uint32_t)0x04000000) /*!< TPM2 External Clock Pin Select */ +#define SIM_SOPT4_TPM1CLKSEL ((uint32_t)0x02000000) /*!< TPM1 External Clock Pin Select */ +#define SIM_SOPT4_TPM0CLKSEL ((uint32_t)0x01000000) /*!< TPM0 External Clock Pin Select */ +#define SIM_SOPT4_TPM2CH0SRC ((uint32_t)0x00100000) /*!< TPM2 channel 0 input capture source select */ +#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18 /*!< TPM1 channel 0 input capture source select (shift) */ +#define SIM_SOPT4_TPM1CH0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT4_TPM1CH0SRC_SHIFT)) /*!< TPM1 channel 0 input capture source select (mask) */ +#define SIM_SOPT4_TPM1CH0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT4_TPM1CH0SRC_SHIFT) & SIM_SOPT4_TPM1CH0SRC_MASK)) /*!< TPM1 channel 0 input capture source select */ + +/******* Bits definition for SIM_SOPT5 register ************/ +#define SIM_SOPT5_UART2ODE ((uint32_t)0x00040000) /*!< UART2 Open Drain Enable */ +#define SIM_SOPT5_LPUART1ODE ((uint32_t)0x00020000) /*!< LPUART1 Open Drain Enable */ +#define SIM_SOPT5_LPUART0ODE ((uint32_t)0x00010000) /*!< LPUART0 Open Drain Enable */ +#define SIM_SOPT5_LPUART1RXSRC ((uint32_t)0x00000040) /*!< LPUART1 receive data source select */ +#define SIM_SOPT5_LPUART1TXSRC_SHIFT 4 /*!< LPUART1 transmit data source select (shift) */ +#define SIM_SOPT5_LPUART1TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_LPUART1TXSRC_SHIFT)) /*!< LPUART1 transmit data source select (mask) */ +#define SIM_SOPT5_LPUART1TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_LPUART1TXSRC_SHIFT) & SIM_SOPT5_LPUART1TXSRC_MASK)) /*!< LPUART1 transmit data source select */ +#define SIM_SOPT5_LPUART0RXSRC ((uint32_t)0x00000040) /*!< LPUART0 receive data source select */ +#define SIM_SOPT5_LPUART0TXSRC_SHIFT 0 /*!< LPUART0 transmit data source select (shift) */ +#define SIM_SOPT5_LPUART0TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_LPUART0TXSRC_SHIFT)) /*!< LPUART0 transmit data source select (mask) */ +#define SIM_SOPT5_LPUART0TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_LPUART0TXSRC_SHIFT) & SIM_SOPT5_LPUART0TXSRC_MASK)) /*!< LPUART0 transmit data source select */ + +/******* Bits definition for SIM_SOPT7 register ************/ +#define SIM_SOPT7_ADC0ALTTRGEN ((uint32_t)0x00000080) /*!< ADC0 Alternate Trigger Enable */ +#define SIM_SOPT7_ADC0PRETRGSEL ((uint32_t)0x00000010) /*!< ADC0 Pretrigger Select */ +#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 /*!< ADC0 Trigger Select (shift) */ +#define SIM_SOPT7_ADC0TRGSEL_MASK ((uint32_t)((uint32_t)0x0F << SIM_SOPT7_ADC0TRGSEL_SHIFT)) /*!< ADC0 Trigger Select (mask) */ +#define SIM_SOPT7_ADC0TRGSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT7_ADC0TRGSEL_SHIFT) & SIM_SOPT7_ADC0TRGSEL_MASK)) /*!< ADC0 Trigger Select */ + +/******** Bits definition for SIM_SDID register ************/ +#define SIM_SDID_FAMID_SHIFT 28 /*!< Kinetis family ID (shift) */ +#define SIM_SDID_FAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_FAMID_SHIFT)) /*!< Kinetis family ID (mask) */ +#define SIM_SDID_SUBFAMID_SHIFT 24 /*!< Kinetis Sub-Family ID (shift) */ +#define SIM_SDID_SUBFAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SUBFAMID_SHIFT)) /*!< Kinetis Sub-Family ID (mask) */ +#define SIM_SDID_SERIESID_SHIFT 20 /*!< Kinetis Series ID (shift) */ +#define SIM_SDID_SERIESID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SERIESID_SHIFT)) /*!< Kinetis Series ID (mask) */ +#define SIM_SDID_SRAMSIZE_SHIFT 16 /*!< System SRAM Size (shift) */ +#define SIM_SDID_SRAMSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SRAMSIZE_SHIFT)) /*!< System SRAM Size (mask) */ +#define SIM_SDID_REVID_SHIFT 12 /*!< Device revision number (shift) */ +#define SIM_SDID_REVID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_REVID_SHIFT)) /*!< Device revision number (mask) */ +#define SIM_SDID_PINID_SHIFT 0 /*!< Pincount identification (shift) */ +#define SIM_SDID_PINID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_PINID_SHIFT)) /*!< Pincount identification (mask) */ + +/******* Bits definition for SIM_SCGC4 register ************/ +#define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) /*!< SPI1 Clock Gate Control */ +#define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) /*!< SPI0 Clock Gate Control */ +#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */ +#define SIM_SCGC4_CMP0 ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ +#define SIM_SCGC4_USBFS ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ +#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ +#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */ +#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ + +/******* Bits definition for SIM_SCGC5 register ************/ +#define SIM_SCGC5_FLEXIO ((uint32_t)0x80000000) /*!< FlexIO Module */ +#define SIM_SCGC5_LPUART1 ((uint32_t)0x00200000) /*!< LPUART1 Clock Gate Control */ +#define SIM_SCGC5_LPUART0 ((uint32_t)0x00100000) /*!< LPUART0 Clock Gate Control */ +#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ +#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ +#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ +#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ +#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ +#define SIM_SCGC5_LPTMR ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ +#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ +#define SIM_SCGC6_TPM2 ((uint32_t)0x04000000) /*!< TPM2 Clock Gate Control */ +#define SIM_SCGC6_TPM1 ((uint32_t)0x02000000) /*!< TPM1 Clock Gate Control */ +#define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) /*!< TPM0 Clock Gate Control */ +#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ +#define SIM_SCGC6_CRC ((uint32_t)0x00040000) /*!< CRC Clock Gate Control */ +#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ +#define SIM_SCGC6_FTF ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ + +/******* Bits definition for SIM_SCGC7 register ************/ +#define SIM_SCGC7_DMA ((uint32_t)0x00000100) /*!< DMA Clock Gate Control */ + +/****** Bits definition for SIM_CLKDIV1 register ***********/ +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 /*!< Clock 1 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0x0F << SIM_CLKDIV1_OUTDIV1_SHIFT)) /*!< Clock 1 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) /*!< Clock 1 output divider value */ +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 /*!< Clock 4 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x07 << SIM_CLKDIV1_OUTDIV4_SHIFT)) /*!< Clock 4 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) /*!< Clock 4 output divider value */ + +/******* Bits definition for SIM_FCFG1 register ************/ +#define SIM_FCFG1_PFSIZE_SHIFT 24 /*!< Program Flash Size (shift) */ +#define SIM_FCFG1_PFSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_FCFG1_PFSIZE_SHIFT)) /*!< Program Flash Size (mask) */ +#define SIM_FCFG1_FLASHDOZE ((uint32_t)0x00000002) /*!< Flash Doze */ +#define SIM_FCFG1_FLASHDIS ((uint32_t)0x00000001) /*!< Flash Disable */ + +/******* Bits definition for SIM_FCFG2 register ************/ +#define SIM_FCFG2_MAXADDR0_SHIFT 24 /*!< Max address lock (shift) */ +#define SIM_FCFG2_MAXADDR0_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR0_SHIFT)) /*!< Max address lock (mask) */ +#define SIM_FCFG2_MAXADDR1_SHIFT 16 /*!< Max address lock (block 1) (shift) */ +#define SIM_FCFG2_MAXADDR1_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR1_SHIFT)) /*!< Max address lock (block 1) (mask) */ + +/******* Bits definition for SIM_UIDMH register ************/ +#define SIM_UIDMH_UID_MASK ((uint32_t)0x0000FFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDML register ************/ +#define SIM_UIDML_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDL register *************/ +#define SIM_UIDL_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_COPC register *************/ +#define SIM_COPC_COPCLKSEL_SHIFT 6 /*!< COP Clock Select (shift) */ +#define SIM_COPC_COPCLKSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_COPC_COPCLKSEL_SHIFT)) /*!< COP Clock Select (mask) */ +#define SIM_COPC_COPCLKSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_COPC_COPCLKSEL_SHIFT) & SIM_COPC_COPCLKSEL_MASK)) /*!< COP Clock Select */ +#define SIM_COPC_COPDBGEN ((uint32_t)0x00000020) /*!< COP Debug Enable */ +#define SIM_COPC_COPSTPEN ((uint32_t)0x00000010) /*!< COP Stop Enable */ +#define SIM_COPC_COPT_SHIFT 2 /*!< COP Watchdog Timeout (shift) */ +#define SIM_COPC_COPT_MASK ((uint32_t)((uint32_t)0x03 << SIM_COPC_COPT_SHIFT)) /*!< COP Watchdog Timeout (mask) */ +#define SIM_COPC_COPT(x) ((uint32_t)(((uint32_t)(x) << SIM_COPC_COPT_SHIFT) & SIM_COPC_COPT_MASK)) /*!< COP Watchdog Timeout */ +#define SIM_COPC_COPCLKS ((uint32_t)0x00000002) /*!< COP Clock Select */ +#define SIM_COPC_COPW ((uint32_t)0x00000001) /*!< COP windowed mode */ + +/******* Bits definition for SIM_SRVCOP register ***********/ +#define SIM_SRVCOP_SRVCOP_SHIFT 0 /*!< Sevice COP Register (shift) */ +#define SIM_SRVCOP_SRVCOP_MASK ((uint32_t)((uint32_t)0xFF << SIM_SRVCOP_SRVCOP_SHIFT)) /*!< Sevice COP Register (mask) */ +#define SIM_SRVCOP_SRVCOP(x) ((uint32_t)(((uint32_t)(x) << SIM_SRVCOP_SRVCOP_SHIFT) & SIM_SRVCOP_SRVCOP_MASK)) /*!< Sevice COP Register */ + + +/****************************************************************/ +/* */ +/* Low-Leakage Wakeup Unit (LLWU) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Port Control and interrupts (PORT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Oscillator (OSC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access (DMA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access Multiplexer (DMAMUX) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Periodic Interrupt Timer (PIT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Analog-to-Digital Converter (ADC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Low-Power Timer (LPTMR) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Multipurpose Clock Generator Lite (MCG_Lite) */ +/* */ +/****************************************************************/ +/*********** Bits definition for MCG_C1 register **************/ +#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */ +#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */ +#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */ +#define MCG_C1_CLKS_HIRC MCG_C1_CLKS(0) /*!< HIRC */ +#define MCG_C1_CLKS_LIRC MCG_C1_CLKS(1) /*!< LIRC (either LIRC2M or LIRC8M) */ +#define MCG_C1_CLKS_EXT MCG_C1_CLKS(2) /*!< EXT (external ref) */ +#define MCG_C1_IRCLKEN ((uint8_t)((uint8_t)1 << 1)) /*!< Internal Reference Clock Enable */ +#define MCG_C1_IREFSTEN ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Stop Enable */ + +/*********** Bits definition for MCG_C2 register **************/ +#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */ +#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x03 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */ +#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */ +#define MCG_C2_HGO0 ((uint8_t)((uint8_t)1 << 3)) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */ +#define MCG_C2_EREFS0 ((uint8_t)((uint8_t)1 << 2)) /*!< External Reference Select (0=clock; 1=oscillator) */ +#define MCG_C2_IRCS ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Select (0=slow; 1=fast) */ + +/************ Bits definition for MCG_S register **************/ +#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */ +#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x03 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */ +#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */ +#define MCG_S_CLKST_HIRC MCG_S_CLKST(0) +#define MCG_S_CLKST_LIRC MCG_S_CLKST(1) +#define MCG_S_CLKST_EXT MCG_S_CLKST(2) +#define MCG_S_OSCINIT0 ((uint8_t)((uint8_t)1 << 1)) /*!< OSC Initialization */ + +/************ Bits definition for MCG_SC register **************/ +#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */ +#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */ +#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */ +#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */ +#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */ +#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */ +#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */ +#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */ +#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */ +#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */ +#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */ + +/************ Bits definition for MCG_MC register *************/ +#define MCG_MC_HIRCEN ((uint8_t)0x80) /*!< High-frequency IRC Enable */ +#define MCG_MC_LIRC_DIV2_SHIFT 0 /*!< Second Low-frequency Internal Reference Clock Divider (shift) */ +#define MCG_MC_LIRC_DIV2_MASK ((uint8_t)((uint8_t)0x07 << MCG_MC_LIRC_DIV2_SHIFT)) /*!< Second Low-frequency Internal Reference Clock Divider (mask) */ +#define MCG_MC_LIRC_DIV2(x) ((uint8_t)(((uint8_t)(x) << MCG_MC_LIRC_DIV2_SHIFT) & MCG_MC_LIRC_DIV2_MASK)) /*!< Second Low-frequency Internal Reference Clock Divider */ +#define MCG_MC_LIRC_DIV2_DIV1 MCG_MC_LIRC_DIV2(0) /*!< Divide Factor is 1 */ +#define MCG_MC_LIRC_DIV2_DIV2 MCG_MC_LIRC_DIV2(1) /*!< Divide Factor is 2 */ +#define MCG_MC_LIRC_DIV2_DIV4 MCG_MC_LIRC_DIV2(2) /*!< Divide Factor is 4 */ +#define MCG_MC_LIRC_DIV2_DIV8 MCG_MC_LIRC_DIV2(3) /*!< Divide Factor is 8 */ +#define MCG_MC_LIRC_DIV2_DIV16 MCG_MC_LIRC_DIV2(4) /*!< Divide Factor is 16 */ +#define MCG_MC_LIRC_DIV2_DIV32 MCG_MC_LIRC_DIV2(5) /*!< Divide Factor is 32 */ +#define MCG_MC_LIRC_DIV2_DIV64 MCG_MC_LIRC_DIV2(6) /*!< Divide Factor is 64 */ +#define MCG_MC_LIRC_DIV2_DIV128 MCG_MC_LIRC_DIV2(7) /*!< Divide Factor is 128 */ + +/****************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/****************************************************************/ +/*********** Bits definition for SPIx_S register **************/ +#define SPIx_S_SPRF ((uint8_t)0x80) /*!< SPI Read Buffer Full Flag */ +#define SPIx_S_SPMF ((uint8_t)0x40) /*!< SPI Match Flag */ +#define SPIx_S_SPTEF ((uint8_t)0x20) /*!< SPI Transmit Buffer Empty Flag */ +#define SPIx_S_MODF ((uint8_t)0x10) /*!< Master Mode Fault Flag */ +#define SPIx_S_RNFULLF ((uint8_t)0x08) /*!< Receive FIFO nearly full flag */ +#define SPIx_S_TNEAREF ((uint8_t)0x04) /*!< Transmit FIFO nearly empty flag */ +#define SPIx_S_TXFULLF ((uint8_t)0x02) /*!< Transmit FIFO full flag */ +#define SPIx_S_RFIFOEF ((uint8_t)0x01) /*!< SPI read FIFO empty flag */ + +/*********** Bits definition for SPIx_BR register *************/ +#define SPIx_BR_SPPR_SHIFT 4 /*!< SPI Baud rate Prescaler Divisor */ +#define SPIx_BR_SPPR_MASK ((uint8_t)((uint8_t)0x7 << SPIx_BR_SPPR_SHIFT)) +#define SPIx_BR_SPPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPPR_SHIFT) & SPIx_BR_SPPR_MASK)) +#define SPIx_BR_SPR_SHIFT 0 /*!< SPI Baud rate Divisor */ +#define SPIx_BR_SPR_MASK ((uint8_t)((uint8_t)0x0F << SPIx_BR_SPR_SHIFT)) +#define SPIx_BR_SPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPR_SHIFT) & SPIx_BR_SPR_MASK)) + +/*********** Bits definition for SPIx_C2 register *************/ +#define SPIx_C2_SPMIE ((uint8_t)0x80) /*!< SPI Match Interrupt Enable */ +#define SPIx_C2_SPIMODE ((uint8_t)0x40) /*!< SPI 8-bit or 16-bit mode */ +#define SPIx_C2_TXDMAE ((uint8_t)0x20) /*!< Transmit DMA Enable */ +#define SPIx_C2_MODFEN ((uint8_t)0x10) /*!< Master Mode-Fault Function Enable */ +#define SPIx_C2_BIDIROE ((uint8_t)0x08) /*!< Bidirectional Mode Output Enable */ +#define SPIx_C2_RXDMAE ((uint8_t)0x04) /*!< Receive DMA Enable */ +#define SPIx_C2_SPISWAI ((uint8_t)0x02) /*!< SPI Stop in Wait Mode */ +#define SPIx_C2_SPC0 ((uint8_t)0x01) /*!< SPI Pin Control 0 */ + +/*********** Bits definition for SPIx_C1 register *************/ +#define SPIx_C1_SPIE ((uint8_t)0x80) /*!< SPI Interrupt Enable */ +#define SPIx_C1_SPE ((uint8_t)0x40) /*!< SPI System Enable */ +#define SPIx_C1_SPTIE ((uint8_t)0x20) /*!< SPI Transmit Interrupt Enable */ +#define SPIx_C1_MSTR ((uint8_t)0x10) /*!< Master/Slave Mode Select */ +#define SPIx_C1_CPOL ((uint8_t)0x08) /*!< Clock Polarity */ +#define SPIx_C1_CPHA ((uint8_t)0x04) /*!< Clock Phase */ +#define SPIx_C1_SSOE ((uint8_t)0x02) /*!< Slave Select Output Enable */ +#define SPIx_C1_LSBFE ((uint8_t)0x01) /*!< LSB First */ + +/*********** Bits definition for SPIx_ML register *************/ +#define SPIx_ML_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - low byte */ +#define SPIx_ML_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_ML_DATA_SHIFT)) +#define SPIx_ML_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_ML_DATA_SHIFT) & SPIx_ML_DATA_MASK)) + +/*********** Bits definition for SPIx_MH register *************/ +#define SPIx_MH_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - high byte */ +#define SPIx_MH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_MH_DATA_SHIFT)) +#define SPIx_MH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_MH_DATA_SHIFT) & SPIx_MH_DATA_MASK)) + +/*********** Bits definition for SPIx_DL register *************/ +#define SPIx_DL_DATA_SHIFT 0 /*!< Data - low byte */ +#define SPIx_DL_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DL_DATA_SHIFT)) +#define SPIx_DL_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DL_DATA_SHIFT) & SPIx_DL_DATA_MASK)) + +/*********** Bits definition for SPIx_DH register *************/ +#define SPIx_DH_DATA_SHIFT 0 /*!< Data - high byte */ +#define SPIx_DH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DH_DATA_SHIFT)) +#define SPIx_DH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DH_DATA_SHIFT) & SPIx_DH_DATA_MASK)) + +/*********** Bits definition for SPIx_CI register *************/ +#define SPIx_CI_TXFERR ((uint8_t)0x80) /*!< Transmit FIFO error flag */ +#define SPIx_CI_RXFERR ((uint8_t)0x40) /*!< Receive FIFO error flag */ +#define SPIx_CI_TXFOF ((uint8_t)0x20) /*!< Transmit FIFO overflow flag */ +#define SPIx_CI_RXFOF ((uint8_t)0x10) /*!< Receive FIFO overflow flag */ +#define SPIx_CI_TNEAREFCI ((uint8_t)0x08) /*!< Transmit FIFO nearly empty flag clear interrupt */ +#define SPIx_CI_RNFULLFCI ((uint8_t)0x04) /*!< Receive FIFO nearly full flag clear interrupt */ +#define SPIx_CI_SPTEFCI ((uint8_t)0x02) /*!< Transmit FIFO empty flag clear interrupt */ +#define SPIx_CI_SPRFCI ((uint8_t)0x01) /*!< Receive FIFO full flag clear interrupt */ + +/*********** Bits definition for SPIx_C3 register *************/ +#define SPIx_C3_TNEAREF_MARK ((uint8_t)0x20) /*!< Transmit FIFO nearly empty watermark */ +#define SPIx_C3_RNFULLF_MARK ((uint8_t)0x10) /*!< Receive FIFO nearly full watermark */ +#define SPIx_C3_INTCLR ((uint8_t)0x08) /*!< Interrupt clearing mechanism select */ +#define SPIx_C3_TNEARIEN ((uint8_t)0x04) /*!< Transmit FIFO nearly empty interrupt enable */ +#define SPIx_C3_RNFULLIEN ((uint8_t)0x02) /*!< Receive FIFO nearly full interrupt enable */ +#define SPIx_C3_FIFOMODE ((uint8_t)0x01) /*!< FIFO mode enable */ + +/****************************************************************/ +/* */ +/* Inter-Integrated Circuit (I2C): Device dependent part */ +/* */ +/****************************************************************/ +/*********** Bits definition for I2Cx_FLT register ************/ +#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ +#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ +#define I2Cx_FLT_SSIE ((uint8_t)0x20) /*!< I2C Bus Stop or Start Interrupt Enable */ +#define I2Cx_FLT_STARTF ((uint8_t)0x10) /*!< I2C Bus Start Detect Flag */ +#define I2Cx_FLT_FLT_SHIFT 0 /*!< I2C Programmable Filter Factor */ +#define I2Cx_FLT_FLT_MASK ((uint8_t)((uint8_t)0x0F << I2Cx_FLT_FLT_SHIFT)) +#define I2Cx_FLT_FLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_FLT_FLT_SHIFT) & I2Cx_FLT_FLT_MASK)) + +/*********** Bits definition for I2Cx_S2 register *************/ +#define I2Cx_S2_ERROR ((uint8_t)0x02) /*!< Error flag */ +#define I2Cx_S2_EMPTY ((uint8_t)0x01) /*!< Empty flag */ + +/****************************************************************/ +/* */ +/* Universal Asynchronous Receiver/Transmitter (UART) */ +/* */ +/****************************************************************/ +/********* Bits definition for UARTx_BDH register *************/ +#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RX Input Active Edge Interrupt Enable */ +#define UARTx_BDH_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDH_SBR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_BDH_SBR_SHIFT)) +#define UARTx_BDH_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDH_SBR_SHIFT) & UARTx_BDH_SBR_MASK)) + +/********* Bits definition for UARTx_BDL register *************/ +#define UARTx_BDL_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDL_SBR_MASK ((uint8_t)((uint8_t)0xFF << UARTx_BDL_SBR_SHIFT)) +#define UARTx_BDL_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDL_SBR_SHIFT) & UARTx_BDL_SBR_MASK)) + +/********* Bits definition for UARTx_C1 register **************/ +#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ +#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */ +#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */ +#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */ +#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */ +#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */ +#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */ + +/********* Bits definition for UARTx_C2 register **************/ +#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */ +#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */ +#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */ +#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */ +#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */ +#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */ +#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */ +#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */ + +/********* Bits definition for UARTx_S1 register **************/ +#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */ +#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */ +#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */ +#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */ +#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */ +#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */ +#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */ +#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */ + +/********* Bits definition for UARTx_S2 register **************/ +#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */ +#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */ +#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */ +#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */ +#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */ +#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */ + +/********* Bits definition for UARTx_C3 register **************/ +#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */ +#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */ +#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */ +#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */ +#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */ +#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */ +#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */ +#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */ + +/********* Bits definition for UARTx_D register ***************/ +#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ +#define UARTx_D_RT_SHIFT 0 +#define UARTx_D_RT_MASK ((uint8_t)0xFF) + +/********* Bits definition for UARTx_MA1 register *************/ +#define UARTx_MA1_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA1_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA1_MA_SHIFT)) +#define UARTx_MA1_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA1_MA_SHIFT) & UARTx_MA1_MA_MASK)) + +/********* Bits definition for UARTx_MA2 register *************/ +#define UARTx_MA2_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA2_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA2_MA_SHIFT)) +#define UARTx_MA2_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA2_MA_SHIFT) & UARTx_MA2_MA_MASK)) + +/********* Bits definition for UARTx_C4 register **************/ +#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ +#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */ +#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */ +#define UARTx_C4_OSR_SHIFT 0 /*!< Over Sampling Ratio */ +#define UARTx_C4_OSR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_C4_OSR_SHIFT)) +#define UARTx_C4_OSR(x) ((uint8_t)(((uint8_t)(x) << UARTx_C4_OSR_SHIFT) & UARTx_C4_OSR_MASK)) + +/********* Bits definition for UARTx_C5 register **************/ +#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */ +#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */ +#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */ +#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */ + +/****************************************************************/ +/* */ +/*Low Power Universal asynchronous receiver/transmitter (LPUART)*/ +/* */ +/****************************************************************/ +/********* Bits definition for LPUARTx_BAUD register **********/ +#define LPUARTx_BAUD_MAEN1 ((uint32_t)0x80000000) /*!< Match Address Mode Enable 1 */ +#define LPUARTx_BAUD_MAEN2 ((uint32_t)0x40000000) /*!< Match Address Mode Enable 2 */ +#define LPUARTx_BAUD_M10 ((uint32_t)0x20000000) /*!< 10-bit Mode select */ +#define LPUARTx_BAUD_OSR_SHIFT 24 /*!< Over Sampling Ratio (shift) */ +#define LPUARTx_BAUD_OSR_MASK ((uint32_t)((uint32_t)0x1F << LPUARTx_BAUD_OSR_SHIFT)) /*!< Over Sampling Ratio (mask) */ +#define LPUARTx_BAUD_OSR(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_BAUD_OSR_SHIFT) & LPUARTx_BAUD_OSR_MASK)) /*!< Over Sampling Ratio */ +#define LPUARTx_BAUD_TDMAE ((uint32_t)0x00800000) /*!< Transmitter DMA Enable */ +#define LPUARTx_BAUD_RDMAE ((uint32_t)0x00200000) /*!< Receiver Full DMA Enable */ +#define LPUARTx_BAUD_MATCFG_SHIFT 18 /*!< Match Configuration (shift) */ +#define LPUARTx_BAUD_MATCFG_MASK ((uint32_t)((uint32_t)0x03 << LPUARTx_BAUD_MATCFG_SHIFT)) /*!< Match Configuration (mask) */ +#define LPUARTx_BAUD_MATCFG(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_BAUD_MATCFG_SHIFT) & LPUARTx_BAUD_MATCFG_MASK)) /*!< Match Configuration */ +#define LPUARTx_BAUD_BOTHEDGE ((uint32_t)0x00020000) /*!< Both Edge Sampling */ +#define LPUARTx_BAUD_RESYNCDIS ((uint32_t)0x00010000) /*!< Resynchronization Disable */ +#define LPUARTx_BAUD_LBKDIE ((uint32_t)0x00008000) /*!< LIN Break Detect Interrupt Enable */ +#define LPUARTx_BAUD_RXEDGIE ((uint32_t)0x00004000) /*!< RX Input Active Edge Interrupt Enable */ +#define LPUARTx_BAUD_SBNS ((uint32_t)0x00002000) /*!< Stop Bit Number Select */ +#define LPUARTx_BAUD_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor (shift) */ +#define LPUARTx_BAUD_SBR_MASK ((uint32_t)((uint32_t)0x1FFF << LPUARTx_BAUD_SBR_SHIFT)) /*!< Baud Rate Modulo Divisor (mask) */ +#define LPUARTx_BAUD_SBR(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_BAUD_SBR_SHIFT) & LPUARTx_BAUD_SBR_MASK)) /*!< Baud Rate Modulo Divisor */ + +/********* Bits definition for LPUARTx_STAT register **********/ +#define LPUARTx_STAT_LBKDIF ((uint32_t)0x80000000) /*!< LIN Break Detect Interrupt Flag */ +#define LPUARTx_STAT_RXEDGIF ((uint32_t)0x40000000) /*!< LPUART_RX Pin Active Edge Interrupt Flag */ +#define LPUARTx_STAT_MSBF ((uint32_t)0x20000000) /*!< MSB First */ +#define LPUARTx_STAT_RXINV ((uint32_t)0x10000000) /*!< Receive Data Inversion */ +#define LPUARTx_STAT_RWUID ((uint32_t)0x08000000) /*!< Receive Wake Up Idle Detect */ +#define LPUARTx_STAT_BRK13 ((uint32_t)0x04000000) /*!< Break Character Generation Length */ +#define LPUARTx_STAT_LBKDE ((uint32_t)0x02000000) /*!< LIN Break Detection Enable */ +#define LPUARTx_STAT_RAF ((uint32_t)0x01000000) /*!< Receiver Active Flag */ +#define LPUARTx_STAT_TDRE ((uint32_t)0x00800000) /*!< Transmit Data Register Empty Flag */ +#define LPUARTx_STAT_TC ((uint32_t)0x00400000) /*!< Transmission Complete Flag */ +#define LPUARTx_STAT_RDRF ((uint32_t)0x00200000) /*!< Receive Data Register Full Flag */ +#define LPUARTx_STAT_IDLE ((uint32_t)0x00100000) /*!< Idle Line Flag */ +#define LPUARTx_STAT_OR ((uint32_t)0x00080000) /*!< Receiver Overrun Flag */ +#define LPUARTx_STAT_NF ((uint32_t)0x00040000) /*!< Noise Flag */ +#define LPUARTx_STAT_FE ((uint32_t)0x00020000) /*!< Framing Error Flag */ +#define LPUARTx_STAT_PF ((uint32_t)0x00010000) /*!< Parity Error Flag */ +#define LPUARTx_STAT_MA1F ((uint32_t)0x00008000) /*!< Match 1 Flag */ +#define LPUARTx_STAT_MA2F ((uint32_t)0x00004000) /*!< Match 2 Flag */ + +/********* Bits definition for LPUARTx_CTRL register **********/ +#define LPUARTx_CTRL_R8T9 ((uint32_t)0x80000000) /*!< Receive Bit 8 / Transmit Bit 9 */ +#define LPUARTx_CTRL_R9T8 ((uint32_t)0x40000000) /*!< Receive Bit 9 / Transmit Bit 8 */ +#define LPUARTx_CTRL_TXDIR ((uint32_t)0x20000000) /*!< LPUART_TX Pin Direction in Single-Wire Mode */ +#define LPUARTx_CTRL_TXINV ((uint32_t)0x10000000) /*!< Transmit Data Inversion */ +#define LPUARTx_CTRL_ORIE ((uint32_t)0x08000000) /*!< Overrun Interrupt Enable */ +#define LPUARTx_CTRL_NEIE ((uint32_t)0x04000000) /*!< Noise Error Interrupt Enable */ +#define LPUARTx_CTRL_FEIE ((uint32_t)0x02000000) /*!< Framing Error Interrupt Enable */ +#define LPUARTx_CTRL_PEIE ((uint32_t)0x01000000) /*!< Parity Error Interrupt Enable */ +#define LPUARTx_CTRL_TIE ((uint32_t)0x00800000) /*!< Transmit Interrupt Enable */ +#define LPUARTx_CTRL_TCIE ((uint32_t)0x00400000) /*!< Transmission Complete Interrupt Enable */ +#define LPUARTx_CTRL_RIE ((uint32_t)0x00200000) /*!< Receiver Interrupt Enable */ +#define LPUARTx_CTRL_ILIE ((uint32_t)0x00100000) /*!< Idle Line Interrupt Enable */ +#define LPUARTx_CTRL_TE ((uint32_t)0x00080000) /*!< Transmitter Enable */ +#define LPUARTx_CTRL_RE ((uint32_t)0x00040000) /*!< Receiver Enable */ +#define LPUARTx_CTRL_RWU ((uint32_t)0x00020000) /*!< Receiver Wakeup Control */ +#define LPUARTx_CTRL_SBK ((uint32_t)0x00010000) /*!< Send Break */ +#define LPUARTx_CTRL_MA1IE ((uint32_t)0x00008000) /*!< Match 1 Interrupt Enable */ +#define LPUARTx_CTRL_MA2IE ((uint32_t)0x00004000) /*!< Match 2 Interrupt Enable */ +#define LPUARTx_CTRL_IDLECFG_SHIFT 8 /*!< Idle Configuration (shift) */ +#define LPUARTx_CTRL_IDLECFG_MASK ((uint32_t)((uint32_t)0x7 << LPUARTx_CTRL_IDLECFG_SHIFT)) /*!< Idle Configuration (mask) */ +#define LPUARTx_CTRL_IDLECFG(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_CTRL_IDLECFG_SHIFT) & LPUARTx_CTRL_IDLECFG_MASK)) /*!< Idle Configuration */ +#define LPUARTx_CTRL_LOOPS ((uint32_t)0x00000080) /*!< Loop Mode Select */ +#define LPUARTx_CTRL_DOZEEN ((uint32_t)0x00000040) /*!< Doze Enable */ +#define LPUARTx_CTRL_RSRC ((uint32_t)0x00000020) /*!< Receiver Source Select */ +#define LPUARTx_CTRL_M ((uint32_t)0x00000010) /*!< 9-Bit or 8-Bit Mode Select */ +#define LPUARTx_CTRL_WAKE ((uint32_t)0x00000008) /*!< Receiver Wakeup Method Select */ +#define LPUARTx_CTRL_ILT ((uint32_t)0x00000004) /*!< Idle Line Type Select */ +#define LPUARTx_CTRL_PE ((uint32_t)0x00000002) /*!< Parity Enable */ +#define LPUARTx_CTRL_PT ((uint32_t)0x00000001) /*!< Parity Type */ + +/********* Bits definition for LPUARTx_DATA register **********/ +#define LPUARTx_DATA_NOISY ((uint32_t)0x00008000) /*!< The current received dataword contained in DATA[R9:R0] was received with noise */ +#define LPUARTx_DATA_PARITYE ((uint32_t)0x00004000) /*!< The current received dataword contained in DATA[R9:R0] was received with a parity error */ +#define LPUARTx_DATA_FRETSC ((uint32_t)0x00002000) /*!< Frame Error / Transmit Special Character */ +#define LPUARTx_DATA_RXEMPT ((uint32_t)0x00001000) /*!< Receive Buffer Empty */ +#define LPUARTx_DATA_IDLINE ((uint32_t)0x00000800) /*!< Idle Line */ +#define LPUARTx_DATA_R9T9 ((uint32_t)0x00000200) /*!< Read receive data buffer 9 or write transmit data buffer 9 */ +#define LPUARTx_DATA_R8T8 ((uint32_t)0x00000100) /*!< Read receive data buffer 8 or write transmit data buffer 8 */ +#define LPUARTx_DATA_R7T7 ((uint32_t)0x00000080) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define LPUARTx_DATA_R6T6 ((uint32_t)0x00000040) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define LPUARTx_DATA_R5T5 ((uint32_t)0x00000020) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define LPUARTx_DATA_R4T4 ((uint32_t)0x00000010) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define LPUARTx_DATA_R3T3 ((uint32_t)0x00000008) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define LPUARTx_DATA_R2T2 ((uint32_t)0x00000004) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define LPUARTx_DATA_R1T1 ((uint32_t)0x00000002) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define LPUARTx_DATA_R0T0 ((uint32_t)0x00000001) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ +#define LPUARTx_DATA_DATA_SHIFT 0 /*!< Data (shift) */ +#define LPUARTx_DATA_DATA_MASK ((uint32_t)((uint32_t)0x3F << LPUARTx_DATA_DATA_SHIFT)) /*!< Data (mask) */ +#define LPUARTx_DATA_DATA(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_DATA_DATA_SHIFT) & LPUARTx_DATA_DATA_MASK)) /*!< Data */ + +/********* Bits definition for LPUARTx_MATCH register *********/ +#define LPUARTx_MATCH_MA2_SHIFT 16 /*!< Match Address 2 (shift) */ +#define LPUARTx_MATCH_MA2_MASK ((uint32_t)((uint32_t)0x3F << LPUARTx_MATCH_MA2_SHIFT)) /*!< Match Address 2 (mask) */ +#define LPUARTx_MATCH_MA2(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_MATCH_MA2_SHIFT) & LPUARTx_MATCH_MA2_MASK)) /*!< Match Address 2 */ +#define LPUARTx_MATCH_MA1_SHIFT 0 /*!< Match Address 1 (shift) */ +#define LPUARTx_MATCH_MA1_MASK ((uint32_t)((uint32_t)0x3F << LPUARTx_MATCH_MA1_SHIFT)) /*!< Match Address 1 (mask) */ +#define LPUARTx_MATCH_MA1(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_MATCH_MA1_SHIFT) & LPUARTx_MATCH_MA1_MASK)) /*!< Match Address 1 */ + +/****************************************************************/ +/* */ +/* Power Management Controller (PMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Timer/PWM Module (TPM) */ +/* */ +/****************************************************************/ +/********** Bits definition for TPMx_SC register ***************/ +#define TPMx_SC_DMA ((uint32_t)0x100) /*!< DMA Enable */ +#define TPMx_SC_TOF ((uint32_t)0x80) /*!< Timer Overflow Flag */ +#define TPMx_SC_TOIE ((uint32_t)0x40) /*!< Timer Overflow Interrupt Enable */ +#define TPMx_SC_CPWMS ((uint32_t)0x20) /*!< Center-aligned PWM Select */ +#define TPMx_SC_CMOD_SHIFT 3 /*!< Clock Mode Selection */ +#define TPMx_SC_CMOD_MASK ((uint32_t)((uint32_t)0x3 << TPMx_SC_CMOD_SHIFT)) +#define TPMx_SC_CMOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_CMOD_SHIFT) & TPMx_SC_CMOD_MASK)) +#define TPMx_SC_PS_SHIFT 0 /*!< Prescale Factor Selection */ +#define TPMx_SC_PS_MASK ((uint32_t)((uint32_t)0x7 << TPMx_SC_PS_SHIFT)) +#define TPMx_SC_PS(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_PS_SHIFT) & TPMx_SC_PS_MASK)) + +/********** Bits definition for TPMx_CNT register **************/ +#define TPMx_CNT_COUNT_SHIFT 0 /*!< Counter Value */ +#define TPMx_CNT_COUNT_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CNT_COUNT_SHIFT)) +#define TPMx_CNT_COUNT(x) ((uint32_t)(((uint32_t)(x) << TPMx_CNT_COUNT_SHIFT) & TPMx_CNT_COUNT_MASK)) + +/********** Bits definition for TPMx_MOD register **************/ +#define TPMx_MOD_MOD_SHIFT 0 /*!< Modulo Value */ +#define TPMx_MOD_MOD_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_MOD_MOD_SHIFT)) +#define TPMx_MOD_MOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_MOD_MOD_SHIFT) & TPMx_MOD_MOD_MASK)) + +/********** Bits definition for TPMx_CnSC register *************/ +#define TPMx_CnSC_CHF ((uint32_t)0x80) /*!< Channel Flag */ +#define TPMx_CnSC_CHIE ((uint32_t)0x40) /*!< Channel Interrupt Enable */ +#define TPMx_CnSC_MSB ((uint32_t)0x20) /*!< Channel Mode Select */ +#define TPMx_CnSC_MSA ((uint32_t)0x10) /*!< Channel Mode Select */ +#define TPMx_CnSC_ELSB ((uint32_t)0x8) /*!< Edge or Level Select */ +#define TPMx_CnSC_ELSA ((uint32_t)0x4) /*!< Edge or Level Select */ +#define TPMx_CnSC_DMA ((uint32_t)0x1) /*!< DMA Enable */ + +/********** Bits definition for TPMx_CnV register **************/ +#define TPMx_CnV_VAL_SHIFT 0 /*!< Channel Value */ +#define TPMx_CnV_VAL_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CnV_VAL_SHIFT)) +#define TPMx_CnV_VAL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CnV_VAL_SHIFT) & TPMx_CnV_VAL_MASK)) + +/********* Bits definition for TPMx_STATUS register ************/ +#define TPMx_STATUS_TOF ((uint32_t)0x100) /*!< Timer Overflow Flag */ +#define TPMx_STATUS_CH5F ((uint32_t)0x20) /*!< Channel 5 Flag */ +#define TPMx_STATUS_CH4F ((uint32_t)0x10) /*!< Channel 4 Flag */ +#define TPMx_STATUS_CH3F ((uint32_t)0x8) /*!< Channel 3 Flag */ +#define TPMx_STATUS_CH2F ((uint32_t)0x4) /*!< Channel 2 Flag */ +#define TPMx_STATUS_CH1F ((uint32_t)0x2) /*!< Channel 1 Flag */ +#define TPMx_STATUS_CH0F ((uint32_t)0x1) /*!< Channel 0 Flag */ + +/********** Bits definition for TPMx_POL register **************/ +#define TPMx_POL_POL5 ((uint32_t)0x20) /*!< Channel 5 Polarity */ +#define TPMx_POL_POL4 ((uint32_t)0x10) /*!< Channel 4 Polarity */ +#define TPMx_POL_POL3 ((uint32_t)0x08) /*!< Channel 3 Polarity */ +#define TPMx_POL_POL2 ((uint32_t)0x04) /*!< Channel 2 Polarity */ +#define TPMx_POL_POL1 ((uint32_t)0x02) /*!< Channel 1 Polarity */ +#define TPMx_POL_POL0 ((uint32_t)0x01) /*!< Channel 0 Polarity */ + +/********** Bits definition for TPMx_CONF register *************/ +#define TPMx_CONF_TRGSEL_SHIFT 24 /*!< Trigger Select */ +#define TPMx_CONF_TRGSEL_MASK ((uint32_t)((uint32_t)0xF << TPMx_CONF_TRGSEL_SHIFT)) +#define TPMx_CONF_TRGSEL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_TRGSEL_SHIFT) & TPMx_CONF_TRGSEL_MASK)) +#define TPMx_CONF_TRGSRC ((uint32_t)0x800000) /*!< Trigger Source */ +#define TPMx_CONF_TRGPOL ((uint32_t)0x400000) /*!< Trigger Polarity */ +#define TPMx_CONF_CPOT ((uint32_t)0x80000) /*!< Counter Pause On Trigger */ +#define TPMx_CONF_CROT ((uint32_t)0x40000) /*!< Counter Reload On Trigger */ +#define TPMx_CONF_CSOO ((uint32_t)0x20000) /*!< Counter Stop On Overflow */ +#define TPMx_CONF_CSOT ((uint32_t)0x10000) /*!< Counter Start on Trigger */ +#define TPMx_CONF_GTBEEN ((uint32_t)0x200) /*!< Global time base enable */ +#define TPMx_CONF_GTBSYNC ((uint32_t)0x100) /*!< Global Time Base Synchronization */ +#define TPMx_CONF_DBGMODE_SHIFT 6 /*!< Debug Mode */ +#define TPMx_CONF_DBGMODE_MASK ((uint32_t)((uint32_t)0x3 << TPMx_CONF_DBGMODE_SHIFT)) +#define TPMx_CONF_DBGMODE(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_DBGMODE_SHIFT) & TPMx_CONF_DBGMODE_MASK)) +#define TPMx_CONF_DOZEEN ((uint32_t)0x20) /*!< Doze Enable */ + +/****************************************************************/ +/* */ +/* USBFS: Device dependent parts */ +/* */ +/****************************************************************/ +/******** Bits definition for USBx_USBTRC0 register *************/ +#define USBx_USBTRC0_USB_CLK_RECOVERY_INT ((uint8_t)0x04) /* Combined USB Clock Recovery interrupt status */ + +/****** Bits definition for USBx_KEEP_ALIVE_CTRL register *******/ +#define USBx_KEEP_ALIVE_CTRL_WAKE_INT_STS ((uint8_t)0x80) /*!< Wakeup Interrupt Status. */ +#define USBx_KEEP_ALIVE_CTRL_WAKE_INT_EN ((uint8_t)0x10) /*!< Wakeup Interrupt Enable. */ +#define USBx_KEEP_ALIVE_CTRL_AHB_DLY_EN ((uint8_t)0x08) /*!< Set to 1 to delay the first USB AHB bus transfer until after the USB has exited KEEP_ALIVE mode. */ +#define USBx_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN ((uint8_t)0x04) /*!< ... see manual ... */ +#define USBx_KEEP_ALIVE_CTRL_OWN_OVERRD_EN ((uint8_t)0x02) /*!< When set to 1, during KEEP_ALIVE mode, if received token is not SETUP, the OWN bit of current BD will be forced to 0, so usb core will response with NAK. */ +#define USBx_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN ((uint8_t)0x01) /*!< Global enable for USB_KEEP_ALIVE mode. */ + +/****** Bits definition for USBx_KEEP_ALIVE_WKCTRL register *****/ +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT 4 /*!< Which endpoint caused the wakeup interrupt. */ +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK ((uint8_t)((uint8_t)0xF << USBx_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT 0 /*!< Which token can wakeup usb */ +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK ((uint8_t)((uint8_t)0xF << USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) ((uint8_t)(((uint8_t)(x) << USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT) & USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK)) +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_OUTSETUP USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(1) +#define USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SETUPONLY USBx_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(0xD) + +/****** Bits definition for USBx_CLK_RECOVER_CTRL register ******/ +#define USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN ((uint8_t)0x80) /*!< Crystal-less USB enable */ +#define USBx_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN ((uint8_t)0x40) /*!< Reset/resume to rough phase enable */ +#define USBx_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN ((uint8_t)0x20) /*!< Restart from IFR trim value */ + +/****** Bits definition for USBx_CLK_RECOVER_IRC_EN register ****/ +#define USBx_CLK_RECOVER_IRC_EN_IRC_EN ((uint8_t)0x02) /*!< IRC48M enable */ + +/****** Bits definition for USBx_CLK_RECOVER_INT_EN register ****/ +#define USBx_CLK_RECOVER_INT_EN_OVF_ERROR_EN ((uint8_t)0x10) /*!< Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT. */ + +/*** Bits definition for USBx_CLK_RECOVER_INT_STATUS register ***/ +#define USBx_CLK_RECOVER_INT_STATUS_OVF_ERROR ((uint8_t)0x10) /*!< frequency trim adjustment needed for the IRC48M output clock is outside the available TRIM_FINE adjustment range */ + +/****************************************************************/ +/* */ +/* Reset Control Module (RCM) */ +/* */ +/****************************************************************/ +/* Device independent parts, plus: */ +/*********** Bits definition for RCM_FM register ****************/ +#define RCM_FM_FORCEROM_SHIFT 1 /*!< Force ROM Boot */ +#define RCM_FM_FORCEROM_MASK ((uint8_t)((uint8_t)0x03 << RCM_FM_FORCEROM_SHIFT)) +#define RCM_FM_FORCEROM(x) ((uint8_t)(((uint8_t)(x) << RCM_FM_FORCEROM_SHIFT) & RCM_FM_FORCEROM_MASK)) + +/*********** Bits definition for RCM_MR register ****************/ +#define RCM_MR_BOOTROM_SHIFT 1 /*!< Boot ROM Configuration */ +#define RCM_MR_BOOTROM_MASK ((uint8_t)((uint8_t)0x03 << RCM_MR_BOOTROM_SHIFT)) +#define RCM_MR_BOOTROM(x) ((uint8_t)(((uint8_t)(x) << RCM_MR_BOOTROM_SHIFT) & RCM_MR_BOOTROM_MASK)) +#define RCM_MR_BOOTROM_FROM_FLASH RCM_MR_BOOTROM(0) +#define RCM_MR_BOOTROM_FROM_ROM_BOOTCFG0 RCM_MR_BOOTROM(1) +#define RCM_MR_BOOTROM_FROM_ROM_FOPT RCM_MR_BOOTROM(2) +#define RCM_MR_BOOTROM_FROM_ROM_BOTH RCM_MR_BOOTROM(3) + +/********** Bits definition for RCM_SSRS0 register ************/ +#define RCM_SSRS0_SPOR ((uint8_t)0x80) /*!< Sticky Power-On Reset */ +#define RCM_SSRS0_SPIN ((uint8_t)0x40) /*!< Sticky External Reset Pin */ +#define RCM_SSRS0_SWDOG ((uint8_t)0x20) /*!< Sticky Watchdog */ +#define RCM_SSRS0_SLVD ((uint8_t)0x02) /*!< Sticky Low-Voltage Detect Reset */ +#define RCM_SSRS0_SWAKEUP ((uint8_t)0x01) /*!< Sticky Low Leakage Wakeup Reset */ + +/********** Bits definition for RCM_SSRS1 register *************/ +#define RCM_SSRS1_SSACKERR ((uint8_t)0x20) /*!< Sticky Stop Mode Acknowledge Error Reset */ +#define RCM_SSRS1_SMDM_AP ((uint8_t)0x08) /*!< Sticky MDM-AP System Reset Request */ +#define RCM_SSRS1_SSW ((uint8_t)0x04) /*!< Sticky Software */ +#define RCM_SSRS1_SLOCKUP ((uint8_t)0x02) /*!< Sticky Core Lockup */ + +/****************************************************************/ +/* */ +/* System Mode Controller (SMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Real Time Clock (RTC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Comparator (CMP) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Flash Memory Module (FTFA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Voltage Reference (VREFV1) */ +/* */ +/****************************************************************/ +/********** Bits definition for VREF_TRM register ***************/ +#define VREF_TRM_CHOPEN ((uint8_t)0x40) /*!< Chop oscillator enable. */ +#define VREF_TRM_TRIM_SHIFT 0 /*!< Trim bits */ +#define VREF_TRM_TRIM_MASK ((uint8_t)((uint8_t)0x3F << VREF_TRM_TRIM_SHIFT)) +#define VREF_TRM_TRIM(x) ((uint8_t)(((uint8_t)(x) << VREF_TRM_TRIM_SHIFT) & VREF_TRM_TRIM_MASK)) + +/********** Bits definition for VREF_SC register ****************/ +#define VREF_SC_VREFEN ((uint8_t)0x80) /*!< Internal Voltage Reference enable */ +#define VREF_SC_REGEN ((uint8_t)0x40) /*!< Regulator enable */ +#define VREF_SC_ICOMPEN ((uint8_t)0x20) /*!< Second order curvature compensation enable */ +#define VREF_SC_VREFST ((uint8_t)0x04) /*!< Internal Voltage Reference stable */ +#define VREF_SC_MODE_LV_SHIFT 0 /*!< Buffer Mode selection */ +#define VREF_SC_MODE_LV_MASK ((uint8_t)((uint8_t)0x3 << VREF_SC_MODE_LV_SHIFT)) +#define VREF_SC_MODE_LV(x) ((uint8_t)(((uint8_t)(x) << VREF_SC_MODE_LV_SHIFT) & VREF_SC_MODE_LV_MASK)) + +#define VREF_SC_MODE_LV_BANDGAP_ONLY VREF_SC_MODE_LV(0) +#define VREF_SC_MODE_LV_HIGH_POWER VREF_SC_MODE_LV(1) +#define VREF_SC_MODE_LV_LOW_POWER VREF_SC_MODE_LV(2) + +/****************************************************************/ +/* */ +/* Cyclic Redundancy Check (CRC) */ +/* */ +/****************************************************************/ +/********** Bits definition for CRC_DATA register ***************/ +#define CRC_DATA_HU_SHIFT 24 /*!< CRC High Upper Byte */ +#define CRC_DATA_HU_MASK ((uint32_t)((uint32_t)0xFF << CRC_DATA_HU_SHIFT)) +#define CRC_DATA_HU(x) ((uint32_t)(((uint32_t)(x) << CRC_DATA_HU_SHIFT) & CRC_DATA_HU_MASK)) +#define CRC_DATA_HL_SHIFT 16 /*!< CRC High Lower Byte */ +#define CRC_DATA_HL_MASK ((uint32_t)((uint32_t)0xFF << CRC_DATA_HL_SHIFT)) +#define CRC_DATA_HL(x) ((uint32_t)(((uint32_t)(x) << CRC_DATA_HL_SHIFT) & CRC_DATA_HL_MASK)) +#define CRC_DATA_LU_SHIFT 8 /*!< CRC Low Upper Byte */ +#define CRC_DATA_LU_MASK ((uint32_t)((uint32_t)0xFF << CRC_DATA_LU_SHIFT)) +#define CRC_DATA_LU(x) ((uint32_t)(((uint32_t)(x) << CRC_DATA_LU_SHIFT) & CRC_DATA_LU_MASK)) +#define CRC_DATA_LL_SHIFT 0 /*!< CRC Low Lower Byte */ +#define CRC_DATA_LL_MASK ((uint32_t)((uint32_t)0xFF << CRC_DATA_LL_SHIFT)) +#define CRC_DATA_LL(x) ((uint32_t)(((uint32_t)(x) << CRC_DATA_LL_SHIFT) & CRC_DATA_LL_MASK)) + +/********** Bits definition for CRC_GPOLY register **************/ +#define CRC_GPOLY_HIGH_SHIFT 16 /*!< High Polynominal Half-word */ +#define CRC_GPOLY_HIGH_MASK ((uint32_t)((uint32_t)0xFFFF << CRC_GPOLY_HIGH_SHIFT)) +#define CRC_GPOLY_HIGH(x) ((uint32_t)(((uint32_t)(x) << CRC_GPOLY_HIGH_SHIFT) & CRC_GPOLY_HIGH_MASK)) +#define CRC_GPOLY_LOW_SHIFT 0 /*!< Low Polynominal Half-word */ +#define CRC_GPOLY_LOW_MASK ((uint32_t)((uint32_t)0xFFFF << CRC_GPOLY_LOW_SHIFT)) +#define CRC_GPOLY_LOW(x) ((uint32_t)(((uint32_t)(x) << CRC_GPOLY_LOW_SHIFT) & CRC_GPOLY_LOW_MASK)) + +/********** Bits definition for CRC_CTRL register ***************/ +#define CRC_CTRL_TOT_SHIFT 30 /*!< Type Of Transpose For Writes */ +#define CRC_CTRL_TOT_MASK ((uint32_t)((uint32_t)0x3 << CRC_CTRL_TOT_SHIFT)) +#define CRC_CTRL_TOT(x) ((uint32_t)(((uint32_t)(x) << CRC_CTRL_TOT_SHIFT) & CRC_CTRL_TOT_MASK)) +#define CRC_CTRL_TOTR_SHIFT 28 /*!< Type Of Transpose For Read */ +#define CRC_CTRL_TOTR_MASK ((uint32_t)((uint32_t)0x3 << CRC_CTRL_TOTR_SHIFT)) +#define CRC_CTRL_TOTR(x) ((uint32_t)(((uint32_t)(x) << CRC_CTRL_TOTR_SHIFT) & CRC_CTRL_TOTR_MASK)) +#define CRC_CTRL_FXOR ((uint32_t)0x04000000) /*!< Complement Read Of CRC Data Register */ +#define CRC_CTRL_WAS ((uint32_t)0x02000000) /*!< Write CRC Data Register As Seed */ +#define CRC_CTRL_TCRC ((uint32_t)0x01000000) /*!< Width of CRC protocol. */ + +#endif /* _KL27ZXX_H_ */ diff --git a/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl27zxxx.h b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl27zxxx.h new file mode 100644 index 0000000..a4c966d --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl27zxxx.h @@ -0,0 +1,1216 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _KL27ZXXX_H_ +#define _KL27ZXXX_H_ + +/** + * @brief KL2x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __MPU_PRESENT 0 +#define __VTOR_PRESENT 1 +#define __NVIC_PRIO_BITS 2 +#define __Vendor_SysTickConfig 0 + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ****************/ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + +/****** KL2x Specific Interrupt Numbers ***********************/ + DMA0_IRQn = 0, + DMA1_IRQn = 1, + DMA2_IRQn = 2, + DMA3_IRQn = 3, + Reserved0_IRQn = 4, + FTFA_IRQn = 5, + PMC_IRQn = 6, + LLWU_IRQn = 7, + I2C0_IRQn = 8, + I2C1_IRQn = 9, + SPI0_IRQn = 10, + SPI1_IRQn = 11, + LPUART0_IRQn = 12, + LPUART1_IRQn = 13, + UART2_IRQn = 14, + ADC0_IRQn = 15, + CMP0_IRQn = 16, + TPM0_IRQn = 17, + TPM1_IRQn = 18, + TPM2_IRQn = 19, + RTC0_IRQn = 20, + RTC1_IRQn = 21, + PIT_IRQn = 22, + I2S0_IRQn = 23, + USB_IRQn = 24, + DAC0_IRQn = 25, + Reserved2_IRQn = 26, + Reserved3_IRQn = 27, + LPTMR0_IRQn = 28, + Reserved4_IRQn = 29, + PINA_IRQn = 30, + PINCD_IRQn = 31, +} IRQn_Type; + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +typedef struct +{ + __IO uint8_t C1; + __IO uint8_t C2; + uint8_t RESERVED0[4]; + __I uint8_t S; + uint8_t RESERVED1[1]; + __IO uint8_t SC; + uint8_t RESERVED2[15]; + __IO uint8_t MC; +} MCGLite_TypeDef; + +typedef struct +{ + __IO uint32_t SC; + __IO uint32_t CNT; + __IO uint32_t MOD; + struct { // Channels + __IO uint32_t SC; + __IO uint32_t V; + } C[6]; + uint32_t RESERVED0[5]; + __IO uint32_t STATUS; + uint32_t RESERVED1[7]; + __IO uint32_t POL; + uint32_t RESERVED2[4]; + __IO uint32_t CONF; +} TPM_TypeDef; + +typedef struct +{ + __IO uint8_t S; + __IO uint8_t BR; + __IO uint8_t C2; + __IO uint8_t C1; + __IO uint8_t ML; + __IO uint8_t MH; + __IO uint8_t DL; + __IO uint8_t DH; + uint8_t RESERVED0[2]; + __IO uint8_t CI; + __IO uint8_t C3; +} SPI_TypeDef; + +typedef struct +{ + __IO uint8_t A1; + __IO uint8_t F; + __IO uint8_t C1; + __IO uint8_t S; + __IO uint8_t D; + __IO uint8_t C2; + __IO uint8_t FLT; + __IO uint8_t RA; + __IO uint8_t SMB; + __IO uint8_t A2; + __IO uint8_t SLTH; + __IO uint8_t SLTL; + __IO uint8_t S2; +} I2C_TypeDef; + +typedef struct +{ + __IO uint32_t BAUD; + __IO uint32_t STAT; + __IO uint32_t CTRL; + __IO uint32_t DATA; + __IO uint32_t MATCH; +} LPUART_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __I uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t MA1; + __IO uint8_t MA2; + __IO uint8_t C4; + __IO uint8_t C5; +} UART_TypeDef; + +typedef struct +{ + __I uint32_t VERID; + __I uint32_t PARAM; + __IO uint32_t CTRL; + uint32_t RESERVED0[1]; + __IO uint32_t SHIFTSTAT; + __IO uint32_t SHIFTERR; + __IO uint32_t TIMSTAT; + uint32_t RESERVED1[1]; + __IO uint32_t SHIFTSIEN; + __IO uint32_t SHIFTEIEN; + __IO uint32_t TIMIEN; + uint32_t RESERVED2[1]; + __IO uint32_t SHIFTSDEN; + uint32_t RESERVED3[19]; + __IO uint32_t SHIFTCTL[4]; + uint32_t RESERVED4[28]; + __IO uint32_t SHIFTCFG[4]; + uint32_t RESERVED5[60]; + __IO uint32_t SHIFTBUF[4]; + uint32_t RESERVED6[28]; + __IO uint32_t SHIFTBUFBIS[4]; + uint32_t RESERVED7[28]; + __IO uint32_t SHIFTBUFBYS[4]; + uint32_t RESERVED8[28]; + __IO uint32_t SHIFTBUFBBS[4]; + uint32_t RESERVED9[28]; + __IO uint32_t TIMCTL[4]; + uint32_t RESERVED10[28]; + __IO uint32_t TIMCFG[4]; + uint32_t RESERVED11[28]; + __IO uint32_t TIMCMP[4]; +} FlexIO_TypeDef; + +typedef struct +{ + __IO uint8_t TRM; + __IO uint8_t SC; +} VREF_TypeDef; + +typedef struct { + __I uint8_t PERID; // 0x00 + uint8_t RESERVED0[3]; + __I uint8_t IDCOMP; // 0x04 + uint8_t RESERVED1[3]; + __I uint8_t REV; // 0x08 + uint8_t RESERVED2[3]; + __I uint8_t ADDINFO; // 0x0C + uint8_t RESERVED3[15]; + __IO uint8_t OTGCTL; // 0x1C + uint8_t RESERVED7[99]; + __IO uint8_t ISTAT; // 0x80 + uint8_t RESERVED8[3]; + __IO uint8_t INTEN; // 0x84 + uint8_t RESERVED9[3]; + __IO uint8_t ERRSTAT; // 0x88 + uint8_t RESERVED10[3]; + __IO uint8_t ERREN; // 0x8C + uint8_t RESERVED11[3]; + __I uint8_t STAT; // 0x90 + uint8_t RESERVED12[3]; + __IO uint8_t CTL; // 0x94 + uint8_t RESERVED13[3]; + __IO uint8_t ADDR; // 0x98 + uint8_t RESERVED14[3]; + __IO uint8_t BDTPAGE1; // 0x9C + uint8_t RESERVED15[3]; + __IO uint8_t FRMNUML; // 0xA0 + uint8_t RESERVED16[3]; + __IO uint8_t FRMNUMH; // 0xA4 + uint8_t RESERVED17[11]; + __IO uint8_t BDTPAGE2; // 0xB0 + uint8_t RESERVED20[3]; + __IO uint8_t BDTPAGE3; // 0xB4 + uint8_t RESERVED21[11]; + struct { + __IO uint8_t V; // 0xC0 + uint8_t RESERVED[3]; + } ENDPT[16]; + __IO uint8_t USBCTRL; // 0x100 + uint8_t RESERVED22[3]; + __I uint8_t OBSERVE; // 0x104 + uint8_t RESERVED23[3]; + __IO uint8_t CONTROL; // 0x108 + uint8_t RESERVED24[3]; + __IO uint8_t USBTRC0; // 0x10C + uint8_t RESERVED25[7]; + __IO uint8_t USBFRMADJUST; // 0x114 + uint8_t RESERVED26[43]; + __IO uint8_t CLK_RECOVER_CTRL; // 0x140 + uint8_t RESERVED27[3]; + __IO uint8_t CLK_RECOVER_IRC_EN; // 0x144 + uint8_t RESERVED28[15]; + __IO uint8_t CLK_RECOVER_INT_EN; // 0x154 + uint8_t RESERVED29[7]; + __IO uint8_t CLK_RECOVER_INT_STATUS; // 0x15c +} USBFS_TypeDef; + +typedef struct +{ + __I uint8_t SRS0; + __I uint8_t SRS1; + uint8_t RESERVED0[2]; + __IO uint8_t RPFC; + __IO uint8_t RPFW; + __IO uint8_t FM; + __IO uint8_t MR; + __IO uint8_t SSRS0; + __IO uint8_t SSRS1; +} RCM_TypeDef; + +typedef struct { + __IO uint32_t TCSR; // 0x00 + uint32_t RESERVED0[1]; + __IO uint32_t TCR2; // 0x08 + __IO uint32_t TCR3; // 0x0C + __IO uint32_t TCR4; // 0x10 + __IO uint32_t TCR5; // 0x14 + uint32_t RESERVED1[2]; + __O uint32_t TDR0; // 0x20 + uint32_t RESERVED2[15]; + __IO uint32_t TMR; // 0x60 + uint32_t RESERVED3[7]; + __IO uint32_t RCSR; // 0x80 + uint32_t RESERVED4[1]; + __IO uint32_t RCR2; // 0x88 + __IO uint32_t RCR3; // 0x8C + __IO uint32_t RCR4; // 0x90 + __IO uint32_t RCR5; // 0x94 + uint32_t RESERVED5[2]; + __I uint32_t RDR0; // 0xA0 + uint32_t RESERVED6[15]; + __IO uint32_t RMR; // 0xE0 + uint32_t RESERVED7[7]; + __IO uint32_t MCR; // 0x100 +} I2S_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ +#define DMA_BASE ((uint32_t)0x40008100) +#define FTFA_BASE ((uint32_t)0x40020000) +#define DMAMUX_BASE ((uint32_t)0x40021000) +#define I2S0_BASE ((uint32_t)0x4002F000) // TODO: registers not implemented +#define PIT_BASE ((uint32_t)0x40037000) +#define LPTPM0_BASE ((uint32_t)0x40038000) +#define LPTPM1_BASE ((uint32_t)0x40039000) +#define LPTPM2_BASE ((uint32_t)0x4003A000) +#define ADC0_BASE ((uint32_t)0x4003B000) +#define RTC_BASE ((uint32_t)0x4003D000) +#define DAC0_BASE ((uint32_t)0x4003F000) +#define LPTMR0_BASE ((uint32_t)0x40040000) +#define SRF_BASE ((uint32_t)0x40041000) +#define SIM_BASE ((uint32_t)0x40047000) +#define PORTA_BASE ((uint32_t)0x40049000) +#define PORTB_BASE ((uint32_t)0x4004A000) +#define PORTC_BASE ((uint32_t)0x4004B000) +#define PORTD_BASE ((uint32_t)0x4004C000) +#define PORTE_BASE ((uint32_t)0x4004D000) +#define LPUART0_BASE ((uint32_t)0x40054000) +#define LPUART1_BASE ((uint32_t)0x40055000) +#define FLEXIO_BASE ((uint32_t)0x4005F000) // TODO: register defs +#define MCGLITE_BASE ((uint32_t)0x40064000) +#define OSC0_BASE ((uint32_t)0x40065000) +#define I2C0_BASE ((uint32_t)0x40066000) +#define I2C1_BASE ((uint32_t)0x40067000) +#define UART2_BASE ((uint32_t)0x4006C000) +#define USBFS_BASE ((uint32_t)0x40072000) +#define CMP_BASE ((uint32_t)0x40073000) +#define VREF_BASE ((uint32_t)0x40074000) +#define SPI0_BASE ((uint32_t)0x40076000) +#define SPI1_BASE ((uint32_t)0x40077000) +#define LLWU_BASE ((uint32_t)0x4007C000) +#define PMC_BASE ((uint32_t)0x4007D000) +#define SMC_BASE ((uint32_t)0x4007E000) +#define RCM_BASE ((uint32_t)0x4007F000) +#define GPIOA_BASE ((uint32_t)0x400FF000) +#define GPIOB_BASE ((uint32_t)0x400FF040) +#define GPIOC_BASE ((uint32_t)0x400FF080) +#define GPIOD_BASE ((uint32_t)0x400FF0C0) +#define GPIOE_BASE ((uint32_t)0x400FF100) +#define MCM_BASE ((uint32_t)0xF0003000) + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define FTFA ((FTFA_TypeDef *) FTFA_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define I2S0 ((I2S_TypeDef *) I2S0_BASE) +#define PIT ((PIT_TypeDef *) PIT_BASE) +#define TPM0 ((TPM_TypeDef *) LPTPM0_BASE) +#define TPM1 ((TPM_TypeDef *) LPTPM1_BASE) +#define TPM2 ((TPM_TypeDef *) LPTPM2_BASE) +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define RTC0 ((RTC_TypeDef *) RTC0_BASE) +#define DAC0 ((DAC_TypeDef *) DAC0_BASE) +#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) +#define TSI0 ((TSI_TypeDef *) TSI0_BASE) +#define SIM ((SIM_TypeDef *) SIM_BASE) +#define LLWU ((LLWU_TypeDef *) LLWU_BASE) +#define PMC ((PMC_TypeDef *) PMC_BASE) +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) +#define PORTD ((PORT_TypeDef *) PORTD_BASE) +#define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define USB0 ((USBFS_TypeDef *) USBFS_BASE) +#define CMP ((CMP_TypeDef *) CMP_BASE) +#define VREF ((VREF_TypeDef *) VREF_BASE) +#define MCG ((MCGLite_TypeDef *) MCGLITE_BASE) +#define OSC0 ((OSC_TypeDef *) OSC0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define LPUART0 ((LPUART_TypeDef *) LPUART0_BASE) +#define LPUART1 ((LPUART_TypeDef *) LPUART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define FLEXIO ((FlexIO_TypeDef *) FLEXIO_BASE) +#define SMC ((SMC_TypeDef *) SMC_BASE) +#define RCM ((RCM_TypeDef *) RCM_BASE) +#define SYSTEM_REGISTER_FILE ((volatile uint8_t *) SRF_BASE) /* 32 bytes */ +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define MCM ((MCM_TypeDef *) MCM_BASE) + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ +/********* Bits definition for SIM_SOPT1 register *************/ +#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ +#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ +#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ +#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ +#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ +#define SIM_SOPT1_OSC32KOUT_SHIFT 16 /*!< 32K oscillator clock output (shift) */ +#define SIM_SOPT1_OSC32KOUT_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock output (mask) */ +#define SIM_SOPT1_OSC32KOUT(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock output */ + +/******* Bits definition for SIM_SOPT1CFG register ************/ +#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ +#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ +#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ + +/******* Bits definition for SIM_SOPT2 register ************/ +#define SIM_SOPT2_LPUART1SRC_SHIFT 28 /*!< LPUART1 clock source select (shift) */ +#define SIM_SOPT2_LPUART1SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_LPUART1SRC_SHIFT)) /*!< LPUART1 clock source select (mask) */ +#define SIM_SOPT2_LPUART1SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_LPUART1SRC_SHIFT) & SIM_SOPT2_LPUART1SRC_MASK)) /*!< LPUART1 clock source select */ +#define SIM_SOPT2_LPUART0SRC_SHIFT 26 /*!< LPUART0 clock source select (shift) */ +#define SIM_SOPT2_LPUART0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_LPUART0SRC_SHIFT)) /*!< LPUART0 clock source select (mask) */ +#define SIM_SOPT2_LPUART0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_LPUART0SRC_SHIFT) & SIM_SOPT2_LPUART0SRC_MASK)) /*!< UART0 clock source select */ +#define SIM_SOPT2_TPMSRC_SHIFT 24 /*!< TPM clock source select (shift) */ +#define SIM_SOPT2_TPMSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_TPMSRC_SHIFT)) /*!< TPM clock source select (mask) */ +#define SIM_SOPT2_TPMSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_TPMSRC_SHIFT) & SIM_SOPT2_TPMSRC_MASK)) /*!< TPM clock source select */ +#define SIM_SOPT2_FLEXIOSRC_SHIFT 22 /*!< FlexIO Module Clock Source Select (shift) */ +#define SIM_SOPT2_FLEXIOSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_FLEXIO_SHIFT)) /*!< FlexIO Module Clock Source Select (mask) */ +#define SIM_SOPT2_FLEXIOSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_FLEXIO_SHIFT) & SIM_SOPT2_FLEXIO_MASK)) /*!< FlexIO Module Clock Source Select */ +#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 /*!< CLKOUT select (shift) */ +#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x07 << SIM_SOPT2_CLKOUTSEL_SHIFT)) /*!< CLKOUT select (mask) */ +#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) /*!< CLKOUT select */ +#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ + +/******* Bits definition for SIM_SOPT4 register ************/ +#define SIM_SOPT4_TPM2CLKSEL ((uint32_t)0x04000000) /*!< TPM2 External Clock Pin Select */ +#define SIM_SOPT4_TPM1CLKSEL ((uint32_t)0x02000000) /*!< TPM1 External Clock Pin Select */ +#define SIM_SOPT4_TPM0CLKSEL ((uint32_t)0x01000000) /*!< TPM0 External Clock Pin Select */ +#define SIM_SOPT4_TPM2CH0SRC ((uint32_t)0x00100000) /*!< TPM2 channel 0 input capture source select */ +#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18 /*!< TPM1 channel 0 input capture source select (shift) */ +#define SIM_SOPT4_TPM1CH0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT4_TPM1CH0SRC_SHIFT)) /*!< TPM1 channel 0 input capture source select (mask) */ +#define SIM_SOPT4_TPM1CH0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT4_TPM1CH0SRC_SHIFT) & SIM_SOPT4_TPM1CH0SRC_MASK)) /*!< TPM1 channel 0 input capture source select */ + +/******* Bits definition for SIM_SOPT5 register ************/ +#define SIM_SOPT5_UART2ODE ((uint32_t)0x00040000) /*!< UART2 Open Drain Enable */ +#define SIM_SOPT5_LPUART1ODE ((uint32_t)0x00020000) /*!< LPUART1 Open Drain Enable */ +#define SIM_SOPT5_LPUART0ODE ((uint32_t)0x00010000) /*!< LPUART0 Open Drain Enable */ +#define SIM_SOPT5_LPUART1RXSRC ((uint32_t)0x00000040) /*!< LPUART1 receive data source select */ +#define SIM_SOPT5_LPUART1TXSRC_SHIFT 4 /*!< LPUART1 transmit data source select (shift) */ +#define SIM_SOPT5_LPUART1TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_LPUART1TXSRC_SHIFT)) /*!< LPUART1 transmit data source select (mask) */ +#define SIM_SOPT5_LPUART1TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_LPUART1TXSRC_SHIFT) & SIM_SOPT5_LPUART1TXSRC_MASK)) /*!< LPUART1 transmit data source select */ +#define SIM_SOPT5_LPUART0RXSRC ((uint32_t)0x00000040) /*!< LPUART0 receive data source select */ +#define SIM_SOPT5_LPUART0TXSRC_SHIFT 0 /*!< LPUART0 transmit data source select (shift) */ +#define SIM_SOPT5_LPUART0TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_LPUART0TXSRC_SHIFT)) /*!< LPUART0 transmit data source select (mask) */ +#define SIM_SOPT5_LPUART0TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_LPUART0TXSRC_SHIFT) & SIM_SOPT5_LPUART0TXSRC_MASK)) /*!< LPUART0 transmit data source select */ + +/******* Bits definition for SIM_SOPT7 register ************/ +#define SIM_SOPT7_ADC0ALTTRGEN ((uint32_t)0x00000080) /*!< ADC0 Alternate Trigger Enable */ +#define SIM_SOPT7_ADC0PRETRGSEL ((uint32_t)0x00000010) /*!< ADC0 Pretrigger Select */ +#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 /*!< ADC0 Trigger Select (shift) */ +#define SIM_SOPT7_ADC0TRGSEL_MASK ((uint32_t)((uint32_t)0x0F << SIM_SOPT7_ADC0TRGSEL_SHIFT)) /*!< ADC0 Trigger Select (mask) */ +#define SIM_SOPT7_ADC0TRGSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT7_ADC0TRGSEL_SHIFT) & SIM_SOPT7_ADC0TRGSEL_MASK)) /*!< ADC0 Trigger Select */ + +/******** Bits definition for SIM_SDID register ************/ +#define SIM_SDID_FAMID_SHIFT 28 /*!< Kinetis family ID (shift) */ +#define SIM_SDID_FAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_FAMID_SHIFT)) /*!< Kinetis family ID (mask) */ +#define SIM_SDID_SUBFAMID_SHIFT 24 /*!< Kinetis Sub-Family ID (shift) */ +#define SIM_SDID_SUBFAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SUBFAMID_SHIFT)) /*!< Kinetis Sub-Family ID (mask) */ +#define SIM_SDID_SERIESID_SHIFT 20 /*!< Kinetis Series ID (shift) */ +#define SIM_SDID_SERIESID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SERIESID_SHIFT)) /*!< Kinetis Series ID (mask) */ +#define SIM_SDID_SRAMSIZE_SHIFT 16 /*!< System SRAM Size (shift) */ +#define SIM_SDID_SRAMSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SRAMSIZE_SHIFT)) /*!< System SRAM Size (mask) */ +#define SIM_SDID_REVID_SHIFT 12 /*!< Device revision number (shift) */ +#define SIM_SDID_REVID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_REVID_SHIFT)) /*!< Device revision number (mask) */ +#define SIM_SDID_PINID_SHIFT 0 /*!< Pincount identification (shift) */ +#define SIM_SDID_PINID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_PINID_SHIFT)) /*!< Pincount identification (mask) */ + +/******* Bits definition for SIM_SCGC4 register ************/ +#define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) /*!< SPI1 Clock Gate Control */ +#define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) /*!< SPI0 Clock Gate Control */ +#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */ +#define SIM_SCGC4_CMP0 ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ +#define SIM_SCGC4_USBFS ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ +#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ +#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */ +#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ + +/******* Bits definition for SIM_SCGC5 register ************/ +#define SIM_SCGC5_FLEXIO ((uint32_t)0x80000000) /*!< FlexIO Module */ +#define SIM_SCGC5_LPUART1 ((uint32_t)0x00200000) /*!< LPUART1 Clock Gate Control */ +#define SIM_SCGC5_LPUART0 ((uint32_t)0x00100000) /*!< LPUART0 Clock Gate Control */ +#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ +#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ +#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ +#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ +#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ +#define SIM_SCGC5_LPTMR ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC6_DAC0 ((uint32_t)0x80000000) /*!< DAC0 Clock Gate Control */ +#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ +#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ +#define SIM_SCGC6_TPM2 ((uint32_t)0x04000000) /*!< TPM2 Clock Gate Control */ +#define SIM_SCGC6_TPM1 ((uint32_t)0x02000000) /*!< TPM1 Clock Gate Control */ +#define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) /*!< TPM0 Clock Gate Control */ +#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ +#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< I2S0 Clock Gate Control */ +#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ +#define SIM_SCGC6_FTF ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ + +/******* Bits definition for SIM_SCGC7 register ************/ +#define SIM_SCGC7_DMA ((uint32_t)0x00000100) /*!< DMA Clock Gate Control */ + +/****** Bits definition for SIM_CLKDIV1 register ***********/ +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 /*!< Clock 1 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0x0F << SIM_CLKDIV1_OUTDIV1_SHIFT)) /*!< Clock 1 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) /*!< Clock 1 output divider value */ +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 /*!< Clock 4 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x07 << SIM_CLKDIV1_OUTDIV4_SHIFT)) /*!< Clock 4 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) /*!< Clock 4 output divider value */ + +/******* Bits definition for SIM_FCFG1 register ************/ +#define SIM_FCFG1_PFSIZE_SHIFT 24 /*!< Program Flash Size (shift) */ +#define SIM_FCFG1_PFSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_FCFG1_PFSIZE_SHIFT)) /*!< Program Flash Size (mask) */ +#define SIM_FCFG1_FLASHDOZE ((uint32_t)0x00000002) /*!< Flash Doze */ +#define SIM_FCFG1_FLASHDIS ((uint32_t)0x00000001) /*!< Flash Disable */ + +/******* Bits definition for SIM_FCFG2 register ************/ +#define SIM_FCFG2_MAXADDR0_SHIFT 24 /*!< Max address lock (shift) */ +#define SIM_FCFG2_MAXADDR0_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR0_SHIFT)) /*!< Max address lock (mask) */ +#define SIM_FCFG2_MAXADDR1_SHIFT 16 /*!< Max address lock (block 1) (shift) */ +#define SIM_FCFG2_MAXADDR1_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR1_SHIFT)) /*!< Max address lock (block 1) (mask) */ + +/******* Bits definition for SIM_UIDMH register ************/ +#define SIM_UIDMH_UID_MASK ((uint32_t)0x0000FFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDML register ************/ +#define SIM_UIDML_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_UIDL register *************/ +#define SIM_UIDL_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */ + +/******* Bits definition for SIM_COPC register *************/ +#define SIM_COPC_COPCLKSEL_SHIFT 6 /*!< COP Clock Select (shift) */ +#define SIM_COPC_COPCLKSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_COPC_COPCLKSEL_SHIFT)) /*!< COP Clock Select (mask) */ +#define SIM_COPC_COPCLKSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_COPC_COPCLKSEL_SHIFT) & SIM_COPC_COPCLKSEL_MASK)) /*!< COP Clock Select */ +#define SIM_COPC_COPDBGEN ((uint32_t)0x00000020) /*!< COP Debug Enable */ +#define SIM_COPC_COPSTPEN ((uint32_t)0x00000010) /*!< COP Stop Enable */ +#define SIM_COPC_COPT_SHIFT 2 /*!< COP Watchdog Timeout (shift) */ +#define SIM_COPC_COPT_MASK ((uint32_t)((uint32_t)0x03 << SIM_COPC_COPT_SHIFT)) /*!< COP Watchdog Timeout (mask) */ +#define SIM_COPC_COPT(x) ((uint32_t)(((uint32_t)(x) << SIM_COPC_COPT_SHIFT) & SIM_COPC_COPT_MASK)) /*!< COP Watchdog Timeout */ +#define SIM_COPC_COPCLKS ((uint32_t)0x00000002) /*!< COP Clock Select */ +#define SIM_COPC_COPW ((uint32_t)0x00000001) /*!< COP windowed mode */ + +/******* Bits definition for SIM_SRVCOP register ***********/ +#define SIM_SRVCOP_SRVCOP_SHIFT 0 /*!< Sevice COP Register (shift) */ +#define SIM_SRVCOP_SRVCOP_MASK ((uint32_t)((uint32_t)0xFF << SIM_SRVCOP_SRVCOP_SHIFT)) /*!< Sevice COP Register (mask) */ +#define SIM_SRVCOP_SRVCOP(x) ((uint32_t)(((uint32_t)(x) << SIM_SRVCOP_SRVCOP_SHIFT) & SIM_SRVCOP_SRVCOP_MASK)) /*!< Sevice COP Register */ + + +/****************************************************************/ +/* */ +/* Low-Leakage Wakeup Unit (LLWU) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Port Control and interrupts (PORT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Oscillator (OSC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access (DMA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Direct Memory Access Multiplexer (DMAMUX) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Periodic Interrupt Timer (PIT) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Analog-to-Digital Converter (ADC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Low-Power Timer (LPTMR) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Multipurpose Clock Generator Lite (MCG_Lite) */ +/* */ +/****************************************************************/ +/*********** Bits definition for MCG_C1 register **************/ +#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */ +#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */ +#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */ +#define MCG_C1_CLKS_HIRC MCG_C1_CLKS(0) /*!< HIRC */ +#define MCG_C1_CLKS_LIRC MCG_C1_CLKS(1) /*!< LIRC (either LIRC2M or LIRC8M) */ +#define MCG_C1_CLKS_EXT MCG_C1_CLKS(2) /*!< EXT (external ref) */ +#define MCG_C1_IRCLKEN ((uint8_t)((uint8_t)1 << 1)) /*!< Internal Reference Clock Enable */ +#define MCG_C1_IREFSTEN ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Stop Enable */ + +/*********** Bits definition for MCG_C2 register **************/ +#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */ +#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x03 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */ +#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */ +#define MCG_C2_HGO0 ((uint8_t)((uint8_t)1 << 3)) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */ +#define MCG_C2_EREFS0 ((uint8_t)((uint8_t)1 << 2)) /*!< External Reference Select (0=clock; 1=oscillator) */ +#define MCG_C2_IRCS ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Select (0=slow; 1=fast) */ + +/************ Bits definition for MCG_S register **************/ +#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */ +#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x03 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */ +#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */ +#define MCG_S_CLKST_HIRC MCG_S_CLKST(0) +#define MCG_S_CLKST_LIRC MCG_S_CLKST(1) +#define MCG_S_CLKST_EXT MCG_S_CLKST(2) +#define MCG_S_OSCINIT0 ((uint8_t)((uint8_t)1 << 1)) /*!< OSC Initialization */ + +/************ Bits definition for MCG_SC register **************/ +#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */ +#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */ +#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */ +#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */ +#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */ +#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */ +#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */ +#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */ +#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */ +#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */ +#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */ + +/************ Bits definition for MCG_MC register *************/ +#define MCG_MC_HIRCEN ((uint8_t)0x80) /*!< High-frequency IRC Enable */ +#define MCG_MC_LIRC_DIV2_SHIFT 0 /*!< Second Low-frequency Internal Reference Clock Divider (shift) */ +#define MCG_MC_LIRC_DIV2_MASK ((uint8_t)((uint8_t)0x07 << MCG_MC_LIRC_DIV2_SHIFT)) /*!< Second Low-frequency Internal Reference Clock Divider (mask) */ +#define MCG_MC_LIRC_DIV2(x) ((uint8_t)(((uint8_t)(x) << MCG_MC_LIRC_DIV2_SHIFT) & MCG_MC_LIRC_DIV2_MASK)) /*!< Second Low-frequency Internal Reference Clock Divider */ +#define MCG_MC_LIRC_DIV2_DIV1 MCG_MC_LIRC_DIV2(0) /*!< Divide Factor is 1 */ +#define MCG_MC_LIRC_DIV2_DIV2 MCG_MC_LIRC_DIV2(1) /*!< Divide Factor is 2 */ +#define MCG_MC_LIRC_DIV2_DIV4 MCG_MC_LIRC_DIV2(2) /*!< Divide Factor is 4 */ +#define MCG_MC_LIRC_DIV2_DIV8 MCG_MC_LIRC_DIV2(3) /*!< Divide Factor is 8 */ +#define MCG_MC_LIRC_DIV2_DIV16 MCG_MC_LIRC_DIV2(4) /*!< Divide Factor is 16 */ +#define MCG_MC_LIRC_DIV2_DIV32 MCG_MC_LIRC_DIV2(5) /*!< Divide Factor is 32 */ +#define MCG_MC_LIRC_DIV2_DIV64 MCG_MC_LIRC_DIV2(6) /*!< Divide Factor is 64 */ +#define MCG_MC_LIRC_DIV2_DIV128 MCG_MC_LIRC_DIV2(7) /*!< Divide Factor is 128 */ + +/****************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/****************************************************************/ +/*********** Bits definition for SPIx_S register **************/ +#define SPIx_S_SPRF ((uint8_t)0x80) /*!< SPI Read Buffer Full Flag */ +#define SPIx_S_SPMF ((uint8_t)0x40) /*!< SPI Match Flag */ +#define SPIx_S_SPTEF ((uint8_t)0x20) /*!< SPI Transmit Buffer Empty Flag */ +#define SPIx_S_MODF ((uint8_t)0x10) /*!< Master Mode Fault Flag */ +#define SPIx_S_RNFULLF ((uint8_t)0x08) /*!< Receive FIFO nearly full flag */ +#define SPIx_S_TNEAREF ((uint8_t)0x04) /*!< Transmit FIFO nearly empty flag */ +#define SPIx_S_TXFULLF ((uint8_t)0x02) /*!< Transmit FIFO full flag */ +#define SPIx_S_RFIFOEF ((uint8_t)0x01) /*!< SPI read FIFO empty flag */ + +/*********** Bits definition for SPIx_BR register *************/ +#define SPIx_BR_SPPR_SHIFT 4 /*!< SPI Baud rate Prescaler Divisor */ +#define SPIx_BR_SPPR_MASK ((uint8_t)((uint8_t)0x7 << SPIx_BR_SPPR_SHIFT)) +#define SPIx_BR_SPPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPPR_SHIFT) & SPIx_BR_SPPR_MASK)) +#define SPIx_BR_SPR_SHIFT 0 /*!< SPI Baud rate Divisor */ +#define SPIx_BR_SPR_MASK ((uint8_t)((uint8_t)0x0F << SPIx_BR_SPR_SHIFT)) +#define SPIx_BR_SPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPR_SHIFT) & SPIx_BR_SPR_MASK)) + +/*********** Bits definition for SPIx_C2 register *************/ +#define SPIx_C2_SPMIE ((uint8_t)0x80) /*!< SPI Match Interrupt Enable */ +#define SPIx_C2_SPIMODE ((uint8_t)0x40) /*!< SPI 8-bit or 16-bit mode */ +#define SPIx_C2_TXDMAE ((uint8_t)0x20) /*!< Transmit DMA Enable */ +#define SPIx_C2_MODFEN ((uint8_t)0x10) /*!< Master Mode-Fault Function Enable */ +#define SPIx_C2_BIDIROE ((uint8_t)0x08) /*!< Bidirectional Mode Output Enable */ +#define SPIx_C2_RXDMAE ((uint8_t)0x04) /*!< Receive DMA Enable */ +#define SPIx_C2_SPISWAI ((uint8_t)0x02) /*!< SPI Stop in Wait Mode */ +#define SPIx_C2_SPC0 ((uint8_t)0x01) /*!< SPI Pin Control 0 */ + +/*********** Bits definition for SPIx_C1 register *************/ +#define SPIx_C1_SPIE ((uint8_t)0x80) /*!< SPI Interrupt Enable */ +#define SPIx_C1_SPE ((uint8_t)0x40) /*!< SPI System Enable */ +#define SPIx_C1_SPTIE ((uint8_t)0x20) /*!< SPI Transmit Interrupt Enable */ +#define SPIx_C1_MSTR ((uint8_t)0x10) /*!< Master/Slave Mode Select */ +#define SPIx_C1_CPOL ((uint8_t)0x08) /*!< Clock Polarity */ +#define SPIx_C1_CPHA ((uint8_t)0x04) /*!< Clock Phase */ +#define SPIx_C1_SSOE ((uint8_t)0x02) /*!< Slave Select Output Enable */ +#define SPIx_C1_LSBFE ((uint8_t)0x01) /*!< LSB First */ + +/*********** Bits definition for SPIx_ML register *************/ +#define SPIx_ML_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - low byte */ +#define SPIx_ML_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_ML_DATA_SHIFT)) +#define SPIx_ML_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_ML_DATA_SHIFT) & SPIx_ML_DATA_MASK)) + +/*********** Bits definition for SPIx_MH register *************/ +#define SPIx_MH_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - high byte */ +#define SPIx_MH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_MH_DATA_SHIFT)) +#define SPIx_MH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_MH_DATA_SHIFT) & SPIx_MH_DATA_MASK)) + +/*********** Bits definition for SPIx_DL register *************/ +#define SPIx_DL_DATA_SHIFT 0 /*!< Data - low byte */ +#define SPIx_DL_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DL_DATA_SHIFT)) +#define SPIx_DL_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DL_DATA_SHIFT) & SPIx_DL_DATA_MASK)) + +/*********** Bits definition for SPIx_DH register *************/ +#define SPIx_DH_DATA_SHIFT 0 /*!< Data - high byte */ +#define SPIx_DH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DH_DATA_SHIFT)) +#define SPIx_DH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DH_DATA_SHIFT) & SPIx_DH_DATA_MASK)) + +/*********** Bits definition for SPIx_CI register *************/ +#define SPIx_CI_TXFERR ((uint8_t)0x80) /*!< Transmit FIFO error flag */ +#define SPIx_CI_RXFERR ((uint8_t)0x40) /*!< Receive FIFO error flag */ +#define SPIx_CI_TXFOF ((uint8_t)0x20) /*!< Transmit FIFO overflow flag */ +#define SPIx_CI_RXFOF ((uint8_t)0x10) /*!< Receive FIFO overflow flag */ +#define SPIx_CI_TNEAREFCI ((uint8_t)0x08) /*!< Transmit FIFO nearly empty flag clear interrupt */ +#define SPIx_CI_RNFULLFCI ((uint8_t)0x04) /*!< Receive FIFO nearly full flag clear interrupt */ +#define SPIx_CI_SPTEFCI ((uint8_t)0x02) /*!< Transmit FIFO empty flag clear interrupt */ +#define SPIx_CI_SPRFCI ((uint8_t)0x01) /*!< Receive FIFO full flag clear interrupt */ + +/*********** Bits definition for SPIx_C3 register *************/ +#define SPIx_C3_TNEAREF_MARK ((uint8_t)0x20) /*!< Transmit FIFO nearly empty watermark */ +#define SPIx_C3_RNFULLF_MARK ((uint8_t)0x10) /*!< Receive FIFO nearly full watermark */ +#define SPIx_C3_INTCLR ((uint8_t)0x08) /*!< Interrupt clearing mechanism select */ +#define SPIx_C3_TNEARIEN ((uint8_t)0x04) /*!< Transmit FIFO nearly empty interrupt enable */ +#define SPIx_C3_RNFULLIEN ((uint8_t)0x02) /*!< Receive FIFO nearly full interrupt enable */ +#define SPIx_C3_FIFOMODE ((uint8_t)0x01) /*!< FIFO mode enable */ + +/****************************************************************/ +/* */ +/* Inter-Integrated Circuit (I2C): Device dependent part */ +/* */ +/****************************************************************/ +/*********** Bits definition for I2Cx_FLT register ************/ +#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ +#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ +#define I2Cx_FLT_SSIE ((uint8_t)0x20) /*!< I2C Bus Stop or Start Interrupt Enable */ +#define I2Cx_FLT_STARTF ((uint8_t)0x10) /*!< I2C Bus Start Detect Flag */ +#define I2Cx_FLT_FLT_SHIFT 0 /*!< I2C Programmable Filter Factor */ +#define I2Cx_FLT_FLT_MASK ((uint8_t)((uint8_t)0x0F << I2Cx_FLT_FLT_SHIFT)) +#define I2Cx_FLT_FLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_FLT_FLT_SHIFT) & I2Cx_FLT_FLT_MASK)) + +/*********** Bits definition for I2Cx_S2 register *************/ +#define I2Cx_S2_ERROR ((uint8_t)0x02) /*!< Error flag */ +#define I2Cx_S2_EMPTY ((uint8_t)0x01) /*!< Empty flag */ + +/****************************************************************/ +/* */ +/* Universal Asynchronous Receiver/Transmitter (UART) */ +/* */ +/****************************************************************/ +/********* Bits definition for UARTx_BDH register *************/ +#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RX Input Active Edge Interrupt Enable */ +#define UARTx_BDH_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDH_SBR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_BDH_SBR_SHIFT)) +#define UARTx_BDH_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDH_SBR_SHIFT) & UARTx_BDH_SBR_MASK)) + +/********* Bits definition for UARTx_BDL register *************/ +#define UARTx_BDL_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */ +#define UARTx_BDL_SBR_MASK ((uint8_t)((uint8_t)0xFF << UARTx_BDL_SBR_SHIFT)) +#define UARTx_BDL_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDL_SBR_SHIFT) & UARTx_BDL_SBR_MASK)) + +/********* Bits definition for UARTx_C1 register **************/ +#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ +#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */ +#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */ +#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */ +#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */ +#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */ +#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */ + +/********* Bits definition for UARTx_C2 register **************/ +#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */ +#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */ +#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */ +#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */ +#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */ +#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */ +#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */ +#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */ + +/********* Bits definition for UARTx_S1 register **************/ +#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */ +#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */ +#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */ +#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */ +#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */ +#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */ +#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */ +#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */ + +/********* Bits definition for UARTx_S2 register **************/ +#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */ +#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */ +#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */ +#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */ +#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */ +#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */ + +/********* Bits definition for UARTx_C3 register **************/ +#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */ +#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */ +#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */ +#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */ +#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */ +#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */ +#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */ +#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */ + +/********* Bits definition for UARTx_D register ***************/ +#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ +#define UARTx_D_RT_SHIFT 0 +#define UARTx_D_RT_MASK ((uint8_t)0xFF) + +/********* Bits definition for UARTx_MA1 register *************/ +#define UARTx_MA1_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA1_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA1_MA_SHIFT)) +#define UARTx_MA1_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA1_MA_SHIFT) & UARTx_MA1_MA_MASK)) + +/********* Bits definition for UARTx_MA2 register *************/ +#define UARTx_MA2_MA_SHIFT 0 /*!< Match Address */ +#define UARTx_MA2_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA2_MA_SHIFT)) +#define UARTx_MA2_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA2_MA_SHIFT) & UARTx_MA2_MA_MASK)) + +/********* Bits definition for UARTx_C4 register **************/ +#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ +#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */ +#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */ +#define UARTx_C4_OSR_SHIFT 0 /*!< Over Sampling Ratio */ +#define UARTx_C4_OSR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_C4_OSR_SHIFT)) +#define UARTx_C4_OSR(x) ((uint8_t)(((uint8_t)(x) << UARTx_C4_OSR_SHIFT) & UARTx_C4_OSR_MASK)) + +/********* Bits definition for UARTx_C5 register **************/ +#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */ +#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */ +#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */ +#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */ + +/****************************************************************/ +/* */ +/*Low Power Universal asynchronous receiver/transmitter (LPUART)*/ +/* */ +/****************************************************************/ +/********* Bits definition for LPUARTx_BAUD register **********/ +#define LPUARTx_BAUD_MAEN1 ((uint32_t)0x80000000) /*!< Match Address Mode Enable 1 */ +#define LPUARTx_BAUD_MAEN2 ((uint32_t)0x40000000) /*!< Match Address Mode Enable 2 */ +#define LPUARTx_BAUD_M10 ((uint32_t)0x20000000) /*!< 10-bit Mode select */ +#define LPUARTx_BAUD_OSR_SHIFT 24 /*!< Over Sampling Ratio (shift) */ +#define LPUARTx_BAUD_OSR_MASK ((uint32_t)((uint32_t)0x1F << LPUARTx_BAUD_OSR_SHIFT)) /*!< Over Sampling Ratio (mask) */ +#define LPUARTx_BAUD_OSR(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_BAUD_OSR_SHIFT) & LPUARTx_BAUD_OSR_MASK)) /*!< Over Sampling Ratio */ +#define LPUARTx_BAUD_TDMAE ((uint32_t)0x00800000) /*!< Transmitter DMA Enable */ +#define LPUARTx_BAUD_RDMAE ((uint32_t)0x00200000) /*!< Receiver Full DMA Enable */ +#define LPUARTx_BAUD_MATCFG_SHIFT 18 /*!< Match Configuration (shift) */ +#define LPUARTx_BAUD_MATCFG_MASK ((uint32_t)((uint32_t)0x03 << LPUARTx_BAUD_MATCFG_SHIFT)) /*!< Match Configuration (mask) */ +#define LPUARTx_BAUD_MATCFG(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_BAUD_MATCFG_SHIFT) & LPUARTx_BAUD_MATCFG_MASK)) /*!< Match Configuration */ +#define LPUARTx_BAUD_BOTHEDGE ((uint32_t)0x00020000) /*!< Both Edge Sampling */ +#define LPUARTx_BAUD_RESYNCDIS ((uint32_t)0x00010000) /*!< Resynchronization Disable */ +#define LPUARTx_BAUD_LBKDIE ((uint32_t)0x00008000) /*!< LIN Break Detect Interrupt Enable */ +#define LPUARTx_BAUD_RXEDGIE ((uint32_t)0x00004000) /*!< RX Input Active Edge Interrupt Enable */ +#define LPUARTx_BAUD_SBNS ((uint32_t)0x00002000) /*!< Stop Bit Number Select */ +#define LPUARTx_BAUD_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor (shift) */ +#define LPUARTx_BAUD_SBR_MASK ((uint32_t)((uint32_t)0x1FFF << LPUARTx_BAUD_SBR_SHIFT)) /*!< Baud Rate Modulo Divisor (mask) */ +#define LPUARTx_BAUD_SBR(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_BAUD_SBR_SHIFT) & LPUARTx_BAUD_SBR_MASK)) /*!< Baud Rate Modulo Divisor */ + +/********* Bits definition for LPUARTx_STAT register **********/ +#define LPUARTx_STAT_LBKDIF ((uint32_t)0x80000000) /*!< LIN Break Detect Interrupt Flag */ +#define LPUARTx_STAT_RXEDGIF ((uint32_t)0x40000000) /*!< LPUART_RX Pin Active Edge Interrupt Flag */ +#define LPUARTx_STAT_MSBF ((uint32_t)0x20000000) /*!< MSB First */ +#define LPUARTx_STAT_RXINV ((uint32_t)0x10000000) /*!< Receive Data Inversion */ +#define LPUARTx_STAT_RWUID ((uint32_t)0x08000000) /*!< Receive Wake Up Idle Detect */ +#define LPUARTx_STAT_BRK13 ((uint32_t)0x04000000) /*!< Break Character Generation Length */ +#define LPUARTx_STAT_LBKDE ((uint32_t)0x02000000) /*!< LIN Break Detection Enable */ +#define LPUARTx_STAT_RAF ((uint32_t)0x01000000) /*!< Receiver Active Flag */ +#define LPUARTx_STAT_TDRE ((uint32_t)0x00800000) /*!< Transmit Data Register Empty Flag */ +#define LPUARTx_STAT_TC ((uint32_t)0x00400000) /*!< Transmission Complete Flag */ +#define LPUARTx_STAT_RDRF ((uint32_t)0x00200000) /*!< Receive Data Register Full Flag */ +#define LPUARTx_STAT_IDLE ((uint32_t)0x00100000) /*!< Idle Line Flag */ +#define LPUARTx_STAT_OR ((uint32_t)0x00080000) /*!< Receiver Overrun Flag */ +#define LPUARTx_STAT_NF ((uint32_t)0x00040000) /*!< Noise Flag */ +#define LPUARTx_STAT_FE ((uint32_t)0x00020000) /*!< Framing Error Flag */ +#define LPUARTx_STAT_PF ((uint32_t)0x00010000) /*!< Parity Error Flag */ +#define LPUARTx_STAT_MA1F ((uint32_t)0x00008000) /*!< Match 1 Flag */ +#define LPUARTx_STAT_MA2F ((uint32_t)0x00004000) /*!< Match 2 Flag */ + +/********* Bits definition for LPUARTx_CTRL register **********/ +#define LPUARTx_CTRL_R8T9 ((uint32_t)0x80000000) /*!< Receive Bit 8 / Transmit Bit 9 */ +#define LPUARTx_CTRL_R9T8 ((uint32_t)0x40000000) /*!< Receive Bit 9 / Transmit Bit 8 */ +#define LPUARTx_CTRL_TXDIR ((uint32_t)0x20000000) /*!< LPUART_TX Pin Direction in Single-Wire Mode */ +#define LPUARTx_CTRL_TXINV ((uint32_t)0x10000000) /*!< Transmit Data Inversion */ +#define LPUARTx_CTRL_ORIE ((uint32_t)0x08000000) /*!< Overrun Interrupt Enable */ +#define LPUARTx_CTRL_NEIE ((uint32_t)0x04000000) /*!< Noise Error Interrupt Enable */ +#define LPUARTx_CTRL_FEIE ((uint32_t)0x02000000) /*!< Framing Error Interrupt Enable */ +#define LPUARTx_CTRL_PEIE ((uint32_t)0x01000000) /*!< Parity Error Interrupt Enable */ +#define LPUARTx_CTRL_TIE ((uint32_t)0x00800000) /*!< Transmit Interrupt Enable */ +#define LPUARTx_CTRL_TCIE ((uint32_t)0x00400000) /*!< Transmission Complete Interrupt Enable */ +#define LPUARTx_CTRL_RIE ((uint32_t)0x00200000) /*!< Receiver Interrupt Enable */ +#define LPUARTx_CTRL_ILIE ((uint32_t)0x00100000) /*!< Idle Line Interrupt Enable */ +#define LPUARTx_CTRL_TE ((uint32_t)0x00080000) /*!< Transmitter Enable */ +#define LPUARTx_CTRL_RE ((uint32_t)0x00040000) /*!< Receiver Enable */ +#define LPUARTx_CTRL_RWU ((uint32_t)0x00020000) /*!< Receiver Wakeup Control */ +#define LPUARTx_CTRL_SBK ((uint32_t)0x00010000) /*!< Send Break */ +#define LPUARTx_CTRL_MA1IE ((uint32_t)0x00008000) /*!< Match 1 Interrupt Enable */ +#define LPUARTx_CTRL_MA2IE ((uint32_t)0x00004000) /*!< Match 2 Interrupt Enable */ +#define LPUARTx_CTRL_IDLECFG_SHIFT 8 /*!< Idle Configuration (shift) */ +#define LPUARTx_CTRL_IDLECFG_MASK ((uint32_t)((uint32_t)0x7 << LPUARTx_CTRL_IDLECFG_SHIFT)) /*!< Idle Configuration (mask) */ +#define LPUARTx_CTRL_IDLECFG(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_CTRL_IDLECFG_SHIFT) & LPUARTx_CTRL_IDLECFG_MASK)) /*!< Idle Configuration */ +#define LPUARTx_CTRL_LOOPS ((uint32_t)0x00000080) /*!< Loop Mode Select */ +#define LPUARTx_CTRL_DOZEEN ((uint32_t)0x00000040) /*!< Doze Enable */ +#define LPUARTx_CTRL_RSRC ((uint32_t)0x00000020) /*!< Receiver Source Select */ +#define LPUARTx_CTRL_M ((uint32_t)0x00000010) /*!< 9-Bit or 8-Bit Mode Select */ +#define LPUARTx_CTRL_WAKE ((uint32_t)0x00000008) /*!< Receiver Wakeup Method Select */ +#define LPUARTx_CTRL_ILT ((uint32_t)0x00000004) /*!< Idle Line Type Select */ +#define LPUARTx_CTRL_PE ((uint32_t)0x00000002) /*!< Parity Enable */ +#define LPUARTx_CTRL_PT ((uint32_t)0x00000001) /*!< Parity Type */ + +/********* Bits definition for LPUARTx_DATA register **********/ +#define LPUARTx_DATA_NOISY ((uint32_t)0x00008000) /*!< The current received dataword contained in DATA[R9:R0] was received with noise */ +#define LPUARTx_DATA_PARITYE ((uint32_t)0x00004000) /*!< The current received dataword contained in DATA[R9:R0] was received with a parity error */ +#define LPUARTx_DATA_FRETSC ((uint32_t)0x00002000) /*!< Frame Error / Transmit Special Character */ +#define LPUARTx_DATA_RXEMPT ((uint32_t)0x00001000) /*!< Receive Buffer Empty */ +#define LPUARTx_DATA_IDLINE ((uint32_t)0x00000800) /*!< Idle Line */ +#define LPUARTx_DATA_R9T9 ((uint32_t)0x00000200) /*!< Read receive data buffer 9 or write transmit data buffer 9 */ +#define LPUARTx_DATA_R8T8 ((uint32_t)0x00000100) /*!< Read receive data buffer 8 or write transmit data buffer 8 */ +#define LPUARTx_DATA_R7T7 ((uint32_t)0x00000080) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define LPUARTx_DATA_R6T6 ((uint32_t)0x00000040) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define LPUARTx_DATA_R5T5 ((uint32_t)0x00000020) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define LPUARTx_DATA_R4T4 ((uint32_t)0x00000010) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define LPUARTx_DATA_R3T3 ((uint32_t)0x00000008) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define LPUARTx_DATA_R2T2 ((uint32_t)0x00000004) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define LPUARTx_DATA_R1T1 ((uint32_t)0x00000002) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define LPUARTx_DATA_R0T0 ((uint32_t)0x00000001) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ +#define LPUARTx_DATA_DATA_SHIFT 0 /*!< Data (shift) */ +#define LPUARTx_DATA_DATA_MASK ((uint32_t)((uint32_t)0x3F << LPUARTx_DATA_DATA_SHIFT)) /*!< Data (mask) */ +#define LPUARTx_DATA_DATA(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_DATA_DATA_SHIFT) & LPUARTx_DATA_DATA_MASK)) /*!< Data */ + +/********* Bits definition for LPUARTx_MATCH register *********/ +#define LPUARTx_MATCH_MA2_SHIFT 16 /*!< Match Address 2 (shift) */ +#define LPUARTx_MATCH_MA2_MASK ((uint32_t)((uint32_t)0x3F << LPUARTx_MATCH_MA2_SHIFT)) /*!< Match Address 2 (mask) */ +#define LPUARTx_MATCH_MA2(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_MATCH_MA2_SHIFT) & LPUARTx_MATCH_MA2_MASK)) /*!< Match Address 2 */ +#define LPUARTx_MATCH_MA1_SHIFT 0 /*!< Match Address 1 (shift) */ +#define LPUARTx_MATCH_MA1_MASK ((uint32_t)((uint32_t)0x3F << LPUARTx_MATCH_MA1_SHIFT)) /*!< Match Address 1 (mask) */ +#define LPUARTx_MATCH_MA1(x) ((uint32_t)(((uint32_t)(x) << LPUARTx_MATCH_MA1_SHIFT) & LPUARTx_MATCH_MA1_MASK)) /*!< Match Address 1 */ + +/****************************************************************/ +/* */ +/* Power Management Controller (PMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Timer/PWM Module (TPM) */ +/* */ +/****************************************************************/ +/********** Bits definition for TPMx_SC register ***************/ +#define TPMx_SC_DMA ((uint32_t)0x100) /*!< DMA Enable */ +#define TPMx_SC_TOF ((uint32_t)0x80) /*!< Timer Overflow Flag */ +#define TPMx_SC_TOIE ((uint32_t)0x40) /*!< Timer Overflow Interrupt Enable */ +#define TPMx_SC_CPWMS ((uint32_t)0x20) /*!< Center-aligned PWM Select */ +#define TPMx_SC_CMOD_SHIFT 3 /*!< Clock Mode Selection */ +#define TPMx_SC_CMOD_MASK ((uint32_t)((uint32_t)0x3 << TPMx_SC_CMOD_SHIFT)) +#define TPMx_SC_CMOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_CMOD_SHIFT) & TPMx_SC_CMOD_MASK)) +#define TPMx_SC_PS_SHIFT 0 /*!< Prescale Factor Selection */ +#define TPMx_SC_PS_MASK ((uint32_t)((uint32_t)0x7 << TPMx_SC_PS_SHIFT)) +#define TPMx_SC_PS(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_PS_SHIFT) & TPMx_SC_PS_MASK)) + +/********** Bits definition for TPMx_CNT register **************/ +#define TPMx_CNT_COUNT_SHIFT 0 /*!< Counter Value */ +#define TPMx_CNT_COUNT_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CNT_COUNT_SHIFT)) +#define TPMx_CNT_COUNT(x) ((uint32_t)(((uint32_t)(x) << TPMx_CNT_COUNT_SHIFT) & TPMx_CNT_COUNT_MASK)) + +/********** Bits definition for TPMx_MOD register **************/ +#define TPMx_MOD_MOD_SHIFT 0 /*!< Modulo Value */ +#define TPMx_MOD_MOD_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_MOD_MOD_SHIFT)) +#define TPMx_MOD_MOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_MOD_MOD_SHIFT) & TPMx_MOD_MOD_MASK)) + +/********** Bits definition for TPMx_CnSC register *************/ +#define TPMx_CnSC_CHF ((uint32_t)0x80) /*!< Channel Flag */ +#define TPMx_CnSC_CHIE ((uint32_t)0x40) /*!< Channel Interrupt Enable */ +#define TPMx_CnSC_MSB ((uint32_t)0x20) /*!< Channel Mode Select */ +#define TPMx_CnSC_MSA ((uint32_t)0x10) /*!< Channel Mode Select */ +#define TPMx_CnSC_ELSB ((uint32_t)0x8) /*!< Edge or Level Select */ +#define TPMx_CnSC_ELSA ((uint32_t)0x4) /*!< Edge or Level Select */ +#define TPMx_CnSC_DMA ((uint32_t)0x1) /*!< DMA Enable */ + +/********** Bits definition for TPMx_CnV register **************/ +#define TPMx_CnV_VAL_SHIFT 0 /*!< Channel Value */ +#define TPMx_CnV_VAL_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CnV_VAL_SHIFT)) +#define TPMx_CnV_VAL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CnV_VAL_SHIFT) & TPMx_CnV_VAL_MASK)) + +/********* Bits definition for TPMx_STATUS register ************/ +#define TPMx_STATUS_TOF ((uint32_t)0x100) /*!< Timer Overflow Flag */ +#define TPMx_STATUS_CH5F ((uint32_t)0x20) /*!< Channel 5 Flag */ +#define TPMx_STATUS_CH4F ((uint32_t)0x10) /*!< Channel 4 Flag */ +#define TPMx_STATUS_CH3F ((uint32_t)0x8) /*!< Channel 3 Flag */ +#define TPMx_STATUS_CH2F ((uint32_t)0x4) /*!< Channel 2 Flag */ +#define TPMx_STATUS_CH1F ((uint32_t)0x2) /*!< Channel 1 Flag */ +#define TPMx_STATUS_CH0F ((uint32_t)0x1) /*!< Channel 0 Flag */ + +/********** Bits definition for TPMx_POL register **************/ +#define TPMx_POL_POL5 ((uint32_t)0x20) /*!< Channel 5 Polarity */ +#define TPMx_POL_POL4 ((uint32_t)0x10) /*!< Channel 4 Polarity */ +#define TPMx_POL_POL3 ((uint32_t)0x08) /*!< Channel 3 Polarity */ +#define TPMx_POL_POL2 ((uint32_t)0x04) /*!< Channel 2 Polarity */ +#define TPMx_POL_POL1 ((uint32_t)0x02) /*!< Channel 1 Polarity */ +#define TPMx_POL_POL0 ((uint32_t)0x01) /*!< Channel 0 Polarity */ + +/********** Bits definition for TPMx_CONF register *************/ +#define TPMx_CONF_TRGSEL_SHIFT 24 /*!< Trigger Select */ +#define TPMx_CONF_TRGSEL_MASK ((uint32_t)((uint32_t)0xF << TPMx_CONF_TRGSEL_SHIFT)) +#define TPMx_CONF_TRGSEL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_TRGSEL_SHIFT) & TPMx_CONF_TRGSEL_MASK)) +#define TPMx_CONF_TRGSRC ((uint32_t)0x800000) /*!< Trigger Source */ +#define TPMx_CONF_TRGPOL ((uint32_t)0x400000) /*!< Trigger Polarity */ +#define TPMx_CONF_CPOT ((uint32_t)0x80000) /*!< Counter Pause On Trigger */ +#define TPMx_CONF_CROT ((uint32_t)0x40000) /*!< Counter Reload On Trigger */ +#define TPMx_CONF_CSOO ((uint32_t)0x20000) /*!< Counter Stop On Overflow */ +#define TPMx_CONF_CSOT ((uint32_t)0x10000) /*!< Counter Start on Trigger */ +#define TPMx_CONF_GTBEEN ((uint32_t)0x200) /*!< Global time base enable */ +#define TPMx_CONF_GTBSYNC ((uint32_t)0x100) /*!< Global Time Base Synchronization */ +#define TPMx_CONF_DBGMODE_SHIFT 6 /*!< Debug Mode */ +#define TPMx_CONF_DBGMODE_MASK ((uint32_t)((uint32_t)0x3 << TPMx_CONF_DBGMODE_SHIFT)) +#define TPMx_CONF_DBGMODE(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_DBGMODE_SHIFT) & TPMx_CONF_DBGMODE_MASK)) +#define TPMx_CONF_DOZEEN ((uint32_t)0x20) /*!< Doze Enable */ + +/****************************************************************/ +/* */ +/* USBFS: Device dependent parts */ +/* */ +/****************************************************************/ +/******** Bits definition for USBx_USBTRC0 register *************/ +#define USBx_USBTRC0_USB_CLK_RECOVERY_INT ((uint8_t)0x04) /* Combined USB Clock Recovery interrupt status */ + +/****** Bits definition for USBx_CLK_RECOVER_CTRL register ******/ +#define USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN ((uint8_t)0x80) /*!< Crystal-less USB enable */ +#define USBx_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN ((uint8_t)0x40) /*!< Reset/resume to rough phase enable */ +#define USBx_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN ((uint8_t)0x20) /*!< Restart from IFR trim value */ + +/****** Bits definition for USBx_CLK_RECOVER_IRC_EN register ****/ +#define USBx_CLK_RECOVER_IRC_EN_IRC_EN ((uint8_t)0x02) /*!< IRC48M enable */ + +/****** Bits definition for USBx_CLK_RECOVER_INT_EN register ****/ +#define USBx_CLK_RECOVER_INT_EN_OVF_ERROR_EN ((uint8_t)0x10) /*!< Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT. */ + +/*** Bits definition for USBx_CLK_RECOVER_INT_STATUS register ***/ +#define USBx_CLK_RECOVER_INT_STATUS_OVF_ERROR ((uint8_t)0x10) /*!< frequency trim adjustment needed for the IRC48M output clock is outside the available TRIM_FINE adjustment range */ + +/****************************************************************/ +/* */ +/* Reset Control Module (RCM) */ +/* */ +/****************************************************************/ +/* Device independent parts, plus: */ +/*********** Bits definition for RCM_FM register ****************/ +#define RCM_FM_FORCEROM_SHIFT 1 /*!< Force ROM Boot */ +#define RCM_FM_FORCEROM_MASK ((uint8_t)((uint8_t)0x03 << RCM_FM_FORCEROM_SHIFT)) +#define RCM_FM_FORCEROM(x) ((uint8_t)(((uint8_t)(x) << RCM_FM_FORCEROM_SHIFT) & RCM_FM_FORCEROM_MASK)) + +/*********** Bits definition for RCM_MR register ****************/ +#define RCM_MR_BOOTROM_SHIFT 1 /*!< Boot ROM Configuration */ +#define RCM_MR_BOOTROM_MASK ((uint8_t)((uint8_t)0x03 << RCM_MR_BOOTROM_SHIFT)) +#define RCM_MR_BOOTROM(x) ((uint8_t)(((uint8_t)(x) << RCM_MR_BOOTROM_SHIFT) & RCM_MR_BOOTROM_MASK)) +#define RCM_MR_BOOTROM_FROM_FLASH RCM_MR_BOOTROM(0) +#define RCM_MR_BOOTROM_FROM_ROM_BOOTCFG0 RCM_MR_BOOTROM(1) +#define RCM_MR_BOOTROM_FROM_ROM_FOPT RCM_MR_BOOTROM(2) +#define RCM_MR_BOOTROM_FROM_ROM_BOTH RCM_MR_BOOTROM(3) + +/********** Bits definition for RCM_SSRS0 register ************/ +#define RCM_SSRS0_SPOR ((uint8_t)0x80) /*!< Sticky Power-On Reset */ +#define RCM_SSRS0_SPIN ((uint8_t)0x40) /*!< Sticky External Reset Pin */ +#define RCM_SSRS0_SWDOG ((uint8_t)0x20) /*!< Sticky Watchdog */ +#define RCM_SSRS0_SLVD ((uint8_t)0x02) /*!< Sticky Low-Voltage Detect Reset */ +#define RCM_SSRS0_SWAKEUP ((uint8_t)0x01) /*!< Sticky Low Leakage Wakeup Reset */ + +/********** Bits definition for RCM_SSRS1 register *************/ +#define RCM_SSRS1_SSACKERR ((uint8_t)0x20) /*!< Sticky Stop Mode Acknowledge Error Reset */ +#define RCM_SSRS1_SMDM_AP ((uint8_t)0x08) /*!< Sticky MDM-AP System Reset Request */ +#define RCM_SSRS1_SSW ((uint8_t)0x04) /*!< Sticky Software */ +#define RCM_SSRS1_SLOCKUP ((uint8_t)0x02) /*!< Sticky Core Lockup */ + +/****************************************************************/ +/* */ +/* System Mode Controller (SMC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Digital-to-Analog Converter (DAC) */ +/* */ +/****************************************************************/ + +/* Mostly Device independent */ + +#define DACx_C1_DACBFMD_SHIFT 1 /*!< DAC Buffer Work Mode Select */ +#define DACx_C1_DACBFMD_MASK ((uint8_t)((uint8_t)0x03 << DACx_C1_DACBFMD_ SHIFT)) +#define DACx_C1_DACBFMD(x) ((uint8_t)(((uint8_t)(x) << DACx_C1_DACBFMD_SHIFT) & DACx_C1_DACBFMD_MASK)) + +#define DACx_C1_DACBFMD_MODE_NORMAL 0x0 +#define DACx_C1_DACBFMD_MODE_OTS 0x2 +#define DACx_C1_DACBFMD_MODE_FIFO 0x3 + +/****************************************************************/ +/* */ +/* Real Time Clock (RTC) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Comparator (CMP) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Flash Memory Module (FTFA) */ +/* */ +/****************************************************************/ + +/* Device independent */ + +/****************************************************************/ +/* */ +/* Voltage Reference (VREFV1) */ +/* */ +/****************************************************************/ +/********** Bits definition for VREF_TRM register ***************/ +#define VREF_TRM_CHOPEN ((uint8_t)0x40) /*!< Chop oscillator enable. */ +#define VREF_TRM_TRIM_SHIFT 0 /*!< Trim bits */ +#define VREF_TRM_TRIM_MASK ((uint8_t)((uint8_t)0x3F << VREF_TRM_TRIM_SHIFT)) +#define VREF_TRM_TRIM(x) ((uint8_t)(((uint8_t)(x) << VREF_TRM_TRIM_SHIFT) & VREF_TRM_TRIM_MASK)) + +/********** Bits definition for VREF_SC register ****************/ +#define VREF_SC_VREFEN ((uint8_t)0x80) /*!< Internal Voltage Reference enable */ +#define VREF_SC_REGEN ((uint8_t)0x40) /*!< Regulator enable */ +#define VREF_SC_ICOMPEN ((uint8_t)0x20) /*!< Second order curvature compensation enable */ +#define VREF_SC_VREFST ((uint8_t)0x04) /*!< Internal Voltage Reference stable */ +#define VREF_SC_MODE_LV_SHIFT 0 /*!< Buffer Mode selection */ +#define VREF_SC_MODE_LV_MASK ((uint8_t)((uint8_t)0x3 << VREF_SC_MODE_LV_SHIFT)) +#define VREF_SC_MODE_LV(x) ((uint8_t)(((uint8_t)(x) << VREF_SC_MODE_LV_SHIFT) & VREF_SC_MODE_LV_MASK)) + +#define VREF_SC_MODE_LV_BANDGAP_ONLY VREF_SC_MODE_LV(0) +#define VREF_SC_MODE_LV_HIGH_POWER VREF_SC_MODE_LV(1) +#define VREF_SC_MODE_LV_LOW_POWER VREF_SC_MODE_LV(2) + +#endif /* _KL27ZXXX_H_ */ diff --git a/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl2xz.h b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl2xz.h new file mode 100644 index 0000000..10dfecf --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ext/CMSIS/KINETIS/kl2xz.h @@ -0,0 +1,1218 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _KL2xZ_H_ +#define _KL2xZ_H_ + +/* + * Include the correct MCU specific header + */ +#if defined(KL25) /* MKL25Z* MCUs */ +#include "kl25z.h" +#elif defined(KL26) /* MKL26Z* MCUs */ +#include "kl26z.h" +#elif defined(KL27Zxxx) /* MKL25Z128* and MKL27Z256* MCUs */ +#include "kl27zxxx.h" +#elif defined(KL27Zxx) /* MKL25Z32* and MKL27Z64* MCUs */ +#include "kl27zxx.h" +#else +#error Please select a supported target MCU in your board.h +#endif + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ + +/* Device dependent */ + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +typedef struct +{ + __IO uint32_t SOPT1; + __IO uint32_t SOPT1CFG; + uint32_t RESERVED0[1023]; + __IO uint32_t SOPT2; + __I uint32_t RESERVED1[1]; + __IO uint32_t SOPT4; + __IO uint32_t SOPT5; + uint32_t RESERVED2[1]; + __IO uint32_t SOPT7; + uint32_t RESERVED3[2]; + __IO uint32_t SDID; + uint32_t RESERVED4[3]; + __IO uint32_t SCGC4; + __IO uint32_t SCGC5; + __IO uint32_t SCGC6; + __IO uint32_t SCGC7; + __IO uint32_t CLKDIV1; + uint32_t RESERVED5[1]; + __IO uint32_t FCFG1; + __IO uint32_t FCFG2; + uint32_t RESERVED6[1]; + __IO uint32_t UIDMH; + __IO uint32_t UIDML; + __IO uint32_t UIDL; + uint32_t RESERVED7[39]; + __IO uint32_t COPC; + __IO uint32_t SRVCOP; +} SIM_TypeDef; + +typedef struct +{ + __IO uint8_t PE1; + __IO uint8_t PE2; + __IO uint8_t PE3; + __IO uint8_t PE4; + __IO uint8_t ME; + __IO uint8_t F1; + __IO uint8_t F2; + __I uint8_t F3; + __IO uint8_t FILT1; + __IO uint8_t FILT2; +} LLWU_TypeDef; + +typedef struct +{ + __IO uint32_t PCR[32]; + __IO uint32_t GPCLR; + __IO uint32_t GPCHR; + uint32_t RESERVED0[6]; + __IO uint32_t ISFR; +} PORT_TypeDef; + +/* Device dependent + MCG_TypeDef; +*/ + +typedef struct +{ + __IO uint8_t CR; +} OSC_TypeDef; + +typedef struct +{ + __IO uint32_t SAR; + __IO uint32_t DAR; + __IO uint32_t DSR_BCR; + __IO uint32_t DCR; +} DMAChannel_TypeDef; + +typedef struct +{ + DMAChannel_TypeDef ch[4]; +} DMA_TypeDef; + +typedef struct +{ + __IO uint8_t CHCFG[4]; +} DMAMUX_TypeDef; + +typedef struct { + __IO uint32_t MCR; /* PIT Module Control Register */ + __I uint32_t LTMR64H; /* PIT Module Control Register */ + __I uint32_t LTMR64L; /* PIT Lower Lifetime Timer Register */ + uint8_t RESERVED0[244]; + struct PIT_CHANNEL { + __IO uint32_t LDVAL; /* Timer Load Value Register */ + __I uint32_t CVAL; /* Current Timer Value Register */ + __IO uint32_t TCTRL; /* Timer Control Register */ + __IO uint32_t TFLG; /* Timer Flag Register */ + } CHANNEL[2]; +} PIT_TypeDef; + +/* Device dependent + TPM_TypeDef; +*/ + +typedef struct +{ + __IO uint32_t SC1A; // ADC Status and Control Registers 1 + __IO uint32_t SC1B; // ADC Status and Control Registers 1 + __IO uint32_t CFG1; // ADC Configuration Register 1 + __IO uint32_t CFG2; // ADC Configuration Register 2 + __I uint32_t RA; // ADC Data Result Register + __I uint32_t RB; // ADC Data Result Register + __IO uint32_t CV1; // Compare Value Registers + __IO uint32_t CV2; // Compare Value Registers + __IO uint32_t SC2; // Status and Control Register 2 + __IO uint32_t SC3; // Status and Control Register 3 + __IO uint32_t OFS; // ADC Offset Correction Register + __IO uint32_t PG; // ADC Plus-Side Gain Register + __IO uint32_t MG; // ADC Minus-Side Gain Register + __IO uint32_t CLPD; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLPS; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP4; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP3; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP2; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP1; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP0; // ADC Plus-Side General Calibration Value Register + uint32_t RESERVED0[1]; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLMD; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLMS; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM4; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM3; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM2; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM1; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM0; // ADC Minus-Side General Calibration Value Register +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; + __IO uint32_t PSR; + __IO uint32_t CMR; + __I uint32_t CNR; +} LPTMR_TypeDef; + +/* Device dependent (TSI or FlexIO) + TSI_TypeDef; +*/ + +typedef struct +{ + __IO uint32_t PDOR; + __IO uint32_t PSOR; + __IO uint32_t PCOR; + __IO uint32_t PTOR; + __IO uint32_t PDIR; + __IO uint32_t PDDR; +} GPIO_TypeDef; + +/* Device dependent + SPI_TypeDef; +*/ + +/* Device dependent + I2C_TypeDef; +*/ + +/* Device dependent + UART_TypeDef; +*/ + +/* Device dependent + LPUART_Typedef; +*/ + +typedef struct +{ + __IO uint8_t LVDSC1; + __IO uint8_t LVDSC2; + __IO uint8_t REGSC; +} PMC_TypeDef; + +/* Device dependent + USBOTG_TypeDef; +*/ + +/* Device dependent + RCM_TypeDef; +*/ + +typedef struct +{ + __IO uint8_t PMPROT; + __IO uint8_t PMCTRL; + __IO uint8_t STOPCTRL; + __I uint8_t PMSTAT; +} SMC_TypeDef; + +typedef struct +{ + struct { + __IO uint8_t DATL; + __IO uint8_t DATH; + } DAT[2]; + uint8_t RESERVED0[28]; + __IO uint8_t SR; + __IO uint8_t C0; + __IO uint8_t C1; + __IO uint8_t C2; +} DAC_TypeDef; + +typedef struct +{ + __IO uint32_t TSR; + __IO uint32_t TPR; + __IO uint32_t TAR; + __IO uint32_t TCR; + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t LR; + __IO uint32_t IER; +} RTC_TypeDef; + +typedef struct +{ + __IO uint8_t CR0; + __IO uint8_t CR1; + __IO uint8_t FPR; + __IO uint8_t SCR; + __IO uint8_t DACCR; + __IO uint8_t MUXCR; +} CMP_TypeDef; + +typedef struct +{ + __IO uint8_t FSTAT; + __IO uint8_t FCNFG; + __I uint8_t FSEC; + __I uint8_t FOPT; + __IO uint8_t FCCOB3; + __IO uint8_t FCCOB2; + __IO uint8_t FCCOB1; + __IO uint8_t FCCOB0; + __IO uint8_t FCCOB7; + __IO uint8_t FCCOB6; + __IO uint8_t FCCOB5; + __IO uint8_t FCCOB4; + __IO uint8_t FCCOBB; + __IO uint8_t FCCOBA; + __IO uint8_t FCCOB9; + __IO uint8_t FCCOB8; + __IO uint8_t FPROT3; + __IO uint8_t FPROT2; + __IO uint8_t FPROT1; + __IO uint8_t FPROT0; +} FTFA_TypeDef; + +typedef struct +{ + uint32_t RESERVED0[2]; + __I uint16_t PLASC; // 0x08 + __I uint16_t PLAMC; // 0x0A + __IO uint32_t PLACR; // 0x0C + uint32_t RESERVED1[12]; + __IO uint32_t CPO; // 0x40 +} MCM_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* */ +/* Low-Leakage Wakeup Unit (LLWU) */ +/* */ +/****************************************************************/ +/********** Bits definition for LLWU_PE1 register *************/ +#define LLWU_PE1_WUPE3_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P3 (shift) */ +#define LLWU_PE1_WUPE3_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE3_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P3 (mask) */ +#define LLWU_PE1_WUPE3(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE3_SHIFT) & LLWU_PE1_WUPE3_MASK)) /*!< Wakeup Pin Enable for LLWU_P3 */ +#define LLWU_PE1_WUPE2_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P2 (shift) */ +#define LLWU_PE1_WUPE2_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE2_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P2 (mask) */ +#define LLWU_PE1_WUPE2(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE2_SHIFT) & LLWU_PE1_WUPE2_MASK)) /*!< Wakeup Pin Enable for LLWU_P2 */ +#define LLWU_PE1_WUPE1_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P1 (shift) */ +#define LLWU_PE1_WUPE1_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE1_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P1 (mask) */ +#define LLWU_PE1_WUPE1(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE1_SHIFT) & LLWU_PE1_WUPE1_MASK)) /*!< Wakeup Pin Enable for LLWU_P1 */ +#define LLWU_PE1_WUPE0_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P0 (shift) */ +#define LLWU_PE1_WUPE0_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE0_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P0 (mask) */ +#define LLWU_PE1_WUPE0(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE0_SHIFT) & LLWU_PE1_WUPE0_MASK)) /*!< Wakeup Pin Enable for LLWU_P0 */ + +/********** Bits definition for LLWU_PE2 register *************/ +#define LLWU_PE2_WUPE7_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P7 (shift) */ +#define LLWU_PE2_WUPE7_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE7_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P7 (mask) */ +#define LLWU_PE2_WUPE7(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE7_SHIFT) & LLWU_PE2_WUPE7_MASK)) /*!< Wakeup Pin Enable for LLWU_P7 */ +#define LLWU_PE2_WUPE6_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P6 (shift) */ +#define LLWU_PE2_WUPE6_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE6_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P6 (mask) */ +#define LLWU_PE2_WUPE6(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE6_SHIFT) & LLWU_PE2_WUPE6_MASK)) /*!< Wakeup Pin Enable for LLWU_P6 */ +#define LLWU_PE2_WUPE5_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P5 (shift) */ +#define LLWU_PE2_WUPE5_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE5_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P5 (mask) */ +#define LLWU_PE2_WUPE5(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE5_SHIFT) & LLWU_PE2_WUPE5_MASK)) /*!< Wakeup Pin Enable for LLWU_P5 */ +#define LLWU_PE2_WUPE4_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P4 (shift) */ +#define LLWU_PE2_WUPE4_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE4_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P4 (mask) */ +#define LLWU_PE2_WUPE4(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE4_SHIFT) & LLWU_PE2_WUPE4_MASK)) /*!< Wakeup Pin Enable for LLWU_P4 */ + +/********** Bits definition for LLWU_PE3 register *************/ +#define LLWU_PE3_WUPE11_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P11 (shift) */ +#define LLWU_PE3_WUPE11_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE11_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P11 (mask) */ +#define LLWU_PE3_WUPE11(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE11_SHIFT) & LLWU_PE3_WUPE11_MASK)) /*!< Wakeup Pin Enable for LLWU_P11 */ +#define LLWU_PE3_WUPE10_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P10 (shift) */ +#define LLWU_PE3_WUPE10_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE10_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P10 (mask) */ +#define LLWU_PE3_WUPE10(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE10_SHIFT) & LLWU_PE3_WUPE10_MASK)) /*!< Wakeup Pin Enable for LLWU_P10 */ +#define LLWU_PE3_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P9 (shift) */ +#define LLWU_PE3_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P9 (mask) */ +#define LLWU_PE3_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE13_SHIFT) & LLWU_PE3_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P9 */ +#define LLWU_PE3_WUPE8_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P8 (shift) */ +#define LLWU_PE3_WUPE8_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE8_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P8 (mask) */ +#define LLWU_PE3_WUPE8(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE8_SHIFT) & LLWU_PE3_WUPE8_MASK)) /*!< Wakeup Pin Enable for LLWU_P8 */ + +/********** Bits definition for LLWU_PE4 register *************/ +#define LLWU_PE4_WUPE15_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P15 (shift) */ +#define LLWU_PE4_WUPE15_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE15_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P15 (mask) */ +#define LLWU_PE4_WUPE15(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE15_SHIFT) & LLWU_PE4_WUPE15_MASK)) /*!< Wakeup Pin Enable for LLWU_P15 */ +#define LLWU_PE4_WUPE14_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P14 (shift) */ +#define LLWU_PE4_WUPE14_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE14_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P14 (mask) */ +#define LLWU_PE4_WUPE14(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE14_SHIFT) & LLWU_PE4_WUPE14_MASK)) /*!< Wakeup Pin Enable for LLWU_P14 */ +#define LLWU_PE4_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P13 (shift) */ +#define LLWU_PE4_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P13 (mask) */ +#define LLWU_PE4_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE13_SHIFT) & LLWU_PE4_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P13 */ +#define LLWU_PE4_WUPE12_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P12 (shift) */ +#define LLWU_PE4_WUPE12_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE12_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P12 (mask) */ +#define LLWU_PE4_WUPE12(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE12_SHIFT) & LLWU_PE4_WUPE12_MASK)) /*!< Wakeup Pin Enable for LLWU_P12 */ + +/********** Bits definition for LLWU_ME register *************/ +#define LLWU_ME_WUME7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Module Enable for Module 7 */ +#define LLWU_ME_WUME6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Module Enable for Module 6 */ +#define LLWU_ME_WUME5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Module Enable for Module 5 */ +#define LLWU_ME_WUME4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Module Enable for Module 4 */ +#define LLWU_ME_WUME3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Module Enable for Module 3 */ +#define LLWU_ME_WUME2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Module Enable for Module 2 */ +#define LLWU_ME_WUME1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Module Enable for Module 1 */ +#define LLWU_ME_WUME0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Module Enable for Module 0 */ + +/********** Bits definition for LLWU_F1 register *************/ +#define LLWU_F1_WUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P7 */ +#define LLWU_F1_WUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P6 */ +#define LLWU_F1_WUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P5 */ +#define LLWU_F1_WUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P4 */ +#define LLWU_F1_WUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P3 */ +#define LLWU_F1_WUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P2 */ +#define LLWU_F1_WUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P1 */ +#define LLWU_F1_WUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P0 */ + +/********** Bits definition for LLWU_F2 register *************/ +#define LLWU_F2_WUF15 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P15 */ +#define LLWU_F2_WUF14 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P14 */ +#define LLWU_F2_WUF13 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P13 */ +#define LLWU_F2_WUF12 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P12 */ +#define LLWU_F2_WUF11 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P11 */ +#define LLWU_F2_WUF10 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P10 */ +#define LLWU_F2_WUF9 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P9 */ +#define LLWU_F2_WUF8 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P8 */ + +/********** Bits definition for LLWU_F3 register *************/ +#define LLWU_F3_MWUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for Module 7 */ +#define LLWU_F3_MWUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for Module 6 */ +#define LLWU_F3_MWUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for Module 5 */ +#define LLWU_F3_MWUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for Module 4 */ +#define LLWU_F3_MWUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for Module 3 */ +#define LLWU_F3_MWUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for Module 2 */ +#define LLWU_F3_MWUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for Module 1 */ +#define LLWU_F3_MWUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for Module 0 */ + +/********** Bits definition for LLWU_FILT1 register *************/ +#define LLWU_FILT1_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ +#define LLWU_FILT1_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ +#define LLWU_FILT1_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT1_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ +#define LLWU_FILT1_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTE_SHIFT) & LLWU_FILT1_FILTE_MASK)) /*!< Digital Filter on External Pin */ +#define LLWU_FILT1_FILTE_DISABLED LLWU_FILT1_FILTE(0) /*!< Filter disabled */ +#define LLWU_FILT1_FILTE_POSEDGE LLWU_FILT1_FILTE(1) /*!< Filter posedge detect enabled */ +#define LLWU_FILT1_FILTE_NEGEDGE LLWU_FILT1_FILTE(2) /*!< Filter negedge detect enabled */ +#define LLWU_FILT1_FILTE_ANYEDGE LLWU_FILT1_FILTE(3) /*!< Filter any edge detect enabled */ +#define LLWU_FILT1_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ +#define LLWU_FILT1_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT1_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ +#define LLWU_FILT1_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTSEL_SHIFT) & LLWU_FILT1_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ + +/********** Bits definition for LLWU_FILT2 register *************/ +#define LLWU_FILT2_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ +#define LLWU_FILT2_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ +#define LLWU_FILT2_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT2_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ +#define LLWU_FILT2_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTE_SHIFT) & LLWU_FILT2_FILTE_MASK)) /*!< Digital Filter on External Pin */ +#define LLWU_FILT2_FILTE_DISABLED LLWU_FILT2_FILTE(0) /*!< Filter disabled */ +#define LLWU_FILT2_FILTE_POSEDGE LLWU_FILT2_FILTE(1) /*!< Filter posedge detect enabled */ +#define LLWU_FILT2_FILTE_NEGEDGE LLWU_FILT2_FILTE(2) /*!< Filter negedge detect enabled */ +#define LLWU_FILT2_FILTE_ANYEDGE LLWU_FILT2_FILTE(3) /*!< Filter any edge detect enabled */ +#define LLWU_FILT2_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ +#define LLWU_FILT2_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT2_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ +#define LLWU_FILT2_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTSEL_SHIFT) & LLWU_FILT2_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ + +/****************************************************************/ +/* */ +/* Port Control and interrupts (PORT) */ +/* */ +/****************************************************************/ +/******** Bits definition for PORTx_PCRn register *************/ +#define PORTx_PCRn_ISF ((uint32_t)0x01000000) /*!< Interrupt Status Flag */ +#define PORTx_PCRn_IRQC_SHIFT 16 +#define PORTx_PCRn_IRQC_MASK ((uint32_t)0x000F0000) /*!< Interrupt Configuration */ +#define PORTx_PCRn_IRQC(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_IRQC_SHIFT) & PORTx_PCRn_IRQC_MASK)) +#define PORTx_PCRn_MUX_SHIFT 8 /*!< Pin Mux Control (shift) */ +#define PORTx_PCRn_MUX_MASK ((uint32_t)0x00000700) /*!< Pin Mux Control (mask) */ +#define PORTx_PCRn_MUX(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_MUX_SHIFT) & PORTx_PCRn_MUX_MASK)) /*!< Pin Mux Control */ +#define PORTx_PCRn_DSE ((uint32_t)0x00000040) /*!< Drive Strength Enable */ +#define PORTx_PCRn_PFE ((uint32_t)0x00000010) /*!< Passive Filter Enable */ +#define PORTx_PCRn_SRE ((uint32_t)0x00000004) /*!< Slew Rate Enable */ +#define PORTx_PCRn_PE ((uint32_t)0x00000002) /*!< Pull Enable */ +#define PORTx_PCRn_PS ((uint32_t)0x00000001) /*!< Pull Select */ + +/****************************************************************/ +/* */ +/* Oscillator (OSC) */ +/* */ +/****************************************************************/ +/*********** Bits definition for OSC_CR register **************/ +#define OSC_CR_ERCLKEN ((uint8_t)0x80) /*!< External Reference Enable */ +#define OSC_CR_EREFSTEN ((uint8_t)0x20) /*!< External Reference Stop Enable */ +#define OSC_CR_SC2P ((uint8_t)0x08) /*!< Oscillator 2pF Capacitor Load Configure */ +#define OSC_CR_SC4P ((uint8_t)0x04) /*!< Oscillator 4pF Capacitor Load Configure */ +#define OSC_CR_SC8P ((uint8_t)0x02) /*!< Oscillator 8pF Capacitor Load Configure */ +#define OSC_CR_SC16P ((uint8_t)0x01) /*!< Oscillator 16pF Capacitor Load Configure */ + +/****************************************************************/ +/* */ +/* Direct Memory Access (DMA) */ +/* */ +/****************************************************************/ +/*********** Bits definition for DMA_BCRn register ************/ +#define DMA_DSR_BCRn_CE ((uint32_t)((uint32_t)1 << 30)) /*!< Configuration Error */ +#define DMA_DSR_BCRn_BES ((uint32_t)((uint32_t)1 << 29)) /*!< Bus Error on Source */ +#define DMA_DSR_BCRn_BED ((uint32_t)((uint32_t)1 << 28)) /*!< Bus Error on Destination */ +#define DMA_DSR_BCRn_REQ ((uint32_t)((uint32_t)1 << 26)) /*!< Request */ +#define DMA_DSR_BCRn_BSY ((uint32_t)((uint32_t)1 << 25)) /*!< Busy */ +#define DMA_DSR_BCRn_DONE ((uint32_t)((uint32_t)1 << 24)) /*!< Transactions done */ +#define DMA_DSR_BCRn_BCR_SHIFT 0 /*!< Bytes yet to be transferred for block (shift) */ +#define DMA_DSR_BCRn_BCR_MASK ((uint32_t)((uint32_t)0x00FFFFFF << DMA_DSR_BCRn_BCR_SHIFT)) /*!< Bytes yet to be transferred for block (mask) */ +#define DMA_DSR_BCRn_BCR(x) ((uint32_t)(((uint32_t)(x) << DMA_DSR_BCRn_BCR_SHIFT) & DMA_DSR_BCRn_BCR_MASK)) /*!< Bytes yet to be transferred for block */ + +/*********** Bits definition for DMA_DCRn register ************/ +#define DMA_DCRn_EINT ((uint32_t)((uint32_t)1 << 31)) /*!< Enable interrupt on completion of transfer */ +#define DMA_DCRn_ERQ ((uint32_t)((uint32_t)1 << 30)) /*!< Enable peripheral request */ +#define DMA_DCRn_CS ((uint32_t)((uint32_t)1 << 29)) /*!< Cycle steal */ +#define DMA_DCRn_AA ((uint32_t)((uint32_t)1 << 28)) /*!< Auto-align */ +#define DMA_DCRn_EADREQ ((uint32_t)((uint32_t)1 << 23)) /*!< Enable asynchronous DMA requests */ +#define DMA_DCRn_SINC ((uint32_t)((uint32_t)1 << 22)) /*!< Source increment */ +#define DMA_DCRn_SSIZE_SHIFT 20 /*!< Source size (shift) */ +#define DMA_DCRn_SSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_SSIZE_SHIFT)) /*!< Source size (mask) */ +#define DMA_DCRn_SSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SSIZE_SHIFT) & DMA_DCRn_SSIZE_MASK)) /*!< Source size */ +#define DMA_DCRn_DINC ((uint32_t)((uint32_t)1 << 19)) /*!< Destination increment */ +#define DMA_DCRn_DSIZE_SHIFT 17 /*!< Destination size (shift) */ +#define DMA_DCRn_DSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_DSIZE_SHIFT)) /*!< Destination size (mask) */ +#define DMA_DCRn_DSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DSIZE_SHIFT) & DMA_DCRn_DSIZE_MASK)) /*!< Destination size */ +#define DMA_DCRn_START ((uint32_t)((uint32_t)1 << 16)) /*!< Start transfer */ +#define DMA_DCRn_SMOD_SHIFT 12 /*!< Source address modulo (shift) */ +#define DMA_DCRn_SMOD_MASK ((uint32_t)((uint32_t)0x0F << DMA_DCRn_SMOD_SHIFT)) /*!< Source address modulo (mask) */ +#define DMA_DCRn_SMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SMOD_SHIFT) & DMA_DCRn_SMOD_MASK)) /*!< Source address modulo */ +#define DMA_DCRn_DMOD_SHIFT 8 /*!< Destination address modulo (shift) */ +#define DMA_DCRn_DMOD_MASK ((uint32_t)0x0F << DMA_DCRn_DMOD_SHIFT) /*!< Destination address modulo (mask) */ +#define DMA_DCRn_DMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DMOD_SHIFT) & DMA_DCRn_DMOD_MASK)) /*!< Destination address modulo */ +#define DMA_DCRn_D_REQ ((uint32_t)((uint32_t)1 << 7)) /*!< Disable request */ +#define DMA_DCRn_LINKCC_SHIFT 4 /*!< Link channel control (shift) */ +#define DMA_DCRn_LINKCC_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LINKCC_SHIFT)) /*!< Link channel control (mask) */ +#define DMA_DCRn_LINKCC(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LINKCC_SHIFT) & DMA_DCRn_LINKCC_MASK)) /*!< Link channel control */ +#define DMA_DCRn_LCH1_SHIFT 2 /*!< Link channel 1 (shift) */ +#define DMA_DCRn_LCH1_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH1_SHIFT)) /*!< Link channel 1 (mask) */ +#define DMA_DCRn_LCH1(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH1_SHIFT) & DMA_DCRn_LCH1_MASK)) /*!< Link channel 1 */ +#define DMA_DCRn_LCH2_SHIFT 0 /*!< Link channel 2 (shift) */ +#define DMA_DCRn_LCH2_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH2_SHIFT)) /*!< Link channel 2 (mask) */ +#define DMA_DCRn_LCH2(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH2_SHIFT) & DMA_DCRn_LCH2_MASK)) /*!< Link channel 2 */ + +/****************************************************************/ +/* */ +/* Direct Memory Access Multiplexer (DMAMUX) */ +/* */ +/****************************************************************/ +/******** Bits definition for DMAMUX_CHCFGn register **********/ +#define DMAMUX_CHCFGn_ENBL ((uint8_t)((uint8_t)1 << 7)) /*!< DMA Channel Enable */ +#define DMAMUX_CHCFGn_TRIG ((uint8_t)((uint8_t)1 << 6)) /*!< DMA Channel Trigger Enable */ +#define DMAMUX_CHCFGn_SOURCE_SHIFT 0 /*!< DMA Channel Source (Slot) (shift) */ +#define DMAMUX_CHCFGn_SOURCE_MASK ((uint8_t)((uint8_t)0x3F << DMAMUX_CHCFGn_SOURCE_SHIFT)) /*!< DMA Channel Source (Slot) (mask) */ +#define DMAMUX_CHCFGn_SOURCE(x) ((uint8_t)(((uint8_t)(x) << DMAMUX_CHCFGn_SOURCE_SHIFT) & DMAMUX_CHCFGn_SOURCE_MASK)) /*!< DMA Channel Source (Slot) */ + +/****************************************************************/ +/* */ +/* Periodic Interrupt Timer (PIT) */ +/* */ +/****************************************************************/ +/*********** Bits definition for PIT_MCR register *************/ +#define PIT_MCR_MDIS ((uint32_t)((uint32_t)1 << 1)) /*!< Module Disable */ +#define PIT_MCR_FRZ ((uint32_t)((uint32_t)1 << 0)) /*!< Freeze */ +/********** Bits definition for PIT_LDVALn register ***********/ +#define PIT_LDVALn_TSV_SHIFT 0 /*!< Timer Start Value */ +#define PIT_LDVALn_TSV_MASK ((uint32_t)((uint32_t)0xFFFFFFFF << PIT_LDVALn_TSV_SHIFT)) +#define PIT_LDVALn_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVALn_TSV_SHIFT))&PIT_LDVALn_TSV_MASK) +/********** Bits definition for PIT_CVALn register ************/ +#define PIT_CVALn_TVL_SHIFT 0 /*!< Current Timer Value */ +#define PIT_CVALn_TVL_MASK ((uint32_t)((uint32_t)0xFFFFFFFF << PIT_CVALn_TVL_SHIFT)) +#define PIT_CVALn_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVALn_TVL_SHIFT))&PIT_CVALn_TVL_MASK) +/********** Bits definition for PIT_TCTRLn register ***********/ +#define PIT_TCTRLn_CHN ((uint32_t)((uint32_t)1 << 2)) /*!< Chain Mode */ +#define PIT_TCTRLn_TIE ((uint32_t)((uint32_t)1 << 1)) /*!< Timer Interrupt Enable */ +#define PIT_TCTRLn_TEN ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Enable */ +/********** Bits definition for PIT_TFLGn register ************/ +#define PIT_TFLGn_TIF ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Interrupt Flag */ + +/****************************************************************/ +/* */ +/* Analog-to-Digital Converter (ADC) */ +/* */ +/****************************************************************/ +/*********** Bits definition for ADCx_SC1n register ***********/ +#define ADCx_SC1n_COCO ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Complete Flag */ +#define ADCx_SC1n_AIEN ((uint32_t)((uint32_t)1 << 6)) /*!< Interrupt Enable */ +#define ADCx_SC1n_DIFF ((uint32_t)((uint32_t)1 << 5)) /*!< Differential Mode Enable */ +#define ADCx_SC1n_ADCH_SHIFT 0 /*!< Input channel select (shift) */ +#define ADCx_SC1n_ADCH_MASK ((uint32_t)((uint32_t)0x1F << ADCx_SC1n_ADCH_SHIFT)) /*!< Input channel select (mask) */ +#define ADCx_SC1n_ADCH(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC1n_ADCH_SHIFT) & ADCx_SC1n_ADCH_MASK)) /*!< Input channel select */ + +/*********** Bits definition for ADCx_CFG1 register ***********/ +#define ADCx_CFG1_ADLPC ((uint32_t)((uint32_t)1 << 7)) /*!< Low-Power Configuration */ +#define ADCx_CFG1_ADIV_SHIFT 5 /*!< Clock Divide Select (shift) */ +#define ADCx_CFG1_ADIV_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADIV_SHIFT)) /*!< Clock Divide Select (mask) */ +#define ADCx_CFG1_ADIV(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADIV_SHIFT) & ADCx_CFG1_ADIV_MASK)) /*!< Clock Divide Select */ +#define ADCx_CFG1_ADLSMP ((uint32_t)((uint32_t)1 << 4)) /*!< Sample time configuration */ +#define ADCx_CFG1_MODE_SHIFT 2 /*!< Conversion mode (resolution) selection (shift) */ +#define ADCx_CFG1_MODE_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_MODE_SHIFT)) /*!< Conversion mode (resolution) selection (mask) */ +#define ADCx_CFG1_MODE(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_MODE_SHIFT) & ADCx_CFG1_MODE_MASK)) /*!< Conversion mode (resolution) selection */ +#define ADCx_CFG1_ADICLK_SHIFT 0 /*!< Input Clock Select (shift) */ +#define ADCx_CFG1_ADICLK_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADICLK_SHIFT)) /*!< Input Clock Select (mask) */ +#define ADCx_CFG1_ADICLK(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADICLK_SHIFT) & ADCx_CFG1_ADICLK_MASK)) /*!< Input Clock Select */ + +/*********** Bits definition for ADCx_CFG2 register ***********/ +#define ADCx_CFG2_MUXSEL ((uint32_t)((uint32_t)1 << 4)) /*!< ADC Mux Select */ +#define ADCx_CFG2_ADACKEN ((uint32_t)((uint32_t)1 << 3)) /*!< Asynchronous Clock Output Enable */ +#define ADCx_CFG2_ADHSC ((uint32_t)((uint32_t)1 << 2)) /*!< High-Speed Configuration */ +#define ADCx_CFG2_ADLSTS_SHIFT 0 /*!< Long Sample Time Select (shift) */ +#define ADCx_CFG2_ADLSTS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG2_ADLSTS_SHIFT)) /*!< Long Sample Time Select (mask) */ +#define ADCx_CFG2_ADLSTS(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG2_ADLSTS_SHIFT) & ADCx_CFG2_ADLSTS_MASK)) /*!< Long Sample Time Select */ + +/*********** Bits definition for ADCx_SC2 register ***********/ +#define ADCx_SC2_ADACT ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Active */ +#define ADCx_SC2_ADTRG ((uint32_t)((uint32_t)1 << 6)) /*!< Conversion Trigger Select */ +#define ADCx_SC2_ACFE ((uint32_t)((uint32_t)1 << 5)) /*!< Compare Function Enable */ +#define ADCx_SC2_ACFGT ((uint32_t)((uint32_t)1 << 4)) /*!< Compare Function Greater Than Enable */ +#define ADCx_SC2_ACREN ((uint32_t)((uint32_t)1 << 3)) /*!< Compare Function Range Enable */ +#define ADCx_SC2_DMAEN ((uint32_t)((uint32_t)1 << 2)) /*!< DMA Enable */ +#define ADCx_SC2_REFSEL_SHIFT 0 /*!< Voltage Reference Selection (shift) */ +#define ADCx_SC2_REFSEL_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC2_REFSEL_SHIFT)) /*!< Voltage Reference Selection (mask) */ +#define ADCx_SC2_REFSEL(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC2_REFSEL_SHIFT) & ADCx_SC2_REFSEL_MASK)) /*!< Voltage Reference Selection */ + +/*********** Bits definition for ADCx_SC3 register ***********/ +#define ADCx_SC3_CAL ((uint32_t)((uint32_t)1 << 7)) /*!< Calibration */ +#define ADCx_SC3_CALF ((uint32_t)((uint32_t)1 << 6)) /*!< Calibration Failed Flag */ +#define ADCx_SC3_ADCO ((uint32_t)((uint32_t)1 << 3)) /*!< Continuous Conversion Enable */ +#define ADCx_SC3_AVGE ((uint32_t)((uint32_t)1 << 2)) /*!< Hardware Average Enable */ +#define ADCx_SC3_AVGS_SHIFT 0 /*!< Hardware Average Select (shift) */ +#define ADCx_SC3_AVGS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC3_AVGS_SHIFT)) /*!< Hardware Average Select (mask) */ +#define ADCx_SC3_AVGS(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC3_AVGS_SHIFT) & ADCx_SC3_AVGS_MASK)) /*!< Hardware Average Select */ + +/****************************************************************/ +/* */ +/* Low-Power Timer (LPTMR) */ +/* */ +/****************************************************************/ +/********** Bits definition for LPTMRx_CSR register ***********/ +#define LPTMRx_CSR_TCF ((uint32_t)((uint32_t)1 << 7)) /*!< Timer Compare Flag */ +#define LPTMRx_CSR_TIE ((uint32_t)((uint32_t)1 << 6)) /*!< Timer Interrupt Enable */ +#define LPTMRx_CSR_TPS_SHIFT 4 /*!< Timer Pin Select (shift) */ +#define LPTMRx_CSR_TPS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_CSR_TPS_SHIFT)) /*!< Timer Pin Select (mask) */ +#define LPTMRx_CSR_TPS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CSR_TPS_SHIFT) & LPTMRx_CSR_TPS_MASK)) /*!< Timer Pin Select */ +#define LPTMRx_CSR_TPP ((uint32_t)((uint32_t)1 << 3)) /*!< Timer Pin Polarity */ +#define LPTMRx_CSR_TFC ((uint32_t)((uint32_t)1 << 2)) /*!< Timer Free-Running Counter */ +#define LPTMRx_CSR_TMS ((uint32_t)((uint32_t)1 << 1)) /*!< Timer Mode Select */ +#define LPTMRx_CSR_TEN ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Enable */ + +/********** Bits definition for LPTMRx_PSR register ***********/ +#define LPTMRx_PSR_PRESCALE_SHIFT 3 /*!< Prescale Value (shift) */ +#define LPTMRx_PSR_PRESCALE_MASK ((uint32_t)((uint32_t)0x0F << LPTMRx_PSR_PRESCALE_SHIFT)) /*!< Prescale Value (mask) */ +#define LPTMRx_PSR_PRESCALE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PRESCALE_SHIFT) & LPTMRx_PSR_PRESCALE_MASK)) /*!< Prescale Value */ +#define LPTMRx_PSR_PBYP ((uint32_t)((uint32_t)1 << 2)) /*!< Prescaler Bypass */ +#define LPTMRx_PSR_PCS_SHIFT 0 /*!< Prescaler Clock Select (shift) */ +#define LPTMRx_PSR_PCS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_PSR_PCS_SHIFT)) /*!< Prescaler Clock Select (mask) */ +#define LPTMRx_PSR_PCS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PCS_SHIFT) & LPTMRx_PSR_PCS_MASK)) /*!< Prescaler Clock Select */ + +/********** Bits definition for LPTMRx_CMR register ***********/ +#define LPTMRx_CMR_COMPARE_SHIFT 0 /*!< Compare Value (shift) */ +#define LPTMRx_CMR_COMPARE_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CMR_COMPARE_SHIFT)) /*!< Compare Value (mask) */ +#define LPTMRx_CMR_COMPARE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CMR_COMPARE_SHIFT) & LPTMRx_CMR_COMPARE_MASK)) /*!< Compare Value */ + +/********** Bits definition for LPTMRx_CNR register ***********/ +#define LPTMRx_CNR_COUNTER_SHIFT 0 /*!< Counter Value (shift) */ +#define LPTMRx_CNR_COUNTER_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CNR_COUNTER_SHIFT)) /*!< Counter Value (mask) */ +#define LPTMRx_CNR_COUNTER(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CNR_COUNTER_SHIFT) & LPTMRx_CNR_COUNTER_MASK)) /*!< Counter Value */ + +/****************************************************************/ +/* */ +/* Touch Sensing Input (TSI) */ +/* */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* */ +/* Multipurpose Clock Generator (MCG) */ +/* */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* */ +/* Inter-Integrated Circuit (I2C): Device independent part */ +/* */ +/****************************************************************/ +/*********** Bits definition for I2Cx_A1 register *************/ +#define I2Cx_A1_AD_MASK ((uint8_t)0xFE) /*!< Address [7:1] */ +#define I2Cx_A1_AD_SHIFT 1 +#define I2Cx_A1_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A1_AD_SHIFT) & I2Cx_A1_AD_MASK) + +/*********** Bits definition for I2Cx_F register **************/ +#define I2Cx_F_MULT_MASK ((uint8_t)0xC0) /*!< Multiplier factor */ +#define I2Cx_F_MULT_SHIFT 6 +#define I2Cx_F_MULT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_MULT_SHIFT) & I2Cx_F_MULT_MASK) +#define I2Cx_F_ICR_MASK ((uint8_t)0x3F) /*!< Clock rate */ +#define I2Cx_F_ICR_SHIFT 0 +#define I2Cx_F_ICR(x) ((uint8_t)(((uint8_t)(x) << I2Cx_F_ICR_SHIFT) & I2Cx_F_ICR_MASK) + +/*********** Bits definition for I2Cx_C1 register *************/ +#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ +#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ +#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ +#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ +#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ +#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ +#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ +#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ + +/*********** Bits definition for I2Cx_S register **************/ +/*** This register is referred to as 'S1' in KL26Z manual *******/ +#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ +#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ +#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ +#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ +#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ +#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ +#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ +#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ + +/*********** Bits definition for I2Cx_D register **************/ +#define I2Cx_D_DATA_SHIFT 0 /*!< Data */ +#define I2Cx_D_DATA_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_D_DATA_SHIFT)) +#define I2Cx_D_DATA(x) ((uint8_t)(((uint8_t)(x) << I2Cx_D_DATA_SHIFT) & I2Cx_D_DATA_MASK)) + +/*********** Bits definition for I2Cx_C2 register *************/ +#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ +#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ +#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ +#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ +#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ +#define I2Cx_C2_AD_SHIFT 0 /*!< Slave Address [10:8] */ +#define I2Cx_C2_AD_MASK ((uint8_t)((uint8_t)0x7 << I2Cx_C2_AD_SHIFT)) +#define I2Cx_C2_AD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_C2_AD_SHIFT) & I2Cx_C2_AD_MASK)) + +/*********** Bits definition for I2Cx_RA register *************/ +#define I2Cx_RA_RAD_SHIFT 1 /*!< Range Slave Address */ +#define I2Cx_RA_RAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_RA_RAD_SHIFT)) +#define I2Cx_RA_RAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_RA_RAD_SHIFT) & I2Cx_RA_RAD_MASK)) + +/*********** Bits definition for I2Cx_SMB register ************/ +#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ +#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ +#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ +#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ +#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ +#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ +#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ +#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ + +/*********** Bits definition for I2Cx_A2 register *************/ +#define I2Cx_A2_SAD_SHIFT 1 /*!< SMBus Address */ +#define I2Cx_A2_SAD_MASK ((uint8_t)((uint8_t)0x7F << I2Cx_A2_SAD_SHIFT)) +#define I2Cx_A2_SAD(x) ((uint8_t)(((uint8_t)(x) << I2Cx_A2_SAD_SHIFT) & I2Cx_A2_SAD_MASK)) + +/*********** Bits definition for I2Cx_SLTH register ***********/ +#define I2Cx_SLTH_SSLT_SHIFT 0 /*!< MSB of SCL low timeout value */ +#define I2Cx_SLTH_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTH_SSLT_SHIFT)) +#define I2Cx_SLTH_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTH_SSLT_SHIFT) & I2Cx_SLTH_SSLT_MASK)) + +/*********** Bits definition for I2Cx_SLTL register ***********/ +#define I2Cx_SLTL_SSLT_SHIFT 0 /*!< LSB of SCL low timeout value */ +#define I2Cx_SLTL_SSLT_MASK ((uint8_t)((uint8_t)0xFF << I2Cx_SLTL_SSLT_SHIFT)) +#define I2Cx_SLTL_SSLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_SLTL_SSLT_SHIFT) & I2Cx_SLTL_SSLT_MASK)) + +/****************************************************************/ +/* */ +/* Universal Asynchronous Receiver/Transmitter (UART) */ +/* */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* */ +/* Power Management Controller (PMC) */ +/* */ +/****************************************************************/ +/********* Bits definition for PMC_LVDSC1 register *************/ +#define PMC_LVDSC1_LVDF ((uint8_t)0x80) /*!< Low-Voltage Detect Flag */ +#define PMC_LVDSC1_LVDACK ((uint8_t)0x40) /*!< Low-Voltage Detect Acknowledge */ +#define PMC_LVDSC1_LVDIE ((uint8_t)0x20) /*!< Low-Voltage Detect Interrupt Enable */ +#define PMC_LVDSC1_LVDRE ((uint8_t)0x10) /*!< Low-Voltage Detect Reset Enable */ +#define PMC_LVDSC1_LVDV_MASK ((uint8_t)0x3) /*!< Low-Voltage Detect Voltage Select */ +#define PMC_LVDSC1_LVDV_SHIFT 0 +#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) +/********* Bits definition for PMC_LVDSC1 register *************/ +#define PMC_LVDSC2_LVWF ((uint8_t)0x80) /*!< Low-Voltage Warning Flag */ +#define PMC_LVDSC2_LVWACK ((uint8_t)0x40) /*!< Low-Voltage Warning Acknowledge */ +#define PMC_LVDSC2_LVWIE ((uint8_t)0x20) /*!< Low-Voltage Warning Interrupt Enable */ +#define PMC_LVDSC2_LVWV_MASK 0x3 /*!< Low-Voltage Warning Voltage Select */ +#define PMC_LVDSC2_LVWV_SHIFT 0 +#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) +/********* Bits definition for PMC_REGSC register *************/ +#define PMC_REGSC_BGEN ((uint8_t)0x10) /*!< Bandgap Enable In VLPx Operation */ +#define PMC_REGSC_ACKISO ((uint8_t)0x8) /*!< Acknowledge Isolation */ +#define PMC_REGSC_REGONS ((uint8_t)0x4) /*!< Regulator In Run Regulation Status */ +#define PMC_REGSC_BGBE ((uint8_t)0x1) /*!< Bandgap Buffer Enable */ + +/****************************************************************/ +/* */ +/* Timer/PWM Module (TPM) */ +/* */ +/****************************************************************/ + +/* Device dependent */ + +/****************************************************************/ +/* */ +/* USB/OTG or FS: Device independent parts */ +/* */ +/****************************************************************/ +/******** Bits definition for USBx_ADDINFO register ***********/ +#define USBx_ADDINFO_IEHOST ((uint8_t)0x01) /*!< Host mode operation? */ + +/******** Bits definition for USBx_OTGCTL register ************/ +#define USBx_OTGCTL_DPHIGH ((uint8_t)0x80) /*!< D+ Data Line pullup resistor enable */ + +/******** Bits definition for USBx_ISTAT register *************/ +#define USBx_ISTAT_STALL ((uint8_t)0x80) /*!< Stall interrupt */ +#define USBx_ISTAT_RESUME ((uint8_t)0x20) /*!< Signal remote wakeup on the bus */ +#define USBx_ISTAT_SLEEP ((uint8_t)0x10) /*!< Detected bus idle for 3ms */ +#define USBx_ISTAT_TOKDNE ((uint8_t)0x08) /*!< Completed processing of current token */ +#define USBx_ISTAT_SOFTOK ((uint8_t)0x04) /*!< Received start of frame */ +#define USBx_ISTAT_ERROR ((uint8_t)0x02) /*!< Error (must check ERRSTAT!) */ +#define USBx_ISTAT_USBRST ((uint8_t)0x01) /*!< USB reset detected */ + +/******** Bits definition for USBx_INTEN register ***************/ +#define USBx_INTEN_STALLEN ((uint8_t)0x80) /*!< STALL interrupt enable */ +#define USBx_INTEN_RESUMEEN ((uint8_t)0x20) /*!< RESUME interrupt enable */ +#define USBx_INTEN_SLEEPEN ((uint8_t)0x10) /*!< SLEEP interrupt enable */ +#define USBx_INTEN_TOKDNEEN ((uint8_t)0x08) /*!< TOKDNE interrupt enable */ +#define USBx_INTEN_SOFTOKEN ((uint8_t)0x04) /*!< SOFTOK interrupt enable */ +#define USBx_INTEN_ERROREN ((uint8_t)0x02) /*!< ERROR interrupt enable */ +#define USBx_INTEN_USBRSTEN ((uint8_t)0x01) /*!< USBRST interrupt enable */ + +/******** Bits definition for USBx_ERRSTAT register ***********/ +#define USBx_ERRSTAT_BTSERR ((uint8_t)0x80) /*!< Bit stuff error detected */ +#define USBx_ERRSTAT_DMAERR ((uint8_t)0x20) /*!< DMA request was not given */ +#define USBx_ERRSTAT_BTOERR ((uint8_t)0x10) /*!< BUS turnaround timeout error */ +#define USBx_ERRSTAT_DFN8 ((uint8_t)0x08) /*!< Received data not 8-bit sized */ +#define USBx_ERRSTAT_CRC16 ((uint8_t)0x04) /*!< Packet with CRC16 error */ +#define USBx_ERRSTAT_CRC5EOF ((uint8_t)0x02) /*!< CRC5 (device) or EOF (host) error */ +#define USBx_ERRSTAT_PIDERR ((uint8_t)0x01) /*!< PID check field fail */ + +/******** Bits definition for USBx_ERREN register ************/ +#define USBx_ERREN_BTSERREN ((uint8_t)0x80) /*!< BTSERR Interrupt Enable */ +#define USBx_ERREN_DMAERREN ((uint8_t)0x20) /*!< DMAERR Interrupt Enable */ +#define USBx_ERREN_BTOERREN ((uint8_t)0x10) /*!< BTOERR Interrupt Enable */ +#define USBx_ERREN_DFN8EN ((uint8_t)0x08) /*!< DFN8 Interrupt Enable */ +#define USBx_ERREN_CRC16EN ((uint8_t)0x04) /*!< CRC16 Interrupt Enable */ +#define USBx_ERREN_CRC5EOFEN ((uint8_t)0x02) /*!< CRC5/EOF Interrupt Enable */ +#define USBx_ERREN_PIDERREN ((uint8_t)0x01) /*!< PIDERR Interrupt Enable */ + +/******** Bits definition for USBx_STAT register *************/ +#define USBx_STAT_ENDP_MASK ((uint8_t)0xF0) /*!< Endpoint address mask*/ +#define USBx_STAT_ENDP_SHIFT ((uint8_t)0x04) /*!< Endpoint address shift*/ +#define USBx_STAT_TX_MASK ((uint8_t)0x08) /*!< Transmit indicator mask*/ +#define USBx_STAT_TX_SHIFT ((uint8_t)0x03) /*!< Transmit indicator shift*/ +#define USBx_STAT_ODD_MASK ((uint8_t)0x04) /*!< EVEN/ODD bank indicator mask*/ +#define USBx_STAT_ODD_SHIFT ((uint8_t)0x02) /*!< EVEN/ODD bank indicator shift */ + +/******** Bits definition for USBx_CTL register *****************/ +#define USBx_CTL_JSTATE ((uint8_t)0x80) /*!< Live USB differential receiver JSTATE signal */ +#define USBx_CTL_SE0 ((uint8_t)0x40) /*!< Live USB single ended zero signal */ +#define USBx_CTL_TXSUSPENDTOKENBUSY ((uint8_t)0x20) /*!< */ +#define USBx_CTL_ODDRST ((uint8_t)0x02) /*!< Reset all BDT ODD ping/pong bits */ +#define USBx_CTL_USBENSOFEN ((uint8_t)0x01) /*!< USB Enable! */ + +/******** Bits definition for USBx_ADDR register ****************/ +#define USBx_ADDR_ADDR_SHIFT 0 /*!< USB Address */ +#define USBx_ADDR_ADDR_MASK ((uint8_t)0x7F) /*!< USB Address */ + +/******** Bits definition for USBx_ENDPTn register **************/ +#define USBx_ENDPTn_EPCTLDIS ((uint8_t)0x10) /*!< Disables control transfers */ +#define USBx_ENDPTn_EPRXEN ((uint8_t)0x08) /*!< Enable RX transfers */ +#define USBx_ENDPTn_EPTXEN ((uint8_t)0x04) /*!< Enable TX transfers */ +#define USBx_ENDPTn_EPSTALL ((uint8_t)0x02) /*!< Endpoint is called and in STALL */ +#define USBx_ENDPTn_EPHSHK ((uint8_t)0x01) /*!< Enable handshaking during transaction */ + +/******** Bits definition for USBx_USBCTRL register *************/ +#define USBx_USBCTRL_SUSP ((uint8_t)0x80) /*!< USB transceiver in suspend state */ +#define USBx_USBCTRL_PDE ((uint8_t)0x40) /*!< Enable weak pull-downs */ + +/******** Bits definition for USBx_OBSERVE register *************/ +#define USBx_OBSERVE_DPPU ((uint8_t)0x80) /*!< Provides observability of the D+ Pullup . signal output from the USB OTG module */ +#define USBx_OBSERVE_DPPD ((uint8_t)0x40) /*!< Provides observability of the D+ Pulldown . signal output from the USB OTG module */ +#define USBx_OBSERVE_DMPD ((uint8_t)0x10) /*!< Provides observability of the D- Pulldown signal output from the USB OTG module */ + +/******** Bits definition for USBx_CONTROL register *************/ +#define USBx_CONTROL_DPPULLUPNONOTG ((uint8_t)0x10) /*!< Control pull-ups in device mode */ + +/******** Bits definition for USBx_USBTRC0 register *************/ +#define USBx_USBTRC0_USBRESET ((uint8_t)0x80) /*!< USB reset */ +#define USBx_USBTRC0_USBRESMEN ((uint8_t)0x20) /*!< Asynchronous resume interrupt enable */ +#define USBx_USBTRC0_SYNC_DET ((uint8_t)0x02) /*!< Synchronous USB interrupt detect */ +#define USBx_USBTRC0_USB_RESUME_INT ((uint8_t)0x01) /*!< USB asynchronous interrupt */ + +/****************************************************************/ +/* */ +/* Reset Control Module (RCM): Device independent parts */ +/* */ +/****************************************************************/ +/********** Bits definition for RCM_SRS0 register *************/ +#define RCM_SRS0_POR ((uint8_t)0x80) /*!< Power-On Reset */ +#define RCM_SRS0_PIN ((uint8_t)0x40) /*!< External Reset Pin */ +#define RCM_SRS0_WDOG ((uint8_t)0x20) /*!< Watchdog */ +#define RCM_SRS0_LOL ((uint8_t)0x08) /*!< Loss-of-Lock Reset */ +#define RCM_SRS0_LOC ((uint8_t)0x04) /*!< Loss-of-Clock Reset */ +#define RCM_SRS0_LVD ((uint8_t)0x02) /*!< Low-Voltage Detect Reset */ +#define RCM_SRS0_WAKEUP ((uint8_t)0x01) /*!< Low Leakage Wakeup Reset */ + +/********** Bits definition for RCM_SRS1 register *************/ +#define RCM_SRS1_SACKERR ((uint8_t)0x20) /*!< Stop Mode Acknowledge Error Reset */ +#define RCM_SRS1_MDM_AP ((uint8_t)0x08) /*!< MDM-AP System Reset Request */ +#define RCM_SRS1_SW ((uint8_t)0x04) /*!< Software */ +#define RCM_SRS1_LOCKUP ((uint8_t)0x02) /*!< Core Lockup */ + +/********** Bits definition for RCM_RPFC register *************/ +#define RCM_RPFC_RSTFLTSS ((uint8_t)0x04) /*!< Reset Pin Filter Select in Stop Mode */ +#define RCM_RPFC_RSTFLTSRW_SHIFT 0 /*!< Reset Pin Filter Select in Run and Wait Modes (shift) */ +#define RCM_RPFC_RSTFLTSRW_MASK ((uint8_t)((uint8_t)0x03 << RCM_RPFC_RSTFLTSRW_SHIFT)) /*!< Reset Pin Filter Select in Run and Wait Modes (mask) */ +#define RCM_RPFC_RSTFLTSRW(x) ((uint8_t)(((uint8_t)(x) << RCM_RPFC_RSTFLTSRW_SHIFT) & RCM_RPFC_RSTFLTSRW_MASK)) /*!< Reset Pin Filter Select in Run and Wait Modes */ + +/********** Bits definition for RCM_RPFW register *************/ +#define RCM_RPFW_RSTFLTSEL_SHIFT 0 /*!< Reset Pin Filter Bus Clock Select (shift) */ +#define RCM_RPFW_RSTFLTSEL_MASK ((uint8_t)((uint8_t)0x1F << RCM_RPFW_RSTFLTSEL_SHIFT)) /*!< Reset Pin Filter Bus Clock Select (mask) */ +#define RCM_RPFW_RSTFLTSEL(x) ((uint8_t)(((uint8_t)(x) << RCM_RPFW_RSTFLTSEL_SHIFT) & RCM_RPFW_RSTFLTSEL_MASK)) /*!< Reset Pin Filter Bus Clock Select */ + +/****************************************************************/ +/* */ +/* System Mode Controller (SMC) */ +/* */ +/****************************************************************/ +/********* Bits definition for SMC_PMPROT register ************/ +#define SMC_PMPROT_AVLP ((uint8_t)0x20) /*!< Allow Very-Low-Power Modes */ +#define SMC_PMPROT_ALLS ((uint8_t)0x08) /*!< Allow Low-Leakage Stop Mode */ +#define SMC_PMPROT_AVLLS ((uint8_t)0x02) /*!< Allow Very-Low-Leakage Stop Mode */ + +/********* Bits definition for SMC_PMCTRL register ************/ +#define SMC_PMCTRL_RUNM_SHIFT 5 /*!< Run Mode Control (shift) */ +#define SMC_PMCTRL_RUNM_MASK ((uint8_t)((uint8_t)0x03 << SMC_PMCTRL_RUNM_SHIFT)) /*!< Run Mode Control (mask) */ +#define SMC_PMCTRL_RUNM(x) ((uint8_t)(((uint8_t)(x) << SMC_PMCTRL_RUNM_SHIFT) & SMC_PMCTRL_RUNM_MASK)) /*!< Run Mode Control */ +#define SMC_PMCTRL_STOPA ((uint8_t)0x08) /*!< Stop Aborted */ +#define SMC_PMCTRL_STOPM_SHIFT 0 /*!< Stop Mode Control (shift) */ +#define SMC_PMCTRL_STOPM_MASK ((uint8_t)((uint8_t)0x07 << SMC_PMCTRL_STOPM_SHIFT)) /*!< Stop Mode Control (mask) */ +#define SMC_PMCTRL_STOPM(x) ((uint8_t)(((uint8_t)(x) << SMC_PMCTRL_STOPM_SHIFT) & SMC_PMCTRL_STOPM_MASK)) /*!< Stop Mode Control */ + +#define SMC_PMCTRL_RUNM_RUN ((uint8_t)0x00) +#define SMC_PMCTRL_RUNM_VLPR ((uint8_t)0x02) +#define SMC_PMCTRL_STOPM_STOP ((uint8_t)0x00) +#define SMC_PMCTRL_STOPM_VLPS ((uint8_t)0x02) +#define SMC_PMCTRL_STOPM_LLS ((uint8_t)0x03) +#define SMC_PMCTRL_STOPM_VLLSx ((uint8_t)0x04) + +/******** Bits definition for SMC_STOPCTRL register ***********/ +#define SMC_STOPCTRL_PSTOPO_SHIFT 6 /*!< Partial Stop Option (shift) */ +#define SMC_STOPCTRL_PSTOPO_MASK ((uint8_t)((uint8_t)0x03 << SMC_STOPCTRL_PSTOPO_SHIFT)) /*!< Partial Stop Option (mask) */ +#define SMC_STOPCTRL_PSTOPO(x) ((uint8_t)(((uint8_t)(x) << SMC_STOPCTRL_PSTOPO_SHIFT) & SMC_STOPCTRL_PSTOPO_MASK)) /*!< Partial Stop Option */ +#define SMC_STOPCTRL_PORP0 ((uint8_t)0x20) /*!< POR Power Option */ +#define SMC_STOPCTRL_VLLSM_SHIFT 0 /*!< VLLS Mode Control (shift) */ +#define SMC_STOPCTRL_VLLSM_MASK ((uint8_t)((uint8_t)0x07 << SMC_STOPCTRL_VLLSM_SHIFT)) /*!< VLLS Mode Control (mask) */ +#define SMC_STOPCTRL_VLLSM(x) ((uint8_t)(((uint8_t)(x) << SMC_STOPCTRL_VLLSM_SHIFT) & SMC_STOPCTRL_VLLSM_MASK)) /*!< VLLS Mode Control */ + +#define SMC_STOPCTRL_PSTOPO_STOP ((uint8_t)0x00) +#define SMC_STOPCTRL_PSTOPO_PSTOP1 ((uint8_t)0x01) +#define SMC_STOPCTRL_PSTOPO_PSTOP2 ((uint8_t)0x02) +#define SMC_STOPCTRL_VLLSM_VLLS0 ((uint8_t)0x00) +#define SMC_STOPCTRL_VLLSM_VLLS1 ((uint8_t)0x01) +#define SMC_STOPCTRL_VLLSM_VLLS2 ((uint8_t)0x03) + +/********* Bits definition for SMC_PMSTAT register ************/ +#define SMC_PMSTAT_PMSTAT_SHIFT 0 /*!< Power Mode Status (shift) */ +#define SMC_PMSTAT_PMSTAT_MASK ((uint8_t)((uint8_t)0x7F << SMC_PMSTAT_PMSTAT_SHIFT)) /*!< Power Mode Status (mask) */ +#define SMC_PMSTAT_PMSTAT(x) ((uint8_t)(((uint8_t)(x) << SMC_PMSTAT_PMSTAT_SHIFT) & SMC_PMSTAT_PMSTAT_MASK)) /*!< Power Mode Status */ + +#define SMC_PMSTAT_RUN ((uint8_t)0x01) +#define SMC_PMSTAT_STOP ((uint8_t)0x02) +#define SMC_PMSTAT_VLPR ((uint8_t)0x04) +#define SMC_PMSTAT_VLPW ((uint8_t)0x08) +#define SMC_PMSTAT_VLPS ((uint8_t)0x10) +#define SMC_PMSTAT_LLS ((uint8_t)0x20) +#define SMC_PMSTAT_VLLS ((uint8_t)0x40) + +/****************************************************************/ +/* */ +/* Digital-to-Analog Converter (DAC) */ +/* */ +/****************************************************************/ +/********* Bits definition for DACx_DATnL register ************/ +#define DACx_DATnL_DATA_SHIFT 0 /*!< DAC Data Low Register (shift) */ +#define DACx_DATnL_DATA_MASK ((uint8_t)((uint8_t)0xFF << DACx_DATnL_DATA_SHIFT)) /*!< DAC Data Low Register (mask) */ +#define DACx_DATnL_DATA(x) ((uint8_t)(((uint8_t)(x) << DACx_DATnL_DATA_SHIFT) & DACx_DATnL_DATA_MASK)) /*!< DAC Data Low Register */ + +/********* Bits definition for DACx_DATnH register ************/ +#define DACx_DATnH_DATA_SHIFT 0 /*!< DAC Data High Register (shift) */ +#define DACx_DATnH_DATA_MASK ((uint8_t)((uint8_t)0x0F << DACx_DATnH_DATA_SHIFT)) /*!< DAC Data High Register (mask) */ +#define DACx_DATnH_DATA(x) ((uint8_t)(((uint8_t)(x) << DACx_DATnH_DATA_SHIFT) & DACx_DATnH_DATA_MASK)) /*!< DAC Data High Register */ + +/********** Bits definition for DACx_SR register **************/ +#define DACx_SR_DACBFRPTF ((uint8_t)0x02) /*!< DAC Buffer Read Pointer Top Position Flag */ +#define DACx_SR_DACBFRPBF ((uint8_t)0x01) /*!< DAC Buffer Read Pointer Bottom Position Flag */ + +/********** Bits definition for DACx_C0 register **************/ +#define DACx_C0_DACEN ((uint8_t)0x80) /*!< DAC Enable */ +#define DACx_C0_DACRFS ((uint8_t)0x40) /*!< DAC Reference Select */ +#define DACx_C0_DACTRGSEL ((uint8_t)0x20) /*!< DAC Trigger Select */ +#define DACx_C0_DACSWTRG ((uint8_t)0x10) /*!< DAC Software Trigger */ +#define DACx_C0_LPEN ((uint8_t)0x08) /*!< DAC Low Power Control */ +#define DACx_C0_DACBTIEN ((uint8_t)0x02) /*!< DAC Buffer Read Pointer Top Flag Interrupt Enable */ +#define DACx_C0_DACBBIEN ((uint8_t)0x01) /*!< DAC Buffer Read Pointer Bottom Flag Interrupt Enable */ + +/********** Bits definition for DACx_C1 register **************/ +#define DACx_C1_DMAEN ((uint8_t)0x80) /*!< DMA Enable Select */ +/* Device dependent bits */ +/* #define DACx_C1_DACBFMD ((uint8_t)0x04)*//*!< DAC Buffer Work Mode Select */ +#define DACx_C1_DACBFEN ((uint8_t)0x01) /*!< DAC Buffer Enable */ + +/********** Bits definition for DACx_C2 register **************/ +#define DACx_C2_DACBFRP ((uint8_t)0x10) /*!< DAC Buffer Read Pointer */ +#define DACx_C2_DACBFUP ((uint8_t)0x01) /*!< DAC Buffer Upper Limit */ + +/****************************************************************/ +/* */ +/* Real Time Clock (RTC) */ +/* */ +/****************************************************************/ +/********** Bits definition for RTC_TSR register **************/ +#define RTC_TSR_TSR_SHIFT 0 /*!< RTC Time Seconds Register (shift) */ +#define RTC_TSR_TSR_MASK ((uint32_t)((uint32_t)0xFFFFFFFF << RTC_TSR_TSR_SHIFT)) /*!< RTC Time Seconds Register (mask) */ +#define RTC_TSR_TSR(x) ((uint32_t)(((uint32_t)(x) << RTC_TSR_TSR_SHIFT) & RTC_TSR_TSR_MASK)) /*!< RTC Time Seconds Register */ + +/********** Bits definition for RTC_TPR register **************/ +#define RTC_TPR_TPR_SHIFT 0 /*!< RTC Time Prescaler Register (shift) */ +#define RTC_TPR_TPR_MASK ((uint32_t)((uint32_t)0xFFFF << RTC_TPR_TPR_SHIFT)) /*!< RTC Time Prescaler Register (mask) */ +#define RTC_TPR_TPR(x) ((uint32_t)(((uint32_t)(x) << RTC_TPR_TPR_SHIFT) & RTC_TPR_TPR_MASK)) /*!< RTC Time Prescaler Register */ + +/********** Bits definition for RTC_TAR register **************/ +#define RTC_TAR_TAR_SHIFT 0 /*!< RTC Time Alarm Register (shift) */ +#define RTC_TAR_TAR_MASK ((uint32_t)((uint32_t)0xFFFFFFFF << RTC_TAR_TAR_SHIFT)) /*!< RTC Time Alarm Register (mask) */ +#define RTC_TAR_TAR(x) ((uint32_t)(((uint32_t)(x) << RTC_TAR_TAR_SHIFT) & RTC_TAR_TAR_MASK)) /*!< RTC Time Alarm Register */ + +/********** Bits definition for RTC_TCR register **************/ +#define RTC_TCR_CIC_SHIFT 24 /*!< Compensation Interval Counter (shift) */ +#define RTC_TCR_CIC_MASK ((uint32_t)((uint32_t)0xFF << RTC_TCR_CIC_SHIFT)) /*!< Compensation Interval Counter (mask) */ +#define RTC_TCR_CIC(x) ((uint32_t)(((uint32_t)(x) << RTC_TCR_CIC_SHIFT) & RTC_TCR_CIC_MASK)) /*!< Compensation Interval Counter */ +#define RTC_TCR_TCV_SHIFT 16 /*!< Time Compensation Value (shift) */ +#define RTC_TCR_TCV_MASK ((uint32_t)((uint32_t)0xFF << RTC_TCR_TCV_SHIFT)) /*!< Time Compensation Value (mask) */ +#define RTC_TCR_TCV(x) ((uint32_t)(((uint32_t)(x) << RTC_TCR_TCV_SHIFT) & RTC_TCR_TCV_MASK)) /*!< Time Compensation Value */ +#define RTC_TCR_CIR_SHIFT 8 /*!< Compensation Interval Register (shift) */ +#define RTC_TCR_CIR_MASK ((uint32_t)((uint32_t)0xFF << RTC_TCR_CIR_SHIFT)) /*!< Compensation Interval Register (mask) */ +#define RTC_TCR_CIR(x) ((uint32_t)(((uint32_t)(x) << RTC_TCR_CIR_SHIFT) & RTC_TCR_CIR_MASK)) /*!< Compensation Interval Register */ +#define RTC_TCR_TCR_SHIFT 0 /*!< Time Compensation Register (shift) */ +#define RTC_TCR_TCR_MASK ((uint32_t)((uint32_t)0xFF << RTC_TCR_TCR_SHIFT)) /*!< Time Compensation Register (mask) */ +#define RTC_TCR_TCR(x) ((uint32_t)(((uint32_t)(x) << RTC_TCR_TCR_SHIFT) & RTC_TCR_TCR_MASK)) /*!< Time Compensation Register */ + +/*********** Bits definition for RTC_CR register **************/ +#define RTC_CR_SC2P ((uint32_t)0x2000) /*!< Oscillator 2pF Load Configure */ +#define RTC_CR_SC4P ((uint32_t)0x1000) /*!< Oscillator 4pF Load Configure */ +#define RTC_CR_SC8P ((uint32_t)0x0800) /*!< Oscillator 8pF Load Configure */ +#define RTC_CR_SC16P ((uint32_t)0x0400) /*!< Oscillator 16pF Load Configure */ +#define RTC_CR_CLKO ((uint32_t)0x0200) /*!< Clock Output */ +#define RTC_CR_OSCE ((uint32_t)0x0100) /*!< Oscillator Enable */ +#define RTC_CR_WPS ((uint32_t)0x0010) /*!< Wakeup Pin Select */ +#define RTC_CR_UM ((uint32_t)0x0008) /*!< Update Mode */ +#define RTC_CR_SUP ((uint32_t)0x0004) /*!< Supervisor Access */ +#define RTC_CR_WPE ((uint32_t)0x0002) /*!< Wakeup Pin Enable */ +#define RTC_CR_SWR ((uint32_t)0x0001) /*!< Software Reset */ + +/*********** Bits definition for RTC_SR register **************/ +#define RTC_SR_TCE ((uint32_t)0x10) /*!< Time Counter Enable */ +#define RTC_SR_TAF ((uint32_t)0x04) /*!< Time Alarm Flag */ +#define RTC_SR_TOF ((uint32_t)0x02) /*!< Time Overflow Flag */ +#define RTC_SR_TIF ((uint32_t)0x01) /*!< Time Invalid Flag */ + +/*********** Bits definition for RTC_LR register **************/ +#define RTC_LR_LRL ((uint32_t)0x40) /*!< Lock Register Lock */ +#define RTC_LR_SRL ((uint32_t)0x20) /*!< Status Register Lock */ +#define RTC_LR_CRL ((uint32_t)0x10) /*!< Control Register Lock */ +#define RTC_LR_TCL ((uint32_t)0x08) /*!< Time Compensation Lock */ + +/********** Bits definition for RTC_IER register **************/ +#define RTC_IER_WPON ((uint32_t)0x80) /*!< Wakeup Pin On */ +#define RTC_IER_TSIE ((uint32_t)0x10) /*!< Time Seconds Interrupt Enable */ +#define RTC_IER_TAIE ((uint32_t)0x04) /*!< Time Alarm Interrupt Enable */ +#define RTC_IER_TOIE ((uint32_t)0x02) /*!< Time Overflow Interrupt Enable */ +#define RTC_IER_TIIE ((uint32_t)0x01) /*!< Time Invalid Interrupt Enable */ + +/****************************************************************/ +/* */ +/* Comparator (CMP) */ +/* */ +/****************************************************************/ +/********** Bits definition for CMP_CR0 register **************/ +#define CMP_CR0_FILTER_CNT_SHIFT 4 /*!< Filter Sample Count (shift) */ +#define CMP_CR0_FILTER_CNT_MASK ((uint8_t)((uint8_t)0x07 << CMP_CR0_FILTER_CNT_SHIFT)) /*!< Filter Sample Count (mask) */ +#define CMP_CR0_FILTER_CNT(x) ((uint8_t)(((uint8_t)(x) << CMP_CR0_FILTER_CNT_SHIFT) & CMP_CR0_FILTER_CNT_MASK)) /*!< Filter Sample Count */ +#define CMP_CR0_HYSTCTR_SHIFT 0 /*!< Comparator hard block hysteresis control (shift) */ +#define CMP_CR0_HYSTCTR_MASK ((uint8_t)((uint8_t)0x03 << CMP_CR0_HYSTCTR_SHIFT)) /*!< Comparator hard block hysteresis control (mask) */ +#define CMP_CR0_HYSTCTR(x) ((uint8_t)(((uint8_t)(x) << CMP_CR0_HYSTCTR_SHIFT) & CMP_CR0_HYSTCTR_MASK)) /*!< Comparator hard block hysteresis control */ + +/********** Bits definition for CMP_CR1 register **************/ +#define CMP_CR1_SE ((uint8_t)0x80) /*!< Sample Enable */ +#define CMP_CR1_WE ((uint8_t)0x40) /*!< Windowing Enable */ +#define CMP_CR1_TRIGM ((uint8_t)0x20) /*!< Trigger Mode Enable */ +#define CMP_CR1_PMODE ((uint8_t)0x10) /*!< Power Mode Select */ +#define CMP_CR1_INV ((uint8_t)0x08) /*!< Comparator INVERT */ +#define CMP_CR1_COS ((uint8_t)0x04) /*!< Comparator Output Select */ +#define CMP_CR1_OPE ((uint8_t)0x02) /*!< Comparator Output Pin Enable */ +#define CMP_CR1_EN ((uint8_t)0x01) /*!< Comparator Module Enable */ + +/********** Bits definition for CMP_FPR register **************/ +#define CMP_CR0_FILT_PER_SHIFT 0 /*!< Filter Sample Period (shift) */ +#define CMP_CR0_FILT_PER_MASK ((uint8_t)((uint8_t)0xFF << CMP_CR0_FILT_PER_SHIFT)) /*!< Filter Sample Period (mask) */ +#define CMP_CR0_FILT_PER(x) ((uint8_t)(((uint8_t)(x) << CMP_CR0_FILT_PER_SHIFT) & CMP_CR0_FILT_PER_MASK)) /*!< Filter Sample Period */ + +/********** Bits definition for CMP_SCR register **************/ +#define CMP_SCR_DMAEN ((uint8_t)0x40) /*!< DMA Enable Control */ +#define CMP_SCR_IER ((uint8_t)0x10) /*!< Comparator Interrupt Enable Rising */ +#define CMP_SCR_IEF ((uint8_t)0x08) /*!< Comparator Interrupt Enable Falling */ +#define CMP_SCR_CFR ((uint8_t)0x04) /*!< Analog Comparator Flag Rising */ +#define CMP_SCR_CFF ((uint8_t)0x02) /*!< Analog Comparator Flag Falling */ +#define CMP_SCR_COUT ((uint8_t)0x01) /*!< Analog Comparator Output */ + +/********** Bits definition for CMP_DACCR register ************/ +#define CMP_DACCR_DACEN ((uint8_t)0x80) /*!< DAC Enable */ +#define CMP_DACCR_VRSEL ((uint8_t)0x40) /*!< Supply Voltage Reference Source Select */ +#define CMP_DACCR_VOSEL_SHIFT 0 /*!< DAC Output Voltage Select (shift) */ +#define CMP_DACCR_VOSEL_MASK ((uint8_t)((uint8_t)0x3F << CMP_DACCR_VOSEL_SHIFT)) /*!< DAC Output Voltage Select (mask) */ +#define CMP_DACCR_VOSEL(x) ((uint8_t)(((uint8_t)(x) << CMP_DACCR_VOSEL_SHIFT) & CMP_DACCR_VOSEL_MASK)) /*!< DAC Output Voltage Select */ + +/********** Bits definition for CMP_MUXCR register ************/ +#define CMP_MUXCR_PSTM ((uint8_t)0x80) /*!< Pass Through Mode Enable */ +#define CMP_MUXCR_PSEL_SHIFT 3 /*!< Plus Input Mux Control (shift) */ +#define CMP_MUXCR_PSEL_MASK ((uint8_t)((uint8_t)0x07 << CMP_MUXCR_PSEL_SHIFT)) /*!< Plus Input Mux Control (mask) */ +#define CMP_MUXCR_PSEL(x) ((uint8_t)(((uint8_t)(x) << CMP_MUXCR_PSEL_SHIFT) & CMP_MUXCR_PSEL_MASK)) /*!< Plus Input Mux Control */ +#define CMP_MUXCR_MSEL_SHIFT 0 /*!< Minus Input Mux Control (shift) */ +#define CMP_MUXCR_MSEL_MASK ((uint8_t)((uint8_t)0x07 << CMP_MUXCR_MSEL_SHIFT)) /*!< Minus Input Mux Control (mask) */ +#define CMP_MUXCR_MSEL(x) ((uint8_t)(((uint8_t)(x) << CMP_MUXCR_MSEL_SHIFT) & CMP_MUXCR_MSEL_MASK)) /*!< Minus Input Mux Control */ + +/****************************************************************/ +/* */ +/* Flash Memory Module (FTFA) */ +/* */ +/****************************************************************/ +/********** Bits definition for FTFA_FSTAT register ***********/ +#define FTFA_FSTAT_CCIF ((uint8_t)0x80) /*!< Command Complete Interrupt Flag */ +#define FTFA_FSTAT_RDCOLERR ((uint8_t)0x40) /*!< Flash Read Collision Error Flag */ +#define FTFA_FSTAT_ACCERR ((uint8_t)0x20) /*!< Flash Access Error Flag */ +#define FTFA_FSTAT_FPVIOL ((uint8_t)0x10) /*!< Flash Protection Violation Flag */ +#define FTFA_FSTAT_MGSTAT0 ((uint8_t)0x01) /*!< Memory Controller Command Completion Status Flag */ + +/********** Bits definition for FTFA_FCNFG register ***********/ +#define FTFA_FCNFG_CCIE ((uint8_t)0x80) /*!< Command Complete Interrupt Enable */ +#define FTFA_FCNFG_RDCOLLIE ((uint8_t)0x40) /*!< Read Collision Error Interrupt Enable */ +#define FTFA_FCNFG_ERSAREQ ((uint8_t)0x20) /*!< Erase All Request */ +#define FTFA_FCNFG_ERSSUSP ((uint8_t)0x10) /*!< Erase Suspend */ + +/********** Bits definition for FTFA_FSEC register ************/ +#define FTFA_FSEC_KEYEN_MASK ((uint8_t)0xC0) /*!< Backdoor Key Security Enable */ +#define FTFA_FSEC_MEEN_MASK ((uint8_t)0x30) /*!< Mass Erase Enable Bits */ +#define FTFA_FSEC_FSLACC_MASK ((uint8_t)0x0C) /*!< Freescale Failure Analysis Access Code */ +#define FTFA_FSEC_SEC_MASK ((uint8_t)0x03) /*!< Flash Security */ +#define FTFA_FSEC_KEYEN_ENABLED ((uint8_t)0x80) +#define FTFA_FSEC_MEEN_DISABLED ((uint8_t)0x20) +#define FTFA_FSEC_SEC_UNSECURE ((uint8_t)0x02) + +/********** Bits definition for FTFA_FOPT register ************/ +#define FTFA_FOPT_BOOTSRC_SEL_MASK ((uint8_t)0xC0) /*!< Boot Source Selection */ +#define FTFA_FOPT_FAST_INIT ((uint8_t)0x20) /*!< Initialization Speed */ +#define FTFA_FOPT_RESET_PIN_CFG ((uint8_t)0x08) /*!< Enables/disables control for the RESET pin */ +#define FTFA_FOPT_NMI_DIS ((uint8_t)0x04) /*!< Enables/disables control for the NMI function */ +#define FTFA_FOPT_BOOTPIN_OPT ((uint8_t)0x02) /*!< External pin selects boot options */ +#define FTFA_FOPT_LPBOOT_MASK ((uint8_t)0x11) /*!< Reset value of OUTDIV1 in SIM_CLKDIV1 and RUNM in SMC_PMCTRL */ +#define FTFA_FOPT_LPBOOT_DIV8 ((uint8_t)0x00) +#define FTFA_FOPT_LPBOOT_DIV4 ((uint8_t)0x01) +#define FTFA_FOPT_LPBOOT_DIV2 ((uint8_t)0x10) +#define FTFA_FOPT_LPBOOT_DIV1 ((uint8_t)0x11) + +/****************************************************************/ +/* */ +/* Miscellaneous Control Module (MCM) */ +/* */ +/****************************************************************/ +/********** Bits definition for MCM_PLASC register ************/ +#define MCM_PLASC_ASC_MASK ((uint16_t)0xFF) /*!< Crossbar Switch (AXBS) Slave Configuration */ + +/********** Bits definition for MCM_PLAMC register ************/ +#define MCM_PLASC_AMC_MASK ((uint16_t)0xFF) /*!< Crossbar Switch (AXBS) Master Configuration */ + +/********** Bits definition for MCM_PLACR register ************/ +#define MCM_PLACR_ESFC ((uint32_t)0x00010000) /*!< Enable Stalling Flash Controller */ +#define MCM_PLACR_DFCS ((uint32_t)0x00008000) /*!< Disable Flash Controller Speculation */ +#define MCM_PLACR_EFDS ((uint32_t)0x00004000) /*!< Enable Flash Data Speculation */ +#define MCM_PLACR_DFCC ((uint32_t)0x00002000) /*!< Disable Flash Controller Cache */ +#define MCM_PLACR_DFCIC ((uint32_t)0x00001000) /*!< Disable Flash Controller Instruction Caching */ +#define MCM_PLACR_DFCDA ((uint32_t)0x00000800) /*!< Disable Flash Controller Data Caching */ +#define MCM_PLACR_CFCC ((uint32_t)0x00000400) /*!< Clear Flash Controller Cache */ +#define MCM_PLACR_ARB ((uint32_t)0x00000200) /*!< Arbitration select */ + +/********** Bits definition for MCM_CPO register **************/ +#define MCM_CPO_CPOWOI ((uint32_t)0x00000004) /*!< Compute Operation wakeup on interrupt */ +#define MCM_CPO_CPOACK ((uint32_t)0x00000002) /*!< Compute Operation acknowledge */ +#define MCM_CPO_CPOREQ ((uint32_t)0x00000001) /*!< Compute Operation request */ + +#endif /* _KL2xZ_H_ */ diff --git a/ChibiOS_16.1.5/community/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103x8.ld b/ChibiOS_16.1.5/community/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103x8.ld new file mode 100644 index 0000000..9ba192e --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103x8.ld @@ -0,0 +1,50 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +/* + * ST32F103x8 memory setup. + */ +MEMORY +{ + flash : org = 0x08000000, len = 64k + ram0 : org = 0x20000000, len = 20k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +INCLUDE rules.ld diff --git a/ChibiOS_16.1.5/community/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xC.ld b/ChibiOS_16.1.5/community/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xC.ld new file mode 100644 index 0000000..705a44f --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xC.ld @@ -0,0 +1,50 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +/* + * ST32F103xC memory setup. + */ +MEMORY +{ + flash : org = 0x08000000, len = 256k + ram0 : org = 0x20000000, len = 48k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +INCLUDE rules.ld diff --git a/ChibiOS_16.1.5/community/os/common/ports/MSP430X/chcore.c b/ChibiOS_16.1.5/community/os/common/ports/MSP430X/chcore.c new file mode 100644 index 0000000..7a8d7f2 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ports/MSP430X/chcore.c @@ -0,0 +1,103 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MSP430X/nilcore.c
+ * @brief MSP430X port code.
+ *
+ * @addtogroup MSP430X_CORE
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects <b>directly</b> the context
+ * switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+#if !(__GNUC__ < 6 && __GNUC_MINOR__ < 4) || defined(__OPTIMIZE__)
+__attribute__((naked))
+#endif
+void _port_switch(thread_t *ntp, thread_t *otp) {
+#if (__GNUC__ < 6 && __GNUC_MINOR__ < 4) && !defined(__OPTIMIZE__)
+ asm volatile ("add #4, r1");
+#endif
+ (void)(ntp);
+ (void)(otp);
+#if defined(__MSP430X_LARGE__)
+ asm volatile ("pushm.a #7, R10");
+ asm volatile ("mova r1, @R13");
+ asm volatile ("mova @R12, r1");
+ asm volatile ("popm.a #7, R10");
+ asm volatile ("reta");
+#else
+ asm volatile ("pushm.w #7, R10");
+ asm volatile ("mov r1, @R13");
+ asm volatile ("mov @R12, r1");
+ asm volatile ("popm.w #7, R10");
+ asm volatile ("ret");
+#endif
+}
+
+/**
+ * @brief Start a thread by invoking its work function.
+ * @details If the work function returns @p chThdExit() is automatically
+ * invoked.
+ */
+void _port_thread_start(void) {
+
+ /* See PORT_SETUP_CONTEXT in nilcore.h */
+ chSysUnlock();
+#if defined(__MSP430X_LARGE__)
+ asm volatile ("mova R5, R12");
+ asm volatile ("calla R4");
+#else
+ asm volatile ("mov R5, R12");
+ asm volatile ("call R4");
+#endif
+ chSysHalt(0);
+}
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/common/ports/MSP430X/chcore.h b/ChibiOS_16.1.5/community/os/common/ports/MSP430X/chcore.h new file mode 100644 index 0000000..09f87c4 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ports/MSP430X/chcore.h @@ -0,0 +1,437 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MSP430X/nilcore.h
+ * @brief MSP430X port macros and structures.
+ *
+ * @addtogroup MSP430X_CORE
+ * @{
+ */
+
+#ifndef CHCORE_H
+#define CHCORE_H
+
+#include <msp430.h>
+#include <in430.h>
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Architecture and Compiler
+ * @{
+ */
+/**
+ * @brief Macro defining the port architecture.
+ */
+#define PORT_ARCHITECTURE_MSP430X
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define PORT_ARCHITECTURE_NAME "MSP430X"
+
+/**
+ * @brief Name of the architecture variant.
+ */
+#define PORT_CORE_VARIANT_NAME "MSP430Xv2"
+
+/* The following code is not processed when the file is included from an
+ * asm module because those intrinsic macrosa re not necessarily defined
+ * by the assembler too.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Compiler name and version.
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_COMPILER_NAME "GCC " __VERSION__
+
+#else
+#error "unsupported compiler"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+/**
+ * @brief Port-specific information string.
+ */
+#define PORT_INFO "16 bits code addressing"
+
+/**
+ * @brief This port supports a realtime counter.
+ */
+#define PORT_SUPPORTS_RT FALSE
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ * the idle thread should take no more space than those reserved
+ * by @p PORT_INT_REQUIRED_STACK.
+ * @note In this port it is set to 8.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
+#define PORT_IDLE_THREAD_STACK_SIZE 8
+#endif
+
+/**
+ * @brief Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ * area size.
+ * @note In this port the default is 32 bytes per thread.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
+#define PORT_INT_REQUIRED_STACK 32
+#endif
+
+/**
+ * @brief Enables an alternative timer implementation.
+ * @details Usually the port uses a timer interface defined in the file
+ * @p nilcore_timer.h, if this option is enabled then the file
+ * @p nilcore_timer_alt.h is included instead.
+ */
+#if !defined(PORT_USE_ALT_TIMER)
+#define PORT_USE_ALT_TIMER FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Type of stack and memory alignment enforcement.
+ */
+typedef uint16_t stkalign_t;
+
+/**
+ * @brief Type of natural register size - depends on memory model.
+ */
+#if defined(__MSP430X_LARGE__)
+typedef unsigned __int20 reg_t;
+#else
+typedef uint16_t reg_t;
+#endif
+
+/**
+ * @brief Natural alignment constant.
+ * @note It is the minimum alignment for pointer-size variables.
+ */
+#define PORT_NATURAL_ALIGN 2U
+
+/**
+ * @brief Stack alignment constant.
+ * @note It is the alignement required for the stack pointer.
+ */
+#define PORT_STACK_ALIGN 2U
+
+/**
+ * @brief Working Areas alignment constant.
+ * @note It is the alignment to be enforced for thread working areas.
+ */
+#define PORT_WORKING_AREA_ALIGN 2U
+/** @} */
+
+/**
+ * @brief System saved context.
+ * @details This structure represents the inner stack frame during a context
+ * switching.
+ */
+struct port_intctx {
+ reg_t r4;
+ reg_t r5;
+ reg_t r6;
+ reg_t r7;
+ reg_t r8;
+ reg_t r9;
+ reg_t r10;
+ reg_t r0; /* program counter */
+};
+
+/**
+ * @brief Platform dependent part of the @p thread_t structure.
+ * @details This structure usually contains just the saved stack pointer
+ * defined as a pointer to a @p port_intctx structure.
+ */
+struct port_context {
+ struct port_intctx *sp;
+};
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Platform dependent thread stack setup.
+ * @details This code usually setup the context switching frame represented
+ * by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
+ (tp)->ctx.sp = (struct port_intctx*)(((uint8_t *)(wtop)) - \
+ sizeof(struct port_intctx)); \
+ (tp)->ctx.sp->r4 = (reg_t)pf; \
+ (tp)->ctx.sp->r5 = (reg_t)arg; \
+ (tp)->ctx.sp->r0 = (reg_t)_port_thread_start; \
+}
+
+/**
+ * @brief Static working area allocation.
+ * @details This macro is used to allocate a static thread working area
+ * aligned as both position and size.
+ *
+ * @param[in] s the name to be assigned to the stack array
+ * @param[in] n the stack size to be assigned to the thread
+ */
+#define PORT_WORKING_AREA(s, n) \
+ stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)]
+
+/**
+ * @brief Computes the thread working area global size.
+ * @note There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) ((sizeof(struct port_intctx) - 1) + \
+ (n) + (PORT_INT_REQUIRED_STACK))
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() chSchRescheduleS()
+
+/**
+ * @brief IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) __attribute__ ((interrupt(id))) \
+ void ISR_ ## id (void)
+
+/**
+ * @brief Fast IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) PORT_IRQ_HANDLER(id)
+
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects <b>directly</b> the context
+ * switch performance so optimize here as much as you can.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+#define port_switch(ntp, otp) _port_switch(ntp, otp)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _port_irq_epilogue(void);
+ void _port_switch(thread_t *ntp, thread_t *otp);
+ void _port_thread_start(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Port-related initialization code.
+ */
+static inline void port_init(void) {
+
+}
+
+/**
+ * @brief Returns a word encoding the current interrupts status.
+ *
+ * @return The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+
+ return __get_SR_register();
+}
+
+/**
+ * @brief Checks the interrupt status.
+ *
+ * @param[in] sts the interrupt status word
+ *
+ * @return The interrupt status.
+ * @retvel false the word specified a disabled interrupts status.
+ * @retvel true the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+ return sts & GIE;
+}
+
+/**
+ * @brief Determines the current execution context.
+ *
+ * @return The execution context.
+ * @retval false not running in ISR mode.
+ * @retval true running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+ /* Efficiency would be enhanced by not doing this,
+ * because of implementation details */
+ return __get_SR_register() & GIE;
+}
+
+/**
+ * @brief Kernel-lock action.
+ */
+static inline void port_lock(void) {
+
+ _disable_interrupts();
+ asm volatile("nop");
+}
+
+/**
+ * @brief Kernel-unlock action.
+ */
+static inline void port_unlock(void) {
+ asm volatile("nop");
+ _enable_interrupts();
+}
+
+/**
+ * @brief Kernel-lock action from an interrupt handler.
+ * @note This function is empty in this port.
+ */
+static inline void port_lock_from_isr(void) {
+
+}
+
+/**
+ * @brief Kernel-unlock action from an interrupt handler.
+ * @note This function is empty in this port.
+ */
+static inline void port_unlock_from_isr(void) {
+
+}
+
+/**
+ * @brief Disables all the interrupt sources.
+ */
+static inline void port_disable(void) {
+
+ _disable_interrupts();
+ asm volatile("nop");
+}
+
+/**
+ * @brief Disables the interrupt sources below kernel-level priority.
+ */
+static inline void port_suspend(void) {
+
+ _disable_interrupts();
+ asm volatile("nop");
+}
+
+/**
+ * @brief Enables all the interrupt sources.
+ */
+static inline void port_enable(void) {
+
+ asm volatile("nop");
+ _enable_interrupts();
+}
+
+/**
+ * @brief Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ * The simplest implementation is an empty function or macro but this
+ * would not take advantage of architecture-specific power saving
+ * modes.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+}
+
+/**
+ * @brief Returns the current value of the realtime counter.
+ *
+ * @return The realtime counter value.
+ */
+static inline rtcnt_t port_rt_get_counter_value(void) {
+ /* TODO implement realtime counter */
+ return 0;
+}
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module late inclusions. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+
+#if CH_CFG_ST_TIMEDELTA > 0
+#if !PORT_USE_ALT_TIMER
+#include "chcore_timer.h"
+#else /* PORT_USE_ALT_TIMER */
+#include "chcore_timer_alt.h"
+#endif /* PORT_USE_ALT_TIMER */
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CHCORE_H */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/common/ports/MSP430X/chcore_timer.h b/ChibiOS_16.1.5/community/os/common/ports/MSP430X/chcore_timer.h new file mode 100644 index 0000000..87ea514 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ports/MSP430X/chcore_timer.h @@ -0,0 +1,119 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MSP430X/chcore_timer.h
+ * @brief System timer header file.
+ *
+ * @addtogroup MSP430X_TIMER
+ * @{
+ */
+
+#ifndef CHCORE_TIMER_H
+#define CHCORE_TIMER_H
+
+#include "hal_st.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ *
+ * @param[in] abstime the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_start_alarm(systime_t abstime) {
+
+ stStartAlarm(abstime);
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void port_timer_stop_alarm(void) {
+ stStopAlarm();
+}
+
+/**
+ * @brief Sets the alarm time.
+ *
+ * @param[in] abstime the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_set_alarm(systime_t abstime) {
+
+ stSetAlarm(abstime);
+}
+
+/**
+ * @brief Returns the system time.
+ *
+ * @return The system time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_time(void) {
+
+ return stGetCounter();
+}
+
+/**
+ * @brief Returns the current alarm time.
+ *
+ * @return The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_alarm(void) {
+
+ return stGetAlarm();
+}
+
+#endif /* CHCORE_TIMER_H */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/common/ports/MSP430X/compilers/GCC/chtypes.h b/ChibiOS_16.1.5/community/os/common/ports/MSP430X/compilers/GCC/chtypes.h new file mode 100644 index 0000000..46a074c --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ports/MSP430X/compilers/GCC/chtypes.h @@ -0,0 +1,111 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MSP430X/compilers/GCC/chtypes.h
+ * @brief MSP430X port system types.
+ *
+ * @addtogroup MSP430X_GCC_CORE
+ * @{
+ */
+
+#ifndef CHTYPES_H
+#define CHTYPES_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @name Common constants
+ */
+/**
+ * @brief Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+/**
+ * @brief Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+/** @} */
+
+/**
+ * @name Kernel types
+ * @{
+ */
+typedef uint16_t rtcnt_t; /**< Realtime counter. */
+typedef uint64_t rttime_t; /**< Realtime accumulator. */
+typedef uint16_t syssts_t; /**< System status word. */
+typedef uint8_t tmode_t; /**< Thread flags. */
+typedef uint8_t tstate_t; /**< Thread state. */
+typedef uint8_t trefs_t; /**< Thread references counter. */
+typedef uint8_t tslices_t; /**< Thread time slices counter.*/
+typedef uint8_t tprio_t; /**< Thread priority. */
+typedef int16_t msg_t; /**< Inter-thread message. */
+typedef int32_t eventid_t; /**< Numeric event identifier. */
+typedef uint8_t eventmask_t; /**< Mask of event identifiers. */
+typedef int16_t cnt_t; /**< Generic signed counter. */
+typedef uint16_t ucnt_t; /**< Generic unsigned counter. */
+
+/**
+ * @brief ROM constant modifier.
+ * @note It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief Makes functions not inlineable.
+ * @note If the compiler does not support such attribute then the
+ * realtime counter precision could be degraded.
+ */
+#define NOINLINE __attribute__((noinline))
+
+/**
+ * @brief Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg) \
+ void tname(void *arg)
+
+/**
+ * @brief Packed variable specifier.
+ */
+#define PACKED_VAR __attribute__((packed))
+
+/**
+ * @brief Memory alignment enforcement for variables.
+ */
+#define ALIGNED_VAR(n) __attribute__((aligned(n)))
+
+/**
+ * @brief Size of a pointer.
+ * @note To be used where the sizeof operator cannot be used, preprocessor
+ * expressions for example.
+ */
+#define SIZEOF_PTR 4
+
+/**
+ * @brief True if alignment is low-high in current architecture.
+ */
+#define REVERSE_ORDER 1
+
+#endif /* CHTYPES_H */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/common/ports/MSP430X/compilers/GCC/mk/port.mk b/ChibiOS_16.1.5/community/os/common/ports/MSP430X/compilers/GCC/mk/port.mk new file mode 100644 index 0000000..0ef5378 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/ports/MSP430X/compilers/GCC/mk/port.mk @@ -0,0 +1,7 @@ +# List of the ChibiOS/RT MSP430X port files.
+PORTSRC = ${CHIBIOS_CONTRIB}/os/common/ports/MSP430X/chcore.c
+
+PORTASM =
+
+PORTINC = ${CHIBIOS_CONTRIB}/os/common/ports/MSP430X \
+ ${CHIBIOS_CONTRIB}/os/common/ports/MSP430X/compilers/GCC
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128.ld new file mode 100644 index 0000000..1725c78 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128.ld @@ -0,0 +1,101 @@ +/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * MK20DX128 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x00000000, len = 0x100
+ flash1 : org = 0x00000400, len = 0x10
+ flash2 : org = 0x00000410, len = 128k - 0x410
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x1FFFE000, len = 16k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* Flash region for the configuration bytes.*/
+SECTIONS
+{
+ .cfmprotect : ALIGN(4) SUBALIGN(4)
+ {
+ KEEP(*(.cfmconfig))
+ } > flash1
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash2);
+REGION_ALIAS("XTORS_FLASH_LMA", flash2);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash2);
+REGION_ALIAS("TEXT_FLASH_LMA", flash2);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash2);
+REGION_ALIAS("RODATA_FLASH_LMA", flash2);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash2);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash2);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128BLDR3.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128BLDR3.ld new file mode 100644 index 0000000..986de7c --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128BLDR3.ld @@ -0,0 +1,92 @@ +/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * MK20DX128 memory setup (3k bootloader section).
+ */
+MEMORY
+{
+ flash0 : org = 0x00000c00, len = 128k - 0xc00
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x1FFFE000, len = 16k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128BLDR4.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128BLDR4.ld new file mode 100644 index 0000000..f00dc37 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX128BLDR4.ld @@ -0,0 +1,92 @@ +/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * MK20DX128 memory setup (4k bootloader section).
+ */
+MEMORY
+{
+ flash0 : org = 0x00001000, len = 128k - 0x1000
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x1FFFE000, len = 16k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX256.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX256.ld new file mode 100644 index 0000000..66bc6b8 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX256.ld @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org> + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * MK20DX256 memory setup. + */ +MEMORY +{ + flash0 : org = 0x00000000, len = 0x400 + flash1 : org = 0x00000400, len = 0x10 + flash2 : org = 0x00000410, len = 256k - 0x410 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x1FFF8000, len = 64k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* Flash region for the configuration bytes.*/ +SECTIONS +{ + .cfmprotect : ALIGN(4) SUBALIGN(4) + { + KEEP(*(.cfmconfig)) + } > flash1 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash2); +REGION_ALIAS("XTORS_FLASH_LMA", flash2); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash2); +REGION_ALIAS("TEXT_FLASH_LMA", flash2); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash2); +REGION_ALIAS("RODATA_FLASH_LMA", flash2); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash2); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash2); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash2); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX256BLDR8.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX256BLDR8.ld new file mode 100644 index 0000000..20c3000 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MK20DX256BLDR8.ld @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * MK20DX256 memory setup (8k bootloader section). + */ +MEMORY +{ + flash0 : org = 0x00002000, len = 256k - 0x2000 + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x1FFF8000, len = 64k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MKL26Z64.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MKL26Z64.ld new file mode 100644 index 0000000..6527edc --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MKL26Z64.ld @@ -0,0 +1,101 @@ +/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * KL26Z64 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x00000000, len = 0x100
+ flash1 : org = 0x00000400, len = 0x10
+ flash2 : org = 0x00000410, len = 64k - 0x410
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x1FFFF800, len = 8k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* Flash region for the configuration bytes.*/
+SECTIONS
+{
+ .cfmprotect : ALIGN(4) SUBALIGN(4)
+ {
+ KEEP(*(.cfmconfig))
+ } > flash1
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash2);
+REGION_ALIAS("XTORS_FLASH_LMA", flash2);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash2);
+REGION_ALIAS("TEXT_FLASH_LMA", flash2);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash2);
+REGION_ALIAS("RODATA_FLASH_LMA", flash2);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash2);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash2);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
\ No newline at end of file diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MKL27Z256.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MKL27Z256.ld new file mode 100644 index 0000000..f0f107a --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MKL27Z256.ld @@ -0,0 +1,101 @@ +/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * KL27Z256 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x00000000, len = 0x100
+ flash1 : org = 0x00000400, len = 0x10
+ flash2 : org = 0x00000410, len = 256k - 0x410
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x1FFFE000, len = 32k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* Flash region for the configuration bytes.*/
+SECTIONS
+{
+ .cfmprotect : ALIGN(4) SUBALIGN(4)
+ {
+ KEEP(*(.cfmconfig))
+ } > flash1
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash2);
+REGION_ALIAS("XTORS_FLASH_LMA", flash2);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash2);
+REGION_ALIAS("TEXT_FLASH_LMA", flash2);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash2);
+REGION_ALIAS("RODATA_FLASH_LMA", flash2);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash2);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash2);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MKL2xZ128.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MKL2xZ128.ld new file mode 100644 index 0000000..e2a5e4a --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/MKL2xZ128.ld @@ -0,0 +1,101 @@ +/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ * (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * KL2xZ128 memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x00000000, len = 0x100
+ flash1 : org = 0x00000400, len = 0x10
+ flash2 : org = 0x00000410, len = 128k - 0x410
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x1FFFF000, len = 16k
+ ram1 : org = 0x00000000, len = 0
+ ram2 : org = 0x00000000, len = 0
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x00000000, len = 0
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* Flash region for the configuration bytes.*/
+SECTIONS
+{
+ .cfmprotect : ALIGN(4) SUBALIGN(4)
+ {
+ KEEP(*(.cfmconfig))
+ } > flash1
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash2);
+REGION_ALIAS("XTORS_FLASH_LMA", flash2);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash2);
+REGION_ALIAS("TEXT_FLASH_LMA", flash2);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash2);
+REGION_ALIAS("RODATA_FLASH_LMA", flash2);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash2);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash2);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/NRF51822.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/NRF51822.ld new file mode 100644 index 0000000..d4db7d4 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/NRF51822.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * NRF51822 memory setup. + */ +MEMORY +{ + flash0 : org = 0x00000000, len = 256k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 32k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for HEAP segment.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld new file mode 100644 index 0000000..da05e8a --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * TM4C123xC3 memory setup. + */ +MEMORY +{ + flash0 : org = 0x00000000, len = 32k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 12k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for HEAP segment.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld new file mode 100644 index 0000000..1a1c89e --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * TM4C123xD5 memory setup. + */ +MEMORY +{ + flash0 : org = 0x00000000, len = 64k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 24k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for HEAP segment.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld new file mode 100644 index 0000000..254cb3a --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * TM4C123xE6 memory setup. + */ +MEMORY +{ + flash0 : org = 0x00000000, len = 128k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 32k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for HEAP segment.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld new file mode 100644 index 0000000..f73f9ec --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * TM4C123xH6 memory setup. + */ +MEMORY +{ + flash0 : org = 0x00000000, len = 256k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 32k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for HEAP segment.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld new file mode 100644 index 0000000..0463ba0 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * TM4C129xKC memory setup. + */ +MEMORY +{ + flash0 : org = 0x00000000, len = 512k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 256k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for HEAP segment.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld new file mode 100644 index 0000000..f1846ca --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld @@ -0,0 +1,84 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * TM4C123xH6 memory setup. + */ +MEMORY +{ + flash0 : org = 0x00000000, len = 1m + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 256k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for HEAP segment.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk new file mode 100644 index 0000000..0c2ec7d --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk @@ -0,0 +1,12 @@ +# List of the ChibiOS generic K20x startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K20x \
+ $(CHIBIOS)/os/common/ext/CMSIS/include \
+ $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
+
+STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk new file mode 100644 index 0000000..7ab25de --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk @@ -0,0 +1,3 @@ +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk
+
+STARTUPINC += $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K20x5
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk new file mode 100644 index 0000000..3c8ea09 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x7.mk @@ -0,0 +1,3 @@ +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk
+
+STARTUPINC += $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K20x7
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk new file mode 100644 index 0000000..ca67f10 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk @@ -0,0 +1,12 @@ +# List of the ChibiOS generic KL2x startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/KL2x \
+ $(CHIBIOS)/os/common/ext/CMSIS/include \
+ $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
+
+STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk new file mode 100644 index 0000000..f005ce0 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk @@ -0,0 +1,10 @@ +# List of the ChibiOS generic NRF51 startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S
+
+STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/NRF51822 \
+ $(CHIBIOS)/os/common/ext/CMSIS/include
+
+STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk new file mode 100644 index 0000000..e9c97e5 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk @@ -0,0 +1,11 @@ +# List of the ChibiOS generic TM4C123x startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S + +STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C123x \ + $(CHIBIOS)/os/common/ext/CMSIS/include + +STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk new file mode 100644 index 0000000..e151434 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk @@ -0,0 +1,11 @@ +# List of the ChibiOS generic TM4C129x startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S + +STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C129x \ + $(CHIBIOS)/os/common/ext/CMSIS/include + +STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/K20x5/cmparams.h b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/K20x5/cmparams.h new file mode 100644 index 0000000..8aebbc0 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/K20x5/cmparams.h @@ -0,0 +1,84 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
+ (C) 2015 RedoX https://github.com/RedoXyde
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file GCC/ARMCMx/K20x5/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the Kinetis K20x5.
+ *
+ * @defgroup ARMCMx_K20x5 Kinetis K20x5 Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * Kinetis K20x5 platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 4
+
+/**
+ * @brief Systick unit presence.
+ */
+#define CORTEX_HAS_ST TRUE
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU FALSE
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 48
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "k20x5.h"
+
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/K20x7/cmparams.h b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/K20x7/cmparams.h new file mode 100644 index 0000000..afb3053 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/K20x7/cmparams.h @@ -0,0 +1,80 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
+ (C) 2015 RedoX https://github.com/RedoXyde
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file GCC/ARMCMx/K20x7/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the Kinetis K20x7.
+ *
+ * @defgroup ARMCMx_K20x7 Kinetis K20x7 Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * Kinetis K20x7 platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 4
+
+/**
+ * @brief Systick unit presence.
+ */
+#define CORTEX_HAS_ST TRUE
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU FALSE
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 96
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "k20x7.h"
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/KL2x/cmparams.h b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/KL2x/cmparams.h new file mode 100644 index 0000000..93a7055 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/KL2x/cmparams.h @@ -0,0 +1,92 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
+ (C) 2015 RedoX https://github.com/RedoXyde
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file KL2x/cmparams.h
+ * @brief ARM Cortex-M0+ parameters for the Kinetis KL2x family.
+ *
+ * @defgroup ARMCMx_KL2x Kinetis KL2x Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M0+ specific parameters for the
+ * Kinetis KL2x platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 0
+
+/**
+ * @brief Systick unit presence.
+ */
+#define CORTEX_HAS_ST TRUE
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU FALSE
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 2
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 32
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined (KL25) && !defined (KL26) && \
+ !defined (KL27Zxxx) && !defined (KL27Zxx)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "kl2xz.h"
+
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/NRF51822/cmparams.h b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/NRF51822/cmparams.h new file mode 100644 index 0000000..126acf6 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/NRF51822/cmparams.h @@ -0,0 +1,82 @@ +/*
+ Copyright (C) 2015 Fabio Utzig
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file NRF51822/cmparams.h
+ * @brief ARM Cortex-M0 parameters for the Nordic Semi NRF51822 family.
+ *
+ * @defgroup ARMCMx_NRF51x Nordic semiconductor NRF51x.
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M0 specific parameters for the
+ * NRF51x platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 0
+
+/**
+ * @brief Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU 1
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 2
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 32
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "nrf51.h"
+
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/TM4C123x/cmparams.h b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/TM4C123x/cmparams.h new file mode 100644 index 0000000..933e111 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/TM4C123x/cmparams.h @@ -0,0 +1,112 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TM4C123x/cmparams.h + * @brief ARM Cortex-M4 parameters for the TM4C123x. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 4 + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU 1 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 1 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 3 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 144 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/* If the device type is not externally defined, for example from the Makefile, + then a file named board.h is included. This file must contain a device + definition compatible with the include file.*/ +#if !defined(TM4C1230C3PM) && !defined(TM4C1230D5PM) && \ + !defined(TM4C1230E6PM) && !defined(TM4C1230H6PM) && \ + !defined(TM4C1231C3PM) && !defined(TM4C1231D5PM) && \ + !defined(TM4C1231D5PZ) && !defined(TM4C1231E6PM) && \ + !defined(TM4C1231E6PZ) && !defined(TM4C1231H6PGE) && \ + !defined(TM4C1231H6PM) && !defined(TM4C1231H6PZ) && \ + !defined(TM4C1232C3PM) && !defined(TM4C1232D5PM) && \ + !defined(TM4C1232E6PM) && !defined(TM4C1232H6PM) && \ + !defined(TM4C1233C3PM) && !defined(TM4C1233D5PM) && \ + !defined(TM4C1233D5PZ) && !defined(TM4C1233E6PM) && \ + !defined(TM4C1233E6PZ) && !defined(TM4C1233H6PGE) && \ + !defined(TM4C1233H6PM) && !defined(TM4C1233H6PZ) && \ + !defined(TM4C1236D5PM) && !defined(TM4C1236E6PM) && \ + !defined(TM4C1236H6PM) && !defined(TM4C1237D5PM) && \ + !defined(TM4C1237D5PZ) && !defined(TM4C1237E6PM) && \ + !defined(TM4C1237E6PZ) && !defined(TM4C1237H6PGE) && \ + !defined(TM4C1237H6PM) && !defined(TM4C1237H6PZ) && \ + !defined(TM4C123AE6PM) && !defined(TM4C123AH6PM) && \ + !defined(TM4C123BE6PM) && !defined(TM4C123BE6PZ) && \ + !defined(TM4C123BH6PGE) && !defined(TM4C123BH6PM) && \ + !defined(TM4C123BH6PZ) && !defined(TM4C123BH6ZRB) && \ + !defined(TM4C123FE6PM) && !defined(TM4C123FH6PM) && \ + !defined(TM4C123GE6PM) && !defined(TM4C123GE6PZ) && \ + !defined(TM4C123GH6PGE) && !defined(TM4C123GH6PM) && \ + !defined(TM4C123GH6PZ) && !defined(TM4C123GH6ZRB) && \ + !defined(TM4C123GH5ZXR) +#include "board.h" +#endif + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "tm4c123x.h" + +#if !CORTEX_HAS_MPU != !__MPU_PRESENT +#error "CMSIS __MPU_PRESENT mismatch" +#endif + +#if !CORTEX_HAS_FPU != !__FPU_PRESENT +#error "CMSIS __FPU_PRESENT mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* _CMPARAMS_H_ */ + +/** + * @} + */ diff --git a/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/TM4C129x/cmparams.h b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/TM4C129x/cmparams.h new file mode 100644 index 0000000..1d2661d --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/ARMCMx/devices/TM4C129x/cmparams.h @@ -0,0 +1,96 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TM4C129x/cmparams.h + * @brief ARM Cortex-M4 parameters for the TM4C129x. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 4 + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU 1 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 1 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 3 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 112 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/* If the device type is not externally defined, for example from the Makefile, + then a file named board.h is included. This file must contain a device + definition compatible with the include file.*/ +#if !defined(TM4C1290NCPDT) && !defined(TM4C1290NCZAD) \ + && !defined(TM4C1292NCPDT) && !defined(TM4C1292NCZAD) \ + && !defined(TM4C1294KCPDT) && !defined(TM4C1294NCPDT) \ + && !defined(TM4C1294NCZAD) && !defined(TM4C1297NCZAD) \ + && !defined(TM4C1299KCZAD) && !defined(TM4C1299NCZAD) \ + && !defined(TM4C129CNCPDT) && !defined(TM4C129CNCZAD) \ + && !defined(TM4C129DNCPDT) && !defined(TM4C129DNCZAD) \ + && !defined(TM4C129EKCPDT) && !defined(TM4C129ENCPDT) \ + && !defined(TM4C129ENCZAD) && !defined(TM4C129LNCZAD) \ + && !defined(TM4C129XKCZAD) && !defined(TM4C129XNCZAD) +#include "board.h" +#endif + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "tm4c129x.h" + +#if !CORTEX_HAS_MPU != !__MPU_PRESENT +#error "CMSIS __MPU_PRESENT mismatch" +#endif + +#if !CORTEX_HAS_FPU != !__FPU_PRESENT +#error "CMSIS __FPU_PRESENT mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* _CMPARAMS_H_ */ + +/** + * @} + */ diff --git a/ChibiOS_16.1.5/community/os/common/startup/MSP430X/compilers/GCC/ld/msp430fr5969.ld b/ChibiOS_16.1.5/community/os/common/startup/MSP430X/compilers/GCC/ld/msp430fr5969.ld new file mode 100644 index 0000000..b618455 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/MSP430X/compilers/GCC/ld/msp430fr5969.ld @@ -0,0 +1,390 @@ +/* This file supports MSP430FR5969 devices. */
+/* Version: 1.0 */
+/* ChibiOS linker script, for normal executables */
+
+OUTPUT_ARCH(msp430)
+ENTRY(_start)
+
+MEMORY {
+ SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */
+ PERIPHERAL_8BIT : ORIGIN = 0x0010, LENGTH = 0x00F0 /* END=0x0100, size 240 */
+ PERIPHERAL_16BIT : ORIGIN = 0x0100, LENGTH = 0x0100 /* END=0x0200, size 256 */
+ RAM : ORIGIN = 0x1C00, LENGTH = 0x0800 /* END=0x23FF, size 2048 */
+ INFOMEM : ORIGIN = 0x1800, LENGTH = 0x0200 /* END=0x19FF, size 512 as 4 128-byte segments */
+ INFOA : ORIGIN = 0x1980, LENGTH = 0x0080 /* END=0x19FF, size 128 */
+ INFOB : ORIGIN = 0x1900, LENGTH = 0x0080 /* END=0x197F, size 128 */
+ INFOC : ORIGIN = 0x1880, LENGTH = 0x0080 /* END=0x18FF, size 128 */
+ INFOD : ORIGIN = 0x1800, LENGTH = 0x0080 /* END=0x187F, size 128 */
+ FRAM (rxw) : ORIGIN = 0x4400, LENGTH = 0xBB80 /* END=0xFF7F, size 48000 */
+ VECT1 : ORIGIN = 0xFF90, LENGTH = 0x0002
+ VECT2 : ORIGIN = 0xFF92, LENGTH = 0x0002
+ VECT3 : ORIGIN = 0xFF94, LENGTH = 0x0002
+ VECT4 : ORIGIN = 0xFF96, LENGTH = 0x0002
+ VECT5 : ORIGIN = 0xFF98, LENGTH = 0x0002
+ VECT6 : ORIGIN = 0xFF9A, LENGTH = 0x0002
+ VECT7 : ORIGIN = 0xFF9C, LENGTH = 0x0002
+ VECT8 : ORIGIN = 0xFF9E, LENGTH = 0x0002
+ VECT9 : ORIGIN = 0xFFA0, LENGTH = 0x0002
+ VECT10 : ORIGIN = 0xFFA2, LENGTH = 0x0002
+ VECT11 : ORIGIN = 0xFFA4, LENGTH = 0x0002
+ VECT12 : ORIGIN = 0xFFA6, LENGTH = 0x0002
+ VECT13 : ORIGIN = 0xFFA8, LENGTH = 0x0002
+ VECT14 : ORIGIN = 0xFFAA, LENGTH = 0x0002
+ VECT15 : ORIGIN = 0xFFAC, LENGTH = 0x0002
+ VECT16 : ORIGIN = 0xFFAE, LENGTH = 0x0002
+ VECT17 : ORIGIN = 0xFFB0, LENGTH = 0x0002
+ VECT18 : ORIGIN = 0xFFB2, LENGTH = 0x0002
+ VECT19 : ORIGIN = 0xFFB4, LENGTH = 0x0002
+ VECT20 : ORIGIN = 0xFFB6, LENGTH = 0x0002
+ VECT21 : ORIGIN = 0xFFB8, LENGTH = 0x0002
+ VECT22 : ORIGIN = 0xFFBA, LENGTH = 0x0002
+ VECT23 : ORIGIN = 0xFFBC, LENGTH = 0x0002
+ VECT24 : ORIGIN = 0xFFBE, LENGTH = 0x0002
+ VECT25 : ORIGIN = 0xFFC0, LENGTH = 0x0002
+ VECT26 : ORIGIN = 0xFFC2, LENGTH = 0x0002
+ VECT27 : ORIGIN = 0xFFC4, LENGTH = 0x0002
+ VECT28 : ORIGIN = 0xFFC6, LENGTH = 0x0002
+ VECT29 : ORIGIN = 0xFFC8, LENGTH = 0x0002
+ VECT30 : ORIGIN = 0xFFCA, LENGTH = 0x0002
+ VECT31 : ORIGIN = 0xFFCC, LENGTH = 0x0002
+ VECT32 : ORIGIN = 0xFFCE, LENGTH = 0x0002
+ VECT33 : ORIGIN = 0xFFD0, LENGTH = 0x0002
+ VECT34 : ORIGIN = 0xFFD2, LENGTH = 0x0002
+ VECT35 : ORIGIN = 0xFFD4, LENGTH = 0x0002
+ VECT36 : ORIGIN = 0xFFD6, LENGTH = 0x0002
+ VECT37 : ORIGIN = 0xFFD8, LENGTH = 0x0002
+ VECT38 : ORIGIN = 0xFFDA, LENGTH = 0x0002
+ VECT39 : ORIGIN = 0xFFDC, LENGTH = 0x0002
+ VECT40 : ORIGIN = 0xFFDE, LENGTH = 0x0002
+ VECT41 : ORIGIN = 0xFFE0, LENGTH = 0x0002
+ VECT42 : ORIGIN = 0xFFE2, LENGTH = 0x0002
+ VECT43 : ORIGIN = 0xFFE4, LENGTH = 0x0002
+ VECT44 : ORIGIN = 0xFFE6, LENGTH = 0x0002
+ VECT45 : ORIGIN = 0xFFE8, LENGTH = 0x0002
+ VECT46 : ORIGIN = 0xFFEA, LENGTH = 0x0002
+ VECT47 : ORIGIN = 0xFFEC, LENGTH = 0x0002
+ VECT48 : ORIGIN = 0xFFEE, LENGTH = 0x0002
+ VECT49 : ORIGIN = 0xFFF0, LENGTH = 0x0002
+ VECT50 : ORIGIN = 0xFFF2, LENGTH = 0x0002
+ VECT51 : ORIGIN = 0xFFF4, LENGTH = 0x0002
+ VECT52 : ORIGIN = 0xFFF6, LENGTH = 0x0002
+ VECT53 : ORIGIN = 0xFFF8, LENGTH = 0x0002
+ VECT54 : ORIGIN = 0xFFFA, LENGTH = 0x0002
+ VECT55 : ORIGIN = 0xFFFC, LENGTH = 0x0002
+ RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002
+ BSL : ORIGIN = 0x1000, LENGTH = 0x0800
+ HIFRAM (rxw) : ORIGIN = 0x00010000, LENGTH = 0x00003FFF
+}
+
+PHDRS {
+ vectors PT_LOAD ;
+ stack PT_LOAD ;
+ rodata PT_LOAD ;
+ data PT_LOAD ;
+ text PT_LOAD ;
+ upper_rodata PT_LOAD ;
+ upper_data PT_LOAD ;
+ upper_text PT_LOAD ;
+}
+
+SECTIONS
+{
+ __interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) } > VECT1 :vectors =0x3C00
+ __interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) } > VECT2 =0x3C00
+ __interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) } > VECT3 =0x3C00
+ __interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) } > VECT4 =0x3C00
+ __interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) } > VECT5 =0x3C00
+ __interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) } > VECT6 =0x3C00
+ __interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) } > VECT7 =0x3C00
+ __interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) } > VECT8 =0x3C00
+ __interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) } > VECT9 =0x3C00
+ __interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) } > VECT10 =0x3C00
+ __interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) } > VECT11 =0x3C00
+ __interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) } > VECT12 =0x3C00
+ __interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) } > VECT13 =0x3C00
+ __interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) } > VECT14 =0x3C00
+ __interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) } > VECT15 =0x3C00
+ __interrupt_vector_16 : { KEEP (*(__interrupt_vector_16)) } > VECT16 =0x3C00
+ __interrupt_vector_17 : { KEEP (*(__interrupt_vector_17)) } > VECT17 =0x3C00
+ __interrupt_vector_18 : { KEEP (*(__interrupt_vector_18)) } > VECT18 =0x3C00
+ __interrupt_vector_19 : { KEEP (*(__interrupt_vector_19)) } > VECT19 =0x3C00
+ __interrupt_vector_20 : { KEEP (*(__interrupt_vector_20)) } > VECT20 =0x3C00
+ __interrupt_vector_21 : { KEEP (*(__interrupt_vector_21)) } > VECT21 =0x3C00
+ __interrupt_vector_22 : { KEEP (*(__interrupt_vector_22)) } > VECT22 =0x3C00
+ __interrupt_vector_23 : { KEEP (*(__interrupt_vector_23)) } > VECT23 =0x3C00
+ __interrupt_vector_24 : { KEEP (*(__interrupt_vector_24)) } > VECT24 =0x3C00
+ __interrupt_vector_25 : { KEEP (*(__interrupt_vector_25)) } > VECT25 =0x3C00
+ __interrupt_vector_26 : { KEEP (*(__interrupt_vector_26)) } > VECT26 =0x3C00
+ __interrupt_vector_27 : { KEEP (*(__interrupt_vector_27)) } > VECT27 =0x3C00
+ __interrupt_vector_28 : { KEEP (*(__interrupt_vector_28)) } > VECT28 =0x3C00
+ __interrupt_vector_29 : { KEEP (*(__interrupt_vector_29)) } > VECT29 =0x3C00
+ __interrupt_vector_30 : { KEEP (*(__interrupt_vector_30)) } > VECT30 =0x3C00
+ __interrupt_vector_31 : { KEEP (*(__interrupt_vector_31)) KEEP (*(__interrupt_vector_aes256)) } > VECT31 =0x3C00
+ __interrupt_vector_32 : { KEEP (*(__interrupt_vector_32)) KEEP (*(__interrupt_vector_rtc)) } > VECT32 =0x3C00
+ __interrupt_vector_33 : { KEEP (*(__interrupt_vector_33)) KEEP (*(__interrupt_vector_port4)) } > VECT33 =0x3C00
+ __interrupt_vector_34 : { KEEP (*(__interrupt_vector_34)) KEEP (*(__interrupt_vector_port3)) } > VECT34 =0x3C00
+ __interrupt_vector_35 : { KEEP (*(__interrupt_vector_35)) KEEP (*(__interrupt_vector_timer3_a1)) } > VECT35 =0x3C00
+ __interrupt_vector_36 : { KEEP (*(__interrupt_vector_36)) KEEP (*(__interrupt_vector_timer3_a0)) } > VECT36 =0x3C00
+ __interrupt_vector_37 : { KEEP (*(__interrupt_vector_37)) KEEP (*(__interrupt_vector_port2)) } > VECT37 =0x3C00
+ __interrupt_vector_38 : { KEEP (*(__interrupt_vector_38)) KEEP (*(__interrupt_vector_timer2_a1)) } > VECT38 =0x3C00
+ __interrupt_vector_39 : { KEEP (*(__interrupt_vector_39)) KEEP (*(__interrupt_vector_timer2_a0)) } > VECT39 =0x3C00
+ __interrupt_vector_40 : { KEEP (*(__interrupt_vector_40)) KEEP (*(__interrupt_vector_port1)) } > VECT40 =0x3C00
+ __interrupt_vector_41 : { KEEP (*(__interrupt_vector_41)) KEEP (*(__interrupt_vector_timer1_a1)) } > VECT41 =0x3C00
+ __interrupt_vector_42 : { KEEP (*(__interrupt_vector_42)) KEEP (*(__interrupt_vector_timer1_a0)) } > VECT42 =0x3C00
+ __interrupt_vector_43 : { KEEP (*(__interrupt_vector_43)) KEEP (*(__interrupt_vector_dma)) } > VECT43 =0x3C00
+ __interrupt_vector_44 : { KEEP (*(__interrupt_vector_44)) KEEP (*(__interrupt_vector_usci_a1)) } > VECT44 =0x3C00
+ __interrupt_vector_45 : { KEEP (*(__interrupt_vector_45)) KEEP (*(__interrupt_vector_timer0_a1)) } > VECT45 =0x3C00
+ __interrupt_vector_46 : { KEEP (*(__interrupt_vector_46)) KEEP (*(__interrupt_vector_timer0_a0)) } > VECT46 =0x3C00
+ __interrupt_vector_47 : { KEEP (*(__interrupt_vector_47)) KEEP (*(__interrupt_vector_adc12)) } > VECT47 =0x3C00
+ __interrupt_vector_48 : { KEEP (*(__interrupt_vector_48)) KEEP (*(__interrupt_vector_usci_b0)) } > VECT48 =0x3C00
+ __interrupt_vector_49 : { KEEP (*(__interrupt_vector_49)) KEEP (*(__interrupt_vector_usci_a0)) } > VECT49 =0x3C00
+ __interrupt_vector_50 : { KEEP (*(__interrupt_vector_50)) KEEP (*(__interrupt_vector_wdt)) } > VECT50 =0x3C00
+ __interrupt_vector_51 : { KEEP (*(__interrupt_vector_51)) KEEP (*(__interrupt_vector_timer0_b1)) } > VECT51 =0x3C00
+ __interrupt_vector_52 : { KEEP (*(__interrupt_vector_52)) KEEP (*(__interrupt_vector_timer0_b0)) } > VECT52 =0x3C00
+ __interrupt_vector_53 : { KEEP (*(__interrupt_vector_53)) KEEP (*(__interrupt_vector_comp_e)) } > VECT53 =0x3C00
+ __interrupt_vector_54 : { KEEP (*(__interrupt_vector_54)) KEEP (*(__interrupt_vector_unmi)) } > VECT54 =0x3C00
+ __interrupt_vector_55 : { KEEP (*(__interrupt_vector_55)) KEEP (*(__interrupt_vector_sysnmi)) } > VECT55 =0x3C00
+ __reset_vector :
+ {
+ KEEP (*(__interrupt_vector_56))
+ KEEP (*(__interrupt_vector_reset))
+ KEEP (*(.resetvec))
+ } > RESETVEC
+
+ .stack :
+ {
+ __main_thread_stack_base__ = .;
+ *(.stack)
+ . += __idle_stack_size__;
+ PROVIDE (__stack = .);
+ . = ALIGN(2);
+ __main_thread_stack_end__ = .;
+ } > FRAM :stack
+
+ .rodata :
+ {
+ . = ALIGN(2);
+ *(.plt)
+ *(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*)
+ *(.rodata1)
+ *(.lower.rodata.* .lower.rodata)
+
+ *(.eh_frame_hdr)
+ KEEP (*(.eh_frame))
+ KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)
+ PROVIDE (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+ PROVIDE (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE (__init_array_end = .);
+ PROVIDE (__fini_array_start = .);
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE (__fini_array_end = .);
+ LONG(0); /* Sentinel. */
+
+ /* gcc uses crtbegin.o to find the start of the constructors, so
+ we make sure it is first. Because this is a wildcard, it
+ doesn't matter if the user does not actually link against
+ crtbegin.o; the linker won't look for a file to match a
+ wildcard. The wildcard also means that it doesn't matter which
+ directory crtbegin.o is in. */
+ KEEP (*crtbegin*.o(.ctors))
+
+ /* We don't want to include the .ctor section from from the
+ crtend.o file until after the sorted ctors. The .ctor section
+ from the crtend file contains the end of ctors marker and it
+ must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+
+ KEEP (*crtbegin*.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } > FRAM :rodata
+
+ .data :
+ {
+ . = ALIGN(2);
+ PROVIDE (__datastart = .);
+
+ KEEP (*(.jcr))
+ *(.data.rel.ro.local) *(.data.rel.ro*)
+ *(.dynamic)
+
+ *(.data .data.* .gnu.linkonce.d.*)
+ KEEP (*(.gnu.linkonce.d.*personality*))
+ SORT(CONSTRUCTORS)
+ *(.data1)
+ *(.got.plt) *(.got)
+
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+ . = ALIGN(2);
+ *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)
+
+ . = ALIGN(2);
+ *(.lower.data.* .lower.data)
+ . = ALIGN(2);
+
+ _edata = .;
+ PROVIDE (edata = .);
+ PROVIDE (__dataend = .);
+ } > FRAM :data
+
+ /* Note that crt0 assumes this is a multiple of two; all the
+ start/stop symbols are also assumed word-aligned. */
+ PROVIDE(__romdatastart = LOADADDR(.data));
+ PROVIDE (__romdatacopysize = SIZEOF(.data));
+
+ .bss :
+ {
+ . = ALIGN(2);
+ PROVIDE (__bssstart = .);
+ *(.dynbss)
+ *(.sbss .sbss.*)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(.lower.bss.* .lower.bss)
+ . = ALIGN(2);
+ *(COMMON)
+ PROVIDE (__bssend = .);
+ } > FRAM
+ PROVIDE (__bsssize = SIZEOF(.bss));
+
+ /* This section contains data that is not initialised at startup. */
+ .noinit (NOLOAD) :
+ {
+ . = ALIGN(2);
+ PROVIDE (__noinit_start = .);
+ *(.noinit)
+ . = ALIGN(2);
+ PROVIDE (__noinit_end = .);
+ } > FRAM /* Because I think this has to go right above .bss */
+
+ _end = .;
+ PROVIDE (end = .);
+
+ .text :
+ {
+ PROVIDE (_start = .);
+
+ . = ALIGN(2);
+ KEEP (*(SORT(.crt_*)))
+
+ . = ALIGN(2);
+ KEEP (*(.lowtext))
+
+ . = ALIGN(2);
+ *(.lower.text.* .lower.text)
+
+ . = ALIGN(2);
+ *(.text .stub .text.* .gnu.linkonce.t.* .text:*)
+
+ KEEP (*(.text.*personality*))
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ *(.interp .hash .dynsym .dynstr .gnu.version*)
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+ . = ALIGN(2);
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ KEEP (*(.tm_clone_table))
+ } > FRAM :text
+
+ .upper.rodata :
+ {
+ *(.upper.rodata.* .upper.rodata)
+ } > HIFRAM :upper_rodata
+
+ .upper.data :
+ {
+ __upper_data_init = LOADADDR (.upper.data);
+ /* Status word. */
+ SHORT(1);
+ __high_datastart = .;
+ *(.upper.data.* .upper.data)
+ __high_dataend = .;
+ } > HIFRAM :upper_data
+
+ __rom_highdatacopysize = SIZEOF(.upper.data) - 2;
+ __rom_highdatastart = LOADADDR(.upper.data) + 2;
+
+ .upper.bss :
+ {
+ . = ALIGN(2);
+ __high_bssstart = .;
+ *(.upper.bss.* .upper.bss)
+ . = ALIGN(2);
+ __high_bssend = .;
+ } > HIFRAM
+
+ .upper.text :
+ {
+ . = ALIGN(2);
+ *(.upper.text.* .upper.text)
+ } > HIFRAM :upper_text
+
+ .infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */
+ .infoB : {} > INFOB
+ .infoC : {} > INFOC
+ .infoD : {} > INFOD
+
+ /* The rest are all not normally part of the runtime image. */
+
+ .MP430.attributes 0 :
+ {
+ KEEP (*(.MSP430.attributes))
+ KEEP (*(.gnu.attributes))
+ KEEP (*(__TI_build_attributes))
+ }
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1. */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions. */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2. */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2. */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions. */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+ /* DWARF Extension. */
+ .debug_macro 0 : { *(.debug_macro) }
+
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
+
+INCLUDE msp430fr5969_symbols.ld
diff --git a/ChibiOS_16.1.5/community/os/common/startup/MSP430X/compilers/GCC/ld/msp430fr6989.ld b/ChibiOS_16.1.5/community/os/common/startup/MSP430X/compilers/GCC/ld/msp430fr6989.ld new file mode 100644 index 0000000..b3cd9ce --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/MSP430X/compilers/GCC/ld/msp430fr6989.ld @@ -0,0 +1,437 @@ +/* This file supports MSP430FR6989 devices. */
+/* Version: 1.188 */
+/* ChibiOS linker script, for normal executables */
+
+OUTPUT_ARCH(msp430)
+ENTRY(_start)
+
+MEMORY {
+ TINYRAM : ORIGIN = 0x0006, LENGTH = 0x001A
+ BSL : ORIGIN = 0x1000, LENGTH = 0x0800
+ RAM : ORIGIN = 0x1C00, LENGTH = 0x0800 /* END=0x23FF, size 2048 */
+ INFOMEM : ORIGIN = 0x1800, LENGTH = 0x0200 /* END=0x19FF, size 512 as 4 128-byte segments */
+ INFOA : ORIGIN = 0x1980, LENGTH = 0x0080 /* END=0x19FF, size 128 */
+ INFOB : ORIGIN = 0x1900, LENGTH = 0x0080 /* END=0x197F, size 128 */
+ INFOC : ORIGIN = 0x1880, LENGTH = 0x0080 /* END=0x18FF, size 128 */
+ INFOD : ORIGIN = 0x1800, LENGTH = 0x0080 /* END=0x187F, size 128 */
+ FRAM (rxw) : ORIGIN = 0x4400, LENGTH = 0xBB80 /* END=0xFF7F, size 48000 */
+ HIFRAM (rxw) : ORIGIN = 0x00010000, LENGTH = 0x00013FFF
+ VECT1 : ORIGIN = 0xFF90, LENGTH = 0x0002
+ VECT2 : ORIGIN = 0xFF92, LENGTH = 0x0002
+ VECT3 : ORIGIN = 0xFF94, LENGTH = 0x0002
+ VECT4 : ORIGIN = 0xFF96, LENGTH = 0x0002
+ VECT5 : ORIGIN = 0xFF98, LENGTH = 0x0002
+ VECT6 : ORIGIN = 0xFF9A, LENGTH = 0x0002
+ VECT7 : ORIGIN = 0xFF9C, LENGTH = 0x0002
+ VECT8 : ORIGIN = 0xFF9E, LENGTH = 0x0002
+ VECT9 : ORIGIN = 0xFFA0, LENGTH = 0x0002
+ VECT10 : ORIGIN = 0xFFA2, LENGTH = 0x0002
+ VECT11 : ORIGIN = 0xFFA4, LENGTH = 0x0002
+ VECT12 : ORIGIN = 0xFFA6, LENGTH = 0x0002
+ VECT13 : ORIGIN = 0xFFA8, LENGTH = 0x0002
+ VECT14 : ORIGIN = 0xFFAA, LENGTH = 0x0002
+ VECT15 : ORIGIN = 0xFFAC, LENGTH = 0x0002
+ VECT16 : ORIGIN = 0xFFAE, LENGTH = 0x0002
+ VECT17 : ORIGIN = 0xFFB0, LENGTH = 0x0002
+ VECT18 : ORIGIN = 0xFFB2, LENGTH = 0x0002
+ VECT19 : ORIGIN = 0xFFB4, LENGTH = 0x0002
+ VECT20 : ORIGIN = 0xFFB6, LENGTH = 0x0002
+ VECT21 : ORIGIN = 0xFFB8, LENGTH = 0x0002
+ VECT22 : ORIGIN = 0xFFBA, LENGTH = 0x0002
+ VECT23 : ORIGIN = 0xFFBC, LENGTH = 0x0002
+ VECT24 : ORIGIN = 0xFFBE, LENGTH = 0x0002
+ VECT25 : ORIGIN = 0xFFC0, LENGTH = 0x0002
+ VECT26 : ORIGIN = 0xFFC2, LENGTH = 0x0002
+ VECT27 : ORIGIN = 0xFFC4, LENGTH = 0x0002
+ VECT28 : ORIGIN = 0xFFC6, LENGTH = 0x0002
+ VECT29 : ORIGIN = 0xFFC8, LENGTH = 0x0002
+ VECT30 : ORIGIN = 0xFFCA, LENGTH = 0x0002
+ VECT31 : ORIGIN = 0xFFCC, LENGTH = 0x0002
+ VECT32 : ORIGIN = 0xFFCE, LENGTH = 0x0002
+ VECT33 : ORIGIN = 0xFFD0, LENGTH = 0x0002
+ VECT34 : ORIGIN = 0xFFD2, LENGTH = 0x0002
+ VECT35 : ORIGIN = 0xFFD4, LENGTH = 0x0002
+ VECT36 : ORIGIN = 0xFFD6, LENGTH = 0x0002
+ VECT37 : ORIGIN = 0xFFD8, LENGTH = 0x0002
+ VECT38 : ORIGIN = 0xFFDA, LENGTH = 0x0002
+ VECT39 : ORIGIN = 0xFFDC, LENGTH = 0x0002
+ VECT40 : ORIGIN = 0xFFDE, LENGTH = 0x0002
+ VECT41 : ORIGIN = 0xFFE0, LENGTH = 0x0002
+ VECT42 : ORIGIN = 0xFFE2, LENGTH = 0x0002
+ VECT43 : ORIGIN = 0xFFE4, LENGTH = 0x0002
+ VECT44 : ORIGIN = 0xFFE6, LENGTH = 0x0002
+ VECT45 : ORIGIN = 0xFFE8, LENGTH = 0x0002
+ VECT46 : ORIGIN = 0xFFEA, LENGTH = 0x0002
+ VECT47 : ORIGIN = 0xFFEC, LENGTH = 0x0002
+ VECT48 : ORIGIN = 0xFFEE, LENGTH = 0x0002
+ VECT49 : ORIGIN = 0xFFF0, LENGTH = 0x0002
+ VECT50 : ORIGIN = 0xFFF2, LENGTH = 0x0002
+ VECT51 : ORIGIN = 0xFFF4, LENGTH = 0x0002
+ VECT52 : ORIGIN = 0xFFF6, LENGTH = 0x0002
+ VECT53 : ORIGIN = 0xFFF8, LENGTH = 0x0002
+ VECT54 : ORIGIN = 0xFFFA, LENGTH = 0x0002
+ VECT55 : ORIGIN = 0xFFFC, LENGTH = 0x0002
+ RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002
+}
+
+PHDRS {
+ vectors PT_LOAD ;
+ stack PT_LOAD ;
+ rodata PT_LOAD ;
+ data PT_LOAD ;
+ text PT_LOAD ;
+ upper_rodata PT_LOAD ;
+ upper_data PT_LOAD ;
+ upper_text PT_LOAD ;
+}
+
+SECTIONS
+{
+ __interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) } > VECT1 :vectors
+ __interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) } > VECT2
+ __interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) } > VECT3
+ __interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) } > VECT4
+ __interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) } > VECT5
+ __interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) } > VECT6
+ __interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) } > VECT7
+ __interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) } > VECT8
+ __interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) } > VECT9
+ __interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) } > VECT10
+ __interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) } > VECT11
+ __interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) } > VECT12
+ __interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) } > VECT13
+ __interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) } > VECT14
+ __interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) } > VECT15
+ __interrupt_vector_16 : { KEEP (*(__interrupt_vector_16)) } > VECT16
+ __interrupt_vector_17 : { KEEP (*(__interrupt_vector_17)) } > VECT17
+ __interrupt_vector_18 : { KEEP (*(__interrupt_vector_18)) } > VECT18
+ __interrupt_vector_19 : { KEEP (*(__interrupt_vector_19)) } > VECT19
+ __interrupt_vector_20 : { KEEP (*(__interrupt_vector_20)) } > VECT20
+ __interrupt_vector_21 : { KEEP (*(__interrupt_vector_21)) } > VECT21
+ __interrupt_vector_22 : { KEEP (*(__interrupt_vector_22)) } > VECT22
+ __interrupt_vector_23 : { KEEP (*(__interrupt_vector_23)) } > VECT23
+ __interrupt_vector_24 : { KEEP (*(__interrupt_vector_24)) } > VECT24
+ __interrupt_vector_25 : { KEEP (*(__interrupt_vector_25)) } > VECT25
+ __interrupt_vector_26 : { KEEP (*(__interrupt_vector_26)) } > VECT26
+ __interrupt_vector_27 : { KEEP (*(__interrupt_vector_27)) } > VECT27
+ __interrupt_vector_28 : { KEEP (*(__interrupt_vector_28)) KEEP (*(__interrupt_vector_aes256)) } > VECT28
+ __interrupt_vector_29 : { KEEP (*(__interrupt_vector_29)) KEEP (*(__interrupt_vector_rtc)) } > VECT29
+ __interrupt_vector_30 : { KEEP (*(__interrupt_vector_30)) KEEP (*(__interrupt_vector_lcd_c)) } > VECT30
+ __interrupt_vector_31 : { KEEP (*(__interrupt_vector_31)) KEEP (*(__interrupt_vector_port4)) } > VECT31
+ __interrupt_vector_32 : { KEEP (*(__interrupt_vector_32)) KEEP (*(__interrupt_vector_port3)) } > VECT32
+ __interrupt_vector_33 : { KEEP (*(__interrupt_vector_33)) KEEP (*(__interrupt_vector_timer3_a1)) } > VECT33
+ __interrupt_vector_34 : { KEEP (*(__interrupt_vector_34)) KEEP (*(__interrupt_vector_timer3_a0)) } > VECT34
+ __interrupt_vector_35 : { KEEP (*(__interrupt_vector_35)) KEEP (*(__interrupt_vector_port2)) } > VECT35
+ __interrupt_vector_36 : { KEEP (*(__interrupt_vector_36)) KEEP (*(__interrupt_vector_timer2_a1)) } > VECT36
+ __interrupt_vector_37 : { KEEP (*(__interrupt_vector_37)) KEEP (*(__interrupt_vector_timer2_a0)) } > VECT37
+ __interrupt_vector_38 : { KEEP (*(__interrupt_vector_38)) KEEP (*(__interrupt_vector_port1)) } > VECT38
+ __interrupt_vector_39 : { KEEP (*(__interrupt_vector_39)) KEEP (*(__interrupt_vector_timer1_a1)) } > VECT39
+ __interrupt_vector_40 : { KEEP (*(__interrupt_vector_40)) KEEP (*(__interrupt_vector_timer1_a0)) } > VECT40
+ __interrupt_vector_41 : { KEEP (*(__interrupt_vector_41)) KEEP (*(__interrupt_vector_dma)) } > VECT41
+ __interrupt_vector_42 : { KEEP (*(__interrupt_vector_42)) KEEP (*(__interrupt_vector_usci_b1)) } > VECT42
+ __interrupt_vector_43 : { KEEP (*(__interrupt_vector_43)) KEEP (*(__interrupt_vector_usci_a1)) } > VECT43
+ __interrupt_vector_44 : { KEEP (*(__interrupt_vector_44)) KEEP (*(__interrupt_vector_timer0_a1)) } > VECT44
+ __interrupt_vector_45 : { KEEP (*(__interrupt_vector_45)) KEEP (*(__interrupt_vector_timer0_a0)) } > VECT45
+ __interrupt_vector_46 : { KEEP (*(__interrupt_vector_46)) KEEP (*(__interrupt_vector_adc12)) } > VECT46
+ __interrupt_vector_47 : { KEEP (*(__interrupt_vector_47)) KEEP (*(__interrupt_vector_usci_b0)) } > VECT47
+ __interrupt_vector_48 : { KEEP (*(__interrupt_vector_48)) KEEP (*(__interrupt_vector_usci_a0)) } > VECT48
+ __interrupt_vector_49 : { KEEP (*(__interrupt_vector_49)) KEEP (*(__interrupt_vector_escan_if)) } > VECT49
+ __interrupt_vector_50 : { KEEP (*(__interrupt_vector_50)) KEEP (*(__interrupt_vector_wdt)) } > VECT50
+ __interrupt_vector_51 : { KEEP (*(__interrupt_vector_51)) KEEP (*(__interrupt_vector_timer0_b1)) } > VECT51
+ __interrupt_vector_52 : { KEEP (*(__interrupt_vector_52)) KEEP (*(__interrupt_vector_timer0_b0)) } > VECT52
+ __interrupt_vector_53 : { KEEP (*(__interrupt_vector_53)) KEEP (*(__interrupt_vector_comp_e)) } > VECT53
+ __interrupt_vector_54 : { KEEP (*(__interrupt_vector_54)) KEEP (*(__interrupt_vector_unmi)) } > VECT54
+ __interrupt_vector_55 : { KEEP (*(__interrupt_vector_55)) KEEP (*(__interrupt_vector_sysnmi)) } > VECT55
+ __reset_vector :
+ {
+ KEEP (*(__interrupt_vector_56))
+ KEEP (*(__interrupt_vector_reset))
+ KEEP (*(.resetvec))
+ } > RESETVEC
+
+ .stack :
+ {
+ __main_thread_stack_base__ = .;
+ *(.stack)
+ . += __idle_stack_size__;
+ PROVIDE (__stack = .);
+ . = ALIGN(2);
+ __main_thread_stack_end__ = .;
+ } > FRAM :stack
+
+ .rodata :
+ {
+ . = ALIGN(2);
+ *(.plt)
+ *(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*)
+ *(.rodata1)
+ *(.lower.rodata.* .lower.rodata)
+ KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)
+ PROVIDE (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+ PROVIDE (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE (__init_array_end = .);
+ PROVIDE (__fini_array_start = .);
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE (__fini_array_end = .);
+ } > FRAM :rodata
+
+ /* Note: This is a separate .rodata section for sections which are
+ read only but which older linkers treat as read-write.
+ This prevents older linkers from marking the entire .rodata
+ section as read-write. */
+ .rodata2 :
+ {
+ . = ALIGN(2);
+ *(.eh_frame_hdr)
+ KEEP (*(.eh_frame))
+
+ /* gcc uses crtbegin.o to find the start of the constructors, so
+ we make sure it is first. Because this is a wildcard, it
+ doesn't matter if the user does not actually link against
+ crtbegin.o; the linker won't look for a file to match a
+ wildcard. The wildcard also means that it doesn't matter which
+ directory crtbegin.o is in. */
+ KEEP (*crtbegin*.o(.ctors))
+
+ /* We don't want to include the .ctor section from from the
+ crtend.o file until after the sorted ctors. The .ctor section
+ from the crtend file contains the end of ctors marker and it
+ must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+
+ KEEP (*crtbegin*.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } > FRAM
+
+ .data :
+ {
+ . = ALIGN(2);
+ PROVIDE (__datastart = .);
+
+ KEEP (*(.jcr))
+ *(.data.rel.ro.local) *(.data.rel.ro*)
+ *(.dynamic)
+
+ *(.data .data.* .gnu.linkonce.d.*)
+ KEEP (*(.gnu.linkonce.d.*personality*))
+ SORT(CONSTRUCTORS)
+ *(.data1)
+ *(.got.plt) *(.got)
+
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+ . = ALIGN(2);
+ *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)
+
+ . = ALIGN(2);
+ *(.lower.data.* .lower.data)
+ . = ALIGN(2);
+
+ _edata = .;
+ PROVIDE (edata = .);
+ PROVIDE (__dataend = .);
+ } > FRAM :data
+
+ /* Note that crt0 assumes this is a multiple of two; all the
+ start/stop symbols are also assumed word-aligned. */
+ PROVIDE(__romdatastart = LOADADDR(.data));
+ PROVIDE (__romdatacopysize = SIZEOF(.data));
+
+ .bss :
+ {
+ . = ALIGN(2);
+ PROVIDE (__bssstart = .);
+ *(.dynbss)
+ *(.sbss .sbss.*)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(.lower.bss.* .lower.bss)
+ . = ALIGN(2);
+ *(COMMON)
+ PROVIDE (__bssend = .);
+ } > FRAM
+ PROVIDE (__bsssize = SIZEOF(.bss));
+
+ /* This section contains data that is not initialised during load
+ or application reset. */
+ .noinit (NOLOAD) :
+ {
+ . = ALIGN(2);
+ PROVIDE (__noinit_start = .);
+ *(.noinit)
+ . = ALIGN(2);
+ PROVIDE (__noinit_end = .);
+ } > FRAM :text
+
+ _end = .;
+ PROVIDE (end = .);
+
+ .text :
+ {
+ PROVIDE (_start = .);
+
+ . = ALIGN(2);
+ KEEP (*(SORT(.crt_*)))
+
+ . = ALIGN(2);
+ KEEP (*(.lowtext))
+
+ . = ALIGN(2);
+ *(.lower.text.* .lower.text)
+
+ . = ALIGN(2);
+ *(.text .stub .text.* .gnu.linkonce.t.* .text:*)
+
+ KEEP (*(.text.*personality*))
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ *(.interp .hash .dynsym .dynstr .gnu.version*)
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+ . = ALIGN(2);
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ KEEP (*(.tm_clone_table))
+ } > FRAM
+
+ .upper.rodata :
+ {
+ *(.upper.rodata.* .upper.rodata)
+ } > HIFRAM :upper_rodata
+
+ /* This section contains data that is initialised during load
+ but not on application reset. */
+ .persistent :
+ {
+ . = ALIGN(2);
+ PROVIDE (__persistent_start = .);
+ *(.persistent)
+ . = ALIGN(2);
+ PROVIDE (__persistent_end = .);
+ } > HIFRAM :upper_data
+
+ .upper.data :
+ {
+ __upper_data_init = LOADADDR (.upper.data);
+ /* Status word. */
+ SHORT(1);
+ __high_datastart = .;
+ *(.upper.data.* .upper.data)
+ __high_dataend = .;
+ } > HIFRAM
+
+ __rom_highdatacopysize = SIZEOF(.upper.data) - 2;
+ __rom_highdatastart = LOADADDR(.upper.data) + 2;
+
+ .upper.bss :
+ {
+ . = ALIGN(2);
+ __high_bssstart = .;
+ *(.upper.bss.* .upper.bss)
+ . = ALIGN(2);
+ __high_bssend = .;
+ __high_bsssize = SIZEOF(.upper.bss);
+ } > HIFRAM
+
+ .upper.text :
+ {
+ . = ALIGN(2);
+ *(.upper.text.* .upper.text)
+ } > HIFRAM :upper_text
+
+ /* We create this section so that "end" will always be in the
+ RAM region (matching .stack below), even if the .bss
+ section is empty. */
+ .heap (NOLOAD) :
+ {
+ . = ALIGN(2);
+ __heap_start__ = .;
+ _end = __heap_start__;
+ PROVIDE (end = .);
+ KEEP (*(.heap))
+ _end = .;
+ PROVIDE (end = .);
+ /* This word is here so that the section is not empty, and thus
+ not discarded by the linker. The actual value does not matter
+ and is ignored. */
+ LONG(0);
+ __heap_end__ = .;
+ __HeapLimit = __heap_end__;
+ } > RAM
+ /* WARNING: Do not place anything in RAM here.
+ The heap section must be the last section in RAM and the stack
+ section must be placed at the very end of the RAM region. */
+
+ .infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */
+ .infoB : {} > INFOB
+ .infoC : {} > INFOC
+ .infoD : {} > INFOD
+
+ /* The rest are all not normally part of the runtime image. */
+
+ .MP430.attributes 0 :
+ {
+ KEEP (*(.MSP430.attributes))
+ KEEP (*(.gnu.attributes))
+ KEEP (*(__TI_build_attributes))
+ }
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1. */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions. */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2. */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2. */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions. */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+ /* DWARF Extension. */
+ .debug_macro 0 : { *(.debug_macro) }
+
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
+
+
+/****************************************************************************/
+/* Include peripherals memory map */
+/****************************************************************************/
+
+INCLUDE msp430fr6989_symbols.ld
+
diff --git a/ChibiOS_16.1.5/community/os/common/startup/MSP430X/compilers/GCC/mk/startup_msp430fr5xxx.mk b/ChibiOS_16.1.5/community/os/common/startup/MSP430X/compilers/GCC/mk/startup_msp430fr5xxx.mk new file mode 100644 index 0000000..9c063cd --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/MSP430X/compilers/GCC/mk/startup_msp430fr5xxx.mk @@ -0,0 +1,10 @@ +# List of the ChibiOS generic MSP430X startup and linker files.
+STARTUPSRC =
+#$(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC/vectors.c
+
+STARTUPASM =
+
+STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC
+
+STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC/ld
+
diff --git a/ChibiOS_16.1.5/community/os/common/startup/MSP430X/compilers/GCC/rules.mk b/ChibiOS_16.1.5/community/os/common/startup/MSP430X/compilers/GCC/rules.mk new file mode 100644 index 0000000..a431b96 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/common/startup/MSP430X/compilers/GCC/rules.mk @@ -0,0 +1,269 @@ +# ARM Cortex-Mx common makefile scripts and rules.
+
+##############################################################################
+# Processing options coming from the upper Makefile.
+#
+
+# Compiler options
+OPT = $(USE_OPT)
+COPT = $(USE_COPT)
+CPPOPT = $(USE_CPPOPT)
+
+# Garbage collection
+ifeq ($(USE_LINK_GC),yes)
+ OPT += -ffunction-sections -fdata-sections -fno-common
+ LDOPT := ,--gc-sections
+else
+ LDOPT :=
+endif
+
+# Linker extra options
+ifneq ($(USE_LDOPT),)
+ LDOPT := $(LDOPT),$(USE_LDOPT)
+endif
+
+# Link time optimizations
+ifeq ($(USE_LTO),yes)
+ OPT += -flto
+endif
+
+# HWMULT-related options
+ifeq ($(USE_HWMULT),)
+ USE_HWMULT = none
+endif
+ifneq ($(USE_HWMULT),none)
+ OPT += -mhwmult=$(USE_HWMULT)
+endif
+
+# Idle thread stack size
+ifeq ($(USE_IDLE_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__idle_stack_size__=0x40
+else
+ LDOPT := $(LDOPT),--defsym=__idle_stack_size__=$(USE_IDLE_STACKSIZE)
+endif
+
+# Output directory and files
+ifeq ($(BUILDDIR),)
+ BUILDDIR = build
+endif
+ifeq ($(BUILDDIR),.)
+ BUILDDIR = build
+endif
+OUTFILES = $(BUILDDIR)/$(PROJECT).elf \
+ $(BUILDDIR)/$(PROJECT).hex \
+ $(BUILDDIR)/$(PROJECT).bin \
+ $(BUILDDIR)/$(PROJECT).dmp \
+ $(BUILDDIR)/$(PROJECT).list
+
+ifdef SREC
+ OUTFILES += $(BUILDDIR)/$(PROJECT).srec
+endif
+
+# Source files groups and paths
+ACSRC = $(CSRC)
+ACPPSRC = $(CPPSRC)
+ASRC = $(CSRC)$(CPPSRC)
+SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
+
+# Various directories
+OBJDIR = $(BUILDDIR)/obj
+LSTDIR = $(BUILDDIR)/lst
+
+# Object files groups
+ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o)))
+ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o)))
+ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
+ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
+
+# Paths
+IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
+LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+
+# Macros
+DEFS = $(DDEFS) $(UDEFS)
+ADEFS = $(DADEFS) $(UADEFS)
+
+# Libs
+LIBS = $(DLIBS) $(ULIBS)
+
+# Various settings
+MCFLAGS = -mmcu=$(MCU) $(MOPT)
+ODFLAGS = -x --syms
+ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
+CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
+CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
+LDFLAGS = $(MCFLAGS) $(OPT) -minrt $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH)/ld,--script=$(LDSCRIPT)$(LDOPT)
+
+# Temporary specfile to deal with messed-up msp430-elf default spec file
+SPECFILE := $(shell mktemp -u)
+
+# Generate dependency information
+ASFLAGS += -MD -MP -MF .dep/$(@F).d
+CFLAGS += -MD -MP -MF .dep/$(@F).d
+CPPFLAGS += -MD -MP -MF .dep/$(@F).d
+
+# Paths where to search for sources
+VPATH = $(SRCPATHS)
+
+#
+# Makefile rules
+#
+
+all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK
+
+PRE_MAKE_ALL_RULE_HOOK:
+
+POST_MAKE_ALL_RULE_HOOK:
+
+$(OBJS): | $(BUILDDIR) $(OBJDIR) $(LSTDIR)
+
+$(BUILDDIR):
+ifneq ($(USE_VERBOSE_COMPILE),yes)
+ @echo Compiler Options
+ @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
+ @echo
+endif
+ @mkdir -p $(BUILDDIR)
+
+$(OBJDIR):
+ @mkdir -p $(OBJDIR)
+
+$(LSTDIR):
+ @mkdir -p $(LSTDIR)
+
+$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ACOBJS) : $(OBJDIR)/%.o : %.c Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCOBJS) : $(OBJDIR)/%.o : %.c Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+# This is gcc-specific - if LD isn't gcc it will fail
+$(SPECFILE) :
+ $(LD) -dumpspecs > $(SPECFILE)
+ sed -i 's/%{!T.*}//' $(SPECFILE)
+
+$(BUILDDIR)/$(PROJECT).elf: $(OBJS) $(LDSCRIPT) $(SPECFILE)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(LD) $(LDFLAGS) -specs=$(SPECFILE) $(OBJS) $(LIBS) -o $@
+else
+ @echo Linking $@
+ @$(LD) $(LDFLAGS) -specs=$(SPECFILE) $(OBJS) $(LIBS) -o $@
+endif
+
+%.hex: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(HEX) $< $@
+else
+ @echo Creating $@
+ @$(HEX) $< $@
+endif
+
+%.bin: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(BIN) $< $@
+else
+ @echo Creating $@
+ @$(BIN) $< $@
+endif
+
+%.srec: %.elf
+ifdef SREC
+ ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(SREC) $< $@
+ else
+ @echo Creating $@
+ @$(SREC) $< $@
+ endif
+endif
+
+%.dmp: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(OD) $(ODFLAGS) $< > $@
+ $(SZ) $<
+else
+ @echo Creating $@
+ @$(OD) $(ODFLAGS) $< > $@
+ @echo
+ @$(SZ) $<
+endif
+
+%.list: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(OD) -S $< > $@
+else
+ @echo Creating $@
+ @$(OD) -S $< > $@
+ @echo
+ @echo Done
+endif
+
+lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a
+
+$(BUILDDIR)/lib$(PROJECT).a: $(OBJS)
+ @$(AR) -r $@ $^
+ @echo
+ @echo Done
+
+clean:
+ @echo Cleaning
+ -rm -fR .dep $(BUILDDIR)
+ @echo
+ @echo Done
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+# *** EOF ***
|