diff options
Diffstat (limited to 'ChibiOS_16.1.5/community/os/hal')
225 files changed, 0 insertions, 81653 deletions
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR5969/board.c b/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR5969/board.c deleted file mode 100644 index ac48ba0..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR5969/board.c +++ /dev/null @@ -1,46 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#include "hal.h"
-
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-const PALConfig pal_default_config =
-{
- {VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0,
- VAL_IOPORT1_SEL1, VAL_IOPORT1_IES, VAL_IOPORT1_IE},
- {VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0,
- VAL_IOPORT2_SEL1, VAL_IOPORT2_IES, VAL_IOPORT2_IE},
- {VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0,
- VAL_IOPORT0_SEL1, VAL_IOPORT0_IES, VAL_IOPORT0_IE}
-}; /* Set UART TX pin correctly */
-#endif /* HAL_USE_PAL */
-
-/**
- * Board-specific initialization code.
- */
-void boardInit(void) {
-
- /*
- * External interrupts setup, all disabled initially.
- */
- _disable_interrupts();
-
-}
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR5969/board.h b/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR5969/board.h deleted file mode 100644 index 97103d3..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR5969/board.h +++ /dev/null @@ -1,129 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for the EXP430FR5969 LaunchPad board
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_EXP430FR5959
-#define BOARD_NAME "MSP430FR5969 LaunchPad"
-
-/*
- * IO lines assignments.
- */
-#define LINE_LED_G PAL_LINE(IOPORT1, 0U)
-#define LINE_LED_R PAL_LINE(IOPORT2, 14U)
-#define LINE_SW_S1 PAL_LINE(IOPORT2, 13U)
-#define LINE_SW_S2 PAL_LINE(IOPORT1, 1U)
-
-/*
- * I/O ports initial setup, this configuration is established soon after reset
- * in the initialization code.
- * Please refer to the MSP430X Family Users Guide for details.
- */
-/*
- * Port A setup:
- *
- * P1.0 - Green LED (output low)
- * P1.1 - Switch S2 (input pullup)
- * P1.2 - BoosterPack BP19 (input pullup)
- * P1.3 - BoosterPack BP11 (input pullup)
- * P1.4 - BoosterPack BP12 (input pullup)
- * P1.5 - BoosterPack BP13 (input pullup)
- * P1.6 - BoosterPack BP15 (input pullup)
- * P1.7 - BoosterPack BP14 (input pullup)
- * P2.0 - Application UART TX (alternate 2)
- * P2.1 - Application UART RX (alternate 2)
- * P2.2 - BoosterPack BP7 (input pullup)
- * P2.3 - N/C (input pullup)
- * P2.4 - BoosterPack BP6 (input pullup)
- * P2.5 - BoosterPack BP4 (input pullup)
- * P2.6 - BoosterPack BP3 (input pullup)
- * P2.7 - N/C (input pullup)
- */
-#define VAL_IOPORT1_OUT 0xFCFE
-#define VAL_IOPORT1_DIR 0x0001
-#define VAL_IOPORT1_REN 0xFCFE
-#define VAL_IOPORT1_SEL0 0x0000
-#define VAL_IOPORT1_SEL1 0x0300
-#define VAL_IOPORT1_IES 0x0000
-#define VAL_IOPORT1_IE 0x0000
-
-/*
- * Port B setup:
- *
- * P3.0 - BoosterPack BP18 (input pullup)
- * P3.1 - N/C (input pullup)
- * P3.2 - N/C (input pullup)
- * P3.3 - N/C (input pullup)
- * P3.4 - BoosterPack BP8 (input pullup)
- * P3.5 - BoosterPack BP9 (input pullup)
- * P3.6 - BoosterPack BP10 (input pullup)
- * P3.7 - N/C (input pullup)
- * P4.0 - Application UART CTS (input pullup)
- * P4.1 - Application UART RTS (output high)
- * P4.2 - BoosterPack BP2 (input pullup)
- * P4.3 - BoosterPack BP5 (input pullup)
- * P4.4 - N/C (input pullup)
- * P4.5 - Switch S1 (input pullup)
- * P4.6 - Red LED (output low)
- * P4.7 - N/C (input pullup)
- */
-#define VAL_IOPORT2_OUT 0xBFFF
-#define VAL_IOPORT2_DIR 0x4200
-#define VAL_IOPORT2_REN 0xBDFF
-#define VAL_IOPORT2_SEL0 0x0000
-#define VAL_IOPORT2_SEL1 0x0000
-#define VAL_IOPORT2_IES 0x0000
-#define VAL_IOPORT2_IE 0x0000
-
-/*
- * Port J setup:
- *
- * PJ.0 - TDO (input pullup)
- * PJ.1 - TDI (input pullup)
- * PJ.2 - TMS (input pullup)
- * PJ.3 - TCK (input pullup)
- * PJ.4 - LFXIN (alternate 1)
- * PJ.5 - LFXOUT (alternate 1)
- * PJ.6 - HFXIN (N/C) (input pullup)
- * PJ.7 - HFXOUT (N/C) (input pullup)
- */
-#define VAL_IOPORT0_OUT 0x00FF
-#define VAL_IOPORT0_DIR 0x0000
-#define VAL_IOPORT0_REN 0x00CF
-#define VAL_IOPORT0_SEL0 0x0030
-#define VAL_IOPORT0_SEL1 0x0000
-#define VAL_IOPORT0_IES 0x0000
-#define VAL_IOPORT0_IE 0x0000
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR5969/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR5969/board.mk deleted file mode 100644 index c629257..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR5969/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files.
-BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/EXP430FR5969/board.c
-
-# Required include directories
-BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/EXP430FR5969
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR6989/board.c b/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR6989/board.c deleted file mode 100644 index a6836cf..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR6989/board.c +++ /dev/null @@ -1,52 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#include "hal.h"
-
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-const PALConfig pal_default_config =
-{
- {VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0,
- VAL_IOPORT1_SEL1, VAL_IOPORT1_IES, VAL_IOPORT1_IE},
- {VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0,
- VAL_IOPORT2_SEL1, VAL_IOPORT2_IES, VAL_IOPORT2_IE},
- {VAL_IOPORT3_OUT, VAL_IOPORT3_DIR, VAL_IOPORT3_REN, VAL_IOPORT3_SEL0,
- VAL_IOPORT3_SEL1, VAL_IOPORT3_IES, VAL_IOPORT3_IE},
- {VAL_IOPORT4_OUT, VAL_IOPORT4_DIR, VAL_IOPORT4_REN, VAL_IOPORT4_SEL0,
- VAL_IOPORT4_SEL1, VAL_IOPORT4_IES, VAL_IOPORT4_IE},
- {VAL_IOPORT5_OUT, VAL_IOPORT5_DIR, VAL_IOPORT5_REN, VAL_IOPORT5_SEL0,
- VAL_IOPORT5_SEL1, VAL_IOPORT5_IES, VAL_IOPORT5_IE},
- {VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0,
- VAL_IOPORT0_SEL1, VAL_IOPORT0_IES, VAL_IOPORT0_IE}
-}; /* Set UART TX pin correctly */
-#endif /* HAL_USE_PAL */
-
-/**
- * Board-specific initialization code.
- */
-void boardInit(void) {
-
- /*
- * External interrupts setup, all disabled initially.
- */
- _disable_interrupts();
-
-}
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR6989/board.h b/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR6989/board.h deleted file mode 100644 index 83b8fbb..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR6989/board.h +++ /dev/null @@ -1,217 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for the EXP430FR6989 LaunchPad board
- */
-
-/* NOTE: LCD segment pins configured as unused - controlled by LCD driver if
- * present
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_EXP430FR6989
-#define BOARD_NAME "MSP430FR6989 LaunchPad"
-
-/*
- * IO lines assignments.
- */
-#define LINE_LED_R PAL_LINE(IOPORT1, 0U)
-#define LINE_LED_G PAL_LINE(IOPORT5, 7U)
-#define LINE_SW_S1 PAL_LINE(IOPORT1, 1U)
-#define LINE_SW_S2 PAL_LINE(IOPORT1, 2U)
-
-/*
- * I/O ports initial setup, this configuration is established soon after reset
- * in the initialization code.
- * Please refer to the MSP430X Family Users Guide for details.
- */
-/*
- * Port A setup:
- *
- * P1.0 - Red LED (output low)
- * P1.1 - Switch S1 (input pullup falling-edge interrupt)
- * P1.2 - Switch S2 (input pullup falling-edge interrupt)
- * P1.3 - BoosterPack BP34 (input pullup)
- * P1.4 - BoosterPack BP7 (input pullup)
- * P1.5 - BoosterPack BP18 (input pullup)
- * P1.6 - BoosterPack BP15 (input pullup)
- * P1.7 - BoosterPack BP14 (input pullup)
- * P2.0 - BoosterPack BP8 (input pullup)
- * P2.1 - BoosterPack BP19 (input pullup)
- * P2.2 - BoosterPack BP35 (input pullup)
- * P2.3 - BoosterPack BP31 (input pullup)
- * P2.4 - BoosterPack BP12 (input pullup)
- * P2.5 - BoosterPack BP13 (input pullup)
- * P2.6 - BoosterPack BP39 (input pullup)
- * P2.7 - BoosterPack BP40 (input pullup)
- */
-#define VAL_IOPORT1_OUT 0xFFFE
-#define VAL_IOPORT1_DIR 0x0001
-#define VAL_IOPORT1_REN 0xFFFE
-#define VAL_IOPORT1_SEL0 0x0000
-#define VAL_IOPORT1_SEL1 0x0000
-#define VAL_IOPORT1_IES 0x0006
-#define VAL_IOPORT1_IE 0x0006
-
-/*
- * Port B setup:
- *
- * P3.0 - BoosterPack BP33 (input pullup)
- * P3.1 - BoosterPack BP32 (input pullup)
- * P3.2 - BoosterPack BP5 (input pullup)
- * P3.3 - BoosterPack BP38 (input pullup)
- * P3.4 - Application UART TX (alternate 1)
- * P3.5 - Application UART RX (alternate 1)
- * P3.6 - BoosterPack BP37 (input pullup)
- * P3.7 - BoosterPack BP36 (input pullup)
- * P4.0 - BoosterPack BP10 (input pullup)
- * P4.1 - BoosterPack BP9 (input pullup)
- * P4.2 - BoosterPack BP4 (input pullup)
- * P4.3 - BoosterPack BP3 (input pullup)
- * P4.4 - LCD S8 (input pullup)
- * P4.5 - LCD S7 (input pullup)
- * P4.6 - LCD S6 (input pullup)
- * P4.7 - BoosterPack BP11 (input pullup)
- */
-#define VAL_IOPORT2_OUT 0xFFCF
-#define VAL_IOPORT2_DIR 0x0000
-#define VAL_IOPORT2_REN 0xFFCF
-#define VAL_IOPORT2_SEL0 0x0030
-#define VAL_IOPORT2_SEL1 0x0000
-#define VAL_IOPORT2_IES 0x0000
-#define VAL_IOPORT2_IE 0x0000
-
-/*
- * Port C setup:
- *
- * P5.0 - LCD S38 (input pullup)
- * P5.1 - LCD S37 (input pullup)
- * P5.2 - LCD S36 (input pullup)
- * P5.3 - LCD S35 (input pullup)
- * P5.4 - LCD S12 (input pullup)
- * P5.5 - LCD S11 (input pullup)
- * P5.6 - LCD S10 (input pullup)
- * P5.7 - LCD S9 (input pullup)
- * P6.0 - LCD R23 (input pullup)
- * P6.1 - LCD R13 (input pullup)
- * P6.2 - LCD R03 (input pullup)
- * P6.3 - LCD COM0 (input pullup)
- * P6.4 - LCD COM1 (input pullup)
- * P6.5 - LCD COM2 (input pullup)
- * P6.6 - LCD COM3 (input pullup)
- * P6.7 - LCD S31 (input pullup)
- */
-#define VAL_IOPORT3_OUT 0xFFFF
-#define VAL_IOPORT3_DIR 0x0000
-#define VAL_IOPORT3_REN 0xFFFF
-#define VAL_IOPORT3_SEL0 0x0000
-#define VAL_IOPORT3_SEL1 0x0000
-#define VAL_IOPORT3_IES 0x0000
-#define VAL_IOPORT3_IE 0x0000
-
-/*
- * Port D setup:
- *
- * P7.0 - LCD S17 (input pullup)
- * P7.1 - LCD S16 (input pullup)
- * P7.2 - LCD S15 (input pullup)
- * P7.3 - LCD S14 (input pullup)
- * P7.4 - LCD S13 (input pullup)
- * P7.5 - LCD S30 (input pullup)
- * P7.6 - LCD S29 (input pullup)
- * P7.7 - LCD S27 (input pullup)
- * P8.0 - LCD S21 (input pullup)
- * P8.1 - LCD S20 (input pullup)
- * P8.2 - LCD S19 (input pullup)
- * P8.3 - LCD S18 (input pullup)
- * P8.4 - BoosterPack BP23 (input pullup)
- * P8.5 - BoosterPack BP24 (input pullup)
- * P8.6 - BoosterPack BP25 (input pullup)
- * P8.7 - BoosterPack BP26 (input pullup)
- */
-#define VAL_IOPORT4_OUT 0xFFFF
-#define VAL_IOPORT4_DIR 0x0000
-#define VAL_IOPORT4_REN 0xFFFF
-#define VAL_IOPORT4_SEL0 0x0000
-#define VAL_IOPORT4_SEL1 0x0000
-#define VAL_IOPORT4_IES 0x0000
-#define VAL_IOPORT4_IE 0x0000
-
-/*
- * Port D setup:
- *
- * P9.0 - BoosterPack BP27 (input pullup)
- * P9.1 - BoosterPack BP28 (input pullup)
- * P9.2 - BoosterPack BP2 (input pullup)
- * P9.3 - BoosterPack BP6 (input pullup)
- * P9.4 - BoosterPack BP17 (input pullup)
- * P9.5 - BoosterPack BP29 (input pullup)
- * P9.6 - BoosterPack BP30 (input pullup)
- * P9.7 - Green LED (output low)
- * P10.0 - LCD S4 (input pullup)
- * P10.1 - LCD S28 (input pullup)
- * P10.2 - LCD S39 (input pullup)
- * P10.3 - N/C Internally (input pullup)
- * P10.4 - N/C Internally (input pullup)
- * P10.5 - N/C Internally (input pullup)
- * P10.6 - N/C Internally (input pullup)
- * P10.7 - N/C Internally (input pullup)
- */
-#define VAL_IOPORT5_OUT 0xFF7F
-#define VAL_IOPORT5_DIR 0x0080
-#define VAL_IOPORT5_REN 0xFF7F
-#define VAL_IOPORT5_SEL0 0x0000
-#define VAL_IOPORT5_SEL1 0x0000
-#define VAL_IOPORT5_IES 0x0000
-#define VAL_IOPORT5_IE 0x0000
-
-/*
- * Port J setup:
- *
- * PJ.0 - TDO (input pullup)
- * PJ.1 - TDI (input pullup)
- * PJ.2 - TMS (input pullup)
- * PJ.3 - TCK (input pullup)
- * PJ.4 - LFXIN (alternate 1)
- * PJ.5 - LFXOUT (alternate 1)
- * PJ.6 - HFXIN (N/C) (input pullup)
- * PJ.7 - HFXOUT (N/C) (input pullup)
- */
-#define VAL_IOPORT0_OUT 0x00FF
-#define VAL_IOPORT0_DIR 0x0000
-#define VAL_IOPORT0_REN 0x00CF
-#define VAL_IOPORT0_SEL0 0x0030
-#define VAL_IOPORT0_SEL1 0x0000
-#define VAL_IOPORT0_IES 0x0000
-#define VAL_IOPORT0_IE 0x0000
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR6989/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR6989/board.mk deleted file mode 100644 index ea1c237..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/EXP430FR6989/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files.
-BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/EXP430FR6989/board.c
-
-# Required include directories
-BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/EXP430FR6989
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c b/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c deleted file mode 100644 index ee86d96..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c +++ /dev/null @@ -1,127 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-const PALConfig pal_default_config =
-{
- .ports = {
- {
- .port = IOPORT1, // PORTA
- .pads = {
- /* PTA0*/ PAL_MODE_ALTERNATIVE_7, /* PTA1*/ PAL_MODE_UNCONNECTED, /* PTA2*/ PAL_MODE_OUTPUT_PUSHPULL,
- /* PTA3*/ PAL_MODE_ALTERNATIVE_7, /* PTA4*/ PAL_MODE_UNCONNECTED, /* PTA5*/ PAL_MODE_UNCONNECTED,
- /* PTA6*/ PAL_MODE_UNCONNECTED, /* PTA7*/ PAL_MODE_UNCONNECTED, /* PTA8*/ PAL_MODE_UNCONNECTED,
- /* PTA9*/ PAL_MODE_UNCONNECTED, /*PTA10*/ PAL_MODE_UNCONNECTED, /*PTA11*/ PAL_MODE_UNCONNECTED,
- /*PTA12*/ PAL_MODE_UNCONNECTED, /*PTA13*/ PAL_MODE_UNCONNECTED, /*PTA14*/ PAL_MODE_UNCONNECTED,
- /*PTA15*/ PAL_MODE_UNCONNECTED, /*PTA16*/ PAL_MODE_UNCONNECTED, /*PTA17*/ PAL_MODE_UNCONNECTED,
- /*PTA18*/ PAL_MODE_INPUT_ANALOG, /*PTA19*/ PAL_MODE_INPUT_ANALOG, /*PTA20*/ PAL_MODE_UNCONNECTED,
- /*PTA21*/ PAL_MODE_UNCONNECTED, /*PTA22*/ PAL_MODE_UNCONNECTED, /*PTA23*/ PAL_MODE_UNCONNECTED,
- /*PTA24*/ PAL_MODE_UNCONNECTED, /*PTA25*/ PAL_MODE_UNCONNECTED, /*PTA26*/ PAL_MODE_UNCONNECTED,
- /*PTA27*/ PAL_MODE_UNCONNECTED, /*PTA28*/ PAL_MODE_UNCONNECTED, /*PTA29*/ PAL_MODE_UNCONNECTED,
- /*PTA30*/ PAL_MODE_UNCONNECTED, /*PTA31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT2, // PORTB
- .pads = {
- /* PTB0*/ PAL_MODE_ALTERNATIVE_2, /* PTB1*/ PAL_MODE_ALTERNATIVE_2, /* PTB2*/ PAL_MODE_UNCONNECTED,
- /* PTB3*/ PAL_MODE_UNCONNECTED, /* PTB4*/ PAL_MODE_UNCONNECTED, /* PTB5*/ PAL_MODE_UNCONNECTED,
- /* PTB6*/ PAL_MODE_UNCONNECTED, /* PTB7*/ PAL_MODE_UNCONNECTED, /* PTB8*/ PAL_MODE_UNCONNECTED,
- /* PTB9*/ PAL_MODE_UNCONNECTED, /*PTB10*/ PAL_MODE_UNCONNECTED, /*PTB11*/ PAL_MODE_UNCONNECTED,
- /*PTB12*/ PAL_MODE_UNCONNECTED, /*PTB13*/ PAL_MODE_UNCONNECTED, /*PTB14*/ PAL_MODE_UNCONNECTED,
- /*PTB15*/ PAL_MODE_UNCONNECTED, /*PTB16*/ PAL_MODE_ALTERNATIVE_3, /*PTB17*/ PAL_MODE_ALTERNATIVE_3,
- /*PTB18*/ PAL_MODE_UNCONNECTED, /*PTB19*/ PAL_MODE_UNCONNECTED, /*PTB20*/ PAL_MODE_UNCONNECTED,
- /*PTB21*/ PAL_MODE_UNCONNECTED, /*PTB22*/ PAL_MODE_UNCONNECTED, /*PTB23*/ PAL_MODE_UNCONNECTED,
- /*PTB24*/ PAL_MODE_UNCONNECTED, /*PTB25*/ PAL_MODE_UNCONNECTED, /*PTB26*/ PAL_MODE_UNCONNECTED,
- /*PTB27*/ PAL_MODE_UNCONNECTED, /*PTB28*/ PAL_MODE_UNCONNECTED, /*PTB29*/ PAL_MODE_UNCONNECTED,
- /*PTB30*/ PAL_MODE_UNCONNECTED, /*PTB31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT3, // PORTC
- .pads = {
- /* PTC0*/ PAL_MODE_UNCONNECTED, /* PTC1*/ PAL_MODE_UNCONNECTED, /* PTC2*/ PAL_MODE_UNCONNECTED,
- /* PTC3*/ PAL_MODE_OUTPUT_PUSHPULL, /* PTC4*/ PAL_MODE_UNCONNECTED, /* PTC5*/ PAL_MODE_UNCONNECTED,
- /* PTC6*/ PAL_MODE_UNCONNECTED, /* PTC7*/ PAL_MODE_UNCONNECTED, /* PTC8*/ PAL_MODE_UNCONNECTED,
- /* PTC9*/ PAL_MODE_UNCONNECTED, /*PTC10*/ PAL_MODE_UNCONNECTED, /*PTC11*/ PAL_MODE_UNCONNECTED,
- /*PTC12*/ PAL_MODE_UNCONNECTED, /*PTC13*/ PAL_MODE_UNCONNECTED, /*PTC14*/ PAL_MODE_UNCONNECTED,
- /*PTC15*/ PAL_MODE_UNCONNECTED, /*PTC16*/ PAL_MODE_UNCONNECTED, /*PTC17*/ PAL_MODE_UNCONNECTED,
- /*PTC18*/ PAL_MODE_UNCONNECTED, /*PTC19*/ PAL_MODE_UNCONNECTED, /*PTC20*/ PAL_MODE_UNCONNECTED,
- /*PTC21*/ PAL_MODE_UNCONNECTED, /*PTC22*/ PAL_MODE_UNCONNECTED, /*PTC23*/ PAL_MODE_UNCONNECTED,
- /*PTC24*/ PAL_MODE_UNCONNECTED, /*PTC25*/ PAL_MODE_UNCONNECTED, /*PTC26*/ PAL_MODE_UNCONNECTED,
- /*PTC27*/ PAL_MODE_UNCONNECTED, /*PTC28*/ PAL_MODE_UNCONNECTED, /*PTC29*/ PAL_MODE_UNCONNECTED,
- /*PTC30*/ PAL_MODE_UNCONNECTED, /*PTC31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT4, // PORTD
- .pads = {
- /* PTD0*/ PAL_MODE_UNCONNECTED, /* PTD1*/ PAL_MODE_UNCONNECTED, /* PTD2*/ PAL_MODE_UNCONNECTED,
- /* PTD3*/ PAL_MODE_UNCONNECTED, /* PTD4*/ PAL_MODE_OUTPUT_PUSHPULL, /* PTD5*/ PAL_MODE_UNCONNECTED,
- /* PTD6*/ PAL_MODE_UNCONNECTED, /* PTD7*/ PAL_MODE_UNCONNECTED, /* PTD8*/ PAL_MODE_UNCONNECTED,
- /* PTD9*/ PAL_MODE_UNCONNECTED, /*PTD10*/ PAL_MODE_UNCONNECTED, /*PTD11*/ PAL_MODE_UNCONNECTED,
- /*PTD12*/ PAL_MODE_UNCONNECTED, /*PTD13*/ PAL_MODE_UNCONNECTED, /*PTD14*/ PAL_MODE_UNCONNECTED,
- /*PTD15*/ PAL_MODE_UNCONNECTED, /*PTD16*/ PAL_MODE_UNCONNECTED, /*PTD17*/ PAL_MODE_UNCONNECTED,
- /*PTD18*/ PAL_MODE_UNCONNECTED, /*PTD19*/ PAL_MODE_UNCONNECTED, /*PTD20*/ PAL_MODE_UNCONNECTED,
- /*PTD21*/ PAL_MODE_UNCONNECTED, /*PTD22*/ PAL_MODE_UNCONNECTED, /*PTD23*/ PAL_MODE_UNCONNECTED,
- /*PTD24*/ PAL_MODE_UNCONNECTED, /*PTD25*/ PAL_MODE_UNCONNECTED, /*PTD26*/ PAL_MODE_UNCONNECTED,
- /*PTD27*/ PAL_MODE_UNCONNECTED, /*PTD28*/ PAL_MODE_UNCONNECTED, /*PTD29*/ PAL_MODE_UNCONNECTED,
- /*PTD30*/ PAL_MODE_UNCONNECTED, /*PTD31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT5, // PORTE
- .pads = {
- /* PTE0*/ PAL_MODE_UNCONNECTED, /* PTE1*/ PAL_MODE_UNCONNECTED, /* PTE2*/ PAL_MODE_UNCONNECTED,
- /* PTE3*/ PAL_MODE_UNCONNECTED, /* PTE4*/ PAL_MODE_UNCONNECTED, /* PTE5*/ PAL_MODE_UNCONNECTED,
- /* PTE6*/ PAL_MODE_UNCONNECTED, /* PTE7*/ PAL_MODE_UNCONNECTED, /* PTE8*/ PAL_MODE_UNCONNECTED,
- /* PTE9*/ PAL_MODE_UNCONNECTED, /*PTE10*/ PAL_MODE_UNCONNECTED, /*PTE11*/ PAL_MODE_UNCONNECTED,
- /*PTE12*/ PAL_MODE_UNCONNECTED, /*PTE13*/ PAL_MODE_UNCONNECTED, /*PTE14*/ PAL_MODE_UNCONNECTED,
- /*PTE15*/ PAL_MODE_UNCONNECTED, /*PTE16*/ PAL_MODE_UNCONNECTED, /*PTE17*/ PAL_MODE_UNCONNECTED,
- /*PTE18*/ PAL_MODE_UNCONNECTED, /*PTE19*/ PAL_MODE_UNCONNECTED, /*PTE20*/ PAL_MODE_UNCONNECTED,
- /*PTE21*/ PAL_MODE_UNCONNECTED, /*PTE22*/ PAL_MODE_UNCONNECTED, /*PTE23*/ PAL_MODE_UNCONNECTED,
- /*PTE24*/ PAL_MODE_UNCONNECTED, /*PTE25*/ PAL_MODE_UNCONNECTED, /*PTE26*/ PAL_MODE_UNCONNECTED,
- /*PTE27*/ PAL_MODE_UNCONNECTED, /*PTE28*/ PAL_MODE_UNCONNECTED, /*PTE29*/ PAL_MODE_UNCONNECTED,
- /*PTE30*/ PAL_MODE_UNCONNECTED, /*PTE31*/ PAL_MODE_UNCONNECTED,
- },
- },
- },
-};
-#endif
-
-/**
- * @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
- */
-void __early_init(void) {
-
- k20x_clock_init();
-}
-
-/**
- * @brief Board-specific initialization code.
- * @todo Add your board-specific code, if any.
- */
-void boardInit(void) {
-}
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h b/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h deleted file mode 100644 index 8f8605c..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h +++ /dev/null @@ -1,70 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for Freescale Freedom K20D50M board.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_FREESCALE_FREEDOM_K20D50M
-#define BOARD_NAME "Freescale Freedom K20D50M"
-
-/* External 8 MHz crystal. */
-#define KINETIS_XTAL_FREQUENCY 8000000UL
-
-/*
- * MCU type
- */
-#define K20x5
-
-/*
- * Onboard features.
- */
-#define GPIO_LED_RED IOPORT3
-#define PIN_LED_RED 3
-#define GPIO_LED_GREEN IOPORT4
-#define PIN_LED_GREEN 4
-#define GPIO_LED_BLUE IOPORT1
-#define PIN_LED_BLUE 2
-
-/* Inertial sensor: MMA8451Q */
-/* Default I2C address 0x1D */
-#define I2C_GYRO I2C0
-
-#define LINE_LED_RED PAL_LINE(GPIO_LED_RED, PIN_LED_RED)
-#define LINE_LED_GREEN PAL_LINE(GPIO_LED_GREEN, PIN_LED_GREEN)
-#define LINE_LED_BLUE PAL_LINE(GPIO_LED_BLUE, PIN_LED_BLUE)
-#define LINE_GYRO_SCL PAL_LINE(GPIOB, 0U)
-#define LINE_GYRO_SDA PAL_LINE(GPIOB, 1U)
-#define LINE_GYRO_INT1 PAL_LINE(GPIOC, 11U)
-#define LINE_GYRO_INT2 PAL_LINE(GPIOC, 6U)
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk deleted file mode 100644 index f74d306..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files.
-BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c
-
-# Required include directories
-BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_K20D50M
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c b/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c deleted file mode 100644 index f5bd3ac..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c +++ /dev/null @@ -1,127 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-const PALConfig pal_default_config =
-{
- .ports = {
- {
- .port = IOPORT1, // PORTA
- .pads = {
- /* PTA0*/ PAL_MODE_ALTERNATIVE_7, /* PTA1*/ PAL_MODE_ALTERNATIVE_2, /* PTA2*/ PAL_MODE_ALTERNATIVE_2,
- /* PTA3*/ PAL_MODE_ALTERNATIVE_7, /* PTA4*/ PAL_MODE_INPUT_ANALOG, /* PTA5*/ PAL_MODE_INPUT_ANALOG,
- /* PTA6*/ PAL_MODE_UNCONNECTED, /* PTA7*/ PAL_MODE_UNCONNECTED, /* PTA8*/ PAL_MODE_UNCONNECTED,
- /* PTA9*/ PAL_MODE_UNCONNECTED, /*PTA10*/ PAL_MODE_UNCONNECTED, /*PTA11*/ PAL_MODE_UNCONNECTED,
- /*PTA12*/ PAL_MODE_INPUT_ANALOG, /*PTA13*/ PAL_MODE_INPUT_ANALOG, /*PTA14*/ PAL_MODE_INPUT_ANALOG,
- /*PTA15*/ PAL_MODE_INPUT_ANALOG, /*PTA16*/ PAL_MODE_INPUT_ANALOG, /*PTA17*/ PAL_MODE_INPUT_ANALOG,
- /*PTA18*/ PAL_MODE_INPUT_ANALOG, /*PTA19*/ PAL_MODE_INPUT_ANALOG, /*PTA20*/ PAL_MODE_ALTERNATIVE_7,
- /*PTA21*/ PAL_MODE_UNCONNECTED, /*PTA22*/ PAL_MODE_UNCONNECTED, /*PTA23*/ PAL_MODE_UNCONNECTED,
- /*PTA24*/ PAL_MODE_UNCONNECTED, /*PTA25*/ PAL_MODE_UNCONNECTED, /*PTA26*/ PAL_MODE_UNCONNECTED,
- /*PTA27*/ PAL_MODE_UNCONNECTED, /*PTA28*/ PAL_MODE_UNCONNECTED, /*PTA29*/ PAL_MODE_UNCONNECTED,
- /*PTA30*/ PAL_MODE_UNCONNECTED, /*PTA31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT2, // PORTB
- .pads = {
- /* PTB0*/ PAL_MODE_INPUT_ANALOG, /* PTB1*/ PAL_MODE_INPUT_ANALOG, /* PTB2*/ PAL_MODE_INPUT_ANALOG,
- /* PTB3*/ PAL_MODE_INPUT_ANALOG, /* PTB4*/ PAL_MODE_UNCONNECTED, /* PTB5*/ PAL_MODE_UNCONNECTED,
- /* PTB6*/ PAL_MODE_UNCONNECTED, /* PTB7*/ PAL_MODE_UNCONNECTED, /* PTB8*/ PAL_MODE_INPUT_ANALOG,
- /* PTB9*/ PAL_MODE_INPUT_ANALOG, /*PTB10*/ PAL_MODE_INPUT_ANALOG, /*PTB11*/ PAL_MODE_INPUT_ANALOG,
- /*PTB12*/ PAL_MODE_UNCONNECTED, /*PTB13*/ PAL_MODE_UNCONNECTED, /*PTB14*/ PAL_MODE_UNCONNECTED,
- /*PTB15*/ PAL_MODE_UNCONNECTED, /*PTB16*/ PAL_MODE_INPUT_ANALOG, /*PTB17*/ PAL_MODE_INPUT_ANALOG,
- /*PTB18*/ PAL_MODE_OUTPUT_PUSHPULL, /*PTB19*/ PAL_MODE_OUTPUT_PUSHPULL, /*PTB20*/ PAL_MODE_UNCONNECTED,
- /*PTB21*/ PAL_MODE_UNCONNECTED, /*PTB22*/ PAL_MODE_UNCONNECTED, /*PTB23*/ PAL_MODE_UNCONNECTED,
- /*PTB24*/ PAL_MODE_UNCONNECTED, /*PTB25*/ PAL_MODE_UNCONNECTED, /*PTB26*/ PAL_MODE_UNCONNECTED,
- /*PTB27*/ PAL_MODE_UNCONNECTED, /*PTB28*/ PAL_MODE_UNCONNECTED, /*PTB29*/ PAL_MODE_UNCONNECTED,
- /*PTB30*/ PAL_MODE_UNCONNECTED, /*PTB31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT3, // PORTC
- .pads = {
- /* PTC0*/ PAL_MODE_INPUT_ANALOG, /* PTC1*/ PAL_MODE_INPUT_ANALOG, /* PTC2*/ PAL_MODE_INPUT_ANALOG,
- /* PTC3*/ PAL_MODE_INPUT_ANALOG, /* PTC4*/ PAL_MODE_INPUT_ANALOG, /* PTC5*/ PAL_MODE_INPUT_ANALOG,
- /* PTC6*/ PAL_MODE_INPUT_ANALOG, /* PTC7*/ PAL_MODE_INPUT_ANALOG, /* PTC8*/ PAL_MODE_INPUT_ANALOG,
- /* PTC9*/ PAL_MODE_INPUT_ANALOG, /*PTC10*/ PAL_MODE_INPUT_ANALOG, /*PTC11*/ PAL_MODE_INPUT_ANALOG,
- /*PTC12*/ PAL_MODE_INPUT_ANALOG, /*PTC13*/ PAL_MODE_INPUT_ANALOG, /*PTC14*/ PAL_MODE_INPUT_ANALOG,
- /*PTC15*/ PAL_MODE_INPUT_ANALOG, /*PTC16*/ PAL_MODE_INPUT_ANALOG, /*PTC17*/ PAL_MODE_INPUT_ANALOG,
- /*PTC18*/ PAL_MODE_UNCONNECTED, /*PTC19*/ PAL_MODE_UNCONNECTED, /*PTC20*/ PAL_MODE_UNCONNECTED,
- /*PTC21*/ PAL_MODE_UNCONNECTED, /*PTC22*/ PAL_MODE_UNCONNECTED, /*PTC23*/ PAL_MODE_UNCONNECTED,
- /*PTC24*/ PAL_MODE_UNCONNECTED, /*PTC25*/ PAL_MODE_UNCONNECTED, /*PTC26*/ PAL_MODE_UNCONNECTED,
- /*PTC27*/ PAL_MODE_UNCONNECTED, /*PTC28*/ PAL_MODE_UNCONNECTED, /*PTC29*/ PAL_MODE_UNCONNECTED,
- /*PTC30*/ PAL_MODE_UNCONNECTED, /*PTC31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT4, // PORTD
- .pads = {
- /* PTD0*/ PAL_MODE_INPUT_ANALOG, /* PTD1*/ PAL_MODE_OUTPUT_PUSHPULL, /* PTD2*/ PAL_MODE_INPUT_ANALOG,
- /* PTD3*/ PAL_MODE_INPUT_ANALOG, /* PTD4*/ PAL_MODE_INPUT_ANALOG, /* PTD5*/ PAL_MODE_INPUT_ANALOG,
- /* PTD6*/ PAL_MODE_INPUT_ANALOG, /* PTD7*/ PAL_MODE_INPUT_ANALOG, /* PTD8*/ PAL_MODE_INPUT_ANALOG,
- /* PTD9*/ PAL_MODE_UNCONNECTED, /*PTD10*/ PAL_MODE_UNCONNECTED, /*PTD11*/ PAL_MODE_UNCONNECTED,
- /*PTD12*/ PAL_MODE_UNCONNECTED, /*PTD13*/ PAL_MODE_UNCONNECTED, /*PTD14*/ PAL_MODE_UNCONNECTED,
- /*PTD15*/ PAL_MODE_UNCONNECTED, /*PTD16*/ PAL_MODE_UNCONNECTED, /*PTD17*/ PAL_MODE_UNCONNECTED,
- /*PTD18*/ PAL_MODE_UNCONNECTED, /*PTD19*/ PAL_MODE_UNCONNECTED, /*PTD20*/ PAL_MODE_UNCONNECTED,
- /*PTD21*/ PAL_MODE_UNCONNECTED, /*PTD22*/ PAL_MODE_UNCONNECTED, /*PTD23*/ PAL_MODE_UNCONNECTED,
- /*PTD24*/ PAL_MODE_UNCONNECTED, /*PTD25*/ PAL_MODE_UNCONNECTED, /*PTD26*/ PAL_MODE_UNCONNECTED,
- /*PTD27*/ PAL_MODE_UNCONNECTED, /*PTD28*/ PAL_MODE_UNCONNECTED, /*PTD29*/ PAL_MODE_UNCONNECTED,
- /*PTD30*/ PAL_MODE_UNCONNECTED, /*PTD31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT5, // PORTE
- .pads = {
- /* PTE0*/ PAL_MODE_INPUT_ANALOG, /* PTE1*/ PAL_MODE_INPUT_ANALOG, /* PTE2*/ PAL_MODE_INPUT_ANALOG,
- /* PTE3*/ PAL_MODE_INPUT_ANALOG, /* PTE4*/ PAL_MODE_INPUT_ANALOG, /* PTE5*/ PAL_MODE_INPUT_ANALOG,
- /* PTE6*/ PAL_MODE_UNCONNECTED, /* PTE7*/ PAL_MODE_UNCONNECTED, /* PTE8*/ PAL_MODE_UNCONNECTED,
- /* PTE9*/ PAL_MODE_UNCONNECTED, /*PTE10*/ PAL_MODE_UNCONNECTED, /*PTE11*/ PAL_MODE_UNCONNECTED,
- /*PTE12*/ PAL_MODE_UNCONNECTED, /*PTE13*/ PAL_MODE_UNCONNECTED, /*PTE14*/ PAL_MODE_UNCONNECTED,
- /*PTE15*/ PAL_MODE_UNCONNECTED, /*PTE16*/ PAL_MODE_UNCONNECTED, /*PTE17*/ PAL_MODE_UNCONNECTED,
- /*PTE18*/ PAL_MODE_UNCONNECTED, /*PTE19*/ PAL_MODE_UNCONNECTED, /*PTE20*/ PAL_MODE_INPUT_ANALOG,
- /*PTE21*/ PAL_MODE_INPUT_ANALOG, /*PTE22*/ PAL_MODE_INPUT_ANALOG, /*PTE23*/ PAL_MODE_INPUT_ANALOG,
- /*PTE24*/ PAL_MODE_ALTERNATIVE_5, /*PTE25*/ PAL_MODE_ALTERNATIVE_5, /*PTE26*/ PAL_MODE_UNCONNECTED,
- /*PTE27*/ PAL_MODE_UNCONNECTED, /*PTE28*/ PAL_MODE_UNCONNECTED, /*PTE29*/ PAL_MODE_INPUT_ANALOG,
- /*PTE30*/ PAL_MODE_INPUT_ANALOG, /*PTE31*/ PAL_MODE_INPUT_ANALOG,
- },
- },
- },
-};
-#endif
-
-/**
- * @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
- */
-void __early_init(void) {
-
- kl2x_clock_init();
-}
-
-/**
- * @brief Board-specific initialization code.
- * @todo Add your board-specific code, if any.
- */
-void boardInit(void) {
-}
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h b/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h deleted file mode 100644 index 289ee91..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h +++ /dev/null @@ -1,79 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for Freescale Freedom KL25Z board.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_FREESCALE_FREEDOM_KL25Z
-#define BOARD_NAME "Freescale Freedom KL25Z"
-
-/* External 8 MHz crystal. */
-#define KINETIS_XTAL_FREQUENCY 8000000UL
-
-/*
- * MCU type
- */
-#define KL25
-
-/*
- * Onboard features.
- */
-#define GPIO_LED_RED IOPORT2
-#define PIN_LED_RED 18
-#define GPIO_LED_GREEN IOPORT2
-#define PIN_LED_GREEN 19
-#define GPIO_LED_BLUE IOPORT4
-#define PIN_LED_BLUE 1
-
-/* Inertial sensor: MMA8451Q */
-/* Default I2C address 0x1D */
-/* Note: the pins PTE24/25 are assigned to I2C0 by default;
- * if I2C0 is wanted on other pins, these need to be
- * assigned another function explicitly!
- */
-#define I2C_GYRO I2C0
-
-#define LINE_LED_RED PAL_LINE(GPIO_LED_RED, PIN_LED_RED)
-#define LINE_LED_GREEN PAL_LINE(GPIO_LED_GREEN, PIN_LED_GREEN)
-#define LINE_LED_BLUE PAL_LINE(GPIO_LED_BLUE, PIN_LED_BLUE)
-#define LINE_GYRO_SCL PAL_LINE(GPIOE, 24U)
-#define LINE_GYRO_SDA PAL_LINE(GPIOE, 25U)
-#define LINE_GYRO_INT1 PAL_LINE(GPIOA, 14U)
-#define LINE_GYRO_INT2 PAL_LINE(GPIOA, 15U)
-
-/*
- * Not configured:
- * - TSI Slider on PTB16/TSI0_CH9 and PTB17/TSI_CH10
- */
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk deleted file mode 100644 index 3097a90..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files.
-BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c
-
-# Required include directories
-BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL25Z
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.c b/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.c deleted file mode 100644 index 7c68f66..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.c +++ /dev/null @@ -1,127 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 flabbergast <s3+flabbergast@sdfeu.org>
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-const PALConfig pal_default_config =
-{
- .ports = {
- {
- .port = IOPORT1, // PORTA
- .pads = {
- /* PTA0*/ PAL_MODE_ALTERNATIVE_7, /* PTA1*/ PAL_MODE_ALTERNATIVE_2, /* PTA2*/ PAL_MODE_ALTERNATIVE_2,
- /* PTA3*/ PAL_MODE_ALTERNATIVE_7, /* PTA4*/ PAL_MODE_INPUT_ANALOG, /* PTA5*/ PAL_MODE_INPUT_ANALOG,
- /* PTA6*/ PAL_MODE_UNCONNECTED, /* PTA7*/ PAL_MODE_UNCONNECTED, /* PTA8*/ PAL_MODE_UNCONNECTED,
- /* PTA9*/ PAL_MODE_UNCONNECTED, /*PTA10*/ PAL_MODE_UNCONNECTED, /*PTA11*/ PAL_MODE_UNCONNECTED,
- /*PTA12*/ PAL_MODE_INPUT_ANALOG, /*PTA13*/ PAL_MODE_INPUT_ANALOG, /*PTA14*/ PAL_MODE_UNCONNECTED,
- /*PTA15*/ PAL_MODE_UNCONNECTED, /*PTA16*/ PAL_MODE_UNCONNECTED, /*PTA17*/ PAL_MODE_UNCONNECTED,
- /*PTA18*/ PAL_MODE_INPUT_ANALOG, /*PTA19*/ PAL_MODE_INPUT_ANALOG, /*PTA20*/ PAL_MODE_ALTERNATIVE_7,
- /*PTA21*/ PAL_MODE_UNCONNECTED, /*PTA22*/ PAL_MODE_UNCONNECTED, /*PTA23*/ PAL_MODE_UNCONNECTED,
- /*PTA24*/ PAL_MODE_UNCONNECTED, /*PTA25*/ PAL_MODE_UNCONNECTED, /*PTA26*/ PAL_MODE_UNCONNECTED,
- /*PTA27*/ PAL_MODE_UNCONNECTED, /*PTA28*/ PAL_MODE_UNCONNECTED, /*PTA29*/ PAL_MODE_UNCONNECTED,
- /*PTA30*/ PAL_MODE_UNCONNECTED, /*PTA31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT2, // PORTB
- .pads = {
- /* PTB0*/ PAL_MODE_INPUT_ANALOG, /* PTB1*/ PAL_MODE_INPUT_ANALOG, /* PTB2*/ PAL_MODE_INPUT_ANALOG,
- /* PTB3*/ PAL_MODE_INPUT_ANALOG, /* PTB4*/ PAL_MODE_UNCONNECTED, /* PTB5*/ PAL_MODE_UNCONNECTED,
- /* PTB6*/ PAL_MODE_UNCONNECTED, /* PTB7*/ PAL_MODE_UNCONNECTED, /* PTB8*/ PAL_MODE_INPUT_ANALOG,
- /* PTB9*/ PAL_MODE_UNCONNECTED, /*PTB10*/ PAL_MODE_UNCONNECTED, /*PTB11*/ PAL_MODE_UNCONNECTED,
- /*PTB12*/ PAL_MODE_UNCONNECTED, /*PTB13*/ PAL_MODE_UNCONNECTED, /*PTB14*/ PAL_MODE_UNCONNECTED,
- /*PTB15*/ PAL_MODE_UNCONNECTED, /*PTB16*/ PAL_MODE_INPUT_ANALOG, /*PTB17*/ PAL_MODE_INPUT_ANALOG,
- /*PTB18*/ PAL_MODE_INPUT_ANALOG, /*PTB19*/ PAL_MODE_INPUT_ANALOG, /*PTB20*/ PAL_MODE_UNCONNECTED,
- /*PTB21*/ PAL_MODE_UNCONNECTED, /*PTB22*/ PAL_MODE_UNCONNECTED, /*PTB23*/ PAL_MODE_UNCONNECTED,
- /*PTB24*/ PAL_MODE_UNCONNECTED, /*PTB25*/ PAL_MODE_UNCONNECTED, /*PTB26*/ PAL_MODE_UNCONNECTED,
- /*PTB27*/ PAL_MODE_UNCONNECTED, /*PTB28*/ PAL_MODE_UNCONNECTED, /*PTB29*/ PAL_MODE_UNCONNECTED,
- /*PTB30*/ PAL_MODE_UNCONNECTED, /*PTB31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT3, // PORTC
- .pads = {
- /* PTC0*/ PAL_MODE_INPUT_ANALOG, /* PTC1*/ PAL_MODE_INPUT_ANALOG, /* PTC2*/ PAL_MODE_INPUT_ANALOG,
- /* PTC3*/ PAL_MODE_INPUT, /* PTC4*/ PAL_MODE_INPUT_ANALOG, /* PTC5*/ PAL_MODE_INPUT_ANALOG,
- /* PTC6*/ PAL_MODE_INPUT_ANALOG, /* PTC7*/ PAL_MODE_INPUT_ANALOG, /* PTC8*/ PAL_MODE_INPUT_ANALOG,
- /* PTC9*/ PAL_MODE_INPUT_ANALOG, /*PTC10*/ PAL_MODE_INPUT_ANALOG, /*PTC11*/ PAL_MODE_INPUT_ANALOG,
- /*PTC12*/ PAL_MODE_UNCONNECTED, /*PTC13*/ PAL_MODE_UNCONNECTED, /*PTC14*/ PAL_MODE_UNCONNECTED,
- /*PTC15*/ PAL_MODE_UNCONNECTED, /*PTC16*/ PAL_MODE_UNCONNECTED, /*PTC17*/ PAL_MODE_UNCONNECTED,
- /*PTC18*/ PAL_MODE_UNCONNECTED, /*PTC19*/ PAL_MODE_UNCONNECTED, /*PTC20*/ PAL_MODE_UNCONNECTED,
- /*PTC21*/ PAL_MODE_UNCONNECTED, /*PTC22*/ PAL_MODE_UNCONNECTED, /*PTC23*/ PAL_MODE_UNCONNECTED,
- /*PTC24*/ PAL_MODE_UNCONNECTED, /*PTC25*/ PAL_MODE_UNCONNECTED, /*PTC26*/ PAL_MODE_UNCONNECTED,
- /*PTC27*/ PAL_MODE_UNCONNECTED, /*PTC28*/ PAL_MODE_UNCONNECTED, /*PTC29*/ PAL_MODE_UNCONNECTED,
- /*PTC30*/ PAL_MODE_UNCONNECTED, /*PTC31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT4, // PORTD
- .pads = {
- /* PTD0*/ PAL_MODE_INPUT_PULLUP, /* PTD1*/ PAL_MODE_INPUT_ANALOG, /* PTD2*/ PAL_MODE_INPUT_ANALOG,
- /* PTD3*/ PAL_MODE_INPUT_ANALOG, /* PTD4*/ PAL_MODE_INPUT_ANALOG, /* PTD5*/ PAL_MODE_OUTPUT_PUSHPULL,
- /* PTD6*/ PAL_MODE_INPUT_ANALOG, /* PTD7*/ PAL_MODE_INPUT_ANALOG, /* PTD8*/ PAL_MODE_UNCONNECTED,
- /* PTD9*/ PAL_MODE_UNCONNECTED, /*PTD10*/ PAL_MODE_UNCONNECTED, /*PTD11*/ PAL_MODE_UNCONNECTED,
- /*PTD12*/ PAL_MODE_UNCONNECTED, /*PTD13*/ PAL_MODE_UNCONNECTED, /*PTD14*/ PAL_MODE_UNCONNECTED,
- /*PTD15*/ PAL_MODE_UNCONNECTED, /*PTD16*/ PAL_MODE_UNCONNECTED, /*PTD17*/ PAL_MODE_UNCONNECTED,
- /*PTD18*/ PAL_MODE_UNCONNECTED, /*PTD19*/ PAL_MODE_UNCONNECTED, /*PTD20*/ PAL_MODE_UNCONNECTED,
- /*PTD21*/ PAL_MODE_UNCONNECTED, /*PTD22*/ PAL_MODE_UNCONNECTED, /*PTD23*/ PAL_MODE_UNCONNECTED,
- /*PTD24*/ PAL_MODE_UNCONNECTED, /*PTD25*/ PAL_MODE_UNCONNECTED, /*PTD26*/ PAL_MODE_UNCONNECTED,
- /*PTD27*/ PAL_MODE_UNCONNECTED, /*PTD28*/ PAL_MODE_UNCONNECTED, /*PTD29*/ PAL_MODE_UNCONNECTED,
- /*PTD30*/ PAL_MODE_UNCONNECTED, /*PTD31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT5, // PORTE
- .pads = {
- /* PTE0*/ PAL_MODE_INPUT_ANALOG, /* PTE1*/ PAL_MODE_INPUT_ANALOG, /* PTE2*/ PAL_MODE_UNCONNECTED,
- /* PTE3*/ PAL_MODE_UNCONNECTED, /* PTE4*/ PAL_MODE_UNCONNECTED, /* PTE5*/ PAL_MODE_UNCONNECTED,
- /* PTE6*/ PAL_MODE_UNCONNECTED, /* PTE7*/ PAL_MODE_UNCONNECTED, /* PTE8*/ PAL_MODE_UNCONNECTED,
- /* PTE9*/ PAL_MODE_UNCONNECTED, /*PTE10*/ PAL_MODE_UNCONNECTED, /*PTE11*/ PAL_MODE_UNCONNECTED,
- /*PTE12*/ PAL_MODE_UNCONNECTED, /*PTE13*/ PAL_MODE_UNCONNECTED, /*PTE14*/ PAL_MODE_UNCONNECTED,
- /*PTE15*/ PAL_MODE_UNCONNECTED, /*PTE16*/ PAL_MODE_UNCONNECTED, /*PTE17*/ PAL_MODE_UNCONNECTED,
- /*PTE18*/ PAL_MODE_UNCONNECTED, /*PTE19*/ PAL_MODE_UNCONNECTED, /*PTE20*/ PAL_MODE_INPUT_ANALOG,
- /*PTE21*/ PAL_MODE_INPUT_ANALOG, /*PTE22*/ PAL_MODE_INPUT, /*PTE23*/ PAL_MODE_INPUT_ANALOG,
- /*PTE24*/ PAL_MODE_ALTERNATIVE_5, /*PTE25*/ PAL_MODE_ALTERNATIVE_5, /*PTE26*/ PAL_MODE_UNCONNECTED,
- /*PTE27*/ PAL_MODE_UNCONNECTED, /*PTE28*/ PAL_MODE_UNCONNECTED, /*PTE29*/ PAL_MODE_OUTPUT_PUSHPULL,
- /*PTE30*/ PAL_MODE_INPUT_ANALOG, /*PTE31*/ PAL_MODE_OUTPUT_PUSHPULL,
- },
- },
- },
-};
-#endif
-
-/**
- * @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
- */
-void __early_init(void) {
-
- kl2x_clock_init();
-}
-
-/**
- * @brief Board-specific initialization code.
- * @todo Add your board-specific code, if any.
- */
-void boardInit(void) {
-}
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h b/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h deleted file mode 100644 index 1db7947..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h +++ /dev/null @@ -1,89 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for Freescale Freedom KL26Z board.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_FREESCALE_FREEDOM_KL26Z
-#define BOARD_NAME "Freescale Freedom KL26Z"
-
-/* External 8 MHz crystal. */
-#define KINETIS_XTAL_FREQUENCY 8000000UL
-
-/*
- * MCU type
- */
-#define KL26
-
-/*
- * Onboard features.
- */
-#define GPIO_LED_RED IOPORT5
-#define PIN_LED_RED 29
-#define GPIO_LED_GREEN IOPORT5
-#define PIN_LED_GREEN 31
-#define GPIO_LED_BLUE IOPORT4
-#define PIN_LED_BLUE 5
-#define GPIO_BUTTON IOPORT4
-#define PIN_BUTTON 0
-#define GPIO_LIGHT_SENSOR IOPORT5
-#define PIN_LIGHT_SENSOR 22
-
-/* Inertial sensor: FXOS8700CQ */
-/* Default I2C address 0x1D */
-/* Note: the pins PTE24/25 are assigned to I2C0 by default;
- * if I2C0 is wanted on other pins, these need to be
- * assigned another function explicitly!
- */
-#define I2C_GYRO I2C0
-
-#define LINE_LED_RED PAL_LINE(GPIO_LED_RED, PIN_LED_RED)
-#define LINE_LED_GREEN PAL_LINE(GPIO_LED_GREEN, PIN_LED_GREEN)
-#define LINE_LED_BLUE PAL_LINE(GPIO_LED_BLUE, PIN_LED_BLUE)
-#define LINE_BUTTON PAL_LINE(GPIO_BUTTON, PIN_BUTTON)
-#define LINE_LIGHT_SENSOR PAL_LINE(GPIO_LIGHT_SENSOR, PIN_LIGHT_SENSOR)
-#define LINE_GYRO_SCL PAL_LINE(GPIOE, 24U)
-#define LINE_GYRO_SDA PAL_LINE(GPIOE, 25U)
-#define LINE_GYRO_INT1 PAL_LINE(GPIOD, 0U)
-#define LINE_GYRO_INT2 PAL_LINE(GPIOD, 1U)
-
-/*
- * Not configured:
- * - TSI Slider on PTB16/TSI0_CH9 and PTB17/TSI_CH10
- * - I2C inertial sensor on I2C0, routed to PTE25 and PTE25
- * Note: these pins are assigned to I2C0 by default;
- * if I2C0 is wanted on other pins, these need to be
- * assigned another function explicitly!
- */
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk deleted file mode 100644 index c352346..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files.
-BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.c
-
-# Required include directories
-BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL26Z
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/MCHCK_K20/board.c b/ChibiOS_16.1.5/community/os/hal/boards/MCHCK_K20/board.c deleted file mode 100644 index d67e6ce..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/MCHCK_K20/board.c +++ /dev/null @@ -1,127 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-const PALConfig pal_default_config =
-{
- .ports = {
- {
- .port = IOPORT1, // PORTA
- .pads = {
- /* PTA0*/ PAL_MODE_ALTERNATIVE_7, /* PTA1*/ PAL_MODE_UNCONNECTED, /* PTA2*/ PAL_MODE_UNCONNECTED,
- /* PTA3*/ PAL_MODE_ALTERNATIVE_7, /* PTA4*/ PAL_MODE_UNCONNECTED, /* PTA5*/ PAL_MODE_UNCONNECTED,
- /* PTA6*/ PAL_MODE_UNCONNECTED, /* PTA7*/ PAL_MODE_UNCONNECTED, /* PTA8*/ PAL_MODE_UNCONNECTED,
- /* PTA9*/ PAL_MODE_UNCONNECTED, /*PTA10*/ PAL_MODE_UNCONNECTED, /*PTA11*/ PAL_MODE_UNCONNECTED,
- /*PTA12*/ PAL_MODE_UNCONNECTED, /*PTA13*/ PAL_MODE_UNCONNECTED, /*PTA14*/ PAL_MODE_UNCONNECTED,
- /*PTA15*/ PAL_MODE_UNCONNECTED, /*PTA16*/ PAL_MODE_UNCONNECTED, /*PTA17*/ PAL_MODE_UNCONNECTED,
- /*PTA18*/ PAL_MODE_UNCONNECTED, /*PTA19*/ PAL_MODE_UNCONNECTED, /*PTA20*/ PAL_MODE_UNCONNECTED,
- /*PTA21*/ PAL_MODE_UNCONNECTED, /*PTA22*/ PAL_MODE_UNCONNECTED, /*PTA23*/ PAL_MODE_UNCONNECTED,
- /*PTA24*/ PAL_MODE_UNCONNECTED, /*PTA25*/ PAL_MODE_UNCONNECTED, /*PTA26*/ PAL_MODE_UNCONNECTED,
- /*PTA27*/ PAL_MODE_UNCONNECTED, /*PTA28*/ PAL_MODE_UNCONNECTED, /*PTA29*/ PAL_MODE_UNCONNECTED,
- /*PTA30*/ PAL_MODE_UNCONNECTED, /*PTA31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT2, // PORTB
- .pads = {
- /* PTB0*/ PAL_MODE_UNCONNECTED, /* PTB1*/ PAL_MODE_UNCONNECTED, /* PTB2*/ PAL_MODE_UNCONNECTED,
- /* PTB3*/ PAL_MODE_UNCONNECTED, /* PTB4*/ PAL_MODE_UNCONNECTED, /* PTB5*/ PAL_MODE_UNCONNECTED,
- /* PTB6*/ PAL_MODE_UNCONNECTED, /* PTB7*/ PAL_MODE_UNCONNECTED, /* PTB8*/ PAL_MODE_UNCONNECTED,
- /* PTB9*/ PAL_MODE_UNCONNECTED, /*PTB10*/ PAL_MODE_UNCONNECTED, /*PTB11*/ PAL_MODE_UNCONNECTED,
- /*PTB12*/ PAL_MODE_UNCONNECTED, /*PTB13*/ PAL_MODE_UNCONNECTED, /*PTB14*/ PAL_MODE_UNCONNECTED,
- /*PTB15*/ PAL_MODE_UNCONNECTED, /*PTB16*/ PAL_MODE_OUTPUT_PUSHPULL, /*PTB17*/ PAL_MODE_UNCONNECTED,
- /*PTB18*/ PAL_MODE_UNCONNECTED, /*PTB19*/ PAL_MODE_UNCONNECTED, /*PTB20*/ PAL_MODE_UNCONNECTED,
- /*PTB21*/ PAL_MODE_UNCONNECTED, /*PTB22*/ PAL_MODE_UNCONNECTED, /*PTB23*/ PAL_MODE_UNCONNECTED,
- /*PTB24*/ PAL_MODE_UNCONNECTED, /*PTB25*/ PAL_MODE_UNCONNECTED, /*PTB26*/ PAL_MODE_UNCONNECTED,
- /*PTB27*/ PAL_MODE_UNCONNECTED, /*PTB28*/ PAL_MODE_UNCONNECTED, /*PTB29*/ PAL_MODE_UNCONNECTED,
- /*PTB30*/ PAL_MODE_UNCONNECTED, /*PTB31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT3, // PORTC
- .pads = {
- /* PTC0*/ PAL_MODE_UNCONNECTED, /* PTC1*/ PAL_MODE_UNCONNECTED, /* PTC2*/ PAL_MODE_UNCONNECTED,
- /* PTC3*/ PAL_MODE_UNCONNECTED, /* PTC4*/ PAL_MODE_UNCONNECTED, /* PTC5*/ PAL_MODE_UNCONNECTED,
- /* PTC6*/ PAL_MODE_UNCONNECTED, /* PTC7*/ PAL_MODE_UNCONNECTED, /* PTC8*/ PAL_MODE_UNCONNECTED,
- /* PTC9*/ PAL_MODE_UNCONNECTED, /*PTC10*/ PAL_MODE_UNCONNECTED, /*PTC11*/ PAL_MODE_UNCONNECTED,
- /*PTC12*/ PAL_MODE_UNCONNECTED, /*PTC13*/ PAL_MODE_UNCONNECTED, /*PTC14*/ PAL_MODE_UNCONNECTED,
- /*PTC15*/ PAL_MODE_UNCONNECTED, /*PTC16*/ PAL_MODE_UNCONNECTED, /*PTC17*/ PAL_MODE_UNCONNECTED,
- /*PTC18*/ PAL_MODE_UNCONNECTED, /*PTC19*/ PAL_MODE_UNCONNECTED, /*PTC20*/ PAL_MODE_UNCONNECTED,
- /*PTC21*/ PAL_MODE_UNCONNECTED, /*PTC22*/ PAL_MODE_UNCONNECTED, /*PTC23*/ PAL_MODE_UNCONNECTED,
- /*PTC24*/ PAL_MODE_UNCONNECTED, /*PTC25*/ PAL_MODE_UNCONNECTED, /*PTC26*/ PAL_MODE_UNCONNECTED,
- /*PTC27*/ PAL_MODE_UNCONNECTED, /*PTC28*/ PAL_MODE_UNCONNECTED, /*PTC29*/ PAL_MODE_UNCONNECTED,
- /*PTC30*/ PAL_MODE_UNCONNECTED, /*PTC31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT4, // PORTD
- .pads = {
- /* PTD0*/ PAL_MODE_UNCONNECTED, /* PTD1*/ PAL_MODE_UNCONNECTED, /* PTD2*/ PAL_MODE_UNCONNECTED,
- /* PTD3*/ PAL_MODE_UNCONNECTED, /* PTD4*/ PAL_MODE_UNCONNECTED, /* PTD5*/ PAL_MODE_UNCONNECTED,
- /* PTD6*/ PAL_MODE_UNCONNECTED, /* PTD7*/ PAL_MODE_UNCONNECTED, /* PTD8*/ PAL_MODE_UNCONNECTED,
- /* PTD9*/ PAL_MODE_UNCONNECTED, /*PTD10*/ PAL_MODE_UNCONNECTED, /*PTD11*/ PAL_MODE_UNCONNECTED,
- /*PTD12*/ PAL_MODE_UNCONNECTED, /*PTD13*/ PAL_MODE_UNCONNECTED, /*PTD14*/ PAL_MODE_UNCONNECTED,
- /*PTD15*/ PAL_MODE_UNCONNECTED, /*PTD16*/ PAL_MODE_UNCONNECTED, /*PTD17*/ PAL_MODE_UNCONNECTED,
- /*PTD18*/ PAL_MODE_UNCONNECTED, /*PTD19*/ PAL_MODE_UNCONNECTED, /*PTD20*/ PAL_MODE_UNCONNECTED,
- /*PTD21*/ PAL_MODE_UNCONNECTED, /*PTD22*/ PAL_MODE_UNCONNECTED, /*PTD23*/ PAL_MODE_UNCONNECTED,
- /*PTD24*/ PAL_MODE_UNCONNECTED, /*PTD25*/ PAL_MODE_UNCONNECTED, /*PTD26*/ PAL_MODE_UNCONNECTED,
- /*PTD27*/ PAL_MODE_UNCONNECTED, /*PTD28*/ PAL_MODE_UNCONNECTED, /*PTD29*/ PAL_MODE_UNCONNECTED,
- /*PTD30*/ PAL_MODE_UNCONNECTED, /*PTD31*/ PAL_MODE_UNCONNECTED,
- },
- },
- {
- .port = IOPORT5, // PORTE
- .pads = {
- /* PTE0*/ PAL_MODE_UNCONNECTED, /* PTE1*/ PAL_MODE_UNCONNECTED, /* PTE2*/ PAL_MODE_UNCONNECTED,
- /* PTE3*/ PAL_MODE_UNCONNECTED, /* PTE4*/ PAL_MODE_UNCONNECTED, /* PTE5*/ PAL_MODE_UNCONNECTED,
- /* PTE6*/ PAL_MODE_UNCONNECTED, /* PTE7*/ PAL_MODE_UNCONNECTED, /* PTE8*/ PAL_MODE_UNCONNECTED,
- /* PTE9*/ PAL_MODE_UNCONNECTED, /*PTE10*/ PAL_MODE_UNCONNECTED, /*PTE11*/ PAL_MODE_UNCONNECTED,
- /*PTE12*/ PAL_MODE_UNCONNECTED, /*PTE13*/ PAL_MODE_UNCONNECTED, /*PTE14*/ PAL_MODE_UNCONNECTED,
- /*PTE15*/ PAL_MODE_UNCONNECTED, /*PTE16*/ PAL_MODE_UNCONNECTED, /*PTE17*/ PAL_MODE_UNCONNECTED,
- /*PTE18*/ PAL_MODE_UNCONNECTED, /*PTE19*/ PAL_MODE_UNCONNECTED, /*PTE20*/ PAL_MODE_UNCONNECTED,
- /*PTE21*/ PAL_MODE_UNCONNECTED, /*PTE22*/ PAL_MODE_UNCONNECTED, /*PTE23*/ PAL_MODE_UNCONNECTED,
- /*PTE24*/ PAL_MODE_UNCONNECTED, /*PTE25*/ PAL_MODE_UNCONNECTED, /*PTE26*/ PAL_MODE_UNCONNECTED,
- /*PTE27*/ PAL_MODE_UNCONNECTED, /*PTE28*/ PAL_MODE_UNCONNECTED, /*PTE29*/ PAL_MODE_UNCONNECTED,
- /*PTE30*/ PAL_MODE_UNCONNECTED, /*PTE31*/ PAL_MODE_UNCONNECTED,
- },
- },
- },
-};
-#endif
-
-/**
- * @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
- */
-void __early_init(void) {
-
- k20x_clock_init();
-}
-
-/**
- * @brief Board-specific initialization code.
- * @todo Add your board-specific code, if any.
- */
-void boardInit(void) {
-}
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/MCHCK_K20/board.h b/ChibiOS_16.1.5/community/os/hal/boards/MCHCK_K20/board.h deleted file mode 100644 index aad3e27..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/MCHCK_K20/board.h +++ /dev/null @@ -1,49 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for MCHCL K20 board with MX20DX128 processor.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_MCHCK_K20_MX20DX128
-#define BOARD_NAME "MCHCK K20 MX20DX128"
-
-/*
- * MCU type
- */
-#define K20x5
-
-#define GPIOB_LED 16
-
-#define LINE_LED PAL_LINE(GPIOB, GPIOB_LED)
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/MCHCK_K20/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/MCHCK_K20/board.mk deleted file mode 100644 index 22406ac..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/MCHCK_K20/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files.
-BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/MCHCK_K20/board.c
-
-# Required include directories
-BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/MCHCK_K20
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c b/ChibiOS_16.1.5/community/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c deleted file mode 100644 index e6c6080..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. - */ -const PALConfig pal_default_config = -{ - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} -}; -#endif - -/** - * @brief Early initialization code. - * @details This initialization must be performed just after stack setup - * and before any other initialization. - */ -void __early_init(void) { - - stm32_clock_init(); -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return TRUE; -} - -/** - * @brief SDC card write protection detection. - */ -bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - /* TODO: Fill the implementation.*/ - return FALSE; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return TRUE; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { - - (void)mmcp; - /* TODO: Fill the implementation.*/ - return FALSE; -} -#endif - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) { -} diff --git a/ChibiOS_16.1.5/community/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h b/ChibiOS_16.1.5/community/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h deleted file mode 100644 index 05aeceb..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h +++ /dev/null @@ -1,1160 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for STMicroelectronics STM32F4-Discovery board. - */ - -/* - * Board identifier. - */ -#define BOARD_NAME "NAND and SRAM test board (codename Buod)" - -/* - * Board oscillators-related settings. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 32768 -#endif - -#if !defined(STM32_HSECLK) -#define STM32_HSECLK 12000000 -#endif - -/* - * Board voltages. - * Required for performance limits calculation. - */ -#define STM32_VDD 300 - -/* - * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. - */ -#define STM32F407xx - -/* - * IO pins assignments. - */ -#define GPIOA_PIN0 0 -#define GPIOA_PIN1 1 -#define GPIOA_PIN2 2 -#define GPIOA_PIN3 3 -#define GPIOA_SPI1_NSS 4 -#define GPIOA_PIN5 5 -#define GPIOA_PIN6 6 -#define GPIOA_PIN7 7 -#define GPIOA_PIN8 8 -#define GPIOA_USB_PRESENT 9 -#define GPIOA_PIN10 10 -#define GPIOA_OTG_FS_DM 11 -#define GPIOA_OTG_FS_DP 12 -#define GPIOA_JTMS 13 -#define GPIOA_JTCK 14 -#define GPIOA_JTDI 15 - - - -#define GPIOA_USB_PRESENT 9 -#define GPIOA_PIN10 10 -#define GPIOA_OTG_FS_DM 11 -#define GPIOA_OTG_FS_DP 12 - - -#define GPIOB_PIN0 0 -#define GPIOB_NAND_WP 1 -#define GPIOB_PIN2 2 -#define GPIOB_JTDO 3 -#define GPIOB_JTRST 4 -#define GPIOB_NVRAM_PWR 5 -#define GPIOB_PIN6 6 -#define GPIOB_PIN7 7 -#define GPIOB_PIN8 8 -#define GPIOB_PIN9 9 -#define GPIOB_PIN10 10 -#define GPIOB_PIN11 11 -#define GPIOB_PIN12 12 -#define GPIOB_PIN13 13 -#define GPIOB_PIN14 14 -#define GPIOB_PIN15 15 - -#define GPIOC_PIN0 0 -#define GPIOC_PIN1 1 -#define GPIOC_PIN2 2 -#define GPIOC_PIN3 3 -#define GPIOC_PIN4 4 -#define GPIOC_PIN5 5 -#define GPIOC_PIN6 6 -#define GPIOC_PIN7 7 -#define GPIOC_PIN8 8 -#define GPIOC_PIN9 9 -#define GPIOC_PIN10 10 -#define GPIOC_PIN11 11 -#define GPIOC_PIN12 12 -#define GPIOC_PIN13 13 -#define GPIOC_PIN14 14 -#define GPIOC_PIN15 15 - -#define GPIOD_MEM_D2 0 -#define GPIOD_MEM_D3 1 -#define GPIOD_PIN2 2 -#define GPIOD_PIN3 3 -#define GPIOD_MEM_OE 4 -#define GPIOD_MEM_WE 5 -#define GPIOD_NAND_RB_NWAIT 6 -#define GPIOD_NAND_CE1 7 -#define GPIOD_MEM_D13 8 -#define GPIOD_MEM_D14 9 -#define GPIOD_MEM_D15 10 -#define GPIOD_MEM_A16 11 -#define GPIOD_MEM_A17 12 -#define GPIOD_PIN13 13 -#define GPIOD_MEM_D0 14 -#define GPIOD_MEM_D1 15 - -#define GPIOE_SRAM_LB 0 -#define GPIOE_SRAM_UB 1 -#define GPIOE_PIN2 2 -#define GPIOE_PIN3 3 -#define GPIOE_PIN4 4 -#define GPIOE_PIN5 5 -#define GPIOE_PIN6 6 -#define GPIOE_MEM_D4 7 -#define GPIOE_MEM_D5 8 -#define GPIOE_MEM_D6 9 -#define GPIOE_MEM_D7 10 -#define GPIOE_MEM_D8 11 -#define GPIOE_MEM_D9 12 -#define GPIOE_MEM_D10 13 -#define GPIOE_MEM_D11 14 -#define GPIOE_MEM_D12 15 - -#define GPIOF_MEM_A0 0 -#define GPIOF_MEM_A1 1 -#define GPIOF_MEM_A2 2 -#define GPIOF_MEM_A3 3 -#define GPIOF_MEM_A4 4 -#define GPIOF_MEM_A5 5 -#define GPIOF_PIN6 6 -#define GPIOF_PIN7 7 -#define GPIOF_PIN8 8 -#define GPIOF_PIN9 9 -#define GPIOF_PIN10 10 -#define GPIOF_PIN11 11 -#define GPIOF_MEM_A6 12 -#define GPIOF_MEM_A7 13 -#define GPIOF_MEM_A8 14 -#define GPIOF_MEM_A9 15 - -#define GPIOG_MEM_A10 0 -#define GPIOG_MEM_A11 1 -#define GPIOG_MEM_A12 2 -#define GPIOG_MEM_A13 3 -#define GPIOG_MEM_A14 4 -#define GPIOG_MEM_A15 5 -#define GPIOG_NAND_RB1 6 -#define GPIOG_NAND_RB2 7 -#define GPIOG_PIN8 8 -#define GPIOG_NAND_CE2 9 -#define GPIOG_PIN10 10 -#define GPIOG_PIN11 11 -#define GPIOG_SRAM_CS1 12 -#define GPIOG_PIN13 13 -#define GPIOG_PIN14 14 -#define GPIOG_PIN15 15 - -#define GPIOH_OSC_IN 0 -#define GPIOH_OSC_OUT 1 -#define GPIOH_PIN2 2 -#define GPIOH_PIN3 3 -#define GPIOH_PIN4 4 -#define GPIOH_PIN5 5 -#define GPIOH_PIN6 6 -#define GPIOH_I2C3_SCL 7 -#define GPIOH_I2C3_SDA 8 -#define GPIOH_PIN9 9 -#define GPIOH_PIN10 10 -#define GPIOH_PIN11 11 -#define GPIOH_PIN12 12 -#define GPIOH_PIN13 13 -#define GPIOH_PIN14 14 -#define GPIOH_PIN15 15 - -#define GPIOI_PIN0 0 -#define GPIOI_PIN1 1 -#define GPIOI_PIN2 2 -#define GPIOI_PIN3 3 -#define GPIOI_PIN4 4 -#define GPIOI_PIN5 5 -#define GPIOI_PIN6 6 -#define GPIOI_PIN7 7 -#define GPIOI_PIN8 8 -#define GPIOI_PIN9 9 -#define GPIOI_LED_R 10 -#define GPIOI_LED_G 11 -#define GPIOI_PIN12 12 -#define GPIOI_PIN13 13 -#define GPIOI_PIN14 14 -#define GPIOI_PIN15 15 - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) -#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) -#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) -#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) -#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) - -/* - * GPIOA setup: - */ -#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \ - PIN_MODE_INPUT(GPIOA_PIN1) | \ - PIN_MODE_INPUT(GPIOA_PIN2) | \ - PIN_MODE_INPUT(GPIOA_PIN3) | \ - PIN_MODE_ALTERNATE(GPIOA_SPI1_NSS) | \ - PIN_MODE_INPUT(GPIOA_PIN5) | \ - PIN_MODE_INPUT(GPIOA_PIN6) | \ - PIN_MODE_INPUT(GPIOA_PIN7) | \ - PIN_MODE_INPUT(GPIOA_PIN8) | \ - PIN_MODE_INPUT(GPIOA_USB_PRESENT) | \ - PIN_MODE_INPUT(GPIOA_PIN10) | \ - PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ - PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ - PIN_MODE_ALTERNATE(GPIOA_JTMS) | \ - PIN_MODE_ALTERNATE(GPIOA_JTCK) | \ - PIN_MODE_ALTERNATE(GPIOA_JTDI)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SPI1_NSS) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOA_USB_PRESENT) |\ - PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ - PIN_OTYPE_PUSHPULL(GPIOA_JTMS) | \ - PIN_OTYPE_PUSHPULL(GPIOA_JTCK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_JTDI)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_PIN0) | \ - PIN_OSPEED_100M(GPIOA_PIN1) | \ - PIN_OSPEED_100M(GPIOA_PIN2) | \ - PIN_OSPEED_100M(GPIOA_PIN3) | \ - PIN_OSPEED_100M(GPIOA_SPI1_NSS) | \ - PIN_OSPEED_100M(GPIOA_PIN5) | \ - PIN_OSPEED_100M(GPIOA_PIN6) | \ - PIN_OSPEED_100M(GPIOA_PIN7) | \ - PIN_OSPEED_100M(GPIOA_PIN8) | \ - PIN_OSPEED_100M(GPIOA_USB_PRESENT) | \ - PIN_OSPEED_100M(GPIOA_PIN10) | \ - PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \ - PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \ - PIN_OSPEED_100M(GPIOA_JTMS) | \ - PIN_OSPEED_100M(GPIOA_JTCK) | \ - PIN_OSPEED_100M(GPIOA_JTDI)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOA_SPI1_NSS) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOA_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOA_USB_PRESENT) |\ - PIN_PUPDR_FLOATING(GPIOA_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ - PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ - PIN_PUPDR_FLOATING(GPIOA_JTMS) | \ - PIN_PUPDR_FLOATING(GPIOA_JTCK) | \ - PIN_PUPDR_FLOATING(GPIOA_JTDI)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ - PIN_ODR_HIGH(GPIOA_PIN1) | \ - PIN_ODR_HIGH(GPIOA_PIN2) | \ - PIN_ODR_HIGH(GPIOA_PIN3) | \ - PIN_ODR_HIGH(GPIOA_SPI1_NSS) | \ - PIN_ODR_HIGH(GPIOA_PIN5) | \ - PIN_ODR_HIGH(GPIOA_PIN6) | \ - PIN_ODR_HIGH(GPIOA_PIN7) | \ - PIN_ODR_HIGH(GPIOA_PIN8) | \ - PIN_ODR_HIGH(GPIOA_USB_PRESENT) | \ - PIN_ODR_HIGH(GPIOA_PIN10) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ - PIN_ODR_HIGH(GPIOA_JTMS) | \ - PIN_ODR_HIGH(GPIOA_JTCK) | \ - PIN_ODR_HIGH(GPIOA_JTDI)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0) | \ - PIN_AFIO_AF(GPIOA_PIN1, 0) | \ - PIN_AFIO_AF(GPIOA_PIN2, 0) | \ - PIN_AFIO_AF(GPIOA_PIN3, 0) | \ - PIN_AFIO_AF(GPIOA_SPI1_NSS, 5) | \ - PIN_AFIO_AF(GPIOA_PIN5, 0) | \ - PIN_AFIO_AF(GPIOA_PIN6, 0) | \ - PIN_AFIO_AF(GPIOA_PIN7, 0)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \ - PIN_AFIO_AF(GPIOA_USB_PRESENT, 0) | \ - PIN_AFIO_AF(GPIOA_PIN10, 0) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ - PIN_AFIO_AF(GPIOA_JTMS, 0) | \ - PIN_AFIO_AF(GPIOA_JTCK, 0) | \ - PIN_AFIO_AF(GPIOA_JTDI, 0)) - -/* - * GPIOB setup: - */ -#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ - PIN_MODE_OUTPUT(GPIOB_NAND_WP) | \ - PIN_MODE_INPUT(GPIOB_PIN2) | \ - PIN_MODE_ALTERNATE(GPIOB_JTDO) | \ - PIN_MODE_ALTERNATE(GPIOB_JTRST) | \ - PIN_MODE_OUTPUT(GPIOB_NVRAM_PWR) | \ - PIN_MODE_INPUT(GPIOB_PIN6) | \ - PIN_MODE_INPUT(GPIOB_PIN7) | \ - PIN_MODE_INPUT(GPIOB_PIN8) | \ - PIN_MODE_INPUT(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_INPUT(GPIOB_PIN13) | \ - PIN_MODE_INPUT(GPIOB_PIN14) | \ - PIN_MODE_INPUT(GPIOB_PIN15)) - -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_NAND_WP) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOB_JTDO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_JTRST) | \ - PIN_OTYPE_OPENDRAIN(GPIOB_NVRAM_PWR) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \ - PIN_OSPEED_100M(GPIOB_NAND_WP) | \ - PIN_OSPEED_100M(GPIOB_PIN2) | \ - PIN_OSPEED_100M(GPIOB_JTDO) | \ - PIN_OSPEED_100M(GPIOB_JTRST) | \ - PIN_OSPEED_2M(GPIOB_NVRAM_PWR) | \ - PIN_OSPEED_100M(GPIOB_PIN6) | \ - PIN_OSPEED_100M(GPIOB_PIN7) | \ - PIN_OSPEED_100M(GPIOB_PIN8) | \ - PIN_OSPEED_100M(GPIOB_PIN9) | \ - PIN_OSPEED_100M(GPIOB_PIN10) | \ - PIN_OSPEED_100M(GPIOB_PIN11) | \ - PIN_OSPEED_100M(GPIOB_PIN12) | \ - PIN_OSPEED_100M(GPIOB_PIN13) | \ - PIN_OSPEED_100M(GPIOB_PIN14) | \ - PIN_OSPEED_100M(GPIOB_PIN15)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \ - PIN_PUPDR_PULLDOWN(GPIOB_NAND_WP) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOB_JTDO) | \ - PIN_PUPDR_FLOATING(GPIOB_JTRST) | \ - PIN_PUPDR_FLOATING(GPIOB_NVRAM_PWR) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOB_PIN15)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_LOW(GPIOB_NAND_WP) | \ - PIN_ODR_HIGH(GPIOB_PIN2) | \ - PIN_ODR_HIGH(GPIOB_JTDO) | \ - PIN_ODR_HIGH(GPIOB_JTRST) | \ - PIN_ODR_LOW(GPIOB_NVRAM_PWR) | \ - PIN_ODR_HIGH(GPIOB_PIN6) | \ - PIN_ODR_HIGH(GPIOB_PIN7) | \ - PIN_ODR_HIGH(GPIOB_PIN8) | \ - PIN_ODR_HIGH(GPIOB_PIN9) | \ - PIN_ODR_HIGH(GPIOB_PIN10) | \ - PIN_ODR_HIGH(GPIOB_PIN11) | \ - PIN_ODR_HIGH(GPIOB_PIN12) | \ - PIN_ODR_HIGH(GPIOB_PIN13) | \ - PIN_ODR_HIGH(GPIOB_PIN14) | \ - PIN_ODR_HIGH(GPIOB_PIN15)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \ - PIN_AFIO_AF(GPIOB_NAND_WP, 0) | \ - PIN_AFIO_AF(GPIOB_PIN2, 0) | \ - PIN_AFIO_AF(GPIOB_JTDO, 0) | \ - PIN_AFIO_AF(GPIOB_JTRST, 0) | \ - PIN_AFIO_AF(GPIOB_NVRAM_PWR, 0) | \ - PIN_AFIO_AF(GPIOB_PIN6, 0) | \ - PIN_AFIO_AF(GPIOB_PIN7, 0)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \ - PIN_AFIO_AF(GPIOB_PIN9, 0) | \ - PIN_AFIO_AF(GPIOB_PIN10, 0) | \ - PIN_AFIO_AF(GPIOB_PIN11, 0) | \ - PIN_AFIO_AF(GPIOB_PIN12, 0) | \ - PIN_AFIO_AF(GPIOB_PIN13, 0) | \ - PIN_AFIO_AF(GPIOB_PIN14, 0) | \ - PIN_AFIO_AF(GPIOB_PIN15, 0)) - -/* - * GPIOC setup: - */ -#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ - PIN_MODE_INPUT(GPIOC_PIN1) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_INPUT(GPIOC_PIN4) | \ - PIN_MODE_INPUT(GPIOC_PIN5) | \ - PIN_MODE_INPUT(GPIOC_PIN6) | \ - PIN_MODE_INPUT(GPIOC_PIN7) | \ - PIN_MODE_INPUT(GPIOC_PIN8) | \ - PIN_MODE_INPUT(GPIOC_PIN9) | \ - PIN_MODE_INPUT(GPIOC_PIN10) | \ - PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_INPUT(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_INPUT(GPIOC_PIN14) | \ - PIN_MODE_INPUT(GPIOC_PIN15)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_PIN0) |\ - PIN_OSPEED_100M(GPIOC_PIN1) | \ - PIN_OSPEED_100M(GPIOC_PIN2) | \ - PIN_OSPEED_100M(GPIOC_PIN3) | \ - PIN_OSPEED_100M(GPIOC_PIN4) | \ - PIN_OSPEED_100M(GPIOC_PIN5) | \ - PIN_OSPEED_100M(GPIOC_PIN6) | \ - PIN_OSPEED_100M(GPIOC_PIN7) | \ - PIN_OSPEED_100M(GPIOC_PIN8) | \ - PIN_OSPEED_100M(GPIOC_PIN9) | \ - PIN_OSPEED_100M(GPIOC_PIN10) | \ - PIN_OSPEED_100M(GPIOC_PIN11) | \ - PIN_OSPEED_100M(GPIOC_PIN12) | \ - PIN_OSPEED_100M(GPIOC_PIN13) | \ - PIN_OSPEED_100M(GPIOC_PIN14) | \ - PIN_OSPEED_100M(GPIOC_PIN15)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOC_PIN15)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ - PIN_ODR_HIGH(GPIOC_PIN1) | \ - PIN_ODR_HIGH(GPIOC_PIN2) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_PIN4) | \ - PIN_ODR_HIGH(GPIOC_PIN5) | \ - PIN_ODR_HIGH(GPIOC_PIN6) | \ - PIN_ODR_HIGH(GPIOC_PIN7) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_PIN9) | \ - PIN_ODR_HIGH(GPIOC_PIN10) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_PIN14) | \ - PIN_ODR_HIGH(GPIOC_PIN15)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \ - PIN_AFIO_AF(GPIOC_PIN1, 0) | \ - PIN_AFIO_AF(GPIOC_PIN2, 0) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0) | \ - PIN_AFIO_AF(GPIOC_PIN4, 0) | \ - PIN_AFIO_AF(GPIOC_PIN5, 0) | \ - PIN_AFIO_AF(GPIOC_PIN6, 0) | \ - PIN_AFIO_AF(GPIOC_PIN7, 0)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \ - PIN_AFIO_AF(GPIOC_PIN9, 0) | \ - PIN_AFIO_AF(GPIOC_PIN10, 0) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0) | \ - PIN_AFIO_AF(GPIOC_PIN14, 0) | \ - PIN_AFIO_AF(GPIOC_PIN15, 0)) - -/* - * GPIOD setup: - */ -#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_MEM_D2) | \ - PIN_MODE_ALTERNATE(GPIOD_MEM_D3) | \ - PIN_MODE_INPUT(GPIOD_PIN2) | \ - PIN_MODE_INPUT(GPIOD_PIN3) | \ - PIN_MODE_ALTERNATE(GPIOD_MEM_OE) | \ - PIN_MODE_ALTERNATE(GPIOD_MEM_WE) | \ - PIN_MODE_INPUT(GPIOD_NAND_RB_NWAIT) | \ - PIN_MODE_ALTERNATE(GPIOD_NAND_CE1) | \ - PIN_MODE_ALTERNATE(GPIOD_MEM_D13) | \ - PIN_MODE_ALTERNATE(GPIOD_MEM_D14) | \ - PIN_MODE_ALTERNATE(GPIOD_MEM_D15) | \ - PIN_MODE_ALTERNATE(GPIOD_MEM_A16) | \ - PIN_MODE_ALTERNATE(GPIOD_MEM_A17) | \ - PIN_MODE_INPUT(GPIOD_PIN13) | \ - PIN_MODE_ALTERNATE(GPIOD_MEM_D0) | \ - PIN_MODE_ALTERNATE(GPIOD_MEM_D1)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_MEM_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_MEM_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_MEM_OE) | \ - PIN_OTYPE_PUSHPULL(GPIOD_MEM_WE) | \ - PIN_OTYPE_PUSHPULL(GPIOD_NAND_RB_NWAIT) |\ - PIN_OTYPE_PUSHPULL(GPIOD_NAND_CE1) | \ - PIN_OTYPE_PUSHPULL(GPIOD_MEM_D13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_MEM_D14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_MEM_D15) | \ - PIN_OTYPE_PUSHPULL(GPIOD_MEM_A16) | \ - PIN_OTYPE_PUSHPULL(GPIOD_MEM_A17) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_MEM_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_MEM_D1)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_MEM_D2) | \ - PIN_OSPEED_100M(GPIOD_MEM_D3) | \ - PIN_OSPEED_100M(GPIOD_PIN2) | \ - PIN_OSPEED_100M(GPIOD_PIN3) | \ - PIN_OSPEED_100M(GPIOD_MEM_OE) | \ - PIN_OSPEED_100M(GPIOD_MEM_WE) | \ - PIN_OSPEED_100M(GPIOD_NAND_RB_NWAIT) | \ - PIN_OSPEED_100M(GPIOD_NAND_CE1) | \ - PIN_OSPEED_100M(GPIOD_MEM_D13) | \ - PIN_OSPEED_100M(GPIOD_MEM_D14) | \ - PIN_OSPEED_100M(GPIOD_MEM_D15) | \ - PIN_OSPEED_100M(GPIOD_MEM_A16) | \ - PIN_OSPEED_100M(GPIOD_MEM_A17) | \ - PIN_OSPEED_100M(GPIOD_PIN13) | \ - PIN_OSPEED_100M(GPIOD_MEM_D0) | \ - PIN_OSPEED_100M(GPIOD_MEM_D1)) - -#if STM32_NAND_USE_EXT_INT -#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_PULLUP(pin)) -#else -#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_FLOATING(pin)) -#endif -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_MEM_D2) | \ - PIN_PUPDR_FLOATING(GPIOD_MEM_D3) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOD_MEM_OE) | \ - PIN_PUPDR_FLOATING(GPIOD_MEM_WE) | \ - NAND_RB_NWAIT_PUPDR(GPIOD_NAND_RB_NWAIT) | \ - PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \ - PIN_PUPDR_FLOATING(GPIOD_MEM_D13) | \ - PIN_PUPDR_FLOATING(GPIOD_MEM_D14) | \ - PIN_PUPDR_FLOATING(GPIOD_MEM_D15) | \ - PIN_PUPDR_FLOATING(GPIOD_MEM_A16) | \ - PIN_PUPDR_FLOATING(GPIOD_MEM_A17) | \ - PIN_PUPDR_FLOATING(GPIOD_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOD_MEM_D0) | \ - PIN_PUPDR_FLOATING(GPIOD_MEM_D1)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_MEM_D2) | \ - PIN_ODR_HIGH(GPIOD_MEM_D3) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_PIN3) | \ - PIN_ODR_HIGH(GPIOD_MEM_OE) | \ - PIN_ODR_HIGH(GPIOD_MEM_WE) | \ - PIN_ODR_HIGH(GPIOD_NAND_RB_NWAIT) | \ - PIN_ODR_HIGH(GPIOD_NAND_CE1) | \ - PIN_ODR_HIGH(GPIOD_MEM_D13) | \ - PIN_ODR_HIGH(GPIOD_MEM_D14) | \ - PIN_ODR_HIGH(GPIOD_MEM_D15) | \ - PIN_ODR_HIGH(GPIOD_MEM_A16) | \ - PIN_ODR_HIGH(GPIOD_MEM_A17) | \ - PIN_ODR_HIGH(GPIOD_PIN13) | \ - PIN_ODR_HIGH(GPIOD_MEM_D0) | \ - PIN_ODR_HIGH(GPIOD_MEM_D1)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_MEM_D2, 12) | \ - PIN_AFIO_AF(GPIOD_MEM_D3, 12) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0) | \ - PIN_AFIO_AF(GPIOD_PIN3, 0) | \ - PIN_AFIO_AF(GPIOD_MEM_OE, 12) | \ - PIN_AFIO_AF(GPIOD_MEM_WE, 12) | \ - PIN_AFIO_AF(GPIOD_NAND_RB_NWAIT, 0) | \ - PIN_AFIO_AF(GPIOD_NAND_CE1, 12)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_MEM_D13, 12) | \ - PIN_AFIO_AF(GPIOD_MEM_D14, 12) | \ - PIN_AFIO_AF(GPIOD_MEM_D15, 12) | \ - PIN_AFIO_AF(GPIOD_MEM_A16, 12) | \ - PIN_AFIO_AF(GPIOD_MEM_A17, 12) | \ - PIN_AFIO_AF(GPIOD_PIN13, 0) | \ - PIN_AFIO_AF(GPIOD_MEM_D0, 12) | \ - PIN_AFIO_AF(GPIOD_MEM_D1, 12)) - -/* - * GPIOE setup: - */ -#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_SRAM_LB) | \ - PIN_MODE_ALTERNATE(GPIOE_SRAM_UB) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_ALTERNATE(GPIOE_MEM_D4) | \ - PIN_MODE_ALTERNATE(GPIOE_MEM_D5) | \ - PIN_MODE_ALTERNATE(GPIOE_MEM_D6) | \ - PIN_MODE_ALTERNATE(GPIOE_MEM_D7) | \ - PIN_MODE_ALTERNATE(GPIOE_MEM_D8) | \ - PIN_MODE_ALTERNATE(GPIOE_MEM_D9) | \ - PIN_MODE_ALTERNATE(GPIOE_MEM_D10) | \ - PIN_MODE_ALTERNATE(GPIOE_MEM_D11) | \ - PIN_MODE_ALTERNATE(GPIOE_MEM_D12)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_SRAM_LB) | \ - PIN_OTYPE_PUSHPULL(GPIOE_SRAM_UB) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_MEM_D4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_MEM_D5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_MEM_D6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_MEM_D7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_MEM_D8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_MEM_D9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_MEM_D10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_MEM_D11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_MEM_D12)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_SRAM_LB) | \ - PIN_OSPEED_100M(GPIOE_SRAM_UB) | \ - PIN_OSPEED_100M(GPIOE_PIN2) | \ - PIN_OSPEED_100M(GPIOE_PIN3) | \ - PIN_OSPEED_100M(GPIOE_PIN4) | \ - PIN_OSPEED_100M(GPIOE_PIN5) | \ - PIN_OSPEED_100M(GPIOE_PIN6) | \ - PIN_OSPEED_100M(GPIOE_MEM_D4) | \ - PIN_OSPEED_100M(GPIOE_MEM_D5) | \ - PIN_OSPEED_100M(GPIOE_MEM_D6) | \ - PIN_OSPEED_100M(GPIOE_MEM_D7) | \ - PIN_OSPEED_100M(GPIOE_MEM_D8) | \ - PIN_OSPEED_100M(GPIOE_MEM_D9) | \ - PIN_OSPEED_100M(GPIOE_MEM_D10) | \ - PIN_OSPEED_100M(GPIOE_MEM_D11) | \ - PIN_OSPEED_100M(GPIOE_MEM_D12)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_SRAM_LB) | \ - PIN_PUPDR_FLOATING(GPIOE_SRAM_UB) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_MEM_D4) | \ - PIN_PUPDR_FLOATING(GPIOE_MEM_D5) | \ - PIN_PUPDR_FLOATING(GPIOE_MEM_D6) | \ - PIN_PUPDR_FLOATING(GPIOE_MEM_D7) | \ - PIN_PUPDR_FLOATING(GPIOE_MEM_D8) | \ - PIN_PUPDR_FLOATING(GPIOE_MEM_D9) | \ - PIN_PUPDR_FLOATING(GPIOE_MEM_D10) | \ - PIN_PUPDR_FLOATING(GPIOE_MEM_D11) | \ - PIN_PUPDR_FLOATING(GPIOE_MEM_D12)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_SRAM_LB) | \ - PIN_ODR_HIGH(GPIOE_SRAM_UB) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_MEM_D4) | \ - PIN_ODR_HIGH(GPIOE_MEM_D5) | \ - PIN_ODR_HIGH(GPIOE_MEM_D6) | \ - PIN_ODR_HIGH(GPIOE_MEM_D7) | \ - PIN_ODR_HIGH(GPIOE_MEM_D8) | \ - PIN_ODR_HIGH(GPIOE_MEM_D9) | \ - PIN_ODR_HIGH(GPIOE_MEM_D10) | \ - PIN_ODR_HIGH(GPIOE_MEM_D11) | \ - PIN_ODR_HIGH(GPIOE_MEM_D12)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_SRAM_LB, 12) | \ - PIN_AFIO_AF(GPIOE_SRAM_UB, 12) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0) | \ - PIN_AFIO_AF(GPIOE_MEM_D4, 12)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_MEM_D5, 12) | \ - PIN_AFIO_AF(GPIOE_MEM_D6, 12) | \ - PIN_AFIO_AF(GPIOE_MEM_D7, 12) | \ - PIN_AFIO_AF(GPIOE_MEM_D8, 12) | \ - PIN_AFIO_AF(GPIOE_MEM_D9, 12) | \ - PIN_AFIO_AF(GPIOE_MEM_D10, 12) | \ - PIN_AFIO_AF(GPIOE_MEM_D11, 12) | \ - PIN_AFIO_AF(GPIOE_MEM_D12, 12)) - -/* - * GPIOF setup: - */ -#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_MEM_A0) | \ - PIN_MODE_ALTERNATE(GPIOF_MEM_A1) | \ - PIN_MODE_ALTERNATE(GPIOF_MEM_A2) | \ - PIN_MODE_ALTERNATE(GPIOF_MEM_A3) | \ - PIN_MODE_ALTERNATE(GPIOF_MEM_A4) | \ - PIN_MODE_ALTERNATE(GPIOF_MEM_A5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN8) | \ - PIN_MODE_INPUT(GPIOF_PIN9) | \ - PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ - PIN_MODE_ALTERNATE(GPIOF_MEM_A6) | \ - PIN_MODE_ALTERNATE(GPIOF_MEM_A7) | \ - PIN_MODE_ALTERNATE(GPIOF_MEM_A8) | \ - PIN_MODE_ALTERNATE(GPIOF_MEM_A9)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_MEM_A0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_MEM_A1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_MEM_A2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_MEM_A3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_MEM_A4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_MEM_A5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOF_MEM_A6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_MEM_A7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_MEM_A8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_MEM_A9)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_MEM_A0) | \ - PIN_OSPEED_100M(GPIOF_MEM_A1) | \ - PIN_OSPEED_100M(GPIOF_MEM_A2) | \ - PIN_OSPEED_100M(GPIOF_MEM_A3) | \ - PIN_OSPEED_100M(GPIOF_MEM_A4) | \ - PIN_OSPEED_100M(GPIOF_MEM_A5) | \ - PIN_OSPEED_100M(GPIOF_PIN6) | \ - PIN_OSPEED_100M(GPIOF_PIN7) | \ - PIN_OSPEED_100M(GPIOF_PIN8) | \ - PIN_OSPEED_100M(GPIOF_PIN9) | \ - PIN_OSPEED_100M(GPIOF_PIN10) | \ - PIN_OSPEED_100M(GPIOF_PIN11) | \ - PIN_OSPEED_100M(GPIOF_MEM_A6) | \ - PIN_OSPEED_100M(GPIOF_MEM_A7) | \ - PIN_OSPEED_100M(GPIOF_MEM_A8) | \ - PIN_OSPEED_100M(GPIOF_MEM_A9)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_MEM_A0) | \ - PIN_PUPDR_FLOATING(GPIOF_MEM_A1) | \ - PIN_PUPDR_FLOATING(GPIOF_MEM_A2) | \ - PIN_PUPDR_FLOATING(GPIOF_MEM_A3) | \ - PIN_PUPDR_FLOATING(GPIOF_MEM_A4) | \ - PIN_PUPDR_FLOATING(GPIOF_MEM_A5) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOF_MEM_A6) | \ - PIN_PUPDR_FLOATING(GPIOF_MEM_A7) | \ - PIN_PUPDR_FLOATING(GPIOF_MEM_A8) | \ - PIN_PUPDR_FLOATING(GPIOF_MEM_A9)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_MEM_A0) | \ - PIN_ODR_HIGH(GPIOF_MEM_A1) | \ - PIN_ODR_HIGH(GPIOF_MEM_A2) | \ - PIN_ODR_HIGH(GPIOF_MEM_A3) | \ - PIN_ODR_HIGH(GPIOF_MEM_A4) | \ - PIN_ODR_HIGH(GPIOF_MEM_A5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_PIN7) | \ - PIN_ODR_HIGH(GPIOF_PIN8) | \ - PIN_ODR_HIGH(GPIOF_PIN9) | \ - PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ - PIN_ODR_HIGH(GPIOF_MEM_A6) | \ - PIN_ODR_HIGH(GPIOF_MEM_A7) | \ - PIN_ODR_HIGH(GPIOF_MEM_A8) | \ - PIN_ODR_HIGH(GPIOF_MEM_A9)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_MEM_A0, 12) | \ - PIN_AFIO_AF(GPIOF_MEM_A1, 12) | \ - PIN_AFIO_AF(GPIOF_MEM_A2, 12) | \ - PIN_AFIO_AF(GPIOF_MEM_A3, 12) | \ - PIN_AFIO_AF(GPIOF_MEM_A4, 12) | \ - PIN_AFIO_AF(GPIOF_MEM_A5, 12) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0) | \ - PIN_AFIO_AF(GPIOF_PIN7, 0)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ - PIN_AFIO_AF(GPIOF_PIN9, 0) | \ - PIN_AFIO_AF(GPIOF_PIN10, 0) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0) | \ - PIN_AFIO_AF(GPIOF_MEM_A6, 12) | \ - PIN_AFIO_AF(GPIOF_MEM_A7, 12) | \ - PIN_AFIO_AF(GPIOF_MEM_A8, 12) | \ - PIN_AFIO_AF(GPIOF_MEM_A9, 12)) - -/* - * GPIOG setup: - */ -#define VAL_GPIOG_MODER (PIN_MODE_ALTERNATE(GPIOG_MEM_A10) | \ - PIN_MODE_ALTERNATE(GPIOG_MEM_A11) | \ - PIN_MODE_ALTERNATE(GPIOG_MEM_A12) | \ - PIN_MODE_ALTERNATE(GPIOG_MEM_A13) | \ - PIN_MODE_ALTERNATE(GPIOG_MEM_A14) | \ - PIN_MODE_ALTERNATE(GPIOG_MEM_A15) | \ - PIN_MODE_ALTERNATE(GPIOG_NAND_RB1) | \ - PIN_MODE_ALTERNATE(GPIOG_NAND_RB2) | \ - PIN_MODE_INPUT(GPIOG_PIN8) | \ - PIN_MODE_ALTERNATE(GPIOG_NAND_CE2) | \ - PIN_MODE_INPUT(GPIOG_PIN10) | \ - PIN_MODE_INPUT(GPIOG_PIN11) | \ - PIN_MODE_ALTERNATE(GPIOG_SRAM_CS1) | \ - PIN_MODE_INPUT(GPIOG_PIN13) | \ - PIN_MODE_INPUT(GPIOG_PIN14) | \ - PIN_MODE_INPUT(GPIOG_PIN15)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_MEM_A10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_MEM_A11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_MEM_A12) | \ - PIN_OTYPE_PUSHPULL(GPIOG_MEM_A13) | \ - PIN_OTYPE_PUSHPULL(GPIOG_MEM_A14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_MEM_A15) | \ - PIN_OTYPE_PUSHPULL(GPIOG_NAND_RB1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_NAND_RB2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOG_NAND_CE2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_SRAM_CS1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_MEM_A10) | \ - PIN_OSPEED_100M(GPIOG_MEM_A11) | \ - PIN_OSPEED_100M(GPIOG_MEM_A12) | \ - PIN_OSPEED_100M(GPIOG_MEM_A13) | \ - PIN_OSPEED_100M(GPIOG_MEM_A14) | \ - PIN_OSPEED_100M(GPIOG_MEM_A15) | \ - PIN_OSPEED_100M(GPIOG_NAND_RB1) | \ - PIN_OSPEED_100M(GPIOG_NAND_RB2) | \ - PIN_OSPEED_100M(GPIOG_PIN8) | \ - PIN_OSPEED_100M(GPIOG_NAND_CE2) | \ - PIN_OSPEED_100M(GPIOG_PIN10) | \ - PIN_OSPEED_100M(GPIOG_PIN11) | \ - PIN_OSPEED_100M(GPIOG_SRAM_CS1) | \ - PIN_OSPEED_100M(GPIOG_PIN13) | \ - PIN_OSPEED_100M(GPIOG_PIN14) | \ - PIN_OSPEED_100M(GPIOG_PIN15)) - -#if STM32_NAND_USE_EXT_INT -#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_FLOATING(pin)) -#else -#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_PULLUP(pin)) -#endif -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_MEM_A10) | \ - PIN_PUPDR_FLOATING(GPIOG_MEM_A11) | \ - PIN_PUPDR_FLOATING(GPIOG_MEM_A12) | \ - PIN_PUPDR_FLOATING(GPIOG_MEM_A13) | \ - PIN_PUPDR_FLOATING(GPIOG_MEM_A14) | \ - PIN_PUPDR_FLOATING(GPIOG_MEM_A15) | \ - NAND_RB1_PUPDR(GPIOG_NAND_RB1) | \ - PIN_PUPDR_FLOATING(GPIOG_NAND_RB2) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOG_SRAM_CS1) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOG_PIN15)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_MEM_A10) | \ - PIN_ODR_HIGH(GPIOG_MEM_A11) | \ - PIN_ODR_HIGH(GPIOG_MEM_A12) | \ - PIN_ODR_HIGH(GPIOG_MEM_A13) | \ - PIN_ODR_HIGH(GPIOG_MEM_A14) | \ - PIN_ODR_HIGH(GPIOG_MEM_A15) | \ - PIN_ODR_HIGH(GPIOG_NAND_RB1) | \ - PIN_ODR_HIGH(GPIOG_NAND_RB2) | \ - PIN_ODR_HIGH(GPIOG_PIN8) | \ - PIN_ODR_HIGH(GPIOG_NAND_CE2) | \ - PIN_ODR_HIGH(GPIOG_PIN10) | \ - PIN_ODR_HIGH(GPIOG_PIN11) | \ - PIN_ODR_HIGH(GPIOG_SRAM_CS1) | \ - PIN_ODR_HIGH(GPIOG_PIN13) | \ - PIN_ODR_HIGH(GPIOG_PIN14) | \ - PIN_ODR_HIGH(GPIOG_PIN15)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_MEM_A10, 12) | \ - PIN_AFIO_AF(GPIOG_MEM_A11, 12) | \ - PIN_AFIO_AF(GPIOG_MEM_A12, 12) | \ - PIN_AFIO_AF(GPIOG_MEM_A13, 12) | \ - PIN_AFIO_AF(GPIOG_MEM_A14, 12) | \ - PIN_AFIO_AF(GPIOG_MEM_A15, 12) | \ - PIN_AFIO_AF(GPIOG_NAND_RB1, 12) | \ - PIN_AFIO_AF(GPIOG_NAND_RB2, 12)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \ - PIN_AFIO_AF(GPIOG_NAND_CE2, 12) | \ - PIN_AFIO_AF(GPIOG_PIN10, 0) | \ - PIN_AFIO_AF(GPIOG_PIN11, 0) | \ - PIN_AFIO_AF(GPIOG_SRAM_CS1, 12) | \ - PIN_AFIO_AF(GPIOG_PIN13, 0) | \ - PIN_AFIO_AF(GPIOG_PIN14, 0) | \ - PIN_AFIO_AF(GPIOG_PIN15, 0)) - -/* - * GPIOH setup: - */ -#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ - PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOH_PIN2) | \ - PIN_MODE_INPUT(GPIOH_PIN3) | \ - PIN_MODE_INPUT(GPIOH_PIN4) | \ - PIN_MODE_INPUT(GPIOH_PIN5) | \ - PIN_MODE_INPUT(GPIOH_PIN6) | \ - PIN_MODE_ALTERNATE(GPIOH_I2C3_SCL) | \ - PIN_MODE_ALTERNATE(GPIOH_I2C3_SDA) | \ - PIN_MODE_INPUT(GPIOH_PIN9) | \ - PIN_MODE_INPUT(GPIOH_PIN10) | \ - PIN_MODE_INPUT(GPIOH_PIN11) | \ - PIN_MODE_INPUT(GPIOH_PIN12) | \ - PIN_MODE_INPUT(GPIOH_PIN13) | \ - PIN_MODE_INPUT(GPIOH_PIN14) | \ - PIN_MODE_INPUT(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ - PIN_OTYPE_OPENDRAIN(GPIOH_I2C3_SCL) | \ - PIN_OTYPE_OPENDRAIN(GPIOH_I2C3_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \ - PIN_OSPEED_100M(GPIOH_OSC_OUT) | \ - PIN_OSPEED_100M(GPIOH_PIN2) | \ - PIN_OSPEED_100M(GPIOH_PIN3) | \ - PIN_OSPEED_100M(GPIOH_PIN4) | \ - PIN_OSPEED_100M(GPIOH_PIN5) | \ - PIN_OSPEED_100M(GPIOH_PIN6) | \ - PIN_OSPEED_2M(GPIOH_I2C3_SCL) | \ - PIN_OSPEED_2M(GPIOH_I2C3_SDA) | \ - PIN_OSPEED_100M(GPIOH_PIN9) | \ - PIN_OSPEED_100M(GPIOH_PIN10) | \ - PIN_OSPEED_100M(GPIOH_PIN11) | \ - PIN_OSPEED_100M(GPIOH_PIN12) | \ - PIN_OSPEED_100M(GPIOH_PIN13) | \ - PIN_OSPEED_100M(GPIOH_PIN14) | \ - PIN_OSPEED_100M(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOH_I2C3_SCL) | \ - PIN_PUPDR_FLOATING(GPIOH_I2C3_SDA) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_PIN5) | \ - PIN_ODR_HIGH(GPIOH_PIN6) | \ - PIN_ODR_HIGH(GPIOH_I2C3_SCL) | \ - PIN_ODR_HIGH(GPIOH_I2C3_SDA) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0) | \ - PIN_AFIO_AF(GPIOH_PIN5, 0) | \ - PIN_AFIO_AF(GPIOH_PIN6, 0) | \ - PIN_AFIO_AF(GPIOH_I2C3_SCL, 4)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_I2C3_SDA, 4) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0)) - -/* - * GPIOI setup: - */ -#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ - PIN_MODE_INPUT(GPIOI_PIN1) | \ - PIN_MODE_INPUT(GPIOI_PIN2) | \ - PIN_MODE_INPUT(GPIOI_PIN3) | \ - PIN_MODE_INPUT(GPIOI_PIN4) | \ - PIN_MODE_INPUT(GPIOI_PIN5) | \ - PIN_MODE_INPUT(GPIOI_PIN6) | \ - PIN_MODE_INPUT(GPIOI_PIN7) | \ - PIN_MODE_INPUT(GPIOI_PIN8) | \ - PIN_MODE_INPUT(GPIOI_PIN9) | \ - PIN_MODE_OUTPUT(GPIOI_LED_R) | \ - PIN_MODE_OUTPUT(GPIOI_LED_G) | \ - PIN_MODE_INPUT(GPIOI_PIN12) | \ - PIN_MODE_INPUT(GPIOI_PIN13) | \ - PIN_MODE_INPUT(GPIOI_PIN14) | \ - PIN_MODE_INPUT(GPIOI_PIN15)) -#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOI_LED_R) | \ - PIN_OTYPE_PUSHPULL(GPIOI_LED_G) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) -#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \ - PIN_OSPEED_100M(GPIOI_PIN1) | \ - PIN_OSPEED_100M(GPIOI_PIN2) | \ - PIN_OSPEED_100M(GPIOI_PIN3) | \ - PIN_OSPEED_100M(GPIOI_PIN4) | \ - PIN_OSPEED_100M(GPIOI_PIN5) | \ - PIN_OSPEED_100M(GPIOI_PIN6) | \ - PIN_OSPEED_100M(GPIOI_PIN7) | \ - PIN_OSPEED_100M(GPIOI_PIN8) | \ - PIN_OSPEED_100M(GPIOI_PIN9) | \ - PIN_OSPEED_100M(GPIOI_LED_R) | \ - PIN_OSPEED_100M(GPIOI_LED_G) | \ - PIN_OSPEED_100M(GPIOI_PIN12) | \ - PIN_OSPEED_100M(GPIOI_PIN13) | \ - PIN_OSPEED_100M(GPIOI_PIN14) | \ - PIN_OSPEED_100M(GPIOI_PIN15)) -#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN1) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOI_LED_R) | \ - PIN_PUPDR_FLOATING(GPIOI_LED_G) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN12) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN14) | \ - PIN_PUPDR_FLOATING(GPIOI_PIN15)) -#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ - PIN_ODR_HIGH(GPIOI_PIN1) | \ - PIN_ODR_HIGH(GPIOI_PIN2) | \ - PIN_ODR_HIGH(GPIOI_PIN3) | \ - PIN_ODR_HIGH(GPIOI_PIN4) | \ - PIN_ODR_HIGH(GPIOI_PIN5) | \ - PIN_ODR_HIGH(GPIOI_PIN6) | \ - PIN_ODR_HIGH(GPIOI_PIN7) | \ - PIN_ODR_HIGH(GPIOI_PIN8) | \ - PIN_ODR_HIGH(GPIOI_PIN9) | \ - PIN_ODR_LOW(GPIOI_LED_R) | \ - PIN_ODR_LOW(GPIOI_LED_G) | \ - PIN_ODR_HIGH(GPIOI_PIN12) | \ - PIN_ODR_HIGH(GPIOI_PIN13) | \ - PIN_ODR_HIGH(GPIOI_PIN14) | \ - PIN_ODR_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \ - PIN_AFIO_AF(GPIOI_PIN1, 0) | \ - PIN_AFIO_AF(GPIOI_PIN2, 0) | \ - PIN_AFIO_AF(GPIOI_PIN3, 0) | \ - PIN_AFIO_AF(GPIOI_PIN4, 0) | \ - PIN_AFIO_AF(GPIOI_PIN5, 0) | \ - PIN_AFIO_AF(GPIOI_PIN6, 0) | \ - PIN_AFIO_AF(GPIOI_PIN7, 0)) -#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ - PIN_AFIO_AF(GPIOI_PIN9, 0) | \ - PIN_AFIO_AF(GPIOI_LED_R, 0) | \ - PIN_AFIO_AF(GPIOI_LED_G, 0) | \ - PIN_AFIO_AF(GPIOI_PIN12, 0) | \ - PIN_AFIO_AF(GPIOI_PIN13, 0) | \ - PIN_AFIO_AF(GPIOI_PIN14, 0) | \ - PIN_AFIO_AF(GPIOI_PIN15, 0)) - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_16.1.5/community/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk deleted file mode 100644 index 8c28257..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c - -# Required include directories -BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2 diff --git a/ChibiOS_16.1.5/community/os/hal/boards/NRF51-DK/board.c b/ChibiOS_16.1.5/community/os/hal/boards/NRF51-DK/board.c deleted file mode 100644 index c5237d7..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/NRF51-DK/board.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - Copyright (C) 2015 Fabio Utzig - 2016 Stéphane D'Alu / Bruno Remond - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/* RAM Banks - * (Values are defined in Nordic gcc_startup_nrf51.s) - */ -#define NRF_POWER_RAMON_ADDRESS 0x40000524 -#define NRF_POWER_RAMONB_ADDRESS 0x40000554 -#define NRF_POWER_RAMONx_RAMxON_ONMODE_Msk 0x3 - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. - */ -const PALConfig pal_default_config = -{ - .pads = { - PAL_MODE_UNCONNECTED, /* P0.0 */ - PAL_MODE_UNCONNECTED, /* P0.1 */ - PAL_MODE_UNCONNECTED, /* P0.2 */ - PAL_MODE_UNCONNECTED, /* P0.3 */ - PAL_MODE_UNCONNECTED, /* P0.4 */ - PAL_MODE_UNCONNECTED, /* P0.5 */ - PAL_MODE_UNCONNECTED, /* P0.6 */ - PAL_MODE_OUTPUT_OPENDRAIN, /* P0.7 : SCL */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.8 : UART_RTS */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.9 : UART_TX */ - PAL_MODE_INPUT_PULLUP, /* P0.10: UART_CTS */ - PAL_MODE_INPUT_PULLUP, /* P0.11: UART_RX */ - PAL_MODE_UNCONNECTED, /* P0.12 */ - PAL_MODE_UNCONNECTED, /* P0.13 */ - PAL_MODE_UNCONNECTED, /* P0.14 */ - PAL_MODE_UNCONNECTED, /* P0.15 */ - PAL_MODE_UNCONNECTED, /* P0.16 */ - PAL_MODE_INPUT_PULLUP, /* P0.17: BTN1 */ - PAL_MODE_INPUT_PULLUP, /* P0.18: BTN2 */ - PAL_MODE_INPUT_PULLUP, /* P0.19: BTN3 */ - PAL_MODE_INPUT_PULLUP, /* P0.20: BTN4 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.21: LED1 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.22: LED2 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.23: LED3 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.24: LED4 | SPI_SEL */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.25: SPI_MOSI */ - PAL_MODE_UNCONNECTED, /* P0.26: XTAL (32MHz) */ - PAL_MODE_UNCONNECTED, /* P0.27: XTAL (32MHz) */ - PAL_MODE_INPUT_PULLUP, /* P0.28: SPI_MISO */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.29: SPI_SCK */ - PAL_MODE_OUTPUT_OPENDRAIN, /* P0.30: SDA */ - PAL_MODE_UNCONNECTED, /* P0.31 */ - }, -}; -#endif - -/** - * @brief Early initialization code. - * @details This initialization is performed just after reset before BSS and - * DATA segments initialization. - */ -void __early_init(void) -{ - /* Make sure ALL RAM banks are powered on */ - *(uint32_t *)NRF_POWER_RAMON_ADDRESS |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk; - *(uint32_t *)NRF_POWER_RAMONB_ADDRESS |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk; -} - -/** - * @brief Late initialization code. - * @note This initialization is performed after BSS and DATA segments - * initialization and before invoking the main() function. - */ -void boardInit(void) -{ -} diff --git a/ChibiOS_16.1.5/community/os/hal/boards/NRF51-DK/board.h b/ChibiOS_16.1.5/community/os/hal/boards/NRF51-DK/board.h deleted file mode 100644 index 67e1724..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/NRF51-DK/board.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - Copyright (C) 2015 Fabio Utzig - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* Board identifier. */ -#define BOARD_NRF51_DK -#define BOARD_NAME "nRF51 DK" - -/* Board oscillators-related settings. */ -#define NRF51_XTAL_VALUE 16000000 -#define NRF51_LFCLK_SOURCE 1 - -/* GPIO pins. */ -#define BTN1 17 -#define BTN2 18 -#define BTN3 19 -#define BTN4 20 -#define LED1 21 -#define LED2 22 -#define LED3 23 -#define LED4 24 -#define UART_RTS 8 -#define UART_TX 9 -#define UART_CTS 10 -#define UART_RX 11 -#define SPI_SCK 29 -#define SPI_MOSI 25 -#define SPI_MISO 28 -#define SPI_SS 24 -#define I2C_SCL 7 -#define I2C_SDA 30 -#define AIN0 26 -#define AIN1 27 -#define AIN2 1 -#define AIN3 2 -#define AIN4 3 -#define AIN5 4 -#define AIN6 5 -#define AIN7 6 -#define AREF0 0 -#define AREF1 6 - -/* - * IO pins assignments. - */ -#define IOPORT1_BTN1 17U -#define IOPORT1_BTN2 18U -#define IOPORT1_BTN3 19U -#define IOPORT1_BTN4 20U -#define IOPORT1_LED1 21U -#define IOPORT1_LED2 22U -#define IOPORT1_LED3 23U -#define IOPORT1_LED4 24U -#define IOPORT1_UART_RTS 8U -#define IOPORT1_UART_TX 9U -#define IOPORT1_UART_CTS 10U -#define IOPORT1_UART_RX 11U -#define IOPORT1_SPI_SCK 29U -#define IOPORT1_SPI_MOSI 25U -#define IOPORT1_SPI_MISO 28U -#define IOPORT1_SPI_SS 24U -#define IOPORT1_I2C_SCL 7U -#define IOPORT1_I2C_SDA 30U -#define IOPORT1_A0 1U -#define IOPORT1_A1 2U -#define IOPORT1_A2 3U -#define IOPORT1_A3 4U -#define IOPORT1_A4 5U -#define IOPORT1_A5 6U -#define IOPORT1_AIN0 26U -#define IOPORT1_AIN1 27U -#define IOPORT1_AIN2 1U -#define IOPORT1_AIN3 2U -#define IOPORT1_AIN4 3U -#define IOPORT1_AIN5 4U -#define IOPORT1_AIN6 5U -#define IOPORT1_AIN7 6U -#define IOPORT1_AREF0 0U -#define IOPORT1_AREF1 6U - -/* - * IO lines assignments. - */ -#define LINE_BTN1 PAL_LINE(IOPORT1, IOPORT1_BTN1) -#define LINE_BTN2 PAL_LINE(IOPORT1, IOPORT1_BTN2) -#define LINE_BTN3 PAL_LINE(IOPORT1, IOPORT1_BTN3) -#define LINE_BTN4 PAL_LINE(IOPORT1, IOPORT1_BTN4) -#define LINE_LED1 PAL_LINE(IOPORT1, IOPORT1_LED1) -#define LINE_LED2 PAL_LINE(IOPORT1, IOPORT1_LED2) -#define LINE_LED3 PAL_LINE(IOPORT1, IOPORT1_LED3) -#define LINE_LED4 PAL_LINE(IOPORT1, IOPORT1_LED4) -#define LINE_UART_RTS PAL_LINE(IOPORT1, IOPORT1_UART_RTS) -#define LINE_UART_TX PAL_LINE(IOPORT1, IOPORT1_UART_TX) -#define LINE_UART_CTS PAL_LINE(IOPORT1, IOPORT1_UART_CTS) -#define LINE_UART_RX PAL_LINE(IOPORT1, IOPORT1_UART_RX) -#define LINE_SPI_SCK PAL_LINE(IOPORT1, IOPORT1_SPI_SCK) -#define LINE_SPI_MOSI PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI) -#define LINE_SPI_MISO PAL_LINE(IOPORT1, IOPORT1_SPI_MISO) -#define LINE_SPI_SS PAL_LINE(IOPORT1, IOPORT1_SPI_SS) -#define LINE_I2C_SCL PAL_LINE(IOPORT1, IOPORT1_I2C_SCL) -#define LINE_I2C_SDA PAL_LINE(IOPORT1, IOPORT1_I2C_SDA) -#define LINE_A0 PAL_LINE(IOPORT1, IOPORT1_A0) -#define LINE_A1 PAL_LINE(IOPORT1, IOPORT1_A1) -#define LINE_A2 PAL_LINE(IOPORT1, IOPORT1_A2) -#define LINE_A3 PAL_LINE(IOPORT1, IOPORT1_A3) -#define LINE_A4 PAL_LINE(IOPORT1, IOPORT1_A4) -#define LINE_A5 PAL_LINE(IOPORT1, IOPORT1_A5) -#define LINE_AIN0 PAL_LINE(IOPORT1, IOPORT1_AIN0) -#define LINE_AIN1 PAL_LINE(IOPORT1, IOPORT1_AIN1) -#define LINE_AIN2 PAL_LINE(IOPORT1, IOPORT1_AIN2) -#define LINE_AIN3 PAL_LINE(IOPORT1, IOPORT1_AIN3) -#define LINE_AIN4 PAL_LINE(IOPORT1, IOPORT1_AIN4) -#define LINE_AIN5 PAL_LINE(IOPORT1, IOPORT1_AIN5) -#define LINE_AIN6 PAL_LINE(IOPORT1, IOPORT1_AIN6) -#define LINE_AIN7 PAL_LINE(IOPORT1, IOPORT1_AIN7) -#define LINE_AREF0 PAL_LINE(IOPORT1, IOPORT1_AREF0) -#define LINE_AREF1 PAL_LINE(IOPORT1, IOPORT1_AREF1) - - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_16.1.5/community/os/hal/boards/NRF51-DK/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/NRF51-DK/board.mk deleted file mode 100644 index 9619bd4..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/NRF51-DK/board.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF51-DK/board.c - -# Required include directories -BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF51-DK - -# Flash -JLINK_DEVICE = nrf51422 -JLINK_PRE_FLASH = w4 4001e504 1 -JLINK_ERASE_ALL = w4 4001e504 2\nw4 4001e50c 1\nsleep 100 - diff --git a/ChibiOS_16.1.5/community/os/hal/boards/OSHCHIP_V1.0/board.c b/ChibiOS_16.1.5/community/os/hal/boards/OSHCHIP_V1.0/board.c deleted file mode 100644 index 85e4486..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/OSHCHIP_V1.0/board.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - Copyright (C) 2016 flabbergast - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. - */ -const PALConfig pal_default_config = -{ - .pads = { - PAL_MODE_OUTPUT_PUSHPULL, /* P0.0: PIN11 (AREF0) */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.1: PIN9 (AIN2) */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.2: PIN10 (AIN3) */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.3: LED_BLUE */ - PAL_MODE_UNCONNECTED, /* P0.4 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.5: LED_GREEN */ - PAL_MODE_UNCONNECTED, /* P0.6 */ - PAL_MODE_UNCONNECTED, /* P0.7 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.8: LED_RED */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.9: PIN7 */ - PAL_MODE_UNCONNECTED, /* P0.10 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.11: PIN6 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.12: PIN5 */ - PAL_MODE_UNCONNECTED, /* P0.13 */ - PAL_MODE_UNCONNECTED, /* P0.14 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.15: PIN4 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.16: PIN3 */ - PAL_MODE_UNCONNECTED, /* P0.17 */ - PAL_MODE_INPUT_PULLUP, /* P0.18: PIN2 (RX) */ - PAL_MODE_UNCONNECTED, /* P0.19 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.20: PIN1 (TX) */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.21: PIN15 */ - PAL_MODE_UNCONNECTED, /* P0.22 */ - PAL_MODE_UNCONNECTED, /* P0.23 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.24: PIN14 */ - PAL_MODE_UNCONNECTED, /* P0.25 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.26: PIN13 (LFXTL) (AIN0) */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.27: PIN12 (LFXTL) (AIN1) */ - PAL_MODE_UNCONNECTED, /* P0.28 */ - PAL_MODE_UNCONNECTED, /* P0.29 */ - PAL_MODE_UNCONNECTED, /* P0.30 */ - PAL_MODE_UNCONNECTED, /* P0.31 */ - }, -}; -#endif - -/** - * @brief Early initialization code. - * @details This initialization is performed just after reset before BSS and - * DATA segments initialization. - */ -void __early_init(void) -{ -} - -/** - * @brief Late initialization code. - * @note This initialization is performed after BSS and DATA segments - * initialization and before invoking the main() function. - */ -void boardInit(void) -{ -} diff --git a/ChibiOS_16.1.5/community/os/hal/boards/OSHCHIP_V1.0/board.h b/ChibiOS_16.1.5/community/os/hal/boards/OSHCHIP_V1.0/board.h deleted file mode 100644 index e3bbb0b..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/OSHCHIP_V1.0/board.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - Copyright (C) 2016 flabbergast - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* Board identifier. */ -#define BOARD_OSHCHIP_V10 -#define BOARD_NAME "OSHChip_V1.0" - -/* Board oscillators-related settings. */ -#define NRF51_XTAL_VALUE 16000000 - -/* Non-header GPIO pins. */ -#define LED_RED 8 -#define LED_GREEN 5 -#define LED_BLUE 3 - -/* Common peripheral GPIO pins. */ -#define UART_TX 20 -#define UART_RX 18 - -/* GPIO on DIP pins. */ -#define OSHCHIP_PIN1 20 -#define OSHCHIP_PIN2 18 -#define OSHCHIP_PIN3 16 -#define OSHCHIP_PIN4 15 -#define OSHCHIP_PIN5 12 -#define OSHCHIP_PIN6 11 -#define OSHCHIP_PIN7 9 -/* Pin 8 is GND */ -#define OSHCHIP_PIN9 1 -#define OSHCHIP_PIN10 2 -#define OSHCHIP_PIN11 0 -#define OSHCHIP_PIN12 27 -#define OSHCHIP_PIN13 26 -#define OSHCHIP_PIN14 24 -#define OSHCHIP_PIN15 21 -/* Pin 16 is VCC */ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_16.1.5/community/os/hal/boards/OSHCHIP_V1.0/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/OSHCHIP_V1.0/board.mk deleted file mode 100644 index 08afdbd..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/OSHCHIP_V1.0/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/OSHCHIP_V1.0/board.c - -# Required include directories -BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/OSHCHIP_V1.0 diff --git a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3/board.c b/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3/board.c deleted file mode 100644 index f89c7e5..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3/board.c +++ /dev/null @@ -1,183 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-const PALConfig pal_default_config =
-{
- .ports = {
- {
- /*
- * PORTA setup.
- *
- * PTA4 - PIN33
- * PTA5 - PIN24
- * PTA12 - PIN3
- * PTA13 - PIN4
- *
- * PTA18/19 crystal
- * PTA0/3 SWD
- */
- .port = IOPORT1,
- .pads = {
- PAL_MODE_ALTERNATIVE_7, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_ALTERNATIVE_7, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_INPUT_ANALOG, PAL_MODE_INPUT_ANALOG, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- {
- /*
- * PORTB setup.
- *
- * PTB0 - PIN16
- * PTB1 - PIN17
- * PTB2 - PIN19
- * PTB3 - PIN18
- * PTB16 - PIN0 - UART0_TX
- * PTB17 - PIN1 - UART0_RX
- * PTB18 - PIN32
- * PTB19 - PIN25
- */
- .port = IOPORT2,
- .pads = {
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_3, PAL_MODE_ALTERNATIVE_3,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- {
- /*
- * PORTC setup.
- *
- * PTC0 - PIN15
- * PTC1 - PIN22
- * PTC2 - PIN23
- * PTC3 - PIN9
- * PTC4 - PIN10
- * PTC5 - PIN13
- * PTC6 - PIN11
- * PTC7 - PIN12
- * PTC8 - PIN28
- * PTC9 - PIN27
- * PTC10 - PIN29
- * PTC11 - PIN30
- */
- .port = IOPORT3,
- .pads = {
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- {
- /*
- * PORTD setup.
- *
- * PTD0 - PIN2
- * PTD1 - PIN14
- * PTD2 - PIN7
- * PTD3 - PIN8
- * PTD4 - PIN6
- * PTD5 - PIN20
- * PTD6 - PIN21
- * PTD7 - PIN5
- */
- .port = IOPORT4,
- .pads = {
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- {
- /*
- * PORTE setup.
- *
- * PTE0 - PIN31
- * PTE1 - PIN26
- */
- .port = IOPORT5,
- .pads = {
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- },
-};
-#endif
-
-/**
- * @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
- */
-void __early_init(void) {
-
- k20x_clock_init();
-}
-
-/**
- * @brief Board-specific initialization code.
- * @todo Add your board-specific code, if any.
- */
-void boardInit(void) {
-}
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3/board.h b/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3/board.h deleted file mode 100644 index f3e7383..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3/board.h +++ /dev/null @@ -1,295 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for the PJRC Teensy 3.0 board.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_PJRC_TEENSY_3
-#define BOARD_NAME "PJRC Teensy 3.0"
-
-/* External 16 MHz crystal */
-#define KINETIS_XTAL_FREQUENCY 16000000UL
-
-/* Use internal capacitors for the crystal */
-#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P
-
-/*
- * MCU type
- */
-#define K20x5
-
-/*
- * IO pins assignments.
- */
-#define PORTA_PIN0 0
-#define PORTA_PIN1 1
-#define PORTA_PIN2 2
-#define PORTA_PIN3 3
-#define TEENSY_PIN33 4
-#define TEENSY_PIN24 5
-#define PORTA_PIN6 6
-#define PORTA_PIN7 7
-#define PORTA_PIN8 8
-#define PORTA_PIN9 9
-#define PORTA_PIN10 10
-#define PORTA_PIN11 11
-#define TEENSY_PIN3 12
-#define TEENSY_PIN4 13
-#define PORTA_PIN14 14
-#define PORTA_PIN15 15
-#define PORTA_PIN16 16
-#define PORTA_PIN17 17
-#define PORTA_PIN18 18
-#define PORTA_PIN19 19
-#define PORTA_PIN20 20
-#define PORTA_PIN21 21
-#define PORTA_PIN22 22
-#define PORTA_PIN23 23
-#define PORTA_PIN24 24
-#define PORTA_PIN25 25
-#define PORTA_PIN26 26
-#define PORTA_PIN27 27
-#define PORTA_PIN28 28
-#define PORTA_PIN29 29
-#define PORTA_PIN30 30
-#define PORTA_PIN31 31
-
-#define TEENSY_PIN3_IOPORT IOPORT1
-#define TEENSY_PIN4_IOPORT IOPORT1
-#define TEENSY_PIN24_IOPORT IOPORT1
-#define TEENSY_PIN33_IOPORT IOPORT1
-
-#define TEENSY_PIN16 0
-#define TEENSY_PIN17 1
-#define TEENSY_PIN19 2
-#define TEENSY_PIN18 3
-#define PORTB_PIN4 4
-#define PORTB_PIN5 5
-#define PORTB_PIN6 6
-#define PORTB_PIN7 7
-#define PORTB_PIN8 8
-#define PORTB_PIN9 9
-#define PORTB_PIN10 10
-#define PORTB_PIN11 11
-#define PORTB_PIN12 12
-#define PORTB_PIN13 13
-#define PORTB_PIN14 14
-#define PORTB_PIN15 15
-#define TEENSY_PIN0 16
-#define TEENSY_PIN1 17
-#define TEENSY_PIN32 18
-#define TEENSY_PIN25 19
-#define PORTB_PIN20 20
-#define PORTB_PIN21 21
-#define PORTB_PIN22 22
-#define PORTB_PIN23 23
-#define PORTB_PIN24 24
-#define PORTB_PIN25 25
-#define PORTB_PIN26 26
-#define PORTB_PIN27 27
-#define PORTB_PIN28 28
-#define PORTB_PIN29 29
-#define PORTB_PIN30 30
-#define PORTB_PIN31 31
-
-#define TEENSY_PIN0_IOPORT IOPORT2
-#define TEENSY_PIN1_IOPORT IOPORT2
-#define TEENSY_PIN16_IOPORT IOPORT2
-#define TEENSY_PIN17_IOPORT IOPORT2
-#define TEENSY_PIN18_IOPORT IOPORT2
-#define TEENSY_PIN19_IOPORT IOPORT2
-#define TEENSY_PIN25_IOPORT IOPORT2
-#define TEENSY_PIN32_IOPORT IOPORT2
-
-#define TEENSY_PIN15 0
-#define TEENSY_PIN22 1
-#define TEENSY_PIN23 2
-#define TEENSY_PIN9 3
-#define TEENSY_PIN10 4
-#define TEENSY_PIN13 5
-#define TEENSY_PIN11 6
-#define TEENSY_PIN12 7
-#define TEENSY_PIN28 8
-#define TEENSY_PIN27 9
-#define TEENSY_PIN29 10
-#define TEENSY_PIN30 11
-#define PORTC_PIN12 12
-#define PORTC_PIN13 13
-#define PORTC_PIN14 14
-#define PORTC_PIN15 15
-#define PORTC_PIN16 16
-#define PORTC_PIN17 17
-#define PORTC_PIN18 18
-#define PORTC_PIN19 19
-#define PORTC_PIN20 20
-#define PORTC_PIN21 21
-#define PORTC_PIN22 22
-#define PORTC_PIN23 23
-#define PORTC_PIN24 24
-#define PORTC_PIN25 25
-#define PORTC_PIN26 26
-#define PORTC_PIN27 27
-#define PORTC_PIN28 28
-#define PORTC_PIN29 29
-#define PORTC_PIN30 30
-#define PORTC_PIN31 31
-
-#define TEENSY_PIN9_IOPORT IOPORT3
-#define TEENSY_PIN10_IOPORT IOPORT3
-#define TEENSY_PIN11_IOPORT IOPORT3
-#define TEENSY_PIN12_IOPORT IOPORT3
-#define TEENSY_PIN13_IOPORT IOPORT3
-#define TEENSY_PIN15_IOPORT IOPORT3
-#define TEENSY_PIN22_IOPORT IOPORT3
-#define TEENSY_PIN23_IOPORT IOPORT3
-#define TEENSY_PIN27_IOPORT IOPORT3
-#define TEENSY_PIN28_IOPORT IOPORT3
-#define TEENSY_PIN29_IOPORT IOPORT3
-#define TEENSY_PIN30_IOPORT IOPORT3
-
-#define TEENSY_PIN2 0
-#define TEENSY_PIN14 1
-#define TEENSY_PIN7 2
-#define TEENSY_PIN8 3
-#define TEENSY_PIN6 4
-#define TEENSY_PIN20 5
-#define TEENSY_PIN21 6
-#define TEENSY_PIN5 7
-#define PORTD_PIN8 8
-#define PORTD_PIN9 9
-#define PORTD_PIN10 10
-#define PORTD_PIN11 11
-#define PORTD_PIN12 12
-#define PORTD_PIN13 13
-#define PORTD_PIN14 14
-#define PORTD_PIN15 15
-#define PORTD_PIN16 16
-#define PORTD_PIN17 17
-#define PORTD_PIN18 18
-#define PORTD_PIN19 19
-#define PORTD_PIN20 20
-#define PORTD_PIN21 21
-#define PORTD_PIN22 22
-#define PORTD_PIN23 23
-#define PORTD_PIN24 24
-#define PORTD_PIN25 25
-#define PORTD_PIN26 26
-#define PORTD_PIN27 27
-#define PORTD_PIN28 28
-#define PORTD_PIN29 29
-#define PORTD_PIN30 30
-#define PORTD_PIN31 31
-
-#define TEENSY_PIN2_IOPORT IOPORT4
-#define TEENSY_PIN5_IOPORT IOPORT4
-#define TEENSY_PIN6_IOPORT IOPORT4
-#define TEENSY_PIN7_IOPORT IOPORT4
-#define TEENSY_PIN8_IOPORT IOPORT4
-#define TEENSY_PIN14_IOPORT IOPORT4
-#define TEENSY_PIN20_IOPORT IOPORT4
-#define TEENSY_PIN21_IOPORT IOPORT4
-
-#define TEENSY_PIN31 0
-#define TEENSY_PIN26 1
-#define PORTE_PIN2 2
-#define PORTE_PIN3 3
-#define PORTE_PIN4 4
-#define PORTE_PIN5 5
-#define PORTE_PIN6 6
-#define PORTE_PIN7 7
-#define PORTE_PIN8 8
-#define PORTE_PIN9 9
-#define PORTE_PIN10 10
-#define PORTE_PIN11 11
-#define PORTE_PIN12 12
-#define PORTE_PIN13 13
-#define PORTE_PIN14 14
-#define PORTE_PIN15 15
-#define PORTE_PIN16 16
-#define PORTE_PIN17 17
-#define PORTE_PIN18 18
-#define PORTE_PIN19 19
-#define PORTE_PIN20 20
-#define PORTE_PIN21 21
-#define PORTE_PIN22 22
-#define PORTE_PIN23 23
-#define PORTE_PIN24 24
-#define PORTE_PIN25 25
-#define PORTE_PIN26 26
-#define PORTE_PIN27 27
-#define PORTE_PIN28 28
-#define PORTE_PIN29 29
-#define PORTE_PIN30 30
-#define PORTE_PIN31 31
-
-#define TEENSY_PIN26_IOPORT IOPORT5
-#define TEENSY_PIN31_IOPORT IOPORT5
-
-#define LINE_PIN1 PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
-#define LINE_PIN2 PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
-#define LINE_PIN3 PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
-#define LINE_PIN4 PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
-#define LINE_PIN5 PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
-#define LINE_PIN6 PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
-#define LINE_PIN7 PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
-#define LINE_PIN8 PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
-#define LINE_PIN9 PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
-#define LINE_PIN10 PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
-#define LINE_PIN11 PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
-#define LINE_PIN12 PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
-#define LINE_PIN13 PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
-#define LINE_PIN14 PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
-#define LINE_PIN15 PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
-#define LINE_PIN16 PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
-#define LINE_PIN17 PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
-#define LINE_PIN18 PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
-#define LINE_PIN19 PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
-#define LINE_PIN20 PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
-#define LINE_PIN21 PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
-#define LINE_PIN22 PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
-#define LINE_PIN23 PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
-#define LINE_PIN24 PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
-#define LINE_PIN25 PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
-#define LINE_PIN25 PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
-#define LINE_PIN26 PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26)
-#define LINE_PIN27 PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27)
-#define LINE_PIN28 PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28)
-#define LINE_PIN29 PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29)
-#define LINE_PIN30 PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30)
-#define LINE_PIN31 PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31)
-#define LINE_PIN32 PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32)
-#define LINE_PIN33 PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33)
-
-#define LINE_LED LINE_PIN13
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3/board.mk deleted file mode 100644 index b9dcdc8..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files.
-BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3/board.c
-
-# Required include directories
-BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3_1/board.c b/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3_1/board.c deleted file mode 100644 index d60a89c..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3_1/board.c +++ /dev/null @@ -1,183 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-const PALConfig pal_default_config =
-{
- .ports = {
- {
- /*
- * PORTA setup.
- *
- * PTA4 - PIN33
- * PTA5 - PIN24
- * PTA12 - PIN3
- * PTA13 - PIN4
- *
- * PTA18/19 crystal
- * PTA0/3 SWD
- */
- .port = IOPORT1,
- .pads = {
- PAL_MODE_ALTERNATIVE_7, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_ALTERNATIVE_7, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_INPUT_ANALOG, PAL_MODE_INPUT_ANALOG, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- {
- /*
- * PORTB setup.
- *
- * PTB0 - PIN16
- * PTB1 - PIN17
- * PTB2 - PIN19
- * PTB3 - PIN18
- * PTB16 - PIN0 - UART0_TX
- * PTB17 - PIN1 - UART0_RX
- * PTB18 - PIN32
- * PTB19 - PIN25
- */
- .port = IOPORT2,
- .pads = {
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_3, PAL_MODE_ALTERNATIVE_3,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- {
- /*
- * PORTC setup.
- *
- * PTC0 - PIN15
- * PTC1 - PIN22
- * PTC2 - PIN23
- * PTC3 - PIN9
- * PTC4 - PIN10
- * PTC5 - PIN13
- * PTC6 - PIN11
- * PTC7 - PIN12
- * PTC8 - PIN28
- * PTC9 - PIN27
- * PTC10 - PIN29
- * PTC11 - PIN30
- */
- .port = IOPORT3,
- .pads = {
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- {
- /*
- * PORTD setup.
- *
- * PTD0 - PIN2
- * PTD1 - PIN14
- * PTD2 - PIN7
- * PTD3 - PIN8
- * PTD4 - PIN6
- * PTD5 - PIN20
- * PTD6 - PIN21
- * PTD7 - PIN5
- */
- .port = IOPORT4,
- .pads = {
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- {
- /*
- * PORTE setup.
- *
- * PTE0 - PIN31
- * PTE1 - PIN26
- */
- .port = IOPORT5,
- .pads = {
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- },
-};
-#endif
-
-/**
- * @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
- */
-void __early_init(void) {
-
- k20x_clock_init();
-}
-
-/**
- * @brief Board-specific initialization code.
- * @todo Add your board-specific code, if any.
- */
-void boardInit(void) {
-}
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3_1/board.h b/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3_1/board.h deleted file mode 100644 index 76a52b7..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3_1/board.h +++ /dev/null @@ -1,295 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for the PJRC Teensy 3.1 board.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_PJRC_TEENSY_3_1
-#define BOARD_NAME "PJRC Teensy 3.1"
-
-/* External 16 MHz crystal */
-#define KINETIS_XTAL_FREQUENCY 16000000UL
-
-/* Use internal capacitors for the crystal */
-#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P
-
-/*
- * MCU type
- */
-#define K20x7
-
-/*
- * IO pins assignments.
- */
-#define PORTA_PIN0 0
-#define PORTA_PIN1 1
-#define PORTA_PIN2 2
-#define PORTA_PIN3 3
-#define TEENSY_PIN33 4
-#define TEENSY_PIN24 5
-#define PORTA_PIN6 6
-#define PORTA_PIN7 7
-#define PORTA_PIN8 8
-#define PORTA_PIN9 9
-#define PORTA_PIN10 10
-#define PORTA_PIN11 11
-#define TEENSY_PIN3 12
-#define TEENSY_PIN4 13
-#define PORTA_PIN14 14
-#define PORTA_PIN15 15
-#define PORTA_PIN16 16
-#define PORTA_PIN17 17
-#define PORTA_PIN18 18
-#define PORTA_PIN19 19
-#define PORTA_PIN20 20
-#define PORTA_PIN21 21
-#define PORTA_PIN22 22
-#define PORTA_PIN23 23
-#define PORTA_PIN24 24
-#define PORTA_PIN25 25
-#define PORTA_PIN26 26
-#define PORTA_PIN27 27
-#define PORTA_PIN28 28
-#define PORTA_PIN29 29
-#define PORTA_PIN30 30
-#define PORTA_PIN31 31
-
-#define TEENSY_PIN3_IOPORT IOPORT1
-#define TEENSY_PIN4_IOPORT IOPORT1
-#define TEENSY_PIN24_IOPORT IOPORT1
-#define TEENSY_PIN33_IOPORT IOPORT1
-
-#define TEENSY_PIN16 0
-#define TEENSY_PIN17 1
-#define TEENSY_PIN19 2
-#define TEENSY_PIN18 3
-#define PORTB_PIN4 4
-#define PORTB_PIN5 5
-#define PORTB_PIN6 6
-#define PORTB_PIN7 7
-#define PORTB_PIN8 8
-#define PORTB_PIN9 9
-#define PORTB_PIN10 10
-#define PORTB_PIN11 11
-#define PORTB_PIN12 12
-#define PORTB_PIN13 13
-#define PORTB_PIN14 14
-#define PORTB_PIN15 15
-#define TEENSY_PIN0 16
-#define TEENSY_PIN1 17
-#define TEENSY_PIN32 18
-#define TEENSY_PIN25 19
-#define PORTB_PIN20 20
-#define PORTB_PIN21 21
-#define PORTB_PIN22 22
-#define PORTB_PIN23 23
-#define PORTB_PIN24 24
-#define PORTB_PIN25 25
-#define PORTB_PIN26 26
-#define PORTB_PIN27 27
-#define PORTB_PIN28 28
-#define PORTB_PIN29 29
-#define PORTB_PIN30 30
-#define PORTB_PIN31 31
-
-#define TEENSY_PIN0_IOPORT IOPORT2
-#define TEENSY_PIN1_IOPORT IOPORT2
-#define TEENSY_PIN16_IOPORT IOPORT2
-#define TEENSY_PIN17_IOPORT IOPORT2
-#define TEENSY_PIN18_IOPORT IOPORT2
-#define TEENSY_PIN19_IOPORT IOPORT2
-#define TEENSY_PIN25_IOPORT IOPORT2
-#define TEENSY_PIN32_IOPORT IOPORT2
-
-#define TEENSY_PIN15 0
-#define TEENSY_PIN22 1
-#define TEENSY_PIN23 2
-#define TEENSY_PIN9 3
-#define TEENSY_PIN10 4
-#define TEENSY_PIN13 5
-#define TEENSY_PIN11 6
-#define TEENSY_PIN12 7
-#define TEENSY_PIN28 8
-#define TEENSY_PIN27 9
-#define TEENSY_PIN29 10
-#define TEENSY_PIN30 11
-#define PORTC_PIN12 12
-#define PORTC_PIN13 13
-#define PORTC_PIN14 14
-#define PORTC_PIN15 15
-#define PORTC_PIN16 16
-#define PORTC_PIN17 17
-#define PORTC_PIN18 18
-#define PORTC_PIN19 19
-#define PORTC_PIN20 20
-#define PORTC_PIN21 21
-#define PORTC_PIN22 22
-#define PORTC_PIN23 23
-#define PORTC_PIN24 24
-#define PORTC_PIN25 25
-#define PORTC_PIN26 26
-#define PORTC_PIN27 27
-#define PORTC_PIN28 28
-#define PORTC_PIN29 29
-#define PORTC_PIN30 30
-#define PORTC_PIN31 31
-
-#define TEENSY_PIN9_IOPORT IOPORT3
-#define TEENSY_PIN10_IOPORT IOPORT3
-#define TEENSY_PIN11_IOPORT IOPORT3
-#define TEENSY_PIN12_IOPORT IOPORT3
-#define TEENSY_PIN13_IOPORT IOPORT3
-#define TEENSY_PIN15_IOPORT IOPORT3
-#define TEENSY_PIN22_IOPORT IOPORT3
-#define TEENSY_PIN23_IOPORT IOPORT3
-#define TEENSY_PIN27_IOPORT IOPORT3
-#define TEENSY_PIN28_IOPORT IOPORT3
-#define TEENSY_PIN29_IOPORT IOPORT3
-#define TEENSY_PIN30_IOPORT IOPORT3
-
-#define TEENSY_PIN2 0
-#define TEENSY_PIN14 1
-#define TEENSY_PIN7 2
-#define TEENSY_PIN8 3
-#define TEENSY_PIN6 4
-#define TEENSY_PIN20 5
-#define TEENSY_PIN21 6
-#define TEENSY_PIN5 7
-#define PORTD_PIN8 8
-#define PORTD_PIN9 9
-#define PORTD_PIN10 10
-#define PORTD_PIN11 11
-#define PORTD_PIN12 12
-#define PORTD_PIN13 13
-#define PORTD_PIN14 14
-#define PORTD_PIN15 15
-#define PORTD_PIN16 16
-#define PORTD_PIN17 17
-#define PORTD_PIN18 18
-#define PORTD_PIN19 19
-#define PORTD_PIN20 20
-#define PORTD_PIN21 21
-#define PORTD_PIN22 22
-#define PORTD_PIN23 23
-#define PORTD_PIN24 24
-#define PORTD_PIN25 25
-#define PORTD_PIN26 26
-#define PORTD_PIN27 27
-#define PORTD_PIN28 28
-#define PORTD_PIN29 29
-#define PORTD_PIN30 30
-#define PORTD_PIN31 31
-
-#define TEENSY_PIN2_IOPORT IOPORT4
-#define TEENSY_PIN5_IOPORT IOPORT4
-#define TEENSY_PIN6_IOPORT IOPORT4
-#define TEENSY_PIN7_IOPORT IOPORT4
-#define TEENSY_PIN8_IOPORT IOPORT4
-#define TEENSY_PIN14_IOPORT IOPORT4
-#define TEENSY_PIN20_IOPORT IOPORT4
-#define TEENSY_PIN21_IOPORT IOPORT4
-
-#define TEENSY_PIN31 0
-#define TEENSY_PIN26 1
-#define PORTE_PIN2 2
-#define PORTE_PIN3 3
-#define PORTE_PIN4 4
-#define PORTE_PIN5 5
-#define PORTE_PIN6 6
-#define PORTE_PIN7 7
-#define PORTE_PIN8 8
-#define PORTE_PIN9 9
-#define PORTE_PIN10 10
-#define PORTE_PIN11 11
-#define PORTE_PIN12 12
-#define PORTE_PIN13 13
-#define PORTE_PIN14 14
-#define PORTE_PIN15 15
-#define PORTE_PIN16 16
-#define PORTE_PIN17 17
-#define PORTE_PIN18 18
-#define PORTE_PIN19 19
-#define PORTE_PIN20 20
-#define PORTE_PIN21 21
-#define PORTE_PIN22 22
-#define PORTE_PIN23 23
-#define PORTE_PIN24 24
-#define PORTE_PIN25 25
-#define PORTE_PIN26 26
-#define PORTE_PIN27 27
-#define PORTE_PIN28 28
-#define PORTE_PIN29 29
-#define PORTE_PIN30 30
-#define PORTE_PIN31 31
-
-#define TEENSY_PIN26_IOPORT IOPORT5
-#define TEENSY_PIN31_IOPORT IOPORT5
-
-#define LINE_PIN1 PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
-#define LINE_PIN2 PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
-#define LINE_PIN3 PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
-#define LINE_PIN4 PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
-#define LINE_PIN5 PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
-#define LINE_PIN6 PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
-#define LINE_PIN7 PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
-#define LINE_PIN8 PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
-#define LINE_PIN9 PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
-#define LINE_PIN10 PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
-#define LINE_PIN11 PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
-#define LINE_PIN12 PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
-#define LINE_PIN13 PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
-#define LINE_PIN14 PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
-#define LINE_PIN15 PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
-#define LINE_PIN16 PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
-#define LINE_PIN17 PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
-#define LINE_PIN18 PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
-#define LINE_PIN19 PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
-#define LINE_PIN20 PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
-#define LINE_PIN21 PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
-#define LINE_PIN22 PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
-#define LINE_PIN23 PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
-#define LINE_PIN24 PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
-#define LINE_PIN25 PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
-#define LINE_PIN25 PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
-#define LINE_PIN26 PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26)
-#define LINE_PIN27 PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27)
-#define LINE_PIN28 PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28)
-#define LINE_PIN29 PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29)
-#define LINE_PIN30 PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30)
-#define LINE_PIN31 PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31)
-#define LINE_PIN32 PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32)
-#define LINE_PIN33 PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33)
-
-#define LINE_LED LINE_PIN13
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3_1/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3_1/board.mk deleted file mode 100644 index 572a524..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_3_1/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files.
-BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_1/board.c
-
-# Required include directories
-BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_1
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_LC/board.c b/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_LC/board.c deleted file mode 100644 index ab321b8..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_LC/board.c +++ /dev/null @@ -1,177 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-const PALConfig pal_default_config =
-{
- .ports = {
- {
- /*
- * PORTA setup.
- *
- * PTA1 - PIN3
- * PTA2 - PIN4
- *
- * PTA18/19 crystal
- * PTA0/3 SWD
- */
- .port = IOPORT1,
- .pads = {
- PAL_MODE_ALTERNATIVE_7, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_ALTERNATIVE_7, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_INPUT_ANALOG, PAL_MODE_INPUT_ANALOG, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- {
- /*
- * PORTB setup.
- *
- * PTB0 - PIN16
- * PTB1 - PIN17
- * PTB2 - PIN19
- * PTB3 - PIN18
- * PTB16 - PIN0 - UART0_TX
- * PTB17 - PIN1 - UART0_RX
- */
- .port = IOPORT2,
- .pads = {
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_3, PAL_MODE_ALTERNATIVE_3,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- {
- /*
- * PORTC setup.
- *
- * PTC0 - PIN15
- * PTC1 - PIN22
- * PTC2 - PIN23
- * PTC3 - PIN9
- * PTC4 - PIN10
- * PTC5 - PIN13
- * PTC6 - PIN11
- * PTC7 - PIN12
- */
- .port = IOPORT3,
- .pads = {
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- {
- /*
- * PORTD setup.
- *
- * PTD0 - PIN2
- * PTD1 - PIN14
- * PTD2 - PIN7
- * PTD3 - PIN8
- * PTD4 - PIN6
- * PTD5 - PIN20
- * PTD6 - PIN21
- * PTD7 - PIN5
- */
- .port = IOPORT4,
- .pads = {
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- },
- },
- {
- /*
- * PORTE setup.
- *
- * PTE20 - PIN24
- * PTE21 - PIN25
- * PTE30 - PIN26
- */
- .port = IOPORT5,
- .pads = {
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
- PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
- },
- },
- },
-};
-#endif
-
-/**
- * @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
- */
-void __early_init(void) {
-
- kl2x_clock_init();
-}
-
-/**
- * @brief Board-specific initialization code.
- * @todo Add your board-specific code, if any.
- */
-void boardInit(void) {
-}
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_LC/board.h b/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_LC/board.h deleted file mode 100644 index ad75343..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_LC/board.h +++ /dev/null @@ -1,279 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for the PJRC Teensy LC board.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_PJRC_TEENSY_LC
-#define BOARD_NAME "PJRC Teensy LC"
-
-/* External 16 MHz crystal */
-#define KINETIS_XTAL_FREQUENCY 16000000UL
-
-/* Use internal capacitors for the crystal */
-#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P|OSC_CR_ERCLKEN
-
-/*
- * MCU type
- */
-#define KL26
-
-/*
- * IO pins assignments.
- */
-#define PORTA_PIN0 0
-#define TEENSY_PIN3 1
-#define TEENSY_PIN4 2
-#define PORTA_PIN3 3
-#define PORTA_PIN4 4
-#define PORTA_PIN5 5
-#define PORTA_PIN6 6
-#define PORTA_PIN7 7
-#define PORTA_PIN8 8
-#define PORTA_PIN9 9
-#define PORTA_PIN10 10
-#define PORTA_PIN11 11
-#define PORTA_PIN12 12
-#define PORTA_PIN13 13
-#define PORTA_PIN14 14
-#define PORTA_PIN15 15
-#define PORTA_PIN16 16
-#define PORTA_PIN17 17
-#define PORTA_PIN18 18
-#define PORTA_PIN19 19
-#define PORTA_PIN20 20
-#define PORTA_PIN21 21
-#define PORTA_PIN22 22
-#define PORTA_PIN23 23
-#define PORTA_PIN24 24
-#define PORTA_PIN25 25
-#define PORTA_PIN26 26
-#define PORTA_PIN27 27
-#define PORTA_PIN28 28
-#define PORTA_PIN29 29
-#define PORTA_PIN30 30
-#define PORTA_PIN31 31
-
-#define TEENSY_PIN3_IOPORT IOPORT1
-#define TEENSY_PIN4_IOPORT IOPORT1
-
-#define TEENSY_PIN16 0
-#define TEENSY_PIN17 1
-#define TEENSY_PIN19 2
-#define TEENSY_PIN18 3
-#define PORTB_PIN4 4
-#define PORTB_PIN5 5
-#define PORTB_PIN6 6
-#define PORTB_PIN7 7
-#define PORTB_PIN8 8
-#define PORTB_PIN9 9
-#define PORTB_PIN10 10
-#define PORTB_PIN11 11
-#define PORTB_PIN12 12
-#define PORTB_PIN13 13
-#define PORTB_PIN14 14
-#define PORTB_PIN15 15
-#define TEENSY_PIN0 16
-#define TEENSY_PIN1 17
-#define PORTB_PIN18 18
-#define PORTB_PIN19 19
-#define PORTB_PIN20 20
-#define PORTB_PIN21 21
-#define PORTB_PIN22 22
-#define PORTB_PIN23 23
-#define PORTB_PIN24 24
-#define PORTB_PIN25 25
-#define PORTB_PIN26 26
-#define PORTB_PIN27 27
-#define PORTB_PIN28 28
-#define PORTB_PIN29 29
-#define PORTB_PIN30 30
-#define PORTB_PIN31 31
-
-#define TEENSY_PIN0_IOPORT IOPORT2
-#define TEENSY_PIN1_IOPORT IOPORT2
-#define TEENSY_PIN16_IOPORT IOPORT2
-#define TEENSY_PIN17_IOPORT IOPORT2
-#define TEENSY_PIN18_IOPORT IOPORT2
-#define TEENSY_PIN19_IOPORT IOPORT2
-
-#define TEENSY_PIN15 0
-#define TEENSY_PIN22 1
-#define TEENSY_PIN23 2
-#define TEENSY_PIN9 3
-#define TEENSY_PIN10 4
-#define TEENSY_PIN13 5
-#define TEENSY_PIN11 6
-#define TEENSY_PIN12 7
-#define PORTC_PIN8 8
-#define PORTC_PIN9 9
-#define PORTC_PIN10 10
-#define PORTC_PIN11 11
-#define PORTC_PIN12 12
-#define PORTC_PIN13 13
-#define PORTC_PIN14 14
-#define PORTC_PIN15 15
-#define PORTC_PIN16 16
-#define PORTC_PIN17 17
-#define PORTC_PIN18 18
-#define PORTC_PIN19 19
-#define PORTC_PIN20 20
-#define PORTC_PIN21 21
-#define PORTC_PIN22 22
-#define PORTC_PIN23 23
-#define PORTC_PIN24 24
-#define PORTC_PIN25 25
-#define PORTC_PIN26 26
-#define PORTC_PIN27 27
-#define PORTC_PIN28 28
-#define PORTC_PIN29 29
-#define PORTC_PIN30 30
-#define PORTC_PIN31 31
-
-#define TEENSY_PIN9_IOPORT IOPORT3
-#define TEENSY_PIN10_IOPORT IOPORT3
-#define TEENSY_PIN11_IOPORT IOPORT3
-#define TEENSY_PIN12_IOPORT IOPORT3
-#define TEENSY_PIN13_IOPORT IOPORT3
-#define TEENSY_PIN15_IOPORT IOPORT3
-#define TEENSY_PIN22_IOPORT IOPORT3
-#define TEENSY_PIN23_IOPORT IOPORT3
-
-#define TEENSY_PIN2 0
-#define TEENSY_PIN14 1
-#define TEENSY_PIN7 2
-#define TEENSY_PIN8 3
-#define TEENSY_PIN6 4
-#define TEENSY_PIN20 5
-#define TEENSY_PIN21 6
-#define TEENSY_PIN5 7
-#define PORTD_PIN8 8
-#define PORTD_PIN9 9
-#define PORTD_PIN10 10
-#define PORTD_PIN11 11
-#define PORTD_PIN12 12
-#define PORTD_PIN13 13
-#define PORTD_PIN14 14
-#define PORTD_PIN15 15
-#define PORTD_PIN16 16
-#define PORTD_PIN17 17
-#define PORTD_PIN18 18
-#define PORTD_PIN19 19
-#define PORTD_PIN20 20
-#define PORTD_PIN21 21
-#define PORTD_PIN22 22
-#define PORTD_PIN23 23
-#define PORTD_PIN24 24
-#define PORTD_PIN25 25
-#define PORTD_PIN26 26
-#define PORTD_PIN27 27
-#define PORTD_PIN28 28
-#define PORTD_PIN29 29
-#define PORTD_PIN30 30
-#define PORTD_PIN31 31
-
-#define TEENSY_PIN2_IOPORT IOPORT4
-#define TEENSY_PIN5_IOPORT IOPORT4
-#define TEENSY_PIN6_IOPORT IOPORT4
-#define TEENSY_PIN7_IOPORT IOPORT4
-#define TEENSY_PIN8_IOPORT IOPORT4
-#define TEENSY_PIN14_IOPORT IOPORT4
-#define TEENSY_PIN20_IOPORT IOPORT4
-#define TEENSY_PIN21_IOPORT IOPORT4
-
-#define PORTE_PIN0 0
-#define PORTE_PIN1 1
-#define PORTE_PIN2 2
-#define PORTE_PIN3 3
-#define PORTE_PIN4 4
-#define PORTE_PIN5 5
-#define PORTE_PIN6 6
-#define PORTE_PIN7 7
-#define PORTE_PIN8 8
-#define PORTE_PIN9 9
-#define PORTE_PIN10 10
-#define PORTE_PIN11 11
-#define PORTE_PIN12 12
-#define PORTE_PIN13 13
-#define PORTE_PIN14 14
-#define PORTE_PIN15 15
-#define PORTE_PIN16 16
-#define PORTE_PIN17 17
-#define PORTE_PIN18 18
-#define PORTE_PIN19 19
-#define TEENSY_PIN24 20
-#define TEENSY_PIN25 21
-#define PORTE_PIN22 22
-#define PORTE_PIN23 23
-#define PORTE_PIN24 24
-#define PORTE_PIN25 25
-#define PORTE_PIN26 26
-#define PORTE_PIN27 27
-#define PORTE_PIN28 28
-#define PORTE_PIN29 29
-#define TEENSY_PIN26 30
-#define PORTE_PIN31 31
-
-#define TEENSY_PIN24_IOPORT IOPORT5
-#define TEENSY_PIN25_IOPORT IOPORT5
-#define TEENSY_PIN26_IOPORT IOPORT5
-
-#define LINE_PIN1 PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
-#define LINE_PIN2 PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
-#define LINE_PIN3 PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
-#define LINE_PIN4 PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
-#define LINE_PIN5 PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
-#define LINE_PIN6 PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
-#define LINE_PIN7 PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
-#define LINE_PIN8 PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
-#define LINE_PIN9 PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
-#define LINE_PIN10 PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
-#define LINE_PIN11 PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
-#define LINE_PIN12 PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
-#define LINE_PIN13 PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
-#define LINE_PIN14 PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
-#define LINE_PIN15 PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
-#define LINE_PIN16 PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
-#define LINE_PIN17 PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
-#define LINE_PIN18 PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
-#define LINE_PIN19 PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
-#define LINE_PIN20 PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
-#define LINE_PIN21 PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
-#define LINE_PIN22 PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
-#define LINE_PIN23 PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
-#define LINE_PIN24 PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
-#define LINE_PIN25 PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
-
-#define LINE_LED LINE_PIN13
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_LC/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_LC/board.mk deleted file mode 100644 index 85c643a..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/PJRC_TEENSY_LC/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files.
-BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_LC/board.c
-
-# Required include directories
-BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_LC
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c b/ChibiOS_16.1.5/community/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c deleted file mode 100644 index dc058f6..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c +++ /dev/null @@ -1,102 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-const PALConfig pal_default_config = {
-#if STM32_HAS_GPIOA
- {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
- VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
-#endif
-#if STM32_HAS_GPIOB
- {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
- VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
-#endif
-#if STM32_HAS_GPIOC
- {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
- VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
-#endif
-#if STM32_HAS_GPIOD
- {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
- VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
-#endif
-#if STM32_HAS_GPIOE
- {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
- VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
-#endif
-#if STM32_HAS_GPIOF
- {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
- VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
-#endif
-#if STM32_HAS_GPIOG
- {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
- VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
-#endif
-#if STM32_HAS_GPIOH
- {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
- VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
-#endif
-#if STM32_HAS_GPIOI
- {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
- VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
-#endif
-};
-#endif
-
-/**
- * @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
- */
-void __early_init(void) {
-
- stm32_clock_init();
-}
-
-#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
-/**
- * @brief MMC_SPI card detection.
- */
-bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
-
- (void)mmcp;
- /* TODO: Fill the implementation.*/
- return true;
-}
-
-/**
- * @brief MMC_SPI card write protection detection.
- */
-bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
-
- (void)mmcp;
- /* TODO: Fill the implementation.*/
- return false;
-}
-#endif
-
-/**
- * @brief Board-specific initialization code.
- * @todo Add your board-specific code, if any.
- */
-void boardInit(void) {
-}
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/ST_STM32F0308_DISCOVERY/board.h b/ChibiOS_16.1.5/community/os/hal/boards/ST_STM32F0308_DISCOVERY/board.h deleted file mode 100644 index a866c88..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/ST_STM32F0308_DISCOVERY/board.h +++ /dev/null @@ -1,757 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for ST STM32F0-Discovery board.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_ST_STM32F0308_DISCOVERY
-#define BOARD_NAME "ST STM32F0308-Discovery"
-
-/*
- * Board oscillators-related settings.
- * NOTE: LSE not fitted.
- * NOTE: HSE not fitted.
- */
-#if !defined(STM32_LSECLK)
-#define STM32_LSECLK 0
-#endif
-
-#define STM32_LSEDRV (3 << 3)
-
-#if !defined(STM32_HSECLK)
-#define STM32_HSECLK 0
-#endif
-
-#define STM32_HSE_BYPASS
-
-/*
- * MCU type as defined in the ST header.
- */
-#define STM32F030x8
-
-/*
- * IO pins assignments.
- */
-#define GPIOA_BUTTON 0
-#define GPIOA_PIN1 1
-#define GPIOA_PIN2 2
-#define GPIOA_PIN3 3
-#define GPIOA_PIN4 4
-#define GPIOA_PIN5 5
-#define GPIOA_PIN6 6
-#define GPIOA_PIN7 7
-#define GPIOA_PIN8 8
-#define GPIOA_PIN9 9
-#define GPIOA_PIN10 10
-#define GPIOA_PIN11 11
-#define GPIOA_PIN12 12
-#define GPIOA_SWDAT 13
-#define GPIOA_SWCLK 14
-#define GPIOA_PIN15 15
-
-#define GPIOB_PIN0 0
-#define GPIOB_PIN1 1
-#define GPIOB_PIN2 2
-#define GPIOB_PIN3 3
-#define GPIOB_PIN4 4
-#define GPIOB_PIN5 5
-#define GPIOB_PIN6 6
-#define GPIOB_PIN7 7
-#define GPIOB_PIN8 8
-#define GPIOB_PIN9 9
-#define GPIOB_PIN10 10
-#define GPIOB_PIN11 11
-#define GPIOB_PIN12 12
-#define GPIOB_PIN13 13
-#define GPIOB_PIN14 14
-#define GPIOB_PIN15 15
-
-#define GPIOC_PIN0 0
-#define GPIOC_PIN1 1
-#define GPIOC_PIN2 2
-#define GPIOC_PIN3 3
-#define GPIOC_PIN4 4
-#define GPIOC_PIN5 5
-#define GPIOC_PIN6 6
-#define GPIOC_PIN7 7
-#define GPIOC_LED4 8
-#define GPIOC_LED3 9
-#define GPIOC_PIN10 10
-#define GPIOC_PIN11 11
-#define GPIOC_PIN12 12
-#define GPIOC_PIN13 13
-#define GPIOC_OSC32_IN 14
-#define GPIOC_OSC32_OUT 15
-
-#define GPIOD_PIN0 0
-#define GPIOD_PIN1 1
-#define GPIOD_PIN2 2
-#define GPIOD_PIN3 3
-#define GPIOD_PIN4 4
-#define GPIOD_PIN5 5
-#define GPIOD_PIN6 6
-#define GPIOD_PIN7 7
-#define GPIOD_PIN8 8
-#define GPIOD_PIN9 9
-#define GPIOD_PIN10 10
-#define GPIOD_PIN11 11
-#define GPIOD_PIN12 12
-#define GPIOD_PIN13 13
-#define GPIOD_PIN14 14
-#define GPIOD_PIN15 15
-
-#define GPIOF_OSC_IN 0
-#define GPIOF_OSC_OUT 1
-#define GPIOF_PIN2 2
-#define GPIOF_PIN3 3
-#define GPIOF_PIN4 4
-#define GPIOF_PIN5 5
-#define GPIOF_PIN6 6
-#define GPIOF_PIN7 7
-#define GPIOF_PIN8 8
-#define GPIOF_PIN9 9
-#define GPIOF_PIN10 10
-#define GPIOF_PIN11 11
-#define GPIOF_PIN12 12
-#define GPIOF_PIN13 13
-#define GPIOF_PIN14 14
-#define GPIOF_PIN15 15
-
-/*
- * I/O ports initial setup, this configuration is established soon after reset
- * in the initialization code.
- * Please refer to the STM32 Reference Manual for details.
- */
-#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
-#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
-#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
-#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
-#define PIN_ODR_LOW(n) (0U << (n))
-#define PIN_ODR_HIGH(n) (1U << (n))
-#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
-#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
-#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
-#define PIN_OSPEED_10M(n) (1U << ((n) * 2))
-#define PIN_OSPEED_40M(n) (3U << ((n) * 2))
-#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
-#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
-#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
-#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
-
-/*
- * GPIOA setup:
- *
- * PA0 - BUTTON (input floating).
- * PA1 - PIN1 (input pullup).
- * PA2 - PIN2 (input pullup).
- * PA3 - PIN3 (input pullup).
- * PA4 - PIN4 (input pullup).
- * PA5 - PIN5 (input pullup).
- * PA6 - PIN6 (input pullup).
- * PA7 - PIN7 (input pullup).
- * PA8 - PIN8 (input pullup).
- * PA9 - PIN9 (input pullup).
- * PA10 - PIN10 (input pullup).
- * PA11 - PIN11 (input pullup).
- * PA12 - PIN12 (input pullup).
- * PA13 - SWDAT (alternate 0).
- * PA14 - SWCLK (alternate 0).
- * PA15 - PIN15 (input pullup).
- */
-#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \
- PIN_MODE_INPUT(GPIOA_PIN1) | \
- PIN_MODE_INPUT(GPIOA_PIN2) | \
- PIN_MODE_INPUT(GPIOA_PIN3) | \
- PIN_MODE_INPUT(GPIOA_PIN4) | \
- PIN_MODE_INPUT(GPIOA_PIN5) | \
- PIN_MODE_INPUT(GPIOA_PIN6) | \
- PIN_MODE_INPUT(GPIOA_PIN7) | \
- PIN_MODE_INPUT(GPIOA_PIN8) | \
- PIN_MODE_INPUT(GPIOA_PIN9) | \
- PIN_MODE_INPUT(GPIOA_PIN10) | \
- PIN_MODE_INPUT(GPIOA_PIN11) | \
- PIN_MODE_INPUT(GPIOA_PIN12) | \
- PIN_MODE_ALTERNATE(GPIOA_SWDAT) | \
- PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
- PIN_MODE_INPUT(GPIOA_PIN15))
-#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOA_SWDAT) | \
- PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
-#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_BUTTON) | \
- PIN_OSPEED_2M(GPIOA_PIN1) | \
- PIN_OSPEED_2M(GPIOA_PIN2) | \
- PIN_OSPEED_2M(GPIOA_PIN3) | \
- PIN_OSPEED_2M(GPIOA_PIN4) | \
- PIN_OSPEED_2M(GPIOA_PIN5) | \
- PIN_OSPEED_2M(GPIOA_PIN6) | \
- PIN_OSPEED_2M(GPIOA_PIN7) | \
- PIN_OSPEED_2M(GPIOA_PIN8) | \
- PIN_OSPEED_2M(GPIOA_PIN9) | \
- PIN_OSPEED_2M(GPIOA_PIN10) | \
- PIN_OSPEED_2M(GPIOA_PIN11) | \
- PIN_OSPEED_2M(GPIOA_PIN12) | \
- PIN_OSPEED_40M(GPIOA_SWDAT) | \
- PIN_OSPEED_40M(GPIOA_SWCLK) | \
- PIN_OSPEED_40M(GPIOA_PIN15))
-#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN5) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN7) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN11) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN12) | \
- PIN_PUPDR_PULLUP(GPIOA_SWDAT) | \
- PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN15))
-#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \
- PIN_ODR_HIGH(GPIOA_PIN1) | \
- PIN_ODR_HIGH(GPIOA_PIN2) | \
- PIN_ODR_HIGH(GPIOA_PIN3) | \
- PIN_ODR_HIGH(GPIOA_PIN4) | \
- PIN_ODR_HIGH(GPIOA_PIN5) | \
- PIN_ODR_HIGH(GPIOA_PIN6) | \
- PIN_ODR_HIGH(GPIOA_PIN7) | \
- PIN_ODR_HIGH(GPIOA_PIN8) | \
- PIN_ODR_HIGH(GPIOA_PIN9) | \
- PIN_ODR_HIGH(GPIOA_PIN10) | \
- PIN_ODR_HIGH(GPIOA_PIN11) | \
- PIN_ODR_HIGH(GPIOA_PIN12) | \
- PIN_ODR_HIGH(GPIOA_SWDAT) | \
- PIN_ODR_HIGH(GPIOA_SWCLK) | \
- PIN_ODR_HIGH(GPIOA_PIN15))
-#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \
- PIN_AFIO_AF(GPIOA_PIN1, 0) | \
- PIN_AFIO_AF(GPIOA_PIN2, 0) | \
- PIN_AFIO_AF(GPIOA_PIN3, 0) | \
- PIN_AFIO_AF(GPIOA_PIN4, 0) | \
- PIN_AFIO_AF(GPIOA_PIN5, 0) | \
- PIN_AFIO_AF(GPIOA_PIN6, 0) | \
- PIN_AFIO_AF(GPIOA_PIN7, 0))
-#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
- PIN_AFIO_AF(GPIOA_PIN9, 0) | \
- PIN_AFIO_AF(GPIOA_PIN10, 0) | \
- PIN_AFIO_AF(GPIOA_PIN11, 0) | \
- PIN_AFIO_AF(GPIOA_PIN12, 0) | \
- PIN_AFIO_AF(GPIOA_SWDAT, 0) | \
- PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
- PIN_AFIO_AF(GPIOA_PIN15, 0))
-
-/*
- * GPIOB setup:
- *
- * PB0 - PIN0 (input pullup).
- * PB1 - PIN1 (input pullup).
- * PB2 - PIN2 (input pullup).
- * PB3 - PIN3 (input pullup).
- * PB4 - PIN4 (input pullup).
- * PB5 - PIN5 (input pullup).
- * PB6 - PIN6 (input pullup).
- * PB7 - PIN7 (input pullup).
- * PB8 - PIN8 (input pullup).
- * PB9 - PIN9 (input pullup).
- * PB10 - PIN10 (input pullup).
- * PB11 - PIN11 (input pullup).
- * PB12 - PIN12 (input pullup).
- * PB13 - PIN13 (input pullup).
- * PB14 - PIN14 (input pullup).
- * PB15 - PIN15 (input pullup).
- */
-#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
- PIN_MODE_INPUT(GPIOB_PIN1) | \
- PIN_MODE_INPUT(GPIOB_PIN2) | \
- PIN_MODE_INPUT(GPIOB_PIN3) | \
- PIN_MODE_INPUT(GPIOB_PIN4) | \
- PIN_MODE_INPUT(GPIOB_PIN5) | \
- PIN_MODE_INPUT(GPIOB_PIN6) | \
- PIN_MODE_INPUT(GPIOB_PIN7) | \
- PIN_MODE_INPUT(GPIOB_PIN8) | \
- PIN_MODE_INPUT(GPIOB_PIN9) | \
- PIN_MODE_INPUT(GPIOB_PIN10) | \
- PIN_MODE_INPUT(GPIOB_PIN11) | \
- PIN_MODE_INPUT(GPIOB_PIN12) | \
- PIN_MODE_INPUT(GPIOB_PIN13) | \
- PIN_MODE_INPUT(GPIOB_PIN14) | \
- PIN_MODE_INPUT(GPIOB_PIN15))
-#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
-#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_2M(GPIOB_PIN0) | \
- PIN_OSPEED_2M(GPIOB_PIN1) | \
- PIN_OSPEED_40M(GPIOB_PIN2) | \
- PIN_OSPEED_40M(GPIOB_PIN3) | \
- PIN_OSPEED_40M(GPIOB_PIN4) | \
- PIN_OSPEED_2M(GPIOB_PIN5) | \
- PIN_OSPEED_2M(GPIOB_PIN6) | \
- PIN_OSPEED_2M(GPIOB_PIN7) | \
- PIN_OSPEED_2M(GPIOB_PIN8) | \
- PIN_OSPEED_2M(GPIOB_PIN9) | \
- PIN_OSPEED_2M(GPIOB_PIN10) | \
- PIN_OSPEED_2M(GPIOB_PIN11) | \
- PIN_OSPEED_2M(GPIOB_PIN12) | \
- PIN_OSPEED_2M(GPIOB_PIN13) | \
- PIN_OSPEED_2M(GPIOB_PIN14) | \
- PIN_OSPEED_2M(GPIOB_PIN15))
-#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN3) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN15))
-#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
- PIN_ODR_HIGH(GPIOB_PIN1) | \
- PIN_ODR_HIGH(GPIOB_PIN2) | \
- PIN_ODR_HIGH(GPIOB_PIN3) | \
- PIN_ODR_HIGH(GPIOB_PIN4) | \
- PIN_ODR_HIGH(GPIOB_PIN5) | \
- PIN_ODR_HIGH(GPIOB_PIN6) | \
- PIN_ODR_HIGH(GPIOB_PIN7) | \
- PIN_ODR_HIGH(GPIOB_PIN8) | \
- PIN_ODR_HIGH(GPIOB_PIN9) | \
- PIN_ODR_HIGH(GPIOB_PIN10) | \
- PIN_ODR_HIGH(GPIOB_PIN11) | \
- PIN_ODR_HIGH(GPIOB_PIN12) | \
- PIN_ODR_HIGH(GPIOB_PIN13) | \
- PIN_ODR_HIGH(GPIOB_PIN14) | \
- PIN_ODR_HIGH(GPIOB_PIN15))
-#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \
- PIN_AFIO_AF(GPIOB_PIN1, 0) | \
- PIN_AFIO_AF(GPIOB_PIN2, 0) | \
- PIN_AFIO_AF(GPIOB_PIN3, 0) | \
- PIN_AFIO_AF(GPIOB_PIN4, 0) | \
- PIN_AFIO_AF(GPIOB_PIN5, 0) | \
- PIN_AFIO_AF(GPIOB_PIN6, 0) | \
- PIN_AFIO_AF(GPIOB_PIN7, 0))
-#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
- PIN_AFIO_AF(GPIOB_PIN9, 0) | \
- PIN_AFIO_AF(GPIOB_PIN10, 0) | \
- PIN_AFIO_AF(GPIOB_PIN11, 0) | \
- PIN_AFIO_AF(GPIOB_PIN12, 0) | \
- PIN_AFIO_AF(GPIOB_PIN13, 0) | \
- PIN_AFIO_AF(GPIOB_PIN14, 0) | \
- PIN_AFIO_AF(GPIOB_PIN15, 0))
-
-/*
- * GPIOC setup:
- *
- * PC0 - PIN0 (input pullup).
- * PC1 - PIN1 (input pullup).
- * PC2 - PIN2 (input pullup).
- * PC3 - PIN3 (input pullup).
- * PC4 - PIN4 (input pullup).
- * PC5 - PIN5 (input pullup).
- * PC6 - PIN6 (input pullup).
- * PC7 - PIN7 (input pullup).
- * PC8 - LED4 (output pushpull maximum).
- * PC9 - LED3 (output pushpull maximum).
- * PC10 - PIN10 (input pullup).
- * PC11 - PIN11 (input pullup).
- * PC12 - PIN12 (input pullup).
- * PC13 - PIN13 (input pullup).
- * PC14 - OSC32_IN (input floating).
- * PC15 - OSC32_OUT (input floating).
- */
-#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
- PIN_MODE_INPUT(GPIOC_PIN1) | \
- PIN_MODE_INPUT(GPIOC_PIN2) | \
- PIN_MODE_INPUT(GPIOC_PIN3) | \
- PIN_MODE_INPUT(GPIOC_PIN4) | \
- PIN_MODE_INPUT(GPIOC_PIN5) | \
- PIN_MODE_INPUT(GPIOC_PIN6) | \
- PIN_MODE_INPUT(GPIOC_PIN7) | \
- PIN_MODE_OUTPUT(GPIOC_LED4) | \
- PIN_MODE_OUTPUT(GPIOC_LED3) | \
- PIN_MODE_INPUT(GPIOC_PIN10) | \
- PIN_MODE_INPUT(GPIOC_PIN11) | \
- PIN_MODE_INPUT(GPIOC_PIN12) | \
- PIN_MODE_INPUT(GPIOC_PIN13) | \
- PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
- PIN_MODE_INPUT(GPIOC_OSC32_OUT))
-#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOC_LED4) | \
- PIN_OTYPE_PUSHPULL(GPIOC_LED3) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
- PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
-#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_2M(GPIOC_PIN0) | \
- PIN_OSPEED_2M(GPIOC_PIN1) | \
- PIN_OSPEED_2M(GPIOC_PIN2) | \
- PIN_OSPEED_2M(GPIOC_PIN3) | \
- PIN_OSPEED_2M(GPIOC_PIN4) | \
- PIN_OSPEED_2M(GPIOC_PIN5) | \
- PIN_OSPEED_2M(GPIOC_PIN6) | \
- PIN_OSPEED_2M(GPIOC_PIN7) | \
- PIN_OSPEED_40M(GPIOC_LED4) | \
- PIN_OSPEED_40M(GPIOC_LED3) | \
- PIN_OSPEED_2M(GPIOC_PIN10) | \
- PIN_OSPEED_2M(GPIOC_PIN11) | \
- PIN_OSPEED_2M(GPIOC_PIN12) | \
- PIN_OSPEED_2M(GPIOC_PIN13) | \
- PIN_OSPEED_40M(GPIOC_OSC32_IN) | \
- PIN_OSPEED_40M(GPIOC_OSC32_OUT))
-#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOC_LED4) | \
- PIN_PUPDR_FLOATING(GPIOC_LED3) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
- PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
-#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
- PIN_ODR_HIGH(GPIOC_PIN1) | \
- PIN_ODR_HIGH(GPIOC_PIN2) | \
- PIN_ODR_HIGH(GPIOC_PIN3) | \
- PIN_ODR_HIGH(GPIOC_PIN4) | \
- PIN_ODR_HIGH(GPIOC_PIN5) | \
- PIN_ODR_HIGH(GPIOC_PIN6) | \
- PIN_ODR_HIGH(GPIOC_PIN7) | \
- PIN_ODR_LOW(GPIOC_LED4) | \
- PIN_ODR_LOW(GPIOC_LED3) | \
- PIN_ODR_HIGH(GPIOC_PIN10) | \
- PIN_ODR_HIGH(GPIOC_PIN11) | \
- PIN_ODR_HIGH(GPIOC_PIN12) | \
- PIN_ODR_HIGH(GPIOC_PIN13) | \
- PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
- PIN_ODR_HIGH(GPIOC_OSC32_OUT))
-#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \
- PIN_AFIO_AF(GPIOC_PIN1, 0) | \
- PIN_AFIO_AF(GPIOC_PIN2, 0) | \
- PIN_AFIO_AF(GPIOC_PIN3, 0) | \
- PIN_AFIO_AF(GPIOC_PIN4, 0) | \
- PIN_AFIO_AF(GPIOC_PIN5, 0) | \
- PIN_AFIO_AF(GPIOC_PIN6, 0) | \
- PIN_AFIO_AF(GPIOC_PIN7, 0))
-#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_LED4, 0) | \
- PIN_AFIO_AF(GPIOC_LED3, 0) | \
- PIN_AFIO_AF(GPIOC_PIN10, 0) | \
- PIN_AFIO_AF(GPIOC_PIN11, 0) | \
- PIN_AFIO_AF(GPIOC_PIN12, 0) | \
- PIN_AFIO_AF(GPIOC_PIN13, 0) | \
- PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \
- PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
-
-/*
- * GPIOD setup:
- *
- * PD0 - PIN0 (input pullup).
- * PD1 - PIN1 (input pullup).
- * PD2 - PIN2 (input pullup).
- * PD3 - PIN3 (input pullup).
- * PD4 - PIN4 (input pullup).
- * PD5 - PIN5 (input pullup).
- * PD6 - PIN6 (input pullup).
- * PD7 - PIN7 (input pullup).
- * PD8 - PIN8 (input pullup).
- * PD9 - PIN9 (input pullup).
- * PD10 - PIN10 (input pullup).
- * PD11 - PIN11 (input pullup).
- * PD12 - PIN12 (input pullup).
- * PD13 - PIN13 (input pullup).
- * PD14 - PIN14 (input pullup).
- * PD15 - PIN15 (input pullup).
- */
-#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
- PIN_MODE_INPUT(GPIOD_PIN1) | \
- PIN_MODE_INPUT(GPIOD_PIN2) | \
- PIN_MODE_INPUT(GPIOD_PIN3) | \
- PIN_MODE_INPUT(GPIOD_PIN4) | \
- PIN_MODE_INPUT(GPIOD_PIN5) | \
- PIN_MODE_INPUT(GPIOD_PIN6) | \
- PIN_MODE_INPUT(GPIOD_PIN7) | \
- PIN_MODE_INPUT(GPIOD_PIN8) | \
- PIN_MODE_INPUT(GPIOD_PIN9) | \
- PIN_MODE_INPUT(GPIOD_PIN10) | \
- PIN_MODE_INPUT(GPIOD_PIN11) | \
- PIN_MODE_INPUT(GPIOD_PIN12) | \
- PIN_MODE_INPUT(GPIOD_PIN13) | \
- PIN_MODE_INPUT(GPIOD_PIN14) | \
- PIN_MODE_INPUT(GPIOD_PIN15))
-#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
-#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_2M(GPIOD_PIN0) | \
- PIN_OSPEED_2M(GPIOD_PIN1) | \
- PIN_OSPEED_2M(GPIOD_PIN2) | \
- PIN_OSPEED_2M(GPIOD_PIN3) | \
- PIN_OSPEED_2M(GPIOD_PIN4) | \
- PIN_OSPEED_2M(GPIOD_PIN5) | \
- PIN_OSPEED_2M(GPIOD_PIN6) | \
- PIN_OSPEED_2M(GPIOD_PIN7) | \
- PIN_OSPEED_2M(GPIOD_PIN8) | \
- PIN_OSPEED_2M(GPIOD_PIN9) | \
- PIN_OSPEED_2M(GPIOD_PIN10) | \
- PIN_OSPEED_2M(GPIOD_PIN11) | \
- PIN_OSPEED_2M(GPIOD_PIN12) | \
- PIN_OSPEED_2M(GPIOD_PIN13) | \
- PIN_OSPEED_2M(GPIOD_PIN14) | \
- PIN_OSPEED_2M(GPIOD_PIN15))
-#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN15))
-#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
- PIN_ODR_HIGH(GPIOD_PIN1) | \
- PIN_ODR_HIGH(GPIOD_PIN2) | \
- PIN_ODR_HIGH(GPIOD_PIN3) | \
- PIN_ODR_HIGH(GPIOD_PIN4) | \
- PIN_ODR_HIGH(GPIOD_PIN5) | \
- PIN_ODR_HIGH(GPIOD_PIN6) | \
- PIN_ODR_HIGH(GPIOD_PIN7) | \
- PIN_ODR_HIGH(GPIOD_PIN8) | \
- PIN_ODR_HIGH(GPIOD_PIN9) | \
- PIN_ODR_HIGH(GPIOD_PIN10) | \
- PIN_ODR_HIGH(GPIOD_PIN11) | \
- PIN_ODR_HIGH(GPIOD_PIN12) | \
- PIN_ODR_HIGH(GPIOD_PIN13) | \
- PIN_ODR_HIGH(GPIOD_PIN14) | \
- PIN_ODR_HIGH(GPIOD_PIN15))
-#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
- PIN_AFIO_AF(GPIOD_PIN1, 0) | \
- PIN_AFIO_AF(GPIOD_PIN2, 0) | \
- PIN_AFIO_AF(GPIOD_PIN3, 0) | \
- PIN_AFIO_AF(GPIOD_PIN4, 0) | \
- PIN_AFIO_AF(GPIOD_PIN5, 0) | \
- PIN_AFIO_AF(GPIOD_PIN6, 0) | \
- PIN_AFIO_AF(GPIOD_PIN7, 0))
-#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
- PIN_AFIO_AF(GPIOD_PIN9, 0) | \
- PIN_AFIO_AF(GPIOD_PIN10, 0) | \
- PIN_AFIO_AF(GPIOD_PIN11, 0) | \
- PIN_AFIO_AF(GPIOD_PIN12, 0) | \
- PIN_AFIO_AF(GPIOD_PIN13, 0) | \
- PIN_AFIO_AF(GPIOD_PIN14, 0) | \
- PIN_AFIO_AF(GPIOD_PIN15, 0))
-
-/*
- * GPIOF setup:
- *
- * PF0 - OSC_IN (input floating).
- * PF1 - OSC_OUT (input floating).
- * PF2 - PIN2 (input pullup).
- * PF3 - PIN3 (input pullup).
- * PF4 - PIN4 (input pullup).
- * PF5 - PIN5 (input pullup).
- * PF6 - PIN6 (input pullup).
- * PF7 - PIN7 (input pullup).
- * PF8 - PIN8 (input pullup).
- * PF9 - PIN9 (input pullup).
- * PF10 - PIN10 (input pullup).
- * PF11 - PIN11 (input pullup).
- * PF12 - PIN12 (input pullup).
- * PF13 - PIN13 (input pullup).
- * PF14 - PIN14 (input pullup).
- * PF15 - PIN15 (input pullup).
- */
-#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \
- PIN_MODE_INPUT(GPIOF_OSC_OUT) | \
- PIN_MODE_INPUT(GPIOF_PIN2) | \
- PIN_MODE_INPUT(GPIOF_PIN3) | \
- PIN_MODE_INPUT(GPIOF_PIN4) | \
- PIN_MODE_INPUT(GPIOF_PIN5) | \
- PIN_MODE_INPUT(GPIOF_PIN6) | \
- PIN_MODE_INPUT(GPIOF_PIN7) | \
- PIN_MODE_INPUT(GPIOF_PIN8) | \
- PIN_MODE_INPUT(GPIOF_PIN9) | \
- PIN_MODE_INPUT(GPIOF_PIN10) | \
- PIN_MODE_INPUT(GPIOF_PIN11) | \
- PIN_MODE_INPUT(GPIOF_PIN12) | \
- PIN_MODE_INPUT(GPIOF_PIN13) | \
- PIN_MODE_INPUT(GPIOF_PIN14) | \
- PIN_MODE_INPUT(GPIOF_PIN15))
-#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \
- PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
-#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_2M(GPIOF_OSC_IN) | \
- PIN_OSPEED_2M(GPIOF_OSC_OUT) | \
- PIN_OSPEED_2M(GPIOF_PIN2) | \
- PIN_OSPEED_2M(GPIOF_PIN3) | \
- PIN_OSPEED_2M(GPIOF_PIN4) | \
- PIN_OSPEED_2M(GPIOF_PIN5) | \
- PIN_OSPEED_2M(GPIOF_PIN6) | \
- PIN_OSPEED_2M(GPIOF_PIN7) | \
- PIN_OSPEED_2M(GPIOF_PIN8) | \
- PIN_OSPEED_2M(GPIOF_PIN9) | \
- PIN_OSPEED_2M(GPIOF_PIN10) | \
- PIN_OSPEED_2M(GPIOF_PIN11) | \
- PIN_OSPEED_2M(GPIOF_PIN12) | \
- PIN_OSPEED_2M(GPIOF_PIN13) | \
- PIN_OSPEED_2M(GPIOF_PIN14) | \
- PIN_OSPEED_2M(GPIOF_PIN15))
-#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \
- PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN15))
-#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \
- PIN_ODR_HIGH(GPIOF_OSC_OUT) | \
- PIN_ODR_HIGH(GPIOF_PIN2) | \
- PIN_ODR_HIGH(GPIOF_PIN3) | \
- PIN_ODR_HIGH(GPIOF_PIN4) | \
- PIN_ODR_HIGH(GPIOF_PIN5) | \
- PIN_ODR_HIGH(GPIOF_PIN6) | \
- PIN_ODR_HIGH(GPIOF_PIN7) | \
- PIN_ODR_HIGH(GPIOF_PIN8) | \
- PIN_ODR_HIGH(GPIOF_PIN9) | \
- PIN_ODR_HIGH(GPIOF_PIN10) | \
- PIN_ODR_HIGH(GPIOF_PIN11) | \
- PIN_ODR_HIGH(GPIOF_PIN12) | \
- PIN_ODR_HIGH(GPIOF_PIN13) | \
- PIN_ODR_HIGH(GPIOF_PIN14) | \
- PIN_ODR_HIGH(GPIOF_PIN15))
-#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0) | \
- PIN_AFIO_AF(GPIOF_OSC_OUT, 0) | \
- PIN_AFIO_AF(GPIOF_PIN2, 0) | \
- PIN_AFIO_AF(GPIOF_PIN3, 0) | \
- PIN_AFIO_AF(GPIOF_PIN4, 0) | \
- PIN_AFIO_AF(GPIOF_PIN5, 0) | \
- PIN_AFIO_AF(GPIOF_PIN6, 0) | \
- PIN_AFIO_AF(GPIOF_PIN7, 0))
-#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
- PIN_AFIO_AF(GPIOF_PIN9, 0) | \
- PIN_AFIO_AF(GPIOF_PIN10, 0) | \
- PIN_AFIO_AF(GPIOF_PIN11, 0) | \
- PIN_AFIO_AF(GPIOF_PIN12, 0) | \
- PIN_AFIO_AF(GPIOF_PIN13, 0) | \
- PIN_AFIO_AF(GPIOF_PIN14, 0) | \
- PIN_AFIO_AF(GPIOF_PIN15, 0))
-
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/ST_STM32F0308_DISCOVERY/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/ST_STM32F0308_DISCOVERY/board.mk deleted file mode 100644 index 35b3939..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/ST_STM32F0308_DISCOVERY/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files.
-BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c
-
-# Required include directories
-BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/ST_STM32F0308_DISCOVERY
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c b/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c deleted file mode 100644 index 2bbbc4c..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. - */ -#if HAL_USE_PAL || defined(__DOXYGEN__) -const PALConfig pal_default_config = -{ - {VAL_GPIOA_DATA, VAL_GPIOA_DIR, VAL_GPIOA_AFSEL, VAL_GPIOA_DR2R, - VAL_GPIOA_DR4R, VAL_GPIOA_DR8R, VAL_GPIOA_ODR, VAL_GPIOA_PUR, - VAL_GPIOA_PDR, VAL_GPIOA_SLR, VAL_GPIOA_DEN, VAL_GPIOA_AMSEL, - VAL_GPIOA_PCTL}, - {VAL_GPIOB_DATA, VAL_GPIOB_DIR, VAL_GPIOB_AFSEL, VAL_GPIOB_DR2R, - VAL_GPIOB_DR4R, VAL_GPIOB_DR8R, VAL_GPIOB_ODR, VAL_GPIOB_PUR, - VAL_GPIOB_PDR, VAL_GPIOB_SLR, VAL_GPIOB_DEN, VAL_GPIOB_AMSEL, - VAL_GPIOB_PCTL}, - {VAL_GPIOC_DATA, VAL_GPIOC_DIR, VAL_GPIOC_AFSEL, VAL_GPIOC_DR2R, - VAL_GPIOC_DR4R, VAL_GPIOC_DR8R, VAL_GPIOC_ODR, VAL_GPIOC_PUR, - VAL_GPIOC_PDR, VAL_GPIOC_SLR, VAL_GPIOC_DEN, VAL_GPIOC_AMSEL, - VAL_GPIOC_PCTL}, - {VAL_GPIOD_DATA, VAL_GPIOD_DIR, VAL_GPIOD_AFSEL, VAL_GPIOD_DR2R, - VAL_GPIOD_DR4R, VAL_GPIOD_DR8R, VAL_GPIOD_ODR, VAL_GPIOD_PUR, - VAL_GPIOD_PDR, VAL_GPIOD_SLR, VAL_GPIOD_DEN, VAL_GPIOD_AMSEL, - VAL_GPIOD_PCTL}, - {VAL_GPIOE_DATA, VAL_GPIOE_DIR, VAL_GPIOE_AFSEL, VAL_GPIOE_DR2R, - VAL_GPIOE_DR4R, VAL_GPIOE_DR8R, VAL_GPIOE_ODR, VAL_GPIOE_PUR, - VAL_GPIOE_PDR, VAL_GPIOE_SLR, VAL_GPIOE_DEN, VAL_GPIOE_AMSEL, - VAL_GPIOE_PCTL}, - {VAL_GPIOF_DATA, VAL_GPIOF_DIR, VAL_GPIOF_AFSEL, VAL_GPIOF_DR2R, - VAL_GPIOF_DR4R, VAL_GPIOF_DR8R, VAL_GPIOF_ODR, VAL_GPIOF_PUR, - VAL_GPIOF_PDR, VAL_GPIOF_SLR, VAL_GPIOF_DEN, VAL_GPIOF_AMSEL, - VAL_GPIOF_PCTL} -}; -#endif - -/** - * @brief Early initialization code. - * @details This initialization is performed just after reset before BSS and - * DATA segments initialization. - */ -void __early_init(void) -{ - tiva_clock_init(); -} - -/** - * @brief Late initialization code. - * @note This initialization is performed after BSS and DATA segments - * initialization and before invoking the main() function. - */ -void boardInit(void) -{ -} diff --git a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h b/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h deleted file mode 100644 index 367dce1..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h +++ /dev/null @@ -1,943 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for Texas Instruments TM4C123G Launchpad Board. - */ - -/* - * Board identifier. - */ -#define BOARD_TI_TM4C123G_LAUNCHPAD -#define BOARD_NAME "Texas Instruments TM4C123G Launchpad" - -/* - * MCU type - */ -//#define TM4C1230C3PM -//#define TM4C1230D5PM -//#define TM4C1230E6PM -//#define TM4C1230H6PM -//#define TM4C1231C3PM -//#define TM4C1231D5PM -//#define TM4C1231D5PZ -//#define TM4C1231E6PM -//#define TM4C1231E6PZ -//#define TM4C1231H6PGE -//#define TM4C1231H6PM -//#define TM4C1231H6PZ -//#define TM4C1232C3PM -//#define TM4C1232D5PM -//#define TM4C1232E6PM -//#define TM4C1232H6PM -//#define TM4C1233C3PM -//#define TM4C1233D5PM -//#define TM4C1233D5PZ -//#define TM4C1233E6PM -//#define TM4C1233E6PZ -//#define TM4C1233H6PGE -//#define TM4C1233H6PM -//#define TM4C1233H6PZ -//#define TM4C1236D5PM -//#define TM4C1236E6PM -//#define TM4C1236H6PM -//#define TM4C1237D5PM -//#define TM4C1237D5PZ -//#define TM4C1237E6PM -//#define TM4C1237E6PZ -//#define TM4C1237H6PGE -//#define TM4C1237H6PM -//#define TM4C1237H6PZ -//#define TM4C123AE6PM -//#define TM4C123AH6PM -//#define TM4C123BE6PM -//#define TM4C123BE6PZ -//#define TM4C123BH6PGE -//#define TM4C123BH6PM -//#define TM4C123BH6PZ -//#define TM4C123BH6ZRB -//#define TM4C123FE6PM -//#define TM4C123FH6PM -//#define TM4C123GE6PM -//#define TM4C123GE6PZ -//#define TM4C123GH6PGE -#define TM4C123GH6PM -//#define TM4C123GH6PZ -//#define TM4C123GH6ZRB -//#define TM4C123GH5ZXR - -/* - * Board oscillators-related settings. - */ -#define TIVA_XTAL_VALUE 16000000 - -/* - * IO pins assignments. - */ -#define GPIOA_UART0_RX 0 -#define GPIOA_UART0_TX 1 -#define GPIOA_SSI0_CLK 2 -#define GPIOA_PIN3 3 -#define GPIOA_SSI0_RX 4 -#define GPIOA_SSI0_TX 5 -#define GPIOA_PIN6 6 -#define GPIOA_PIN7 7 - -#define GPIOB_PIN0 0 -#define GPIOB_PIN1 1 -#define GPIOB_I2C0_SCL 2 -#define GPIOB_I2C0_SDA 3 -#define GPIOB_PIN4 4 -#define GPIOB_PIN5 5 -#define GPIOB_PIN6 6 -#define GPIOB_PIN7 7 - -#define GPIOC_TCK_SWCLK 0 -#define GPIOC_TMS_SWDIO 1 -#define GPIOC_TDI 2 -#define GPIOC_TDO_SWO 3 -#define GPIOC_PIN4 4 -#define GPIOC_PIN5 5 -#define GPIOC_PIN6 6 -#define GPIOC_PIN7 7 - -#define GPIOD_PIN0 0 -#define GPIOD_PIN1 1 -#define GPIOD_PIN2 2 -#define GPIOD_PIN3 3 -#define GPIOD_PIN4 4 -#define GPIOD_PIN5 5 -#define GPIOD_PIN6 6 -#define GPIOD_PIN7 7 - -#define GPIOE_PIN0 0 -#define GPIOE_PIN1 1 -#define GPIOE_PIN2 2 -#define GPIOE_PIN3 3 -#define GPIOE_PIN4 4 -#define GPIOE_PIN5 5 -#define GPIOE_PIN6 6 -#define GPIOE_PIN7 7 - -#define GPIOF_SW2 0 -#define GPIOF_LED_RED 1 -#define GPIOF_LED_BLUE 2 -#define GPIOF_LED_GREEN 3 -#define GPIOF_SW1 4 -#define GPIOF_PIN5 5 -#define GPIOF_PIN6 6 -#define GPIOF_PIN7 7 - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - */ -#define PIN_DATA_LOW(n) (0U << (n)) -#define PIN_DATA_HIGH(n) (1U << (n)) - -#define PIN_DIR_IN(n) (0U << (n)) -#define PIN_DIR_OUT(n) (1U << (n)) - -#define PIN_AFSEL_GPIO(n) (0U << (n)) -#define PIN_AFSEL_ALTERNATE(n) (1U << (n)) - -#define PIN_ODR_DISABLE(n) (0U << (n)) -#define PIN_ODR_ENABLE(n) (1U << (n)) - -#define PIN_PxR_DISABLE(n) (0U << (n)) -#define PIN_PxR_ENABLE(n) (1U << (n)) - -#define PIN_DEN_DISABLE(n) (0U << (n)) -#define PIN_DEN_ENABLE(n) (1U << (n)) - -#define PIN_AMSEL_DISABLE(n) (0U << (n)) -#define PIN_AMSEL_ENABLE(n) (1U << (n)) - -#define PIN_DRxR_DISABLE(n) (0U << (n)) -#define PIN_DRxR_ENABLE(n) (1U << (n)) - -#define PIN_SLR_DISABLE(n) (0U << (n)) -#define PIN_SLR_ENABLE(n) (1U << (n)) - -#define PIN_PCTL_MODE(n, mode) (mode << ((n) * 4)) - -/* - * GPIOA Setup: - * - * PA0 - UART0 RX () - * PA1 - UART0 TX () - * PA2 - PIN2 () - * PA3 - PIN3 () - * PA4 - PIN4 () - * PA5 - PIN5 () - * PA6 - PIN6 () - * PA7 - PIN7 () - */ -#define VAL_GPIOA_DATA (PIN_DATA_LOW(GPIOA_UART0_RX) | \ - PIN_DATA_LOW(GPIOA_UART0_TX) | \ - PIN_DATA_LOW(GPIOA_SSI0_CLK) | \ - PIN_DATA_LOW(GPIOA_PIN3) | \ - PIN_DATA_LOW(GPIOA_SSI0_RX) | \ - PIN_DATA_LOW(GPIOA_SSI0_TX) | \ - PIN_DATA_LOW(GPIOA_PIN6) | \ - PIN_DATA_LOW(GPIOA_PIN7)) - -#define VAL_GPIOA_DIR (PIN_DIR_IN(GPIOA_UART0_RX) | \ - PIN_DIR_IN(GPIOA_UART0_TX) | \ - PIN_DIR_IN(GPIOA_SSI0_CLK) | \ - PIN_DIR_IN(GPIOA_PIN3) | \ - PIN_DIR_IN(GPIOA_SSI0_RX) | \ - PIN_DIR_IN(GPIOA_SSI0_TX) | \ - PIN_DIR_IN(GPIOA_PIN6) | \ - PIN_DIR_IN(GPIOA_PIN7)) - -#define VAL_GPIOA_AFSEL (PIN_AFSEL_GPIO(GPIOA_UART0_RX) | \ - PIN_AFSEL_GPIO(GPIOA_UART0_TX) | \ - PIN_AFSEL_GPIO(GPIOA_SSI0_CLK) | \ - PIN_AFSEL_GPIO(GPIOA_PIN3) | \ - PIN_AFSEL_GPIO(GPIOA_SSI0_RX) | \ - PIN_AFSEL_GPIO(GPIOA_SSI0_TX) | \ - PIN_AFSEL_GPIO(GPIOA_PIN6) | \ - PIN_AFSEL_GPIO(GPIOA_PIN7)) - -#define VAL_GPIOA_ODR (PIN_ODR_DISABLE(GPIOA_UART0_RX) | \ - PIN_ODR_DISABLE(GPIOA_UART0_TX) | \ - PIN_ODR_DISABLE(GPIOA_SSI0_CLK) | \ - PIN_ODR_DISABLE(GPIOA_PIN3) | \ - PIN_ODR_DISABLE(GPIOA_SSI0_RX) | \ - PIN_ODR_DISABLE(GPIOA_SSI0_TX) | \ - PIN_ODR_DISABLE(GPIOA_PIN6) | \ - PIN_ODR_DISABLE(GPIOA_PIN7)) - -#define VAL_GPIOA_PUR (PIN_PxR_DISABLE(GPIOA_UART0_RX) | \ - PIN_PxR_DISABLE(GPIOA_UART0_TX) | \ - PIN_PxR_DISABLE(GPIOA_SSI0_CLK) | \ - PIN_PxR_DISABLE(GPIOA_PIN3) | \ - PIN_PxR_DISABLE(GPIOA_SSI0_RX) | \ - PIN_PxR_DISABLE(GPIOA_SSI0_TX) | \ - PIN_PxR_DISABLE(GPIOA_PIN6) | \ - PIN_PxR_DISABLE(GPIOA_PIN7)) - -#define VAL_GPIOA_PDR (PIN_PxR_DISABLE(GPIOA_UART0_RX) | \ - PIN_PxR_DISABLE(GPIOA_UART0_TX) | \ - PIN_PxR_DISABLE(GPIOA_SSI0_CLK) | \ - PIN_PxR_DISABLE(GPIOA_PIN3) | \ - PIN_PxR_DISABLE(GPIOA_SSI0_RX) | \ - PIN_PxR_DISABLE(GPIOA_SSI0_TX) | \ - PIN_PxR_DISABLE(GPIOA_PIN6) | \ - PIN_PxR_DISABLE(GPIOA_PIN7)) - -#define VAL_GPIOA_DEN (PIN_DEN_ENABLE(GPIOA_UART0_RX) | \ - PIN_DEN_ENABLE(GPIOA_UART0_TX) | \ - PIN_DEN_ENABLE(GPIOA_SSI0_CLK) | \ - PIN_DEN_ENABLE(GPIOA_PIN3) | \ - PIN_DEN_ENABLE(GPIOA_SSI0_RX) | \ - PIN_DEN_ENABLE(GPIOA_SSI0_TX) | \ - PIN_DEN_ENABLE(GPIOA_PIN6) | \ - PIN_DEN_ENABLE(GPIOA_PIN7)) - -#define VAL_GPIOA_AMSEL (PIN_AMSEL_DISABLE(GPIOA_UART0_RX) | \ - PIN_AMSEL_DISABLE(GPIOA_UART0_TX) | \ - PIN_AMSEL_DISABLE(GPIOA_SSI0_CLK) | \ - PIN_AMSEL_DISABLE(GPIOA_PIN3)) - -#define VAL_GPIOA_DR2R (PIN_DRxR_ENABLE(GPIOA_UART0_RX) | \ - PIN_DRxR_ENABLE(GPIOA_UART0_TX) | \ - PIN_DRxR_ENABLE(GPIOA_SSI0_CLK) | \ - PIN_DRxR_ENABLE(GPIOA_PIN3) | \ - PIN_DRxR_ENABLE(GPIOA_SSI0_RX) | \ - PIN_DRxR_ENABLE(GPIOA_SSI0_TX) | \ - PIN_DRxR_ENABLE(GPIOA_PIN6) | \ - PIN_DRxR_ENABLE(GPIOA_PIN7)) - -#define VAL_GPIOA_DR4R (PIN_DRxR_DISABLE(GPIOA_UART0_RX) | \ - PIN_DRxR_DISABLE(GPIOA_UART0_TX) | \ - PIN_DRxR_DISABLE(GPIOA_SSI0_CLK) | \ - PIN_DRxR_DISABLE(GPIOA_PIN3) | \ - PIN_DRxR_DISABLE(GPIOA_SSI0_RX) | \ - PIN_DRxR_DISABLE(GPIOA_SSI0_TX) | \ - PIN_DRxR_DISABLE(GPIOA_PIN6) | \ - PIN_DRxR_DISABLE(GPIOA_PIN7)) - -#define VAL_GPIOA_DR8R (PIN_DRxR_DISABLE(GPIOA_UART0_RX) | \ - PIN_DRxR_DISABLE(GPIOA_UART0_TX) | \ - PIN_DRxR_DISABLE(GPIOA_SSI0_CLK) | \ - PIN_DRxR_DISABLE(GPIOA_PIN3) | \ - PIN_DRxR_DISABLE(GPIOA_SSI0_RX) | \ - PIN_DRxR_DISABLE(GPIOA_SSI0_TX) | \ - PIN_DRxR_DISABLE(GPIOA_PIN6) | \ - PIN_DRxR_DISABLE(GPIOA_PIN7)) - - -#define VAL_GPIOA_SLR (PIN_SLR_DISABLE(GPIOA_UART0_RX) | \ - PIN_SLR_DISABLE(GPIOA_UART0_TX) | \ - PIN_SLR_DISABLE(GPIOA_SSI0_CLK) | \ - PIN_SLR_DISABLE(GPIOA_PIN3) | \ - PIN_SLR_DISABLE(GPIOA_SSI0_RX) | \ - PIN_SLR_DISABLE(GPIOA_SSI0_TX) | \ - PIN_SLR_DISABLE(GPIOA_PIN6) | \ - PIN_SLR_DISABLE(GPIOA_PIN7)) - -#define VAL_GPIOA_PCTL (PIN_PCTL_MODE(GPIOA_UART0_RX, 0) | \ - PIN_PCTL_MODE(GPIOA_UART0_TX, 0) | \ - PIN_PCTL_MODE(GPIOA_SSI0_CLK, 0) | \ - PIN_PCTL_MODE(GPIOA_PIN3, 0) | \ - PIN_PCTL_MODE(GPIOA_SSI0_RX, 0) | \ - PIN_PCTL_MODE(GPIOA_SSI0_TX, 0) | \ - PIN_PCTL_MODE(GPIOA_PIN6, 0) | \ - PIN_PCTL_MODE(GPIOA_PIN7, 0)) - -/* - * GPIOB Setup: - * - * PB0 - PIN0 () - * PB1 - PIN1 () - * PB2 - I2C0_SCL () - * PB3 - I2C0_SDA () - * PB4 - PIN4 () - * PB5 - PIN5 () - * PB6 - PIN6 () - * PB7 - PIN7 () - */ -#define VAL_GPIOB_DATA (PIN_DATA_LOW(GPIOB_PIN0) | \ - PIN_DATA_LOW(GPIOB_PIN1) | \ - PIN_DATA_LOW(GPIOB_I2C0_SCL) | \ - PIN_DATA_LOW(GPIOB_I2C0_SDA) | \ - PIN_DATA_LOW(GPIOB_PIN4) | \ - PIN_DATA_LOW(GPIOB_PIN5) | \ - PIN_DATA_LOW(GPIOB_PIN6) | \ - PIN_DATA_LOW(GPIOB_PIN7)) - -#define VAL_GPIOB_DIR (PIN_DIR_IN(GPIOB_PIN0) | \ - PIN_DIR_IN(GPIOB_PIN1) | \ - PIN_DIR_IN(GPIOB_I2C0_SCL) | \ - PIN_DIR_IN(GPIOB_I2C0_SDA) | \ - PIN_DIR_IN(GPIOB_PIN4) | \ - PIN_DIR_IN(GPIOB_PIN5) | \ - PIN_DIR_IN(GPIOB_PIN6) | \ - PIN_DIR_IN(GPIOB_PIN7)) - -#define VAL_GPIOB_AFSEL (PIN_AFSEL_GPIO(GPIOB_PIN0) | \ - PIN_AFSEL_GPIO(GPIOB_PIN1) | \ - PIN_AFSEL_GPIO(GPIOB_I2C0_SCL) | \ - PIN_AFSEL_GPIO(GPIOB_I2C0_SDA) | \ - PIN_AFSEL_GPIO(GPIOB_PIN4) | \ - PIN_AFSEL_GPIO(GPIOB_PIN5) | \ - PIN_AFSEL_GPIO(GPIOB_PIN6) | \ - PIN_AFSEL_GPIO(GPIOB_PIN7)) - -#define VAL_GPIOB_DR2R (PIN_DRxR_ENABLE(GPIOB_PIN0) | \ - PIN_DRxR_ENABLE(GPIOB_PIN1) | \ - PIN_DRxR_ENABLE(GPIOB_I2C0_SCL) | \ - PIN_DRxR_ENABLE(GPIOB_I2C0_SDA) | \ - PIN_DRxR_ENABLE(GPIOB_PIN4) | \ - PIN_DRxR_ENABLE(GPIOB_PIN5) | \ - PIN_DRxR_ENABLE(GPIOB_PIN6) | \ - PIN_DRxR_ENABLE(GPIOB_PIN7)) - -#define VAL_GPIOB_DR4R (PIN_DRxR_DISABLE(GPIOB_PIN0) | \ - PIN_DRxR_DISABLE(GPIOB_PIN1) | \ - PIN_DRxR_DISABLE(GPIOB_I2C0_SCL) | \ - PIN_DRxR_DISABLE(GPIOB_I2C0_SDA) | \ - PIN_DRxR_DISABLE(GPIOB_PIN4) | \ - PIN_DRxR_DISABLE(GPIOB_PIN5) | \ - PIN_DRxR_DISABLE(GPIOB_PIN6) | \ - PIN_DRxR_DISABLE(GPIOB_PIN7)) - -#define VAL_GPIOB_DR8R (PIN_DRxR_DISABLE(GPIOB_PIN0) | \ - PIN_DRxR_DISABLE(GPIOB_PIN1) | \ - PIN_DRxR_DISABLE(GPIOB_I2C0_SCL) | \ - PIN_DRxR_DISABLE(GPIOB_I2C0_SDA) | \ - PIN_DRxR_DISABLE(GPIOB_PIN4) | \ - PIN_DRxR_DISABLE(GPIOB_PIN5) | \ - PIN_DRxR_DISABLE(GPIOB_PIN6) | \ - PIN_DRxR_DISABLE(GPIOB_PIN7)) - -#define VAL_GPIOB_ODR (PIN_ODR_DISABLE(GPIOB_PIN0) | \ - PIN_ODR_DISABLE(GPIOB_PIN1) | \ - PIN_ODR_DISABLE(GPIOB_I2C0_SCL) | \ - PIN_ODR_DISABLE(GPIOB_I2C0_SDA) | \ - PIN_ODR_DISABLE(GPIOB_PIN4) | \ - PIN_ODR_DISABLE(GPIOB_PIN5) | \ - PIN_ODR_DISABLE(GPIOB_PIN6) | \ - PIN_ODR_DISABLE(GPIOB_PIN7)) - -#define VAL_GPIOB_PUR (PIN_PxR_DISABLE(GPIOB_PIN0) | \ - PIN_PxR_DISABLE(GPIOB_PIN1) | \ - PIN_PxR_DISABLE(GPIOB_I2C0_SCL) | \ - PIN_PxR_DISABLE(GPIOB_I2C0_SDA) | \ - PIN_PxR_DISABLE(GPIOB_PIN4) | \ - PIN_PxR_DISABLE(GPIOB_PIN5) | \ - PIN_PxR_DISABLE(GPIOB_PIN6) | \ - PIN_PxR_DISABLE(GPIOB_PIN7)) - -#define VAL_GPIOB_PDR (PIN_PxR_DISABLE(GPIOB_PIN0) | \ - PIN_PxR_DISABLE(GPIOB_PIN1) | \ - PIN_PxR_DISABLE(GPIOB_I2C0_SCL) | \ - PIN_PxR_DISABLE(GPIOB_I2C0_SDA) | \ - PIN_PxR_DISABLE(GPIOB_PIN4) | \ - PIN_PxR_DISABLE(GPIOB_PIN5) | \ - PIN_PxR_DISABLE(GPIOB_PIN6) | \ - PIN_PxR_DISABLE(GPIOB_PIN7)) - -#define VAL_GPIOB_SLR (PIN_SLR_DISABLE(GPIOB_PIN0) | \ - PIN_SLR_DISABLE(GPIOB_PIN1) | \ - PIN_SLR_DISABLE(GPIOB_I2C0_SCL) | \ - PIN_SLR_DISABLE(GPIOB_I2C0_SDA) | \ - PIN_SLR_DISABLE(GPIOB_PIN4) | \ - PIN_SLR_DISABLE(GPIOB_PIN5) | \ - PIN_SLR_DISABLE(GPIOB_PIN6) | \ - PIN_SLR_DISABLE(GPIOB_PIN7)) - -#define VAL_GPIOB_DEN (PIN_DEN_ENABLE(GPIOB_PIN0) | \ - PIN_DEN_ENABLE(GPIOB_PIN1) | \ - PIN_DEN_ENABLE(GPIOB_I2C0_SCL) | \ - PIN_DEN_ENABLE(GPIOB_I2C0_SDA) | \ - PIN_DEN_ENABLE(GPIOB_PIN4) | \ - PIN_DEN_ENABLE(GPIOB_PIN5) | \ - PIN_DEN_ENABLE(GPIOB_PIN6) | \ - PIN_DEN_ENABLE(GPIOB_PIN7)) - -#define VAL_GPIOB_AMSEL (PIN_AMSEL_DISABLE(GPIOB_PIN0) | \ - PIN_AMSEL_DISABLE(GPIOB_PIN1) | \ - PIN_AMSEL_DISABLE(GPIOB_I2C0_SCL) | \ - PIN_AMSEL_DISABLE(GPIOB_I2C0_SDA)) - -#define VAL_GPIOB_PCTL (PIN_PCTL_MODE(GPIOB_PIN0, 0) | \ - PIN_PCTL_MODE(GPIOB_PIN1, 0) | \ - PIN_PCTL_MODE(GPIOB_I2C0_SCL, 0) | \ - PIN_PCTL_MODE(GPIOB_I2C0_SDA, 0) | \ - PIN_PCTL_MODE(GPIOB_PIN4, 0) | \ - PIN_PCTL_MODE(GPIOB_PIN5, 0) | \ - PIN_PCTL_MODE(GPIOB_PIN6, 0) | \ - PIN_PCTL_MODE(GPIOB_PIN7, 0)) - -/* - * GPIOC Setup: - * - * PC0 - TCK_SWCLK (alternate 1) - * PC1 - TMS_SWDIO (alternate 1) - * PC2 - TDI (alternate 1) - * PC3 - TDO_SWO (alternate 1) - * PC4 - PIN4 () - * PC5 - PIN5 () - * PC6 - PIN6 () - * PC7 - PIN7 () - */ - -#define VAL_GPIOC_DATA (PIN_DATA_LOW(GPIOC_TCK_SWCLK) | \ - PIN_DATA_LOW(GPIOC_TMS_SWDIO) | \ - PIN_DATA_LOW(GPIOC_TDI) | \ - PIN_DATA_LOW(GPIOC_TDO_SWO) | \ - PIN_DATA_LOW(GPIOC_PIN4) | \ - PIN_DATA_LOW(GPIOC_PIN5) | \ - PIN_DATA_LOW(GPIOC_PIN6) | \ - PIN_DATA_LOW(GPIOC_PIN7)) - -#define VAL_GPIOC_DIR (PIN_DIR_IN(GPIOC_TCK_SWCLK) | \ - PIN_DIR_IN(GPIOC_TMS_SWDIO) | \ - PIN_DIR_IN(GPIOC_TDI) | \ - PIN_DIR_OUT(GPIOC_TDO_SWO) | \ - PIN_DIR_IN(GPIOC_PIN4) | \ - PIN_DIR_IN(GPIOC_PIN5) | \ - PIN_DIR_IN(GPIOC_PIN6) | \ - PIN_DIR_IN(GPIOC_PIN7)) - -#define VAL_GPIOC_AFSEL (PIN_AFSEL_ALTERNATE(GPIOC_TCK_SWCLK) | \ - PIN_AFSEL_ALTERNATE(GPIOC_TMS_SWDIO) | \ - PIN_AFSEL_ALTERNATE(GPIOC_TDI) | \ - PIN_AFSEL_ALTERNATE(GPIOC_TDO_SWO) | \ - PIN_AFSEL_GPIO(GPIOC_PIN4) | \ - PIN_AFSEL_GPIO(GPIOC_PIN5) | \ - PIN_AFSEL_GPIO(GPIOC_PIN6) | \ - PIN_AFSEL_GPIO(GPIOC_PIN7)) - -#define VAL_GPIOC_DR2R (PIN_DRxR_ENABLE(GPIOC_TCK_SWCLK) | \ - PIN_DRxR_ENABLE(GPIOC_TMS_SWDIO) | \ - PIN_DRxR_ENABLE(GPIOC_TDI) | \ - PIN_DRxR_ENABLE(GPIOC_TDO_SWO) | \ - PIN_DRxR_ENABLE(GPIOC_PIN4) | \ - PIN_DRxR_ENABLE(GPIOC_PIN5) | \ - PIN_DRxR_ENABLE(GPIOC_PIN6) | \ - PIN_DRxR_ENABLE(GPIOC_PIN7)) - -#define VAL_GPIOC_DR4R (PIN_DRxR_DISABLE(GPIOC_TCK_SWCLK) | \ - PIN_DRxR_DISABLE(GPIOC_TMS_SWDIO) | \ - PIN_DRxR_DISABLE(GPIOC_TDI) | \ - PIN_DRxR_DISABLE(GPIOC_TDO_SWO) | \ - PIN_DRxR_DISABLE(GPIOC_PIN4) | \ - PIN_DRxR_DISABLE(GPIOC_PIN5) | \ - PIN_DRxR_DISABLE(GPIOC_PIN6) | \ - PIN_DRxR_DISABLE(GPIOC_PIN7)) - -#define VAL_GPIOC_DR8R (PIN_DRxR_DISABLE(GPIOC_TCK_SWCLK) | \ - PIN_DRxR_DISABLE(GPIOC_TMS_SWDIO) | \ - PIN_DRxR_DISABLE(GPIOC_TDI) | \ - PIN_DRxR_DISABLE(GPIOC_TDO_SWO) | \ - PIN_DRxR_DISABLE(GPIOC_PIN4) | \ - PIN_DRxR_DISABLE(GPIOC_PIN5) | \ - PIN_DRxR_DISABLE(GPIOC_PIN6) | \ - PIN_DRxR_DISABLE(GPIOC_PIN7)) - -#define VAL_GPIOC_ODR (PIN_ODR_DISABLE(GPIOC_TCK_SWCLK) | \ - PIN_ODR_DISABLE(GPIOC_TMS_SWDIO) | \ - PIN_ODR_DISABLE(GPIOC_TDI) | \ - PIN_ODR_DISABLE(GPIOC_TDO_SWO) | \ - PIN_ODR_DISABLE(GPIOC_PIN4) | \ - PIN_ODR_DISABLE(GPIOC_PIN5) | \ - PIN_ODR_DISABLE(GPIOC_PIN6) | \ - PIN_ODR_DISABLE(GPIOC_PIN7)) - -#define VAL_GPIOC_PUR (PIN_PxR_DISABLE(GPIOC_TCK_SWCLK) | \ - PIN_PxR_DISABLE(GPIOC_TMS_SWDIO) | \ - PIN_PxR_DISABLE(GPIOC_TDI) | \ - PIN_PxR_DISABLE(GPIOC_TDO_SWO) | \ - PIN_PxR_DISABLE(GPIOC_PIN4) | \ - PIN_PxR_DISABLE(GPIOC_PIN5) | \ - PIN_PxR_DISABLE(GPIOC_PIN6) | \ - PIN_PxR_DISABLE(GPIOC_PIN7)) - -#define VAL_GPIOC_PDR (PIN_PxR_DISABLE(GPIOC_TCK_SWCLK) | \ - PIN_PxR_DISABLE(GPIOC_TMS_SWDIO) | \ - PIN_PxR_DISABLE(GPIOC_TDI) | \ - PIN_PxR_DISABLE(GPIOC_TDO_SWO) | \ - PIN_PxR_DISABLE(GPIOC_PIN4) | \ - PIN_PxR_DISABLE(GPIOC_PIN5) | \ - PIN_PxR_DISABLE(GPIOC_PIN6) | \ - PIN_PxR_DISABLE(GPIOC_PIN7)) - -#define VAL_GPIOC_SLR (PIN_SLR_DISABLE(GPIOC_TCK_SWCLK) | \ - PIN_SLR_DISABLE(GPIOC_TMS_SWDIO) | \ - PIN_SLR_DISABLE(GPIOC_TDI) | \ - PIN_SLR_DISABLE(GPIOC_TDO_SWO) | \ - PIN_SLR_DISABLE(GPIOC_PIN4) | \ - PIN_SLR_DISABLE(GPIOC_PIN5) | \ - PIN_SLR_DISABLE(GPIOC_PIN6) | \ - PIN_SLR_DISABLE(GPIOC_PIN7)) - -#define VAL_GPIOC_DEN (PIN_DEN_ENABLE(GPIOC_TCK_SWCLK) | \ - PIN_DEN_ENABLE(GPIOC_TMS_SWDIO) | \ - PIN_DEN_ENABLE(GPIOC_TDI) | \ - PIN_DEN_ENABLE(GPIOC_TDO_SWO) | \ - PIN_DEN_ENABLE(GPIOC_PIN4) | \ - PIN_DEN_ENABLE(GPIOC_PIN5) | \ - PIN_DEN_ENABLE(GPIOC_PIN6) | \ - PIN_DEN_ENABLE(GPIOC_PIN7)) - -#define VAL_GPIOC_AMSEL (PIN_AMSEL_DISABLE(GPIOC_TCK_SWCLK) | \ - PIN_AMSEL_DISABLE(GPIOC_TMS_SWDIO) | \ - PIN_AMSEL_DISABLE(GPIOC_TDI) | \ - PIN_AMSEL_DISABLE(GPIOC_TDO_SWO)) - -#define VAL_GPIOC_PCTL (PIN_PCTL_MODE(GPIOC_TCK_SWCLK, 1) | \ - PIN_PCTL_MODE(GPIOC_TMS_SWDIO, 1) | \ - PIN_PCTL_MODE(GPIOC_TDI, 1) | \ - PIN_PCTL_MODE(GPIOC_TDO_SWO, 1) | \ - PIN_PCTL_MODE(GPIOC_PIN4, 0) | \ - PIN_PCTL_MODE(GPIOC_PIN5, 0) | \ - PIN_PCTL_MODE(GPIOC_PIN6, 0) | \ - PIN_PCTL_MODE(GPIOC_PIN7, 0)) - -/* - * GPIOD Setup: - * - * PD0 - PIN0 () - * PD1 - PIN1 () - * PD2 - PIN2 () - * PD3 - PIN3 () - * PD4 - PIN4 () - * PD5 - PIN5 () - * PD6 - PIN6 () - * PD7 - PIN7 () - */ -#define VAL_GPIOD_DATA (PIN_DATA_LOW(GPIOD_PIN0) | \ - PIN_DATA_LOW(GPIOD_PIN1) | \ - PIN_DATA_LOW(GPIOD_PIN2) | \ - PIN_DATA_LOW(GPIOD_PIN3) | \ - PIN_DATA_LOW(GPIOD_PIN4) | \ - PIN_DATA_LOW(GPIOD_PIN5) | \ - PIN_DATA_LOW(GPIOD_PIN6) | \ - PIN_DATA_LOW(GPIOD_PIN7)) - -#define VAL_GPIOD_DIR (PIN_DIR_IN(GPIOD_PIN0) | \ - PIN_DIR_IN(GPIOD_PIN1) | \ - PIN_DIR_IN(GPIOD_PIN2) | \ - PIN_DIR_IN(GPIOD_PIN3) | \ - PIN_DIR_IN(GPIOD_PIN4) | \ - PIN_DIR_IN(GPIOD_PIN5) | \ - PIN_DIR_IN(GPIOD_PIN6) | \ - PIN_DIR_IN(GPIOD_PIN7)) - -#define VAL_GPIOD_AFSEL (PIN_AFSEL_GPIO(GPIOD_PIN0) | \ - PIN_AFSEL_GPIO(GPIOD_PIN1) | \ - PIN_AFSEL_GPIO(GPIOD_PIN2) | \ - PIN_AFSEL_GPIO(GPIOD_PIN3) | \ - PIN_AFSEL_GPIO(GPIOD_PIN4) | \ - PIN_AFSEL_GPIO(GPIOD_PIN5) | \ - PIN_AFSEL_GPIO(GPIOD_PIN6) | \ - PIN_AFSEL_GPIO(GPIOD_PIN7)) - -#define VAL_GPIOD_DR2R (PIN_DRxR_ENABLE(GPIOD_PIN0) | \ - PIN_DRxR_ENABLE(GPIOD_PIN1) | \ - PIN_DRxR_ENABLE(GPIOD_PIN2) | \ - PIN_DRxR_ENABLE(GPIOD_PIN3) | \ - PIN_DRxR_ENABLE(GPIOD_PIN4) | \ - PIN_DRxR_ENABLE(GPIOD_PIN5) | \ - PIN_DRxR_ENABLE(GPIOD_PIN6) | \ - PIN_DRxR_ENABLE(GPIOD_PIN7)) - -#define VAL_GPIOD_DR4R (PIN_DRxR_DISABLE(GPIOD_PIN0) | \ - PIN_DRxR_DISABLE(GPIOD_PIN1) | \ - PIN_DRxR_DISABLE(GPIOD_PIN2) | \ - PIN_DRxR_DISABLE(GPIOD_PIN3) | \ - PIN_DRxR_DISABLE(GPIOD_PIN4) | \ - PIN_DRxR_DISABLE(GPIOD_PIN5) | \ - PIN_DRxR_DISABLE(GPIOD_PIN6) | \ - PIN_DRxR_DISABLE(GPIOD_PIN7)) - -#define VAL_GPIOD_DR8R (PIN_DRxR_DISABLE(GPIOD_PIN0) | \ - PIN_DRxR_DISABLE(GPIOD_PIN1) | \ - PIN_DRxR_DISABLE(GPIOD_PIN2) | \ - PIN_DRxR_DISABLE(GPIOD_PIN3) | \ - PIN_DRxR_DISABLE(GPIOD_PIN4) | \ - PIN_DRxR_DISABLE(GPIOD_PIN5) | \ - PIN_DRxR_DISABLE(GPIOD_PIN6) | \ - PIN_DRxR_DISABLE(GPIOD_PIN7)) - -#define VAL_GPIOD_ODR (PIN_ODR_DISABLE(GPIOD_PIN0) | \ - PIN_ODR_DISABLE(GPIOD_PIN1) | \ - PIN_ODR_DISABLE(GPIOD_PIN2) | \ - PIN_ODR_DISABLE(GPIOD_PIN3) | \ - PIN_ODR_DISABLE(GPIOD_PIN4) | \ - PIN_ODR_DISABLE(GPIOD_PIN5) | \ - PIN_ODR_DISABLE(GPIOD_PIN6) | \ - PIN_ODR_DISABLE(GPIOD_PIN7)) - -#define VAL_GPIOD_PUR (PIN_PxR_DISABLE(GPIOD_PIN0) | \ - PIN_PxR_DISABLE(GPIOD_PIN1) | \ - PIN_PxR_DISABLE(GPIOD_PIN2) | \ - PIN_PxR_DISABLE(GPIOD_PIN3) | \ - PIN_PxR_DISABLE(GPIOD_PIN4) | \ - PIN_PxR_DISABLE(GPIOD_PIN5) | \ - PIN_PxR_DISABLE(GPIOD_PIN6) | \ - PIN_PxR_DISABLE(GPIOD_PIN7)) - -#define VAL_GPIOD_PDR (PIN_PxR_DISABLE(GPIOD_PIN0) | \ - PIN_PxR_DISABLE(GPIOD_PIN1) | \ - PIN_PxR_DISABLE(GPIOD_PIN2) | \ - PIN_PxR_DISABLE(GPIOD_PIN3) | \ - PIN_PxR_DISABLE(GPIOD_PIN4) | \ - PIN_PxR_DISABLE(GPIOD_PIN5) | \ - PIN_PxR_DISABLE(GPIOD_PIN6) | \ - PIN_PxR_DISABLE(GPIOD_PIN7)) - -#define VAL_GPIOD_SLR (PIN_SLR_DISABLE(GPIOD_PIN0) | \ - PIN_SLR_DISABLE(GPIOD_PIN1) | \ - PIN_SLR_DISABLE(GPIOD_PIN2) | \ - PIN_SLR_DISABLE(GPIOD_PIN3) | \ - PIN_SLR_DISABLE(GPIOD_PIN4) | \ - PIN_SLR_DISABLE(GPIOD_PIN5) | \ - PIN_SLR_DISABLE(GPIOD_PIN6) | \ - PIN_SLR_DISABLE(GPIOD_PIN7)) - -#define VAL_GPIOD_DEN (PIN_DEN_ENABLE(GPIOD_PIN0) | \ - PIN_DEN_ENABLE(GPIOD_PIN1) | \ - PIN_DEN_ENABLE(GPIOD_PIN2) | \ - PIN_DEN_ENABLE(GPIOD_PIN3) | \ - PIN_DEN_ENABLE(GPIOD_PIN4) | \ - PIN_DEN_ENABLE(GPIOD_PIN5) | \ - PIN_DEN_ENABLE(GPIOD_PIN6) | \ - PIN_DEN_ENABLE(GPIOD_PIN7)) - -#define VAL_GPIOD_AMSEL (PIN_AMSEL_DISABLE(GPIOD_PIN0) | \ - PIN_AMSEL_DISABLE(GPIOD_PIN1) | \ - PIN_AMSEL_DISABLE(GPIOD_PIN2) | \ - PIN_AMSEL_DISABLE(GPIOD_PIN3)) - -#define VAL_GPIOD_PCTL (PIN_PCTL_MODE(GPIOD_PIN0, 0) | \ - PIN_PCTL_MODE(GPIOD_PIN1, 0) | \ - PIN_PCTL_MODE(GPIOD_PIN2, 0) | \ - PIN_PCTL_MODE(GPIOD_PIN3, 0) | \ - PIN_PCTL_MODE(GPIOD_PIN4, 0) | \ - PIN_PCTL_MODE(GPIOD_PIN5, 0) | \ - PIN_PCTL_MODE(GPIOD_PIN6, 0) | \ - PIN_PCTL_MODE(GPIOD_PIN7, 0)) - -/* - * GPIOE Setup: - * - * PE0 - PIN0 () - * PE1 - PIN1 () - * PE2 - PIN2 () - * PE3 - PIN3 () - * PE4 - PIN4 () - * PE5 - PIN5 () - * PE6 - PIN6 () - * PE7 - PIN7 () - */ -#define VAL_GPIOE_DATA (PIN_DATA_LOW(GPIOE_PIN0) | \ - PIN_DATA_LOW(GPIOE_PIN1) | \ - PIN_DATA_LOW(GPIOE_PIN2) | \ - PIN_DATA_LOW(GPIOE_PIN3) | \ - PIN_DATA_LOW(GPIOE_PIN4) | \ - PIN_DATA_LOW(GPIOE_PIN5) | \ - PIN_DATA_LOW(GPIOE_PIN6) | \ - PIN_DATA_LOW(GPIOE_PIN7)) - -#define VAL_GPIOE_DIR (PIN_DIR_IN(GPIOE_PIN0) | \ - PIN_DIR_IN(GPIOE_PIN1) | \ - PIN_DIR_IN(GPIOE_PIN2) | \ - PIN_DIR_IN(GPIOE_PIN3) | \ - PIN_DIR_IN(GPIOE_PIN4) | \ - PIN_DIR_IN(GPIOE_PIN5) | \ - PIN_DIR_IN(GPIOE_PIN6) | \ - PIN_DIR_IN(GPIOE_PIN7)) - -#define VAL_GPIOE_AFSEL (PIN_AFSEL_GPIO(GPIOE_PIN0) | \ - PIN_AFSEL_GPIO(GPIOE_PIN1) | \ - PIN_AFSEL_GPIO(GPIOE_PIN2) | \ - PIN_AFSEL_GPIO(GPIOE_PIN3) | \ - PIN_AFSEL_GPIO(GPIOE_PIN4) | \ - PIN_AFSEL_GPIO(GPIOE_PIN5) | \ - PIN_AFSEL_GPIO(GPIOE_PIN6) | \ - PIN_AFSEL_GPIO(GPIOE_PIN7)) - -#define VAL_GPIOE_DR2R (PIN_DRxR_ENABLE(GPIOE_PIN0) | \ - PIN_DRxR_ENABLE(GPIOE_PIN1) | \ - PIN_DRxR_ENABLE(GPIOE_PIN2) | \ - PIN_DRxR_ENABLE(GPIOE_PIN3) | \ - PIN_DRxR_ENABLE(GPIOE_PIN4) | \ - PIN_DRxR_ENABLE(GPIOE_PIN5) | \ - PIN_DRxR_ENABLE(GPIOE_PIN6) | \ - PIN_DRxR_ENABLE(GPIOE_PIN7)) - -#define VAL_GPIOE_DR4R (PIN_DRxR_DISABLE(GPIOE_PIN0) | \ - PIN_DRxR_DISABLE(GPIOE_PIN1) | \ - PIN_DRxR_DISABLE(GPIOE_PIN2) | \ - PIN_DRxR_DISABLE(GPIOE_PIN3) | \ - PIN_DRxR_DISABLE(GPIOE_PIN4) | \ - PIN_DRxR_DISABLE(GPIOE_PIN5) | \ - PIN_DRxR_DISABLE(GPIOE_PIN6) | \ - PIN_DRxR_DISABLE(GPIOE_PIN7)) - -#define VAL_GPIOE_DR8R (PIN_DRxR_DISABLE(GPIOE_PIN0) | \ - PIN_DRxR_DISABLE(GPIOE_PIN1) | \ - PIN_DRxR_DISABLE(GPIOE_PIN2) | \ - PIN_DRxR_DISABLE(GPIOE_PIN3) | \ - PIN_DRxR_DISABLE(GPIOE_PIN4) | \ - PIN_DRxR_DISABLE(GPIOE_PIN5) | \ - PIN_DRxR_DISABLE(GPIOE_PIN6) | \ - PIN_DRxR_DISABLE(GPIOE_PIN7)) - -#define VAL_GPIOE_ODR (PIN_ODR_DISABLE(GPIOE_PIN0) | \ - PIN_ODR_DISABLE(GPIOE_PIN1) | \ - PIN_ODR_DISABLE(GPIOE_PIN2) | \ - PIN_ODR_DISABLE(GPIOE_PIN3) | \ - PIN_ODR_DISABLE(GPIOE_PIN4) | \ - PIN_ODR_DISABLE(GPIOE_PIN5) | \ - PIN_ODR_DISABLE(GPIOE_PIN6) | \ - PIN_ODR_DISABLE(GPIOE_PIN7)) - -#define VAL_GPIOE_PUR (PIN_PxR_DISABLE(GPIOE_PIN0) | \ - PIN_PxR_DISABLE(GPIOE_PIN1) | \ - PIN_PxR_DISABLE(GPIOE_PIN2) | \ - PIN_PxR_DISABLE(GPIOE_PIN3) | \ - PIN_PxR_DISABLE(GPIOE_PIN4) | \ - PIN_PxR_DISABLE(GPIOE_PIN5) | \ - PIN_PxR_DISABLE(GPIOE_PIN6) | \ - PIN_PxR_DISABLE(GPIOE_PIN7)) - -#define VAL_GPIOE_PDR (PIN_PxR_DISABLE(GPIOE_PIN0) | \ - PIN_PxR_DISABLE(GPIOE_PIN1) | \ - PIN_PxR_DISABLE(GPIOE_PIN2) | \ - PIN_PxR_DISABLE(GPIOE_PIN3) | \ - PIN_PxR_DISABLE(GPIOE_PIN4) | \ - PIN_PxR_DISABLE(GPIOE_PIN5) | \ - PIN_PxR_DISABLE(GPIOE_PIN6) | \ - PIN_PxR_DISABLE(GPIOE_PIN7)) - -#define VAL_GPIOE_SLR (PIN_SLR_DISABLE(GPIOE_PIN0) | \ - PIN_SLR_DISABLE(GPIOE_PIN1) | \ - PIN_SLR_DISABLE(GPIOE_PIN2) | \ - PIN_SLR_DISABLE(GPIOE_PIN3) | \ - PIN_SLR_DISABLE(GPIOE_PIN4) | \ - PIN_SLR_DISABLE(GPIOE_PIN5) | \ - PIN_SLR_DISABLE(GPIOE_PIN6) | \ - PIN_SLR_DISABLE(GPIOE_PIN7)) - -#define VAL_GPIOE_DEN (PIN_DEN_ENABLE(GPIOE_PIN0) | \ - PIN_DEN_ENABLE(GPIOE_PIN1) | \ - PIN_DEN_ENABLE(GPIOE_PIN2) | \ - PIN_DEN_ENABLE(GPIOE_PIN3) | \ - PIN_DEN_ENABLE(GPIOE_PIN4) | \ - PIN_DEN_ENABLE(GPIOE_PIN5) | \ - PIN_DEN_ENABLE(GPIOE_PIN6) | \ - PIN_DEN_ENABLE(GPIOE_PIN7)) - -#define VAL_GPIOE_AMSEL (PIN_AMSEL_DISABLE(GPIOE_PIN0) | \ - PIN_AMSEL_DISABLE(GPIOE_PIN1) | \ - PIN_AMSEL_DISABLE(GPIOE_PIN2) | \ - PIN_AMSEL_DISABLE(GPIOE_PIN3)) - -#define VAL_GPIOE_PCTL (PIN_PCTL_MODE(GPIOE_PIN0, 0) | \ - PIN_PCTL_MODE(GPIOE_PIN1, 0) | \ - PIN_PCTL_MODE(GPIOE_PIN2, 0) | \ - PIN_PCTL_MODE(GPIOE_PIN3, 0) | \ - PIN_PCTL_MODE(GPIOE_PIN4, 0) | \ - PIN_PCTL_MODE(GPIOE_PIN5, 0) | \ - PIN_PCTL_MODE(GPIOE_PIN6, 0) | \ - PIN_PCTL_MODE(GPIOE_PIN7, 0)) - -/* - * GPIOF Setup: - * - * PF0 - SW2 () - * PF1 - LED_RED () - * PF2 - LED_BLUE () - * PF3 - LED_GREEN () - * PF4 - SW1 () - * PF5 - PIN5 () - * PF6 - PIN6 () - * PF7 - PIN7 () - */ - -#define VAL_GPIOF_DATA (PIN_DATA_LOW(GPIOF_SW2) | \ - PIN_DATA_LOW(GPIOF_LED_RED) | \ - PIN_DATA_LOW(GPIOF_LED_BLUE) | \ - PIN_DATA_LOW(GPIOF_LED_GREEN) | \ - PIN_DATA_LOW(GPIOF_SW1) | \ - PIN_DATA_LOW(GPIOF_PIN5) | \ - PIN_DATA_LOW(GPIOF_PIN6) | \ - PIN_DATA_LOW(GPIOF_PIN7)) - -#define VAL_GPIOF_DIR (PIN_DIR_IN(GPIOF_SW2) | \ - PIN_DIR_IN(GPIOF_LED_RED) | \ - PIN_DIR_IN(GPIOF_LED_BLUE) | \ - PIN_DIR_IN(GPIOF_LED_GREEN) | \ - PIN_DIR_IN(GPIOF_SW1) | \ - PIN_DIR_IN(GPIOF_PIN5) | \ - PIN_DIR_IN(GPIOF_PIN6) | \ - PIN_DIR_IN(GPIOF_PIN7)) - -#define VAL_GPIOF_AFSEL (PIN_AFSEL_GPIO(GPIOF_SW2) | \ - PIN_AFSEL_GPIO(GPIOF_LED_RED) | \ - PIN_AFSEL_GPIO(GPIOF_LED_BLUE) | \ - PIN_AFSEL_GPIO(GPIOF_LED_GREEN) | \ - PIN_AFSEL_GPIO(GPIOF_SW1) | \ - PIN_AFSEL_GPIO(GPIOF_PIN5) | \ - PIN_AFSEL_GPIO(GPIOF_PIN6) | \ - PIN_AFSEL_GPIO(GPIOF_PIN7)) - -#define VAL_GPIOF_DR2R (PIN_DRxR_ENABLE(GPIOF_SW2) | \ - PIN_DRxR_ENABLE(GPIOF_LED_RED) | \ - PIN_DRxR_ENABLE(GPIOF_LED_BLUE) | \ - PIN_DRxR_ENABLE(GPIOF_LED_GREEN) | \ - PIN_DRxR_ENABLE(GPIOF_SW1) | \ - PIN_DRxR_ENABLE(GPIOF_PIN5) | \ - PIN_DRxR_ENABLE(GPIOF_PIN6) | \ - PIN_DRxR_ENABLE(GPIOF_PIN7)) - -#define VAL_GPIOF_DR4R (PIN_DRxR_DISABLE(GPIOF_SW2) | \ - PIN_DRxR_DISABLE(GPIOF_LED_RED) | \ - PIN_DRxR_DISABLE(GPIOF_LED_BLUE) | \ - PIN_DRxR_DISABLE(GPIOF_LED_GREEN) | \ - PIN_DRxR_DISABLE(GPIOF_SW1) | \ - PIN_DRxR_DISABLE(GPIOF_PIN5) | \ - PIN_DRxR_DISABLE(GPIOF_PIN6) | \ - PIN_DRxR_DISABLE(GPIOF_PIN7)) - -#define VAL_GPIOF_DR8R (PIN_DRxR_DISABLE(GPIOF_SW2) | \ - PIN_DRxR_DISABLE(GPIOF_LED_RED) | \ - PIN_DRxR_DISABLE(GPIOF_LED_BLUE) | \ - PIN_DRxR_DISABLE(GPIOF_LED_GREEN) | \ - PIN_DRxR_DISABLE(GPIOF_SW1) | \ - PIN_DRxR_DISABLE(GPIOF_PIN5) | \ - PIN_DRxR_DISABLE(GPIOF_PIN6) | \ - PIN_DRxR_DISABLE(GPIOF_PIN7)) - -#define VAL_GPIOF_ODR (PIN_ODR_DISABLE(GPIOF_SW2) | \ - PIN_ODR_DISABLE(GPIOF_LED_RED) | \ - PIN_ODR_DISABLE(GPIOF_LED_BLUE) | \ - PIN_ODR_DISABLE(GPIOF_LED_GREEN) | \ - PIN_ODR_DISABLE(GPIOF_SW1) | \ - PIN_ODR_DISABLE(GPIOF_PIN5) | \ - PIN_ODR_DISABLE(GPIOF_PIN6) | \ - PIN_ODR_DISABLE(GPIOF_PIN7)) - -#define VAL_GPIOF_PUR (PIN_PxR_DISABLE(GPIOF_SW2) | \ - PIN_PxR_DISABLE(GPIOF_LED_RED) | \ - PIN_PxR_DISABLE(GPIOF_LED_BLUE) | \ - PIN_PxR_DISABLE(GPIOF_LED_GREEN) | \ - PIN_PxR_DISABLE(GPIOF_SW1) | \ - PIN_PxR_DISABLE(GPIOF_PIN5) | \ - PIN_PxR_DISABLE(GPIOF_PIN6) | \ - PIN_PxR_DISABLE(GPIOF_PIN7)) - -#define VAL_GPIOF_PDR (PIN_PxR_DISABLE(GPIOF_SW2) | \ - PIN_PxR_DISABLE(GPIOF_LED_RED) | \ - PIN_PxR_DISABLE(GPIOF_LED_BLUE) | \ - PIN_PxR_DISABLE(GPIOF_LED_GREEN) | \ - PIN_PxR_DISABLE(GPIOF_SW1) | \ - PIN_PxR_DISABLE(GPIOF_PIN5) | \ - PIN_PxR_DISABLE(GPIOF_PIN6) | \ - PIN_PxR_DISABLE(GPIOF_PIN7)) - -#define VAL_GPIOF_SLR (PIN_SLR_DISABLE(GPIOF_SW2) | \ - PIN_SLR_DISABLE(GPIOF_LED_RED) | \ - PIN_SLR_DISABLE(GPIOF_LED_BLUE) | \ - PIN_SLR_DISABLE(GPIOF_LED_GREEN) | \ - PIN_SLR_DISABLE(GPIOF_SW1) | \ - PIN_SLR_DISABLE(GPIOF_PIN5) | \ - PIN_SLR_DISABLE(GPIOF_PIN6) | \ - PIN_SLR_DISABLE(GPIOF_PIN7)) - -#define VAL_GPIOF_DEN (PIN_DEN_ENABLE(GPIOF_SW2) | \ - PIN_DEN_ENABLE(GPIOF_LED_RED) | \ - PIN_DEN_ENABLE(GPIOF_LED_BLUE) | \ - PIN_DEN_ENABLE(GPIOF_LED_GREEN) | \ - PIN_DEN_ENABLE(GPIOF_SW1) | \ - PIN_DEN_ENABLE(GPIOF_PIN5) | \ - PIN_DEN_ENABLE(GPIOF_PIN6) | \ - PIN_DEN_ENABLE(GPIOF_PIN7)) - -#define VAL_GPIOF_AMSEL (PIN_AMSEL_DISABLE(GPIOF_SW2) | \ - PIN_AMSEL_DISABLE(GPIOF_LED_RED) | \ - PIN_AMSEL_DISABLE(GPIOF_LED_BLUE) | \ - PIN_AMSEL_DISABLE(GPIOF_LED_GREEN)) - -#define VAL_GPIOF_PCTL (PIN_PCTL_MODE(GPIOF_SW2, 0) | \ - PIN_PCTL_MODE(GPIOF_LED_RED, 0) | \ - PIN_PCTL_MODE(GPIOF_LED_BLUE, 0) | \ - PIN_PCTL_MODE(GPIOF_LED_GREEN, 0) | \ - PIN_PCTL_MODE(GPIOF_SW1, 0) | \ - PIN_PCTL_MODE(GPIOF_PIN5, 0) | \ - PIN_PCTL_MODE(GPIOF_PIN6, 0) | \ - PIN_PCTL_MODE(GPIOF_PIN7, 0)) - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk deleted file mode 100644 index 8232a30..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c - -# Required include directories -BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C123G_LAUNCHPAD diff --git a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c b/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c deleted file mode 100644 index 437dcf8..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. - */ -#if HAL_USE_PAL || defined(__DOXYGEN__) -const PALConfig pal_default_config = -{ - {VAL_GPIOA_DATA, VAL_GPIOA_DIR, VAL_GPIOA_AFSEL, VAL_GPIOA_DR2R, - VAL_GPIOA_DR4R, VAL_GPIOA_DR8R, VAL_GPIOA_ODR, VAL_GPIOA_PUR, - VAL_GPIOA_PDR, VAL_GPIOA_SLR, VAL_GPIOA_DEN, VAL_GPIOA_AMSEL, - VAL_GPIOA_PCTL}, - {VAL_GPIOB_DATA, VAL_GPIOB_DIR, VAL_GPIOB_AFSEL, VAL_GPIOB_DR2R, - VAL_GPIOB_DR4R, VAL_GPIOB_DR8R, VAL_GPIOB_ODR, VAL_GPIOB_PUR, - VAL_GPIOB_PDR, VAL_GPIOB_SLR, VAL_GPIOB_DEN, VAL_GPIOB_AMSEL, - VAL_GPIOB_PCTL}, - {VAL_GPIOC_DATA, VAL_GPIOC_DIR, VAL_GPIOC_AFSEL, VAL_GPIOC_DR2R, - VAL_GPIOC_DR4R, VAL_GPIOC_DR8R, VAL_GPIOC_ODR, VAL_GPIOC_PUR, - VAL_GPIOC_PDR, VAL_GPIOC_SLR, VAL_GPIOC_DEN, VAL_GPIOC_AMSEL, - VAL_GPIOC_PCTL}, - {VAL_GPIOD_DATA, VAL_GPIOD_DIR, VAL_GPIOD_AFSEL, VAL_GPIOD_DR2R, - VAL_GPIOD_DR4R, VAL_GPIOD_DR8R, VAL_GPIOD_ODR, VAL_GPIOD_PUR, - VAL_GPIOD_PDR, VAL_GPIOD_SLR, VAL_GPIOD_DEN, VAL_GPIOD_AMSEL, - VAL_GPIOD_PCTL}, - {VAL_GPIOE_DATA, VAL_GPIOE_DIR, VAL_GPIOE_AFSEL, VAL_GPIOE_DR2R, - VAL_GPIOE_DR4R, VAL_GPIOE_DR8R, VAL_GPIOE_ODR, VAL_GPIOE_PUR, - VAL_GPIOE_PDR, VAL_GPIOE_SLR, VAL_GPIOE_DEN, VAL_GPIOE_AMSEL, - VAL_GPIOE_PCTL}, - {VAL_GPIOF_DATA, VAL_GPIOF_DIR, VAL_GPIOF_AFSEL, VAL_GPIOF_DR2R, - VAL_GPIOF_DR4R, VAL_GPIOF_DR8R, VAL_GPIOF_ODR, VAL_GPIOF_PUR, - VAL_GPIOF_PDR, VAL_GPIOF_SLR, VAL_GPIOF_DEN, VAL_GPIOF_AMSEL, - VAL_GPIOF_PCTL}, - {VAL_GPIOG_DATA, VAL_GPIOG_DIR, VAL_GPIOG_AFSEL, VAL_GPIOG_DR2R, - VAL_GPIOG_DR4R, VAL_GPIOG_DR8R, VAL_GPIOG_ODR, VAL_GPIOG_PUR, - VAL_GPIOG_PDR, VAL_GPIOG_SLR, VAL_GPIOG_DEN, VAL_GPIOG_AMSEL, - VAL_GPIOG_PCTL}, - {VAL_GPIOH_DATA, VAL_GPIOH_DIR, VAL_GPIOH_AFSEL, VAL_GPIOH_DR2R, - VAL_GPIOH_DR4R, VAL_GPIOH_DR8R, VAL_GPIOH_ODR, VAL_GPIOH_PUR, - VAL_GPIOH_PDR, VAL_GPIOH_SLR, VAL_GPIOH_DEN, VAL_GPIOH_AMSEL, - VAL_GPIOH_PCTL}, - {VAL_GPIOJ_DATA, VAL_GPIOJ_DIR, VAL_GPIOJ_AFSEL, VAL_GPIOJ_DR2R, - VAL_GPIOJ_DR4R, VAL_GPIOJ_DR8R, VAL_GPIOJ_ODR, VAL_GPIOJ_PUR, - VAL_GPIOJ_PDR, VAL_GPIOJ_SLR, VAL_GPIOJ_DEN, VAL_GPIOJ_AMSEL, - VAL_GPIOJ_PCTL}, - {VAL_GPIOK_DATA, VAL_GPIOK_DIR, VAL_GPIOK_AFSEL, VAL_GPIOK_DR2R, - VAL_GPIOK_DR4R, VAL_GPIOK_DR8R, VAL_GPIOK_ODR, VAL_GPIOK_PUR, - VAL_GPIOK_PDR, VAL_GPIOK_SLR, VAL_GPIOK_DEN, VAL_GPIOK_AMSEL, - VAL_GPIOK_PCTL}, - {VAL_GPIOL_DATA, VAL_GPIOL_DIR, VAL_GPIOL_AFSEL, VAL_GPIOL_DR2R, - VAL_GPIOL_DR4R, VAL_GPIOL_DR8R, VAL_GPIOL_ODR, VAL_GPIOL_PUR, - VAL_GPIOL_PDR, VAL_GPIOL_SLR, VAL_GPIOL_DEN, VAL_GPIOL_AMSEL, - VAL_GPIOL_PCTL}, - {VAL_GPIOM_DATA, VAL_GPIOM_DIR, VAL_GPIOM_AFSEL, VAL_GPIOM_DR2R, - VAL_GPIOM_DR4R, VAL_GPIOM_DR8R, VAL_GPIOM_ODR, VAL_GPIOM_PUR, - VAL_GPIOM_PDR, VAL_GPIOM_SLR, VAL_GPIOM_DEN, VAL_GPIOM_AMSEL, - VAL_GPIOM_PCTL}, - {VAL_GPION_DATA, VAL_GPION_DIR, VAL_GPION_AFSEL, VAL_GPION_DR2R, - VAL_GPION_DR4R, VAL_GPION_DR8R, VAL_GPION_ODR, VAL_GPION_PUR, - VAL_GPION_PDR, VAL_GPION_SLR, VAL_GPION_DEN, VAL_GPION_AMSEL, - VAL_GPION_PCTL}, - {VAL_GPIOP_DATA, VAL_GPIOP_DIR, VAL_GPIOP_AFSEL, VAL_GPIOP_DR2R, - VAL_GPIOP_DR4R, VAL_GPIOP_DR8R, VAL_GPIOP_ODR, VAL_GPIOP_PUR, - VAL_GPIOP_PDR, VAL_GPIOP_SLR, VAL_GPIOP_DEN, VAL_GPIOP_AMSEL, - VAL_GPIOP_PCTL}, - {VAL_GPIOQ_DATA, VAL_GPIOQ_DIR, VAL_GPIOQ_AFSEL, VAL_GPIOQ_DR2R, - VAL_GPIOQ_DR4R, VAL_GPIOQ_DR8R, VAL_GPIOQ_ODR, VAL_GPIOQ_PUR, - VAL_GPIOQ_PDR, VAL_GPIOQ_SLR, VAL_GPIOQ_DEN, VAL_GPIOQ_AMSEL, - VAL_GPIOQ_PCTL} -}; -#endif - -/** - * @brief Early initialization code. - * @details This initialization is performed just after reset before BSS and - * DATA segments initialization. - */ -void __early_init(void) { - tiva_clock_init(); -} - -/** - * @brief Late initialization code. - * @note This initialization is performed after BSS and DATA segments - * initialization and before invoking the main() function. - */ -void boardInit(void) { -} diff --git a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h b/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h deleted file mode 100644 index 08bb36f..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h +++ /dev/null @@ -1,429 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Setup for Texas Instruments TM4C1294 Launchpad Board. - */ - -/* - * Board identifier. - */ -#define BOARD_TI_TM4C1294_LAUNCHPAD -#define BOARD_NAME "Texas Instruments TM4C1294 Launchpad" - -/* - * Ethernet PHY type. - */ -#define BOARD_PHY_ADDR 0 /* 0 is internal PHY */ -#define BOARD_PHY_ID 0x2000A221 /* internal PHY ID */ -/* uncomment when using RMII */ -//#define BOARD_PHY_RMII - -/* - * MCU type - */ -//#define TM4C1290NCPDT -//#define TM4C1290NCZAD -//#define TM4C1292NCPDT -//#define TM4C1292NCZAD -//#define TM4C1294KCPDT -#define TM4C1294NCPDT -//#define TM4C1294NCZAD -//#define TM4C1297NCZAD -//#define TM4C1299KCZAD -//#define TM4C1299NCZAD -//#define TM4C129CNCPDT -//#define TM4C129CNCZAD -//#define TM4C129DNCPDT -//#define TM4C129DNCZAD -//#define TM4C129EKCPDT -//#define TM4C129ENCPDT -//#define TM4C129ENCZAD -//#define TM4C129LNCZAD -//#define TM4C129XKCZAD -//#define TM4C129XNCZAD - -/* - * Board oscillators-related settings. - */ -#define TIVA_XTAL_VALUE 25000000 - -/* - * IO pins assignments. - */ -#define GPIOA_UART0_RX 0 -#define GPIOA_UART0_TX 1 -#define GPIOA_PIN2 2 -#define GPIOA_PIN3 3 -#define GPIOA_PIN4 4 -#define GPIOA_PIN5 5 -#define GPIOA_PIN6 6 -#define GPIOA_PIN7 7 - -#define GPIOB_PIN0 0 -#define GPIOB_PIN1 1 -#define GPIOB_PIN2 2 -#define GPIOB_PIN3 3 -#define GPIOB_PIN4 4 -#define GPIOB_PIN5 5 -#define GPIOB_PIN6 6 -#define GPIOB_PIN7 7 - -#define GPIOC_TCK_SWCLK 0 -#define GPIOC_TMS_SWDIO 1 -#define GPIOC_TDI 2 -#define GPIOC_TDO_SWO 3 -#define GPIOC_PIN4 4 -#define GPIOC_PIN5 5 -#define GPIOC_PIN6 6 -#define GPIOC_PIN7 7 - -#define GPIOD_PIN0 0 -#define GPIOD_PIN1 1 -#define GPIOD_PIN2 2 -#define GPIOD_PIN3 3 -#define GPIOD_PIN4 4 -#define GPIOD_PIN5 5 -#define GPIOD_PIN6 6 -#define GPIOD_PIN7 7 - -#define GPIOE_PIN0 0 -#define GPIOE_PIN1 1 -#define GPIOE_PIN2 2 -#define GPIOE_PIN3 3 -#define GPIOE_PIN4 4 -#define GPIOE_PIN5 5 -#define GPIOE_PIN6 6 -#define GPIOE_PIN7 7 - -#define GPIOF_LED0 0 -#define GPIOF_PIN1 1 -#define GPIOF_PIN2 2 -#define GPIOF_PIN3 3 -#define GPIOF_LED1 4 -#define GPIOF_PIN5 5 -#define GPIOF_PIN6 6 -#define GPIOF_PIN7 7 - -#define GPIOG_PIN0 0 -#define GPIOG_PIN1 1 -#define GPIOG_PIN2 2 -#define GPIOG_PIN3 3 -#define GPIOG_PIN4 4 -#define GPIOG_PIN5 5 -#define GPIOG_PIN6 6 -#define GPIOG_PIN7 7 - -#define GPIOH_PIN0 0 -#define GPIOH_PIN1 1 -#define GPIOH_PIN2 2 -#define GPIOH_PIN3 3 -#define GPIOH_PIN4 4 -#define GPIOH_PIN5 5 -#define GPIOH_PIN6 6 -#define GPIOH_PIN7 7 - -#define GPIOJ_SW1 0 -#define GPIOJ_PIN1 1 -#define GPIOJ_PIN2 2 -#define GPIOJ_PIN3 3 -#define GPIOJ_PIN4 4 -#define GPIOJ_PIN5 5 -#define GPIOJ_PIN6 6 -#define GPIOJ_PIN7 7 - -#define GPIOK_PIN0 0 -#define GPIOK_PIN1 1 -#define GPIOK_PIN2 2 -#define GPIOK_PIN3 3 -#define GPIOK_PIN4 4 -#define GPIOK_PIN5 5 -#define GPIOK_PIN6 6 -#define GPIOK_PIN7 7 - -#define GPIOL_PIN0 0 -#define GPIOL_PIN1 1 -#define GPIOL_PIN2 2 -#define GPIOL_PIN3 3 -#define GPIOL_PIN4 4 -#define GPIOL_PIN5 5 -#define GPIOL_PIN6 6 -#define GPIOL_PIN7 7 - -#define GPIOM_PIN0 0 -#define GPIOM_PIN1 1 -#define GPIOM_PIN2 2 -#define GPIOM_PIN3 3 -#define GPIOM_PIN4 4 -#define GPIOM_PIN5 5 -#define GPIOM_PIN6 6 -#define GPIOM_PIN7 7 - -#define GPION_LED2 0 -#define GPION_LED3 1 -#define GPION_PIN2 2 -#define GPION_PIN3 3 -#define GPION_PIN4 4 -#define GPION_PIN5 5 -#define GPION_PIN6 6 -#define GPION_PIN7 7 - -#define GPIOP_PIN0 0 -#define GPIOP_PIN1 1 -#define GPIOP_PIN2 2 -#define GPIOP_PIN3 3 -#define GPIOP_PIN4 4 -#define GPIOP_PIN5 5 -#define GPIOP_PIN6 6 -#define GPIOP_PIN7 7 - -#define GPIOQ_PIN0 0 -#define GPIOQ_PIN1 1 -#define GPIOQ_PIN2 2 -#define GPIOQ_PIN3 3 -#define GPIOQ_PIN4 4 -#define GPIOQ_PIN5 5 -#define GPIOQ_PIN6 6 -#define GPIOQ_PIN7 7 - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - */ -#define VAL_GPIOA_DATA 0b00000000 -#define VAL_GPIOA_DIR 0b00000000 -#define VAL_GPIOA_AFSEL 0b00000000 -#define VAL_GPIOA_DR2R 0b11111111 -#define VAL_GPIOA_DR4R 0b00000000 -#define VAL_GPIOA_DR8R 0b00000000 -#define VAL_GPIOA_ODR 0b00000000 -#define VAL_GPIOA_PUR 0b00000000 -#define VAL_GPIOA_PDR 0b00000000 -#define VAL_GPIOA_SLR 0b00000000 -#define VAL_GPIOA_DEN 0b11111111 -#define VAL_GPIOA_AMSEL 0b0000 -#define VAL_GPIOA_PCTL 0x00000000 - -#define VAL_GPIOB_DATA 0b00000000 -#define VAL_GPIOB_DIR 0b00000000 -#define VAL_GPIOB_AFSEL 0b00000000 -#define VAL_GPIOB_DR2R 0b11111111 -#define VAL_GPIOB_DR4R 0b00000000 -#define VAL_GPIOB_DR8R 0b00000000 -#define VAL_GPIOB_ODR 0b00000000 -#define VAL_GPIOB_PUR 0b00000000 -#define VAL_GPIOB_PDR 0b00000000 -#define VAL_GPIOB_SLR 0b00000000 -#define VAL_GPIOB_DEN 0b11111111 -#define VAL_GPIOB_AMSEL 0b0000 -#define VAL_GPIOB_PCTL 0x00000000 - -#define VAL_GPIOC_DATA 0b00000000 -#define VAL_GPIOC_DIR 0b00001000 -#define VAL_GPIOC_AFSEL 0b00001111 -#define VAL_GPIOC_DR2R 0b11111111 -#define VAL_GPIOC_DR4R 0b00000000 -#define VAL_GPIOC_DR8R 0b00000000 -#define VAL_GPIOC_ODR 0b00000000 -#define VAL_GPIOC_PUR 0b00001111 -#define VAL_GPIOC_PDR 0b00000000 -#define VAL_GPIOC_SLR 0b00000000 -#define VAL_GPIOC_DEN 0b11111111 -#define VAL_GPIOC_AMSEL 0b0000 -#define VAL_GPIOC_PCTL 0x00001111 - -#define VAL_GPIOD_DATA 0b00000000 -#define VAL_GPIOD_DIR 0b00000000 -#define VAL_GPIOD_AFSEL 0b00000000 -#define VAL_GPIOD_DR2R 0b11111111 -#define VAL_GPIOD_DR4R 0b00000000 -#define VAL_GPIOD_DR8R 0b00000000 -#define VAL_GPIOD_ODR 0b00000000 -#define VAL_GPIOD_PUR 0b00000000 -#define VAL_GPIOD_PDR 0b00000000 -#define VAL_GPIOD_SLR 0b00000000 -#define VAL_GPIOD_DEN 0b11111111 -#define VAL_GPIOD_AMSEL 0b0000 -#define VAL_GPIOD_PCTL 0x00000000 - -#define VAL_GPIOE_DATA 0b00000000 -#define VAL_GPIOE_DIR 0b00000000 -#define VAL_GPIOE_AFSEL 0b00000000 -#define VAL_GPIOE_DR2R 0b11111111 -#define VAL_GPIOE_DR4R 0b00000000 -#define VAL_GPIOE_DR8R 0b00000000 -#define VAL_GPIOE_ODR 0b00000000 -#define VAL_GPIOE_PUR 0b00000000 -#define VAL_GPIOE_PDR 0b00000000 -#define VAL_GPIOE_SLR 0b00000000 -#define VAL_GPIOE_DEN 0b11111111 -#define VAL_GPIOE_AMSEL 0b0000 -#define VAL_GPIOE_PCTL 0x00000000 - -#define VAL_GPIOF_DATA 0b00000000 -#define VAL_GPIOF_DIR 0b00000000 -#define VAL_GPIOF_AFSEL 0b00000000 -#define VAL_GPIOF_DR2R 0b11111111 -#define VAL_GPIOF_DR4R 0b00000000 -#define VAL_GPIOF_DR8R 0b00000000 -#define VAL_GPIOF_ODR 0b00000000 -#define VAL_GPIOF_PUR 0b00000000 -#define VAL_GPIOF_PDR 0b00000000 -#define VAL_GPIOF_SLR 0b00000000 -#define VAL_GPIOF_DEN 0b11111111 -#define VAL_GPIOF_AMSEL 0b0000 -#define VAL_GPIOF_PCTL 0x00000000 - -#define VAL_GPIOG_DATA 0b00000000 -#define VAL_GPIOG_DIR 0b00000000 -#define VAL_GPIOG_AFSEL 0b00000000 -#define VAL_GPIOG_DR2R 0b11111111 -#define VAL_GPIOG_DR4R 0b00000000 -#define VAL_GPIOG_DR8R 0b00000000 -#define VAL_GPIOG_ODR 0b00000000 -#define VAL_GPIOG_PUR 0b00000000 -#define VAL_GPIOG_PDR 0b00000000 -#define VAL_GPIOG_SLR 0b00000000 -#define VAL_GPIOG_DEN 0b11111111 -#define VAL_GPIOG_AMSEL 0b0000 -#define VAL_GPIOG_PCTL 0x00000000 - -#define VAL_GPIOH_DATA 0b00000000 -#define VAL_GPIOH_DIR 0b00000000 -#define VAL_GPIOH_AFSEL 0b00000000 -#define VAL_GPIOH_DR2R 0b11111111 -#define VAL_GPIOH_DR4R 0b00000000 -#define VAL_GPIOH_DR8R 0b00000000 -#define VAL_GPIOH_ODR 0b00000000 -#define VAL_GPIOH_PUR 0b00000000 -#define VAL_GPIOH_PDR 0b00000000 -#define VAL_GPIOH_SLR 0b00000000 -#define VAL_GPIOH_DEN 0b11111111 -#define VAL_GPIOH_AMSEL 0b0000 -#define VAL_GPIOH_PCTL 0x00000000 - -#define VAL_GPIOJ_DATA 0b00000000 -#define VAL_GPIOJ_DIR 0b00000000 -#define VAL_GPIOJ_AFSEL 0b00000000 -#define VAL_GPIOJ_DR2R 0b11111111 -#define VAL_GPIOJ_DR4R 0b00000000 -#define VAL_GPIOJ_DR8R 0b00000000 -#define VAL_GPIOJ_ODR 0b00000000 -#define VAL_GPIOJ_PUR 0b00000001 -#define VAL_GPIOJ_PDR 0b00000000 -#define VAL_GPIOJ_SLR 0b00000000 -#define VAL_GPIOJ_DEN 0b11111111 -#define VAL_GPIOJ_AMSEL 0b0000 -#define VAL_GPIOJ_PCTL 0x00000000 - -#define VAL_GPIOK_DATA 0b00000000 -#define VAL_GPIOK_DIR 0b00000000 -#define VAL_GPIOK_AFSEL 0b00000000 -#define VAL_GPIOK_DR2R 0b11111111 -#define VAL_GPIOK_DR4R 0b00000000 -#define VAL_GPIOK_DR8R 0b00000000 -#define VAL_GPIOK_ODR 0b00000000 -#define VAL_GPIOK_PUR 0b00000000 -#define VAL_GPIOK_PDR 0b00000000 -#define VAL_GPIOK_SLR 0b00000000 -#define VAL_GPIOK_DEN 0b11111111 -#define VAL_GPIOK_AMSEL 0b0000 -#define VAL_GPIOK_PCTL 0x00000000 - -#define VAL_GPIOL_DATA 0b00000000 -#define VAL_GPIOL_DIR 0b00000000 -#define VAL_GPIOL_AFSEL 0b00000000 -#define VAL_GPIOL_DR2R 0b11111111 -#define VAL_GPIOL_DR4R 0b00000000 -#define VAL_GPIOL_DR8R 0b00000000 -#define VAL_GPIOL_ODR 0b00000000 -#define VAL_GPIOL_PUR 0b00000000 -#define VAL_GPIOL_PDR 0b00000000 -#define VAL_GPIOL_SLR 0b00000000 -#define VAL_GPIOL_DEN 0b11111111 -#define VAL_GPIOL_AMSEL 0b0000 -#define VAL_GPIOL_PCTL 0x00000000 - -#define VAL_GPIOM_DATA 0b00000000 -#define VAL_GPIOM_DIR 0b00000000 -#define VAL_GPIOM_AFSEL 0b00000000 -#define VAL_GPIOM_DR2R 0b11111111 -#define VAL_GPIOM_DR4R 0b00000000 -#define VAL_GPIOM_DR8R 0b00000000 -#define VAL_GPIOM_ODR 0b00000000 -#define VAL_GPIOM_PUR 0b00000000 -#define VAL_GPIOM_PDR 0b00000000 -#define VAL_GPIOM_SLR 0b00000000 -#define VAL_GPIOM_DEN 0b11111111 -#define VAL_GPIOM_AMSEL 0b0000 -#define VAL_GPIOM_PCTL 0x00000000 - -#define VAL_GPION_DATA 0b00000000 -#define VAL_GPION_DIR 0b00000000 -#define VAL_GPION_AFSEL 0b00000000 -#define VAL_GPION_DR2R 0b11111111 -#define VAL_GPION_DR4R 0b00000000 -#define VAL_GPION_DR8R 0b00000000 -#define VAL_GPION_ODR 0b00000000 -#define VAL_GPION_PUR 0b00000000 -#define VAL_GPION_PDR 0b00000000 -#define VAL_GPION_SLR 0b00000000 -#define VAL_GPION_DEN 0b11111111 -#define VAL_GPION_AMSEL 0b0000 -#define VAL_GPION_PCTL 0x00000000 - -#define VAL_GPIOP_DATA 0b00000000 -#define VAL_GPIOP_DIR 0b00000000 -#define VAL_GPIOP_AFSEL 0b00000000 -#define VAL_GPIOP_DR2R 0b11111111 -#define VAL_GPIOP_DR4R 0b00000000 -#define VAL_GPIOP_DR8R 0b00000000 -#define VAL_GPIOP_ODR 0b00000000 -#define VAL_GPIOP_PUR 0b00000000 -#define VAL_GPIOP_PDR 0b00000000 -#define VAL_GPIOP_SLR 0b00000000 -#define VAL_GPIOP_DEN 0b11111111 -#define VAL_GPIOP_AMSEL 0b0000 -#define VAL_GPIOP_PCTL 0x00000000 - -#define VAL_GPIOQ_DATA 0b00000000 -#define VAL_GPIOQ_DIR 0b00000000 -#define VAL_GPIOQ_AFSEL 0b00000000 -#define VAL_GPIOQ_DR2R 0b11111111 -#define VAL_GPIOQ_DR4R 0b00000000 -#define VAL_GPIOQ_DR8R 0b00000000 -#define VAL_GPIOQ_ODR 0b00000000 -#define VAL_GPIOQ_PUR 0b00000000 -#define VAL_GPIOQ_PDR 0b00000000 -#define VAL_GPIOQ_SLR 0b00000000 -#define VAL_GPIOQ_DEN 0b11111111 -#define VAL_GPIOQ_AMSEL 0b0000 -#define VAL_GPIOQ_PCTL 0x00000000 - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk deleted file mode 100644 index 56298eb..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c - -# Required include directories -BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD diff --git a/ChibiOS_16.1.5/community/os/hal/boards/WVSHARE_BLE400/board.c b/ChibiOS_16.1.5/community/os/hal/boards/WVSHARE_BLE400/board.c deleted file mode 100644 index 9bae7ab..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/WVSHARE_BLE400/board.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - Copyright (C) 2015 Fabio Utzig - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. - */ -const PALConfig pal_default_config = -{ - .pads = { - PAL_MODE_OUTPUT_OPENDRAIN, /* P0.0: SDA */ - PAL_MODE_OUTPUT_OPENDRAIN, /* P0.1: SCL */ - PAL_MODE_UNCONNECTED, /* P0.2 */ - PAL_MODE_UNCONNECTED, /* P0.3 */ - PAL_MODE_UNCONNECTED, /* P0.4 */ - PAL_MODE_UNCONNECTED, /* P0.5 */ - PAL_MODE_UNCONNECTED, /* P0.6 */ - PAL_MODE_UNCONNECTED, /* P0.7 */ - PAL_MODE_UNCONNECTED, /* P0.8 UART_RTS */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.9: UART_TX */ - PAL_MODE_UNCONNECTED, /* P0.10 UART_CTS */ - PAL_MODE_INPUT_PULLUP, /* P0.11: UART_RX */ - PAL_MODE_UNCONNECTED, /* P0.12 */ - PAL_MODE_UNCONNECTED, /* P0.13 */ - PAL_MODE_UNCONNECTED, /* P0.14 */ - PAL_MODE_UNCONNECTED, /* P0.15 */ - PAL_MODE_INPUT_PULLUP, /* P0.16: KEY1 */ - PAL_MODE_INPUT_PULLUP, /* P0.17: KEY2 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.18: LED0 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.19: LED1 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.20: LED2 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.21: LED3 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.22: LED4 */ - PAL_MODE_INPUT, /* P0.23: SPI_MISO */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.24: SPI_MOSI */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.25: SPI_SCK */ - PAL_MODE_UNCONNECTED, /* P0.26 */ - PAL_MODE_UNCONNECTED, /* P0.27 */ - PAL_MODE_UNCONNECTED, /* P0.28 */ - PAL_MODE_UNCONNECTED, /* P0.29 */ - PAL_MODE_OUTPUT_PUSHPULL, /* P0.30: SPI_NSS */ - PAL_MODE_UNCONNECTED, /* P0.31 */ - }, -}; -#endif - -/** - * @brief Early initialization code. - * @details This initialization is performed just after reset before BSS and - * DATA segments initialization. - */ -void __early_init(void) -{ -} - -/** - * @brief Late initialization code. - * @note This initialization is performed after BSS and DATA segments - * initialization and before invoking the main() function. - */ -void boardInit(void) -{ - //FIXME: not really needed yet - //NRF_CLOCK->XTALFREQ = 0xff; - //NRF_CLOCK->EVENTS_HFCLKSTARTED = 0; - //NRF_CLOCK->TASKS_HFCLKSTART = 1; - //while (!NRF_CLOCK->EVENTS_HFCLKSTARTED) {} -} diff --git a/ChibiOS_16.1.5/community/os/hal/boards/WVSHARE_BLE400/board.h b/ChibiOS_16.1.5/community/os/hal/boards/WVSHARE_BLE400/board.h deleted file mode 100644 index 5a4e8f0..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/WVSHARE_BLE400/board.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - Copyright (C) 2015 Fabio Utzig - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* Board identifier. */ -#define BOARD_WVSHARE_BLE400 -#define BOARD_NAME "WvShare BLE400" - -/* Board oscillators-related settings. */ -#define NRF51_XTAL_VALUE 16000000 - -/* GPIO pins. */ -#define KEY1 16 -#define KEY2 17 -#define LED0 18 -#define LED1 19 -#define LED2 20 -#define LED3 21 -#define LED4 22 -#define UART_TX 9 -#define UART_RX 11 -#define UART_RTS 8 -#define UART_CTS 10 -#define SPI_SCK 25 -#define SPI_MOSI 24 -#define SPI_MISO 23 -#define SPI_SS 30 -#define I2C_SCL 1 -#define I2C_SDA 0 -#define AIN0 26 -#define AIN1 27 -#define AIN2 1 -#define AIN3 2 -#define AIN4 3 -#define AIN5 4 -#define AIN6 5 -#define AIN7 6 -#define AREF0 0 -#define AREF1 6 - -/* - * IO pins assignments. - */ -#define IOPORT1_KEY1 16U -#define IOPORT1_KEY2 17U -#define IOPORT1_LED0 18U -#define IOPORT1_LED1 19U -#define IOPORT1_LED2 20U -#define IOPORT1_LED3 21U -#define IOPORT1_LED4 22U -#define IOPORT1_UART_TX 9U -#define IOPORT1_UART_RX 11U -#define IOPORT1_UART_RTS 8U -#define IOPORT1_UART_CTS 10U -#define IOPORT1_SPI_SCK 25U -#define IOPORT1_SPI_MOSI 24U -#define IOPORT1_SPI_MISO 23U -#define IOPORT1_SPI_SS 30U -#define IOPORT1_I2C_SCL 1U -#define IOPORT1_I2C_SDA 0U -#define IOPORT1_AIN0 26U -#define IOPORT1_AIN1 27U -#define IOPORT1_AIN2 1U -#define IOPORT1_AIN3 2U -#define IOPORT1_AIN4 3U -#define IOPORT1_AIN5 4U -#define IOPORT1_AIN6 5U -#define IOPORT1_AIN7 6U -#define IOPORT1_AREF0 0U -#define IOPORT1_AREF1 6U - -/* - * IO lines assignments. - */ -#define LINE_KEY1 PAL_LINE(IOPORT1, IOPORT1_KEY1) -#define LINE_KEY2 PAL_LINE(IOPORT1, IOPORT1_KEY2) -#define LINE_LED0 PAL_LINE(IOPORT1, IOPORT1_LED0) -#define LINE_LED1 PAL_LINE(IOPORT1, IOPORT1_LED1) -#define LINE_LED2 PAL_LINE(IOPORT1, IOPORT1_LED2) -#define LINE_LED3 PAL_LINE(IOPORT1, IOPORT1_LED3) -#define LINE_LED4 PAL_LINE(IOPORT1, IOPORT1_LED4) -#define LINE_UART_TX PAL_LINE(IOPORT1, IOPORT1_UART_TX) -#define LINE_UART_RX PAL_LINE(IOPORT1, IOPORT1_UART_RX) -#define LINE_UART_RTS PAL_LINE(IOPORT1, IOPORT1_UART_RTS) -#define LINE_UART_CTS PAL_LINE(IOPORT1, IOPORT1_UART_CTS) -#define LINE_SPI_SCK PAL_LINE(IOPORT1, IOPORT1_SPI_SCK) -#define LINE_SPI_MOSI PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI) -#define LINE_SPI_MISO PAL_LINE(IOPORT1, IOPORT1_SPI_MISO) -#define LINE_SPI_SS PAL_LINE(IOPORT1, IOPORT1_SPI_SS) -#define LINE_I2C_SCL PAL_LINE(IOPORT1, IOPORT1_I2C_SCL) -#define LINE_I2C_SDA PAL_LINE(IOPORT1, IOPORT1_I2C_SDA) -#define LINE_AIN0 PAL_LINE(IOPORT1, IOPORT1_AIN0) -#define LINE_AIN1 PAL_LINE(IOPORT1, IOPORT1_AIN1) -#define LINE_AIN2 PAL_LINE(IOPORT1, IOPORT1_AIN2) -#define LINE_AIN3 PAL_LINE(IOPORT1, IOPORT1_AIN3) -#define LINE_AIN4 PAL_LINE(IOPORT1, IOPORT1_AIN4) -#define LINE_AIN5 PAL_LINE(IOPORT1, IOPORT1_AIN5) -#define LINE_AIN6 PAL_LINE(IOPORT1, IOPORT1_AIN6) -#define LINE_AIN7 PAL_LINE(IOPORT1, IOPORT1_AIN7) -#define LINE_AREF0 PAL_LINE(IOPORT1, IOPORT1_AREF0) -#define LINE_AREF1 PAL_LINE(IOPORT1, IOPORT1_AREF1) - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* _BOARD_H_ */ diff --git a/ChibiOS_16.1.5/community/os/hal/boards/WVSHARE_BLE400/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/WVSHARE_BLE400/board.mk deleted file mode 100644 index ade4201..0000000 --- a/ChibiOS_16.1.5/community/os/hal/boards/WVSHARE_BLE400/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# List of all the board related files. -BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/WVSHARE_BLE400/board.c - -# Required include directories -BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/WVSHARE_BLE400 diff --git a/ChibiOS_16.1.5/community/os/hal/hal.mk b/ChibiOS_16.1.5/community/os/hal/hal.mk deleted file mode 100644 index ce74620..0000000 --- a/ChibiOS_16.1.5/community/os/hal/hal.mk +++ /dev/null @@ -1,23 +0,0 @@ -include ${CHIBIOS}/os/hal/hal.mk
-
-HALSRC += ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_rng.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_usbh.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_debug.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_desciter.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_hub.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_msd.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_ftdi.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/usbh/hal_usbh_uvc.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee24xx.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_ee25xx.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_eeprom.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_timcap.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_qei.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c
-
-HALINC += ${CHIBIOS_CONTRIB}/os/hal/include
diff --git a/ChibiOS_16.1.5/community/os/hal/include/hal_community.h b/ChibiOS_16.1.5/community/os/hal/include/hal_community.h deleted file mode 100644 index 1518c7e..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/hal_community.h +++ /dev/null @@ -1,122 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file hal_community.h
- * @brief HAL subsystem header (community part).
- *
- * @addtogroup HAL_COMMUNITY
- * @{
- */
-
-#ifndef HAL_COMMUNITY_H
-#define HAL_COMMUNITY_H
-
-
-/* Error checks on the configuration header file.*/
-#if !defined(HAL_USE_CRC)
-#define HAL_USE_CRC FALSE
-#endif
-
-#if !defined(HAL_USE_EEPROM)
-#define HAL_USE_EEPROM FALSE
-#endif
-
-#if !defined(HAL_USE_EICU)
-#define HAL_USE_EICU FALSE
-#endif
-
-#if !defined(HAL_USE_NAND)
-#define HAL_USE_NAND FALSE
-#endif
-
-#if !defined(HAL_USE_ONEWIRE)
-#define HAL_USE_ONEWIRE FALSE
-#endif
-
-#if !defined(HAL_USE_QEI)
-#define HAL_USE_QEI FALSE
-#endif
-
-#if !defined(HAL_USE_RNG)
-#define HAL_USE_RNG FALSE
-#endif
-
-#if !defined(HAL_USE_TIMCAP)
-#define HAL_USE_TIMCAP FALSE
-#endif
-
-#if !defined(HAL_USE_USBH)
-#define HAL_USE_USBH FALSE
-#endif
-
-#if !defined(HAL_USE_USB_HID)
-#define HAL_USE_USB_HID FALSE
-#endif
-
-/* Abstract interfaces.*/
-
-/* Shared headers.*/
-
-/* Normal drivers.*/
-#include "hal_nand.h"
-#include "hal_eicu.h"
-#include "hal_rng.h"
-#include "hal_usbh.h"
-#include "hal_timcap.h"
-#include "hal_qei.h"
-
-/* Complex drivers.*/
-#include "hal_onewire.h"
-#include "hal_crc.h"
-#include "hal_eeprom.h"
-#include "hal_usb_hid.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void halCommunityInit(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_COMMUNITY_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/include/hal_crc.h b/ChibiOS_16.1.5/community/os/hal/include/hal_crc.h deleted file mode 100644 index 8c4c895..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/hal_crc.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - ChibiOS - Copyright (C) 2015 Michael D. Spradling - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _CRC_H_ -#define _CRC_H_ - -#if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief Enable DMA CRC - * @note Enables DMA when doing CRC calculations. This may be less - * efficient with smaller CRC calculations. - */ -#if !defined(CRC_USE_DMA) || defined(__DOXYGEN__) -#define CRC_USE_DMA FALSE -#endif - -/** - * @brief Enables the @p crcAcquireBus() and @p crcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(CRC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define CRC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_CRC_USE_CRC1 != TRUE && CRCSW_USE_CRC1 != TRUE -#error "CRC requires at least one LLD driver." -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - CRC_UNINIT, /* Not initialized. */ - CRC_STOP, /* Stopped. */ - CRC_READY, /* Ready. */ - CRC_ACTIVE, /* Calculating CRC. */ - CRC_COMPLETE /* Asynchronous operation complete. */ -} crcstate_t; - -#include "hal_crc_lld.h" -#include "crcsw.h" /* Include software LL driver */ - - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Low level driver helper macros - * @{ - */ - -/** - * @brief Wakes up the waiting thread. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @notapi - */ -#define _crc_wakeup_isr(crcp) { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(crcp)->thread, MSG_OK); \ - osalSysUnlockFromISR(); \ -} - -/** - * @brief Common ISR code. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @notapi - */ -#define _crc_isr_code(crcp, crc) { \ - if ((crcp)->config->end_cb) { \ - (crcp)->state = CRC_COMPLETE; \ - (crcp)->config->end_cb(crcp, crc); \ - if ((crcp)->state == CRC_COMPLETE) \ - (crcp)->state = CRC_READY; \ - } \ - else \ - (crcp)->state = CRC_READY; \ - _crc_wakeup_isr(crcp); \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void crcInit(void); - void crcObjectInit(CRCDriver *crcp); - void crcStart(CRCDriver *crcp, const CRCConfig *config); - void crcStop(CRCDriver *crcp); - void crcReset(CRCDriver *crcp); - void crcResetI(CRCDriver *crcp); - uint32_t crcCalc(CRCDriver *crcp, size_t n, const void *buf); - uint32_t crcCalcI(CRCDriver *crcp, size_t n, const void *buf); -#if CRC_USE_DMA == TRUE - void crcStartCalc(CRCDriver *crcp, size_t n, const void *buf); - void crcStartCalcI(CRCDriver *crcp, size_t n, const void *buf); -#endif -#if CRC_USE_MUTUAL_EXCLUSION == TRUE - void crcAcquireUnit(CRCDriver *crcp); - void crcReleaseUnit(CRCDriver *crcp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_CRC */ - -#endif /* _CRC_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/include/hal_ee24xx.h b/ChibiOS_16.1.5/community/os/hal/include/hal_ee24xx.h deleted file mode 100644 index ab12fd1..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/hal_ee24xx.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - Copyright 2012 Uladzimir Pylinski aka barthess. - You may use this work without restrictions, as long as this notice is included. - The work is provided "as is" without warranty of any kind, neither express nor implied. -*/ - -#ifndef EE24XX_H -#define EE24XX_H - -#include "hal.h" - -#if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM && EEPROM_USE_EE24XX - -#define EEPROM_DEV_24XX 24 - -/** - * @extends EepromFileConfig - */ -typedef struct { - _eeprom_file_config_data - /** - * Driver connected to IC. - */ - I2CDriver *i2cp; - /** - * Address of IC on I2C bus. - */ - i2caddr_t addr; - /** - * Pointer to write buffer. The safest size is (pagesize + 2) - */ - uint8_t *write_buf; -} I2CEepromFileConfig; - -/** - * @brief @p I2CEepromFileStream specific data. - */ -#define _eeprom_file_stream_data_i2c \ - _eeprom_file_stream_data - -/** - * @extends EepromFileStream - * - * @brief EEPROM file stream driver class for I2C device. - */ -typedef struct { - const struct EepromFileStreamVMT *vmt; - _eeprom_file_stream_data_i2c - /* Overwritten parent data member. */ - const I2CEepromFileConfig *cfg; -} I2CEepromFileStream; - - -/** - * Open I2C EEPROM IC as file and return pointer to the file stream object - * @note Fucntion allways successfully open file. All checking makes - * in read/write functions. - */ -#define I2CEepromFileOpen(efs, eepcfg, eepdev) \ - EepromFileOpen((EepromFileStream *)efs, (EepromFileConfig *)eepcfg, eepdev); - -#endif /* #if defined(EEPROM_USE_EE24XX) && EEPROM_USE_EE24XX */ - -#endif // EE24XX_H diff --git a/ChibiOS_16.1.5/community/os/hal/include/hal_ee25xx.h b/ChibiOS_16.1.5/community/os/hal/include/hal_ee25xx.h deleted file mode 100644 index fc2ad6f..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/hal_ee25xx.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - Copyright 2012 Uladzimir Pylinski aka barthess. - You may use this work without restrictions, as long as this notice is included. - The work is provided "as is" without warranty of any kind, neither express nor implied. -*/ - -#ifndef EE25XX_H -#define EE25XX_H - -#include "hal.h" - -#if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM && EEPROM_USE_EE25XX - -#define EEPROM_DEV_25XX 25 - -/** - * @extends EepromFileConfig - */ -typedef struct { - _eeprom_file_config_data - /** - * Driver connected to IC. - */ - SPIDriver *spip; - /** - * Config associated with SPI driver. - */ - const SPIConfig *spicfg; -} SPIEepromFileConfig; - -/** - * @brief @p SPIEepromFileStream specific data. - */ -#define _eeprom_file_stream_data_spi \ - _eeprom_file_stream_data - -/** - * @extends EepromFileStream - * - * @brief EEPROM file stream driver class for SPI device. - */ -typedef struct { - const struct EepromFileStreamVMT *vmt; - _eeprom_file_stream_data_spi - /* Overwritten parent data member. */ - const SPIEepromFileConfig *cfg; -} SPIEepromFileStream; - -/** - * Open SPI EEPROM IC as file and return pointer to the file stream object - * @note Fucntion allways successfully open file. All checking makes - * in read/write functions. - */ -EepromFileStream *SPIEepromFileOpen(SPIEepromFileStream *efs, - const SPIEepromFileConfig *eepcfg, - const EepromDevice *eepdev); - -#define SPIEepromFileOpen(efs, eepcfg, eepdev) \ - EepromFileOpen((EepromFileStream *)efs, (EepromFileConfig *)eepcfg, eepdev); - -#endif /* #if defined(EEPROM_USE_EE25XX) && EEPROM_USE_EE25XX */ - -#endif // EE25XX_H diff --git a/ChibiOS_16.1.5/community/os/hal/include/hal_eeprom.h b/ChibiOS_16.1.5/community/os/hal/include/hal_eeprom.h deleted file mode 100644 index cd05e14..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/hal_eeprom.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - Copyright (c) 2013 Timon Wong - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in all - copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - THE SOFTWARE. -*/ - -/* - Copyright 2012 Uladzimir Pylinski aka barthess. - You may use this work without restrictions, as long as this notice is included. - The work is provided "as is" without warranty of any kind, neither express nor implied. -*/ - -#ifndef __EEPROM_H__ -#define __EEPROM_H__ - -#include "ch.h" -#include "hal.h" - -#ifndef EEPROM_USE_EE25XX -#define EEPROM_USE_EE25XX FALSE -#endif - -#ifndef EEPROM_USE_EE24XX -#define EEPROM_USE_EE24XX FALSE -#endif - -#if (HAL_USE_EEPROM == TRUE) || defined(__DOXYGEN__) - -#if EEPROM_USE_EE25XX && EEPROM_USE_EE24XX -#define EEPROM_TABLE_SIZE 2 -#elif EEPROM_USE_EE25XX || EEPROM_USE_EE24XX -#define EEPROM_TABLE_SIZE 1 -#else -#error "No EEPROM device selected!" -#endif - -#if EEPROM_USE_EE25XX && !HAL_USE_SPI -#error "25xx enabled but SPI driver is disabled!" -#endif - -#if EEPROM_USE_EE24XX && !HAL_USE_I2C -#error "24xx enabled but I2C driver is disabled!" -#endif - -#define _eeprom_file_config_data \ - /* Lower barrier of file in EEPROM memory array. */ \ - uint32_t barrier_low; \ - /* Higher barrier of file in EEPROM memory array. */ \ - uint32_t barrier_hi; \ - /* Size of memory array in bytes. */ \ - uint32_t size; \ - /* Size of single page in bytes. */ \ - uint16_t pagesize; \ - /* Time needed by IC for single byte/page writing. */ \ - systime_t write_time; - -typedef uint32_t fileoffset_t; - -typedef struct { - _eeprom_file_config_data -} EepromFileConfig; - -/** - * @brief @p EepromFileStream specific data. - */ -#define _eeprom_file_stream_data \ - _base_sequential_stream_data \ - uint32_t errors; \ - uint32_t position; \ - -/** - * @extends BaseFileStreamVMT - * - * @brief @p EepromFileStream virtual methods table. - */ -struct EepromFileStreamVMT { - _file_stream_methods -}; - -/** - * @extends BaseFileStream - * - * @brief EEPROM file stream driver class. - * @details This class extends @p BaseFileStream by adding some fields. - */ -typedef struct { - /** @brief Virtual Methods Table.*/ - const struct EepromFileStreamVMT *vmt; - _eeprom_file_stream_data - /** pointer to config object, must be overwritten by all derived classes.*/ - const EepromFileConfig *cfg; -} EepromFileStream; - -/** - * @brief Low level device descriptor. - */ -typedef struct { - const uint8_t id; - const struct EepromFileStreamVMT *efsvmt; -} EepromDevice; - -const EepromDevice *EepromFindDevice(uint8_t id); - -EepromFileStream *EepromFileOpen(EepromFileStream *efs, - const EepromFileConfig *eepcfg, - const EepromDevice *eepdev); - -uint8_t EepromReadByte(EepromFileStream *efs); -uint16_t EepromReadHalfword(EepromFileStream *efs); -uint32_t EepromReadWord(EepromFileStream *efs); -size_t EepromWriteByte(EepromFileStream *efs, uint8_t data); -size_t EepromWriteHalfword(EepromFileStream *efs, uint16_t data); -size_t EepromWriteWord(EepromFileStream *efs, uint32_t data); - -msg_t eepfs_getsize(void *ip); -msg_t eepfs_getposition(void *ip); -msg_t eepfs_lseek(void *ip, fileoffset_t offset); -msg_t eepfs_close(void *ip); -msg_t eepfs_geterror(void *ip); -msg_t eepfs_put(void *ip, uint8_t b); -msg_t eepfs_get(void *ip); - -#include "hal_ee24xx.h" -#include "hal_ee25xx.h" - -#endif /* #if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM */ -#endif /* __EEPROM_H__ */ diff --git a/ChibiOS_16.1.5/community/os/hal/include/hal_eicu.h b/ChibiOS_16.1.5/community/os/hal/include/hal_eicu.h deleted file mode 100644 index d4b0ed2..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/hal_eicu.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Rewritten by Emil Fresk (1/5 - 2014) for extended input capture - functionality. And fix for spurious callbacks in the interrupt handler. -*/ -/* - Improved by Uladzimir Pylinsky aka barthess (1/3 - 2015) for support of - 32-bit timers and timers with single capture/compare channels. -*/ - -#ifndef _EICU_H_ -#define _EICU_H_ - -#if (HAL_USE_EICU == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - EICU_UNINIT, /* Not initialized. */ - EICU_STOP, /* Stopped. */ - EICU_READY, /* Ready. */ - EICU_WAITING, /* Waiting for first edge. */ - EICU_ACTIVE, /* Active cycle phase. */ - EICU_IDLE /* Idle cycle phase. */ -} eicustate_t; - -/** - * @brief Channel state machine possible states. - */ -typedef enum { - EICU_CH_IDLE, /* Idle cycle phase. */ - EICU_CH_ACTIVE /* Active cycle phase. */ -} eicuchannelstate_t; - -/** - * @brief EICU channel selection definition - */ -typedef enum { - EICU_CHANNEL_1, - EICU_CHANNEL_2, - EICU_CHANNEL_3, - EICU_CHANNEL_4, - EICU_CHANNEL_ENUM_END -} eicuchannel_t; - -/** - * @brief Type of a structure representing an EICU driver. - */ -typedef struct EICUDriver EICUDriver; - -/** - * @brief EICU notification callback type. - * - * @param[in] eicup Pointer to a EICUDriver object - * @param[in] channel EICU channel that fired the interrupt - * @param[in] width Pulse width - * @param[in] period Pulse period - */ -typedef void (*eicucallback_t)(EICUDriver *eicup, eicuchannel_t channel, - uint32_t width, uint32_t period); - -#include "hal_eicu_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Enables the extended input capture. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @iclass - */ -#define eicuEnableI(eicup) eicu_lld_enable(eicup) - -/** - * @brief Disables the extended input capture. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @iclass - */ -#define eicuDisableI(eicup) eicu_lld_disable(eicup) -/** @} */ - -/** - * @name Low Level driver helper macros - * @{ - */ -/** - * @brief Common ISR code, EICU PWM width event. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * @param[in] channel The timer channel that fired the interrupt. - * - * @notapi - */ -static inline void _eicu_isr_invoke_pwm_width_cb(EICUDriver *eicup, - eicuchannel_t channel) { - if (eicup->state != EICU_WAITING) { - eicup->state = EICU_IDLE; - eicup->config->iccfgp[channel]->capture_cb(eicup, channel, 0, 0); - } -} - -/** - * @brief Common ISR code, EICU PWM period event. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * @param[in] channel The timer channel that fired the interrupt. - * - * @notapi - */ -static inline void _eicu_isr_invoke_pwm_period_cb(EICUDriver *eicup, - eicuchannel_t channel) { - eicustate_t previous_state = eicup->state; - eicup->state = EICU_ACTIVE; - if (previous_state != EICU_WAITING) - eicup->channel[channel].config->capture_cb(eicup, channel, 0, 0); -} - -/** - * @brief Common ISR code, EICU timer overflow event. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @notapi - */ -#define _eicu_isr_invoke_overflow_cb(icup) do { \ - (eicup)->config->overflow_cb(eicup, 0, 0, 0); \ -} while (0) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void eicuInit(void); - void eicuObjectInit(EICUDriver *eicup); - void eicuStart(EICUDriver *eicup, const EICUConfig *config); - void eicuStop(EICUDriver *eicup); - void eicuEnable(EICUDriver *eicup); - void eicuDisable(EICUDriver *eicup); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EICU */ - -#endif /* _EICU_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/include/hal_nand.h b/ChibiOS_16.1.5/community/os/hal/include/hal_nand.h deleted file mode 100644 index d5a1c04..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/hal_nand.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file nand.h - * @brief NAND Driver macros and structures. - * - * @addtogroup NAND - * @{ - */ - -#ifndef _NAND_H_ -#define _NAND_H_ - -#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Standard NAND flash commands - */ -#define NAND_CMD_READ0 0x00 -#define NAND_CMD_RNDOUT 0x05 -#define NAND_CMD_PAGEPROG 0x10 -#define NAND_CMD_READ0_CONFIRM 0x30 -#define NAND_CMD_READOOB 0x50 -#define NAND_CMD_ERASE 0x60 -#define NAND_CMD_STATUS 0x70 -#define NAND_CMD_STATUS_MULTI 0x71 -#define NAND_CMD_WRITE 0x80 -#define NAND_CMD_RNDIN 0x85 -#define NAND_CMD_READID 0x90 -#define NAND_CMD_ERASE_CONFIRM 0xD0 -#define NAND_CMD_RESET 0xFF - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @brief Enables the mutual exclusion APIs on the NAND. - */ -#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define NAND_USE_MUTUAL_EXCLUSION FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ -#if NAND_USE_MUTUAL_EXCLUSION && !CH_CFG_USE_MUTEXES && !CH_CFG_USE_SEMAPHORES -#error "NAND_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - NAND_UNINIT = 0, /**< Not initialized. */ - NAND_STOP = 1, /**< Stopped. */ - NAND_READY = 2, /**< Ready. */ - NAND_PROGRAM = 3, /**< Programming in progress. */ - NAND_ERASE = 4, /**< Erasing in progress. */ - NAND_WRITE = 5, /**< Writing to NAND buffer. */ - NAND_READ = 6, /**< Reading from NAND. */ - NAND_DMA_TX = 7, /**< DMA transmitting. */ - NAND_DMA_RX = 8, /**< DMA receiving. */ -} nandstate_t; - -/** - * @brief Type of a structure representing a NAND driver. - */ -typedef struct NANDDriver NANDDriver; - -#include "hal_nand_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void nandInit(void); - void nandObjectInit(NANDDriver *nandp); - void nandStart(NANDDriver *nandp, const NANDConfig *config, bitmap_t *bb_map); - void nandStop(NANDDriver *nandp); - void nandReadPageWhole(NANDDriver *nandp, uint32_t block, uint32_t page, - uint8_t *data, size_t datalen); - void nandMarkBad(NANDDriver *nandp, uint32_t block); - void nandReadPageData(NANDDriver *nandp, uint32_t block, uint32_t page, - uint8_t *data, size_t datalen, uint32_t *ecc); - void nandReadPageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, - uint8_t *spare, size_t sparelen); - uint8_t nandWritePageWhole(NANDDriver *nandp, uint32_t block, uint32_t page, - const uint8_t *data, size_t datalen); - uint8_t nandWritePageData(NANDDriver *nandp, uint32_t block, uint32_t page, - const uint8_t *data, size_t datalen, uint32_t *ecc); - uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, - const uint8_t *spare, size_t sparelen); - uint8_t nandReadBadMark(NANDDriver *nandp, uint32_t block, uint32_t page); - uint8_t nandErase(NANDDriver *nandp, uint32_t block); - bool nandIsBad(NANDDriver *nandp, uint32_t block); -#if NAND_USE_MUTUAL_EXCLUSION - void nandAcquireBus(NANDDriver *nandp); - void nandReleaseBus(NANDDriver *nandp); -#endif /* NAND_USE_MUTUAL_EXCLUSION */ -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_NAND */ - -#endif /* _NAND_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/include/hal_onewire.h b/ChibiOS_16.1.5/community/os/hal/include/hal_onewire.h deleted file mode 100644 index 9fb5be2..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/hal_onewire.h +++ /dev/null @@ -1,366 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file onewire.h - * @brief 1-wire Driver macros and structures. - * - * @addtogroup onewire - * @{ - */ - -#ifndef _ONEWIRE_H_ -#define _ONEWIRE_H_ - -#if (HAL_USE_ONEWIRE == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ -/** - * @brief Enable synthetic test for 'search ROM' procedure. - * @note Only for debugging/testing! - */ -#define ONEWIRE_SYNTH_SEARCH_TEST FALSE - -/** - * @brief Aliases for 1-wire protocol. - */ -#define ONEWIRE_CMD_READ_ROM 0x33 -#define ONEWIRE_CMD_SEARCH_ROM 0xF0 -#define ONEWIRE_CMD_MATCH_ROM 0x55 -#define ONEWIRE_CMD_SKIP_ROM 0xCC -#define ONEWIRE_CMD_CONVERT_TEMP 0x44 -#define ONEWIRE_CMD_READ_SCRATCHPAD 0xBE - -/** - * @brief How many bits will be used for transaction length storage. - */ -#define ONEWIRE_REG_BYTES_WIDTH 16U - -/** - * @brief Precalculated maximum transaction length. - */ -#define ONEWIRE_MAX_TRANSACTION_LEN ((1U << ONEWIRE_REG_BYTES_WIDTH) - 1U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !HAL_USE_PWM -#error "1-wire Driver requires HAL_USE_PWM" -#endif - -#if !HAL_USE_PAL -#error "1-wire Driver requires HAL_USE_PAL" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -#if ONEWIRE_USE_STRONG_PULLUP -/** - * @brief 1-wire strong pull up assert callback type. - */ -typedef void (*onewire_pullup_assert_t)(void); - -/** - * @brief 1-wire strong pull up release callback type. - */ -typedef void (*onewire_pullup_release_t)(void); -#endif /* ONEWIRE_USE_STRONG_PULLUP */ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - ONEWIRE_UNINIT = 0, /**< Not initialized. */ - ONEWIRE_STOP = 1, /**< Stopped. */ - ONEWIRE_READY = 2, /**< Ready. */ -#if ONEWIRE_USE_STRONG_PULLUP - ONEWIRE_PULL_UP /**< Pull up asserted. */ -#endif -} onewire_state_t; - -#if ONEWIRE_USE_SEARCH_ROM -/** - * @brief Search ROM procedure possible state. - */ -typedef enum { - ONEWIRE_SEARCH_ROM_SUCCESS = 0, /**< ROM successfully discovered. */ - ONEWIRE_SEARCH_ROM_LAST = 1, /**< Last ROM successfully discovered. */ - ONEWIRE_SEARCH_ROM_ERROR = 2 /**< Error happened during search. */ -} search_rom_result_t; - -/** - * @brief Search ROM procedure iteration enum. - */ -typedef enum { - ONEWIRE_SEARCH_ROM_FIRST = 0, /**< First search run. */ - ONEWIRE_SEARCH_ROM_NEXT = 1 /**< Next search run. */ -} search_iteration_t; -#endif /* ONEWIRE_USE_SEARCH_ROM */ - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief Pointer to @p PWM driver used for communication. - */ - PWMDriver *pwmd; - /** - * @brief Pointer to configuration structure for underlying PWM driver. - * @note It is NOT constant because 1-wire driver needs to change them - * during normal functioning. - */ - PWMConfig *pwmcfg; - /** - * @brief Active logic level for master channel. - * @details Just set it to @p PWM_OUTPUT_ACTIVE_LOW when 1-wire bus - * connected to direct (not complementary) output of the timer. - * In opposite case you need to check documentation to choose - * correct value. - */ - pwmmode_t pwmmode; - /** - * @brief Number of PWM channel used as master pulse generator. - */ - size_t master_channel; - /** - * @brief Number of PWM channel used as sample interrupt generator. - */ - size_t sample_channel; - /** - * @brief Port Identifier. - * @details This type can be a scalar or some kind of pointer, do not make - * any assumption about it, use the provided macros when populating - * variables of this type. - */ - ioportid_t port; - /** - * @brief Digital I/O port pad. - */ - ioportmask_t pad; -#if defined(STM32F1XX) - /** - * @brief Digital I/O mode for idle bus. - * @details This is a kind of workaround against F1x realization of alternate - * function. Alternate function mode will be activated only - * when you starts appropriate peripheral. - */ - iomode_t pad_mode_idle; -#endif - /** - * @brief Digital I/O mode for active bus. - */ - iomode_t pad_mode_active; -#if ONEWIRE_USE_STRONG_PULLUP - /** - * @brief Pointer to function asserting of strong pull up. - */ - onewire_pullup_assert_t pullup_assert; - /** - * @brief Pointer to function releasing of strong pull up. - */ - onewire_pullup_release_t pullup_release; -#endif -} onewireConfig; - -#if ONEWIRE_USE_SEARCH_ROM -/** - * @brief Search ROM registry. Contains small variables used - * in 'search ROM' procedure. - */ -typedef struct { - /** - * @brief Bool flag. True when bus has single slave device. - */ - uint32_t single_device: 1; - /** - * @brief Search iteration (@p search_iteration_t enum). - */ - uint32_t search_iter: 1; - /** - * @brief Result of discovery procedure (@p search_rom_result_t enum). - */ - uint32_t result: 2; - /** - * @brief One of 3 steps of bit discovery. - * @details 0 - direct, 1 - complemented, 2 - generated by master. - */ - uint32_t bit_step: 2; - /** - * @brief Values acquired during bit discovery. - */ - uint32_t bit_buf: 2; - /** - * @brief Currently processing ROM bit. - * @note Must be big enough to store number 64. - */ - uint32_t rombit: 7; - /** - * @brief Total device count discovered on bus. - * @note Maximum 256. - */ - uint32_t devices_found: 8; -} search_rom_reg_t; - -/** - * @brief Helper structure for 'search ROM' procedure - */ -typedef struct { - /** - * @brief Search ROM registry. - */ - search_rom_reg_t reg; - /** - * @brief Pointer to buffer with currently discovering ROM - */ - uint8_t *retbuf; - /** - * @brief Previously discovered ROM. - */ - uint8_t prev_path[8]; - /** - * @brief Last zero turn branch. - * @note Negative values use to point out of device tree's root. - */ - int8_t last_zero_branch; - /** - * @brief Previous zero turn branch. - * @note Negative values use to point out of device tree's root. - */ - int8_t prev_zero_branch; -} onewire_search_rom_t; -#endif /* ONEWIRE_USE_SEARCH_ROM */ - -/** - * @brief Onewire registry. Some small variables combined - * in single machine word to save RAM. - */ -typedef struct { -#if ONEWIRE_USE_STRONG_PULLUP - /** - * @brief This flag will be asserted by driver to signalizes - * ISR part when strong pull up needed. - */ - uint32_t need_pullup: 1; -#endif - /** - * @brief Bool flag. If @p true than at least one device presence on bus. - */ - uint32_t slave_present: 1; - /** - * @brief Driver internal state (@p onewire_state_t enum). - */ - uint32_t state: 2; - /** - * @brief Bit number in currently receiving/sending byte. - * @note Must be big enough to store 8. - */ - uint32_t bit: 4; - /** - * @brief Bool flag for premature timer stop prevention. - */ - uint32_t final_timeslot: 1; - /** - * @brief Bytes number to be processing in current transaction. - */ - uint32_t bytes: ONEWIRE_REG_BYTES_WIDTH; -} onewire_reg_t; - -/** - * @brief Structure representing an 1-wire driver. - */ -typedef struct { - /** - * @brief Onewire registry. - */ - onewire_reg_t reg; - /** - * @brief Onewire config. - */ - const onewireConfig *config; - /** - * @brief Pointer to I/O data buffer. - */ - uint8_t *buf; -#if ONEWIRE_USE_SEARCH_ROM - /** - * @brief Search ROM helper structure. - */ - onewire_search_rom_t search_rom; -#endif /* ONEWIRE_USE_SEARCH_ROM */ - /** - * @brief Thread waiting for I/O completion. - */ - thread_reference_t thread; -} onewireDriver; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern onewireDriver OWD1; - -#ifdef __cplusplus -extern "C" { -#endif - void onewireInit(void); - void onewireObjectInit(onewireDriver *owp); - void onewireStart(onewireDriver *owp, const onewireConfig *config); - void onewireStop(onewireDriver *owp); - bool onewireReset(onewireDriver *owp); - void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes); - uint8_t onewireCRC(const uint8_t *buf, size_t len); - void onewireWrite(onewireDriver *owp, uint8_t *txbuf, - size_t txbytes, systime_t pullup_time); -#if ONEWIRE_USE_SEARCH_ROM - size_t onewireSearchRom(onewireDriver *owp, - uint8_t *result, size_t max_rom_cnt); -#endif /* ONEWIRE_USE_SEARCH_ROM */ -#if ONEWIRE_SYNTH_SEARCH_TEST - void _synth_ow_write_bit(onewireDriver *owp, ioline_t bit); - ioline_t _synth_ow_read_bit(void); - void synthSearchRomTest(onewireDriver *owp); -#endif /* ONEWIRE_SYNTH_SEARCH_TEST */ -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ONEWIRE */ - -#endif /* _ONEWIRE_H_ */ - -/** @} */ - - - - - - - - - diff --git a/ChibiOS_16.1.5/community/os/hal/include/hal_qei.h b/ChibiOS_16.1.5/community/os/hal/include/hal_qei.h deleted file mode 100644 index 92f03fc..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/hal_qei.h +++ /dev/null @@ -1,130 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2016 Martino Migliavacca
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file hal_qei.h
- * @brief QEI Driver macros and structures.
- *
- * @addtogroup QEI
- * @{
- */
-
-#ifndef HAL_QEI_H
-#define HAL_QEI_H
-
-#if (HAL_USE_QEI == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Driver state machine possible states.
- */
-typedef enum {
- QEI_UNINIT = 0, /**< Not initialized. */
- QEI_STOP = 1, /**< Stopped. */
- QEI_READY = 2, /**< Ready. */
- QEI_ACTIVE = 3, /**< Active. */
-} qeistate_t;
-
-/**
- * @brief Type of a structure representing an QEI driver.
- */
-typedef struct QEIDriver QEIDriver;
-
-/**
- * @brief QEI notification callback type.
- *
- * @param[in] qeip pointer to a @p QEIDriver object
- */
-typedef void (*qeicallback_t)(QEIDriver *qeip);
-
-#include "hal_qei_lld.h"
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Enables the input capture.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- *
- * @iclass
- */
-#define qeiEnableI(qeip) qei_lld_enable(qeip)
-
-/**
- * @brief Disables the input capture.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- *
- * @iclass
- */
-#define qeiDisableI(qeip) qei_lld_disable(qeip)
-
-/**
- * @brief Returns the counter value.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- * @return The current counter value.
- *
- * @iclass
- */
-#define qeiGetCountI(qeip) qei_lld_get_count(qeip)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void qeiInit(void);
- void qeiObjectInit(QEIDriver *qeip);
- void qeiStart(QEIDriver *qeip, const QEIConfig *config);
- void qeiStop(QEIDriver *qeip);
- void qeiEnable(QEIDriver *qeip);
- void qeiDisable(QEIDriver *qeip);
- qeicnt_t qeiGetCount(QEIDriver *qeip);
- qeidelta_t qeiUpdate(QEIDriver *qeip);
- qeidelta_t qeiUpdateI(QEIDriver *qeip);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_QEI == TRUE */
-
-#endif /* HAL_QEI_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/include/hal_rng.h b/ChibiOS_16.1.5/community/os/hal/include/hal_rng.h deleted file mode 100644 index 0e3c484..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/hal_rng.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - RNG for ChibiOS - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef _RNG_H_ -#define _RNG_H_ - -#if (HAL_USE_RNG == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief Enables the @p rngAcquireBus() and @p rngReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(RNG_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define RNG_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - RNG_UNINIT, /* Not initialized. */ - RNG_STOP, /* Stopped. */ - RNG_READY, /* Ready. */ -} rngstate_t; - -#include "hal_rng_lld.h" - - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Low level driver helper macros - * @{ - */ - -/** - * @brief Wakes up the waiting thread. - * - * @param[in] rngp pointer to the @p RNGDriver object - * - * @notapi - */ -#define _rng_wakeup_isr(rngp) { \ - osalSysLockFromISR(); \ - osalThreadResumeI(&(rngp)->thread, MSG_OK); \ - osalSysUnlockFromISR(); \ -} - -/** - * @brief Common ISR code. - * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. - * - Driver state transitions. - * . - * @note This macro is meant to be used in the low level drivers - * implementation only. - * - * @param[in] rngp pointer to the @p RNGDriver object - * - * @notapi - */ -#define _rng_isr_code(rngp, rng) { \ - if ((rngp)->config->end_cb) { \ - (rngp)->state = RNG_COMPLETE; \ - (rngp)->config->end_cb(rngp, rng); \ - if ((rngp)->state == RNG_COMPLETE) \ - (rngp)->state = RNG_READY; \ - } \ - else \ - (rngp)->state = RNG_READY; \ - _rng_wakeup_isr(rngp); \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void rngInit(void); - void rngObjectInit(RNGDriver *rngp); - void rngStart(RNGDriver *rngp, const RNGConfig *config); - void rngStop(RNGDriver *rngp); - msg_t rngWriteI(RNGDriver *rngp, uint8_t *buf, size_t n, systime_t timeout); - msg_t rngWrite(RNGDriver *rngp, uint8_t *buf, size_t n, systime_t timeout); -#if RNG_USE_MUTUAL_EXCLUSION == TRUE - void rngAcquireUnit(RNGDriver *rngp); - void rngReleaseUnit(RNGDriver *rngp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_RNG */ - -#endif /* _RNG_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/include/hal_timcap.h b/ChibiOS_16.1.5/community/os/hal/include/hal_timcap.h deleted file mode 100644 index bd43dd1..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/hal_timcap.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see <http://www.gnu.org/licenses/>. -*/ - -/** - * @file timcap.h - * @brief TIMCAP Driver macros and structures. - * - * @addtogroup TIMCAP - * @{ - */ - -#ifndef _TIMCAP_H_ -#define _TIMCAP_H_ - -#include "ch.h" -#include "hal.h" - -#if (HAL_USE_TIMCAP == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - TIMCAP_UNINIT = 0, /**< Not initialized. */ - TIMCAP_STOP = 1, /**< Stopped. */ - TIMCAP_READY = 2, /**< Ready. */ - TIMCAP_WAITING = 3, /**< Waiting first edge. */ - TIMCAP_ACTIVE = 4, /**< Active cycle phase. */ - TIMCAP_IDLE = 5, /**< Idle cycle phase. */ -} timcapstate_t; - -/** - * @brief Type of a structure representing an TIMCAP driver. - */ -typedef struct TIMCAPDriver TIMCAPDriver; - - -/** - * @brief TIMCAP notification callback type. - * - * @param[in] timcapp pointer to a @p TIMCAPDriver object - */ -typedef void (*timcapcallback_t)(TIMCAPDriver *timcapp); - -#include "hal_timcap_lld.h" - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Enables the input capture. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @iclass - */ -#define timcapEnableI(timcapp) timcap_lld_enable(timcapp) - -/** - * @brief Disables the input capture. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @iclass - */ -#define timcapDisableI(timcapp) timcap_lld_disable(timcapp) - - - - -/** @} */ - -/** - * @name Low Level driver helper macros - * @{ - */ - - -/** - * @brief Common ISR code, TIMCAP channel 1 event. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -#define _timcap_isr_invoke_channel1_cb(timcapp) { \ - timcapstate_t previous_state = (timcapp)->state; \ - (timcapp)->state = TIMCAP_ACTIVE; \ - if (previous_state != TIMCAP_WAITING) \ - (timcapp)->config->capture_cb_array[0](timcapp); \ -} - -/** - * @brief Common ISR code, TIMCAP channel 2 event. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -#define _timcap_isr_invoke_channel2_cb(timcapp) { \ - timcapstate_t previous_state = (timcapp)->state; \ - (timcapp)->state = TIMCAP_ACTIVE; \ - if (previous_state != TIMCAP_WAITING) \ - (timcapp)->config->capture_cb_array[1](timcapp); \ -} - -/** - * @brief Common ISR code, TIMCAP channel 3 event. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -#define _timcap_isr_invoke_channel3_cb(timcapp) { \ - timcapstate_t previous_state = (timcapp)->state; \ - (timcapp)->state = TIMCAP_ACTIVE; \ - if (previous_state != TIMCAP_WAITING) \ - (timcapp)->config->capture_cb_array[2](timcapp); \ -} - -/** - * @brief Common ISR code, TIMCAP channel 4 event. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -#define _timcap_isr_invoke_channel4_cb(timcapp) { \ - timcapstate_t previous_state = (timcapp)->state; \ - (timcapp)->state = TIMCAP_ACTIVE; \ - if (previous_state != TIMCAP_WAITING) \ - (timcapp)->config->capture_cb_array[3](timcapp); \ -} - -/** - * @brief Common ISR code, TIMCAP timer overflow event. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -#define _timcap_isr_invoke_overflow_cb(timcapp) { \ - (timcapp)->config->overflow_cb(timcapp); \ -} -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void timcapInit(void); - void timcapObjectInit(TIMCAPDriver *timcapp); - void timcapStart(TIMCAPDriver *timcapp, const TIMCAPConfig *config); - void timcapStop(TIMCAPDriver *timcapp); - void timcapEnable(TIMCAPDriver *timcapp); - void timcapDisable(TIMCAPDriver *timcapp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_TIMCAP */ - -#endif /* _TIMCAP_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/include/hal_usb_hid.h b/ChibiOS_16.1.5/community/os/hal/include/hal_usb_hid.h deleted file mode 100644 index 2a2d73a..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/hal_usb_hid.h +++ /dev/null @@ -1,510 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Jonathan Struebel
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file hal_usb_hid.h
- * @brief USB HID macros and structures.
- *
- * @addtogroup USB_HID
- * @{
- */
-
-#ifndef HAL_USB_HID_H
-#define HAL_USB_HID_H
-
-#if (HAL_USE_USB_HID == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name HID specific messages.
- * @{
- */
-#define HID_GET_REPORT 0x01U
-#define HID_GET_IDLE 0x02U
-#define HID_GET_PROTOCOL 0x03U
-#define HID_SET_REPORT 0x09U
-#define HID_SET_IDLE 0x0AU
-#define HID_SET_PROTOCOL 0x0BU
-/** @} */
-
-/**
- * @name HID classes
- * @{
- */
-#define HID_INTERFACE_CLASS 0x03U
-/** @} */
-
-/**
- * @name HID subclasses
- * @{
- */
-#define HID_BOOT_INTERFACE 0x01U
-/** @} */
-
-/**
- * @name HID descriptors
- * @{
- */
-#define USB_DESCRIPTOR_HID 0x21U
-#define HID_REPORT 0x22U
-#define HID_PHYSICAL 0x23U
-/** @} */
-
-/**
- * @name HID Report items
- * @{
- */
-#define HID_REPORT_USAGE_PAGE 0x04
-#define HID_REPORT_USAGE 0x08
-#define HID_REPORT_LOGICAL_MINIMUM 0x14
-#define HID_REPORT_USAGE_MINIMUM 0x18
-#define HID_REPORT_LOGICAL_MAXIMUM 0x24
-#define HID_REPORT_USAGE_MAXIMUM 0x28
-#define HID_REPORT_REPORT_SIZE 0x74
-#define HID_REPORT_INPUT 0x80
-#define HID_REPORT_REPORT_COUNT 0x94
-#define HID_REPORT_COLLECTION 0xA0
-#define HID_REPORT_END_COLLECTION 0xC0
-/** @} */
-
-/**
- * @name HID Collection item definitions
- * @{
- */
-#define HID_COLLECTION_PHYSICAL 0x00
-#define HID_COLLECTION_APPLICATION 0x01
-#define HID_COLLECTION_LOGICAL 0x02
-#define HID_COLLECTION_REPORT 0x03
-#define HID_COLLECTION_NAMED_ARRAY 0x04
-#define HID_COLLECTION_USAGE_SWITCH 0x05
-#define HID_COLLECTION_USAGE_MODIFIER 0x06
-/** @} */
-
-/**
- * @name HID Usage Page item definitions
- * @{
- */
-#define HID_USAGE_PAGE_GENERIC_DESKTOP 0x01
-#define HID_USAGE_PAGE_SIMULATION 0x02
-#define HID_USAGE_PAGE_VR 0x03
-#define HID_USAGE_PAGE_SPORT 0x04
-#define HID_USAGE_PAGE_GAME 0x05
-#define HID_USAGE_PAGE_GENERIC_DEVICE 0x06
-#define HID_USAGE_PAGE_KEYBOARD_KEYPAD 0x07
-#define HID_USAGE_PAGE_LEDS 0x08
-#define HID_USAGE_PAGE_BUTTON 0x09
-#define HID_USAGE_PAGE_ORDINAL 0x0A
-#define HID_USAGE_PAGE_TELEPHONY 0x0B
-#define HID_USAGE_PAGE_CONSUMER 0x0C
-#define HID_USAGE_PAGE_DIGITIZER 0x0D
-#define HID_USAGE_PAGE_PID 0x0F
-#define HID_USAGE_PAGE_UNICODE 0x10
-/** @} */
-
-/**
- * @name HID Usage item definitions
- * @{
- */
-#define HID_USAGE_ALPHANUMERIC_DISPLAY 0x14
-#define HID_USAGE_MEDICAL_INSTRUMENTS 0x40
-#define HID_USAGE_MONITOR_PAGE1 0x80
-#define HID_USAGE_MONITOR_PAGE2 0x81
-#define HID_USAGE_MONITOR_PAGE3 0x82
-#define HID_USAGE_MONITOR_PAGE4 0x83
-#define HID_USAGE_POWER_PAGE1 0x84
-#define HID_USAGE_POWER_PAGE2 0x85
-#define HID_USAGE_POWER_PAGE3 0x86
-#define HID_USAGE_POWER_PAGE4 0x87
-#define HID_USAGE_BAR_CODE_SCANNER_PAGE 0x8C
-#define HID_USAGE_SCALE_PAGE 0x8D
-#define HID_USAGE_MSR_PAGE 0x8E
-#define HID_USAGE_CAMERA_PAGE 0x90
-#define HID_USAGE_ARCADE_PAGE 0x91
-
-#define HID_USAGE_POINTER 0x01
-#define HID_USAGE_MOUSE 0x02
-#define HID_USAGE_JOYSTICK 0x04
-#define HID_USAGE_GAMEPAD 0x05
-#define HID_USAGE_KEYBOARD 0x06
-#define HID_USAGE_KEYPAD 0x07
-#define HID_USAGE_MULTIAXIS_CONTROLLER 0x08
-
-#define HID_USAGE_BUTTON1 0x01
-#define HID_USAGE_BUTTON2 0x02
-#define HID_USAGE_BUTTON3 0x03
-#define HID_USAGE_BUTTON4 0x04
-#define HID_USAGE_BUTTON5 0x05
-#define HID_USAGE_BUTTON6 0x06
-#define HID_USAGE_BUTTON7 0x07
-#define HID_USAGE_BUTTON8 0x08
-
-#define HID_USAGE_X 0x30
-#define HID_USAGE_Y 0x31
-#define HID_USAGE_Z 0x32
-#define HID_USAGE_RX 0x33
-#define HID_USAGE_RY 0x34
-#define HID_USAGE_RZ 0x35
-#define HID_USAGE_VX 0x40
-#define HID_USAGE_VY 0x41
-#define HID_USAGE_VZ 0x42
-#define HID_USAGE_VBRX 0x43
-#define HID_USAGE_VBRY 0x44
-#define HID_USAGE_VBRZ 0x45
-#define HID_USAGE_VNO 0x46
-/** @} */
-
-/**
- * @name HID Input item definitions.
- * @{
- */
-#define HID_INPUT_DATA_VAR_ABS 0x02
-#define HID_INPUT_CNST_VAR_ABS 0x03
-#define HID_INPUT_DATA_VAR_REL 0x06
-/** @} */
-
-/**
- * @name Helper macros for USB HID descriptors
- * @{
- */
-/*
- * @define HID Descriptor size.
- */
-#define USB_DESC_HID_SIZE 9U
-
-/**
- * @brief HID Descriptor helper macro.
- * @note This macro can only be used with a single HID report descriptor
- */
-#define USB_DESC_HID(bcdHID, bCountryCode, bNumDescriptors, \
- bDescriptorType, wDescriptorLength) \
- USB_DESC_BYTE(USB_DESC_HID_SIZE), \
- USB_DESC_BYTE(USB_DESCRIPTOR_HID), \
- USB_DESC_BCD(bcdHID), \
- USB_DESC_BYTE(bCountryCode), \
- USB_DESC_BYTE(bNumDescriptors), \
- USB_DESC_BYTE(bDescriptorType), \
- USB_DESC_WORD(wDescriptorLength)
-
-/**
- * @brief HID Report Usage Page item helper macro (Single byte).
- */
-#define HID_USAGE_PAGE_B(up) \
- USB_DESC_BYTE(HID_REPORT_USAGE_PAGE | 0x01), \
- USB_DESC_BYTE(up)
-
-/**
- * @brief HID Report Usage Page item helper macro (Double byte).
- */
-#define HID_USAGE_PAGE_W(up) \
- USB_DESC_BYTE(HID_REPORT_USAGE_PAGE | 0x02), \
- USB_DESC_WORD(up)
-
-/**
- * @brief HID Report Usage item helper macro (Single byte).
- */
-#define HID_USAGE_B(u) \
- USB_DESC_BYTE(HID_REPORT_USAGE | 0x01), \
- USB_DESC_BYTE(u)
-
-/**
- * @brief HID Report Usage item helper macro (Double byte).
- */
-#define HID_USAGE_W(u) \
- USB_DESC_BYTE(HID_REPORT_USAGE | 0x02), \
- USB_DESC_WORD(u)
-
-/**
- * @brief HID Report Collection item helper macro (Single Byte).
- */
-#define HID_COLLECTION_B(c) \
- USB_DESC_BYTE(HID_REPORT_COLLECTION | 0x01), \
- USB_DESC_BYTE(c)
-
-/**
- * @brief HID Report Collection item helper macro (Double Byte).
- */
-#define HID_COLLECTION_W(c) \
- USB_DESC_BYTE(HID_REPORT_COLLECTION | 0x02), \
- USB_DESC_WORD(c)
-
-/**
- * @brief HID Report End Collection item helper macro.
- */
-#define HID_END_COLLECTION \
- USB_DESC_BYTE(HID_REPORT_END_COLLECTION)
-
-/**
- * @brief HID Report Usage Minimum item helper macro (Single byte).
- */
-#define HID_USAGE_MINIMUM_B(x) \
- USB_DESC_BYTE(HID_REPORT_USAGE_MINIMUM | 0x01), \
- USB_DESC_BYTE(x)
-
-/**
- * @brief HID Report Usage Minimum item helper macro (Double byte).
- */
-#define HID_USAGE_MINIMUM_W(x) \
- USB_DESC_BYTE(HID_REPORT_USAGE_MINIMUM | 0x02), \
- USB_DESC_WORD(x)
-
-/**
- * @brief HID Report Usage Maximum item helper macro (Single byte).
- */
-#define HID_USAGE_MAXIMUM_B(x) \
- USB_DESC_BYTE(HID_REPORT_USAGE_MAXIMUM | 0x01), \
- USB_DESC_BYTE(x)
-
-/**
- * @brief HID Report Usage Maximum item helper macro (Double byte).
- */
-#define HID_USAGE_MAXIMUM_W(x) \
- USB_DESC_BYTE(HID_REPORT_USAGE_MAXIMUM | 0x02), \
- USB_DESC_WORD(x)
-
-/**
- * @brief HID Report Logical Minimum item helper macro (Single byte).
- */
-#define HID_LOGICAL_MINIMUM_B(x) \
- USB_DESC_BYTE(HID_REPORT_LOGICAL_MINIMUM | 0x01), \
- USB_DESC_BYTE(x)
-
-/**
- * @brief HID Report Logical Minimum item helper macro (Double byte).
- */
-#define HID_LOGICAL_MINIMUM_W(x) \
- USB_DESC_BYTE(HID_REPORT_LOGICAL_MINIMUM | 0x02), \
- USB_DESC_WORD(x)
-
-/**
- * @brief HID Report Logical Maximum item helper macro (Single byte).
- */
-#define HID_LOGICAL_MAXIMUM_B(x) \
- USB_DESC_BYTE(HID_REPORT_LOGICAL_MAXIMUM | 0x01), \
- USB_DESC_BYTE(x)
-
-/**
- * @brief HID Report Logical Maximum item helper macro (Double byte).
- */
-#define HID_LOGICAL_MAXIMUM_W(x) \
- USB_DESC_BYTE(HID_REPORT_LOGICAL_MAXIMUM | 0x02), \
- USB_DESC_WORD(x)
-
-/**
- * @brief HID Report Count item helper macro (Single byte).
- */
-#define HID_REPORT_COUNT_B(x) \
- USB_DESC_BYTE(HID_REPORT_REPORT_COUNT | 0x01), \
- USB_DESC_BYTE(x)
-
-/**
- * @brief HID Report Count item helper macro (Double byte).
- */
-#define HID_REPORT_COUNT_W(x) \
- USB_DESC_BYTE(HID_REPORT_REPORT_COUNT | 0x02), \
- USB_DESC_WORD(x)
-
-/**
- * @brief HID Report Size item helper macro (Single byte).
- */
-#define HID_REPORT_SIZE_B(x) \
- USB_DESC_BYTE(HID_REPORT_REPORT_SIZE | 0x01), \
- USB_DESC_BYTE(x)
-
-/**
- * @brief HID Report Size item helper macro (Double byte).
- */
-#define HID_REPORT_SIZE_W(x) \
- USB_DESC_BYTE(HID_REPORT_REPORT_SIZE | 0x02), \
- USB_DESC_WORD(x)
-
-/**
- * @brief HID Report Input item helper macro (Single byte).
- */
-#define HID_INPUT_B(x) \
- USB_DESC_BYTE(HID_REPORT_INPUT | 0x01), \
- USB_DESC_BYTE(x)
-
-/**
- * @brief HID Report Input item helper macro (Double byte).
- */
-#define HID_INPUT_W(x) \
- USB_DESC_BYTE(HID_REPORT_INPUT | 0x02), \
- USB_DESC_WORD(x)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name USB HID configuration options
- * @{
- */
-/**
- * @brief USB HID buffers size.
- * @details Configuration parameter, the buffer size must be a multiple of
- * the USB data endpoint maximum packet size.
- * @note The default is 256 bytes for both the transmission and receive
- * buffers.
- */
-#if !defined(USB_HID_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define USB_HID_BUFFERS_SIZE 256
-#endif
-
-/**
- * @brief USB HID number of buffers.
- * @note The default is 2 buffers.
- */
-#if !defined(USB_HID_BUFFERS_NUMBER) || defined(__DOXYGEN__)
-#define USB_HID_BUFFERS_NUMBER 2
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if HAL_USE_USB == FALSE
-#error "USB HID Driver requires HAL_USE_USB"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Driver state machine possible states.
- */
-typedef enum {
- HID_UNINIT = 0, /**< Not initialized. */
- HID_STOP = 1, /**< Stopped. */
- HID_READY = 2 /**< Ready. */
-} hidstate_t;
-
-/**
- * @brief Structure representing a USB HID driver.
- */
-typedef struct USBHIDDriver USBHIDDriver;
-
-/**
- * @brief USB HID Driver configuration structure.
- * @details An instance of this structure must be passed to @p hidStart()
- * in order to configure and start the driver operations.
- */
-typedef struct {
- /**
- * @brief USB driver to use.
- */
- USBDriver *usbp;
- /**
- * @brief Interrupt IN endpoint used for outgoing data transfer.
- */
- usbep_t int_in;
- /**
- * @brief Interrupt OUT endpoint used for incoming data transfer.
- */
- usbep_t int_out;
-} USBHIDConfig;
-
-/**
- * @brief @p USBHIDDriver specific data.
- */
-#define _usb_hid_driver_data \
- _base_asynchronous_channel_data \
- /* Driver state.*/ \
- hidstate_t state; \
- /* Input buffers queue.*/ \
- input_buffers_queue_t ibqueue; \
- /* Output queue.*/ \
- output_buffers_queue_t obqueue; \
- /* Input buffer.*/ \
- uint8_t ib[BQ_BUFFER_SIZE(USB_HID_BUFFERS_NUMBER, \
- USB_HID_BUFFERS_SIZE)]; \
- /* Output buffer.*/ \
- uint8_t ob[BQ_BUFFER_SIZE(USB_HID_BUFFERS_NUMBER, \
- USB_HID_BUFFERS_SIZE)]; \
- /* End of the mandatory fields.*/ \
- /* Current configuration data.*/ \
- const USBHIDConfig *config;
-
-/**
- * @brief @p USBHIDDriver specific methods.
- */
-#define _usb_hid_driver_methods \
- _base_asynchronous_channel_methods \
- /* Buffer flush method.*/ \
- void (*flush)(void *instance);
-
-/**
- * @extends BaseAsynchronousChannelVMT
- *
- * @brief @p USBHIDDriver virtual methods table.
- */
-struct USBHIDDriverVMT {
- _usb_hid_driver_methods
-};
-
-/**
- * @extends BaseAsynchronousChannel
- *
- * @brief Full duplex USB HID driver class.
- * @details This class extends @p BaseAsynchronousChannel by adding physical
- * I/O queues.
- */
-struct USBHIDDriver {
- /** @brief Virtual Methods Table.*/
- const struct USBHIDDriverVMT *vmt;
- _usb_hid_driver_data
-};
-
-#define USB_DRIVER_EXT_FIELDS \
- USBHIDDriver hid
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-#ifdef __cplusplus
-extern "C" {
-#endif
- void hidInit(void);
- void hidObjectInit(USBHIDDriver *uhdp);
- void hidStart(USBHIDDriver *uhdp, const USBHIDConfig *config);
- void hidStop(USBHIDDriver *uhdp);
- void hidDisconnectI(USBHIDDriver *uhdp);
- void hidConfigureHookI(USBHIDDriver *uhdp);
- bool hidRequestsHook(USBDriver *usbp);
- void hidDataTransmitted(USBDriver *usbp, usbep_t ep);
- void hidDataReceived(USBDriver *usbp, usbep_t ep);
- size_t hidWriteReport(USBHIDDriver *uhdp, uint8_t *bp, size_t n);
- size_t hidWriteReportt(USBHIDDriver *uhdp, uint8_t *bp, size_t n, systime_t timeout);
- size_t hidReadReport(USBHIDDriver *uhdp, uint8_t *bp, size_t n);
- size_t hidReadReportt(USBHIDDriver *uhdp, uint8_t *bp, size_t n, systime_t timeout);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_USB_HID */
-
-#endif /* HAL_USB_HID_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/include/hal_usbh.h b/ChibiOS_16.1.5/community/os/hal/include/hal_usbh.h deleted file mode 100644 index 5fd0047..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/hal_usbh.h +++ /dev/null @@ -1,436 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef USBH_H_ -#define USBH_H_ - -#include "hal.h" - - -#ifndef HAL_USBH_USE_FTDI -#define HAL_USBH_USE_FTDI FALSE -#endif - -#ifndef HAL_USBH_USE_HUB -#define HAL_USBH_USE_HUB FALSE -#endif - -#ifndef HAL_USBH_USE_MSD -#define HAL_USBH_USE_MSD FALSE -#endif - -#ifndef HAL_USBH_USE_UVC -#define HAL_USBH_USE_UVC FALSE -#endif - -#if (HAL_USE_USBH == TRUE) || defined(__DOXYGEN__) - -#include "osal.h" -#include "usbh/list.h" -#include "usbh/defs.h" - -/* TODO: - * - * - Integrate VBUS power switching functionality to the API. - * - */ - - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !HAL_USBH_USE_HUB -#define USBH_MAX_ADDRESSES 1 -#else -#define USBH_MAX_ADDRESSES (HAL_USBHHUB_MAX_PORTS + 1) -#endif - -enum usbh_status { - USBH_STATUS_STOPPED = 0, - USBH_STATUS_STARTED, - USBH_STATUS_SUSPENDED, -}; - -enum usbh_devstatus { - USBH_DEVSTATUS_DISCONNECTED = 0, - USBH_DEVSTATUS_ATTACHED, - USBH_DEVSTATUS_CONNECTED, - USBH_DEVSTATUS_DEFAULT, - USBH_DEVSTATUS_ADDRESS, - USBH_DEVSTATUS_CONFIGURED, -}; - -enum usbh_devspeed { - USBH_DEVSPEED_LOW = 0, - USBH_DEVSPEED_FULL, - USBH_DEVSPEED_HIGH, -}; - -enum usbh_epdir { - USBH_EPDIR_IN = 0x80, - USBH_EPDIR_OUT = 0 -}; - -enum usbh_eptype { - USBH_EPTYPE_CTRL = 0, - USBH_EPTYPE_ISO = 1, - USBH_EPTYPE_BULK = 2, - USBH_EPTYPE_INT = 3, -}; - -enum usbh_epstatus { - USBH_EPSTATUS_UNINITIALIZED = 0, - USBH_EPSTATUS_CLOSED, - USBH_EPSTATUS_OPEN, - USBH_EPSTATUS_HALTED, -}; - -enum usbh_urbstatus { - USBH_URBSTATUS_UNINITIALIZED = 0, - USBH_URBSTATUS_INITIALIZED, - USBH_URBSTATUS_PENDING, -// USBH_URBSTATUS_QUEUED, - USBH_URBSTATUS_ERROR, - USBH_URBSTATUS_TIMEOUT, - USBH_URBSTATUS_CANCELLED, - USBH_URBSTATUS_STALL, - USBH_URBSTATUS_DISCONNECTED, -// USBH_URBSTATUS_EPCLOSED, - USBH_URBSTATUS_OK, -}; - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/* forward declarations */ -typedef struct USBHDriver USBHDriver; -typedef struct usbh_port usbh_port_t; -typedef struct usbh_device usbh_device_t; -typedef struct usbh_ep usbh_ep_t; -typedef struct usbh_urb usbh_urb_t; -typedef struct usbh_baseclassdriver usbh_baseclassdriver_t; -typedef struct usbh_classdriverinfo usbh_classdriverinfo_t; -#if HAL_USBH_USE_HUB -typedef struct USBHHubDriver USBHHubDriver; -#endif - -/* typedefs */ -typedef enum usbh_status usbh_status_t; -typedef enum usbh_devspeed usbh_devspeed_t; -typedef enum usbh_devstatus usbh_devstatus_t; -typedef enum usbh_epdir usbh_epdir_t; -typedef enum usbh_eptype usbh_eptype_t; -typedef enum usbh_epstatus usbh_epstatus_t; -typedef enum usbh_urbstatus usbh_urbstatus_t; -typedef uint16_t usbh_portstatus_t; -typedef uint16_t usbh_portcstatus_t; -typedef void (*usbh_completion_cb)(usbh_urb_t *); - -/* include the low level driver; the required definitions are above */ -#include "hal_usbh_lld.h" - -#define USBH_DEFINE_BUFFER(type, name) USBH_LLD_DEFINE_BUFFER(type, name) - -struct usbh_urb { - usbh_ep_t *ep; - - void *userData; - usbh_completion_cb callback; - - const void *setup_buff; - void *buff; - uint32_t requestedLength; - uint32_t actualLength; - - usbh_urbstatus_t status; - - thread_reference_t waitingThread; - thread_reference_t abortingThread; - - /* Low level part */ - _usbh_urb_ll_data -}; - -struct usbh_ep { - usbh_device_t *device; - usbh_ep_t *next; - - usbh_epstatus_t status; - uint8_t address; - bool in; - usbh_eptype_t type; - uint16_t wMaxPacketSize; - uint8_t bInterval; - - /* debug */ - const char *name; - - /* Low-level part */ - _usbh_ep_ll_data -}; - -struct usbh_device { - USBHDriver *host; /* shortcut to host */ - - usbh_ep_t ctrl; - usbh_ep_t *endpoints; - - usbh_baseclassdriver_t *drivers; - - uint16_t langID0; - - usbh_devstatus_t status; - usbh_devspeed_t speed; - - USBH_DEFINE_BUFFER(usbh_device_descriptor_t, devDesc); - unsigned char align_bytes[2]; - USBH_DEFINE_BUFFER(usbh_config_descriptor_t, basicConfigDesc); - - uint8_t *fullConfigurationDescriptor; - uint8_t keepFullCfgDesc; - - uint8_t address; - uint8_t bConfiguration; - - /* Low level part */ - _usbh_device_ll_data -}; - - -struct usbh_port { -#if HAL_USBH_USE_HUB - USBHHubDriver *hub; -#endif - - usbh_portstatus_t status; - usbh_portcstatus_t c_status; - - usbh_port_t *next; - - uint8_t number; - - usbh_device_t device; - - /* Low level part */ - _usbh_port_ll_data -}; - -struct USBHDriver { - usbh_status_t status; - uint8_t address_bitmap[(USBH_MAX_ADDRESSES + 7) / 8]; - - usbh_port_t rootport; - -#if HAL_USBH_USE_HUB - struct list_head hubs; -#endif - - /* Low level part */ - _usbhdriver_ll_data - -#if USBH_DEBUG_ENABLE - /* debug */ - uint8_t dbg_buff[USBH_DEBUG_BUFFER]; - THD_WORKING_AREA(waDebug, 512); - input_queue_t iq; -#endif -}; - - - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_USBH_USE_OTG1 -extern USBHDriver USBHD1; -#endif - -#if STM32_USBH_USE_OTG2 -extern USBHDriver USBHD2; -#endif - - -/*===========================================================================*/ -/* Main driver API. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - - /* Main functions */ - void usbhObjectInit(USBHDriver *usbh); - void usbhInit(void); - void usbhStart(USBHDriver *usbh); - void usbhStop(USBHDriver *usbh); - void usbhSuspend(USBHDriver *usbh); - void usbhResume(USBHDriver *usbh); - - /* Device-related */ -#if USBH_DEBUG_ENABLE && USBH_DEBUG_ENABLE_INFO - void usbhDevicePrintInfo(usbh_device_t *dev); - void usbhDevicePrintConfiguration(const uint8_t *descriptor, uint16_t rem); -#else -# define usbhDevicePrintInfo(dev) do {} while(0) -# define usbhDevicePrintConfiguration(descriptor, rem) do {} while(0) -#endif - bool usbhDeviceReadString(usbh_device_t *dev, char *dest, uint8_t size, - uint8_t index, uint16_t langID); - static inline usbh_port_t *usbhDeviceGetPort(usbh_device_t *dev) { - return container_of(dev, usbh_port_t, device); - } - - /* Synchronous API */ - usbh_urbstatus_t usbhBulkTransfer(usbh_ep_t *ep, - void *data, - uint32_t len, - uint32_t *actual_len, - systime_t timeout); - usbh_urbstatus_t usbhControlRequest(usbh_device_t *dev, - uint8_t bmRequestType, - uint8_t bRequest, - uint16_t wValue, - uint16_t wIndex, - uint16_t wLength, - uint8_t *buff); - usbh_urbstatus_t usbhControlRequestExtended(usbh_device_t *dev, - const usbh_control_request_t *req, - uint8_t *buff, - uint32_t *actual_len, - systime_t timeout); - - /* Standard request helpers */ - bool usbhStdReqGetDeviceDescriptor(usbh_device_t *dev, - uint16_t wLength, - uint8_t *buf); - bool usbhStdReqGetConfigurationDescriptor(usbh_device_t *dev, - uint8_t index, - uint16_t wLength, - uint8_t *buf); - bool usbhStdReqGetStringDescriptor(usbh_device_t *dev, - uint8_t index, - uint16_t langID, - uint16_t wLength, - uint8_t *buf); - bool usbhStdReqSetInterface(usbh_device_t *dev, - uint8_t bInterfaceNumber, - uint8_t bAlternateSetting); - bool usbhStdReqGetInterface(usbh_device_t *dev, - uint8_t bInterfaceNumber, - uint8_t *bAlternateSetting); - - /* Endpoint/pipe management */ - void usbhEPObjectInit(usbh_ep_t *ep, usbh_device_t *dev, const usbh_endpoint_descriptor_t *desc); - static inline void usbhEPOpen(usbh_ep_t *ep) { - osalDbgCheck(ep != 0); - osalSysLock(); - osalDbgAssert(ep->status == USBH_EPSTATUS_CLOSED, "invalid state"); - usbh_lld_ep_open(ep); - ep->next = ep->device->endpoints; - ep->device->endpoints = ep; - osalSysUnlock(); - } - static inline void usbhEPCloseS(usbh_ep_t *ep) { - osalDbgCheck(ep != 0); - osalDbgCheckClassS(); - osalDbgAssert(ep->status != USBH_EPSTATUS_UNINITIALIZED, "invalid state"); - if (ep->status == USBH_EPSTATUS_CLOSED) { - osalOsRescheduleS(); - return; - } - usbh_lld_ep_close(ep); - } - static inline void usbhEPClose(usbh_ep_t *ep) { - osalSysLock(); - usbhEPCloseS(ep); - osalSysUnlock(); - } - static inline void usbhEPResetI(usbh_ep_t *ep) { - osalDbgCheckClassI(); - osalDbgCheck(ep != NULL); - usbh_lld_epreset(ep); - } - static inline bool usbhEPIsPeriodic(usbh_ep_t *ep) { - osalDbgCheck(ep != NULL); - return (ep->type & 1) != 0; - } - static inline bool usbhURBIsBusy(usbh_urb_t *urb) { - osalDbgCheck(urb != NULL); - return (urb->status == USBH_URBSTATUS_PENDING); - } - static inline void usbhEPSetName(usbh_ep_t *ep, const char *name) { - ep->name = name; - } - - /* URB management */ - void usbhURBObjectInit(usbh_urb_t *urb, usbh_ep_t *ep, usbh_completion_cb callback, - void *user, void *buff, uint32_t len); - void usbhURBObjectResetI(usbh_urb_t *urb); - void usbhURBSubmitI(usbh_urb_t *urb); - bool usbhURBCancelI(usbh_urb_t *urb); - msg_t usbhURBSubmitAndWaitS(usbh_urb_t *urb, systime_t timeout); - void usbhURBCancelAndWaitS(usbh_urb_t *urb); - msg_t usbhURBWaitTimeoutS(usbh_urb_t *urb, systime_t timeout); - - /* Main loop */ - void usbhMainLoop(USBHDriver *usbh); - -#ifdef __cplusplus -} -#endif - - -/*===========================================================================*/ -/* Class driver definitions and API. */ -/*===========================================================================*/ - -typedef struct usbh_classdriver_vmt usbh_classdriver_vmt_t; -struct usbh_classdriver_vmt { - usbh_baseclassdriver_t *(*load)(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem); - void (*unload)(usbh_baseclassdriver_t *drv); -}; - -struct usbh_classdriverinfo { - int16_t class; - int16_t subclass; - int16_t protocol; - const char *name; - const usbh_classdriver_vmt_t *vmt; -}; - -#define _usbh_base_classdriver_data \ - const usbh_classdriverinfo_t *info; \ - usbh_device_t *dev; \ - usbh_baseclassdriver_t *next; - -struct usbh_baseclassdriver { - _usbh_base_classdriver_data -}; - - -/*===========================================================================*/ -/* Helper functions. */ -/*===========================================================================*/ -#include <usbh/desciter.h> /* descriptor iterators */ -#include <usbh/debug.h> /* debug */ - -#endif - -#endif /* USBH_H_ */ diff --git a/ChibiOS_16.1.5/community/os/hal/include/usbh/debug.h b/ChibiOS_16.1.5/community/os/hal/include/usbh/debug.h deleted file mode 100644 index 5120121..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/usbh/debug.h +++ /dev/null @@ -1,44 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
- Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-
-#ifndef USBH_DEBUG_H_
-#define USBH_DEBUG_H_
-
-#include "hal_usbh.h"
-
-#if HAL_USE_USBH
-
-//TODO: Debug is only for USBHD1, make it generic.
-
-#if USBH_DEBUG_ENABLE
- void usbDbgPrintf(const char *fmt, ...);
- void usbDbgPuts(const char *s);
- void usbDbgInit(USBHDriver *host);
- void usbDbgReset(void);
- void usbDbgSystemHalted(void);
-#else
-#define usbDbgPrintf(fmt, ...) do {} while(0)
-#define usbDbgPuts(s) do {} while(0)
-#define usbDbgInit(host) do {} while(0)
-#define usbDbgReset() do {} while(0)
-#define usbDbgSystemHalted() do {} while(0)
-#endif
-
-#endif
-
-#endif /* USBH_DEBUG_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/include/usbh/defs.h b/ChibiOS_16.1.5/community/os/hal/include/usbh/defs.h deleted file mode 100644 index c3d8a9a..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/usbh/defs.h +++ /dev/null @@ -1,160 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
- Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef USBH_DEFS_H_
-#define USBH_DEFS_H_
-
-#include "hal.h"
-
-#if HAL_USE_USBH
-
-#include "osal.h"
-
-#ifdef __IAR_SYSTEMS_ICC__
-#define PACKED_STRUCT typedef PACKED_VAR struct
-#else
-#define PACKED_STRUCT typedef struct PACKED_VAR
-#endif
-
-PACKED_STRUCT {
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint16_t bcdUSB;
- uint8_t bDeviceClass;
- uint8_t bDeviceSubClass;
- uint8_t bDeviceProtocol;
- uint8_t bMaxPacketSize0;
- uint16_t idVendor;
- uint16_t idProduct;
- uint16_t bcdDevice;
- uint8_t iManufacturer;
- uint8_t iProduct;
- uint8_t iSerialNumber;
- uint8_t bNumConfigurations;
-} usbh_device_descriptor_t;
-#define USBH_DT_DEVICE 0x01
-#define USBH_DT_DEVICE_SIZE 18
-
-PACKED_STRUCT {
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint16_t wTotalLength;
- uint8_t bNumInterfaces;
- uint8_t bConfigurationValue;
- uint8_t iConfiguration;
- uint8_t bmAttributes;
- uint8_t bMaxPower;
-} usbh_config_descriptor_t;
-#define USBH_DT_CONFIG 0x02
-#define USBH_DT_CONFIG_SIZE 9
-
-PACKED_STRUCT {
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint16_t wData[1];
-} usbh_string_descriptor_t;
-#define USBH_DT_STRING 0x03
-#define USBH_DT_STRING_SIZE 2
-
-PACKED_STRUCT {
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint8_t bInterfaceNumber;
- uint8_t bAlternateSetting;
- uint8_t bNumEndpoints;
- uint8_t bInterfaceClass;
- uint8_t bInterfaceSubClass;
- uint8_t bInterfaceProtocol;
- uint8_t iInterface;
-} usbh_interface_descriptor_t;
-#define USBH_DT_INTERFACE 0x04
-#define USBH_DT_INTERFACE_SIZE 9
-
-PACKED_STRUCT {
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint8_t bEndpointAddress;
- uint8_t bmAttributes;
- uint16_t wMaxPacketSize;
- uint8_t bInterval;
-} usbh_endpoint_descriptor_t;
-#define USBH_DT_ENDPOINT 0x05
-#define USBH_DT_ENDPOINT_SIZE 7
-
-PACKED_STRUCT {
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint8_t bFirstInterface;
- uint8_t bInterfaceCount;
- uint8_t bFunctionClass;
- uint8_t bFunctionSubClass;
- uint8_t bFunctionProtocol;
- uint8_t iFunction;
-} usbh_ia_descriptor_t;
-#define USBH_DT_INTERFACE_ASSOCIATION 0x0b
-#define USBH_DT_INTERFACE_ASSOCIATION_SIZE 8
-
-PACKED_STRUCT {
- uint8_t bDescLength;
- uint8_t bDescriptorType;
- uint8_t bNbrPorts;
- uint16_t wHubCharacteristics;
- uint8_t bPwrOn2PwrGood;
- uint8_t bHubContrCurrent;
- uint32_t DeviceRemovable;
-} usbh_hub_descriptor_t;
-#define USBH_DT_HUB 0x29
-#define USBH_DT_HUB_SIZE (7 + 4)
-
-PACKED_STRUCT {
- uint8_t bmRequestType;
- uint8_t bRequest;
- uint16_t wValue;
- uint16_t wIndex;
- uint16_t wLength;
-} usbh_control_request_t;
-
-
-#define USBH_REQ_GET_STATUS 0x00
-#define USBH_REQ_CLEAR_FEATURE 0x01
-#define USBH_REQ_SET_FEATURE 0x03
-#define USBH_REQ_SET_ADDRESS 0x05
-#define USBH_REQ_GET_DESCRIPTOR 0x06
-#define USBH_REQ_SET_DESCRIPTOR 0x07
-#define USBH_REQ_GET_CONFIGURATION 0x08
-#define USBH_REQ_SET_CONFIGURATION 0x09
-#define USBH_REQ_GET_INTERFACE 0x0A
-#define USBH_REQ_SET_INTERFACE 0x0B
-#define USBH_REQ_SYNCH_FRAME 0x0C
-
-
-#define USBH_REQTYPE_IN 0x80
-#define USBH_REQTYPE_OUT 0x00
-
-#define USBH_REQTYPE_STANDARD 0x00
-#define USBH_REQTYPE_CLASS 0x20
-#define USBH_REQTYPE_VENDOR 0x40
-
-#define USBH_REQTYPE_DEVICE 0x00
-#define USBH_REQTYPE_INTERFACE 0x01
-#define USBH_REQTYPE_ENDPOINT 0x02
-#define USBH_REQTYPE_OTHER 0x03
-
-#endif
-
-
-#endif /* USBH_DEFS_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/include/usbh/desciter.h b/ChibiOS_16.1.5/community/os/hal/include/usbh/desciter.h deleted file mode 100644 index 52b0c98..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/usbh/desciter.h +++ /dev/null @@ -1,63 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
- Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-
-#ifndef USBH_DESCITER_H_
-#define USBH_DESCITER_H_
-
-#include "hal.h"
-
-#if HAL_USE_USBH
-
-#include "usbh/defs.h"
-
-
-/* DESCRIPTOR PARSING */
-#define _generic_iterator_fields \
- const uint8_t *curr; \
- uint16_t rem; \
- bool valid;
-
-typedef struct {
- _generic_iterator_fields
-} generic_iterator_t;
-
-typedef struct {
- _generic_iterator_fields
- const usbh_ia_descriptor_t *iad;
-} if_iterator_t;
-
-void cfg_iter_init(generic_iterator_t *icfg, const uint8_t *buff, uint16_t rem);
-void if_iter_init(if_iterator_t *iif, const generic_iterator_t *icfg);
-void ep_iter_init(generic_iterator_t *iep, const if_iterator_t *iif);
-void cs_iter_init(generic_iterator_t *ics, const generic_iterator_t *iter);
-void if_iter_next(if_iterator_t *iif);
-void ep_iter_next(generic_iterator_t *iep);
-void cs_iter_next(generic_iterator_t *ics);
-static inline const usbh_config_descriptor_t *cfg_get(generic_iterator_t *icfg) {
- return (const usbh_config_descriptor_t *)icfg->curr;
-}
-static inline const usbh_interface_descriptor_t *if_get(if_iterator_t *iif) {
- return (const usbh_interface_descriptor_t *)iif->curr;
-}
-static inline const usbh_endpoint_descriptor_t *ep_get(generic_iterator_t *iep) {
- return (const usbh_endpoint_descriptor_t *)iep->curr;
-}
-
-#endif
-
-#endif /* USBH_DESCITER_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/include/usbh/dev/ftdi.h b/ChibiOS_16.1.5/community/os/hal/include/usbh/dev/ftdi.h deleted file mode 100644 index ad6b4cd..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/usbh/dev/ftdi.h +++ /dev/null @@ -1,154 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
- Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef USBH_FTDI_H_
-#define USBH_FTDI_H_
-
-#include "hal_usbh.h"
-
-#if HAL_USE_USBH && HAL_USBH_USE_FTDI
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-#define USBHFTDI_FRAMING_DATABITS_7 (0x7 << 0)
-#define USBHFTDI_FRAMING_DATABITS_8 (0x8 << 0)
-#define USBHFTDI_FRAMING_PARITY_NONE (0x0 << 8)
-#define USBHFTDI_FRAMING_PARITY_NONE (0x0 << 8)
-#define USBHFTDI_FRAMING_PARITY_ODD (0x1 << 8)
-#define USBHFTDI_FRAMING_PARITY_EVEN (0x2 << 8)
-#define USBHFTDI_FRAMING_PARITY_MARK (0x3 << 8)
-#define USBHFTDI_FRAMING_PARITY_SPACE (0x4 << 8)
-#define USBHFTDI_FRAMING_STOP_BITS_1 (0x0 << 11)
-#define USBHFTDI_FRAMING_STOP_BITS_15 (0x1 << 11)
-#define USBHFTDI_FRAMING_STOP_BITS_2 (0x2 << 11)
-
-#define USBHFTDI_HANDSHAKE_NONE (0x0)
-#define USBHFTDI_HANDSHAKE_RTS_CTS (0x1)
-#define USBHFTDI_HANDSHAKE_DTR_DSR (0x2)
-#define USBHFTDI_HANDSHAKE_XON_XOFF (0x4)
-
-
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-typedef struct {
- uint32_t speed;
- uint16_t framing;
- uint8_t handshake;
- uint8_t xon_character;
- uint8_t xoff_character;
-} USBHFTDIPortConfig;
-
-typedef enum {
- USBHFTDI_TYPE_A,
- USBHFTDI_TYPE_B,
- USBHFTDI_TYPE_H,
-} usbhftdi_type_t;
-
-typedef enum {
- USBHFTDIP_STATE_UNINIT = 0,
- USBHFTDIP_STATE_STOP = 1,
- USBHFTDIP_STATE_ACTIVE = 2,
- USBHFTDIP_STATE_READY = 3
-} usbhftdip_state_t;
-
-
-#define _ftdi_port_driver_methods \
- _base_asynchronous_channel_methods
-
-struct FTDIPortDriverVMT {
- _ftdi_port_driver_methods
-};
-
-typedef struct USBHFTDIPortDriver USBHFTDIPortDriver;
-typedef struct USBHFTDIDriver USBHFTDIDriver;
-
-struct USBHFTDIPortDriver {
- /* inherited from abstract asyncrhonous channel driver */
- const struct FTDIPortDriverVMT *vmt;
- _base_asynchronous_channel_data
-
- USBHFTDIDriver *ftdip;
-
- usbhftdip_state_t state;
-
- usbh_ep_t epin;
- usbh_urb_t iq_urb;
- threads_queue_t iq_waiting;
- uint32_t iq_counter;
- USBH_DEFINE_BUFFER(uint8_t, iq_buff[64]);
- uint8_t *iq_ptr;
-
-
- usbh_ep_t epout;
- usbh_urb_t oq_urb;
- threads_queue_t oq_waiting;
- uint32_t oq_counter;
- USBH_DEFINE_BUFFER(uint8_t, oq_buff[64]);
- uint8_t *oq_ptr;
-
- virtual_timer_t vt;
- uint8_t ifnum;
-
- USBHFTDIPortDriver *next;
-};
-
-typedef struct USBHFTDIDriver {
- /* inherited from abstract class driver */
- _usbh_base_classdriver_data
-
- usbhftdi_type_t type;
- USBHFTDIPortDriver *ports;
-
- mutex_t mtx;
-} USBHFTDIDriver;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-extern USBHFTDIDriver USBHFTDID[HAL_USBHFTDI_MAX_INSTANCES];
-extern USBHFTDIPortDriver FTDIPD[HAL_USBHFTDI_MAX_PORTS];
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- /* FTDI device driver */
- void usbhftdiObjectInit(USBHFTDIDriver *ftdip);
-
- /* FTDI port driver */
- void usbhftdipObjectInit(USBHFTDIPortDriver *ftdipp);
- void usbhftdipStart(USBHFTDIPortDriver *ftdipp, const USBHFTDIPortConfig *config);
- void usbhftdipStop(USBHFTDIPortDriver *ftdipp);
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif
-
-#endif /* USBH_FTDI_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/include/usbh/dev/hub.h b/ChibiOS_16.1.5/community/os/hal/include/usbh/dev/hub.h deleted file mode 100644 index 07e88e6..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/usbh/dev/hub.h +++ /dev/null @@ -1,138 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
- Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef USBH_HUB_H_
-#define USBH_HUB_H_
-
-#include "hal_usbh.h"
-
-#if HAL_USE_USBH
-#if HAL_USBH_USE_HUB
-
-typedef struct USBHHubDriver {
- /* inherited from abstract class driver */
- _usbh_base_classdriver_data
-
- struct list_head node;
-
- usbh_ep_t epint;
- usbh_urb_t urb;
-
- USBH_DEFINE_BUFFER(uint8_t, scbuff[4]);
- volatile uint32_t statuschange;
- uint16_t status;
- uint16_t c_status;
-
- usbh_port_t *ports;
-
- USBH_DEFINE_BUFFER(usbh_hub_descriptor_t, hubDesc);
-
- /* Low level part */
- _usbh_hub_ll_data
-
-} USBHHubDriver;
-
-extern USBHHubDriver USBHHUBD[HAL_USBHHUB_MAX_INSTANCES];
-
-
-usbh_urbstatus_t usbhhubControlRequest(USBHDriver *host, USBHHubDriver *hub,
- uint8_t bmRequestType,
- uint8_t bRequest,
- uint16_t wValue,
- uint16_t wIndex,
- uint16_t wLength,
- uint8_t *buf);
-
-
-static inline usbh_urbstatus_t usbhhubClearFeaturePort(usbh_port_t *port, uint8_t feature) {
- return usbhhubControlRequest(port->device.host, port->hub,
- USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER,
- USBH_REQ_CLEAR_FEATURE,
- feature,
- port->number,
- 0,
- 0);
-}
-
-static inline usbh_urbstatus_t usbhhubClearFeatureHub(USBHDriver *host, USBHHubDriver *hub, uint8_t feature) {
- return usbhhubControlRequest(host, hub,
- USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE,
- USBH_REQ_CLEAR_FEATURE,
- feature,
- 0,
- 0,
- 0);
-}
-
-static inline usbh_urbstatus_t usbhhubSetFeaturePort(usbh_port_t *port, uint8_t feature) {
- return usbhhubControlRequest(port->device.host, port->hub,
- USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER,
- USBH_REQ_SET_FEATURE,
- feature,
- port->number,
- 0,
- 0);
-}
-
-void usbhhubObjectInit(USBHHubDriver *hubdp);
-#else
-
-static inline usbh_urbstatus_t usbhhubControlRequest(USBHDriver *host,
- uint8_t bmRequestType,
- uint8_t bRequest,
- uint16_t wValue,
- uint16_t wIndex,
- uint16_t wLength,
- uint8_t *buf) {
- return usbh_lld_root_hub_request(host, bmRequestType, bRequest, wValue, wIndex, wLength, buf);
-}
-
-static inline usbh_urbstatus_t usbhhubClearFeaturePort(usbh_port_t *port, uint8_t feature) {
- return usbhhubControlRequest(port->device.host,
- USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER,
- USBH_REQ_CLEAR_FEATURE,
- feature,
- port->number,
- 0,
- 0);
-}
-
-static inline usbh_urbstatus_t usbhhubClearFeatureHub(USBHDriver *host, uint8_t feature) {
- return usbhhubControlRequest(host,
- USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE,
- USBH_REQ_CLEAR_FEATURE,
- feature,
- 0,
- 0,
- 0);
-}
-
-static inline usbh_urbstatus_t usbhhubSetFeaturePort(usbh_port_t *port, uint8_t feature) {
- return usbhhubControlRequest(port->device.host,
- USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER,
- USBH_REQ_SET_FEATURE,
- feature,
- port->number,
- 0,
- 0);
-}
-
-#endif
-
-#endif
-
-#endif /* USBH_HUB_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/include/usbh/dev/msd.h b/ChibiOS_16.1.5/community/os/hal/include/usbh/dev/msd.h deleted file mode 100644 index d164618..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/usbh/dev/msd.h +++ /dev/null @@ -1,125 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
- Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef USBH_MSD_H_
-#define USBH_MSD_H_
-
-#include "hal_usbh.h"
-
-#if HAL_USE_USBH && HAL_USBH_USE_MSD
-
-/* TODO:
- *
- * - Implement of conditional compilation of multiple-luns per instance.
- * - Implement error checking and recovery when commands fail.
- *
- */
-
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-#define _usbhmsd_driver_methods \
- _base_block_device_methods
-
-struct USBHMassStorageDriverVMT {
- _usbhmsd_driver_methods
-};
-
-typedef struct USBHMassStorageLUNDriver USBHMassStorageLUNDriver;
-typedef struct USBHMassStorageDriver USBHMassStorageDriver;
-
-struct USBHMassStorageLUNDriver {
- /* inherited from abstract block driver */
- const struct USBHMassStorageDriverVMT *vmt;
- _base_block_device_data
-
- BlockDeviceInfo info;
- USBHMassStorageDriver *msdp;
-
- USBHMassStorageLUNDriver *next;
-};
-
-typedef struct USBHMassStorageDriver {
- /* inherited from abstract class driver */
- _usbh_base_classdriver_data
-
- /* for LUN request serialization, can be removed
- * if the driver is configured to support only one LUN
- * per USBHMassStorageDriver instance */
- mutex_t mtx;
-
- usbh_ep_t epin;
- usbh_ep_t epout;
- uint8_t ifnum;
- uint8_t max_lun;
- uint32_t tag;
-
- USBHMassStorageLUNDriver *luns;
-} USBHMassStorageDriver;
-
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-extern USBHMassStorageLUNDriver MSBLKD[HAL_USBHMSD_MAX_LUNS];
-extern USBHMassStorageDriver USBHMSD[HAL_USBHMSD_MAX_INSTANCES];
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- /* Mass Storage Driver */
- void usbhmsdObjectInit(USBHMassStorageDriver *msdp);
-
- /* Mass Storage LUN Driver (block driver) */
- void usbhmsdLUNObjectInit(USBHMassStorageLUNDriver *lunp);
- void usbhmsdLUNStart(USBHMassStorageLUNDriver *lunp);
- void usbhmsdLUNStop(USBHMassStorageLUNDriver *lunp);
- bool usbhmsdLUNConnect(USBHMassStorageLUNDriver *lunp);
- bool usbhmsdLUNDisconnect(USBHMassStorageLUNDriver *lunp);
- bool usbhmsdLUNRead(USBHMassStorageLUNDriver *lunp, uint32_t startblk,
- uint8_t *buffer, uint32_t n);
- bool usbhmsdLUNWrite(USBHMassStorageLUNDriver *lunp, uint32_t startblk,
- const uint8_t *buffer, uint32_t n);
- bool usbhmsdLUNSync(USBHMassStorageLUNDriver *lunp);
- bool usbhmsdLUNGetInfo(USBHMassStorageLUNDriver *lunp, BlockDeviceInfo *bdip);
- bool usbhmsdLUNIsInserted(USBHMassStorageLUNDriver *lunp);
- bool usbhmsdLUNIsProtected(USBHMassStorageLUNDriver *lunp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif /* USBH_MSD_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/include/usbh/internal.h b/ChibiOS_16.1.5/community/os/hal/include/usbh/internal.h deleted file mode 100644 index baa477f..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/usbh/internal.h +++ /dev/null @@ -1,148 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
- Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail)
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef USBH_INTERNAL_H_
-#define USBH_INTERNAL_H_
-
-#include "hal_usbh.h"
-
-#if HAL_USE_USBH
-
-/*===========================================================================*/
-/* These declarations are not part of the public API. */
-/*===========================================================================*/
-
-#if HAL_USBH_USE_FTDI
-extern const usbh_classdriverinfo_t usbhftdiClassDriverInfo;
-#endif
-#if HAL_USBH_USE_MSD
-extern const usbh_classdriverinfo_t usbhmsdClassDriverInfo;
-#endif
-#if HAL_USBH_USE_UVC
-extern const usbh_classdriverinfo_t usbhuvcClassDriverInfo;
-#endif
-#if HAL_USBH_USE_HUB
-extern const usbh_classdriverinfo_t usbhhubClassDriverInfo;
-void _usbhub_port_object_init(usbh_port_t *port, USBHDriver *usbh,
- USBHHubDriver *hub, uint8_t number);
-#else
-void _usbhub_port_object_init(usbh_port_t *port, USBHDriver *usbh, uint8_t number);
-#endif
-
-void _usbh_port_disconnected(usbh_port_t *port);
-void _usbh_urb_completeI(usbh_urb_t *urb, usbh_urbstatus_t status);
-bool _usbh_urb_abortI(usbh_urb_t *urb, usbh_urbstatus_t status);
-void _usbh_urb_abort_and_waitS(usbh_urb_t *urb, usbh_urbstatus_t status);
-
-
-#define USBH_CLASSIN(type, req, value, index) \
- (USBH_REQTYPE_IN | type | USBH_REQTYPE_CLASS), \
- req, \
- value, \
- index
-
-#define USBH_CLASSOUT(type, req, value, index) \
- (USBH_REQTYPE_OUT | type | USBH_REQTYPE_CLASS), \
- req, \
- value, \
- index
-
-#define USBH_STANDARDIN(type, req, value, index) \
- (USBH_REQTYPE_IN | type | USBH_REQTYPE_STANDARD), \
- req, \
- value, \
- index
-
-#define USBH_STANDARDOUT(type, req, value, index) \
- (USBH_REQTYPE_OUT | type | USBH_REQTYPE_STANDARD), \
- req, \
- value, \
- index
-
-
-#define USBH_PID_DATA0 0
-#define USBH_PID_DATA2 1
-#define USBH_PID_DATA1 2
-#define USBH_PID_MDATA 3
-#define USBH_PID_SETUP 3
-
-
-/* GetBusState and SetHubDescriptor are optional, omitted */
-#define ClearHubFeature (((USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE) << 8) \
- | USBH_REQ_CLEAR_FEATURE)
-#define SetHubFeature (((USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE) << 8) \
- | USBH_REQ_SET_FEATURE)
-#define ClearPortFeature (((USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER) << 8) \
- | USBH_REQ_CLEAR_FEATURE)
-#define SetPortFeature (((USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER) << 8) \
- | USBH_REQ_SET_FEATURE)
-#define GetHubDescriptor (((USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE) << 8) \
- | USBH_REQ_GET_DESCRIPTOR)
-#define GetHubStatus (((USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE) << 8) \
- | USBH_REQ_GET_STATUS)
-#define GetPortStatus (((USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER) << 8) \
- | USBH_REQ_GET_STATUS)
-
-
-#define USBH_PORTSTATUS_CONNECTION 0x0001
-#define USBH_PORTSTATUS_ENABLE 0x0002
-#define USBH_PORTSTATUS_SUSPEND 0x0004
-#define USBH_PORTSTATUS_OVERCURRENT 0x0008
-#define USBH_PORTSTATUS_RESET 0x0010
-/* bits 5 to 7 are reserved */
-#define USBH_PORTSTATUS_POWER 0x0100
-#define USBH_PORTSTATUS_LOW_SPEED 0x0200
-#define USBH_PORTSTATUS_HIGH_SPEED 0x0400
-#define USBH_PORTSTATUS_TEST 0x0800
-#define USBH_PORTSTATUS_INDICATOR 0x1000
-/* bits 13 to 15 are reserved */
-
-#define USBH_PORTSTATUS_C_CONNECTION 0x0001
-#define USBH_PORTSTATUS_C_ENABLE 0x0002
-#define USBH_PORTSTATUS_C_SUSPEND 0x0004
-#define USBH_PORTSTATUS_C_OVERCURRENT 0x0008
-#define USBH_PORTSTATUS_C_RESET 0x0010
-
-#define USBH_HUBSTATUS_C_HUB_LOCAL_POWER 0x0001
-#define USBH_HUBSTATUS_C_HUB_OVER_CURRENT 0x0002
-
-/*
- * Port feature numbers
- * See USB 2.0 spec Table 11-17
- */
-#define USBH_HUB_FEAT_C_HUB_LOCAL_POWER 0
-#define USBH_HUB_FEAT_C_HUB_OVER_CURRENT 1
-#define USBH_PORT_FEAT_CONNECTION 0
-#define USBH_PORT_FEAT_ENABLE 1
-#define USBH_PORT_FEAT_SUSPEND 2
-#define USBH_PORT_FEAT_OVERCURRENT 3
-#define USBH_PORT_FEAT_RESET 4
-#define USBH_PORT_FEAT_POWER 8
-#define USBH_PORT_FEAT_LOWSPEED 9
-#define USBH_PORT_FEAT_C_CONNECTION 16
-#define USBH_PORT_FEAT_C_ENABLE 17
-#define USBH_PORT_FEAT_C_SUSPEND 18
-#define USBH_PORT_FEAT_C_OVERCURRENT 19
-#define USBH_PORT_FEAT_C_RESET 20
-#define USBH_PORT_FEAT_TEST 21
-#define USBH_PORT_FEAT_INDICATOR 22
-
-#define sizeof_array(x) (sizeof(x)/sizeof(*(x)))
-
-#endif
-
-#endif /* USBH_INTERNAL_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/include/usbh/list.h b/ChibiOS_16.1.5/community/os/hal/include/usbh/list.h deleted file mode 100644 index 4eceacd..0000000 --- a/ChibiOS_16.1.5/community/os/hal/include/usbh/list.h +++ /dev/null @@ -1,598 +0,0 @@ -#ifndef USBH_LIST_H_
-#define USBH_LIST_H_
-
-/* TODO: re-write this file; stolen from linux */
-
-#ifndef offsetof
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-#endif
-
-#define container_of(ptr, type, member) ((type *)(void *)((char *)(ptr) - offsetof(type, member)))
-#ifndef container_of
-#define container_of(ptr, type, member) ({ \
- const typeof(((type *)0)->member) * __mptr = (ptr); \
- (type *)((char *)__mptr - offsetof(type, member)); })
-#endif
-
-/*
- * Simple doubly linked list implementation.
- *
- * Some of the internal functions ("__xxx") are useful when
- * manipulating whole lists rather than single entries, as
- * sometimes we already know the next/prev entries and we can
- * generate better code by using them directly rather than
- * using the generic single-entry routines.
- */
-struct list_head {
- struct list_head *next, *prev;
-};
-
-#define LIST_HEAD_INIT(name) { &(name), &(name) }
-
-#define LIST_HEAD(name) \
- struct list_head name = LIST_HEAD_INIT(name)
-
-static inline void INIT_LIST_HEAD(struct list_head *list)
-{
- list->next = list;
- list->prev = list;
-}
-
-/*
- * Insert a new entry between two known consecutive entries.
- *
- * This is only for internal list manipulation where we know
- * the prev/next entries already!
- */
-#ifndef CONFIG_DEBUG_LIST
-static inline void __list_add(struct list_head *new,
- struct list_head *prev,
- struct list_head *next)
-{
- next->prev = new;
- new->next = next;
- new->prev = prev;
- prev->next = new;
-}
-#else
-extern void __list_add(struct list_head *new,
- struct list_head *prev,
- struct list_head *next);
-#endif
-
-/**
- * list_add - add a new entry
- * @new: new entry to be added
- * @head: list head to add it after
- *
- * Insert a new entry after the specified head.
- * This is good for implementing stacks.
- */
-static inline void list_add(struct list_head *new, struct list_head *head)
-{
- __list_add(new, head, head->next);
-}
-
-
-/**
- * list_add_tail - add a new entry
- * @new: new entry to be added
- * @head: list head to add it before
- *
- * Insert a new entry before the specified head.
- * This is useful for implementing queues.
- */
-static inline void list_add_tail(struct list_head *new, struct list_head *head)
-{
- __list_add(new, head->prev, head);
-}
-
-/*
- * Delete a list entry by making the prev/next entries
- * point to each other.
- *
- * This is only for internal list manipulation where we know
- * the prev/next entries already!
- */
-static inline void __list_del(struct list_head * prev, struct list_head * next)
-{
- next->prev = prev;
- prev->next = next;
-}
-
-/**
- * list_del - deletes entry from list.
- * @entry: the element to delete from the list.
- * Note: list_empty() on entry does not return true after this, the entry is
- * in an undefined state.
- */
-#ifndef CONFIG_DEBUG_LIST
-static inline void __list_del_entry(struct list_head *entry)
-{
- __list_del(entry->prev, entry->next);
-}
-
-static inline void list_del(struct list_head *entry)
-{
- __list_del(entry->prev, entry->next);
- // entry->next = LIST_POISON1;
- // entry->prev = LIST_POISON2;
-}
-#else
-extern void __list_del_entry(struct list_head *entry);
-extern void list_del(struct list_head *entry);
-#endif
-
-/**
- * list_replace - replace old entry by new one
- * @old : the element to be replaced
- * @new : the new element to insert
- *
- * If @old was empty, it will be overwritten.
- */
-static inline void list_replace(struct list_head *old,
- struct list_head *new)
-{
- new->next = old->next;
- new->next->prev = new;
- new->prev = old->prev;
- new->prev->next = new;
-}
-
-static inline void list_replace_init(struct list_head *old,
- struct list_head *new)
-{
- list_replace(old, new);
- INIT_LIST_HEAD(old);
-}
-
-/**
- * list_del_init - deletes entry from list and reinitialize it.
- * @entry: the element to delete from the list.
- */
-static inline void list_del_init(struct list_head *entry)
-{
- __list_del_entry(entry);
- INIT_LIST_HEAD(entry);
-}
-
-/**
- * list_move - delete from one list and add as another's head
- * @list: the entry to move
- * @head: the head that will precede our entry
- */
-static inline void list_move(struct list_head *list, struct list_head *head)
-{
- __list_del_entry(list);
- list_add(list, head);
-}
-
-/**
- * list_move_tail - delete from one list and add as another's tail
- * @list: the entry to move
- * @head: the head that will follow our entry
- */
-static inline void list_move_tail(struct list_head *list,
- struct list_head *head)
-{
- __list_del_entry(list);
- list_add_tail(list, head);
-}
-
-/**
- * list_is_last - tests whether @list is the last entry in list @head
- * @list: the entry to test
- * @head: the head of the list
- */
-static inline int list_is_last(const struct list_head *list,
- const struct list_head *head)
-{
- return list->next == head;
-}
-
-/**
- * list_empty - tests whether a list is empty
- * @head: the list to test.
- */
-static inline int list_empty(const struct list_head *head)
-{
- return head->next == head;
-}
-
-/**
- * list_empty_careful - tests whether a list is empty and not being modified
- * @head: the list to test
- *
- * Description:
- * tests whether a list is empty _and_ checks that no other CPU might be
- * in the process of modifying either member (next or prev)
- *
- * NOTE: using list_empty_careful() without synchronization
- * can only be safe if the only activity that can happen
- * to the list entry is list_del_init(). Eg. it cannot be used
- * if another CPU could re-list_add() it.
- */
-static inline int list_empty_careful(const struct list_head *head)
-{
- struct list_head *next = head->next;
- return (next == head) && (next == head->prev);
-}
-
-/**
- * list_rotate_left - rotate the list to the left
- * @head: the head of the list
- */
-static inline void list_rotate_left(struct list_head *head)
-{
- struct list_head *first;
-
- if (!list_empty(head)) {
- first = head->next;
- list_move_tail(first, head);
- }
-}
-
-/**
- * list_is_singular - tests whether a list has just one entry.
- * @head: the list to test.
- */
-static inline int list_is_singular(const struct list_head *head)
-{
- return !list_empty(head) && (head->next == head->prev);
-}
-
-static inline void __list_cut_position(struct list_head *list,
- struct list_head *head, struct list_head *entry)
-{
- struct list_head *new_first = entry->next;
- list->next = head->next;
- list->next->prev = list;
- list->prev = entry;
- entry->next = list;
- head->next = new_first;
- new_first->prev = head;
-}
-
-/**
- * list_cut_position - cut a list into two
- * @list: a new list to add all removed entries
- * @head: a list with entries
- * @entry: an entry within head, could be the head itself
- * and if so we won't cut the list
- *
- * This helper moves the initial part of @head, up to and
- * including @entry, from @head to @list. You should
- * pass on @entry an element you know is on @head. @list
- * should be an empty list or a list you do not care about
- * losing its data.
- *
- */
-static inline void list_cut_position(struct list_head *list,
- struct list_head *head, struct list_head *entry)
-{
- if (list_empty(head))
- return;
- if (list_is_singular(head) &&
- (head->next != entry && head != entry))
- return;
- if (entry == head)
- INIT_LIST_HEAD(list);
- else
- __list_cut_position(list, head, entry);
-}
-
-static inline void __list_splice(const struct list_head *list,
- struct list_head *prev,
- struct list_head *next)
-{
- struct list_head *first = list->next;
- struct list_head *last = list->prev;
-
- first->prev = prev;
- prev->next = first;
-
- last->next = next;
- next->prev = last;
-}
-
-/**
- * list_splice - join two lists, this is designed for stacks
- * @list: the new list to add.
- * @head: the place to add it in the first list.
- */
-static inline void list_splice(const struct list_head *list,
- struct list_head *head)
-{
- if (!list_empty(list))
- __list_splice(list, head, head->next);
-}
-
-/**
- * list_splice_tail - join two lists, each list being a queue
- * @list: the new list to add.
- * @head: the place to add it in the first list.
- */
-static inline void list_splice_tail(struct list_head *list,
- struct list_head *head)
-{
- if (!list_empty(list))
- __list_splice(list, head->prev, head);
-}
-
-/**
- * list_splice_init - join two lists and reinitialise the emptied list.
- * @list: the new list to add.
- * @head: the place to add it in the first list.
- *
- * The list at @list is reinitialised
- */
-static inline void list_splice_init(struct list_head *list,
- struct list_head *head)
-{
- if (!list_empty(list)) {
- __list_splice(list, head, head->next);
- INIT_LIST_HEAD(list);
- }
-}
-
-/**
- * list_splice_tail_init - join two lists and reinitialise the emptied list
- * @list: the new list to add.
- * @head: the place to add it in the first list.
- *
- * Each of the lists is a queue.
- * The list at @list is reinitialised
- */
-static inline void list_splice_tail_init(struct list_head *list,
- struct list_head *head)
-{
- if (!list_empty(list)) {
- __list_splice(list, head->prev, head);
- INIT_LIST_HEAD(list);
- }
-}
-
-/**
- * list_entry - get the struct for this entry
- * @ptr: the &struct list_head pointer.
- * @type: the type of the struct this is embedded in.
- * @member: the name of the list_head within the struct.
- */
-#define list_entry(ptr, type, member) \
- container_of(ptr, type, member)
-
-/**
- * list_first_entry - get the first element from a list
- * @ptr: the list head to take the element from.
- * @type: the type of the struct this is embedded in.
- * @member: the name of the list_head within the struct.
- *
- * Note, that list is expected to be not empty.
- */
-#define list_first_entry(ptr, type, member) \
- list_entry((ptr)->next, type, member)
-
-/**
- * list_last_entry - get the last element from a list
- * @ptr: the list head to take the element from.
- * @type: the type of the struct this is embedded in.
- * @member: the name of the list_head within the struct.
- *
- * Note, that list is expected to be not empty.
- */
-#define list_last_entry(ptr, type, member) \
- list_entry((ptr)->prev, type, member)
-
-/**
- * list_first_entry_or_null - get the first element from a list
- * @ptr: the list head to take the element from.
- * @type: the type of the struct this is embedded in.
- * @member: the name of the list_head within the struct.
- *
- * Note that if the list is empty, it returns NULL.
- */
-#define list_first_entry_or_null(ptr, type, member) \
- (!list_empty(ptr) ? list_first_entry(ptr, type, member) : NULL)
-
-/**
- * list_next_entry - get the next element in list
- * @pos: the type * to cursor
- * @member: the name of the list_head within the struct.
- */
-#define list_next_entry(pos, type, member) \
- list_entry((pos)->member.next, type, member)
-
-/**
- * list_prev_entry - get the prev element in list
- * @pos: the type * to cursor
- * @member: the name of the list_head within the struct.
- */
-#define list_prev_entry(pos, type, member) \
- list_entry((pos)->member.prev, type, member)
-
-/**
- * list_for_each - iterate over a list
- * @pos: the &struct list_head to use as a loop cursor.
- * @head: the head for your list.
- */
-#define list_for_each(pos, head) \
- for (pos = (head)->next; pos != (head); pos = pos->next)
-
-/**
- * list_for_each_prev - iterate over a list backwards
- * @pos: the &struct list_head to use as a loop cursor.
- * @head: the head for your list.
- */
-#define list_for_each_prev(pos, head) \
- for (pos = (head)->prev; pos != (head); pos = pos->prev)
-
-/**
- * list_for_each_safe - iterate over a list safe against removal of list entry
- * @pos: the &struct list_head to use as a loop cursor.
- * @n: another &struct list_head to use as temporary storage
- * @head: the head for your list.
- */
-#define list_for_each_safe(pos, n, head) \
- for (pos = (head)->next, n = pos->next; pos != (head); \
- pos = n, n = pos->next)
-
-/**
- * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry
- * @pos: the &struct list_head to use as a loop cursor.
- * @n: another &struct list_head to use as temporary storage
- * @head: the head for your list.
- */
-#define list_for_each_prev_safe(pos, n, head) \
- for (pos = (head)->prev, n = pos->prev; \
- pos != (head); \
- pos = n, n = pos->prev)
-
-/**
- * list_for_each_entry - iterate over list of given type
- * @pos: the type * to use as a loop cursor.
- * @head: the head for your list.
- * @member: the name of the list_head within the struct.
- */
-#define list_for_each_entry(pos, type, head, member) \
- for (pos = list_first_entry(head, type, member); \
- &pos->member != (head); \
- pos = list_next_entry(pos, type, member))
-
-/**
- * list_for_each_entry_reverse - iterate backwards over list of given type.
- * @pos: the type * to use as a loop cursor.
- * @head: the head for your list.
- * @member: the name of the list_head within the struct.
- */
-#define list_for_each_entry_reverse(pos, type, head, member) \
- for (pos = list_last_entry(head, type, member); \
- &pos->member != (head); \
- pos = list_prev_entry(pos, type, member))
-
-/**
- * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue()
- * @pos: the type * to use as a start point
- * @head: the head of the list
- * @member: the name of the list_head within the struct.
- *
- * Prepares a pos entry for use as a start point in list_for_each_entry_continue().
- */
-#define list_prepare_entry(pos, type, head, member) \
- ((pos) ? : list_entry(head, type, member))
-
-/**
- * list_for_each_entry_continue - continue iteration over list of given type
- * @pos: the type * to use as a loop cursor.
- * @head: the head for your list.
- * @member: the name of the list_head within the struct.
- *
- * Continue to iterate over list of given type, continuing after
- * the current position.
- */
-#define list_for_each_entry_continue(pos, type, head, member) \
- for (pos = list_next_entry(pos, type, member); \
- &pos->member != (head); \
- pos = list_next_entry(pos, type, member))
-
-/**
- * list_for_each_entry_continue_reverse - iterate backwards from the given point
- * @pos: the type * to use as a loop cursor.
- * @head: the head for your list.
- * @member: the name of the list_head within the struct.
- *
- * Start to iterate over list of given type backwards, continuing after
- * the current position.
- */
-#define list_for_each_entry_continue_reverse(pos, type, head, member) \
- for (pos = list_prev_entry(pos, type, member); \
- &pos->member != (head); \
- pos = list_prev_entry(pos, type, member))
-
-/**
- * list_for_each_entry_from - iterate over list of given type from the current point
- * @pos: the type * to use as a loop cursor.
- * @head: the head for your list.
- * @member: the name of the list_head within the struct.
- *
- * Iterate over list of given type, continuing from current position.
- */
-#define list_for_each_entry_from(pos, type, head, member) \
- for (; &pos->member != (head); \
- pos = list_next_entry(pos, type, member))
-
-/**
- * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry
- * @pos: the type * to use as a loop cursor.
- * @n: another type * to use as temporary storage
- * @head: the head for your list.
- * @member: the name of the list_head within the struct.
- */
-#define list_for_each_entry_safe(pos, type, n, head, member) \
- for (pos = list_first_entry(head, type, member), \
- n = list_next_entry(pos, type, member); \
- &pos->member != (head); \
- pos = n, n = list_next_entry(n, type, member))
-
-/**
- * list_for_each_entry_safe_continue - continue list iteration safe against removal
- * @pos: the type * to use as a loop cursor.
- * @n: another type * to use as temporary storage
- * @head: the head for your list.
- * @member: the name of the list_head within the struct.
- *
- * Iterate over list of given type, continuing after current point,
- * safe against removal of list entry.
- */
-#define list_for_each_entry_safe_continue(pos, type, n, head, member) \
- for (pos = list_next_entry(pos, type, member), \
- n = list_next_entry(pos, type, member); \
- &pos->member != (head); \
- pos = n, n = list_next_entry(n, type, member))
-
-/**
- * list_for_each_entry_safe_from - iterate over list from current point safe against removal
- * @pos: the type * to use as a loop cursor.
- * @n: another type * to use as temporary storage
- * @head: the head for your list.
- * @member: the name of the list_head within the struct.
- *
- * Iterate over list of given type from current point, safe against
- * removal of list entry.
- */
-#define list_for_each_entry_safe_from(pos, type, n, head, member) \
- for (n = list_next_entry(pos, type, member); \
- &pos->member != (head); \
- pos = n, n = list_next_entry(n, type, member))
-
-/**
- * list_for_each_entry_safe_reverse - iterate backwards over list safe against removal
- * @pos: the type * to use as a loop cursor.
- * @n: another type * to use as temporary storage
- * @head: the head for your list.
- * @member: the name of the list_head within the struct.
- *
- * Iterate backwards over list of given type, safe against removal
- * of list entry.
- */
-#define list_for_each_entry_safe_reverse(pos, type, n, head, member) \
- for (pos = list_last_entry(head, type, member), \
- n = list_prev_entry(pos, type, member); \
- &pos->member != (head); \
- pos = n, n = list_prev_entry(n, type, member))
-
-/**
- * list_safe_reset_next - reset a stale list_for_each_entry_safe loop
- * @pos: the loop cursor used in the list_for_each_entry_safe loop
- * @n: temporary storage used in list_for_each_entry_safe
- * @member: the name of the list_head within the struct.
- *
- * list_safe_reset_next is not safe to use in general if the list may be
- * modified concurrently (eg. the lock is dropped in the loop body). An
- * exception to this is if the cursor element (pos) is pinned in the list,
- * and list_safe_reset_next is called after re-taking the lock and before
- * completing the current iteration of the loop body.
- */
-#define list_safe_reset_next(pos, type, n, member) \
- n = list_next_entry(pos, type, member)
-
-#endif /* USBH_LIST_H_ */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_lld.c deleted file mode 100644 index e6eeed8..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_lld.c +++ /dev/null @@ -1,234 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file templates/hal_lld.c
- * @brief HAL Driver subsystem low level driver source template.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-#ifdef __CC_ARM
-__attribute__ ((section(".ARM.__at_0x400")))
-#else
-__attribute__ ((used,section(".cfmconfig")))
-#endif
-const uint8_t _cfm[0x10] = {
- 0xFF, /* NV_BACKKEY3: KEY=0xFF */
- 0xFF, /* NV_BACKKEY2: KEY=0xFF */
- 0xFF, /* NV_BACKKEY1: KEY=0xFF */
- 0xFF, /* NV_BACKKEY0: KEY=0xFF */
- 0xFF, /* NV_BACKKEY7: KEY=0xFF */
- 0xFF, /* NV_BACKKEY6: KEY=0xFF */
- 0xFF, /* NV_BACKKEY5: KEY=0xFF */
- 0xFF, /* NV_BACKKEY4: KEY=0xFF */
- 0xFF, /* NV_FPROT3: PROT=0xFF */
- 0xFF, /* NV_FPROT2: PROT=0xFF */
- 0xFF, /* NV_FPROT1: PROT=0xFF */
- 0xFF, /* NV_FPROT0: PROT=0xFF */
- 0x7E, /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
- 0xFF, /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
- NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
- 0xFF,
- 0xFF
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level HAL driver initialization.
- * @todo Use a macro to define the system clock frequency.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-}
-
-/**
- * @brief K20x clock initialization.
- * @note All the involved constants come from the file @p board.h.
- * @note This function is meant to be invoked early during the system
- * initialization, it is usually invoked from the file
- * @p board.c.
- * @todo This function needs to be more generic.
- *
- * @special
- */
-void k20x_clock_init(void) {
-#if !KINETIS_NO_INIT
-
- /* Disable the watchdog */
- WDOG->UNLOCK = 0xC520;
- WDOG->UNLOCK = 0xD928;
- WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;
-
- SIM->SCGC5 |= SIM_SCGC5_PORTA |
- SIM_SCGC5_PORTB |
- SIM_SCGC5_PORTC |
- SIM_SCGC5_PORTD |
- SIM_SCGC5_PORTE;
-
-#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
- /* This is the default mode at reset. */
-
- /* Configure FEI mode */
- MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
- (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
-
- /* Set clock dividers */
- SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
- SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
- SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
- SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); /* not strictly necessary since usb_lld will set this */
-
-#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
-
- uint32_t ratio, frdiv;
- uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
- uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
- uint8_t i;
-
- /* EXTAL0 and XTAL0 */
- PORTA->PCR[18] = 0;
- PORTA->PCR[19] = 0;
-
- /*
- * Start in FEI mode
- */
-
- /* Internal capacitors for crystal */
-#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
- OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
-#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
- /* Disable the internal capacitors */
- OSC0->CR = 0;
-#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
-
- /* TODO: need to add more flexible calculation, specially regarding
- * divisors which may not be available depending on the XTAL
- * frequency, which would required other registers to be modified.
- */
- /* Enable OSC, low power mode */
- MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0;
- if (KINETIS_XTAL_FREQUENCY > 8000000UL)
- MCG->C2 |= MCG_C2_RANGE0(2);
- else
- MCG->C2 |= MCG_C2_RANGE0(1);
-
- frdiv = 7;
- ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
- for (i = 0; i < ratio_quantity; ++i) {
- if (ratio == ratios[i]) {
- frdiv = i;
- break;
- }
- }
-
- /* Switch to crystal as clock source, FLL input of 31.25 KHz */
- MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(frdiv);
-
- /* Wait for crystal oscillator to begin */
- while (!(MCG->S & MCG_S_OSCINIT0));
-
- /* Wait for the FLL to use the oscillator */
- while (MCG->S & MCG_S_IREFST);
-
- /* Wait for the MCGOUTCLK to use the oscillator */
- while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
-
- /*
- * Now in FBE mode
- */
- #define KINETIS_PLLIN_FREQUENCY 2000000UL
- /*
- * Config PLL input for 2 MHz
- * TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz
- */
- MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
-
- /*
- * Config PLL output to match KINETIS_SYSCLK_FREQUENCY
- * TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match
- */
- for(i = 24; i < 56; i++)
- {
- if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY))
- {
- /* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
- MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
- break;
- }
- }
-
- if(i>=56) /* Config PLL for 96 MHz output as default setting */
- MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
-
- /* Wait for PLL to start using crystal as its input, and to lock */
- while ((MCG->S & (MCG_S_PLLST|MCG_S_LOCK0))!=(MCG_S_PLLST|MCG_S_LOCK0));
-
- /*
- * Now in PBE mode
- */
- /* Set the PLL dividers for the different clocks */
- SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
- SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
- SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
- SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
- SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL;
-
- /* Switch to PLL as clock source */
- MCG->C1 = MCG_C1_CLKS(0);
-
- /* Wait for PLL clock to be used */
- while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
-
- /*
- * Now in PEE mode
- */
-#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
-#error Unimplemented KINETIS_MCG_MODE
-#endif /* KINETIS_MCG_MODE == ... */
-
-#endif /* !KINETIS_NO_INIT */
-}
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_lld.h deleted file mode 100644 index b7f6b46..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_lld.h +++ /dev/null @@ -1,302 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file K20x/hal_lld.h
- * @brief Kinetis K20x HAL subsystem low level driver header.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef HAL_LLD_H_
-#define HAL_LLD_H_
-
-#include "kinetis_registry.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @name Platform identification
- * @{
- */
-#define PLATFORM_NAME "Kinetis"
-/** @} */
-
-/**
- * @name Internal clock sources
- * @{
- */
-#define KINETIS_IRCLK_F 4000000 /**< Fast internal reference clock, factory trimmed. */
-#define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
-/** @} */
-
-#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
-#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
-#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
-#define KINETIS_MCG_MODE_FBE 4 /**< FLL Bypassed External. */
-#define KINETIS_MCG_MODE_PEE 5 /**< PLL Engaged External. */
-#define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
-#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
-#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief Disables the MCG/system clock initialization in the HAL.
- */
-#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
-#define KINETIS_NO_INIT FALSE
-#endif
-
-/**
- * @brief MCG mode selection.
- */
-#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
-#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
-#endif
-
-/**
- * @brief MCU PLL clock frequency.
- */
-#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_PLLCLK_FREQUENCY 96000000UL
-#endif
-
-/**
- * @brief Clock divider for core/system clocks (OUTDIV1).
- * @note The allowed range is 1..16
- * @note The default value is calculated for a 48 MHz system clock
- * from a 96 MHz PLL output.
- */
-#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
- #if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
- #define KINETIS_CLKDIV1_OUTDIV1 (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
- #else
- #define KINETIS_CLKDIV1_OUTDIV1 2
- #endif
-#endif
-
-/**
- * @brief Clock divider for bus clock (OUTDIV2).
- * @note The allowed range is 1..16
- * @note The default value is calculated for a 48 MHz bus clock
- * from a 96 MHz PLL output.
- */
-#if !defined(KINETIS_CLKDIV1_OUTDIV2) || defined(__DOXYGEN__)
- #if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
- #define KINETIS_CLKDIV1_OUTDIV2 (KINETIS_PLLCLK_FREQUENCY/KINETIS_BUSCLK_FREQUENCY)
- #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
- #define KINETIS_CLKDIV1_OUTDIV2 KINETIS_CLKDIV1_OUTDIV1
- #else
- #define KINETIS_CLKDIV1_OUTDIV2 2
- #endif
-#endif
-
-/**
- * @brief Clock divider for flash clock (OUTDIV4).
- * @note The allowed range is 1..16
- * @note The default value is calculated for a 24 MHz flash clock
- * from a 96 MHz PLL output
- */
-#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
- #if defined(KINETIS_FLASHCLK_FREQUENCY) && KINETIS_FLASHCLK_FREQUENCY > 0
- #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLASHCLK_FREQUENCY)
- #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
- #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_CLKDIV1_OUTDIV1*2)
- #else
- #define KINETIS_CLKDIV1_OUTDIV4 4
- #endif
-#endif
-
-/**
- * @brief FLL DCO tuning enable for 32.768 kHz reference.
- * @note Set to 1 for fine-tuning DCO for maximum frequency with
- * a 32.768 kHz reference.
- * @note The default value is for a 32.768 kHz external crystal.
- */
-#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
-#define KINETIS_MCG_FLL_DMX32 1
-#endif
-
-/**
- * @brief FLL DCO range selection.
- * @note The allowed range is 0...3.
- * @note The default value is calculated for 48 MHz FLL output
- * from a 32.768 kHz external crystal.
- * (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
- *
- */
-#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
-#define KINETIS_MCG_FLL_DRS 2
-#endif
-
-/**
- * @brief MCU system/core clock frequency.
- */
-#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_SYSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
-#endif
-
-/**
- * @brief MCU bus clock frequency.
- */
-#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV2)
-#endif
-
-/**
- * @brief MCU flash clock frequency.
- */
-#if !defined(KINETIS_FLASHCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !defined(KINETIS_SYSCLK_FREQUENCY)
- #error KINETIS_SYSCLK_FREQUENCY must be defined
-#endif
-
-#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
- #error KINETIS_SYSCLK_FREQUENCY out of range
-#endif
-
-#if !defined(KINETIS_BUSCLK_FREQUENCY)
- #error KINETIS_BUSCLK_FREQUENCY must be defined
-#endif
-
-#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
- #error KINETIS_BUSCLK_FREQUENCY out of range
-#endif
-
-#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
- #error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
- KINETIS_SYSCLK_FREQUENCY
-#endif
-
-#if !defined(KINETIS_FLASHCLK_FREQUENCY)
- #error KINETIS_FLASHCLK_FREQUENCY must be defined
-#endif
-
-#if KINETIS_FLASHCLK_FREQUENCY <= 0 || KINETIS_FLASHCLK_FREQUENCY > KINETIS_FLASHCLK_MAX
- #error KINETIS_FLASHCLK_FREQUENCY out of range
-#endif
-
-#if KINETIS_FLASHCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
- #error KINETIS_FLASHCLK_FREQUENCY must be an integer divide of\
- KINETIS_SYSCLK_FREQUENCY
-#endif
-
-#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
- KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
- #error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
-#endif
-
-#if !(defined(KINETIS_CLKDIV1_OUTDIV2) && \
- KINETIS_CLKDIV1_OUTDIV2 >= 1 && KINETIS_CLKDIV1_OUTDIV2 <= 16)
-#error KINETIS_CLKDIV1_OUTDIV2 must be 1 through 16
-#endif
-
-#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
- KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
-#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
-#endif
-
-#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
-#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
-#endif
-
-#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
-#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This service is implemented by returning the content of the
- * DWT_CYCCNT register.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value() 0
-
-/**
- * @brief Realtime counter frequency.
- * @note The DWT_CYCCNT register is incremented directly by the system
- * clock so this function returns STM32_HCLK.
- *
- * @return The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency() 0
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#include "nvic.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void hal_lld_init(void);
- void k20x_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_pwm_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_pwm_lld.c deleted file mode 100644 index f5a8d96..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_pwm_lld.c +++ /dev/null @@ -1,390 +0,0 @@ -/*
- ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file K20x/pwm_lld.c
- * @brief KINETIS PWM subsystem low level driver source.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief PWMD1 driver identifier.
- * @note The driver PWMD1 allocates the timer FTM0 when enabled.
- */
-#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief PWMD2 driver identifier.
- * @note The driver PWMD2 allocates the timer FTM1 when enabled.
- */
-#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief PWMD3 driver identifier.
- * @note The driver PWMD3 allocates the timer FTM2 when enabled.
- */
-#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
- uint32_t sr;
-
- sr = pwmp->ftm->SC;
- pwmp->ftm->SC = sr&(~FTM_SC_TOF);
-
- if (((sr & FTM_SC_TOF) != 0) && /* Timer Overflow */
- ((sr & FTM_SC_TOIE) != 0) &&
- (pwmp->config->callback != NULL)) {
- pwmp->config->callback(pwmp);
- }
-
- uint8_t n=0;
- for(n=0;n<pwmp->channels;n++) {
- sr = pwmp->ftm->CHANNEL[n].CnSC;
- pwmp->ftm->CHANNEL[n].CnSC = sr&(~FTM_CnSC_CHF);
- if (((sr & FTM_CnSC_CHF) != 0) &&
- ((sr & FTM_CnSC_CHIE) != 0) &&
- (pwmp->config->channels[n].callback != NULL)) {
- pwmp->config->channels[n].callback(pwmp);
- }
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if KINETIS_PWM_USE_FTM0
-/**
- * @brief FTM0 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_FTM0_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD1);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_PWM_USE_FTM0 */
-
-#if KINETIS_PWM_USE_FTM1
-/**
- * @brief FTM1 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_FTM1_IRQ_VECTOR) {
-
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD2);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_PWM_USE_FTM1 */
-
-#if KINETIS_PWM_USE_FTM2
-/**
- * @brief FTM2 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_FTM2_IRQ_VECTOR) {
-
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD3);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_PWM_USE_FTM2 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-
-#if KINETIS_PWM_USE_FTM0
- pwmObjectInit(&PWMD1);
- PWMD1.channels = KINETIS_FTM0_CHANNELS;
- PWMD1.ftm = FTM0;
-#endif
-
-#if KINETIS_PWM_USE_FTM1
- pwmObjectInit(&PWMD2);
- PWMD2.channels = KINETIS_FTM1_CHANNELS;
- PWMD2.ftm = FTM1;
-#endif
-
-#if KINETIS_PWM_USE_FTM2
- pwmObjectInit(&PWMD3);
- PWMD3.channels = KINETIS_FTM2_CHANNELS;
- PWMD3.ftm = FTM2;
-#endif
-}
-
-/**
- * @brief Configures and activates the PWM peripheral.
- * @note Starting a driver that is already in the @p PWM_READY state
- * disables all the active channels.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
- uint16_t psc;
- uint8_t i=0;
-
- if (pwmp->state == PWM_STOP) {
- /* Clock activation and timer reset.*/
-#if KINETIS_PWM_USE_FTM0
- if (&PWMD1 == pwmp) {
- SIM->SCGC6 |= SIM_SCGC6_FTM0;
- nvicEnableVector(FTM0_IRQn, KINETIS_PWM_FTM0_PRIORITY);
- }
-#endif
-
-#if KINETIS_PWM_USE_FTM1
- if (&PWMD2 == pwmp) {
- SIM->SCGC6 |= SIM_SCGC6_FTM1;
- nvicEnableVector(FTM1_IRQn, KINETIS_PWM_FTM1_PRIORITY);
- }
-#endif
-
-#if KINETIS_PWM_USE_FTM2
- if (&PWMD3 == pwmp) {
- SIM->SCGC3 |= SIM_SCGC3_FTM2;
- nvicEnableVector(FTM2_IRQn, KINETIS_PWM_FTM2_PRIORITY);
- }
-#endif
- }
- pwmp->ftm->MODE = FTM_MODE_FTMEN_MASK|FTM_MODE_PWMSYNC_MASK;
- pwmp->ftm->SYNC = FTM_SYNC_CNTMIN_MASK|FTM_SYNC_CNTMAX_MASK
- |FTM_SYNC_SWSYNC_MASK;
- pwmp->ftm->COMBINE = FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_SYNCEN2_MASK
- | FTM_COMBINE_SYNCEN1_MASK | FTM_COMBINE_SYNCEN0_MASK;
- pwmp->ftm->SYNCONF = FTM_SYNCONF_SYNCMODE_MASK;
-
- pwmp->ftm->CNTIN = 0x0000;
- //~ pwmp->ftm->SC = 0; /* Disable FTM counter.*/
- pwmp->ftm->CNT = 0x0000; /* Clear count register.*/
-
- /* Prescaler value calculation.*/
- psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency);
- //~ /* Prescaler must be power of two between 1 and 128.*/
- osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency");
- //~ /* Prescaler register value determination.
- //~ Prescaler register value conveniently corresponds to bit position,
- //~ i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/
- for (i = 0; i < 8; i++) {
- if (psc == (unsigned)(1 << i)) {
- break;
- }
- }
-
- /* Set prescaler and clock mode.
- This also sets the following:
- CPWMS up-counting mode
- Timer overflow interrupt disabled
- DMA disabled.*/
- pwmp->ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(i);
- /* Configure period */
- pwmp->ftm->MOD = pwmp->period-1;
- pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
-}
-
-/**
- * @brief Deactivates the PWM peripheral.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
- /* If in ready state then disables the PWM clock.*/
- if (pwmp->state == PWM_READY) {
-#if KINETIS_PWM_USE_FTM0
- if (&PWMD1 == pwmp) {
- SIM->SCGC6 &= ~SIM_SCGC6_FTM0;
- nvicDisableVector(FTM0_IRQn);
- }
-#endif
-
-#if KINETIS_PWM_USE_FTM1
- if (&PWMD2 == pwmp) {
- SIM->SCGC6 &= ~SIM_SCGC6_FTM1;
- nvicDisableVector(FTM1_IRQn);
- }
-#endif
-
-#if KINETIS_PWM_USE_FTM2
- if (&PWMD3 == pwmp) {
- SIM->SCGC3 &= ~SIM_SCGC3_FTM2;
- nvicDisableVector(FTM2_IRQn);
- }
-#endif
- /* Disable FTM counter.*/
- pwmp->ftm->SC = 0;
- pwmp->ftm->MOD = 0;
- }
-}
-
-/**
- * @brief Enables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is active using the specified configuration.
- * @note The function has effect at the next cycle start.
- * @note Channel notification is not enabled.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- * @param[in] width PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width) {
- uint32_t mode = FTM_CnSC_MSB; /* Edge-aligned PWM mode.*/
-
- switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
- case PWM_OUTPUT_ACTIVE_HIGH:
- mode |= FTM_CnSC_ELSB;
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
- mode |= FTM_CnSC_ELSA;
- break;
- }
-
- if (pwmp->ftm->CHANNEL[channel].CnSC & FTM_CnSC_CHIE)
- mode |= FTM_CnSC_CHIE;
-
- pwmp->ftm->CHANNEL[channel].CnSC = mode;
- pwmp->ftm->CHANNEL[channel].CnV = width;
- pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
-}
-
-/**
- * @brief Disables a PWM channel and its notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is disabled and its output line returned to the
- * idle state.
- * @note The function has effect at the next cycle start.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
- pwmp->ftm->CHANNEL[channel].CnSC = 0;
- pwmp->ftm->CHANNEL[channel].CnV = 0;
-}
-
-/**
- * @brief Enables the periodic activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @note If the notification is already enabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
- pwmp->ftm->SC |= FTM_SC_TOIE;
-}
-
-/**
- * @brief Disables the periodic activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @note If the notification is already disabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
- pwmp->ftm->SC &= ~FTM_SC_TOIE;
-}
-
-/**
- * @brief Enables a channel de-activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @pre The channel must have been activated using @p pwmEnableChannel().
- * @note If the notification is already enabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel) {
- pwmp->ftm->CHANNEL[channel].CnSC |= FTM_CnSC_CHIE;
-}
-
-/**
- * @brief Disables a channel de-activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @pre The channel must have been activated using @p pwmEnableChannel().
- * @note If the notification is already disabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel) {
- pwmp->ftm->CHANNEL[channel].CnSC &= ~FTM_CnSC_CHIE;
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_pwm_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_pwm_lld.h deleted file mode 100644 index ccc100f..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_pwm_lld.h +++ /dev/null @@ -1,270 +0,0 @@ -/*
- ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file K20x7/pwm_lld.h
- * @brief KINETIS PWM subsystem low level driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef HAL_PWM_LLD_H_
-#define HAL_PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS 8
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-#if !defined(KINETIS_PWM_USE_FTM0)
- #define KINETIS_PWM_USE_FTM0 FALSE
-#endif
-
-#if !defined(KINETIS_PWM_USE_FTM1)
- #define KINETIS_PWM_USE_FTM1 FALSE
-#endif
-
-#if !defined(KINETIS_PWM_USE_FTM2)
- #define KINETIS_PWM_USE_FTM2 FALSE
-#endif
-
-/**
- * @brief FTM0 interrupt priority level setting.
- */
-#if !defined(KINETIS_PWM_FTM0_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_PWM_FTM0_PRIORITY 12
-#endif
-
-/**
- * @brief FTM1 interrupt priority level setting.
- */
-#if !defined(KINETIS_PWM_FTM1_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_PWM_FTM1_PRIORITY 12
-#endif
-
-/**
- * @brief FTM2 interrupt priority level setting.
- */
-#if !defined(KINETIS_PWM_FTM2_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_PWM_FTM2_PRIORITY 12
-#endif
-
-/** @} */
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief If advanced timer features switch.
- * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
- * enabled.
- * @note The default is @p TRUE.
- */
-#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
-#define KINETIS_PWM_USE_ADVANCED FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Configuration checks. */
-/*===========================================================================*/
-
-#if !KINETIS_PWM_USE_FTM0 && !KINETIS_PWM_USE_FTM1 && !KINETIS_PWM_USE_FTM2
-#error "PWM driver activated but no FTM peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a PWM mode.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief Type of a PWM channel.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief Type of a channels mask.
- */
-typedef uint32_t pwmchnmsk_t;
-
-/**
- * @brief Type of a PWM counter.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief Type of a PWM driver channel configuration structure.
- */
-typedef struct {
- /**
- * @brief Channel active logic level.
- */
- pwmmode_t mode;
-
- /**
- * @brief Channel callback pointer.
- * @note This callback is invoked on the channel compare event. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief Type of a PWM driver configuration structure.
- */
-typedef struct {
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- uint32_t frequency;
- /**
- * @brief PWM period in ticks.
- * @note The low level can use assertions in order to catch invalid
- * period specifications.
- */
- pwmcnt_t period;
- /**
- * @brief Periodic callback pointer.
- * @note This callback is invoked on PWM counter reset. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /**
- * @brief Channels configurations.
- */
- PWMChannelConfig channels[PWM_CHANNELS];
- /* End of the mandatory fields.*/
-} PWMConfig;
-
-/**
- * @brief Structure representing a PWM driver.
- */
-struct PWMDriver {
- /**
- * @brief Driver state.
- */
- pwmstate_t state;
- /**
- * @brief Current driver configuration data.
- */
- const PWMConfig *config;
- /**
- * @brief Current PWM period in ticks.
- */
- pwmcnt_t period;
- /**
- * @brief Mask of the enabled channels.
- */
- pwmchnmsk_t enabled;
- /**
- * @brief Number of channels in this instance.
- */
- pwmchannel_t channels;
-#if defined(PWM_DRIVER_EXT_FIELDS)
- PWM_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the FTM registers block.
- */
- FTM_TypeDef *ftm;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- * been activated using @p pwmStart().
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The PWM unit period is changed to the new value.
- * @note The function has effect at the next cycle start.
- * @note If a period is specified that is shorter than the pulse width
- * programmed in one of the channels then the behavior is not
- * guaranteed.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] period new cycle time in ticks
- *
- * @notapi
- */
-#define pwm_lld_change_period(pwmp, period) \
- do { \
- (pwmp)->ftm->MOD = ((period) - 1); \
- pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;\
- } while(0)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void pwm_lld_init(void);
- void pwm_lld_start(PWMDriver *pwmp);
- void pwm_lld_stop(PWMDriver *pwmp);
- void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width);
- void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
- void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
- void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
- void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel);
- void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* HAL_PWM_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_spi_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_spi_lld.c deleted file mode 100644 index 29ab4e8..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_spi_lld.c +++ /dev/null @@ -1,539 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/spi_lld.c
- * @brief KINETIS SPI subsystem low level driver source.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#if !defined(KINETIS_SPI0_RX_DMA_IRQ_PRIORITY)
-#define KINETIS_SPI0_RX_DMA_IRQ_PRIORITY 8
-#endif
-
-#if !defined(KINETIS_SPI0_RX_DMAMUX_CHANNEL)
-#define KINETIS_SPI0_RX_DMAMUX_CHANNEL 0
-#endif
-
-#if !defined(KINETIS_SPI0_RX_DMA_CHANNEL)
-#define KINETIS_SPI0_RX_DMA_CHANNEL 0
-#endif
-
-#if !defined(KINETIS_SPI0_TX_DMAMUX_CHANNEL)
-#define KINETIS_SPI0_TX_DMAMUX_CHANNEL 1
-#endif
-
-#if !defined(KINETIS_SPI0_TX_DMA_CHANNEL)
-#define KINETIS_SPI0_TX_DMA_CHANNEL 1
-#endif
-
-#if !defined(KINETIS_SPI1_RX_DMA_IRQ_PRIORITY)
-#define KINETIS_SPI1_RX_DMA_IRQ_PRIORITY 8
-#endif
-
-#if !defined(KINETIS_SPI1_RX_DMAMUX_CHANNEL)
-#define KINETIS_SPI1_RX_DMAMUX_CHANNEL 0
-#endif
-
-#if !defined(KINETIS_SPI1_RX_DMA_CHANNEL)
-#define KINETIS_SPI1_RX_DMA_CHANNEL 0
-#endif
-
-#if !defined(KINETIS_SPI1_TX_DMAMUX_CHANNEL)
-#define KINETIS_SPI1_TX_DMAMUX_CHANNEL 1
-#endif
-
-#if !defined(KINETIS_SPI1_TX_DMA_CHANNEL)
-#define KINETIS_SPI1_TX_DMA_CHANNEL 1
-#endif
-
-#if KINETIS_SPI_USE_SPI0
-#define DMAMUX_SPI_RX_SOURCE 16
-#define DMAMUX_SPI_TX_SOURCE 17
-#endif
-
-#if KINETIS_SPI_USE_SPI1
-#define DMAMUX_SPI_RX_SOURCE 18
-#define DMAMUX_SPI_TX_SOURCE 19
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief SPI0 driver identifier.*/
-#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
-SPIDriver SPID1;
-#endif
-
-/** @brief SPI1 driver identifier.*/
-#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
-SPIDriver SPID2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/* Use a dummy byte as the source/destination when a buffer is not provided */
-/* Note: The MMC driver relies on 0xFF being sent for dummy bytes. */
-static volatile uint16_t dmaRxDummy;
-static uint16_t dmaTxDummy = 0xFFFF;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-static void spi_start_xfer(SPIDriver *spip, bool polling)
-{
- /*
- * Enable the DSPI peripheral in master mode.
- * Clear the TX and RX FIFOs.
- * */
- spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_CLR_TXF | SPIx_MCR_CLR_RXF;
-
- /* If we are not polling then enable DMA */
- if (!polling) {
-
- /* Enable receive dma and transmit dma */
- spip->spi->RSER = SPIx_RSER_RFDF_DIRS | SPIx_RSER_RFDF_RE |
- SPIx_RSER_TFFF_RE | SPIx_RSER_TFFF_DIRS;
-
- /* Configure RX DMA */
- if (spip->rxbuf) {
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)spip->rxbuf;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = spip->word_size;
- } else {
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)&dmaRxDummy;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = 0;
- }
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
-
- /* Enable Request Register (ERQ) for RX by writing 0 to SERQ */
- DMA->SERQ = KINETIS_SPI0_RX_DMA_CHANNEL;
-
- /* Configure TX DMA */
- if (spip->txbuf) {
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)spip->txbuf;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = spip->word_size;
- } else {
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)&dmaTxDummy;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = 0;
- }
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
-
- /* Enable Request Register (ERQ) for TX by writing 1 to SERQ */
- DMA->SERQ = KINETIS_SPI0_TX_DMA_CHANNEL;
- }
-}
-
-static void spi_stop_xfer(SPIDriver *spip)
-{
- /* Halt the DSPI peripheral */
- spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_HALT;
-
- /* Clear all the flags which are currently set. */
- spip->spi->SR |= spip->spi->SR;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
-
-OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
- /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
- DMA->CINT = KINETIS_SPI0_RX_DMA_CHANNEL;
-
- spi_stop_xfer(&SPID1);
-
- _spi_isr_code(&SPID1);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-#endif
-
-#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
-
-OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
- /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
- DMA->CINT = KINETIS_SPI1_RX_DMA_CHANNEL;
-
- spi_stop_xfer(&SPID2);
-
- _spi_isr_code(&SPID2);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-#if KINETIS_SPI_USE_SPI0
- spiObjectInit(&SPID1);
-#endif
-#if KINETIS_SPI_USE_SPI1
- spiObjectInit(&SPID2);
-#endif
-}
-
-/**
- * @brief Configures and activates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
- /* If in stopped state then enables the SPI and DMA clocks.*/
- if (spip->state == SPI_STOP) {
-
-#if KINETIS_SPI_USE_SPI0
- if (&SPID1 == spip) {
-
- /* Enable the clock for SPI0 */
- SIM->SCGC6 |= SIM_SCGC6_SPI0;
-
- SPID1.spi = SPI0;
-
- if (spip->config->tar0) {
- spip->spi->CTAR[0] = spip->config->tar0;
- } else {
- spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
- }
- }
-#endif
-
-#if KINETIS_SPI_USE_SPI1
- if (&SPID2 == spip) {
-
- /* Enable the clock for SPI0 */
- SIM->SCGC6 |= SIM_SCGC6_SPI1;
-
- SPID2.spi = SPI1;
-
- if (spip->config->tar0) {
- spip->spi->CTAR[0] = spip->config->tar0;
- } else {
- spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
- }
- }
-#endif
-
- nvicEnableVector(DMA0_IRQn, KINETIS_SPI0_RX_DMA_IRQ_PRIORITY);
-
- SIM->SCGC6 |= SIM_SCGC6_DMAMUX;
- SIM->SCGC7 |= SIM_SCGC7_DMA;
-
- /* Clear DMA error flags */
- DMA->ERR = 0x0F;
-
-#if KINETIS_SPI_USE_SPI0
- /* Rx, select SPI Rx FIFO */
- DMAMUX->CHCFG[KINETIS_SPI0_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
- DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
-
- /* Tx, select SPI Tx FIFO */
- DMAMUX->CHCFG[KINETIS_SPI0_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
- DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
-
- /* Extract the frame size from the TAR */
- uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
- SPIx_CTARn_FMSZ_MASK) + 1;
-
- /* DMA transfer size is 16 bits for a frame size > 8 bits */
- uint16_t dma_size = frame_size > 8 ? 1 : 0;
-
- /* DMA word size is 2 for a 16 bit frame size */
- spip->word_size = frame_size > 8 ? 2 : 1;
-
- /* configure DMA RX fixed values */
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI0->POPR;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SOFF = 0;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SLAST = 0;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DLASTSGA = 0;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
- DMA_ATTR_DSIZE(dma_size);
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
- DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
- DMA_CSR_INTMAJOR_MASK;
-
- /* configure DMA TX fixed values */
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SLAST = 0;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI0->PUSHR;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DOFF = 0;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DLASTSGA = 0;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
- DMA_ATTR_DSIZE(dma_size);
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
- DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
-#endif
-
-#if KINETIS_SPI_USE_SPI1
- /* Rx, select SPI Rx FIFO */
- DMAMUX->CHCFG[KINETIS_SPI1_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
- DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
-
- /* Tx, select SPI Tx FIFO */
- DMAMUX->CHCFG[KINETIS_SPI1_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
- DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
-
- /* Extract the frame size from the TAR */
- uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
- SPIx_CTARn_FMSZ_MASK) + 1;
-
- /* DMA transfer size is 16 bits for a frame size > 8 bits */
- uint16_t dma_size = frame_size > 8 ? 1 : 0;
-
- /* DMA word size is 2 for a 16 bit frame size */
- spip->word_size = frame_size > 8 ? 2 : 1;
-
- /* configure DMA RX fixed values */
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI1->POPR;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SOFF = 0;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SLAST = 0;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].DLASTSGA = 0;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
- DMA_ATTR_DSIZE(dma_size);
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
- DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
- DMA_CSR_INTMAJOR_MASK;
-
- /* configure DMA TX fixed values */
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].SLAST = 0;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI1->PUSHR;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DOFF = 0;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DLASTSGA = 0;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
- DMA_ATTR_DSIZE(dma_size);
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
- DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
-#endif
- }
-}
-
-/**
- * @brief Deactivates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
- /* If in ready state then disables the SPI clock.*/
- if (spip->state == SPI_READY) {
-
- nvicDisableVector(DMA0_IRQn);
-
- SIM->SCGC7 &= ~SIM_SCGC7_DMA;
- SIM->SCGC6 &= ~SIM_SCGC6_DMAMUX;
-
-#if KINETIS_SPI_USE_SPI0
- if (&SPID1 == spip) {
- /* SPI halt.*/
- spip->spi->MCR |= SPIx_MCR_HALT;
- }
-
- /* Disable the clock for SPI0 */
- SIM->SCGC6 &= ~SIM_SCGC6_SPI0;
-#endif
-
-#if KINETIS_SPI_USE_SPI1
- if (&SPID2 == spip) {
- /* SPI halt.*/
- spip->spi->MCR |= SPIx_MCR_HALT;
- }
-
- /* Disable the clock for SPI1 */
- SIM->SCGC6 &= ~SIM_SCGC6_SPI1;
-#endif
- }
-}
-
-/**
- * @brief Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
- palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
- palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief Ignores data on the SPI bus.
- * @details This asynchronous function starts the transmission of a series of
- * idle words on the SPI bus and ignores the received data.
- * @post At the end of the operation the configured callback is invoked.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
- spip->count = n;
- spip->rxbuf = NULL;
- spip->txbuf = NULL;
-
- spi_start_xfer(spip, false);
-}
-
-/**
- * @brief Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- * operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf) {
-
- spip->count = n;
- spip->rxbuf = rxbuf;
- spip->txbuf = txbuf;
-
- spi_start_xfer(spip, false);
-}
-
-/**
- * @brief Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to send
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
- spip->count = n;
- spip->rxbuf = NULL;
- spip->txbuf = (void *)txbuf;
-
- spi_start_xfer(spip, false);
-}
-
-/**
- * @brief Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to receive
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
- spip->count = n;
- spip->rxbuf = rxbuf;
- spip->txbuf = NULL;
-
- spi_start_xfer(spip, false);
-}
-
-/**
- * @brief Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- * synchronization method. This function is useful when exchanging
- * small amount of data on high speed channels, usually in this
- * situation is much more efficient just wait for completion using
- * polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] frame the data frame to send over the SPI bus
- * @return The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
- spi_start_xfer(spip, true);
-
- spip->spi->PUSHR = SPIx_PUSHR_TXDATA(frame);
-
- while ((spip->spi->SR & SPIx_SR_RFDF) == 0)
- ;
-
- frame = spip->spi->POPR;
-
- spi_stop_xfer(spip);
-
- return frame;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_spi_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_spi_lld.h deleted file mode 100644 index 0cf108e..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_spi_lld.h +++ /dev/null @@ -1,261 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/spi_lld.h
- * @brief KINETIS SPI subsystem low level driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef HAL_SPI_LLD_H_
-#define HAL_SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief SPI0 driver enable switch.
- * @details If set to @p TRUE the support for SPI0 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(KINETIS_SPI_USE_SPI0) || defined(__DOXYGEN__)
-#define KINETIS_SPI_USE_SPI0 FALSE
-#endif
-
-/**
- * @brief SPI0 interrupt priority level setting.
- */
-#if !defined(KINETIS_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SPI_SPI0_IRQ_PRIORITY 10
-#endif
-
-/**
- * @brief SPI1 driver enable switch.
- * @details If set to @p TRUE the support for SPI0 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(KINETIS_SPI_USE_SPI1) || defined(__DOXYGEN__)
-#define KINETIS_SPI_USE_SPI1 FALSE
-#endif
-
-/**
- * @brief SPI1 interrupt priority level setting.
- */
-#if !defined(KINETIS_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SPI_SPI1_IRQ_PRIORITY 10
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if KINETIS_SPI_USE_SPI0 && !KINETIS_HAS_SPI0
-#error "SPI0 not present in the selected device"
-#endif
-
-#if KINETIS_SPI_USE_SPI1 && !KINETIS_HAS_SPI1
-#error "SPI1 not present in the selected device"
-#endif
-
-#if KINETIS_SPI_USE_SPI0 && KINETIS_SPI_USE_SPI1
-#error "Only one SPI peripheral can be enabled"
-#endif
-
-#if !(KINETIS_SPI_USE_SPI0 || KINETIS_SPI_USE_SPI1)
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-#if KINETIS_SPI_USE_SPI0 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI0"
-#endif
-
-#if KINETIS_SPI_USE_SPI1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI1"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief SPI notification callback type.
- *
- * @param[in] spip pointer to the @p SPIDriver object triggering the
- * callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
- /**
- * @brief Operation complete callback or @p NULL.
- */
- spicallback_t end_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief The chip select line port - when not using pcs.
- */
- ioportid_t ssport;
- /**
- * @brief The chip select line pad number - when not using pcs.
- */
- uint16_t sspad;
- /**
- * @brief SPI initialization data.
- */
- uint32_t tar0;
-} SPIConfig;
-
-/**
- * @brief Structure representing a SPI driver.
- */
-struct SPIDriver {
- /**
- * @brief Driver state.
- */
- spistate_t state;
- /**
- * @brief Current configuration data.
- */
- const SPIConfig *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- thread_reference_t thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the bus.
- */
- mutex_t mutex;
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
- SPI_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the SPIx registers block.
- */
- SPI_TypeDef *spi;
- /**
- * @brief Number of bytes/words of data to transfer.
- */
- size_t count;
- /**
- * @brief Word size in bytes.
- */
- size_t word_size;
- /**
- * @brief Pointer to the buffer with data to send.
- */
- const uint8_t *txbuf;
- /**
- * @brief Pointer to the buffer to put received data.
- */
- uint8_t *rxbuf;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/* TAR settings for n bits at SYSCLK / 2 */
-#define KINETIS_SPI_TAR_SYSCLK_DIV_2(n)\
- SPIx_CTARn_FMSZ((n) - 1) | \
- SPIx_CTARn_CPOL | \
- SPIx_CTARn_CPHA | \
- SPIx_CTARn_DBR | \
- SPIx_CTARn_PBR(0) | \
- SPIx_CTARn_BR(0) | \
- SPIx_CTARn_CSSCK(0) | \
- SPIx_CTARn_ASC(0) | \
- SPIx_CTARn_DT(0)
-
-/* TAR settings for n bits at SYSCLK / 4096 for debugging */
-#define KINETIS_SPI_TAR_SYSCLK_DIV_4096(n) \
- SPIx_CTARn_FMSZ(((n) - 1)) | \
- SPIx_CTARn_CPOL | \
- SPIx_CTARn_CPHA | \
- SPIx_CTARn_PBR(0) | \
- SPIx_CTARn_BR(0xB) | \
- SPIx_CTARn_CSSCK(0xB) | \
- SPIx_CTARn_ASC(0x7) | \
- SPIx_CTARn_DT(0xB)
-
-#define KINETIS_SPI_TAR_8BIT_FAST KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
-#define KINETIS_SPI_TAR_8BIT_SLOW KINETIS_SPI_TAR_SYSCLK_DIV_4096(8)
-
-#define KINETIS_SPI_TAR0_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
-#define KINETIS_SPI_TAR1_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if KINETIS_SPI_USE_SPI0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if KINETIS_SPI_USE_SPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void spi_lld_init(void);
- void spi_lld_start(SPIDriver *spip);
- void spi_lld_stop(SPIDriver *spip);
- void spi_lld_select(SPIDriver *spip);
- void spi_lld_unselect(SPIDriver *spip);
- void spi_lld_ignore(SPIDriver *spip, size_t n);
- void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf);
- void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
- void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
- uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* HAL_SPI_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/kinetis_registry.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/kinetis_registry.h deleted file mode 100644 index d2eea6f..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/kinetis_registry.h +++ /dev/null @@ -1,258 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014 Derek Mulcahy
- (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file K20x/kinetis_registry.h
- * @brief K20x capabilities registry.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef KINETIS_REGISTRY_H_
-#define KINETIS_REGISTRY_H_
-
-#if !defined(K20x) || defined(__DOXYGEN__)
-#define K20x
-#endif
-
-/*===========================================================================*/
-/* Platform capabilities. */
-/*===========================================================================*/
-
-/**
- * @name K20x capabilities
- * @{
- */
-/*===========================================================================*/
-/* K20x5 */
-/*===========================================================================*/
-#if defined(K20x5) || defined(__DOXYGEN__)
-
-/**
- * @brief Maximum system and core clock (f_SYS) frequency.
- */
-#define KINETIS_SYSCLK_MAX 50000000L
-
-/**
- * @brief Maximum bus clock (f_BUS) frequency.
- */
-#define KINETIS_BUSCLK_MAX 50000000L
-
-/**
- * @brief Maximum flash clock (f_FLASH) frequency.
- */
-#define KINETIS_FLASHCLK_MAX 25000000L
-
-/* ADC attributes.*/
-#define KINETIS_HAS_ADC0 TRUE
-#define KINETIS_ADC0_IRQ_VECTOR Vector98
-#define KINETIS_HAS_ADC1 FALSE
-
-/* DAC attributes.*/
-#define KINETIS_HAS_DAC0 FALSE
-
-/* DMA attributes.*/
-#define KINETIS_DMA0_IRQ_VECTOR Vector40
-#define KINETIS_DMA1_IRQ_VECTOR Vector44
-#define KINETIS_DMA2_IRQ_VECTOR Vector48
-#define KINETIS_DMA3_IRQ_VECTOR Vector4C
-#define KINETIS_HAS_DMA_ERROR_IRQ TRUE
-#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector50
-
-/* EXT attributes.*/
-#define KINETIS_PORTA_IRQ_VECTOR VectorE0
-#define KINETIS_PORTB_IRQ_VECTOR VectorE4
-#define KINETIS_PORTC_IRQ_VECTOR VectorE8
-#define KINETIS_PORTD_IRQ_VECTOR VectorEC
-#define KINETIS_PORTE_IRQ_VECTOR VectorF0
-#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
-#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
-#define KINETIS_GPIO_HAS_OPENDRAIN TRUE
-
-/* I2C attributes.*/
-#define KINETIS_HAS_I2C0 TRUE
-#define KINETIS_I2C0_IRQ_VECTOR Vector6C
-#define KINETIS_HAS_I2C1 FALSE
-
-/* Serial attributes.*/
-#define KINETIS_HAS_SERIAL0 TRUE
-#define KINETIS_SERIAL0_IRQ_VECTOR Vector80
-#define KINETIS_HAS_SERIAL1 TRUE
-#define KINETIS_SERIAL1_IRQ_VECTOR Vector88
-#define KINETIS_HAS_SERIAL2 TRUE
-#define KINETIS_SERIAL2_IRQ_VECTOR Vector90
-#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
-#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR Vector84
-#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR Vector8C
-#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR Vector94
-#define KINETIS_SERIAL0_IS_LPUART FALSE
-#define KINETIS_SERIAL0_IS_UARTLP FALSE
-#define KINETIS_SERIAL1_IS_LPUART FALSE
-
-/* SPI attributes.*/
-#define KINETIS_HAS_SPI0 TRUE
-#define KINETIS_SPI0_IRQ_VECTOR Vector70
-#define KINETIS_HAS_SPI1 FALSE
-
-/* FlexTimer attributes.*/
-#define KINETIS_FTM0_CHANNELS 8
-#define KINETIS_FTM1_CHANNELS 2
-
-#define KINETIS_FTM0_IRQ_VECTOR VectorA4
-#define KINETIS_FTM1_IRQ_VECTOR VectorA8
-#define KINETIS_HAS_FTM2 FALSE
-
-/* GPT attributes.*/
-#define KINETIS_HAS_PIT0 TRUE
-#define KINETIS_PIT0_IRQ_VECTOR VectorB8
-#define KINETIS_HAS_PIT1 TRUE
-#define KINETIS_PIT1_IRQ_VECTOR VectorBC
-#define KINETIS_HAS_PIT2 TRUE
-#define KINETIS_PIT2_IRQ_VECTOR VectorC0
-#define KINETIS_HAS_PIT3 TRUE
-#define KINETIS_PIT3_IRQ_VECTOR VectorC4
-#define KINETIS_HAS_PIT_COMMON_IRQ FALSE
-
-/* USB attributes.*/
-#define KINETIS_HAS_USB TRUE
-#define KINETIS_USB_IRQ_VECTOR VectorCC
-#define KINETIS_USB0_IS_USBOTG TRUE
-#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
-
-/* LPTMR attributes.*/
-#define KINETIS_LPTMR0_IRQ_VECTOR VectorDC
-
-/*===========================================================================*/
-/* K20x7 */
-/*===========================================================================*/
-#elif defined(K20x7)
-
-/**
- * @brief Maximum system and core clock (f_SYS) frequency.
- */
-#define KINETIS_SYSCLK_MAX 72000000L
-
-/**
- * @brief Maximum bus clock (f_BUS) frequency.
- */
-#define KINETIS_BUSCLK_MAX 50000000L
-
-/**
- * @brief Maximum flash clock (f_FLASH) frequency.
- */
-#define KINETIS_FLASHCLK_MAX 25000000L
-
-/**
- * @name K20x7 attributes
- * @{
- */
-
-/* ADC attributes.*/
-#define KINETIS_HAS_ADC0 TRUE
-#define KINETIS_ADC0_IRQ_VECTOR Vector124
-#define KINETIS_HAS_ADC1 TRUE
-#define KINETIS_ADC1_IRQ_VECTOR Vector128
-
-/* DAC attributes.*/
-#define KINETIS_HAS_DAC0 TRUE
-#define KINTEIS_DAC0_IRQ_VECTOR Vector184
-
-/* DMA attributes.*/
-#define KINETIS_DMA0_IRQ_VECTOR Vector40
-#define KINETIS_DMA1_IRQ_VECTOR Vector44
-#define KINETIS_DMA2_IRQ_VECTOR Vector48
-#define KINETIS_DMA3_IRQ_VECTOR Vector4C
-#define KINETIS_HAS_DMA_ERROR_IRQ TRUE
-#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector50
-
-/* EXT attributes.*/
-#define KINETIS_PORTA_IRQ_VECTOR Vector19C
-#define KINETIS_PORTB_IRQ_VECTOR Vector1A0
-#define KINETIS_PORTC_IRQ_VECTOR Vector1A4
-#define KINETIS_PORTD_IRQ_VECTOR Vector1A8
-#define KINETIS_PORTE_IRQ_VECTOR Vector1AC
-#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
-#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
-#define KINETIS_GPIO_HAS_OPENDRAIN TRUE
-
-/* I2C attributes.*/
-#define KINETIS_HAS_I2C0 TRUE
-#define KINETIS_I2C0_IRQ_VECTOR VectorA0
-#define KINETIS_HAS_I2C1 TRUE
-#define KINETIS_I2C1_IRQ_VECTOR VectorA4
-
-/* Serial attributes.*/
-#define KINETIS_HAS_SERIAL0 TRUE
-#define KINETIS_SERIAL0_IRQ_VECTOR VectorF4
-#define KINETIS_HAS_SERIAL1 TRUE
-#define KINETIS_SERIAL1_IRQ_VECTOR VectorFC
-#define KINETIS_HAS_SERIAL2 TRUE
-#define KINETIS_SERIAL2_IRQ_VECTOR Vector104
-#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
-#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR VectorF8
-#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR Vector100
-#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR Vector108
-#define KINETIS_SERIAL0_IS_LPUART FALSE
-#define KINETIS_SERIAL0_IS_UARTLP FALSE
-#define KINETIS_SERIAL1_IS_LPUART FALSE
-
-/* SPI attributes.*/
-#define KINETIS_HAS_SPI0 TRUE
-#define KINETIS_SPI0_IRQ_VECTOR VectorA8
-#define KINETIS_HAS_SPI1 TRUE
-#define KINETIS_SPI1_IRQ_VECTOR VectorAC
-
-/* FlexTimer attributes.*/
-#define KINETIS_FTM0_CHANNELS 8
-#define KINETIS_FTM1_CHANNELS 2
-#define KINETIS_FTM2_CHANNELS 2
-
-#define KINETIS_FTM0_IRQ_VECTOR Vector138
-#define KINETIS_FTM1_IRQ_VECTOR Vector13C
-#define KINETIS_HAS_FTM2 TRUE
-#define KINETIS_FTM2_IRQ_VECTOR Vector140
-
-/* GPT attributes.*/
-#define KINETIS_HAS_PIT0 TRUE
-#define KINETIS_PIT0_IRQ_VECTOR Vector150
-#define KINETIS_HAS_PIT1 TRUE
-#define KINETIS_PIT1_IRQ_VECTOR Vector154
-#define KINETIS_HAS_PIT2 TRUE
-#define KINETIS_PIT2_IRQ_VECTOR Vector158
-#define KINETIS_HAS_PIT3 TRUE
-#define KINETIS_PIT3_IRQ_VECTOR Vector15C
-#define KINETIS_HAS_PIT FALSE
-#define KINETIS_PIT_CHANNELS 4
-#define KINETIS_HAS_PIT_COMMON_IRQ FALSE
-
-/* USB attributes.*/
-#define KINETIS_HAS_USB TRUE
-#define KINETIS_USB_IRQ_VECTOR Vector164
-#define KINETIS_USB0_IS_USBOTG TRUE
-#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
-
-/* LPTMR attributes.*/
-#define KINETIS_LPTMR0_IRQ_VECTOR Vector194
-
-#endif /* K20xY */
-
-/** @} */
-
-#endif /* KINETIS_REGISTRY_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/platform.dox b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/platform.dox deleted file mode 100644 index 3fb142d..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/platform.dox +++ /dev/null @@ -1,365 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/* TODO Still need to edit this entire file */
-
-/**
- * @defgroup MK20D5_DRIVERS MK20D5 Drivers
- * @details This section describes all the supported drivers on the MK20D5
- * platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup MK20D5_HAL MK20D5 Initialization Support
- * @details The MK20D5 HAL support is responsible for system initialization.
- *
- * @section mk20d5_hal_1 Supported HW resources
- * - PLL1.
- * - PLL2.
- * - RCC.
- * - Flash.
- * .
- * @section mk20d5_hal_2 MK20D5 HAL driver implementation features
- * - PLL startup and stabilization.
- * - Clock tree initialization.
- * - Clock source selection.
- * - Flash wait states initialization based on the selected clock options.
- * - SYSTICK initialization based on current clock and kernel required rate.
- * - DMA support initialization.
- * .
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_ADC MK20D5 ADC Support
- * @details The MK20D5 ADC driver supports the ADC peripherals using DMA
- * channels for maximum performance.
- *
- * @section mk20d5_adc_1 Supported HW resources
- * - ADC1.
- * - ADC2.
- * - ADC3.
- * - DMA2.
- * .
- * @section mk20d5_adc_2 MK20D5 ADC driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Streaming conversion using DMA for maximum performance.
- * - Programmable ADC interrupt priority level.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - DMA and ADC errors detection.
- * .
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_CAN MK20D5 CAN Support
- * @details The MK20D5 CAN driver uses the CAN peripherals.
- *
- * @section mk20d5_can_1 Supported HW resources
- * - bxCAN1.
- * .
- * @section mk20d5_can_2 MK20D5 CAN driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Support for bxCAN sleep mode.
- * - Programmable bxCAN interrupts priority level.
- * .
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_EXT MK20D5 EXT Support
- * @details The MK20D5 EXT driver uses the EXTI peripheral.
- *
- * @section mk20d5_ext_1 Supported HW resources
- * - EXTI.
- * .
- * @section mk20d5_ext_2 MK20D5 EXT driver implementation features
- * - Each EXTI channel can be independently enabled and programmed.
- * - Programmable EXTI interrupts priority level.
- * - Capability to work as event sources (WFE) rather than interrupt sources.
- * .
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_GPT MK20D5 GPT Support
- * @details The MK20D5 GPT driver uses the TIMx peripherals.
- *
- * @section mk20d5_gpt_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * - TIM8.
- * .
- * @section mk20d5_gpt_2 MK20D5 GPT driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_ICU MK20D5 ICU Support
- * @details The MK20D5 ICU driver uses the TIMx peripherals.
- *
- * @section mk20d5_icu_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * - TIM8.
- * .
- * @section mk20d5_icu_2 MK20D5 ICU driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_MAC MK20D5 MAC Support
- * @details The MK20D5 MAC driver supports the ETH peripheral.
- *
- * @section mk20d5_mac_1 Supported HW resources
- * - ETH.
- * - PHY (external).
- * .
- * @section mk20d5_mac_2 MK20D5 MAC driver implementation features
- * - Dedicated DMA operations.
- * - Support for checksum off-loading.
- * .
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_PAL MK20D5 PAL Support
- * @details The MK20D5 PAL driver uses the GPIO peripherals.
- *
- * @section mk20d5_pal_1 Supported HW resources
- * - GPIOA.
- * - GPIOB.
- * - GPIOC.
- * - GPIOD.
- * - GPIOE.
- * - GPIOF.
- * - GPIOG.
- * - GPIOH.
- * - GPIOI.
- * .
- * @section mk20d5_pal_2 MK20D5 PAL driver implementation features
- * The PAL driver implementation fully supports the following hardware
- * capabilities:
- * - 16 bits wide ports.
- * - Atomic set/reset functions.
- * - Atomic set+reset function (atomic bus operations).
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section mk20d5_pal_3 Supported PAL setup modes
- * The MK20D5 PAL driver supports the following I/O modes:
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_INPUT_PULLUP.
- * - @p PAL_MODE_INPUT_PULLDOWN.
- * - @p PAL_MODE_INPUT_ANALOG.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * - @p PAL_MODE_OUTPUT_OPENDRAIN.
- * - @p PAL_MODE_ALTERNATE (non standard).
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section mk20d5_pal_4 Suboptimal behavior
- * The MK20D5 GPIO is less than optimal in several areas, the limitations
- * should be taken in account while using the PAL driver:
- * - Pad/port toggling operations are not atomic.
- * - Pad/group mode setup is not atomic.
- * .
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_PWM MK20D5 PWM Support
- * @details The MK20D5 PWM driver uses the TIMx peripherals.
- *
- * @section mk20d5_pwm_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * - TIM8.
- * .
- * @section mk20d5_pwm_2 MK20D5 PWM driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Four independent PWM channels per timer.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_SDC MK20D5 SDC Support
- * @details The MK20D5 SDC driver uses the SDIO peripheral.
- *
- * @section mk20d5_sdc_1 Supported HW resources
- * - SDIO.
- * - DMA2.
- * .
- * @section mk20d5_sdc_2 MK20D5 SDC driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Programmable interrupt priority.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * .
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_SERIAL MK20D5 Serial Support
- * @details The MK20D5 Serial driver uses the USART/UART peripherals in a
- * buffered, interrupt driven, implementation.
- *
- * @section mk20d5_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * - USART3.
- * - UART4.
- * - UART5.
- * - USART6.
- * .
- * @section mk20d5_serial_2 MK20D5 Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each UART/USART can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Fully interrupt driven.
- * - Programmable priority levels for each UART/USART.
- * .
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_SPI MK20D5 SPI Support
- * @details The SPI driver supports the MK20D5 SPI peripherals using DMA
- * channels for maximum performance.
- *
- * @section mk20d5_spi_1 Supported HW resources
- * - SPI1.
- * - SPI2.
- * - SPI3.
- * - DMA1.
- * - DMA2.
- * .
- * @section mk20d5_spi_2 MK20D5 SPI driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each SPI can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each SPI.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - Programmable DMA error hook.
- * .
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_UART MK20D5 UART Support
- * @details The UART driver supports the MK20D5 USART peripherals using DMA
- * channels for maximum performance.
- *
- * @section mk20d5_uart_1 Supported HW resources
- * The UART driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * - USART3.
- * - DMA1.
- * - DMA2.
- * .
- * @section mk20d5_uart_2 MK20D5 UART driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each UART/USART can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each UART/USART.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - Programmable DMA error hook.
- * .
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_PLATFORM_DRIVERS MK20D5 Platform Drivers
- * @details Platform support drivers. Platform drivers do not implement HAL
- * standard driver templates, their role is to support platform
- * specific functionalities.
- *
- * @ingroup MK20D5_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_DMA MK20D5 DMA Support
- * @details This DMA helper driver is used by the other drivers in order to
- * access the shared DMA resources in a consistent way.
- *
- * @section mk20d5_dma_1 Supported HW resources
- * The DMA driver can support any of the following hardware resources:
- * - DMA1.
- * - DMA2.
- * .
- * @section mk20d5_dma_2 MK20D5 DMA driver implementation features
- * - Exports helper functions/macros to the other drivers that share the
- * DMA resource.
- * - Automatic DMA clock stop when not in use by any driver.
- * - DMA streams and interrupt vectors sharing among multiple drivers.
- * .
- * @ingroup MK20D5_PLATFORM_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_ISR MK20D5 ISR Support
- * @details This ISR helper driver is used by the other drivers in order to
- * map ISR names to physical vector names.
- *
- * @ingroup MK20D5_PLATFORM_DRIVERS
- */
-
-/**
- * @defgroup MK20D5_RCC MK20D5 RCC Support
- * @details This RCC helper driver is used by the other drivers in order to
- * access the shared RCC resources in a consistent way.
- *
- * @section mk20d5_rcc_1 Supported HW resources
- * - RCC.
- * .
- * @section mk20d5_rcc_2 MK20D5 RCC driver implementation features
- * - Peripherals reset.
- * - Peripherals clock enable.
- * - Peripherals clock disable.
- * .
- * @ingroup MK20D5_PLATFORM_DRIVERS
- */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/platform.mk b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/platform.mk deleted file mode 100644 index beee336..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/platform.mk +++ /dev/null @@ -1,18 +0,0 @@ -# List of all platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/hal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_pal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_serial_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/hal_spi_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/hal_pwm_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_lld.c deleted file mode 100644 index 77addf0..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_lld.c +++ /dev/null @@ -1,472 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/hal_lld.c
- * @brief Kinetis KL2x HAL Driver subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "osal.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-#ifdef __CC_ARM
-__attribute__ ((section(".ARM.__at_0x400")))
-#else
-__attribute__ ((used,section(".cfmconfig")))
-#endif
-const uint8_t _cfm[0x10] = {
- 0xFF, /* NV_BACKKEY3: KEY=0xFF */
- 0xFF, /* NV_BACKKEY2: KEY=0xFF */
- 0xFF, /* NV_BACKKEY1: KEY=0xFF */
- 0xFF, /* NV_BACKKEY0: KEY=0xFF */
- 0xFF, /* NV_BACKKEY7: KEY=0xFF */
- 0xFF, /* NV_BACKKEY6: KEY=0xFF */
- 0xFF, /* NV_BACKKEY5: KEY=0xFF */
- 0xFF, /* NV_BACKKEY4: KEY=0xFF */
- 0xFF, /* NV_FPROT3: PROT=0xFF */
- 0xFF, /* NV_FPROT2: PROT=0xFF */
- 0xFF, /* NV_FPROT1: PROT=0xFF */
- 0xFF, /* NV_FPROT0: PROT=0xFF */
-#if defined(KINETIS_NV_FSEC_BYTE)
- #warning Please triple check your FSEC setting: KEYEN!=b10, MEEN==b10, SEC!=b10 leads to an unmodifiable chip.
- KINETIS_NV_FSEC_BYTE,
-#else /* KINETIS_NV_FSEC_BYTE */
- 0x7E, /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
-#endif /* KINETIS_NV_FSEC_BYTE */
-#if defined(KINETIS_NV_FOPT_BYTE)
- KINETIS_NV_FOPT_BYTE,
-#else /* KINETIS_NV_FOPT_BYTE */
- 0xFF, /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
- NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
- /* on KL27: bit7-6:BOOTSRC_SEL=0b11 (11=from ROM; 00=from FLASH)
- bit1:BOOTPIN_OPT=1 (NMI pin not sampled at boot) */
-#endif /* KINETIS_NV_FOPT_BYTE */
- 0xFF,
- 0xFF
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-}
-
-/**
- * @brief KL2x clocks and PLL initialization.
- * @note All the involved constants come from the file @p board.h.
- * @note This function should be invoked just after the system reset.
- *
- * @special
- */
-void kl2x_clock_init(void) {
-#if !KINETIS_NO_INIT
-
- /* Disable COP watchdog */
- SIM->COPC = 0;
-
- /* Enable PORTA */
- SIM->SCGC5 |= SIM_SCGC5_PORTA;
-
- /* --- MCG mode: FEI (default out of reset) ---
- f_MCGOUTCLK = f_int * F
- F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits.
- Typical f_MCGOUTCLK = 21 MHz immediately after reset.
- C4[DMX32]=0 and C4[DRST_DRS]=00 => FLL factor=640.
- C3[SCTRIM] and C4[SCFTRIM] factory trim values apply to f_int. */
-
- /* System oscillator drives 32 kHz clock (OSC32KSEL=0) */
- SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
-
-#if KINETIS_HAS_MCG_LITE
-/* MCU only has MCG_Lite */
-
-#if KINETIS_MCGLITE_MODE == KINETIS_MCGLITE_MODE_LIRC8M
- /* Out of reset, the MCU is in LIRC8M mode. */
- /* Except when coming out of the ROM bootloader, then
- * the MCU is in HIRC mode; so better set it explicitly here. */
-
- /* Switching to LIRC8M mode, page 414 of the KL27Z manual. */
-
- /* (1) Write 1b to MCG_C2[IRCS] to select LIRC 8M. */
- MCG->C2 |= MCG_C2_IRCS;
-
- /* (2) Write 1b to MCG_C1[IRCLKEN] to enable LIRC clock (optional). */
- MCG->C1 |= MCG_C1_IRCLKEN;
-
- /* (2) Write 01b to MCG_C1[CLKS] to select LIRC clock source. */
- MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS_LIRC;
-
- /* (3) Check MCG_S[CLKST] to confirm LIRC clock source is selected. */
- while( (MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_LIRC )
- ;
-
-#elif KINETIS_MCGLITE_MODE == KINETIS_MCGLITE_MODE_HIRC
- /* Switching to HIRC mode, page 413 of the KL27Z manual. */
-
- /* (1) Write 1b to MCG_MC[HIRCEN] to enable HIRC (optional). */
- MCG->MC |= MCG_MC_HIRCEN;
-
- /* (2) Write 00b to MCG_C1[CLKS] to select HIRC clock source. */
- MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS_HIRC;
-
- /* (3) Check MCG_S[CLKST] to confirm HIRC clock source is selected. */
- while( (MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_HIRC )
- ;
-
-#elif KINETIS_MCGLITE_MODE == KINETIS_MCGLITE_MODE_EXT
- /* Assuming we have an external crystal, frequency
- * specified with KINETIS_XTAL_FREQUENCY.
- *
- * Note: Except with 32768 kHz crystal (low-freq mode),
- * external load capacitors and a feedback resistor
- * are *required*. Additionally, a series resistor is
- * required in the high-gain mode, and forbidden in
- * the low-power mode.
- * In this case, the internal caps can be configured
- * via KINETIS_BOARD_OSCILLATOR_SETTING.
- * (Page 420 of the KL27 manual.) */
-
- /* EXTAL0 and XTAL0 */
- PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
- PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
-
- /* Internal capacitors for crystal */
-#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
- OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
-#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
- /* Disable the internal capacitors */
- OSC0->CR = 0;
-#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
-
- /* Switching to EXT mode, page 413 of the KL27 manual. */
-
- /* (1) Configure MCG_C2[EREFS0] for external clock source selection. */
- #if KINETIS_XTAL_FREQUENCY == 32768 /* low range */
- MCG->C2 = (MCG->C2 & ~MCG_C2_RANGE0_MASK) | MCG_C2_RANGE0(0);
- #elif (KINETIS_XTAL_FREQUENCY >= 1000000 && \
- KINETIS_XTAL_FREQUENCY <= 8000000) /* high range */
- MCG->C2 = (MCG->C2 & ~MCG_C2_RANGE0_MASK) | MCG_C2_RANGE0(1);
- #elif (KINETIS_XTAL_FREQUENCY > 8000000 && \
- KINETIS_XTAL_FREQUENCY <= 32000000) /* very high range */
- MCG->C2 = (MCG->C2 & ~MCG_C2_RANGE0_MASK) | MCG_C2_RANGE0(2);
- #else /* KINETIS_XTAL_FREQUENCY == */
- #error KINETIS_XTAL_FREQUENCY not in allowed range
- #endif /* KINETIS_XTAL_FREQUENCY == */
-
- #if defined(KINETIS_XTAL_HIGH_GAIN) && KINETIS_XTAL_HIGH_GAIN
- MCG->C2 |= MCG_C2_HGO0;
- #endif /* KINETIS_XTAL_HIGH_GAIN */
-
- /* Oscillator requested. */
- MCG->C2 |= MCG_C2_EREFS0;
-
- /* (2) Write 10b to MCG_C1[CLKS] to select external clock source. */
- MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS_EXT;
-
- /* (3) Check MCG_S[CLKST] to confirm external clock source is selected. */
- while( (MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXT )
- ;
-
-#else /* KINETIS_MCGLITE_MODE */
-#error Unimplemented KINETIS_MCGLITE_MODE
-#endif /* KINETIS_MCGLITE_MODE */
-
-#else /* KINETIS_HAS_MCG_LITE */
-/* MCU has full blown MCG */
-
-#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
- /* This is the default mode at reset. */
- /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
- * OUTDIV1 (divider for core/system and bus/flash clock)
- * OUTDIV4 (additional divider for bus/flash clock) */
- SIM->CLKDIV1 =
- SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
- SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
-
- /* Configure FEI mode */
- MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
- (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
-
-#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEE
- /* TODO: check this, for generality */
- /*
- * FLL Enabled External (FEE) MCG Mode
- * 24 MHz core, 12 MHz bus - using 32.768 kHz crystal with FLL.
- * f_MCGOUTCLK = (f_ext / FLL_R) * F
- * = (32.768 kHz ) *
- * FLL_R is the reference divider selected by C1[FRDIV]
- * F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32].
- *
- * Then the core/system and bus/flash clocks are divided:
- * f_SYS = f_MCGOUTCLK / OUTDIV1 = 48 MHz / 1 = 48 MHz
- * f_BUS = f_MCGOUTCLK / OUTDIV1 / OUTDIV4 = MHz / 4 = 24 MHz
- */
-
- SIM->SOPT2 =
- SIM_SOPT2_TPMSRC(1); /* MCGFLLCLK clock or MCGPLLCLK/2 */
- /* PLLFLLSEL=0 -> MCGFLLCLK */
-
- /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
- * OUTDIV1 (divider for core/system and bus/flash clock)
- * OUTDIV4 (additional divider for bus/flash clock) */
- SIM->CLKDIV1 =
- SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1 - 1) |
- SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4 - 1);
-
- /* EXTAL0 and XTAL0 */
- PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
- PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
-
- /* Internal capacitors for crystal */
-#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
- OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
-#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
- /* Disable the internal capacitors */
- OSC0->CR = 0;
-#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
-
- /* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
- /* To change from FEI mode to FEE mode: */
- /* (1) Select the external clock source in C2 register.
- Use low-power OSC mode (HGO0=0) which enables internal feedback
- resistor, for 32.768 kHz crystal configuration. */
- MCG->C2 =
- MCG_C2_RANGE0(0) | /* low frequency range (<= 40 kHz) */
- MCG_C2_EREFS0; /* external reference (using a crystal) */
- /* (2) Write to C1 to select the clock mode. */
- MCG->C1 = /* Clear the IREFS bit to switch to the external reference. */
- MCG_C1_CLKS_FLLPLL | /* Use FLL for system clock, MCGCLKOUT. */
- MCG_C1_FRDIV(0); /* Don't divide 32kHz ERCLK FLL reference. */
- MCG->C6 = 0; /* PLLS=0: Select FLL as MCG source, not PLL */
-
- /* Loop until S[OSCINIT0] is 1, indicating the
- crystal selected by C2[EREFS0] has been initialized. */
- while ((MCG->S & MCG_S_OSCINIT0) == 0)
- ;
- /* Loop until S[IREFST] is 0, indicating the
- external reference is the current reference clock source. */
- while ((MCG->S & MCG_S_IREFST) != 0)
- ; /* Wait until external reference clock is FLL reference. */
- /* (1)(e) Loop until S[CLKST] indicates FLL feeds MCGOUTCLK. */
- while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_FLL)
- ; /* Wait until FLL has been selected. */
-
- /* --- MCG mode: FEE --- */
- /* Set frequency range for DCO output (MCGFLLCLK). */
- MCG->C4 = (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0) |
- MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS);
-
- /* Wait for the FLL lock time; t[fll_acquire][max] = 1 ms */
- /* TODO - not implemented - is it required? Freescale example code
- seems to omit it. */
-
-#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
- uint32_t ratio, frdiv;
- uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
- uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
- uint8_t i;
-
- /*
- * PLL Enabled External (PEE) MCG Mode
- * Uses external crystal (KINETIS_XTAL_FREQUENCY) with PLL.
- * f_MCGOUTCLK = (OSCCLK / PLL_R) * M
- * OSCCLK = KINETIS_XTAL_FREQUENCY
- * PLL_R is the reference divider selected by C5[PRDIV0]
- * (OSCCLK/PLL_R must be between 2 and 4 MHz)
- * M is the multiplier selected by C6[VDIV0]
- *
- * Running from PLL, so assuming PLLCLK = MCGOUTCLK.
- *
- * Then the core/system and bus/flash clocks are divided:
- * f_SYS = f_MCGOUTCLK / OUTDIV1 = 96 MHz / 2 = 48 MHz
- * f_BUS = f_MCGOUTCLK / OUTDIV1 / OUTDIV4 = 96 MHz / 4 = 24 MHz
- */
-
- /* EXTAL0 and XTAL0 */
- PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
- PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
-
- /* Start in FEI mode */
-
- /* Internal capacitors for crystal */
-#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
- OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
-#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
- /* Disable the internal capacitors */
- OSC0->CR = 0;
-#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
-
- /* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
- /* To change from FEI mode to FBE mode: */
- /* (1) Select the external clock source in C2 register.
- Use low-power OSC mode (HGO0=0) which enables internal feedback
- resistor since FRDM-KL25Z has feedback resistor R25 unpopulated.
- Use high-gain mode by setting C2[HGO0] instead if external
- feedback resistor Rf is installed. */
- MCG->C2 = MCG_C2_EREFS0; /* external reference (using a crystal) */
- if (KINETIS_XTAL_FREQUENCY > 8000000UL)
- MCG->C2 |= MCG_C2_RANGE0(2);
- else
- MCG->C2 |= MCG_C2_RANGE0(1);
- /* (2) Write to C1 to select the clock mode. */
- frdiv = 7;
- ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
- for (i = 0; i < ratio_quantity; ++i) {
- if (ratio == ratios[i]) {
- frdiv = i;
- break;
- }
- }
-
- /* Switch to crystal as clock source, FLL input of 31.25 KHz */
- MCG->C1 = /* Clear the IREFS bit to switch to the external reference. */
- MCG_C1_CLKS_ERCLK | /* Use Ext Ref Clock for system clock, MCGCLKOUT. */
- MCG_C1_FRDIV(frdiv); /* Divide ERCLK / 256 for FLL reference. */
- /* Note: FLL reference frequency must be 31.25 kHz to 39.0625 kHz. */
-
- MCG->C4 &= ~(MCG_C4_DMX32 | MCG_C4_DRST_DRS_MASK);
- MCG->C6 = 0; /* PLLS=0: Select FLL as MCG source, not PLL */
-
- /* (3) Once configuration is set, wait for MCG mode change. */
-
- /* From KL25P80M48SF0RM section 24.5.31: */
- /* (1)(c) Loop until S[OSCINIT0] is 1, indicating the
- crystal selected by C2[EREFS0] has been initialized. */
- while ((MCG->S & MCG_S_OSCINIT0) == 0)
- ;
- /* (1)(d) Loop until S[IREFST] is 0, indicating the
- external reference is the current reference clock source. */
- while ((MCG->S & MCG_S_IREFST) != 0)
- ; /* Wait until external reference clock is FLL reference. */
- /* (1)(e) Loop until S[CLKST] is 2'b10, indicating
- the external reference clock is selected to feed MCGOUTCLK. */
- while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_ERCLK)
- ; /* Wait until external reference clock has been selected. */
-
- /* --- MCG mode: FBE (FLL bypassed, external crystal) ---
- Now the MCG is in FBE mode.
- Although the FLL is bypassed, it is still on. */
-
- /* (2) Then configure C5[PRDIV0] to generate the
- correct PLL reference frequency. */
- #define KINETIS_PLLIN_FREQUENCY 2000000UL
- /* TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz */
- /* PLL External Reference Divide by ... */
- MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
- /* (3) Then from FBE transition to PBE mode. */
- /* (3)(b) C6[PLLS]=1 to select PLL. */
- /* (3)(b) C6[VDIV0]= PLLIN MHz * i = PLLCLK MHz. */
- /* Config PLL output to match KINETIS_SYSCLK_FREQUENCY
- * TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match */
- for(i = 24; i < 56; i++) {
- if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY)) {
- /* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
- MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
- break;
- }
- }
- if(i>=56) /* Config PLL for 96 MHz output as default setting */
- MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
-
- /* (3)(d) Loop until S[PLLST], indicating PLL
- is the PLLS clock source. */
- while ((MCG->S & MCG_S_PLLST) == 0)
- ; /* wait until PLL is the PLLS clock source. */
- /* (3)(e) Loop until S[LOCK0] is set, indicating the PLL has acquired lock. */
- /* PLL selected as MCG source. VDIV0=00000 (Multiply=24). */
- while ((MCG->S & MCG_S_LOCK0) == 0)
- ; /* wait until PLL locked */
-
- /* --- MCG mode: PBE (PLL bypassed, external crystal) --- */
-
- /* Set the PLL dividers for the different clocks */
- /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
- * OUTDIV1 (divider for core/system and bus/flash clock)
- * OUTDIV4 (additional divider for bus/flash clock)
- * - these are computed in .h */
- SIM->CLKDIV1 =
- SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
- SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
-
- SIM->SOPT2 =
- SIM_SOPT2_TPMSRC(1) | /* MCGFLLCLK clock or MCGPLLCLK/2 */
- SIM_SOPT2_PLLFLLSEL; /* PLLFLLSEL=MCGPLLCLK/2 */
-
- /* (4) Transition from PBE mode to PEE mode. */
- /* (4)(a) C1[CLKS] = 2'b00 to select PLL output as system clock source. */
- // Switch to PEE mode
- // Select PLL output (CLKS=0)
- // FLL external reference divider (FRDIV) already set
- // External reference clock for FLL (IREFS=0)
- MCG->C1 = MCG_C1_CLKS(0);
- /* (4)(b) Loop until S[CLKST] are 2'b11, indicating the PLL output is selected for MCGOUTCLK. */
- while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL)
- ; /* wait until clock switched to PLL output */
-
- /* --- MCG mode: PEE (PLL enabled, external crystal) --- */
-
-#else /* KINETIS_MCG_MODE != KINETIS_MCG_MODE_PEE */
-#error Unimplemented KINETIS_MCG_MODE
-#endif /* KINETIS_MCG_MODE != KINETIS_MCG_MODE_PEE */
-
-#endif /* KINETIS_HAS_MCG_LITE */
-
-#endif /* !KINETIS_NO_INIT */
-}
-
-/**
- * @brief Platform early initialization.
- * @note All the involved constants come from the file @p board.h.
- * @note This function is meant to be invoked early during the system
- * initialization, it is usually invoked from the file
- * @p board.c.
- *
- * @special
- */
-void platform_early_init(void) {
-
-}
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_lld.h deleted file mode 100644 index d16e13f..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_lld.h +++ /dev/null @@ -1,316 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/hal_lld.h
- * @brief Kinetis KL2x HAL subsystem low level driver header.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef HAL_LLD_H_
-#define HAL_LLD_H_
-
-#include "kl2xz.h"
-#include "kinetis_registry.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @name Platform identification
- * @{
- */
-#define PLATFORM_NAME "Kinetis"
-/** @} */
-
-#if KINETIS_HAS_MCG_LITE
-/* MCU only has MCG_Lite */
-
-/**
- * @name Internal clock sources
- * @{
- */
-#define KINETIS_HIRC 48000000 /**< High-frequency internal reference clock (USB recovery). */
-#define KINETIS_LIRC_8 8000000 /**< Low-frequency internal reference clock (faster). */
-#define KINETIS_LIRC_2 2000000 /**< Low-frequency internal reference clock (slower). */
-/** @} */
-
-/**
- * @name MCG modes of operation
- * @{
- */
-#define KINETIS_MCGLITE_MODE_LIRC8M 1 /**< Low frequency internal reference mode (8MHz). */
-#define KINETIS_MCGLITE_MODE_LIRC2M 2 /**< Low frequency internal reference mode (2MHz). */
-#define KINETIS_MCGLITE_MODE_HIRC 3 /**< High frequency internal reference mode (with optional USB recovery). */
-#define KINETIS_MCGLITE_MODE_EXT 4 /**< External reference mode. */
-/** @} */
-
-#else /* KINETIS_HAS_MCG_LITE */
-/* MCU has full blown MCG */
-
-/**
- * @name Internal clock sources
- * @{
- */
-#define KINETIS_IRCLK_F 4000000 /**< Fast internal reference clock, factory trimmed. */
-#define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
-/** @} */
-
-/**
- * @name MCG modes of operation
- * @{
- */
-#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
-#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
-#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
-#define KINETIS_MCG_MODE_FBE 4 /**< FLL Bypassed External. */
-#define KINETIS_MCG_MODE_PEE 5 /**< PLL Engaged External. */
-#define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
-#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
-#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
-/** @} */
-
-#endif /* KINETIS_HAS_MCG_LITE */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief Disables the MCG/system clock initialization in the HAL.
- */
-#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
-#define KINETIS_NO_INIT FALSE
-#endif
-
-/**
- * @brief MCG mode selection.
- */
-#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
-#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
-#endif
-
-#if !defined(KINETIS_MCGLITE_MODE) || defined(__DOXYGEN__)
-#define KINETIS_MCGLITE_MODE KINETIS_MCGLITE_MODE_HIRC
-#endif
-
-/**
- * @brief MCU PLL clock frequency.
- */
-#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_PLLCLK_FREQUENCY 96000000UL
-#endif
-
-/**
- * @brief Clock divider for core/system and bus/flash clocks (OUTDIV1).
- * @note The allowed range is 1...16.
- * @note The default value is calculated for a 48 MHz system clock
- * from a 96 MHz PLL output.
- */
-#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
- #if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
- #define KINETIS_CLKDIV1_OUTDIV1 (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
- #else
- #define KINETIS_CLKDIV1_OUTDIV1 2
- #endif
-#endif
-
-/**
- * @brief Additional clock divider bus/flash clocks (OUTDIV4).
- * @note The allowed range is 1...8.
- * @note This divider is on top of the OUTDIV1 divider.
- * @note The default value is calculated for 24 MHz bus/flash clocks
- * from a 96 MHz PLL output and 48 MHz core/system clock.
- */
-#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
- #if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
- #define KINETIS_CLKDIV1_OUTDIV4 ((KINETIS_PLLCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV1)/KINETIS_BUSCLK_FREQUENCY)
- #else
- #define KINETIS_CLKDIV1_OUTDIV4 2
- #endif
-#endif
-
-/**
- * @brief FLL DCO tuning enable for 32.768 kHz reference.
- * @note Set to 1 for fine-tuning DCO for maximum frequency with
- * a 32.768 kHz reference.
- * @note The default value is for a 32.768 kHz external crystal.
- */
-#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
-#define KINETIS_MCG_FLL_DMX32 1
-#endif
-
-/**
- * @brief FLL DCO range selection.
- * @note The allowed range is 0...3.
- * @note The default value is calculated for 48 MHz FLL output
- * from a 32.768 kHz external crystal.
- * (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
- *
- */
-#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
-#define KINETIS_MCG_FLL_DRS 2
-#endif
-
-/**
- * @brief MCU system/core clock frequency.
- */
-#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_SYSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
-#endif
-
-/**
- * @brief MCU bus/flash clock frequency.
- */
-#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
-#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
-#endif
-
-/**
- * @brief UART0 clock frequency.
- * @note The default value is based on 96 MHz PLL/2 source.
- * If you use a different source, such as the FLL,
- * you must set this properly.
- */
-#if !defined(KINETIS_UART0_CLOCK_FREQ) || defined(__DOXYGEN__)
-#define KINETIS_UART0_CLOCK_FREQ KINETIS_SYSCLK_FREQUENCY
-#endif
-
-/**
- * @brief UART0 clock source.
- * @note The default value is to use PLL/2 or FLL source.
- */
-#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
-#define KINETIS_UART0_CLOCK_SRC 1
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !defined(KINETIS_SYSCLK_FREQUENCY)
-#error KINETIS_SYSCLK_FREQUENCY must be defined
-#endif
-
-#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
-#error KINETIS_SYSCLK_FREQUENCY out of range
-#endif
-
-#if !defined(KINETIS_BUSCLK_FREQUENCY)
-#error KINETIS_BUSCLK_FREQUENCY must be defined
-#endif
-
-#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
-#error KINETIS_BUSCLK_FREQUENCY out of range
-#endif
-
-#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
- #error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
- KINETIS_SYSCLK_FREQUENCY
-#endif
-
-
-#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
- KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
- #error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
-#endif
-
-#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
- KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
-#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
-#endif
-
-#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
-#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
-#endif
-
-#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
-#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type representing a system clock frequency.
- */
-typedef uint32_t halclock_t;
-
-/**
- * @brief Type of the realtime free counter value.
- */
-typedef uint32_t halrtcnt_t;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the current value of the system free running counter.
- * @note This service is implemented by returning the content of the
- * DWT_CYCCNT register.
- *
- * @return The value of the system free running counter of
- * type halrtcnt_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_value() 0
-
-/**
- * @brief Realtime counter frequency.
- * @note The DWT_CYCCNT register is incremented directly by the system
- * clock so this function returns STM32_HCLK.
- *
- * @return The realtime counter frequency of type halclock_t.
- *
- * @notapi
- */
-#define hal_lld_get_counter_frequency() 0
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#include "nvic.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void hal_lld_init(void);
- void kl2x_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.c deleted file mode 100644 index 2f56216..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.c +++ /dev/null @@ -1,388 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014 Adam J. Porter
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/pwm_lld.c
- * @brief KINETIS PWM subsystem low level driver source.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief PWMD1 driver identifier.
- * @note The driver PWMD1 allocates the timer TPM0 when enabled.
- */
-#if KINETIS_PWM_USE_TPM0 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief PWMD2 driver identifier.
- * @note The driver PWMD2 allocates the timer TPM1 when enabled.
- */
-#if KINETIS_PWM_USE_TPM1 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief PWMD3 driver identifier.
- * @note The driver PWMD3 allocates the timer TPM2 when enabled.
- */
-#if KINETIS_PWM_USE_TPM2 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
- uint32_t sr;
-
- sr = pwmp->tpm->STATUS;
- pwmp->tpm->STATUS = 0xFFFFFFFF;
-
- if (((sr & TPMx_STATUS_TOF) != 0) &&
- (pwmp->config->callback != NULL))
- pwmp->config->callback(pwmp);
- if (((sr & TPMx_STATUS_CH0F) != 0) &&
- (pwmp->config->channels[0].callback != NULL))
- pwmp->config->channels[0].callback(pwmp);
- if (((sr & TPMx_STATUS_CH1F) != 0) &&
- (pwmp->config->channels[1].callback != NULL))
- pwmp->config->channels[1].callback(pwmp);
- if (((sr & TPMx_STATUS_CH2F) != 0) &&
- (pwmp->config->channels[2].callback != NULL))
- pwmp->config->channels[2].callback(pwmp);
- if (((sr & TPMx_STATUS_CH3F) != 0) &&
- (pwmp->config->channels[3].callback != NULL))
- pwmp->config->channels[3].callback(pwmp);
- if (((sr & TPMx_STATUS_CH4F) != 0) &&
- (pwmp->config->channels[4].callback != NULL))
- pwmp->config->channels[4].callback(pwmp);
- if (((sr & TPMx_STATUS_CH5F) != 0) &&
- (pwmp->config->channels[5].callback != NULL))
- pwmp->config->channels[5].callback(pwmp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if KINETIS_PWM_USE_TPM0
-/**
- * @brief TPM0 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_TPM0_IRQ_VECTOR) {
-
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD1);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_PWM_USE_TPM0 */
-
-#if KINETIS_PWM_USE_TPM1
-/**
- * @brief TPM1 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_TPM1_IRQ_VECTOR) {
-
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD2);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_PWM_USE_TPM1 */
-
-#if KINETIS_PWM_USE_TPM2
-/**
- * @brief TPM2 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_TPM2_IRQ_VECTOR) {
-
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD3);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_PWM_USE_TPM2 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-
-#if KINETIS_PWM_USE_TPM0
- pwmObjectInit(&PWMD1);
- PWMD1.channels = KINETIS_TPM0_CHANNELS;
- PWMD1.tpm = TPM0;
-#endif
-
-#if KINETIS_PWM_USE_TPM1
- pwmObjectInit(&PWMD2);
- PWMD2.channels = KINETIS_TPM1_CHANNELS;
- PWMD2.tpm = TPM1;
-#endif
-
-#if KINETIS_PWM_USE_TPM2
- pwmObjectInit(&PWMD3);
- PWMD3.channels = KINETIS_TPM2_CHANNELS;
- PWMD3.tpm = TPM2;
-#endif
-}
-
-/**
- * @brief Configures and activates the PWM peripheral.
- * @note Starting a driver that is already in the @p PWM_READY state
- * disables all the active channels.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
- uint32_t psc;
- int i;
-
- if (pwmp->state == PWM_STOP) {
- /* Clock activation and timer reset.*/
-#if KINETIS_PWM_USE_TPM0
- if (&PWMD1 == pwmp) {
- SIM->SCGC6 |= SIM_SCGC6_TPM0;
- nvicEnableVector(TPM0_IRQn, KINETIS_PWM_TPM0_IRQ_PRIORITY);
- }
-#endif
-
-#if KINETIS_PWM_USE_TPM1
- if (&PWMD2 == pwmp) {
- SIM->SCGC6 |= SIM_SCGC6_TPM1;
- nvicEnableVector(TPM1_IRQn, KINETIS_PWM_TPM1_IRQ_PRIORITY);
- }
-#endif
-
-#if KINETIS_PWM_USE_TPM2
- if (&PWMD3 == pwmp) {
- SIM->SCGC6 |= SIM_SCGC6_TPM2;
- nvicEnableVector(TPM2_IRQn, KINETIS_PWM_TPM2_IRQ_PRIORITY);
- }
-#endif
- }
-
- /* Disable LPTPM counter.*/
- pwmp->tpm->SC = 0;
- /* Clear count register.*/
- pwmp->tpm->CNT = 0;
-
- /* Prescaler value calculation.*/
- psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency);
- /* Prescaler must be power of two between 1 and 128.*/
- osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency");
- /* Prescaler register value determination.
- Prescaler register value conveniently corresponds to bit position,
- i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/
- for (i = 0; i < 8; i++) {
- if (psc == (1UL << i)) {
- break;
- }
- }
- /* Set prescaler and clock mode.
- This also sets the following:
- CPWM up-counting mode
- Timer overflow interrupt disabled
- DMA disabled.*/
- pwmp->tpm->SC = TPMx_SC_CMOD_LPTPM_CLK | i;
- /* Configure period.*/
- pwmp->tpm->MOD = pwmp->period - 1;
-}
-
-/**
- * @brief Deactivates the PWM peripheral.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
- /* If in ready state then disables the PWM clock.*/
- if (pwmp->state == PWM_READY) {
-#if KINETIS_PWM_USE_TPM0
- if (&PWMD1 == pwmp) {
- SIM->SCGC6 &= ~SIM_SCGC6_TPM0;
- nvicDisableVector(TPM0_IRQn);
- }
-#endif
-
-#if KINETIS_PWM_USE_TPM1
- if (&PWMD2 == pwmp) {
- SIM->SCGC6 &= ~SIM_SCGC6_TPM1;
- nvicDisableVector(TPM1_IRQn);
- }
-#endif
-
-#if KINETIS_PWM_USE_TPM2
- if (&PWMD3 == pwmp) {
- SIM->SCGC6 &= ~SIM_SCGC6_TPM2;
- nvicDisableVector(TPM2_IRQn);
- }
-#endif
- /* Disable LPTPM counter.*/
- pwmp->tpm->SC = 0;
- pwmp->tpm->MOD = 0;
- }
-}
-
-
-/**
- * @brief Enables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is active using the specified configuration.
- * @note The function has effect at the next cycle start.
- * @note Channel notification is not enabled.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- * @param[in] width PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width) {
- uint32_t mode = TPMx_CnSC_MSB; /* Edge-aligned PWM mode.*/
-
- switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
- case PWM_OUTPUT_ACTIVE_HIGH:
- mode |= TPMx_CnSC_ELSB;
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
- mode |= TPMx_CnSC_ELSA;
- break;
- }
-
- if (pwmp->tpm->C[channel].SC & TPMx_CnSC_CHIE)
- mode |= TPMx_CnSC_CHIE;
-
- pwmp->tpm->C[channel].SC = mode;
- pwmp->tpm->C[channel].V = width;
-}
-
-/**
- * @brief Disables a PWM channel and its notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is disabled and its output line returned to the
- * idle state.
- * @note The function has effect at the next cycle start.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
- pwmp->tpm->C[channel].SC = 0;
- pwmp->tpm->C[channel].V = 0;
-}
-
-/**
- * @brief Enables the periodic activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @note If the notification is already enabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
-
- pwmp->tpm->SC |= TPMx_SC_TOIE;
-}
-
-/**
- * @brief Disables the periodic activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @note If the notification is already disabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
-
- pwmp->tpm->SC &= ~TPMx_SC_TOIE;
-}
-
-/**
- * @brief Enables a channel de-activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @pre The channel must have been activated using @p pwmEnableChannel().
- * @note If the notification is already enabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel) {
-
- pwmp->tpm->C[channel].SC |= TPMx_CnSC_CHIE;
-}
-
-/**
- * @brief Disables a channel de-activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @pre The channel must have been activated using @p pwmEnableChannel().
- * @note If the notification is already disabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel) {
-
- pwmp->tpm->C[channel].SC &= ~TPMx_CnSC_CHIE;
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.h deleted file mode 100644 index 64ff9ee..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.h +++ /dev/null @@ -1,305 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Adam J. Porter
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/pwm_lld.h
- * @brief KINETIS PWM subsystem low level driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef HAL_PWM_LLD_H_
-#define HAL_PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-#if !defined(KINETIS_PWM_USE_TPM0)
-#define KINETIS_PWM_USE_TPM0 FALSE
-#endif
-#if !defined(KINETIS_PWM_USE_TPM1)
-#define KINETIS_PWM_USE_TPM1 FALSE
-#endif
-#if !defined(KINETIS_PWM_USE_TPM2)
-#define KINETIS_PWM_USE_TPM2 FALSE
-#endif
-
-/**
- * @brief Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS 6
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief If advanced timer features switch.
- * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
- * enabled.
- * @note The default is @p TRUE.
- */
-#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
-#define KINETIS_PWM_USE_ADVANCED FALSE
-#endif
-
-/**
- * @brief TPM0 interrupt priority level setting.
- * @note The default is 2.
- */
-#if !defined(KINETIS_PWM_TPM0_IRQ_PRIORITY)|| defined(__DOXYGEN__)
-#define KINETIS_PWM_TPM0_IRQ_PRIORITY 2
-#endif
-
-/**
- * @brief TPM1 interrupt priority level setting.
- * @note The default is 2.
- */
-#if !defined(KINETIS_PWM_TPM1_IRQ_PRIORITY)|| defined(__DOXYGEN__)
-#define KINETIS_PWM_TPM1_IRQ_PRIORITY 2
-#endif
-
-/**
- * @brief TPM2 interrupt priority level setting.
- * @note The default is 2.
- */
-#if !defined(KINETIS_PWM_TPM2_IRQ_PRIORITY)|| defined(__DOXYGEN__)
-#define KINETIS_PWM_TPM2_IRQ_PRIORITY 2
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Configuration checks. */
-/*===========================================================================*/
-
-#if KINETIS_PWM_USE_TPM0 && !KINETIS_HAS_TPM0
-#error "TPM0 not present in the selected device"
-#endif
-
-#if KINETIS_PWM_USE_TPM1 && !KINETIS_HAS_TPM1
-#error "TPM1 not present in the selected device"
-#endif
-
-#if KINETIS_PWM_USE_TPM2 && !KINETIS_HAS_TPM2
-#error "TPM2 not present in the selected device"
-#endif
-
-#if !KINETIS_PWM_USE_TPM0 && !KINETIS_PWM_USE_TPM1 && !KINETIS_PWM_USE_TPM2
-#error "PWM driver activated but no TPM peripheral assigned"
-#endif
-
-#if KINETIS_PWM_USE_TPM0 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM0_IRQ_PRIORITY"
-#endif
-
-#if KINETIS_PWM_USE_TPM1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM1_IRQ_PRIORITY"
-#endif
-
-#if KINETIS_PWM_USE_TPM2 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM2_IRQ_PRIORITY"
-#endif
-
-#if !defined(KINETIS_TPM0_IRQ_VECTOR)
-#error "KINETIS_TPM0_IRQ_VECTOR not defined"
-#endif
-
-#if !defined(KINETIS_TPM1_IRQ_VECTOR)
-#error "KINETIS_TPM1_IRQ_VECTOR not defined"
-#endif
-
-#if !defined(KINETIS_TPM2_IRQ_VECTOR)
-#error "KINETIS_TPM2_IRQ_VECTOR not defined"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a PWM mode.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief Type of a PWM channel.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief Type of a channels mask.
- */
-typedef uint32_t pwmchnmsk_t;
-
-/**
- * @brief Type of a PWM counter.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief Type of a PWM driver channel configuration structure.
- */
-typedef struct {
- /**
- * @brief Channel active logic level.
- */
- pwmmode_t mode;
- /**
- * @brief Channel callback pointer.
- * @note This callback is invoked on the channel compare event. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief Type of a PWM driver configuration structure.
- */
-typedef struct {
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- uint32_t frequency;
- /**
- * @brief PWM period in ticks.
- * @note The low level can use assertions in order to catch invalid
- * period specifications.
- */
- pwmcnt_t period;
- /**
- * @brief Periodic callback pointer.
- * @note This callback is invoked on PWM counter reset. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /**
- * @brief Channels configurations.
- */
- PWMChannelConfig channels[PWM_CHANNELS];
- /* End of the mandatory fields.*/
-} PWMConfig;
-
-/**
- * @brief Structure representing a PWM driver.
- */
-struct PWMDriver {
- /**
- * @brief Driver state.
- */
- pwmstate_t state;
- /**
- * @brief Current driver configuration data.
- */
- const PWMConfig *config;
- /**
- * @brief Current PWM period in ticks.
- */
- pwmcnt_t period;
- /**
- * @brief Mask of the enabled channels.
- */
- pwmchnmsk_t enabled;
- /**
- * @brief Number of channels in this instance.
- */
- pwmchannel_t channels;
-#if defined(PWM_DRIVER_EXT_FIELDS)
- PWM_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the TPM registers block.
- */
- TPM_TypeDef *tpm;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- * been activated using @p pwmStart().
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The PWM unit period is changed to the new value.
- * @note The function has effect at the next cycle start.
- * @note If a period is specified that is shorter than the pulse width
- * programmed in one of the channels then the behavior is not
- * guaranteed.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] period new cycle time in ticks
- *
- * @notapi
- */
-#define pwm_lld_change_period(pwmp, period) \
- ((pwmp)->tpm->MOD = ((period) - 1))
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if KINETIS_PWM_USE_TPM0 || defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-#if KINETIS_PWM_USE_TPM1 || defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-#if KINETIS_PWM_USE_TPM2 || defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void pwm_lld_init(void);
- void pwm_lld_start(PWMDriver *pwmp);
- void pwm_lld_stop(PWMDriver *pwmp);
- void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width);
- void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
- void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
- void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
- void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel);
- void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* HAL_PWM_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/kinetis_registry.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/kinetis_registry.h deleted file mode 100644 index 49b1ec8..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/kinetis_registry.h +++ /dev/null @@ -1,258 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014 Derek Mulcahy
- (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/kinetis_registry.h
- * @brief KL2x capabilities registry.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef KINETIS_REGISTRY_H_
-#define KINETIS_REGISTRY_H_
-
-#if !defined(KL2x) || defined(__DOXYGEN__)
-#define KL2x
-#endif
-
-/*===========================================================================*/
-/* Platform capabilities. */
-/*===========================================================================*/
-
-/**
- * @name KL2x capabilities
- * @{
- */
-
-/*===========================================================================*/
-/* Common features */
-/*===========================================================================*/
-
-/**
- * @brief Maximum system and core clock (f_SYS) frequency.
- */
-#define KINETIS_SYSCLK_MAX 48000000
-
-/**
- * @brief Maximum bus clock (f_BUS) frequency.
- */
-#define KINETIS_BUSCLK_MAX 24000000
-
-/* ADC attributes.*/
-#define KINETIS_HAS_ADC0 TRUE
-#define KINETIS_ADC0_IRQ_VECTOR Vector7C
-#define KINETIS_HAS_ADC1 FALSE
-
-/* DMA attributes.*/
-#define KINETIS_DMA0_IRQ_VECTOR Vector40
-#define KINETIS_DMA1_IRQ_VECTOR Vector44
-#define KINETIS_DMA2_IRQ_VECTOR Vector48
-#define KINETIS_DMA3_IRQ_VECTOR Vector4C
-#define KINETIS_HAS_DMA_ERROR_IRQ FALSE
-
-/* GPT attributes.*/
-#define KINETIS_PIT_IRQ_VECTOR Vector98
-#define KINETIS_HAS_PIT_COMMON_IRQ TRUE
-#define KINETIS_HAS_PIT0 TRUE
-#define KINETIS_HAS_PIT1 TRUE
-#define KINETIS_HAS_PIT2 FALSE
-#define KINETIS_HAS_PIT3 FALSE
-
-/* I2C attributes.*/
-#define KINETIS_HAS_I2C0 TRUE
-#define KINETIS_I2C0_IRQ_VECTOR Vector60
-#define KINETIS_HAS_I2C1 TRUE
-#define KINETIS_I2C1_IRQ_VECTOR Vector64
-
-/* Serial attributes */
-#define KINETIS_HAS_SERIAL0 TRUE
-#define KINETIS_SERIAL0_IRQ_VECTOR Vector70
-#define KINETIS_HAS_SERIAL1 TRUE
-#define KINETIS_SERIAL1_IRQ_VECTOR Vector74
-#define KINETIS_HAS_SERIAL2 TRUE
-#define KINETIS_SERIAL2_IRQ_VECTOR Vector78
-#define KINETIS_HAS_SERIAL_ERROR_IRQ FALSE
-
-/* SPI attributes.*/
-#define KINETIS_HAS_SPI0 TRUE
-#define KINETIS_SPI0_IRQ_VECTOR Vector68
-#define KINETIS_HAS_SPI1 TRUE
-#define KINETIS_SPI1_IRQ_VECTOR Vector6C
-
-/* TPM attributes.*/
-#define KINETIS_HAS_TPM0 TRUE
-#define KINETIS_TPM0_CHANNELS 6
-#define KINETIS_TPM0_IRQ_VECTOR Vector84
-#define KINETIS_HAS_TPM1 TRUE
-#define KINETIS_TPM1_CHANNELS 2
-#define KINETIS_TPM1_IRQ_VECTOR Vector88
-#define KINETIS_HAS_TPM2 TRUE
-#define KINETIS_TPM2_CHANNELS 2
-#define KINETIS_TPM2_IRQ_VECTOR Vector8C
-
-/* USB attributes.*/
-#define KINETIS_HAS_USB TRUE
-#define KINETIS_USB_IRQ_VECTOR VectorA0
-
-/* FTFA attributes.*/
-#define KINETIS_FTFA_IRQ_VECTOR Vector54
-
-/* LPTMR attributes */
-#define KINETIS_LPTMR0_IRQ_VECTOR VectorB0
-
-/*===========================================================================*/
-/* KL25 */
-/*===========================================================================*/
-#if defined(KL25) || defined(__DOXYGEN__)
-
-/* DAC attributes.*/
-#define KINETIS_HAS_DAC0 TRUE
-#define KINTEIS_DAC0_IRQ_VECTOR VectorA4
-
-/* EXT attributes.*/
-#define KINETIS_PORTA_IRQ_VECTOR VectorB8
-#define KINETIS_PORTD_IRQ_VECTOR VectorBC
-#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
-#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
-#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
-
-/* I2S attributes.*/
-#define KINETIS_HAS_I2S0 FALSE
-
-/* MCG attributes.*/
-#define KINETIS_HAS_MCG_LITE FALSE
-
-/* Serial attributes */
-#define KINETIS_SERIAL0_IS_UARTLP TRUE
-#define KINETIS_SERIAL0_IS_LPUART FALSE
-#define KINETIS_SERIAL1_IS_LPUART FALSE
-
-/* USB attributes.*/
-#define KINETIS_USB0_IS_USBOTG TRUE
-#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
-
-/*===========================================================================*/
-/* KL26 */
-/*===========================================================================*/
-#elif defined(KL26) /* defined(KL25) */
-
-/* DAC attributes.*/
-#define KINETIS_HAS_DAC0 TRUE
-#define KINTEIS_DAC0_IRQ_VECTOR VectorA4
-
-/* EXT attributes.*/
-#define KINETIS_PORTA_IRQ_VECTOR VectorB8
-/* Common IRQ vector for PORTC and PORTD */
-#define KINETIS_PORTD_IRQ_VECTOR VectorBC
-#define KINETIS_EXT_HAS_COMMON_CD_IRQ TRUE
-#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
-#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
-
-/* I2S attributes.*/
-#define KINETIS_HAS_I2S0 TRUE
-#define KINETIS_I2S0_IRQ_VECTOR Vector9C
-
-/* MCG attributes.*/
-#define KINETIS_HAS_MCG_LITE FALSE
-
-/* Serial attributes */
-#define KINETIS_SERIAL0_IS_UARTLP TRUE
-#define KINETIS_SERIAL0_IS_LPUART FALSE
-#define KINETIS_SERIAL1_IS_LPUART FALSE
-
-/* USB attributes.*/
-#define KINETIS_USB0_IS_USBOTG TRUE
-#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
-
-/*===========================================================================*/
-/* KL27 */
-/*===========================================================================*/
-#elif defined(KL27Zxxx) || defined(KL27Zxx) /* defined(KL26) */
-
-#if !defined(KL27)
-#define KL27
-#endif
-
-/* MCG attributes.*/
-#define KINETIS_HAS_MCG_LITE TRUE
-
-/* Note: on this device, SERIAL2 IRQ is alternatively FlexIO IRQ. */
-/* Serial attributes */
-#define KINETIS_SERIAL0_IS_UARTLP FALSE
-#define KINETIS_SERIAL0_IS_LPUART TRUE
-#define KINETIS_SERIAL1_IS_LPUART TRUE
-
-/* USB attributes.*/
-#define KINETIS_USB0_IS_USBOTG FALSE
-#define KINETIS_HAS_USB_CLOCK_RECOVERY TRUE
-
-/*===========================================================================*/
-/* KL27Zxxx (MKL27Z128* and MKL27Z256*) specific */
-/*===========================================================================*/
-#if defined(KL27Zxxx)
-
-/* DAC attributes.*/
-#define KINETIS_HAS_DAC0 TRUE
-#define KINTEIS_DAC0_IRQ_VECTOR VectorA4
-
-/* EXT attributes.*/
-#define KINETIS_PORTA_IRQ_VECTOR VectorB8
-/* Common IRQ vector for PORTC and PORTD */
-#define KINETIS_PORTD_IRQ_VECTOR VectorBC
-#define KINETIS_EXT_HAS_COMMON_CD_IRQ TRUE
-#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
-#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
-
-/* I2S attributes.*/
-#define KINETIS_HAS_I2S0 TRUE
-#define KINETIS_I2S0_IRQ_VECTOR Vector9C
-
-/*===========================================================================*/
-/* KL27Zxx (MKL27Z32* and MKL27Z264*) specific */
-/*===========================================================================*/
-#elif defined(KL27Zxx) /* defined(KL27Zxxx) */
-
-/* Has CRC module */
-/* Does not have USB voltage regulator */
-/* Does have KEEP_ALIVE USB feature */
-
-/* DAC attributes.*/
-#define KINETIS_HAS_DAC0 FALSE
-
-/* EXT attributes.*/
-#define KINETIS_PORTA_IRQ_VECTOR VectorB8
-/* Common IRQ vector for PORTB to PORTE */
-#define KINETIS_PORTD_IRQ_VECTOR VectorBC
-#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
-#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ TRUE
-#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
-
-/* I2S attributes.*/
-#define KINETIS_HAS_I2S0 FALSE
-
-#endif /* defined(KL27Zxx) */
-
-#else /* ! (KL25 || KL26 || KL27) */
-#error MCU type not described in kinetis_registry
-#endif /* KL2Y */
-
-/** @} */
-
-#endif /* KINETIS_REGISTRY_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/platform.mk b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/platform.mk deleted file mode 100644 index dda7a6d..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/platform.mk +++ /dev/null @@ -1,17 +0,0 @@ -# List of all platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/hal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_pal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_serial_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x \
- ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_adc_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_adc_lld.c deleted file mode 100644 index 56ae4c3..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_adc_lld.c +++ /dev/null @@ -1,259 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014 Derek Mulcahy
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/LLD/adc_lld.c
- * @brief KINETIS ADC subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#define ADC_CHANNEL_MASK 0x1f
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief ADC1 driver identifier.*/
-#if KINETIS_ADC_USE_ADC0 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-static void calibrate(ADCDriver *adcp) {
-
- /* Clock Divide by 8, Use Bus Clock Div 2 */
- /* At 48MHz this results in ADCCLK of 48/8/2 == 3MHz */
- adcp->adc->CFG1 = ADCx_CFG1_ADIV(ADCx_CFG1_ADIV_DIV_8) |
- ADCx_CFG1_ADICLK(ADCx_CFG1_ADIVCLK_BUS_CLOCK_DIV_2);
-
- /* Use software trigger and disable DMA etc. */
- adcp->adc->SC2 = 0;
-
- /* Enable Hardware Average, Average 32 Samples, Calibrate */
- adcp->adc->SC3 = ADCx_SC3_AVGE |
- ADCx_SC3_AVGS(ADCx_SC3_AVGS_AVERAGE_32_SAMPLES) |
- ADCx_SC3_CAL;
-
- /* FIXME: May take several ms. Use an interrupt instead of busy wait */
- /* Wait for calibration completion */
- while (!(adcp->adc->SC1A & ADCx_SC1n_COCO))
- ;
-
- uint16_t gain = ((adcp->adc->CLP0 + adcp->adc->CLP1 + adcp->adc->CLP2 +
- adcp->adc->CLP3 + adcp->adc->CLP4 + adcp->adc->CLPS) / 2) | 0x8000;
- adcp->adc->PG = gain;
-
- gain = ((adcp->adc->CLM0 + adcp->adc->CLM1 + adcp->adc->CLM2 +
- adcp->adc->CLM3 + adcp->adc->CLM4 + adcp->adc->CLMS) / 2) | 0x8000;
- adcp->adc->MG = gain;
-
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if KINETIS_ADC_USE_ADC0 || defined(__DOXYGEN__)
-/**
- * @brief ADC interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_ADC0_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
- ADCDriver *adcp = &ADCD1;
-
- /* Disable Interrupt, Disable Channel */
- adcp->adc->SC1A = ADCx_SC1n_ADCH(ADCx_SC1n_ADCH_DISABLED);
-
- /* Read the sample into the buffer */
- adcp->samples[adcp->current_index++] = adcp->adc->RA;
-
- bool more = true;
-
- /* At the end of the buffer then we may be finished */
- if (adcp->current_index == adcp->number_of_samples) {
- /* We are never finished in circular mode */ - more = ADCD1.grpp->circular; - - _adc_isr_full_code(&ADCD1);
-
- adcp->current_index = 0;
-
- }
-
- if (more) {
-
- /* Signal half completion in circular mode. */
- if (ADCD1.grpp->circular &&
- (adcp->current_index == (adcp->number_of_samples / 2))) {
-
- _adc_isr_half_code(&ADCD1);
- }
-
- /* Skip to the next channel */
- do {
- adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK;
- } while (((1 << adcp->current_channel) & adcp->grpp->channel_mask) == 0);
-
- /* Enable Interrupt, Select the Channel */
- adcp->adc->SC1A = ADCx_SC1n_AIEN | ADCx_SC1n_ADCH(adcp->current_channel);
- }
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-#if KINETIS_ADC_USE_ADC0
- /* Driver initialization.*/
- adcObjectInit(&ADCD1);
-#endif
-
- /* The shared vector is initialized on driver initialization and never
- disabled.*/
- nvicEnableVector(ADC0_IRQn, KINETIS_ADC_IRQ_PRIORITY);
-}
-
-/**
- * @brief Configures and activates the ADC peripheral.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
- /* If in stopped state then enables the ADC clock.*/
- if (adcp->state == ADC_STOP) {
- SIM->SCGC6 |= SIM_SCGC6_ADC0;
-
-#if KINETIS_ADC_USE_ADC0
- if (&ADCD1 == adcp) {
- adcp->adc = ADC0;
- if (adcp->config->calibrate) {
- calibrate(adcp);
- }
- }
-#endif /* KINETIS_ADC_USE_ADC0 */
- }
-}
-
-/**
- * @brief Deactivates the ADC peripheral.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
- /* If in ready state then disables the ADC clock.*/
- if (adcp->state == ADC_READY) {
- SIM->SCGC6 &= ~SIM_SCGC6_ADC0;
-
-#if KINETIS_ADC_USE_ADC0
- if (&ADCD1 == adcp) {
- /* Disable Interrupt, Disable Channel */
- adcp->adc->SC1A = ADCx_SC1n_ADCH(ADCx_SC1n_ADCH_DISABLED);
- }
-#endif
- }
-}
-
-/**
- * @brief Starts an ADC conversion.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
- const ADCConversionGroup *grpp = adcp->grpp;
-
- /* Enable the Bandgap Buffer if channel mask includes BANDGAP */
- if (grpp->channel_mask & ADC_BANDGAP) {
- PMC->REGSC |= PMC_REGSC_BGBE;
- }
-
- adcp->number_of_samples = adcp->depth * grpp->num_channels;
- adcp->current_index = 0;
-
- /* Skip to the next channel */
- adcp->current_channel = 0;
- while (((1 << adcp->current_channel) & grpp->channel_mask) == 0) {
- adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK;
- }
-
- /* Set clock speed and conversion size */
- adcp->adc->CFG1 = grpp->cfg1;
-
- /* Set averaging */
- adcp->adc->SC3 = grpp->sc3;
-
- /* Enable Interrupt, Select Channel */
- adcp->adc->SC1A = ADCx_SC1n_AIEN | ADCx_SC1n_ADCH(adcp->current_channel);
-}
-
-/**
- * @brief Stops an ongoing conversion.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
- const ADCConversionGroup *grpp = adcp->grpp;
-
- /* Disable the Bandgap buffer if channel mask includes BANDGAP */
- if (grpp->channel_mask & ADC_BANDGAP) {
- /* Clear BGBE, ACKISO is w1c, avoid setting */
- PMC->REGSC &= ~(PMC_REGSC_BGBE | PMC_REGSC_ACKISO);
- }
-
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_adc_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_adc_lld.h deleted file mode 100644 index c4edbd6..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_adc_lld.h +++ /dev/null @@ -1,360 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014 Derek Mulcahy
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/LLD/adc_lld.h
- * @brief KINETIS ADC subsystem low level driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef HAL_ADC_LLD_H_
-#define HAL_ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief Minimum ADC clock frequency.
- */
-#define KINETIS_ADCCLK_MIN 600000
-
-/**
- * @brief Maximum ADC clock frequency.
- */
-#define KINETIS_ADCCLK_MAX 36000000
-
-#define ADCx_SC3_AVGS_AVERAGE_4_SAMPLES 0
-#define ADCx_SC3_AVGS_AVERAGE_8_SAMPLES 1
-#define ADCx_SC3_AVGS_AVERAGE_16_SAMPLES 2
-#define ADCx_SC3_AVGS_AVERAGE_32_SAMPLES 3
-
-#define ADCx_CFG1_ADIV_DIV_1 0
-#define ADCx_CFG1_ADIV_DIV_2 1
-#define ADCx_CFG1_ADIV_DIV_4 2
-#define ADCx_CFG1_ADIV_DIV_8 3
-
-#define ADCx_CFG1_ADIVCLK_BUS_CLOCK 0
-#define ADCx_CFG1_ADIVCLK_BUS_CLOCK_DIV_2 1
-#define ADCx_CFG1_ADIVCLK_BUS_ALTCLK 2
-#define ADCx_CFG1_ADIVCLK_BUS_ADACK 3
-
-#define ADCx_CFG1_MODE_8_OR_9_BITS 0
-#define ADCx_CFG1_MODE_12_OR_13_BITS 1
-#define ADCx_CFG1_MODE_10_OR_11_BITS 2
-#define ADCx_CFG1_MODE_16_BITS 3
-
-#define ADCx_SC1n_ADCH_DAD0 0
-#define ADCx_SC1n_ADCH_DAD1 1
-#define ADCx_SC1n_ADCH_DAD2 2
-#define ADCx_SC1n_ADCH_DAD3 3
-#define ADCx_SC1n_ADCH_DADP0 0
-#define ADCx_SC1n_ADCH_DADP1 1
-#define ADCx_SC1n_ADCH_DADP2 2
-#define ADCx_SC1n_ADCH_DADP3 3
-#define ADCx_SC1n_ADCH_AD4 4
-#define ADCx_SC1n_ADCH_AD5 5
-#define ADCx_SC1n_ADCH_AD6 6
-#define ADCx_SC1n_ADCH_AD7 7
-#define ADCx_SC1n_ADCH_AD8 8
-#define ADCx_SC1n_ADCH_AD9 9
-#define ADCx_SC1n_ADCH_AD10 10
-#define ADCx_SC1n_ADCH_AD11 11
-#define ADCx_SC1n_ADCH_AD12 12
-#define ADCx_SC1n_ADCH_AD13 13
-#define ADCx_SC1n_ADCH_AD14 14
-#define ADCx_SC1n_ADCH_AD15 15
-#define ADCx_SC1n_ADCH_AD16 16
-#define ADCx_SC1n_ADCH_AD17 17
-#define ADCx_SC1n_ADCH_AD18 18
-#define ADCx_SC1n_ADCH_AD19 19
-#define ADCx_SC1n_ADCH_AD20 20
-#define ADCx_SC1n_ADCH_AD21 21
-#define ADCx_SC1n_ADCH_AD22 22
-#define ADCx_SC1n_ADCH_AD23 23
-#define ADCx_SC1n_ADCH_TEMP_SENSOR 26
-#define ADCx_SC1n_ADCH_BANDGAP 27
-#define ADCx_SC1n_ADCH_VREFSH 29
-#define ADCx_SC1n_ADCH_VREFSL 30
-#define ADCx_SC1n_ADCH_DISABLED 31
-
-#define ADC_DAD0 (1 << ADCx_SC1n_ADCH_DAD0)
-#define ADC_DAD1 (1 << ADCx_SC1n_ADCH_DAD1)
-#define ADC_DAD2 (1 << ADCx_SC1n_ADCH_DAD2)
-#define ADC_DAD3 (1 << ADCx_SC1n_ADCH_DAD3)
-#define ADC_DADP0 (1 << ADCx_SC1n_ADCH_DADP0)
-#define ADC_DADP1 (1 << ADCx_SC1n_ADCH_DADP1)
-#define ADC_DADP2 (1 << ADCx_SC1n_ADCH_DADP2)
-#define ADC_DADP3 (1 << ADCx_SC1n_ADCH_DADP3)
-#define ADC_AD4 (1 << ADCx_SC1n_ADCH_AD4)
-#define ADC_AD5 (1 << ADCx_SC1n_ADCH_AD5)
-#define ADC_AD6 (1 << ADCx_SC1n_ADCH_AD6)
-#define ADC_AD7 (1 << ADCx_SC1n_ADCH_AD7)
-#define ADC_AD8 (1 << ADCx_SC1n_ADCH_AD8)
-#define ADC_AD9 (1 << ADCx_SC1n_ADCH_AD9)
-#define ADC_AD10 (1 << ADCx_SC1n_ADCH_AD10)
-#define ADC_AD11 (1 << ADCx_SC1n_ADCH_AD11)
-#define ADC_AD12 (1 << ADCx_SC1n_ADCH_AD12)
-#define ADC_AD13 (1 << ADCx_SC1n_ADCH_AD13)
-#define ADC_AD14 (1 << ADCx_SC1n_ADCH_AD14)
-#define ADC_AD15 (1 << ADCx_SC1n_ADCH_AD15)
-#define ADC_AD16 (1 << ADCx_SC1n_ADCH_AD16)
-#define ADC_AD17 (1 << ADCx_SC1n_ADCH_AD17)
-#define ADC_AD18 (1 << ADCx_SC1n_ADCH_AD18)
-#define ADC_AD19 (1 << ADCx_SC1n_ADCH_AD19)
-#define ADC_AD20 (1 << ADCx_SC1n_ADCH_AD20)
-#define ADC_AD21 (1 << ADCx_SC1n_ADCH_AD21)
-#define ADC_AD22 (1 << ADCx_SC1n_ADCH_AD22)
-#define ADC_AD23 (1 << ADCx_SC1n_ADCH_AD23)
-#define ADC_TEMP_SENSOR (1 << ADCx_SC1n_ADCH_TEMP_SENSOR)
-#define ADC_BANDGAP (1 << ADCx_SC1n_ADCH_BANDGAP)
-#define ADC_VREFSH (1 << ADCx_SC1n_ADCH_VREFSH)
-#define ADC_VREFSL (1 << ADCx_SC1n_ADCH_VREFSL)
-#define ADC_DISABLED (1 << ADCx_SC1n_ADCH_DISABLED)
-
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-
-/**
- * @brief ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(KINETIS_ADC_USE_ADC0) || defined(__DOXYGEN__)
-#define KINETIS_ADC_USE_ADC0 FALSE
-#endif
-
-/**
- * @brief ADC interrupt priority level setting.
- */
-#if !defined(KINETIS_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_ADC_IRQ_PRIORITY 5
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if KINETIS_ADC_USE_ADC0 && !KINETIS_HAS_ADC0
-#error "ADC1 not present in the selected device"
-#endif
-
-#if !KINETIS_ADC_USE_ADC0
-#error "ADC driver activated but no ADC peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief ADC sample data type.
- */
-typedef uint16_t adcsample_t;
-
-/**
- * @brief Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief Possible ADC failure causes.
- * @note Error codes are architecture dependent and should not relied
- * upon.
- */
-typedef enum {
- ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
- ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
-} adcerror_t;
-
-/**
- * @brief Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief ADC notification callback type.
- *
- * @param[in] adcp pointer to the @p ADCDriver object triggering the
- * callback
- * @param[in] buffer pointer to the most recent samples data
- * @param[in] n number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief ADC error callback type.
- *
- * @param[in] adcp pointer to the @p ADCDriver object triggering the
- * callback
- * @param[in] err ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- * operation.
- */
-typedef struct {
- /**
- * @brief Enables the circular buffer mode for the group.
- */
- bool circular;
- /**
- * @brief Number of the analog channels belonging to the conversion group.
- */
- adc_channels_num_t num_channels;
- /**
- * @brief Callback function associated to the group or @p NULL.
- */
- adccallback_t end_cb;
- /**
- * @brief Error callback or @p NULL.
- */
- adcerrorcallback_t error_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief Bitmask of channels for ADC conversion.
- */
- uint32_t channel_mask;
- /**
- * @brief ADC CFG1 register initialization data.
- * @note All the required bits must be defined into this field.
- */
- uint32_t cfg1;
- /**
- * @brief ADC SC3 register initialization data.
- * @note All the required bits must be defined into this field.
- */
- uint32_t sc3;
-} ADCConversionGroup;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /* Perform first time calibration */
- bool calibrate;
-} ADCConfig;
-
-/**
- * @brief Structure representing an ADC driver.
- */
-struct ADCDriver {
- /**
- * @brief Driver state.
- */
- adcstate_t state;
- /**
- * @brief Current configuration data.
- */
- const ADCConfig *config;
- /**
- * @brief Current samples buffer pointer or @p NULL.
- */
- adcsample_t *samples;
- /**
- * @brief Current samples buffer depth or @p 0.
- */
- size_t depth;
- /**
- * @brief Current conversion group pointer or @p NULL.
- */
- const ADCConversionGroup *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- thread_reference_t thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the peripheral.
- */
- mutex_t mutex;
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
- ADC_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the ADCx registers block.
- */
- ADC_TypeDef *adc;
- /**
- * @brief Number of samples expected.
- */
- size_t number_of_samples;
- /**
- * @brief Current position in the buffer.
- */
- size_t current_index;
- /**
- * @brief Current channel index into group channel_mask.
- */
- size_t current_channel;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if KINETIS_ADC_USE_ADC0 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void adc_lld_init(void);
- void adc_lld_start(ADCDriver *adcp);
- void adc_lld_stop(ADCDriver *adcp);
- void adc_lld_start_conversion(ADCDriver *adcp);
- void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* HAL_ADC_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_ext_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_ext_lld.c deleted file mode 100644 index 21bb6e0..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_ext_lld.c +++ /dev/null @@ -1,434 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014 Derek Mulcahy
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/LLD/ext_lld.c
- * @brief KINETIS EXT subsystem low level driver source.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#define PCR_IRQC_DISABLED 0x0
-#define PCR_IRQC_DMA_RISING_EDGE 0x1
-#define PCR_IRQC_DMA_FALLING_EDGE 0x2
-#define PCR_IRQC_DMA_EITHER_EDGE 0x3
-
-#define PCR_IRQC_LOGIC_ZERO 0x8
-#define PCR_IRQC_RISING_EDGE 0x9
-#define PCR_IRQC_FALLING_EDGE 0xA
-#define PCR_IRQC_EITHER_EDGE 0xB
-#define PCR_IRQC_LOGIC_ONE 0xC
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief EXTD1 driver identifier.
- */
-EXTDriver EXTD1;
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/* A channel map for each channel.
- *
- * The index is the pin number.
- * The result is the channel for that pin.
- */
-#if KINETIS_EXT_PORTA_WIDTH > 0
-uint8_t porta_channel_map[KINETIS_EXT_PORTA_WIDTH];
-#endif
-#if KINETIS_EXT_PORTB_WIDTH > 0
-uint8_t portb_channel_map[KINETIS_EXT_PORTB_WIDTH];
-#endif
-#if KINETIS_EXT_PORTC_WIDTH > 0
-uint8_t portc_channel_map[KINETIS_EXT_PORTC_WIDTH];
-#endif
-#if KINETIS_EXT_PORTD_WIDTH > 0
-uint8_t portd_channel_map[KINETIS_EXT_PORTD_WIDTH];
-#endif
-#if KINETIS_EXT_PORTE_WIDTH > 0
-uint8_t porte_channel_map[KINETIS_EXT_PORTE_WIDTH];
-#endif
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Enables EXTI IRQ sources.
- *
- * @notapi
- */
-static void ext_lld_exti_irq_enable(void) {
-
-#if KINETIS_EXT_PORTA_WIDTH > 0
- nvicEnableVector(PINA_IRQn, KINETIS_EXT_PORTA_IRQ_PRIORITY);
-#endif
-
-#if KINETIS_EXT_HAS_COMMON_BCDE_IRQ
-#if (KINETIS_EXT_PORTB_WIDTH > 0) || (KINETIS_EXT_PORTC_WIDTH > 0) \
- || (KINETIS_EXT_PORTD_WIDTH > 0) || (KINETIS_EXT_PORTE_WIDTH > 0)
- nvicEnableVector(PINBCDE_IRQn, KINETIS_EXT_PORTD_IRQ_PRIORITY);
-#endif
-
-#elif KINETIS_EXT_HAS_COMMON_CD_IRQ /* KINETIS_EXT_HAS_COMMON_BCDE_IRQ */
-#if (KINETIS_EXT_PORTC_WIDTH > 0) || (KINETIS_EXT_PORTD_WIDTH > 0)
- nvicEnableVector(PINCD_IRQn, KINETIS_EXT_PORTD_IRQ_PRIORITY);
-#endif
-
-#else /* KINETIS_EXT_HAS_COMMON_CD_IRQ */
-#if KINETIS_EXT_PORTB_WIDTH > 0
- nvicEnableVector(PINB_IRQn, KINETIS_EXT_PORTB_IRQ_PRIORITY);
-#endif
-#if KINETIS_EXT_PORTC_WIDTH > 0
- nvicEnableVector(PINC_IRQn, KINETIS_EXT_PORTC_IRQ_PRIORITY);
-#endif
-#if KINETIS_EXT_PORTD_WIDTH > 0
- nvicEnableVector(PIND_IRQn, KINETIS_EXT_PORTD_IRQ_PRIORITY);
-#endif
-#if KINETIS_EXT_PORTE_WIDTH > 0
- nvicEnableVector(PINE_IRQn, KINETIS_EXT_PORTE_IRQ_PRIORITY);
-#endif
-#endif /* !KINETIS_EXT_HAS_COMMON_CD_IRQ */
-}
-
-/**
- * @brief Disables EXTI IRQ sources.
- *
- * @notapi
- */
-static void ext_lld_exti_irq_disable(void) {
-
-#if KINETIS_EXT_PORTA_WIDTH > 0
- nvicDisableVector(PINA_IRQn);
-#endif
-
-#if KINETIS_EXT_HAS_COMMON_BCDE_IRQ
-#if (KINETIS_EXT_PORTB_WIDTH > 0) || (KINETIS_EXT_PORTC_WIDTH > 0) \
- || (KINETIS_EXT_PORTD_WIDTH > 0) || (KINETIS_EXT_PORTE_WIDTH > 0)
- nvicDisableVector(PINBCDE_IRQn);
-#endif
-
-#elif KINETIS_EXT_HAS_COMMON_CD_IRQ /* KINETIS_EXT_HAS_COMMON_BCDE_IRQ */
-#if (KINETIS_EXT_PORTC_WIDTH > 0) || (KINETIS_EXT_PORTD_WIDTH > 0)
- nvicDisableVector(PINCD_IRQn);
-#endif
-
-#else /* KINETIS_EXT_HAS_COMMON_CD_IRQ */
-#if KINETIS_EXT_PORTB_WIDTH > 0
- nvicDisableVector(PINB_IRQn);
-#endif
-#if KINETIS_EXT_PORTC_WIDTH > 0
- nvicDisableVector(PINC_IRQn);
-#endif
-#if KINETIS_EXT_PORTD_WIDTH > 0
- nvicDisableVector(PIND_IRQn);
-#endif
-#if KINETIS_EXT_PORTE_WIDTH > 0
- nvicDisableVector(PINE_IRQn);
-#endif
-#endif /* !KINETIS_EXT_HAS_COMMON_CD_IRQ */
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*
- * Generic interrupt handler.
- */
-static inline void irq_handler(PORT_TypeDef * const port, const unsigned port_width, const uint8_t *channel_map) {
- unsigned pin;
- uint32_t isfr = port->ISFR;
-
- /* Clear all pending interrupts on this port. */
- port->ISFR = 0xFFFFFFFF;
-
- for (pin = 0; pin < port_width; pin++) {
- if (isfr & (1 << pin)) {
- expchannel_t channel = channel_map[pin];
- EXTD1.config->channels[channel].cb(&EXTD1, channel);
- }
- }
-}
-
-/**
- * @brief PORTA interrupt handler.
- *
- * @isr
- */
-#if defined(KINETIS_PORTA_IRQ_VECTOR) && KINETIS_EXT_PORTA_WIDTH > 0
-OSAL_IRQ_HANDLER(KINETIS_PORTA_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
- irq_handler(PORTA, KINETIS_EXT_PORTA_WIDTH, porta_channel_map);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_EXT_PORTA_WIDTH > 0 */
-
-#if KINETIS_EXT_HAS_COMMON_BCDE_IRQ
-
-#if defined(KINETIS_PORTD_IRQ_VECTOR)
-OSAL_IRQ_HANDLER(KINETIS_PORTD_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
-#if (KINETIS_EXT_PORTB_WIDTH > 0)
- irq_handler(PORTB, KINETIS_EXT_PORTB_WIDTH, portb_channel_map);
-#endif
-#if (KINETIS_EXT_PORTC_WIDTH > 0)
- irq_handler(PORTC, KINETIS_EXT_PORTC_WIDTH, portc_channel_map);
-#endif
-#if (KINETIS_EXT_PORTD_WIDTH > 0)
- irq_handler(PORTD, KINETIS_EXT_PORTD_WIDTH, portd_channel_map);
-#endif
-#if (KINETIS_EXT_PORTE_WIDTH > 0)
- irq_handler(PORTE, KINETIS_EXT_PORTE_WIDTH, porte_channel_map);
-#endif
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* defined(KINETIS_PORTD_IRQ_VECTOR) */
-
-#elif KINETIS_EXT_HAS_COMMON_CD_IRQ /* KINETIS_EXT_HAS_COMMON_BCDE_IRQ */
-
-#if defined(KINETIS_PORTD_IRQ_VECTOR)
-OSAL_IRQ_HANDLER(KINETIS_PORTD_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
-#if (KINETIS_EXT_PORTC_WIDTH > 0)
- irq_handler(PORTC, KINETIS_EXT_PORTC_WIDTH, portc_channel_map);
-#endif
-#if (KINETIS_EXT_PORTD_WIDTH > 0)
- irq_handler(PORTD, KINETIS_EXT_PORTD_WIDTH, portd_channel_map);
-#endif
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* defined(KINETIS_PORTD_IRQ_VECTOR) */
-
-
-#else /* KINETIS_EXT_HAS_COMMON_CD_IRQ */
-
-/**
- * @brief PORTB interrupt handler.
- *
- * @isr
- */
-#if defined(KINETIS_PORTB_IRQ_VECTOR) && KINETIS_EXT_PORTB_WIDTH > 0
-OSAL_IRQ_HANDLER(KINETIS_PORTB_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
- irq_handler(PORTB, KINETIS_EXT_PORTB_WIDTH, portb_channel_map);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_EXT_PORTB_WIDTH > 0 */
-
-/**
- * @brief PORTC interrupt handler.
- *
- * @isr
- */
-#if defined(KINETIS_PORTC_IRQ_VECTOR) && KINETIS_EXT_PORTC_WIDTH > 0
-OSAL_IRQ_HANDLER(KINETIS_PORTC_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
- irq_handler(PORTC, KINETIS_EXT_PORTC_WIDTH, portc_channel_map);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_EXT_PORTC_WIDTH > 0 */
-
-/**
- * @brief PORTD interrupt handler.
- *
- * @isr
- */
-#if defined(KINETIS_PORTD_IRQ_VECTOR) && KINETIS_EXT_PORTD_WIDTH > 0
-OSAL_IRQ_HANDLER(KINETIS_PORTD_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
- irq_handler(PORTD, KINETIS_EXT_PORTD_WIDTH, portd_channel_map);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_EXT_PORTD_WIDTH > 0 */
-
-/**
- * @brief PORTE interrupt handler.
- *
- * @isr
- */
-#if defined(KINETIS_PORTE_IRQ_VECTOR) && KINETIS_EXT_PORTE_WIDTH > 0
-OSAL_IRQ_HANDLER(KINETIS_PORTE_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-
- irq_handler(PORTE, KINETIS_EXT_PORTE_WIDTH, porte_channel_map);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_EXT_PORTE_WIDTH > 0 */
-
-#endif /* !KINETIS_EXT_HAS_COMMON_CD_IRQ */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level EXT driver initialization.
- *
- * @notapi
- */
-void ext_lld_init(void) {
-
- /* Driver initialization.*/
- extObjectInit(&EXTD1);
-}
-
-/**
- * @brief Configures and activates the EXT peripheral.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_start(EXTDriver *extp) {
- expchannel_t channel;
-
- if (extp->state == EXT_STOP)
- ext_lld_exti_irq_enable();
-
- /* Configuration of automatic channels.*/
- for (channel = 0; channel < EXT_MAX_CHANNELS; channel++) {
-
- uint32_t mode = extp->config->channels[channel].mode;
- PORT_TypeDef *port = extp->config->channels[channel].port;
- uint32_t pin = extp->config->channels[channel].pin;
-
- /* Initialize the channel map */
-#if KINETIS_EXT_PORTA_WIDTH > 0
- if (port == PORTA)
- porta_channel_map[pin] = channel;
- else
-#endif
-#if KINETIS_EXT_PORTB_WIDTH > 0
- if (port == PORTB)
- portb_channel_map[pin] = channel;
- else
-#endif
-#if KINETIS_EXT_PORTC_WIDTH > 0
- if (port == PORTC)
- portc_channel_map[pin] = channel;
- else
-#endif
-#if KINETIS_EXT_PORTD_WIDTH > 0
- if (port == PORTD)
- portd_channel_map[pin] = channel;
- else
-#endif
-#if KINETIS_EXT_PORTE_WIDTH > 0
- if (port == PORTE)
- porte_channel_map[pin] = channel;
- else
-#endif
- {}
-
- if (mode & EXT_CH_MODE_AUTOSTART)
- ext_lld_channel_enable(extp, channel);
- else if (port != NULL)
- ext_lld_channel_disable(extp, channel);
- }
-}
-
-/**
- * @brief Deactivates the EXT peripheral.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_stop(EXTDriver *extp) {
-
- if (extp->state == EXT_ACTIVE)
- ext_lld_exti_irq_disable();
-}
-
-/**
- * @brief Enables an EXT channel.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- * @param[in] channel channel to be enabled
- *
- * @notapi
- */
-void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
-
- uint32_t irqc;
- uint32_t mode = extp->config->channels[channel].mode;
- if (mode & EXT_CH_MODE_RISING_EDGE)
- irqc = PCR_IRQC_RISING_EDGE;
- else if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE)
- irqc = PCR_IRQC_FALLING_EDGE;
- else if (extp->config->channels[channel].mode & EXT_CH_MODE_BOTH_EDGES)
- irqc = PCR_IRQC_EITHER_EDGE;
- else
- irqc = PCR_IRQC_DISABLED;
-
- PORT_TypeDef *port = extp->config->channels[channel].port;
- uint32_t pin = extp->config->channels[channel].pin;
-
- uint32_t pcr = port->PCR[pin];
-
- /* Clear all the IRQC bits */
- pcr &= ~PORTx_PCRn_IRQC_MASK;
- /* Set the required IRQC bits */
- pcr |= PORTx_PCRn_IRQC(irqc);
-
- port->PCR[pin] = pcr;
-}
-
-/**
- * @brief Disables an EXT channel.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- * @param[in] channel channel to be disabled
- *
- * @notapi
- */
-void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
-
- PORT_TypeDef *port = extp->config->channels[channel].port;
- uint32_t pin = extp->config->channels[channel].pin;
- port->PCR[pin] |= PORTx_PCRn_IRQC(PCR_IRQC_DISABLED);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_ext_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_ext_lld.h deleted file mode 100644 index bcd9cb0..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_ext_lld.h +++ /dev/null @@ -1,188 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014 Derek Mulcahy
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/LLD/ext_lld.h
- * @brief KINETIS EXT subsystem low level driver header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef HAL_EXT_LLD_H_
-#define HAL_EXT_LLD_H_
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Number of EXT channels required.
- */
-#define EXT_MAX_CHANNELS KINETIS_EXTI_NUM_CHANNELS
-
-/**
- * @name KINETIS-specific EXT channel modes
- * @{
- */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief PORTA interrupt priority level setting.
- */
-#if !defined(KINETIS_EXT_PORTA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_EXT_PORTA_IRQ_PRIORITY 3
-#endif
-
-/**
- * @brief PORTB interrupt priority level setting.
- */
-#if !defined(KINETIS_EXT_PORTB_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_EXT_PORTB_IRQ_PRIORITY 3
-#endif
-
-/**
- * @brief PORTC interrupt priority level setting.
- */
-#if !defined(KINETIS_EXT_PORTC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_EXT_PORTC_IRQ_PRIORITY 3
-#endif
-
-/**
- * @brief PORTD interrupt priority level setting.
- */
-#if !defined(KINETIS_EXT_PORTD_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_EXT_PORTD_IRQ_PRIORITY 3
-#endif
-
-/**
- * @brief PORTE interrupt priority level setting.
- */
-#if !defined(KINETIS_EXT_PORTE_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_EXT_PORTE_IRQ_PRIORITY 3
-#endif
-/** @} */
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief EXT channel identifier.
- */
-typedef uint32_t expchannel_t;
-
-/**
- * @brief Type of an EXT generic notification callback.
- *
- * @param[in] extp pointer to the @p EXPDriver object triggering the
- * callback
- */
-typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
-
-/**
- * @brief Channel configuration structure.
- */
-typedef struct {
- /**
- * @brief Channel mode.
- */
- uint32_t mode;
- /**
- * @brief Channel callback.
- */
- extcallback_t cb;
-
- /**
- * @brief Port.
- */
- PORT_TypeDef *port;
-
- /**
- * @brief Pin.
- */
- uint32_t pin;
-} EXTChannelConfig;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief Channel configurations.
- */
- EXTChannelConfig channels[EXT_MAX_CHANNELS];
- /* End of the mandatory fields.*/
-} EXTConfig;
-
-/**
- * @brief Structure representing an EXT driver.
- */
-struct EXTDriver {
- /**
- * @brief Driver state.
- */
- extstate_t state;
- /**
- * @brief Current configuration data.
- */
- const EXTConfig *config;
- /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern EXTDriver EXTD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void ext_lld_init(void);
- void ext_lld_start(EXTDriver *extp);
- void ext_lld_stop(EXTDriver *extp);
- void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
- void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* HAL_EXT_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c deleted file mode 100644 index 6e88f88..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c +++ /dev/null @@ -1,391 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014 Derek Mulcahy
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/gpt_lld.c
- * @brief KINETIS GPT subsystem low level driver source.
- *
- * @addtogroup GPT
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief GPTD1 driver identifier.
- * @note The driver GPTD1 allocates the complex timer PIT0 when enabled.
- */
-#if KINETIS_GPT_USE_PIT0 || defined(__DOXYGEN__)
-GPTDriver GPTD1;
-#endif
-
-/**
- * @brief GPTD2 driver identifier.
- * @note The driver GPTD2 allocates the timer PIT1 when enabled.
- */
-#if KINETIS_GPT_USE_PIT1 || defined(__DOXYGEN__)
-GPTDriver GPTD2;
-#endif
-
-/**
- * @brief GPTD3 driver identifier.
- * @note The driver GPTD3 allocates the timer PIT2 when enabled.
- */
-#if KINETIS_GPT_USE_PIT2 || defined(__DOXYGEN__)
-GPTDriver GPTD3;
-#endif
-
-/**
- * @brief GPTD4 driver identifier.
- * @note The driver GPTD4 allocates the timer PIT3 when enabled.
- */
-#if KINETIS_GPT_USE_PIT3 || defined(__DOXYGEN__)
-GPTDriver GPTD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-#if KINETIS_HAS_PIT_COMMON_IRQ
-static uint8_t active_channels = 0;
-#endif /* KINETIS_HAS_PIT_COMMON_IRQ */
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Shared IRQ handler.
- *
- * @param[in] gptp pointer to a @p GPTDriver object
- */
-static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
-
- /* Clear the interrupt */
- gptp->channel->TFLG |= PIT_TFLGn_TIF;
-
- if (gptp->state == GPT_ONESHOT) {
- gptp->state = GPT_READY; /* Back in GPT_READY state. */
- gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */
- }
- gptp->config->callback(gptp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if !KINETIS_HAS_PIT_COMMON_IRQ
-
-#if KINETIS_GPT_USE_PIT0
-/**
- * @brief PIT1 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_PIT0_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
- gpt_lld_serve_interrupt(&GPTD1);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_GPT_USE_PIT0 */
-
-#if KINETIS_GPT_USE_PIT1
-/**
- * @brief PIT1 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_PIT1_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
- gpt_lld_serve_interrupt(&GPTD2);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_GPT_USE_PIT1 */
-
-#if KINETIS_GPT_USE_PIT2
-/**
- * @brief PIT2 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_PIT2_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
- gpt_lld_serve_interrupt(&GPTD3);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_GPT_USE_PIT2 */
-
-#if KINETIS_GPT_USE_PIT3
-/**
- * @brief PIT3 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_PIT3_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
- gpt_lld_serve_interrupt(&GPTD4);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_GPT_USE_PIT3 */
-
-#else /* !KINETIS_HAS_PIT_COMMON_IRQ */
-/**
- * @brief Common PIT interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_PIT_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
-#if KINETIS_GPT_USE_PIT0
- if(GPTD1.channel->TFLG & PIT_TFLGn_TIF)
- gpt_lld_serve_interrupt(&GPTD1);
-#endif /* KINETIS_GPT_USE_PIT0 */
-#if KINETIS_GPT_USE_PIT1
- if(GPTD2.channel->TFLG & PIT_TFLGn_TIF)
- gpt_lld_serve_interrupt(&GPTD2);
-#endif /* KINETIS_GPT_USE_PIT1 */
-#if KINETIS_GPT_USE_PIT2
- if(GPTD3.channel->TFLG & PIT_TFLGn_TIF)
- gpt_lld_serve_interrupt(&GPTD3);
-#endif /* KINETIS_GPT_USE_PIT2 */
-#if KINETIS_GPT_USE_PIT3
- if(GPTD4.channel->TFLG & PIT_TFLGn_TIF)
- gpt_lld_serve_interrupt(&GPTD4);
-#endif /* KINETIS_GPT_USE_PIT3 */
- OSAL_IRQ_EPILOGUE();
-}
-
-#endif /* !KINETIS_HAS_PIT_COMMON_IRQ */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level GPT driver initialization.
- *
- * @notapi
- */
-void gpt_lld_init(void) {
-
-#if KINETIS_GPT_USE_PIT0
- /* Driver initialization.*/
- GPTD1.channel = &PIT->CHANNEL[0];
- gptObjectInit(&GPTD1);
-#endif
-
-#if KINETIS_GPT_USE_PIT1
- /* Driver initialization.*/
- GPTD2.channel = &PIT->CHANNEL[1];
- gptObjectInit(&GPTD2);
-#endif
-
-#if KINETIS_GPT_USE_PIT2
- /* Driver initialization.*/
- GPTD3.channel = &PIT->CHANNEL[2];
- gptObjectInit(&GPTD3);
-#endif
-
-#if KINETIS_GPT_USE_PIT3
- /* Driver initialization.*/
- GPTD4.channel = &PIT->CHANNEL[3];
- gptObjectInit(&GPTD4);
-#endif
-}
-
-/**
- * @brief Configures and activates the GPT peripheral.
- *
- * @param[in] gptp pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_start(GPTDriver *gptp) {
- uint16_t psc;
-
- if (gptp->state == GPT_STOP) {
- /* Clock activation.*/
- SIM->SCGC6 |= SIM_SCGC6_PIT;
- gptp->clock = KINETIS_SYSCLK_FREQUENCY;
-
-#if !KINETIS_HAS_PIT_COMMON_IRQ
-
-#if KINETIS_GPT_USE_PIT0
- if (&GPTD1 == gptp) {
- nvicEnableVector(PITChannel0_IRQn, KINETIS_GPT_PIT0_IRQ_PRIORITY);
- }
-#endif
-#if KINETIS_GPT_USE_PIT1
- if (&GPTD2 == gptp) {
- nvicEnableVector(PITChannel1_IRQn, KINETIS_GPT_PIT1_IRQ_PRIORITY);
- }
-#endif
-#if KINETIS_GPT_USE_PIT2
- if (&GPTD3 == gptp) {
- nvicEnableVector(PITChannel2_IRQn, KINETIS_GPT_PIT2_IRQ_PRIORITY);
- }
-#endif
-#if KINETIS_GPT_USE_PIT3
- if (&GPTD4 == gptp) {
- nvicEnableVector(PITChannel3_IRQn, KINETIS_GPT_PIT3_IRQ_PRIORITY);
- }
-#endif
-
-#else /* !KINETIS_HAS_PIT_COMMON_IRQ */
- nvicEnableVector(PIT_IRQn, KINETIS_GPT_PIT_IRQ_PRIORITY);
- active_channels++;
-#endif /* !KINETIS_HAS_PIT_COMMON_IRQ */
- }
-
- /* Prescaler value calculation.*/
- psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);
- osalDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
- "invalid frequency");
-
- /* Enable the PIT */
- PIT->MCR = 0;
-}
-
-/**
- * @brief Deactivates the GPT peripheral.
- *
- * @param[in] gptp pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop(GPTDriver *gptp) {
-
- if (gptp->state == GPT_READY) {
- SIM->SCGC6 &= ~SIM_SCGC6_PIT;
-
- /* Disable the channel */
- gptp->channel->TCTRL = 0;
-
- /* Clear pending interrupts */
- gptp->channel->TFLG |= PIT_TFLGn_TIF;
-
-#if !KINETIS_HAS_PIT_COMMON_IRQ
-
-#if KINETIS_GPT_USE_PIT0
- if (&GPTD1 == gptp) {
- nvicDisableVector(PITChannel0_IRQn);
- }
-#endif
-#if KINETIS_GPT_USE_PIT1
- if (&GPTD2 == gptp) {
- nvicDisableVector(PITChannel1_IRQn);
- }
-#endif
-#if KINETIS_GPT_USE_PIT2
- if (&GPTD3 == gptp) {
- nvicDisableVector(PITChannel2_IRQn);
- }
-#endif
-#if KINETIS_GPT_USE_PIT3
- if (&GPTD4 == gptp) {
- nvicDisableVector(PITChannel3_IRQn);
- }
-#endif
-
-#else /* !KINETIS_HAS_PIT_COMMON_IRQ */
- if(--active_channels == 0)
- nvicDisableVector(PIT_IRQn);
-#endif /* !KINETIS_HAS_PIT_COMMON_IRQ */
- }
-}
-
-/**
- * @brief Starts the timer in continuous mode.
- *
- * @param[in] gptp pointer to the @p GPTDriver object
- * @param[in] interval period in ticks
- *
- * @notapi
- */
-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
-
- /* Clear pending interrupts */
- gptp->channel->TFLG |= PIT_TFLGn_TIF;
-
- /* Set the interval */
- gpt_lld_change_interval(gptp, interval);
-
- /* Start the timer */
- gptp->channel->TCTRL |= PIT_TCTRLn_TIE | PIT_TCTRLn_TEN;
-}
-
-/**
- * @brief Stops the timer.
- *
- * @param[in] gptp pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop_timer(GPTDriver *gptp) {
-
- /* Stop the timer */
- gptp->channel->TCTRL = 0;
-}
-
-/**
- * @brief Starts the timer in one shot mode and waits for completion.
- * @details This function specifically polls the timer waiting for completion
- * in order to not have extra delays caused by interrupt servicing,
- * this function is only recommended for short delays.
- *
- * @param[in] gptp pointer to the @p GPTDriver object
- * @param[in] interval time interval in ticks
- *
- * @notapi
- */
-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
- struct PIT_CHANNEL *channel = gptp->channel;
-
- /* Disable timer and disable interrupts */
- channel->TCTRL = 0;
-
- /* Clear the interrupt flag */
- channel->TFLG |= PIT_TFLGn_TIF;
-
- /* Set the interval */
- channel->LDVAL = (gptp->clock / gptp->config->frequency) * interval;
-
- /* Enable Timer but keep interrupts disabled */
- channel->TCTRL = PIT_TCTRLn_TEN;
-
- /* Wait for the interrupt flag to be set */
- while (!(channel->TFLG & PIT_TFLGn_TIF))
- ;
-
- /* Disable timer and disable interrupts */
- channel->TCTRL = 0;
-}
-
-#endif /* HAL_USE_GPT */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_gpt_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_gpt_lld.h deleted file mode 100644 index 1b9e5ef..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_gpt_lld.h +++ /dev/null @@ -1,333 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014 Derek Mulcahy
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/gpt_lld.h
- * @brief KINETIS GPT subsystem low level driver header.
- *
- * @addtogroup GPT
- * @{
- */
-
-#ifndef HAL_GPT_LLD_H_
-#define HAL_GPT_LLD_H_
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief GPTD1 driver enable switch.
- * @details If set to @p TRUE the support for GPTD1 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(KINETIS_GPT_USE_PIT0) || defined(__DOXYGEN__)
-#define KINETIS_GPT_USE_PIT0 FALSE
-#endif
-
-/**
- * @brief GPTD2 driver enable switch.
- * @details If set to @p TRUE the support for GPTD2 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(KINETIS_GPT_USE_PIT1) || defined(__DOXYGEN__)
-#define KINETIS_GPT_USE_PIT1 FALSE
-#endif
-
-/**
- * @brief GPTD3 driver enable switch.
- * @details If set to @p TRUE the support for GPTD3 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(KINETIS_GPT_USE_PIT2) || defined(__DOXYGEN__)
-#define KINETIS_GPT_USE_PIT2 FALSE
-#endif
-
-/**
- * @brief GPTD4 driver enable switch.
- * @details If set to @p TRUE the support for GPTD4 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(KINETIS_GPT_USE_PIT3) || defined(__DOXYGEN__)
-#define KINETIS_GPT_USE_PIT3 FALSE
-#endif
-
-/**
- * @brief GPTD1 interrupt priority level setting.
- */
-#if !defined(KINETIS_GPT_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_GPT_PIT0_IRQ_PRIORITY 7
-#endif
-
-/**
- * @brief GPTD2 interrupt priority level setting.
- */
-#if !defined(KINETIS_GPT_PIT1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_GPT_PIT1_IRQ_PRIORITY 7
-#endif
-
-/**
- * @brief GPTD3 interrupt priority level setting.
- */
-#if !defined(KINETIS_GPT_PIT2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_GPT_PIT2_IRQ_PRIORITY 7
-#endif
-
-/**
- * @brief GPTD4 interrupt priority level setting.
- */
-#if !defined(KINETIS_GPT_PIT3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_GPT_PIT3_IRQ_PRIORITY 7
-#endif
-
-/**
- * @brief GPTD* common interrupt priority level setting.
- */
-#if (KINETIS_HAS_PIT_COMMON_IRQ && !defined(KINETIS_GPT_PIT_IRQ_PRIORITY)) \
- || defined(__DOXYGEN__)
-#define KINETIS_GPT_PIT_IRQ_PRIORITY 2
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if KINETIS_GPT_USE_PIT0 && !KINETIS_HAS_PIT0
-#error "PIT0 not present in the selected device"
-#endif
-
-#if KINETIS_GPT_USE_PIT1 && !KINETIS_HAS_PIT1
-#error "PIT1 not present in the selected device"
-#endif
-
-#if KINETIS_GPT_USE_PIT2 && !KINETIS_HAS_PIT2
-#error "PIT2 not present in the selected device"
-#endif
-
-#if KINETIS_GPT_USE_PIT3 && !KINETIS_HAS_PIT3
-#error "PIT3 not present in the selected device"
-#endif
-
-#if !KINETIS_GPT_USE_PIT0 && !KINETIS_GPT_USE_PIT1 && \
- !KINETIS_GPT_USE_PIT2 && !KINETIS_GPT_USE_PIT3
-#error "GPT driver activated but no PIT peripheral assigned"
-#endif
-
-#if KINETIS_GPT_USE_PIT0 && !KINETIS_HAS_PIT_COMMON_IRQ && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to PIT0"
-#endif
-
-#if KINETIS_GPT_USE_PIT1 && !KINETIS_HAS_PIT_COMMON_IRQ && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to PIT1"
-#endif
-
-#if KINETIS_GPT_USE_PIT2 && !KINETIS_HAS_PIT_COMMON_IRQ && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to PIT2"
-#endif
-
-#if KINETIS_GPT_USE_PIT3 && !KINETIS_HAS_PIT_COMMON_IRQ && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to PIT3"
-#endif
-
-#if KINETIS_HAS_PIT_COMMON_IRQ && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to PIT"
-#endif
-
-#if KINETIS_GPT_USE_PIT0 && !defined(KINETIS_PIT0_IRQ_VECTOR) && \
- !KINETIS_HAS_PIT_COMMON_IRQ
-#error "KINETIS_PIT0_IRQ_VECTOR not defined"
-#endif
-
-#if KINETIS_GPT_USE_PIT1 && !defined(KINETIS_PIT1_IRQ_VECTOR) && \
- !KINETIS_HAS_PIT_COMMON_IRQ
-#error "KINETIS_PIT1_IRQ_VECTOR not defined"
-#endif
-
-#if KINETIS_GPT_USE_PIT2 && !defined(KINETIS_PIT2_IRQ_VECTOR) && \
- !KINETIS_HAS_PIT_COMMON_IRQ
-#error "KINETIS_PIT2_IRQ_VECTOR not defined"
-#endif
-
-#if KINETIS_GPT_USE_PIT3 && !defined(KINETIS_PIT3_IRQ_VECTOR) && \
- !KINETIS_HAS_PIT_COMMON_IRQ
-#error "KINETIS_PIT3_IRQ_VECTOR not defined"
-#endif
-
-#if KINETIS_HAS_PIT_COMMON_IRQ && !defined(KINETIS_PIT_IRQ_VECTOR)
-#error "KINETIS_PIT_IRQ_VECTOR not defined"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief GPT frequency type.
- */
-typedef uint32_t gptfreq_t;
-
-/**
- * @brief GPT counter type.
- */
-typedef uint32_t gptcnt_t;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- gptfreq_t frequency;
- /**
- * @brief Timer callback pointer.
- * @note This callback is invoked on GPT counter events.
- * @note This callback can be set to @p NULL but in that case the
- * one-shot mode cannot be used.
- */
- gptcallback_t callback;
- /* End of the mandatory fields.*/
-} GPTConfig;
-
-/**
- * @brief Structure representing a GPT driver.
- */
-struct GPTDriver {
- /**
- * @brief Driver state.
- */
- gptstate_t state;
- /**
- * @brief Current configuration data.
- */
- const GPTConfig *config;
-#if defined(GPT_DRIVER_EXT_FIELDS)
- GPT_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Timer base clock.
- */
- uint32_t clock;
- /**
- * @brief Channel structure in PIT registers block.
- */
- struct PIT_CHANNEL *channel;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Changes the interval of GPT peripheral.
- * @details This function changes the interval of a running GPT unit.
- * @pre The GPT unit must be running in continuous mode.
- * @post The GPT unit interval is changed to the new value.
- * @note The function has effect at the next cycle start.
- *
- * @param[in] gptp pointer to a @p GPTDriver object
- * @param[in] interval new cycle time in timer ticks
- *
- * @notapi
- */
-#define gpt_lld_change_interval(gptp, interval) \
- ((gptp)->channel->LDVAL = (uint32_t)( \
- ( (gptp)->clock / (gptp)->config->frequency ) * \
- ( interval ) ))
-
-/**
- * @brief Returns the interval of GPT peripheral.
- * @pre The GPT unit must be running in continuous mode.
- *
- * @param[in] gptp pointer to a @p GPTDriver object
- * @return The current interval.
- *
- * @notapi
- */
-#define gpt_lld_get_interval(gptp) \
- ((uint32_t)( ( (uint64_t)(gptp)->channel->LDVAL * (gptp)->config->frequency ) / \
- ( (uint32_t)(gptp)->clock ) ))
-
-/**
- * @brief Returns the counter value of GPT peripheral.
- * @pre The GPT unit must be running in continuous mode.
- * @note The nature of the counter is not defined, it may count upward
- * or downward, it could be continuously running or not.
- *
- * @param[in] gptp pointer to a @p GPTDriver object
- * @return The current counter value.
- *
- * @notapi
- */
-#define gpt_lld_get_counter(gptp) ((gptcnt_t)(gptp)->pit->CHANNEL[gptp->channel].CVAL)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if KINETIS_GPT_USE_PIT0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD1;
-#endif
-
-#if KINETIS_GPT_USE_PIT1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD2;
-#endif
-
-#if KINETIS_GPT_USE_PIT2 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD3;
-#endif
-
-#if KINETIS_GPT_USE_PIT3 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void gpt_lld_init(void);
- void gpt_lld_start(GPTDriver *gptp);
- void gpt_lld_stop(GPTDriver *gptp);
- void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
- void gpt_lld_stop_timer(GPTDriver *gptp);
- void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_GPT */
-
-#endif /* HAL_GPT_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c deleted file mode 100644 index c6b3d11..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c +++ /dev/null @@ -1,583 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/LLD/i2c_lld.c
- * @brief KINETIS I2C subsystem low level driver source.
- *
- * @addtogroup I2C
- * @{
- */
-
-#include "osal.h"
-#include "hal.h"
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief I2C0 driver identifier.
- */
-#if KINETIS_I2C_USE_I2C0 || defined(__DOXYGEN__)
-I2CDriver I2CD1;
-#endif
-
-/**
- * @brief I2C1 driver identifier.
- */
-#if KINETIS_I2C_USE_I2C1 || defined(__DOXYGEN__)
-I2CDriver I2CD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-void config_frequency(I2CDriver *i2cp) {
-
- /* Each index in the table corresponds to a a frequency
- * divider used to generate the SCL clock from the main
- * system clock.
- */
- const uint16_t icr_table[] = {
- /* 0x00 - 0x0F */
- 20,22,24,26,28,30,34,40,28,32,36,40,44,48,56,68,
- /* 0x10 - 0x1F */
- 48,56,64,72,80,88,104,128,80,96,112,128,144,160,192,240,
- /* 0x20 - 0x2F */
- 160,192,224,256,288,320,384,480,320,384,448,512,576,640,768,960,
- /* 0x30 - 0x3F */
- 640,768,896,1024,1152,1280,1536,1920,1280,1536,1792,2048,2304,2560,3072,3840,
- };
-
- int length = sizeof(icr_table) / sizeof(icr_table[0]);
- uint16_t divisor;
- uint8_t i = 0, index = 0;
- uint16_t best, diff;
-
- if (i2cp->config != NULL)
- divisor = KINETIS_BUSCLK_FREQUENCY / i2cp->config->clock;
- else
- divisor = KINETIS_BUSCLK_FREQUENCY / 100000;
-
- best = ~0;
- index = 0;
- /* Tries to find the SCL clock which is the closest
- * approximation to the clock passed in config. To
- * stay on the safe side, only values that generate
- * lower frequency are used.
- */
- for (i = 0; i < length; i++) {
- if (icr_table[i] >= divisor) {
- diff = icr_table[i] - divisor;
- if (diff < best) {
- best = diff;
- index = i;
- }
- }
- }
-
- i2cp->i2c->F = index;
-}
-
-/**
- * @brief Common IRQ handler.
- * @note Tries hard to clear all the pending interrupt sources, we don't
- * want to go through the whole ISR and have another interrupt soon
- * after.
- *
- * @param[in] i2cp pointer to an I2CDriver
- */
-static void serve_interrupt(I2CDriver *i2cp) {
-
- I2C_TypeDef *i2c = i2cp->i2c;
- intstate_t state = i2cp->intstate;
-
- /* check if we're master or slave */
- if (i2c->C1 & I2Cx_C1_MST) {
- /* master */
-
- if (i2c->S & I2Cx_S_ARBL) {
- /* check if we lost arbitration */
- i2cp->errors |= I2C_ARBITRATION_LOST;
- i2c->S |= I2Cx_S_ARBL;
- /* TODO: may need to do more here, reset bus? */
- /* Perhaps clear MST? */
- }
-
-#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
- else if ((i2cp->rsta_workaround == RSTA_WORKAROUND_ON) && (i2cp->i2c->FLT & I2Cx_FLT_STARTF)) {
- i2cp->rsta_workaround = RSTA_WORKAROUND_OFF;
- /* clear+disable STARTF/STOPF interrupts and wake up the thread */
- i2cp->i2c->FLT |= I2Cx_FLT_STOPF|I2Cx_FLT_STARTF;
- i2cp->i2c->FLT &= ~I2Cx_FLT_SSIE;
- i2c->S |= I2Cx_S_IICIF;
- _i2c_wakeup_isr(i2cp);
- }
-#endif /* KL27Z RST workaround */
-
- else if (i2c->S & I2Cx_S_TCF) {
- /* just completed byte transfer */
- if (i2c->C1 & I2Cx_C1_TX) {
- /* the byte was transmitted */
-
- if (state == STATE_SEND) {
- /* currently sending stuff */
-
- if (i2c->S & I2Cx_S_RXAK) {
- /* slave did not ACK */
- i2cp->errors |= I2C_ACK_FAILURE;
- /* the thread will be woken up at the end of ISR and release the bus */
-
- } else if (i2cp->txbuf != NULL && i2cp->txidx < i2cp->txbytes) {
- /* slave ACK'd and we want to send more */
- i2c->D = i2cp->txbuf[i2cp->txidx++];
- } else {
- /* slave ACK'd and we are done sending */
- i2cp->intstate = STATE_STOP;
- /* this wakes up the waiting thread at the end of ISR */
- }
-
- } else if (state == STATE_RECV) {
- /* should be receiving stuff, so we've just sent the address */
-
- if (i2c->S & I2Cx_S_RXAK) {
- /* slave did not ACK */
- i2cp->errors |= I2C_ACK_FAILURE;
- /* the thread will be woken up and release the bus */
-
- } else {
- /* slave ACK'd, we should be receiving next */
- i2c->C1 &= ~I2Cx_C1_TX;
-
- if (i2cp->rxbytes > 1) {
- /* multi-byte read, send ACK after next transfer */
- i2c->C1 &= ~I2Cx_C1_TXAK;
- } else {
- /* only 1 byte remaining, send NAK */
- i2c->C1 |= I2Cx_C1_TXAK;
- }
-
- (void) i2c->D; /* dummy read; triggers next receive */
- }
-
- } /* possibly check other states here - should not happen! */
-
- } else {
- /* the byte was received */
-
- if (state == STATE_RECV) {
- /* currently receiving stuff */
- /* the received byte is now in D */
-
- if (i2cp->rxbytes > 1) {
- /* expecting at least one byte after this one */
- if (i2cp->rxidx == (i2cp->rxbytes - 2)) {
- /* expecting exactly one byte after this one, NAK that one */
- i2c->C1 |= I2Cx_C1_TXAK;
- } else {
- /* expecting more than one after this one, respond with ACK */
- i2c->C1 &= ~I2Cx_C1_TXAK;
- }
- }
-
- if (i2cp->rxidx == i2cp->rxbytes - 1) {
- /* D is the last byte we're expecting */
- /* release bus: switch to RX mode, send STOP */
- /* need to do it now otherwise the I2C module will wait for another byte */
- // delayMicroseconds(1);
- i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST);
- i2cp->intstate = STATE_STOP;
- /* this wakes up the waiting thread at the end of ISR */
- }
-
- /* get the data from D; this triggers the next receive */
- i2cp->rxbuf[i2cp->rxidx++] = i2c->D;
-
- // if (i2cp->rxidx == i2cp->rxbytes) {
- /* done receiving */
- // }
- } /* possibly check other states here - should not happen! */
- }
-
- } /* possibly check other interrupt flags here */
- } else {
- /* slave */
-
- /* Not implemented yet */
- }
-
- /* Reset other interrupt sources */
-#if defined(I2Cx_FLT_STOPF) /* extra flags on KL26Z and KL27Z */
- i2cp->i2c->FLT |= I2Cx_FLT_STOPF;
-#endif
-#if defined(I2Cx_FLT_STARTF) /* extra flags on KL27Z */
- i2cp->i2c->FLT |= I2Cx_FLT_STARTF;
-#endif
- /* Reset interrupt flag */
- i2c->S |= I2Cx_S_IICIF;
-
- if (i2cp->errors != I2C_NO_ERROR)
- _i2c_wakeup_error_isr(i2cp);
-
- if (i2cp->intstate == STATE_STOP)
- _i2c_wakeup_isr(i2cp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if KINETIS_I2C_USE_I2C0 || defined(__DOXYGEN__)
-
-OSAL_IRQ_HANDLER(KINETIS_I2C0_IRQ_VECTOR) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&I2CD1);
- OSAL_IRQ_EPILOGUE();
-}
-
-#endif
-
-#if KINETIS_I2C_USE_I2C1 || defined(__DOXYGEN__)
-
-OSAL_IRQ_HANDLER(KINETIS_I2C1_IRQ_VECTOR) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&I2CD2);
- OSAL_IRQ_EPILOGUE();
-}
-
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level I2C driver initialization.
- *
- * @notapi
- */
-void i2c_lld_init(void) {
-
-#if KINETIS_I2C_USE_I2C0
- i2cObjectInit(&I2CD1);
- I2CD1.thread = NULL;
- I2CD1.i2c = I2C0;
-#endif
-
-#if KINETIS_I2C_USE_I2C1
- i2cObjectInit(&I2CD2);
- I2CD2.thread = NULL;
- I2CD2.i2c = I2C1;
-#endif
-
-}
-
-/**
- * @brief Configures and activates the I2C peripheral.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_start(I2CDriver *i2cp) {
-
- if (i2cp->state == I2C_STOP) {
-
- /* TODO:
- * The PORT must be enabled somewhere. The PIN multiplexer
- * will map the I2C functionality to some PORT which must
- * than be enabled. The easier way is enabling all PORTs at
- * startup, which is currently being done in __early_init.
- */
-
-#if KINETIS_I2C_USE_I2C0
- if (&I2CD1 == i2cp) {
- SIM->SCGC4 |= SIM_SCGC4_I2C0;
- nvicEnableVector(I2C0_IRQn, KINETIS_I2C_I2C0_PRIORITY);
- }
-#endif
-
-#if KINETIS_I2C_USE_I2C1
- if (&I2CD2 == i2cp) {
- SIM->SCGC4 |= SIM_SCGC4_I2C1;
- nvicEnableVector(I2C1_IRQn, KINETIS_I2C_I2C1_PRIORITY);
- }
-#endif
-
- }
-
- config_frequency(i2cp);
- i2cp->i2c->C1 = I2Cx_C1_IICEN | I2Cx_C1_IICIE; // reset I2C, enable interrupts
- i2cp->i2c->S = I2Cx_S_IICIF | I2Cx_S_ARBL; // clear status flags just in case
- i2cp->intstate = STATE_STOP; // internal state
-}
-
-/**
- * @brief Deactivates the I2C peripheral.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_stop(I2CDriver *i2cp) {
-
- if (i2cp->state != I2C_STOP) {
-
- i2cp->i2c->C1 &= ~(I2Cx_C1_IICEN | I2Cx_C1_IICIE);
-
-#if KINETIS_I2C_USE_I2C0
- if (&I2CD1 == i2cp) {
- SIM->SCGC4 &= ~SIM_SCGC4_I2C0;
- nvicDisableVector(I2C0_IRQn);
- }
-#endif
-
-#if KINETIS_I2C_USE_I2C1
- if (&I2CD2 == i2cp) {
- SIM->SCGC4 &= ~SIM_SCGC4_I2C1;
- nvicDisableVector(I2C1_IRQn);
- }
-#endif
-
- }
-}
-
-static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr,
- const uint8_t *txbuf, size_t txbytes,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout) {
-
- msg_t msg;
- systime_t start, end;
-
- uint8_t op = (i2cp->intstate == STATE_SEND) ? 0 : 1;
-
- i2cp->errors = I2C_NO_ERROR;
- i2cp->addr = addr;
-
- i2cp->txbuf = txbuf;
- i2cp->txbytes = txbytes;
- i2cp->txidx = 0;
-
- i2cp->rxbuf = rxbuf;
- i2cp->rxbytes = rxbytes;
- i2cp->rxidx = 0;
-
-#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
- i2cp->rsta_workaround = RSTA_WORKAROUND_OFF;
-#endif /* KL27Z RST workaround */
-
- /* clear status flags */
-#if defined(I2Cx_FLT_STOPF) /* extra flags on KL26Z and KL27Z */
- i2cp->i2c->FLT |= I2Cx_FLT_STOPF;
-#endif
-#if defined(I2Cx_FLT_STARTF) /* extra flags on KL27Z */
- i2cp->i2c->FLT |= I2Cx_FLT_STARTF;
-#endif
- i2cp->i2c->S = I2Cx_S_IICIF|I2Cx_S_ARBL;
-
- /* acquire the bus */
- /* check to see if we already have the bus */
- if(i2cp->i2c->C1 & I2Cx_C1_MST) {
-
-#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
- /* need to wait for STARTF interrupt after issuing repeated start,
- * otherwise the double buffering mechanism sends the last sent byte
- * instead of the slave address.
- * https://community.freescale.com/thread/377611
- */
- i2cp->rsta_workaround = RSTA_WORKAROUND_ON;
- /* clear any interrupt bits and enable STARTF/STOPF interrupts */
- i2cp->i2c->FLT |= I2Cx_FLT_STOPF|I2Cx_FLT_STARTF;
- i2cp->i2c->S |= I2Cx_S_IICIF|I2Cx_S_ARBL;
- i2cp->i2c->FLT |= I2Cx_FLT_SSIE;
-#endif /* KL27Z RST workaround */
-
- /* send repeated start */
- i2cp->i2c->C1 |= I2Cx_C1_RSTA | I2Cx_C1_TX;
-
-#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
- /* wait for the STARTF interrupt */
- msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
- /* abort if this didn't go well (timed out) */
- if (msg != MSG_OK) {
- /* release bus - RX mode, send STOP */
- i2cp->i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST);
- return msg;
- }
-#endif /* KL27Z RST workaround */
-
- } else {
- /* unlock during the wait, so that tasks with
- * higher priority can get attention */
- osalSysUnlock();
-
- /* wait until the bus is released */
- /* Calculating the time window for the timeout on the busy bus condition.*/
- start = osalOsGetSystemTimeX();
- end = start + OSAL_MS2ST(KINETIS_I2C_BUSY_TIMEOUT);
-
- while(true) {
- osalSysLock();
- /* If the bus is not busy then the operation can continue, note, the
- loop is exited in the locked state.*/
- if(!(i2cp->i2c->S & I2Cx_S_BUSY))
- break;
- /* If the system time went outside the allowed window then a timeout
- condition is returned.*/
- if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) {
- return MSG_TIMEOUT;
- }
- osalSysUnlock();
- }
-
- /* send START */
- i2cp->i2c->C1 |= I2Cx_C1_MST|I2Cx_C1_TX;
- }
-
- /* send slave address */
- i2cp->i2c->D = addr << 1 | op;
-
- /* wait for the ISR to signal that the transmission (or receive if no transmission) phase is complete */
- msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
-
- /* FIXME */
- //if (i2cp->i2c->S & I2Cx_S_RXAK)
- // i2cp->errors |= I2C_ACK_FAILURE;
-
- /* the transmitting (or receiving if no transmission) phase has finished,
- * do we expect to receive something? */
- if (msg == MSG_OK && rxbuf != NULL && rxbytes > 0 && i2cp->rxidx < rxbytes) {
-
-#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
- /* the same KL27Z RST workaround as above */
- i2cp->rsta_workaround = RSTA_WORKAROUND_ON;
- /* clear any interrupt bits and enable STARTF/STOPF interrupts */
- i2cp->i2c->FLT |= I2Cx_FLT_STOPF|I2Cx_FLT_STARTF;
- i2cp->i2c->S |= I2Cx_S_IICIF|I2Cx_S_ARBL;
- i2cp->i2c->FLT |= I2Cx_FLT_SSIE;
-#endif /* KL27Z RST workaround */
-
- /* send repeated start */
- i2cp->i2c->C1 |= I2Cx_C1_RSTA;
-
-#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
- /* wait for the STARTF interrupt */
- msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
- /* abort if this didn't go well (timed out) */
- if (msg != MSG_OK) {
- /* release bus - RX mode, send STOP */
- i2cp->i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST);
- return msg;
- }
-#endif /* KL27Z RST workaround */
-
- /* FIXME */
- // while (!(i2cp->i2c->S & I2Cx_S_BUSY));
-
- i2cp->intstate = STATE_RECV;
- i2cp->i2c->D = i2cp->addr << 1 | 1;
-
- msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
- }
-
- /* release bus - RX mode, send STOP */
- // other kinetis I2C drivers wait here for 1us. is this needed?
- i2cp->i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST);
- /* FIXME */
- // while (i2cp->i2c->S & I2Cx_S_BUSY);
-
- return msg;
-}
-
-/**
- * @brief Receives data via the I2C bus as master.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] addr slave device address
- * @param[out] rxbuf pointer to the receive buffer
- * @param[in] rxbytes number of bytes to be received
- * @param[in] timeout the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval MSG_OK if the function succeeded.
- * @retval MSG_RESET if one or more I2C errors occurred, the errors can
- * be retrieved using @p i2cGetErrors().
- * @retval MSG_TIMEOUT if a timeout occurred before operation end. <b>After a
- * timeout the driver must be stopped and restarted
- * because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout) {
-
- i2cp->intstate = STATE_RECV;
- return _i2c_txrx_timeout(i2cp, addr, NULL, 0, rxbuf, rxbytes, timeout);
-}
-
-/**
- * @brief Transmits data via the I2C bus as master.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] addr slave device address
- * @param[in] txbuf pointer to the transmit buffer
- * @param[in] txbytes number of bytes to be transmitted
- * @param[out] rxbuf pointer to the receive buffer
- * @param[in] rxbytes number of bytes to be received
- * @param[in] timeout the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval MSG_OK if the function succeeded.
- * @retval MSG_RESET if one or more I2C errors occurred, the errors can
- * be retrieved using @p i2cGetErrors().
- * @retval MSG_TIMEOUT if a timeout occurred before operation end. <b>After a
- * timeout the driver must be stopped and restarted
- * because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
- const uint8_t *txbuf, size_t txbytes,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout) {
-
- i2cp->intstate = STATE_SEND;
- return _i2c_txrx_timeout(i2cp, addr, txbuf, txbytes, rxbuf, rxbytes, timeout);
-}
-
-#endif /* HAL_USE_I2C */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h deleted file mode 100644 index bfc5008..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h +++ /dev/null @@ -1,247 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/LLD/i2c_lld.h
- * @brief KINETIS I2C subsystem low level driver header.
- *
- * @addtogroup I2C
- * @{
- */
-
-#ifndef HAL_I2C_LLD_H_
-#define HAL_I2C_LLD_H_
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-#define STATE_STOP 0x00
-#define STATE_SEND 0x01
-#define STATE_RECV 0x02
-
-#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
-#define RSTA_WORKAROUND_OFF 0x00
-#define RSTA_WORKAROUND_ON 0x01
-#endif /* KL27Z RST workaround */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief I2C0 driver enable switch.
- * @details If set to @p TRUE the support for I2C0 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(KINETIS_I2C_USE_I2C0) || defined(__DOXYGEN__)
-#define KINETIS_I2C_USE_I2C0 FALSE
-#endif
-
-/**
- * @brief I2C1 driver enable switch.
- * @details If set to @p TRUE the support for I2C1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(KINETIS_I2C_USE_I2C1) || defined(__DOXYGEN__)
-#define KINETIS_I2C_USE_I2C1 FALSE
-#endif
-/** @} */
-
-/**
- * @brief I2C0 interrupt priority level setting.
- */
-#if !defined(KINETIS_I2C_I2C0_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_I2C_I2C0_PRIORITY 12
-#endif
-
-/**
- * @brief I2C1 interrupt priority level setting.
- */
-#if !defined(KINETIS_I2C_I2C1_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_I2C_I2C1_PRIORITY 12
-#endif
-
-/**
- * @brief Timeout for external clearing BUSY bus (in ms).
- */
-#if !defined(KINETIS_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__)
-#define KINETIS_I2C_BUSY_TIMEOUT 50
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/** @brief error checks */
-#if KINETIS_I2C_USE_I2C0 && !KINETIS_HAS_I2C0
-#error "I2C0 not present in the selected device"
-#endif
-
-#if KINETIS_I2C_USE_I2C1 && !KINETIS_HAS_I2C1
-#error "I2C1 not present in the selected device"
-#endif
-
-
-#if !(KINETIS_I2C_USE_I2C0 || KINETIS_I2C_USE_I2C1)
-#error "I2C driver activated but no I2C peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/* @brief Type representing I2C address. */
-typedef uint8_t i2caddr_t;
-
-/* @brief Type of I2C Driver condition flags. */
-typedef uint32_t i2cflags_t;
-
-/* @brief Type used to control the ISR state machine. */
-typedef uint8_t intstate_t;
-
-/**
- * @brief Driver configuration structure.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
-
- /* @brief Clock to be used for the I2C bus. */
- uint32_t clock;
-
-} I2CConfig;
-
-/**
- * @brief Type of a structure representing an I2C driver.
- */
-typedef struct I2CDriver I2CDriver;
-
-/**
- * @brief Structure representing an I2C driver.
- */
-struct I2CDriver {
- /**
- * @brief Driver state.
- */
- i2cstate_t state;
- /**
- * @brief Current configuration data.
- */
- const I2CConfig *config;
- /**
- * @brief Error flags.
- */
- i2cflags_t errors;
-#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the bus.
- */
- mutex_t mutex;
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
-#if defined(I2C_DRIVER_EXT_FIELDS)
- I2C_DRIVER_EXT_FIELDS
-#endif
- /* @brief Thread waiting for I/O completion. */
- thread_reference_t thread;
- /* @brief Current slave address without R/W bit. */
- i2caddr_t addr;
-
- /* End of the mandatory fields.*/
-
- /* @brief Pointer to the buffer with data to send. */
- const uint8_t *txbuf;
- /* @brief Number of bytes of data to send. */
- size_t txbytes;
- /* @brief Current index in buffer when sending data. */
- size_t txidx;
- /* @brief Pointer to the buffer to put received data. */
- uint8_t *rxbuf;
- /* @brief Number of bytes of data to receive. */
- size_t rxbytes;
- /* @brief Current index in buffer when receiving data. */
- size_t rxidx;
- /* @brief Tracks current ISR state. */
- intstate_t intstate;
- /* @brief Low-level register access. */
- I2C_TypeDef *i2c;
-#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
- /* @brief Auxiliary variable for KL27Z repeated start workaround. */
- intstate_t rsta_workaround;
-#endif /* KL27Z RST workaround */
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Get errors from I2C driver.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-
-#if KINETIS_I2C_USE_I2C0
-extern I2CDriver I2CD1;
-#endif
-
-#if KINETIS_I2C_USE_I2C1
-extern I2CDriver I2CD2;
-#endif
-
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void i2c_lld_init(void);
- void i2c_lld_start(I2CDriver *i2cp);
- void i2c_lld_stop(I2CDriver *i2cp);
- msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
- const uint8_t *txbuf, size_t txbytes,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout);
- msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_I2C */
-
-#endif /* HAL_I2C_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_pal_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_pal_lld.c deleted file mode 100644 index 51f8a2e..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_pal_lld.c +++ /dev/null @@ -1,245 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/LLD/pal_lld.c
- * @brief PAL subsystem low level driver.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "osal.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Reads a logical state from an I/O pad.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @return The logical state.
- * @retval PAL_LOW low logical state.
- * @retval PAL_HIGH high logical state.
- *
- * @notapi
- */
-uint8_t _pal_lld_readpad(ioportid_t port,
- uint8_t pad) {
-
- return (port->PDIR & ((uint32_t) 1 << pad)) ? PAL_HIGH : PAL_LOW;
-}
-
-/**
- * @brief Writes a logical state on an output pad.
- * @note This function is not meant to be invoked directly by the
- * application code.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] bit logical value, the value must be @p PAL_LOW or
- * @p PAL_HIGH
- *
- * @notapi
- */
-void _pal_lld_writepad(ioportid_t port,
- uint8_t pad,
- uint8_t bit) {
-
- if (bit == PAL_HIGH)
- port->PDOR |= ((uint32_t) 1 << pad);
- else
- port->PDOR &= ~((uint32_t) 1 << pad);
-}
-
-/**
- * @brief Pad mode setup.
- * @details This function programs a pad with the specified mode.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] mode pad mode
- *
- * @notapi
- */
-void _pal_lld_setpadmode(ioportid_t port,
- uint8_t pad,
- iomode_t mode) {
-
- PORT_TypeDef *portcfg = NULL;
-
- osalDbgAssert(pad < PADS_PER_PORT, "pal_lld_setpadmode() #1, invalid pad");
-
- if (mode == PAL_MODE_OUTPUT_PUSHPULL)
- port->PDDR |= ((uint32_t) 1 << pad);
- else
- port->PDDR &= ~((uint32_t) 1 << pad);
-
- if (port == IOPORT1)
- portcfg = PORTA;
- else if (port == IOPORT2)
- portcfg = PORTB;
- else if (port == IOPORT3)
- portcfg = PORTC;
- else if (port == IOPORT4)
- portcfg = PORTD;
- else if (port == IOPORT5)
- portcfg = PORTE;
-
- osalDbgAssert(portcfg != NULL, "pal_lld_setpadmode() #2, invalid port");
-
- switch (mode) {
- case PAL_MODE_RESET:
- case PAL_MODE_INPUT:
- case PAL_MODE_OUTPUT_PUSHPULL:
- portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1);
- break;
-#if KINETIS_GPIO_HAS_OPENDRAIN
- case PAL_MODE_OUTPUT_OPENDRAIN:
- portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |
- PORTx_PCRn_ODE;
- break;
-#else
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-#endif
- case PAL_MODE_INPUT_PULLUP:
- portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |
- PORTx_PCRn_PE |
- PORTx_PCRn_PS;
- break;
- case PAL_MODE_INPUT_PULLDOWN:
- portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |
- PORTx_PCRn_PE;
- break;
- case PAL_MODE_UNCONNECTED:
- case PAL_MODE_INPUT_ANALOG:
- portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(0);
- break;
- case PAL_MODE_ALTERNATIVE_1:
- portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1);
- break;
- case PAL_MODE_ALTERNATIVE_2:
- portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(2);
- break;
- case PAL_MODE_ALTERNATIVE_3:
- portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(3);
- break;
- case PAL_MODE_ALTERNATIVE_4:
- portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(4);
- break;
- case PAL_MODE_ALTERNATIVE_5:
- portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(5);
- break;
- case PAL_MODE_ALTERNATIVE_6:
- portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(6);
- break;
- case PAL_MODE_ALTERNATIVE_7:
- portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(7);
- break;
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Kinetis I/O ports configuration.
- * @details Ports A-E clocks enabled.
- *
- * @param[in] config the Kinetis ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
- int i, j;
-
- /* Enable clocking on all Ports */
- SIM->SCGC5 |= SIM_SCGC5_PORTA |
- SIM_SCGC5_PORTB |
- SIM_SCGC5_PORTC |
- SIM_SCGC5_PORTD |
- SIM_SCGC5_PORTE;
-
- /* Initial PORT and GPIO setup */
- for (i = 0; i < TOTAL_PORTS; i++) {
- for (j = 0; j < PADS_PER_PORT; j++) {
- pal_lld_setpadmode(config->ports[i].port,
- j,
- config->ports[i].pads[j]);
- }
- }
-}
-
-/**
- * @brief Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- *
- * @param[in] port the port identifier
- * @param[in] mask the group mask
- * @param[in] mode the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode) {
-
- int i;
-
- (void)mask;
-
- for (i = 0; i < PADS_PER_PORT; i++) {
- pal_lld_setpadmode(port, i, mode);
- }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_pal_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_pal_lld.h deleted file mode 100644 index 833d95e..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_pal_lld.h +++ /dev/null @@ -1,423 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/LLD/pal_lld.h
- * @brief PAL subsystem low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef HAL_PAL_LLD_H_
-#define HAL_PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes */
-/*===========================================================================*/
-
-#define PAL_MODE_ALTERNATIVE_1 0x10
-#define PAL_MODE_ALTERNATIVE_2 0x11
-#define PAL_MODE_ALTERNATIVE_3 0x12
-#define PAL_MODE_ALTERNATIVE_4 0x13
-#define PAL_MODE_ALTERNATIVE_5 0x14
-#define PAL_MODE_ALTERNATIVE_6 0x15
-#define PAL_MODE_ALTERNATIVE_7 0x16
-
-#define PIN_MUX_ALTERNATIVE(x) PORTx_PCRn_MUX(x)
-
-/*===========================================================================*/
-/* I/O Ports Types and constants. */
-/*===========================================================================*/
-
-#define TOTAL_PORTS 5
-#define PADS_PER_PORT 32
-
-/**
- * @brief Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief Whole port mask.
- * @brief This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
-
-/**
- * @brief Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief Type of an I/O line.
- */
-typedef uint32_t ioline_t;
-
-/**
- * @brief Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- * any assumption about it, use the provided macros when populating
- * variables of this type.
- */
-typedef GPIO_TypeDef *ioportid_t;
-
-/**
- * @brief Port Configuration.
- * @details This structure stores the configuration parameters of all pads
- * belonging to a port.
- */
-typedef struct {
- ioportid_t port;
- iomode_t pads[PADS_PER_PORT];
-} PortConfig;
-
-/**
- * @brief Generic I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- * system startup time in order to initialized the digital I/O
- * subsystem. This represents only the initial setup, specific pads
- * or whole ports can be reprogrammed at later time.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- PortConfig ports[TOTAL_PORTS];
-} PALConfig;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers. */
-/*===========================================================================*/
-
-/**
- * @brief GPIO port A identifier.
- */
-#define IOPORT1 GPIOA
-
-/**
- * @brief GPIO port B identifier.
- */
-#define IOPORT2 GPIOB
-
-/**
- * @brief GPIO port C identifier.
- */
-#define IOPORT3 GPIOC
-
-/**
- * @brief GPIO port D identifier.
- */
-#define IOPORT4 GPIOD
-
-/**
- * @brief GPIO port E identifier.
- */
-#define IOPORT5 GPIOE
-
-/**
- * @name Line handling macros
- * @{
- */
-/**
- * @brief Forms a line identifier.
- * @details A port/pad pair are encoded into an @p ioline_t type. The encoding
- * of this type is platform-dependent.
- * @note In this driver the pad number is encoded in the byte of the GPIO
- * address that's zero on all Kinetis devices.
- */
-#define PAL_LINE(port, pad) \
- ((ioline_t)((uint32_t)(port) | ((uint32_t)(pad)<<20)))
-
-/**
- * @brief Decodes a port identifier from a line identifier.
- */
-#define PAL_PORT(line) \
- ((GPIO_TypeDef *)(((uint32_t)(line)) & 0xF00FFFFFU))
-
-/**
- * @brief Decodes a pad identifier from a line identifier.
- */
-#define PAL_PAD(line) \
- ((uint32_t)((uint32_t)(line) & 0x0FF00000U)>>20)
-
-/**
- * @brief Value identifying an invalid line.
- */
-#define PAL_NOLINE 0U
-/** @} */
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as */
-/* functions, if so please put them in pal_lld.c. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PAL subsystem initialization.
- *
- * @param[in] config architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief Reads the physical I/O port states.
- *
- * @param[in] port port identifier
- * @return The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) \
- (port)->PDIR
-
-/**
- * @brief Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- * value.
- *
- * @param[in] port port identifier
- * @return The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) \
- (port)->PDOR
-
-/**
- * @brief Writes a bits mask on a I/O port.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) \
- (port)->PDOR = (bits)
-
-/**
- * @brief Sets a bits mask on a I/O port.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) \
- (port)->PSOR = (bits)
-
-/**
- * @brief Clears a bits mask on a I/O port.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) \
- (port)->PCOR = (bits)
-
-/**
- * @brief Toggles a bits mask on a I/O port.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be toggled on the specified port
- *
- * @notapi
- */
-#define pal_lld_toggleport(port, bits) \
- (port)->PTOR = (bits)
-
-/**
- * @brief Reads a group of bits.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @return The group logical states.
- *
- * @notapi
- */
-#define pal_lld_readgroup(port, mask, offset) 0
-
-/**
- * @brief Writes a group of bits.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] bits bits to be written. Values exceeding the group width
- * are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits) (void)bits
-
-/**
- * @brief Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] mode group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode) \
- _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief Reads a logical state from an I/O pad.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @return The logical state.
- * @retval PAL_LOW low logical state.
- * @retval PAL_HIGH high logical state.
- *
- * @notapi
- */
-#define pal_lld_readpad(port, pad) _pal_lld_readpad(port, pad)
-
-/**
- * @brief Writes a logical state on an output pad.
- * @note This function is not meant to be invoked directly by the
- * application code.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] bit logical value, the value must be @p PAL_LOW or
- * @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit) _pal_lld_writepad(port, pad, bit)
-
-/**
- * @brief Sets a pad logical state to @p PAL_HIGH.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad) (port)->PSOR = ((uint32_t) 1 << (pad))
-
-/**
- * @brief Clears a pad logical state to @p PAL_LOW.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad) (port)->PCOR = ((uint32_t) 1 << (pad))
-
-/**
- * @brief Toggles a pad logical state.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_togglepad(port, pad) (port)->PTOR = ((uint32_t) 1 << (pad))
-
-/**
- * @brief Pad mode setup.
- * @details This function programs a pad with the specified mode.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] mode pad mode
- *
- * @notapi
- */
-#define pal_lld_setpadmode(port, pad, mode) \
- _pal_lld_setpadmode(port, pad, mode)
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void _pal_lld_init(const PALConfig *config);
- void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode);
- void _pal_lld_setpadmode(ioportid_t port,
- uint8_t pad,
- iomode_t mode);
- uint8_t _pal_lld_readpad(ioportid_t port,
- uint8_t pad);
- void _pal_lld_writepad(ioportid_t port,
- uint8_t pad,
- uint8_t bit);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* HAL_PAL_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_serial_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_serial_lld.c deleted file mode 100644 index c80cf22..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_serial_lld.c +++ /dev/null @@ -1,583 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/serial_lld.c
- * @brief Kinetis KL2x Serial Driver subsystem low level driver source.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "osal.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief SD1 driver identifier.
- */
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-SerialDriver SD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Driver default configuration.
- */
-static const SerialConfig default_config = {
- 38400
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-/**
- * @brief Error handling routine.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] isr UART s1 register value
- */
-static void set_error(SerialDriver *sdp, uint8_t s1) {
- eventflags_t sts = 0;
-
- if (s1 & UARTx_S1_OR)
- sts |= SD_OVERRUN_ERROR;
- if (s1 & UARTx_S1_PF)
- sts |= SD_PARITY_ERROR;
- if (s1 & UARTx_S1_FE)
- sts |= SD_FRAMING_ERROR;
- if (s1 & UARTx_S1_NF)
- sts |= SD_NOISE_ERROR;
- osalSysLockFromISR();
- chnAddFlagsI(sdp, sts);
- osalSysUnlockFromISR();
-}
-
-/**
- * @brief Common error IRQ handler.
- *
- * @param[in] sdp communication channel associated to the UART
- */
-static void serve_error_interrupt(SerialDriver *sdp) {
- UART_w_TypeDef *u = &(sdp->uart);
- uint8_t s1 = *(u->s1_p);
-
- /* S1 bits are write-1-to-clear for UART0 on KL2x. */
- /* Clearing on K20x and KL2x/UART>0 is done by reading S1 and
- * then reading D.*/
-
-#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
- if(sdp == &SD1) {
- if(s1 & UARTx_S1_IDLE) {
- *(u->s1_p) |= UARTx_S1_IDLE;
- }
-
- if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
- set_error(sdp, s1);
- *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
- }
- return;
- }
-#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */
-
- if(s1 & UARTx_S1_IDLE) {
- (void)*(u->d_p);
- }
-
- if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
- set_error(sdp, s1);
- (void)*(u->d_p);
- }
-}
-
-/**
- * @brief Common IRQ handler.
- * @note Tries hard to clear all the pending interrupt sources, we don't
- * want to go through the whole ISR and have another interrupt soon
- * after.
- *
- * @param[in] sdp communication channel associated to the UART
- */
-static void serve_interrupt(SerialDriver *sdp) {
- UART_w_TypeDef *u = &(sdp->uart);
- uint8_t s1 = *(u->s1_p);
-
- if (s1 & UARTx_S1_RDRF) {
- osalSysLockFromISR();
- if (iqIsEmptyI(&sdp->iqueue))
- chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
- if (iqPutI(&sdp->iqueue, *(u->d_p)) < Q_OK)
- chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
- osalSysUnlockFromISR();
- }
-
- if (s1 & UARTx_S1_TDRE) {
- msg_t b;
-
- osalSysLockFromISR();
- b = oqGetI(&sdp->oqueue);
- osalSysUnlockFromISR();
-
- if (b < Q_OK) {
- osalSysLockFromISR();
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- osalSysUnlockFromISR();
- *(u->c2_p) &= ~UARTx_C2_TIE;
- } else {
- *(u->d_p) = b;
- }
- }
-
- serve_error_interrupt(sdp);
-}
-
-/**
- * @brief Attempts a TX preload
- */
-static void preload(SerialDriver *sdp) {
- UART_w_TypeDef *u = &(sdp->uart);
-
- if (*(u->s1_p) & UARTx_S1_TDRE) {
- msg_t b = oqGetI(&sdp->oqueue);
- if (b < Q_OK) {
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- return;
- }
- *(u->d_p) = b;
- *(u->c2_p) |= UARTx_C2_TIE;
- }
-}
-
-/**
- * @brief Driver output notification.
- */
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD1);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify2(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD2);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-static void notify3(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD3);
-}
-#endif
-
-/**
- * @brief Common UART configuration.
- *
- */
-static void configure_uart(SerialDriver *sdp, const SerialConfig *config) {
-
- UART_w_TypeDef *uart = &(sdp->uart);
- uint32_t divisor;
-
- /* Discard any incoming data. */
- while (*(uart->s1_p) & UARTx_S1_RDRF) {
- (void)*(uart->d_p);
- }
-
- /* Disable UART while configuring */
- *(uart->c2_p) &= ~(UARTx_C2_RE | UARTx_C2_TE);
-
- /* The clock sources for various UARTs can be different. */
- divisor=KINETIS_BUSCLK_FREQUENCY;
-
-#if defined(KL2x)
-
-#if KINETIS_SERIAL_USE_UART0
- if (sdp == &SD1) {
- /* UART0 can be clocked from several sources on KL2x. */
- divisor = KINETIS_UART0_CLOCK_FREQ;
- /* FIXME: change fixed OSR = 16 to dynamic value based on baud */
- /* Note: OSR only works on KL2x/UART0; further UARTs have fixed 16. */
- *(uart->c4_p) = UARTx_C4_OSR(16 - 1);
- }
-#endif /* KINETIS_SERIAL_USE_UART0 */
-
-#elif defined(K20x) /* KL2x */
-
- /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x. */
-#if KINETIS_SERIAL_USE_UART0
- if(sdp == &SD1)
- divisor = KINETIS_SYSCLK_FREQUENCY;
-#endif /* KINETIS_SERIAL_USE_UART0 */
-#if KINETIS_SERIAL_USE_UART1
- if(sdp == &SD2)
- divisor = KINETIS_SYSCLK_FREQUENCY;
-#endif /* KINETIS_SERIAL_USE_UART1 */
-
-#else /* K20x */
-#error Baud rate selection not implemented for this MCU type
-#endif /* K20x */
-
- divisor = (divisor * 2 + 1) / config->sc_speed;
-
- *(uart->bdh_p) = UARTx_BDH_SBR(divisor >> 13) | (*(uart->bdh_p) & ~UARTx_BDH_SBR_MASK);
- *(uart->bdl_p) = UARTx_BDL_SBR(divisor >> 5);
-#if defined(K20x)
- *(uart->c4_p) = UARTx_C4_BRFA(divisor) | (*(uart->c4_p) & ~UARTx_C4_BRFA_MASK);
-#endif /* K20x */
-
- /* Line settings. */
- *(uart->c1_p) = 0;
- /* Enable error event interrupts (overrun, noise, framing, parity) */
- *(uart->c3_p) = UARTx_C3_ORIE | UARTx_C3_NEIE | UARTx_C3_FEIE | UARTx_C3_PEIE;
- /* Enable the peripheral; including receive interrupts. */
- *(uart->c2_p) |= UARTx_C2_RE | UARTx_C2_RIE | UARTx_C2_TE;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(KINETIS_SERIAL0_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD1);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(KINETIS_SERIAL1_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD2);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(KINETIS_SERIAL2_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&SD3);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if KINETIS_HAS_SERIAL_ERROR_IRQ
-
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(KINETIS_SERIAL0_ERROR_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
- serve_error_interrupt(&SD1);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(KINETIS_SERIAL1_ERROR_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
- serve_error_interrupt(&SD2);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(KINETIS_SERIAL2_ERROR_IRQ_VECTOR) {
- OSAL_IRQ_PROLOGUE();
- serve_error_interrupt(&SD3);
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if KINETIS_SERIAL_USE_UART0
- /* Driver initialization.*/
- sdObjectInit(&SD1, NULL, notify1);
-#if ! KINETIS_SERIAL0_IS_LPUART
- SD1.uart.bdh_p = &(UART0->BDH);
- SD1.uart.bdl_p = &(UART0->BDL);
- SD1.uart.c1_p = &(UART0->C1);
- SD1.uart.c2_p = &(UART0->C2);
- SD1.uart.c3_p = &(UART0->C3);
- SD1.uart.c4_p = &(UART0->C4);
- SD1.uart.s1_p = (volatile uint8_t *)&(UART0->S1);
- SD1.uart.s2_p = &(UART0->S2);
- SD1.uart.d_p = &(UART0->D);
-#else /* ! KINETIS_SERIAL0_IS_LPUART */
- /* little endian! */
- SD1.uart.bdh_p = ((uint8_t *)&(LPUART0->BAUD)) + 1; /* BDH: BAUD, byte 3 */
- SD1.uart.bdl_p = ((uint8_t *)&(LPUART0->BAUD)) + 0; /* BDL: BAUD, byte 4 */
- SD1.uart.c1_p = ((uint8_t *)&(LPUART0->CTRL)) + 0; /* C1: CTRL, byte 4 */
- SD1.uart.c2_p = ((uint8_t *)&(LPUART0->CTRL)) + 2; /* C2: CTRL, byte 2 */
- SD1.uart.c3_p = ((uint8_t *)&(LPUART0->CTRL)) + 3; /* C3: CTRL, byte 1 */
- SD1.uart.c4_p = ((uint8_t *)&(LPUART0->BAUD)) + 3; /* C4: BAUD, byte 1 */
- SD1.uart.s1_p = ((uint8_t *)&(LPUART0->STAT)) + 2; /* S1: STAT, byte 2 */
- SD1.uart.s2_p = ((uint8_t *)&(LPUART0->STAT)) + 3; /* S2: STAT, byte 1 */
- SD1.uart.d_p = ((uint8_t *)&(LPUART0->DATA)) + 0; /* D: DATA, byte 4 */
-#endif /* ! KINETIS_SERIAL0_IS_LPUART */
-#if KINETIS_SERIAL0_IS_UARTLP
- SD1.uart.uartlp_p = UART0;
- SD1.uart.uart_p = NULL;
-#elif KINETIS_SERIAL0_IS_LPUART
- SD1.uart.lpuart_p = LPUART0;
- SD1.uart.uart_p = NULL;
-#else /* KINETIS_SERIAL0_IS_LPUART */
- SD1.uart.uart_p = UART0;
-#endif /* KINETIS_SERIAL0_IS_LPUART */
-#endif /* KINETIS_SERIAL_USE_UART0 */
-
-#if KINETIS_SERIAL_USE_UART1
- /* Driver initialization.*/
- sdObjectInit(&SD2, NULL, notify2);
-#if ! KINETIS_SERIAL1_IS_LPUART
- SD2.uart.bdh_p = &(UART1->BDH);
- SD2.uart.bdl_p = &(UART1->BDL);
- SD2.uart.c1_p = &(UART1->C1);
- SD2.uart.c2_p = &(UART1->C2);
- SD2.uart.c3_p = &(UART1->C3);
- SD2.uart.c4_p = &(UART1->C4);
- SD2.uart.s1_p = (volatile uint8_t *)&(UART1->S1);
- SD2.uart.s2_p = &(UART1->S2);
- SD2.uart.d_p = &(UART1->D);
- SD2.uart.uart_p = UART1;
-#else /* ! KINETIS_SERIAL1_IS_LPUART */
- /* little endian! */
- SD2.uart.bdh_p = ((uint8_t *)&(LPUART1->BAUD)) + 1; /* BDH: BAUD, byte 3 */
- SD2.uart.bdl_p = ((uint8_t *)&(LPUART1->BAUD)) + 0; /* BDL: BAUD, byte 4 */
- SD2.uart.c1_p = ((uint8_t *)&(LPUART1->CTRL)) + 0; /* C1: CTRL, byte 4 */
- SD2.uart.c2_p = ((uint8_t *)&(LPUART1->CTRL)) + 2; /* C2: CTRL, byte 2 */
- SD2.uart.c3_p = ((uint8_t *)&(LPUART1->CTRL)) + 3; /* C3: CTRL, byte 1 */
- SD2.uart.c4_p = ((uint8_t *)&(LPUART1->BAUD)) + 3; /* C4: BAUD, byte 1 */
- SD2.uart.s1_p = ((uint8_t *)&(LPUART1->STAT)) + 2; /* S1: STAT, byte 2 */
- SD2.uart.s2_p = ((uint8_t *)&(LPUART1->STAT)) + 3; /* S2: STAT, byte 1 */
- SD2.uart.d_p = ((uint8_t *)&(LPUART1->DATA)) + 0; /* D: DATA, byte 4 */
- SD2.uart.lpuart_p = LPUART1;
- SD2.uart.uart_p = NULL;
-#endif /* ! KINETIS_SERIAL1_IS_LPUART */
-#endif /* KINETIS_SERIAL_USE_UART1 */
-
-#if KINETIS_SERIAL_USE_UART2
- /* Driver initialization.*/
- sdObjectInit(&SD3, NULL, notify3);
- SD3.uart.bdh_p = &(UART2->BDH);
- SD3.uart.bdl_p = &(UART2->BDL);
- SD3.uart.c1_p = &(UART2->C1);
- SD3.uart.c2_p = &(UART2->C2);
- SD3.uart.c3_p = &(UART2->C3);
- SD3.uart.c4_p = &(UART2->C4);
- SD3.uart.s1_p = (volatile uint8_t *)&(UART2->S1);
- SD3.uart.s2_p = &(UART2->S2);
- SD3.uart.d_p = &(UART2->D);
- SD3.uart.uart_p = UART2;
-#endif /* KINETIS_SERIAL_USE_UART2 */
-}
-
-/**
- * @brief Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration.
- * If this parameter is set to @p NULL then a default
- * configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
- if (config == NULL)
- config = &default_config;
-
- if (sdp->state == SD_STOP) {
- /* Enables the peripheral.*/
-
-#if KINETIS_SERIAL_USE_UART0
- if (sdp == &SD1) {
-#if KINETIS_SERIAL0_IS_LPUART
- SIM->SCGC5 |= SIM_SCGC5_LPUART0;
- SIM->SOPT2 =
- (SIM->SOPT2 & ~SIM_SOPT2_LPUART0SRC_MASK) |
- SIM_SOPT2_LPUART0SRC(KINETIS_UART0_CLOCK_SRC);
-#else /* KINETIS_SERIAL0_IS_LPUART */
- SIM->SCGC4 |= SIM_SCGC4_UART0;
-#endif /* KINETIS_SERIAL0_IS_LPUART */
-#if KINETIS_SERIAL0_IS_UARTLP
- SIM->SOPT2 =
- (SIM->SOPT2 & ~SIM_SOPT2_UART0SRC_MASK) |
- SIM_SOPT2_UART0SRC(KINETIS_UART0_CLOCK_SRC);
-#endif /* KINETIS_SERIAL0_IS_UARTLP */
- configure_uart(sdp, config);
-#if KINETIS_HAS_SERIAL_ERROR_IRQ
- nvicEnableVector(UART0Status_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
- nvicEnableVector(UART0Error_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
-#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
-#if KINETIS_SERIAL0_IS_LPUART
- nvicEnableVector(LPUART0_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
-#else /* KINETIS_SERIAL0_IS_LPUART */
- nvicEnableVector(UART0_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
-#endif /* KINETIS_SERIAL0_IS_LPUART */
-#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
- }
-#endif /* KINETIS_SERIAL_USE_UART0 */
-
-#if KINETIS_SERIAL_USE_UART1
- if (sdp == &SD2) {
-#if KINETIS_SERIAL1_IS_LPUART
- SIM->SCGC5 |= SIM_SCGC5_LPUART1;
- SIM->SOPT2 =
- (SIM->SOPT2 & ~SIM_SOPT2_LPUART1SRC_MASK) |
- SIM_SOPT2_LPUART1SRC(KINETIS_UART1_CLOCK_SRC);
-#else /* KINETIS_SERIAL1_IS_LPUART */
- SIM->SCGC4 |= SIM_SCGC4_UART1;
-#endif /* KINETIS_SERIAL1_IS_LPUART */
- configure_uart(sdp, config);
-#if KINETIS_HAS_SERIAL_ERROR_IRQ
- nvicEnableVector(UART1Status_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
- nvicEnableVector(UART1Error_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
-#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
-#if KINETIS_SERIAL1_IS_LPUART
- nvicEnableVector(LPUART1_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
-#else /* KINETIS_SERIAL1_IS_LPUART */
- nvicEnableVector(UART1_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
-#endif /* KINETIS_SERIAL1_IS_LPUART */
-#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
- }
-#endif /* KINETIS_SERIAL_USE_UART1 */
-
-#if KINETIS_SERIAL_USE_UART2
- if (sdp == &SD3) {
- SIM->SCGC4 |= SIM_SCGC4_UART2;
- configure_uart(sdp, config);
-#if KINETIS_HAS_SERIAL_ERROR_IRQ
- nvicEnableVector(UART2Status_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
- nvicEnableVector(UART2Error_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
-#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
- nvicEnableVector(UART2_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
-#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
- }
-#endif /* KINETIS_SERIAL_USE_UART2 */
-
- }
- /* Configures the peripheral.*/
-
-}
-
-/**
- * @brief Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- * interrupt vector.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
- if (sdp->state == SD_READY) {
- /* TODO: Resets the peripheral.*/
-
-#if KINETIS_SERIAL_USE_UART0
- if (sdp == &SD1) {
-#if KINETIS_HAS_SERIAL_ERROR_IRQ
- nvicDisableVector(UART0Status_IRQn);
- nvicDisableVector(UART0Error_IRQn);
-#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
-#if KINETIS_SERIAL0_IS_LPUART
- nvicDisableVector(LPUART0_IRQn);
-#else /* KINETIS_SERIAL0_IS_LPUART */
- nvicDisableVector(UART0_IRQn);
-#endif /* KINETIS_SERIAL0_IS_LPUART */
-#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
-#if KINETIS_SERIAL0_IS_LPUART
- SIM->SCGC5 &= ~SIM_SCGC5_LPUART0;
-#else /* KINETIS_SERIAL0_IS_LPUART */
- SIM->SCGC4 &= ~SIM_SCGC4_UART0;
-#endif /* KINETIS_SERIAL0_IS_LPUART */
- }
-#endif
-
-#if KINETIS_SERIAL_USE_UART1
- if (sdp == &SD2) {
-#if KINETIS_HAS_SERIAL_ERROR_IRQ
- nvicDisableVector(UART1Status_IRQn);
- nvicDisableVector(UART1Error_IRQn);
-#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
-#if KINETIS_SERIAL1_IS_LPUART
- nvicDisableVector(LPUART1_IRQn);
-#else /* KINETIS_SERIAL1_IS_LPUART */
- nvicDisableVector(UART1_IRQn);
-#endif /* KINETIS_SERIAL1_IS_LPUART */
-#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
-#if KINETIS_SERIAL1_IS_LPUART
- SIM->SCGC5 &= ~SIM_SCGC5_LPUART1;
-#else /* KINETIS_SERIAL1_IS_LPUART */
- SIM->SCGC4 &= ~SIM_SCGC4_UART1;
-#endif /* KINETIS_SERIAL1_IS_LPUART */
- }
-#endif
-
-#if KINETIS_SERIAL_USE_UART2
- if (sdp == &SD3) {
-#if KINETIS_HAS_SERIAL_ERROR_IRQ
- nvicDisableVector(UART2Status_IRQn);
- nvicDisableVector(UART2Error_IRQn);
-#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
- nvicDisableVector(UART2_IRQn);
-#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
- SIM->SCGC4 &= ~SIM_SCGC4_UART2;
- }
-#endif
- }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_serial_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_serial_lld.h deleted file mode 100644 index f11c063..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_serial_lld.h +++ /dev/null @@ -1,220 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KL2x/serial_lld.h
- * @brief Kinetis KL2x Serial Driver subsystem low level driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef HAL_SERIAL_LLD_H_
-#define HAL_SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief SD1 driver enable switch.
- * @details If set to @p TRUE the support for SD1 is included.
- */
-#if !defined(KINETIS_SERIAL_USE_UART0) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_USE_UART0 FALSE
-#endif
-/**
- * @brief SD2 driver enable switch.
- * @details If set to @p TRUE the support for SD2 is included.
- */
-#if !defined(KINETIS_SERIAL_USE_UART1) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_USE_UART1 FALSE
-#endif
-/**
- * @brief SD3 driver enable switch.
- * @details If set to @p TRUE the support for SD3 is included.
- */
-#if !defined(KINETIS_SERIAL_USE_UART2) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_USE_UART2 FALSE
-#endif
-
-/**
- * @brief UART0 interrupt priority level setting.
- */
-#if !defined(KINETIS_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_UART0_PRIORITY 12
-#endif
-
-/**
- * @brief UART1 interrupt priority level setting.
- */
-#if !defined(KINETIS_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_UART1_PRIORITY 12
-#endif
-
-/**
- * @brief UART2 interrupt priority level setting.
- */
-#if !defined(KINETIS_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_SERIAL_UART2_PRIORITY 12
-#endif
-
-/**
- * @brief UART0 clock source.
- */
-#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
-#define KINETIS_UART0_CLOCK_SRC 1 /* MCGFLLCLK clock, or MCGPLLCLK/2; or IRC48M */
-#endif
-
-/**
- * @brief UART1 clock source.
- */
-#if !defined(KINETIS_UART1_CLOCK_SRC) || defined(__DOXYGEN__)
-#define KINETIS_UART1_CLOCK_SRC 1 /* IRC48M */
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/** @brief error checks */
-#if KINETIS_SERIAL_USE_UART0 && !KINETIS_HAS_SERIAL0
-#error "UART0 not present in the selected device"
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 && !KINETIS_HAS_SERIAL1
-#error "UART1 not present in the selected device"
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 && !KINETIS_HAS_SERIAL2
-#error "UART2 not present in the selected device"
-#endif
-
-#if !(KINETIS_SERIAL_USE_UART0 || KINETIS_SERIAL_USE_UART1 || \
- KINETIS_SERIAL_USE_UART2)
-#error "Serial driver activated but no UART peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Generic Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- * in order to configure and start a serial driver operations.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- /**
- * @brief Bit rate.
- */
- uint32_t sc_speed;
- /* End of the mandatory fields.*/
-} SerialConfig;
-
-/**
- * @brief Generic UART register structure.
- * @note Individual UART register blocks (even within the same chip) can differ.
- */
-
-typedef struct {
- volatile uint8_t* bdh_p;
- volatile uint8_t* bdl_p;
- volatile uint8_t* c1_p;
- volatile uint8_t* c2_p;
- volatile uint8_t* c3_p;
- volatile uint8_t* c4_p;
- volatile uint8_t* s1_p;
- volatile uint8_t* s2_p;
- volatile uint8_t* d_p;
- UART_TypeDef *uart_p;
-#if KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_UARTLP
- UARTLP_TypeDef *uartlp_p;
-#endif /* KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_UARTLP */
-#if (KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_LPUART) \
- || (KINETIS_SERIAL_USE_UART1 && KINETIS_SERIAL1_IS_LPUART)
- LPUART_TypeDef *lpuart_p;
-#endif /* KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_LPUART */
-} UART_w_TypeDef;
-
-/**
- * @brief @p SerialDriver specific data.
- */
-#define _serial_driver_data \
- _base_asynchronous_channel_data \
- /* Driver state.*/ \
- sdstate_t state; \
- /* Input queue.*/ \
- input_queue_t iqueue; \
- /* Output queue.*/ \
- output_queue_t oqueue; \
- /* Input circular buffer.*/ \
- uint8_t ib[SERIAL_BUFFERS_SIZE]; \
- /* Output circular buffer.*/ \
- uint8_t ob[SERIAL_BUFFERS_SIZE]; \
- /* End of the mandatory fields.*/ \
- /* Pointer to the UART registers block.*/ \
- UART_w_TypeDef uart;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if KINETIS_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#if KINETIS_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void sd_lld_init(void);
- void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
- void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* HAL_SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_st_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_st_lld.c deleted file mode 100644 index e6ed9e5..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_st_lld.c +++ /dev/null @@ -1,98 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/LLD/st_lld.c
- * @brief ST Driver subsystem low level driver code.
- *
- * @addtogroup ST
- * @{
- */
-
-#include "hal.h"
-
-#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
-/**
- * @brief System Timer vector.
- * @details This interrupt is used for system tick in periodic mode.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(SysTick_Handler) {
-
- OSAL_IRQ_PROLOGUE();
-
- osalSysLockFromISR();
- osalOsTimerHandlerI();
- osalSysUnlockFromISR();
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ST driver initialization.
- *
- * @notapi
- */
-void st_lld_init(void) {
-#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
- /* Periodic systick mode, the Cortex-Mx internal systick timer is used
- in this mode.*/
- SysTick->LOAD = (KINETIS_SYSCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
- SysTick->VAL = 0;
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_ENABLE_Msk |
- SysTick_CTRL_TICKINT_Msk;
-
- /* IRQ enabled.*/
- nvicSetSystemHandlerPriority(HANDLER_SYSTICK, KINETIS_ST_IRQ_PRIORITY);
-#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
-}
-
-#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_st_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_st_lld.h deleted file mode 100644 index 29c7035..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_st_lld.h +++ /dev/null @@ -1,156 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/LLD/st_lld.h
- * @brief ST Driver subsystem low level driver header.
- * @details This header is designed to be include-able without having to
- * include other files from the HAL.
- *
- * @addtogroup ST
- * @{
- */
-
-#ifndef HAL_ST_LLD_H_
-#define HAL_ST_LLD_H_
-
-#include "mcuconf.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief SysTick timer IRQ priority.
- */
-#if !defined(KINETIS_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define KINETIS_ST_IRQ_PRIORITY 8
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void st_lld_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-/*===========================================================================*/
-/* Driver inline functions. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the time counter value.
- *
- * @return The counter value.
- *
- * @notapi
- */
-static inline systime_t st_lld_get_counter(void) {
-
- return (systime_t)0;
-}
-
-/**
- * @brief Starts the alarm.
- * @note Makes sure that no spurious alarms are triggered after
- * this call.
- *
- * @param[in] time the time to be set for the first alarm
- *
- * @notapi
- */
-static inline void st_lld_start_alarm(systime_t time) {
-
- (void)time;
-}
-
-/**
- * @brief Stops the alarm interrupt.
- *
- * @notapi
- */
-static inline void st_lld_stop_alarm(void) {
-
-}
-
-/**
- * @brief Sets the alarm time.
- *
- * @param[in] time the time to be set for the next alarm
- *
- * @notapi
- */
-static inline void st_lld_set_alarm(systime_t time) {
-
- (void)time;
-}
-
-/**
- * @brief Returns the current alarm time.
- *
- * @return The currently set alarm time.
- *
- * @notapi
- */
-static inline systime_t st_lld_get_alarm(void) {
-
- return (systime_t)0;
-}
-
-/**
- * @brief Determines if the alarm is active.
- *
- * @return The alarm status.
- * @retval false if the alarm is not active.
- * @retval true is the alarm is active
- *
- * @notapi
- */
-static inline bool st_lld_is_alarm_active(void) {
-
- return false;
-}
-
-#endif /* HAL_ST_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_usb_lld.c deleted file mode 100644 index e8d9778..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_usb_lld.c +++ /dev/null @@ -1,832 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde/
- (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/LLD/usb_lld.c
- * @brief KINETIS USB subsystem low level driver source.
- *
- * @addtogroup USB
- * @{
- */
-
-#include <string.h>
-
-#include "hal.h"
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief USB0 driver identifier.*/
-#if KINETIS_USB_USE_USB0 || defined(__DOXYGEN__)
-USBDriver USBD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief IN EP0 state.
- */
-USBInEndpointState ep0in;
-
-/**
- * @brief OUT EP0 state.
- */
-USBOutEndpointState ep0out;
-
-/**
- * @brief Buffer for the EP0 setup packets.
- */
-static uint8_t ep0setup_buffer[8];
-
-/**
- * @brief EP0 initialization structure.
- */
-static const USBEndpointConfig ep0config = {
- USB_EP_MODE_TYPE_CTRL,
- _usb_ep0setup,
- _usb_ep0in,
- _usb_ep0out,
- 64,
- 64,
- &ep0in,
- &ep0out,
- 1,
- ep0setup_buffer
-};
-
-/*
- * Buffer Descriptor Table (BDT)
- */
-
-/*
- * Buffer Descriptor (BD)
- * */
-typedef struct {
- uint32_t desc;
- uint8_t* addr;
-} bd_t;
-
-/*
- * Buffer Descriptor fields - p.889
- */
-#define BDT_OWN 0x80
-#define BDT_DATA 0x40
-#define BDT_KEEP 0x20
-#define BDT_NINC 0x10
-#define BDT_DTS 0x08
-#define BDT_STALL 0x04
-
-#define BDT_DESC(bc, data) (BDT_OWN | BDT_DTS | ((data&0x1)<<6) | ((bc) << 16))
-
-/*
- * BDT PID - p.891
- */
-#define BDT_PID_OUT 0x01
-#define BDT_PID_IN 0x09
-#define BDT_PID_SETUP 0x0D
-#define BDT_TOK_PID(n) (((n)>>2)&0xF)
-
-/*
- * BDT index fields
- */
-#define DATA0 0
-#define DATA1 1
-
-#define RX 0
-#define TX 1
-
-#define EVEN 0
-#define ODD 1
-
-#define BDT_INDEX(endpoint, tx, odd) (((endpoint)<<2) | ((tx)<<1) | (odd))
-/*
- * Get RX-ed/TX-ed bytes count from BDT entry
- */
-#define BDT_BC(n) (((n)>>16)&0x3FF)
-
-/* The USB-FS needs 2 BDT entry per endpoint direction
- * that adds to: 2*2*16 BDT entries for 16 bi-directional EP
- */
-static volatile bd_t _bdt[(KINETIS_USB_ENDPOINTS)*2*2] __attribute__((aligned(512)));
-
-/* FIXME later with dyn alloc
- * 16 EP
- * 2 directions per EP
- * 2 buffer per direction
- * => 64 buffers
- */
-static uint8_t _usbb[KINETIS_USB_ENDPOINTS*4][64] __attribute__((aligned(4)));
-static volatile uint8_t _usbbn=0;
-uint8_t* usb_alloc(uint8_t size)
-{
- (void)size;
- if(_usbbn < (KINETIS_USB_ENDPOINTS)*4)
- return _usbb[_usbbn++];
- while(1); /* Should not happen, ever */
-}
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/* Called from locked ISR. */
-void usb_packet_transmit(USBDriver *usbp, usbep_t ep, size_t n)
-{
- const USBEndpointConfig *epc = usbp->epc[ep];
- USBInEndpointState *isp = epc->in_state;
-
- bd_t *bd = (bd_t *)&_bdt[BDT_INDEX(ep, TX, isp->odd_even)];
-
- if (n > (size_t)epc->in_maxsize)
- n = (size_t)epc->in_maxsize;
-
- /* Copy from buf to _usbb[] */
- size_t i=0;
- for(i=0;i<n;i++)
- bd->addr[i] = isp->txbuf[i];
-
- /* Update the Buffer status */
- bd->desc = BDT_DESC(n, isp->data_bank);
- /* Toggle the odd and data bits for next TX */
- isp->data_bank ^= DATA1;
- isp->odd_even ^= ODD;
-}
-
-/* Called from locked ISR. */
-void usb_packet_receive(USBDriver *usbp, usbep_t ep, size_t n)
-{
- const USBEndpointConfig *epc = usbp->epc[ep];
- USBOutEndpointState *osp = epc->out_state;
-
- bd_t *bd = (bd_t *)&_bdt[BDT_INDEX(ep, RX, osp->odd_even)];
-
- if (n > (size_t)epc->out_maxsize)
- n = (size_t)epc->out_maxsize;
-
- /* Copy from _usbb[] to buf */
- size_t i=0;
- for(i=0;i<n;i++)
- osp->rxbuf[i] = bd->addr[i];
-
- /* Update the Buffer status
- * Set current buffer to same DATA bank and then toggle.
- * Since even/odd buffers are ping-pong and setup re-initialized them
- * this should work correctly */
- bd->desc = BDT_DESC(epc->out_maxsize, osp->data_bank);
- osp->data_bank ^= DATA1;
- usb_lld_start_out(usbp, ep);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*============================================================================*/
-
-#if KINETIS_USB_USE_USB0 || defined(__DOXYGEN__)
-/**
- * @brief USB interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(KINETIS_USB_IRQ_VECTOR) {
- USBDriver *usbp = &USBD1;
- uint8_t istat = USB0->ISTAT;
-
- OSAL_IRQ_PROLOGUE();
-
- /* 04 - Bit2 - Start Of Frame token received */
- if(istat & USBx_ISTAT_SOFTOK) {
- _usb_isr_invoke_sof_cb(usbp);
- USB0->ISTAT = USBx_ISTAT_SOFTOK;
- }
-
- /* 08 - Bit3 - Token processing completed */
- while(istat & USBx_ISTAT_TOKDNE) {
- uint8_t stat = USB0->STAT;
- uint8_t ep = stat >> 4;
- if(ep > KINETIS_USB_ENDPOINTS) {
- OSAL_IRQ_EPILOGUE();
- return;
- }
- const USBEndpointConfig *epc = usbp->epc[ep];
-
- /* Get the correct BDT entry */
- uint8_t odd_even = (stat & USBx_STAT_ODD_MASK) >> USBx_STAT_ODD_SHIFT;
- uint8_t tx_rx = (stat & USBx_STAT_TX_MASK) >> USBx_STAT_TX_SHIFT;
- bd_t *bd = (bd_t*)&_bdt[BDT_INDEX(ep,tx_rx,odd_even)];
-
- /* Update the ODD/EVEN state for RX */
- if(tx_rx == RX && epc->out_state != NULL)
- epc->out_state->odd_even = odd_even;
-
- switch(BDT_TOK_PID(bd->desc))
- {
- case BDT_PID_SETUP: // SETUP
- {
- /* Clear any pending IN stuff */
- _bdt[BDT_INDEX(ep, TX, EVEN)].desc = 0;
- _bdt[BDT_INDEX(ep, TX, ODD)].desc = 0;
- /* Also in the chibios state machine */
- (usbp)->receiving &= ~1;
- /* After a SETUP, IN is always DATA1 */
- usbp->epc[ep]->in_state->data_bank = DATA1;
-
- /* Call SETUP function (ChibiOS core), which sends back stuff */
- _usb_isr_invoke_setup_cb(usbp, ep);
- /* Buffer is released by the above callback. */
- /* from Paul: "unfreeze the USB, now that we're ready" */
- USB0->CTL = USBx_CTL_USBENSOFEN;
- } break;
- case BDT_PID_IN: // IN
- {
- if(epc->in_state == NULL)
- break;
- /* Special case for SetAddress for EP0 */
- if(ep == 0 && (((uint16_t)usbp->setup[0]<<8)|usbp->setup[1]) == 0x0500)
- {
- usbp->address = usbp->setup[2];
- usb_lld_set_address(usbp);
- _usb_isr_invoke_event_cb(usbp, USB_EVENT_ADDRESS);
- usbp->state = USB_SELECTED;
- }
- uint16_t txed = BDT_BC(bd->desc);
- epc->in_state->txcnt += txed;
- if(epc->in_state->txcnt < epc->in_state->txsize)
- {
- epc->in_state->txbuf += txed;
- osalSysLockFromISR();
- usb_packet_transmit(usbp,ep,epc->in_state->txsize - epc->in_state->txcnt);
- osalSysUnlockFromISR();
- }
- else
- {
- if(epc->in_cb != NULL)
- _usb_isr_invoke_in_cb(usbp,ep);
- }
- } break;
- case BDT_PID_OUT: // OUT
- {
- if(epc->out_state == NULL)
- break;
- uint16_t rxed = BDT_BC(bd->desc);
-
- osalSysLockFromISR();
- usb_packet_receive(usbp,ep,rxed);
- osalSysUnlockFromISR();
- if(rxed)
- {
- epc->out_state->rxbuf += rxed;
-
- /* Update transaction data */
- epc->out_state->rxcnt += rxed;
- epc->out_state->rxsize -= rxed;
- epc->out_state->rxpkts -= 1;
-
- /* The transaction is completed if the specified number of packets
- has been received or the current packet is a short packet.*/
- if ((rxed < epc->out_maxsize) || (epc->out_state->rxpkts == 0))
- {
- if(epc->out_cb != NULL)
- _usb_isr_invoke_out_cb(usbp, ep);
- }
- }
- } break;
- default:
- break;
- }
- USB0->ISTAT = USBx_ISTAT_TOKDNE;
- istat = USB0->ISTAT;
- }
-
- /* 01 - Bit0 - Valid USB Reset received */
- if(istat & USBx_ISTAT_USBRST) {
- _usb_reset(usbp);
- USB0->ISTAT = USBx_ISTAT_USBRST;
- OSAL_IRQ_EPILOGUE();
- return;
- }
-
- /* 80 - Bit7 - STALL handshake received */
- if(istat & USBx_ISTAT_STALL) {
- USB0->ISTAT = USBx_ISTAT_STALL;
- }
-
- /* 02 - Bit1 - ERRSTAT condition triggered */
- if(istat & USBx_ISTAT_ERROR) {
- uint8_t err = USB0->ERRSTAT;
- USB0->ERRSTAT = err;
- USB0->ISTAT = USBx_ISTAT_ERROR;
- }
-
- /* 10 - Bit4 - Constant IDLE on USB bus detected */
- if(istat & USBx_ISTAT_SLEEP) {
- /* This seems to fire a few times before the device is
- * configured - need to ignore those occurences somehow. */
- /* The other option would be to only activate INTEN_SLEEPEN
- * on CONFIGURED event, but that would need to be done in
- * user firmware. */
- if(usbp->state == USB_ACTIVE) {
- _usb_suspend(usbp);
- /* Enable interrupt on resume */
- USB0->INTEN |= USBx_INTEN_RESUMEEN;
- }
-
- // low-power version (check!):
- // enable wakeup interrupt on resume USB signaling
- // (check that it was a wakeup int with USBx_USBTRC0_USB_RESUME_INT)
- //? USB0->USBTRC0 |= USBx_USBTRC0_USBRESMEN
- // suspend the USB module
- //? USB0->USBCTRL |= USBx_USBCTRL_SUSP;
-
- USB0->ISTAT = USBx_ISTAT_SLEEP;
- }
-
- /* 20 - Bit5 - Resume - Only allowed in sleep=suspend mode */
- if(istat & USBx_ISTAT_RESUME) {
- /* Disable interrupt on resume (should be disabled
- * during normal operation according to datasheet). */
- USB0->INTEN &= ~USBx_INTEN_RESUMEEN;
-
- // low power version (check!):
- // desuspend the USB module
- //? USB0->USBCTRL &= ~USBx_USBCTRL_SUSP;
- // maybe also
- //? USB0->CTL = USBx_CTL_USBENSOFEN;
- _usb_wakeup(usbp);
- USB0->ISTAT = USBx_ISTAT_RESUME;
- }
-
- /* 40 - Bit6 - ATTACH - used */
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* KINETIS_USB_USE_USB0 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level USB driver initialization.
- *
- * @notapi
- */
-void usb_lld_init(void) {
- /* Driver initialization.*/
- usbObjectInit(&USBD1);
-
-#if KINETIS_USB_USE_USB0
-
- SIM->SOPT2 |= SIM_SOPT2_USBSRC;
-
-#if defined(K20x5) || defined(K20x7)
-
-#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
-
- /* MCGOUTCLK is the SYSCLK frequency, so don't divide for USB clock */
- SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
-
-#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
-
- #define KINETIS_USBCLK_FREQUENCY 48000000UL
- uint32_t i,j;
- for(i=0; i < 2; i++) {
- for(j=0; j < 8; j++) {
- if((KINETIS_PLLCLK_FREQUENCY * (i+1)) == (KINETIS_USBCLK_FREQUENCY*(j+1))) {
- SIM->CLKDIV2 = i | SIM_CLKDIV2_USBDIV(j);
- goto usbfrac_match_found;
- }
- }
- }
- usbfrac_match_found:
- osalDbgAssert(i<2 && j <8,"USB Init error");
-
-#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
-#error USB clock setting not implemented for this KINETIS_MCG_MODE
-#endif /* KINETIS_MCG_MODE == ... */
-
-#elif defined(KL25) || defined (KL26) || defined(KL27)
-
- /* No extra clock dividers for USB clock */
-
-#else /* defined(KL25) || defined (KL26) || defined(KL27) */
-#error USB driver not implemented for your MCU type
-#endif
-
-#endif /* KINETIS_USB_USE_USB0 */
-}
-
-/**
- * @brief Configures and activates the USB peripheral.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_start(USBDriver *usbp) {
- if (usbp->state == USB_STOP) {
-#if KINETIS_USB_USE_USB0
- if (&USBD1 == usbp) {
- /* Clear BDT */
- uint8_t i;
- for(i=0;i<KINETIS_USB_ENDPOINTS;i++) {
- _bdt[i].desc=0;
- _bdt[i].addr=0;
- }
-
- /* Enable Clock */
-#if KINETIS_USB0_IS_USBOTG
- SIM->SCGC4 |= SIM_SCGC4_USBOTG;
-#else /* KINETIS_USB0_IS_USBOTG */
- SIM->SCGC4 |= SIM_SCGC4_USBFS;
-#endif /* KINETIS_USB0_IS_USBOTG */
-
-#if KINETIS_HAS_USB_CLOCK_RECOVERY
- USB0->CLK_RECOVER_IRC_EN |= USBx_CLK_RECOVER_IRC_EN_IRC_EN;
- USB0->CLK_RECOVER_CTRL |= USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN;
-#endif /* KINETIS_HAS_USB_CLOCK_RECOVERY */
-
- /* Reset USB module, wait for completion */
- USB0->USBTRC0 |= USBx_USBTRC0_USBRESET;
- while ((USB0->USBTRC0 & USBx_USBTRC0_USBRESET));
-
- /* Set BDT Address */
- USB0->BDTPAGE1 = ((uint32_t)_bdt) >> 8;
- USB0->BDTPAGE2 = ((uint32_t)_bdt) >> 16;
- USB0->BDTPAGE3 = ((uint32_t)_bdt) >> 24;
-
- /* Clear all ISR flags */
- USB0->ISTAT = 0xFF;
- USB0->ERRSTAT = 0xFF;
-#if KINETIS_USB0_IS_USBOTG
- USB0->OTGISTAT = 0xFF;
-#endif /* KINETIS_USB0_IS_USBOTG */
- USB0->USBTRC0 |= 0x40; //a hint was given that this is an undocumented interrupt bit
-
- /* Enable USB */
- USB0->CTL = USBx_CTL_ODDRST | USBx_CTL_USBENSOFEN;
- USB0->USBCTRL = 0;
-
- /* Enable reset interrupt */
- USB0->INTEN |= USBx_INTEN_USBRSTEN;
-
- /* Enable interrupt in NVIC */
-#if KINETIS_USB0_IS_USBOTG
- nvicEnableVector(USB_OTG_IRQn, KINETIS_USB_USB0_IRQ_PRIORITY);
-#else /* KINETIS_USB0_IS_USBOTG */
- nvicEnableVector(USB_IRQn, KINETIS_USB_USB0_IRQ_PRIORITY);
-#endif /* KINETIS_USB0_IS_USBOTG */
- }
-#endif /* KINETIS_USB_USE_USB0 */
- }
-}
-
-/**
- * @brief Deactivates the USB peripheral.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_stop(USBDriver *usbp) {
- /* TODO: If in ready state then disables the USB clock.*/
- if (usbp->state == USB_STOP) {
-#if KINETIS_USB_USE_USB0
- if (&USBD1 == usbp) {
-#if KINETIS_USB0_IS_USBOTG
- nvicDisableVector(USB_OTG_IRQn);
-#else /* KINETIS_USB0_IS_USBOTG */
- nvicDisableVector(USB_IRQn);
-#endif /* KINETIS_USB0_IS_USBOTG */
- }
-#endif /* KINETIS_USB_USE_USB0 */
- }
-}
-
-/**
- * @brief USB low level reset routine.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_reset(USBDriver *usbp) {
- // FIXME, dyn alloc
- _usbbn = 0;
-
-#if KINETIS_USB_USE_USB0
-
- /* Reset BDT ODD/EVEN bits */
- USB0->CTL = USBx_CTL_ODDRST;
-
- /* EP0 initialization.*/
- usbp->epc[0] = &ep0config;
- usb_lld_init_endpoint(usbp, 0);
-
- /* Clear all pending interrupts */
- USB0->ERRSTAT = 0xFF;
- USB0->ISTAT = 0xFF;
-
- /* Set the address to zero during enumeration */
- usbp->address = 0;
- USB0->ADDR = 0;
-
- /* Enable other interrupts */
- USB0->ERREN = 0xFF;
- USB0->INTEN = USBx_INTEN_TOKDNEEN |
- USBx_INTEN_SOFTOKEN |
- USBx_INTEN_STALLEN |
- USBx_INTEN_ERROREN |
- USBx_INTEN_USBRSTEN |
- USBx_INTEN_SLEEPEN;
-
- /* "is this necessary?", Paul from PJRC */
- USB0->CTL = USBx_CTL_USBENSOFEN;
-#endif /* KINETIS_USB_USE_USB0 */
-}
-
-/**
- * @brief Sets the USB address.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_set_address(USBDriver *usbp) {
-
-#if KINETIS_USB_USE_USB0
- USB0->ADDR = usbp->address&0x7F;
-#endif /* KINETIS_USB_USE_USB0 */
-}
-
-/**
- * @brief Enables an endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
-
- if(ep > KINETIS_USB_ENDPOINTS)
- return;
-
- const USBEndpointConfig *epc = usbp->epc[ep];
- uint8_t mask=0;
-
- if(epc->out_state != NULL)
- {
- /* OUT Endpoint */
- epc->out_state->odd_even = EVEN;
- epc->out_state->data_bank = DATA0;
- /* RXe */
- _bdt[BDT_INDEX(ep, RX, EVEN)].desc = BDT_DESC(epc->out_maxsize, DATA0);
- _bdt[BDT_INDEX(ep, RX, EVEN)].addr = usb_alloc(epc->out_maxsize);
- /* RXo */
- _bdt[BDT_INDEX(ep, RX, ODD)].desc = BDT_DESC(epc->out_maxsize, DATA1);
- _bdt[BDT_INDEX(ep, RX, ODD)].addr = usb_alloc(epc->out_maxsize);
- /* Enable OUT direction */
- mask |= USBx_ENDPTn_EPRXEN;
- }
- if(epc->in_state != NULL)
- {
- /* IN Endpoint */
- epc->in_state->odd_even = EVEN;
- epc->in_state->data_bank = DATA0;
- /* TXe, not used yet */
- _bdt[BDT_INDEX(ep, TX, EVEN)].desc = 0;
- _bdt[BDT_INDEX(ep, TX, EVEN)].addr = usb_alloc(epc->in_maxsize);
- /* TXo, not used yet */
- _bdt[BDT_INDEX(ep, TX, ODD)].desc = 0;
- _bdt[BDT_INDEX(ep, TX, ODD)].addr = usb_alloc(epc->in_maxsize);
- /* Enable IN direction */
- mask |= USBx_ENDPTn_EPTXEN;
- }
-
- /* EPHSHK should be set for CTRL, BULK, INTR not for ISOC*/
- if((epc->ep_mode & USB_EP_MODE_TYPE) != USB_EP_MODE_TYPE_ISOC)
- mask |= USBx_ENDPTn_EPHSHK;
- /* Endpoint is not a CTRL endpoint, disable SETUP transfers */
- if((epc->ep_mode & USB_EP_MODE_TYPE) != USB_EP_MODE_TYPE_CTRL)
- mask |= USBx_ENDPTn_EPCTLDIS;
-
-#if KINETIS_USB_USE_USB0
- USB0->ENDPT[ep].V = mask;
-#endif /* KINETIS_USB_USE_USB0 */
-}
-
-/**
- * @brief Disables all the active endpoints except the endpoint zero.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- *
- * @notapi
- */
-void usb_lld_disable_endpoints(USBDriver *usbp) {
- (void)usbp;
- uint8_t i;
-#if KINETIS_USB_USE_USB0
- for(i=1;i<KINETIS_USB_ENDPOINTS;i++)
- USB0->ENDPT[i].V = 0;
-#endif /* KINETIS_USB_USE_USB0 */
-}
-
-/**
- * @brief Returns the status of an OUT endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @return The endpoint status.
- * @retval EP_STATUS_DISABLED The endpoint is not active.
- * @retval EP_STATUS_STALLED The endpoint is stalled.
- * @retval EP_STATUS_ACTIVE The endpoint is active.
- *
- * @notapi
- */
-usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
- (void)usbp;
-#if KINETIS_USB_USE_USB0
- if(ep > USB_MAX_ENDPOINTS)
- return EP_STATUS_DISABLED;
- if(!(USB0->ENDPT[ep].V & (USBx_ENDPTn_EPRXEN)))
- return EP_STATUS_DISABLED;
- else if(USB0->ENDPT[ep].V & USBx_ENDPTn_EPSTALL)
- return EP_STATUS_STALLED;
- return EP_STATUS_ACTIVE;
-#endif /* KINETIS_USB_USE_USB0 */
-}
-
-/**
- * @brief Returns the status of an IN endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @return The endpoint status.
- * @retval EP_STATUS_DISABLED The endpoint is not active.
- * @retval EP_STATUS_STALLED The endpoint is stalled.
- * @retval EP_STATUS_ACTIVE The endpoint is active.
- *
- * @notapi
- */
-usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
- (void)usbp;
- if(ep > USB_MAX_ENDPOINTS)
- return EP_STATUS_DISABLED;
-#if KINETIS_USB_USE_USB0
- if(!(USB0->ENDPT[ep].V & (USBx_ENDPTn_EPTXEN)))
- return EP_STATUS_DISABLED;
- else if(USB0->ENDPT[ep].V & USBx_ENDPTn_EPSTALL)
- return EP_STATUS_STALLED;
- return EP_STATUS_ACTIVE;
-#endif /* KINETIS_USB_USE_USB0 */
-}
-
-/**
- * @brief Reads a setup packet from the dedicated packet buffer.
- * @details This function must be invoked in the context of the @p setup_cb
- * callback in order to read the received setup packet.
- * @pre In order to use this function the endpoint must have been
- * initialized as a control endpoint.
- * @post The endpoint is ready to accept another packet.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @param[out] buf buffer where to copy the packet data
- *
- * @notapi
- */
-void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
- /* Get the BDT entry */
- USBOutEndpointState *os = usbp->epc[ep]->out_state;
- bd_t *bd = (bd_t*)&_bdt[BDT_INDEX(ep, RX, os->odd_even)];
- /* Copy the 8 bytes of data */
- uint8_t n;
- for (n = 0; n < 8; n++) {
- buf[n] = bd->addr[n];
- }
- /* Release the buffer
- * Setup packet is always DATA0
- * Initialize buffers so current expects DATA0 & opposite DATA1 */
- bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);
- _bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)].desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
- os->data_bank = DATA1;
-}
-
-/**
- * @brief Starts a receive operation on an OUT endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
- USBOutEndpointState *osp = usbp->epc[ep]->out_state;
- /* Transfer initialization.*/
- if (osp->rxsize == 0) /* Special case for zero sized packets.*/
- osp->rxpkts = 1;
- else
- osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) /
- usbp->epc[ep]->out_maxsize);
-}
-
-/**
- * @brief Starts a transmit operation on an IN endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @note Called from ISR and locked zone.
- * @notapi
- */
-void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
- (void)usbp;
- (void)ep;
- usb_packet_transmit(usbp,ep,usbp->epc[ep]->in_state->txsize);
-}
-
-/**
- * @brief Brings an OUT endpoint in the stalled state.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) {
- (void)usbp;
-#if KINETIS_USB_USE_USB0
- USB0->ENDPT[ep].V |= USBx_ENDPTn_EPSTALL;
-#endif /* KINETIS_USB_USE_USB0 */
-}
-
-/**
- * @brief Brings an IN endpoint in the stalled state.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) {
- (void)usbp;
-#if KINETIS_USB_USE_USB0
- USB0->ENDPT[ep].V |= USBx_ENDPTn_EPSTALL;
-#endif /* KINETIS_USB_USE_USB0 */
-}
-
-/**
- * @brief Brings an OUT endpoint in the active state.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) {
- (void)usbp;
-#if KINETIS_USB_USE_USB0
- USB0->ENDPT[ep].V &= ~USBx_ENDPTn_EPSTALL;
-#endif /* KINETIS_USB_USE_USB0 */
-}
-
-/**
- * @brief Brings an IN endpoint in the active state.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- *
- * @notapi
- */
-void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
- (void)usbp;
-#if KINETIS_USB_USE_USB0
- USB0->ENDPT[ep].V &= ~USBx_ENDPTn_EPSTALL;
-#endif /* KINETIS_USB_USE_USB0 */
-}
-
-#endif /* HAL_USE_USB */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_usb_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_usb_lld.h deleted file mode 100644 index 593ef16..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_usb_lld.h +++ /dev/null @@ -1,428 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde/
- (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file KINETIS/LLD/usb_lld.h
- * @brief KINETIS USB subsystem low level driver header.
- *
- * @addtogroup USB
- * @{
- */
-
-#ifndef HAL_USB_LLD_H_
-#define HAL_USB_LLD_H_
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Maximum endpoint address.
- */
-#define USB_MAX_ENDPOINTS 15
-
-/**
- * @brief Status stage handling method.
- */
-#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW
-
-/**
- * @brief Address ack handling
- */
-#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW
-
-/**
- * @brief This device requires the address change after the status packet.
- */
-#define USB_SET_ADDRESS_MODE USB_LATE_SET_ADDRESS
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @brief USB1 driver enable switch.
- * @details If set to @p TRUE the support for USB1 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(KINETIS_USB_USE_USB0) || defined(__DOXYGEN__)
-#define KINETIS_USB_USE_USB0 FALSE
-#endif
-
-/**
- * @brief USB1 interrupt priority level setting.
- */
-#if !defined(KINETIS_USB_USB0_IRQ_PRIORITY)|| defined(__DOXYGEN__)
-#define KINETIS_USB_USB0_IRQ_PRIORITY 5
-#endif
-
-#if !defined(KINETIS_USB_ENDPOINTS) || defined(__DOXYGEN__)
- #define KINETIS_USB_ENDPOINTS USB_MAX_ENDPOINTS+1
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if KINETIS_USB_USE_USB0 && !KINETIS_HAS_USB
-#error "USB not present in the selected device"
-#endif
-
-#if !KINETIS_USB_USE_USB0
-#error "USB driver activated but no USB peripheral assigned"
-#endif
-
-#if KINETIS_USB_USE_USB0 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_USB_USB0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to KINETIS_USB_USB0_IRQ_PRIORITY"
-#endif
-
-#if !defined(KINETIS_USB_IRQ_VECTOR)
-#error "KINETIS_USB_IRQ_VECTOR not defined"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of an IN endpoint state structure.
- */
-typedef struct {
- /**
- * @brief Requested transmit transfer size.
- */
- size_t txsize;
- /**
- * @brief Transmitted bytes so far.
- */
- size_t txcnt;
- /**
- * @brief Pointer to the transmission linear buffer.
- */
- const uint8_t *txbuf;
-#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- thread_reference_t thread;
-#endif
- /* End of the mandatory fields.*/
- /* */
- bool odd_even; /* ODD / EVEN */
- /* */
- bool data_bank; /* DATA0 / DATA1 */
-} USBInEndpointState;
-
-/**
- * @brief Type of an OUT endpoint state structure.
- */
-typedef struct {
- /**
- * @brief Requested receive transfer size.
- */
- size_t rxsize;
- /**
- * @brief Received bytes so far.
- */
- size_t rxcnt;
- /**
- * @brief Pointer to the receive linear buffer.
- */
- uint8_t *rxbuf;
-#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- thread_reference_t thread;
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Number of packets to receive.
- */
- uint16_t rxpkts;
- /* */
- bool odd_even; /* ODD / EVEN */
- /* */
- bool data_bank; /* DATA0 / DATA1 */
-} USBOutEndpointState;
-
-/**
- * @brief Type of an USB endpoint configuration structure.
- * @note Platform specific restrictions may apply to endpoints.
- */
-typedef struct {
- /**
- * @brief Type and mode of the endpoint.
- */
- uint32_t ep_mode;
- /**
- * @brief Setup packet notification callback.
- * @details This callback is invoked when a setup packet has been
- * received.
- * @post The application must immediately call @p usbReadPacket() in
- * order to access the received packet.
- * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL
- * endpoints, it should be set to @p NULL for other endpoint
- * types.
- */
- usbepcallback_t setup_cb;
- /**
- * @brief IN endpoint notification callback.
- * @details This field must be set to @p NULL if callback is not required.
- */
- usbepcallback_t in_cb;
- /**
- * @brief OUT endpoint notification callback.
- * @details This field must be set to @p NULL if callback is not required.
- */
- usbepcallback_t out_cb;
- /**
- * @brief IN endpoint maximum packet size.
- * @details This field must be set to zero if the IN endpoint is not used.
- */
- uint16_t in_maxsize;
- /**
- * @brief OUT endpoint maximum packet size.
- * @details This field must be set to zero if the OUT endpoint is not used.
- */
- uint16_t out_maxsize;
- /**
- * @brief @p USBEndpointState associated to the IN endpoint.
- * @details This field must be set to @p NULL if the IN endpoint is not
- * used.
- */
- USBInEndpointState *in_state;
- /**
- * @brief @p USBEndpointState associated to the OUT endpoint.
- * @details This field must be set to @p NULL if the OUT endpoint is not
- * used.
- */
- USBOutEndpointState *out_state;
- /* End of the mandatory fields.*/
- /**
- * @brief Reserved field, not currently used.
- * @note Initialize this field to 1 in order to be forward compatible.
- */
- uint16_t ep_buffers;
- /**
- * @brief Pointer to a buffer for setup packets.
- * @details Setup packets require a dedicated 8-bytes buffer, set this
- * field to @p NULL for non-control endpoints.
- */
- uint8_t *setup_buf;
-} USBEndpointConfig;
-
-/**
- * @brief Type of an USB driver configuration structure.
- */
-typedef struct {
- /**
- * @brief USB events callback.
- * @details This callback is invoked when an USB driver event is registered.
- */
- usbeventcb_t event_cb;
- /**
- * @brief Device GET_DESCRIPTOR request callback.
- * @note This callback is mandatory and cannot be set to @p NULL.
- */
- usbgetdescriptor_t get_descriptor_cb;
- /**
- * @brief Requests hook callback.
- * @details This hook allows to be notified of standard requests or to
- * handle non standard requests.
- */
- usbreqhandler_t requests_hook_cb;
- /**
- * @brief Start Of Frame callback.
- */
- usbcallback_t sof_cb;
- /* End of the mandatory fields.*/
-} USBConfig;
-
-/**
- * @brief Structure representing an USB driver.
- */
-struct USBDriver {
- /**
- * @brief Driver state.
- */
- usbstate_t state;
- /**
- * @brief Current configuration data.
- */
- const USBConfig *config;
- /**
- * @brief Bit map of the transmitting IN endpoints.
- */
- uint16_t transmitting;
- /**
- * @brief Bit map of the receiving OUT endpoints.
- */
- uint16_t receiving;
- /**
- * @brief Active endpoints configurations.
- */
- const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1];
- /**
- * @brief Fields available to user, it can be used to associate an
- * application-defined handler to an IN endpoint.
- * @note The base index is one, the endpoint zero does not have a
- * reserved element in this array.
- */
- void *in_params[USB_MAX_ENDPOINTS];
- /**
- * @brief Fields available to user, it can be used to associate an
- * application-defined handler to an OUT endpoint.
- * @note The base index is one, the endpoint zero does not have a
- * reserved element in this array.
- */
- void *out_params[USB_MAX_ENDPOINTS];
- /**
- * @brief Endpoint 0 state.
- */
- usbep0state_t ep0state;
- /**
- * @brief Next position in the buffer to be transferred through endpoint 0.
- */
- uint8_t *ep0next;
- /**
- * @brief Number of bytes yet to be transferred through endpoint 0.
- */
- size_t ep0n;
- /**
- * @brief Endpoint 0 end transaction callback.
- */
- usbcallback_t ep0endcb;
- /**
- * @brief Setup packet buffer.
- */
- uint8_t setup[8];
- /**
- * @brief Current USB device status.
- */
- uint16_t status;
- /**
- * @brief Assigned USB address.
- */
- uint8_t address;
- /**
- * @brief Current USB device configuration.
- */
- uint8_t configuration;
-#if defined(USB_DRIVER_EXT_FIELDS)
- USB_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the next address in the packet memory.
- */
- uint32_t pmnext;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the current frame number.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @return The current frame number.
- *
- * @notapi
- */
-#define usb_lld_get_frame_number(usbp) ((USB0->FRMNUMH<<8)|USB0->FRMNUML)
-
-/**
- * @brief Returns the exact size of a receive transaction.
- * @details The received size can be different from the size specified in
- * @p usbStartReceiveI() because the last packet could have a size
- * different from the expected one.
- * @pre The OUT endpoint must have been configured in transaction mode
- * in order to use this function.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep endpoint number
- * @return Received data size.
- *
- * @notapi
- */
-#define usb_lld_get_transaction_size(usbp, ep) \
- ((usbp)->epc[ep]->out_state->rxcnt)
-
-/**
- * @brief Connects the USB device.
- *
- * @api
- */
-#if !defined(usb_lld_connect_bus)
-#define usb_lld_connect_bus(usbp) (USB0->CONTROL |= USBx_CONTROL_DPPULLUPNONOTG)
-#endif
-
-/**
- * @brief Disconnect the USB device.
- *
- * @api
- */
-#if !defined(usb_lld_disconnect_bus)
-/* Writing to USB0->CONTROL causes an unhandled exception when USB module is not clocked. */
-#if KINETIS_USB0_IS_USBOTG
-#define usb_lld_disconnect_bus(usbp) if(SIM->SCGC4 & SIM_SCGC4_USBOTG) {USB0->CONTROL &= ~USBx_CONTROL_DPPULLUPNONOTG;} else {}
-#else /* KINETIS_USB0_IS_USBOTG */
-#define usb_lld_disconnect_bus(usbp) if(SIM->SCGC4 & SIM_SCGC4_USBFS) {USB0->CONTROL &= ~USBx_CONTROL_DPPULLUPNONOTG;} else {}
-#endif /* KINETIS_USB0_IS_USBOTG */
-#endif
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if KINETIS_USB_USE_USB0 && !defined(__DOXYGEN__)
-extern USBDriver USBD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void usb_lld_init(void);
- void usb_lld_start(USBDriver *usbp);
- void usb_lld_stop(USBDriver *usbp);
- void usb_lld_reset(USBDriver *usbp);
- void usb_lld_set_address(USBDriver *usbp);
- void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
- void usb_lld_disable_endpoints(USBDriver *usbp);
- usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
- usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
- void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
- void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
- void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
- void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
- void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
- void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
- void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_USB */
-
-#endif /* HAL_USB_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_dma_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_dma_lld.c deleted file mode 100644 index 43e1d6c..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_dma_lld.c +++ /dev/null @@ -1,259 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file MSP430X hal_dma_lld.c
- * @brief MSP430X DMA subsystem low level driver source.
- *
- * @addtogroup MSP430X_DMA
- * @{
- */
-
-#include "hal.h"
-#include "ch.h"
-#include "hal_dma_lld.h"
-
-#if (HAL_USE_DMA == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-static msp430x_dma_ch_reg_t * const dma_channels =
- (msp430x_dma_ch_reg_t *)&DMA0CTL;
-
-static msp430x_dma_cb_t callbacks[MSP430X_DMA_CHANNELS];
-#if CH_CFG_USE_SEMAPHORES
-static semaphore_t dma_lock;
-#endif
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Set a DMA trigger using an index.
- *
- * @param[in] index The index of the DMA channel whose trigger is set.
- * @param[in] trigger The trigger to use.
- * @note This is all to get around weird MSP behavior when writing to memory-
- * mapped registers using bytewise instructions.
- */
-static void dma_trigger_set(uint8_t index, uint8_t trigger) {
- uint16_t * ctl = ((uint16_t *)((uintptr_t)(&DMACTL0)) + (index / 2));
- *ctl &= 0xFF00 >> (8 * (index % 2));
- *ctl |= trigger << (8 * (index % 2));
-}
-static void init_request(const msp430x_dma_req_t * request, uint8_t index) {
-
- dma_trigger_set(index, request->trigger);
- callbacks[index] = request->callback;
- msp430x_dma_ch_reg_t * ch = &dma_channels[index];
- ch->sa = (uintptr_t)request->source_addr;
- ch->da = (uintptr_t)request->dest_addr;
- ch->sz = request->size;
- ch->ctl = DMAREQ | DMAIE | DMAEN | request->data_mode | request->addr_mode |
- request->transfer_mode;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-PORT_IRQ_HANDLER(DMA_VECTOR) {
- uint8_t index;
- OSAL_IRQ_PROLOGUE();
-
- index = (DMAIV >> 1) - 1;
-
- if (index < MSP430X_DMA_CHANNELS) {
-#if CH_CFG_USE_SEMAPHORES
- chSemSignalI(&dma_lock);
-#endif
-
- msp430x_dma_cb_t * cb = &callbacks[index];
-
- /* WARNING: CALLBACKS ARE CALLED IN AN ISR CONTEXT! */
- if (cb->callback != NULL) {
- cb->callback(cb->args);
- }
- }
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Initialize the DMA engine.
- *
- * @init
- */
-void dmaInit(void) {
-#if CH_CFG_USE_SEMAPHORES
- chSemObjectInit(&dma_lock, MSP430X_DMA_CHANNELS);
-#endif
-}
-
-/**
- * @brief Requests a DMA transfer operation from the DMA engine.
- * @note The DMA engine uses unclaimed DMA channels to provide DMA services
- * for one-off or infrequent uses. If all channels are busy, and
- * semaphores are enabled, the calling thread will sleep until a
- * channel is available or the request times out. If semaphores are
- * disabled, the calling thread will busy-wait instead of sleeping.
- */
-bool dmaRequest(msp430x_dma_req_t * request, systime_t timeout) {
-/* Check if a DMA channel is available */
-#if CH_CFG_USE_SEMAPHORES
- msg_t semresult = chSemWaitTimeout(&dma_lock, timeout);
- if (semresult != MSG_OK)
- return true;
-#endif
-
-#if !(CH_CFG_USE_SEMAPHORES)
- systime_t start = chVTGetSystemTimeX();
-
- do {
-#endif
- /* Grab the correct DMA channel to use */
- int i = 0;
- for (i = 0; i < MSP430X_DMA_CHANNELS; i++) {
- if (!(dma_channels[i].ctl & DMAEN)) {
- break;
- }
- }
-#if !(CH_CFG_USE_SEMAPHORES)
- while (chVTTimeElapsedSinceX(start) < timeout)
- ;
-#endif
-
-#if !(CH_CFG_USE_SEMAPHORES)
- if (i == MSP430X_DMA_CHANNELS) {
- return true;
- }
-#endif
-
- /* Make the request */
- init_request(request, i);
-
- return false;
- }
-
- /**
- * @brief Acquires exclusive control of a DMA channel.
- * @pre The channel must not be already acquired or an error is returned.
- * @note If the channel is in use by the DMA engine, blocks until acquired.
- * @post This channel must be interacted with using only the functions
- * defined in this module.
- *
- * @param[out] channel The channel handle. Must be pre-allocated.
- * @param[in] index The index of the channel (< MSP430X_DMA_CHANNELS).
- * @return The operation status.
- * @retval false no error, channel acquired.
- * @retval true error, channel already acquired.
- */
- bool dmaAcquire(msp430x_dma_ch_t * channel, uint8_t index) {
- /* Acquire the channel in an idle mode */
-
- /* Is the channel already acquired? */
- osalDbgAssert(index < MSP430X_DMA_CHANNELS, "invalid channel index");
- if (dma_channels[index].ctl & DMADT_4) {
- return true;
- }
-
-/* Increment the DMA counter */
-#if CH_CFG_USE_SEMAPHORES
- msg_t semresult = chSemWait(&dma_lock);
- if (semresult != MSG_OK)
- return true;
-#endif
-
- while (dma_channels[index].ctl & DMAEN)
- ;
-
- dma_trigger_set(index, DMA_TRIGGER_MNEM(DMAREQ));
- dma_channels[index].sz = 0;
- dma_channels[index].ctl = DMAEN | DMAABORT | DMADT_4;
-
- channel->registers = dma_channels + index;
- channel->index = index;
- channel->cb = callbacks + index;
-
- return false;
- }
-
- /**
- * @brief Initiates a DMA transfer operation using an acquired channel.
- * @pre The channel must have been acquired using @p dmaAcquire().
- *
- * @param[in] channel pointer to a DMA channel from @p dmaAcquire().
- * @param[in] request pointer to a DMA request object.
- */
- void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request) {
-
- dma_trigger_set(channel->index, request->trigger);
- /**(channel->ctl) = request->trigger;*/
-
- channel->cb->callback = request->callback.callback;
- channel->cb->args = request->callback.args;
-
- chSysLock();
- channel->registers->ctl &= (~DMAEN);
- channel->registers->sa = (uintptr_t)request->source_addr;
- channel->registers->da = (uintptr_t)request->dest_addr;
- channel->registers->sz = request->size;
- channel->registers->ctl = DMAIE | request->data_mode | request->addr_mode |
- request->transfer_mode | DMADT_4 | DMAEN |
- DMAREQ; /* repeated transfers */
- chSysUnlock();
- }
-
- /**
- * @brief Releases exclusive control of a DMA channel.
- * @details The channel is released from control and returned to the DMA
- * engine
- * pool. Trying to release an unallocated channel is an illegal
- * operation and is trapped if assertions are enabled.
- * @pre The channel must have been acquired using @p dmaAcquire().
- * @post The channel is returned to the DMA engine pool.
- */
- void dmaRelease(msp430x_dma_ch_t * channel) {
-
- osalDbgCheck(channel != NULL);
-
- /* Release the channel in an idle mode */
- channel->registers->ctl = DMAABORT;
-
-/* release the DMA counter */
-#if CH_CFG_USE_SEMAPHORES
- chSemSignal(&dma_lock);
-#endif
- }
-
-#endif /* HAL_USE_DMA == TRUE */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_dma_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_dma_lld.h deleted file mode 100644 index d1495d2..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_dma_lld.h +++ /dev/null @@ -1,173 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file MSP430X/hal_dma_lld.c
- * @brief MSP430X DMA subsystem low level driver header.
- * @note This driver is used as a DMA engine for the other
- * low level drivers.
- *
- * @addtogroup MSP430X_DMA
- * @{
- */
-
-#ifndef HAL_MSP430X_DMA_H
-#define HAL_MSP430X_DMA_H
-
-#if (HAL_USE_DMA == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-#define MSP430X_DMA_SINGLE DMADT_0
-#define MSP430X_DMA_BLOCK DMADT_1
-#define MSP430X_DMA_BURST DMADT_2
-
-#define MSP430X_DMA_SRCINCR DMASRCINCR_3
-#define MSP430X_DMA_SRCDECR DMASRCINCR_2
-#define MSP430X_DMA_DSTINCR DMADSTINCR_3
-#define MSP430X_DMA_DSTDECR DMADSTINCR_2
-
-#define MSP430X_DMA_SRCBYTE DMASRCBYTE
-#define MSP430X_DMA_DSTBYTE DMADSTBYTE
-#define MSP430X_DMA_SRCWORD 0
-#define MSP430X_DMA_DSTWORD 0
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !defined(DMA_BASE) && !defined(MSP430X_DMA_SOFTWARE)
-#error "The MSP430 device in use does not support DMA. Explicitly enable"
-#error "software emulation by defining MSP430X_DMA_SOFTWARE."
-#endif
-
-#if defined(__MSP430_HAS_DMAX_1__) || defined(__MSP430X_HAS_DMA_1__)
-#define MSP430X_DMA_CHANNELS 1
-#elif defined(__MSP430_HAS_DMAX_3__) || defined(__MSP430X_HAS_DMA_3__)
-#define MSP430X_DMA_CHANNELS 3
-#elif defined(__MSP430_HAS_DMAX_6__) || defined(__MSP430X_HAS_DMA_6__)
-#define MSP430X_DMA_CHANNELS 6
-#else
-#error "Unexpected error - how many DMA channels does your MSP have?"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of DMA callback function pointer.
- */
-typedef void (*msp430x_dma_cbp_t)(void * args);
-
-/**
- * @brief DMA callback, function and argument.
- */
-typedef struct {
- msp430x_dma_cbp_t callback; /**< @brief Callback function pointer */
- void * args; /**< @brief Callback function arguments */
-} msp430x_dma_cb_t;
-
-/**
- * @brief MSP430X DMA request structure.
- */
-typedef struct {
- const void * source_addr; /**< @brief Source address */
- void * dest_addr; /**< @brief Destination address */
- uint16_t size; /**< @brief Number of values to transfer */
- uint16_t addr_mode; /**< @brief Address manipulation mode */
- uint16_t data_mode; /**< @brief Data sizes (b2b, w2w, b2w, w2b) */
- uint16_t transfer_mode; /**< @brief Transfer mode (single, block, burst) */
- uint16_t trigger; /**< @brief Triggering event (see datasheet) */
- msp430x_dma_cb_t callback; /**< @brief Callback function and arguments */
-} msp430x_dma_req_t;
-
-/**
- * @brief MSP430X DMA channel register structure.
- */
-typedef struct {
- volatile uint16_t ctl; /**< @brief Control register */
- volatile uint32_t sa; /**< @brief Source address register */
- volatile uint32_t da; /**< @brief Destination address register */
- volatile uint16_t sz; /**< @brief Size register */
- volatile uint16_t pad1;
- volatile uint16_t pad2;
-} msp430x_dma_ch_reg_t;
-
-/**
- * @brief MSP430X DMA controller register structure.
- */
-typedef struct {
- volatile uint8_t tsel0; /**< @brief Trigger select for channel 0 */
- volatile uint8_t tsel1; /**< @brief Trigger select for channel 1 */
- volatile uint8_t tsel2; /**< @brief Trigger select for channel 2 */
- volatile uint8_t tsel3; /**< @brief Trigger select for channel 3 */
- volatile uint8_t tsel4; /**< @brief Trigger select for channel 4 */
- volatile uint8_t tsel5; /**< @brief Trigger select for channel 5 */
- volatile uint8_t tsel6; /**< @brief Trigger select for channel 6 */
- volatile uint8_t tsel7; /**< @brief Trigger select for channel 7 */
- volatile uint16_t ctl4; /**< @brief Controller register 4 */
-} msp430x_dma_ctl_reg_t;
-
-/**
- * @brief MSP430X DMA channel structure.
- */
-typedef struct {
- msp430x_dma_ch_reg_t * registers; /**< @brief Pointer to channel registers */
- uint8_t index; /**< @brief Index of channel trigger control register */
- msp430x_dma_cb_t * cb; /**< @brief Pointer to callback function and args */
-} msp430x_dma_ch_t;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Identifies a DMA trigger using a mnemonic.
- *
- * @param[in] mnem The mnemonic for the trigger, e.g. UCA0RXIFG to trigger
- * on UART receive.
- */
-#define DMA_TRIGGER_MNEM(mnem) DMA0TSEL__##mnem
-
-/** @} */
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-void dmaInit(void);
-bool dmaRequest(msp430x_dma_req_t * request, systime_t timeout);
-bool dmaAcquire(msp430x_dma_ch_t * channel, uint8_t index);
-void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request);
-void dmaRelease(msp430x_dma_ch_t * channel);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_DMA == true */
-
-#endif /* HAL_MSP430X_DMA_H */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_lld.c deleted file mode 100644 index 872fe97..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_lld.c +++ /dev/null @@ -1,87 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file MSP430X/hal_lld.c
- * @brief MSP430X HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
- /* Disable watchdog */
- /* TODO Real watchdog support */
- WDTCTL = WDTPW | WDTHOLD;
- /* Init clock system */
- CSCTL0 = CSKEY; /* unlock clock system */
- CSCTL1 = MSP430X_DCOSEL;
- CSCTL2 = (MSP430X_ACLK_SRC << 8) | (MSP430X_SMCLK_SRC << 4) | (MSP430X_MCLK_SRC);
- CSCTL3 = (DIVIDER(MSP430X_ACLK_DIV) << 8) | (DIVIDER(MSP430X_SMCLK_DIV) << 4) | (DIVIDER(MSP430X_MCLK_DIV));
- CSCTL4 = (MSP430X_HFXTCLK_DRIVE << 14) | (MSP430X_HFXTCLK_BYPASS << 12) | (MSP430X_HFFREQ << 10) | HFXTOFF | \
- (MSP430X_LFXTCLK_DRIVE << 6) | (MSP430X_LFXTCLK_BYPASS << 4) | VLOOFF | LFXTOFF;
- CSCTL6 = (MODCLKREQEN) | (SMCLKREQEN) | (MCLKREQEN) | (ACLKREQEN);
- #if defined(MSP430X_USE_HFXT) && defined(MSP430X_USE_LFXT)
- do {
- CSCTL5 &= ~(HFXTOFFG | LFXTOFFG);
- SFRIFG1 &= ~OFIFG;
- } while (SFRIFG1 & OFIFG);
- #elif defined(MSP430X_USE_HFXT)
- do {
- CSCTL5 &= ~(HFXTOFFG);
- SFRIFG1 &= ~OFIFG;
- } while (SFRIFG1 & OFIFG);
- #elif defined(MSP430X_USE_LFXT)
- do {
- CSCTL5 &= ~(LFXTOFFG);
- SFRIFG1 &= ~OFIFG;
- } while (SFRIFG1 & OFIFG);
- #endif
- CSCTL0_H = 0xFF; /* Lock clock system */
-}
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_lld.h deleted file mode 100644 index 9549453..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_lld.h +++ /dev/null @@ -1,245 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file MSP430X/hal_lld.h
- * @brief MSP430X HAL subsystem low level driver header.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Defines the support for realtime counters in the HAL.
- */
-/* someday*/
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @name Platform identification macros
- * @{
- */
-#define PLATFORM_NAME "MSP430X"
-/** @} */
-
-#define MSP430X_LFXTCLK 0
-#define MSP430X_VLOCLK 1
-#define MSP430X_LFMODCLK 2
-#define MSP430X_DCOCLK 3
-#define MSP430X_MODCLK 4
-#define MSP430X_HFXTCLK 5
-
-#if !defined(MSP430X_LFXTCLK_FREQ)
- #define MSP430X_LFXTCLK_FREQ 32768
- #warning "LFXTCLK freqency not defined - assuming 32768 Hz"
-#endif
-#define MSP430X_VLOCLK_FREQ 10000
-#define MSP430X_MODCLK_FREQ 5000000
-#define MSP430X_LFMODCLK_FREQ (MSP430X_MODCLK_FREQ/128)
-#if !defined(MSP430X_DCOCLK_FREQ)
- #define MSP430X_DCOCLK_FREQ 8000000
- #warning "DCOCLK frequency not defined - assuming 8 MHz"
-#endif
-#if !defined(MSP430X_HFXTCLK_FREQ)
- #define MSP430X_HFXTCLK_FREQ 0
- #warning "HFXTCLK frequency not defined - assuming disabled"
-#endif
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name MSP430X configuration options
- * @{
- */
-
-/* Clock dividers */
-#if !defined(MSP430X_ACLK_DIV)
- #define MSP430X_ACLK_DIV 1
-#endif
-#if !defined(MSP430X_MCLK_DIV)
- #define MSP430X_MCLK_DIV 8
-#endif
-#if !defined(MSP430X_SMCLK_DIV)
- #define MSP430X_SMCLK_DIV 8
-#endif
-
-/* Clock sources */
-#if !defined(MSP430X_ACLK_SRC)
- #define MSP430X_ACLK_SRC MSP430X_LFXTCLK
-#endif
-#if !defined(MSP430X_MCLK_SRC)
- #define MSP430X_MCLK_SRC MSP430X_DCOCLK
-#endif
-#if !defined(MSP430X_SMCLK_SRC)
- #define MSP430X_SMCLK_SRC MSP430X_DCOCLK
-#endif
-
-/* HFXT and LFXT settings */
-#if !defined(MSP430X_LFXTCLK_BYPASS)
- #define MSP430X_LFXTCLK_BYPASS 0
-#endif
-#if !defined(MSP430X_LFXTCLK_DRIVE)
- #define MSP430X_LFXTCLK_DRIVE 3
-#endif
-#if !defined(MSP430X_HFXTCLK_BYPASS)
- #define MSP430X_HFXTCLK_BYPASS 0
-#endif
-#if !defined(MSP430X_HFXTCLK_DRIVE)
- #define MSP430X_HFXTCLK_DRIVE 3
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if (MSP430X_ACLK_SRC == MSP430X_LFXTCLK) || (MSP430X_MCLK_SRC == MSP430X_LFXTCLK) || (MSP430X_SMCLK_SRC == MSP430X_LFXTCLK)
- #define MSP430X_USE_LFXTCLK
-#endif
-#if (MSP430X_MCLK_SRC == MSP430X_HFXTCLK) || (MSP430X_SMCLK_SRC == MSP430X_HFXTCLK)
- #define MSP430X_USE_HFXTCLK
-#endif
-
-#if defined(MSP430X_USE_HFXTCLK) && MSP430X_HFXTCLK_FREQ == 0
- #error "HFXT requested as clock source but disabled"
-#endif
-
-/* Clock speeds */
-#if (MSP430X_ACLK_SRC == MSP430X_LFXTCLK)
- #define MSP430X_ACLK_FREQ (MSP430X_LFXTCLK_FREQ / MSP430X_ACLK_DIV)
-#elif (MSP430X_ACLK_SRC == MSP430X_VLOCLK)
- #define MSP430X_ACLK_FREQ (MSP430X_VLOCLK_FREQ / MSP430X_ACLK_DIV)
-#elif (MSP430X_ACLK_SRC == MSP430X_LFMODCLK)
- #define MSP430X_ACLK_FREQ (MSP430X_LFMODCLK_FREQ / MSP430X_ACLK_DIV)
-#else
- #error "ACLK source invalid!"
-#endif
-#if (MSP430X_MCLK_SRC == MSP430X_LFXTCLK)
- #define MSP430X_MCLK_FREQ (MSP430X_LFXTCLK_FREQ / MSP430X_MCLK_DIV)
-#elif (MSP430X_MCLK_SRC == MSP430X_VLOCLK)
- #define MSP430X_MCLK_FREQ (MSP430X_VLOCLK_FREQ / MSP430X_MCLK_DIV)
-#elif (MSP430X_MCLK_SRC == MSP430X_LFMODCLK)
- #define MSP430X_MCLK_FREQ (MSP430X_LFMODCLK_FREQ / MSP430X_MCLK_DIV)
-#elif (MSP430X_MCLK_SRC == MSP430X_DCOCLK)
- #define MSP430X_MCLK_FREQ (MSP430X_DCOCLK_FREQ / MSP430X_MCLK_DIV)
-#elif (MSP430X_MCLK_SRC == MSP430X_MODCLK)
- #define MSP430X_MCLK_FREQ (MSP430X_MODCLK_FREQ / MSP430X_MCLK_DIV)
-#elif (MSP430X_MCLK_SRC == MSP430X_HFXTCLK)
- #define MSP430X_MCLK_FREQ (MSP430X_HFXTCLK_FREQ / MSP430X_MCLK_DIV)
-#else
- #error "MCLK source invalid!"
-#endif
-#if (MSP430X_SMCLK_SRC == MSP430X_LFXTCLK)
- #define MSP430X_SMCLK_FREQ (MSP430X_LFXTCLK_FREQ / MSP430X_SMCLK_DIV)
-#elif (MSP430X_SMCLK_SRC == MSP430X_VLOCLK)
- #define MSP430X_SMCLK_FREQ (MSP430X_VLOCLK_FREQ / MSP430X_SMCLK_DIV)
-#elif (MSP430X_SMCLK_SRC == MSP430X_LFMODCLK)
- #define MSP430X_SMCLK_FREQ (MSP430X_LFMODCLK_FREQ / MSP430X_SMCLK_DIV)
-#elif (MSP430X_SMCLK_SRC == MSP430X_DCOCLK)
- #define MSP430X_SMCLK_FREQ (MSP430X_DCOCLK_FREQ / MSP430X_SMCLK_DIV)
-#elif (MSP430X_SMCLK_SRC == MSP430X_MODCLK)
- #define MSP430X_SMCLK_FREQ (MSP430X_MODCLK_FREQ / MSP430X_SMCLK_DIV)
-#elif (MSP430X_SMCLK_SRC == MSP430X_HFXTCLK)
- #define MSP430X_SMCLK_FREQ (MSP430X_HFXTCLK_FREQ / MSP430X_SMCLK_DIV)
-#else
- #error "SMCLK source invalid!"
-#endif
-
-#if !defined(MSP430X_MCUCONF)
-#error "Using an incorrect mcuconf.h file, MSP430X_MCUCONF not defined"
-#endif
-
-/* HFXT-specific settings */
-#if MSP430X_HFXTCLK_FREQ <= 4000000
- #define MSP430X_HFFREQ HFFREQ_0
-#elif MSP430X_HFXTCLK_FREQ <= 8000000
- #define MSP430X_HFFREQ HFFREQ_1
-#elif MSP430X_HFXTCLK_FREQ <= 16000000
- #define MSP430X_HFFREQ HFFREQ_2
-#elif MSP430X_HFXTCLK_FREQ <= 24000000
- #define MSP430X_HFFREQ HFFREQ_3
-#else
- #error "HFXT frequency too high - must be <= 24000000"
-#endif
-
-/* DCO-specific settings */
-#if MSP430X_DCOCLK_FREQ == 1000000
- #define MSP430X_DCOSEL DCOFSEL_0
-#elif MSP430X_DCOCLK_FREQ == 2670000
- #define MSP430X_DCOSEL DCOFSEL_1
-#elif MSP430X_DCOCLK_FREQ == 3330000
- #define MSP430X_DCOSEL DCOFSEL_2
-#elif MSP430X_DCOCLK_FREQ == 4000000
- #define MSP430X_DCOSEL DCOFSEL_3
-#elif MSP430X_DCOCLK_FREQ == 5330000
- #define MSP430X_DCOSEL DCOFSEL_4
-#elif MSP430X_DCOCLK_FREQ == 6670000
- #define MSP430X_DCOSEL DCOFSEL_5
-#elif MSP430X_DCOCLK_FREQ == 8000000
- #define MSP430X_DCOSEL DCOFSEL_6
-#elif MSP430X_DCOCLK_FREQ == 16000000
- #define MSP430X_DCOSEL (DCORSEL | DCOFSEL_4)
-#elif MSP430X_DCOCLK_FREQ == 21000000
- #define MSP430X_DCOSEL (DCORSEL | DCOFSEL_5)
-#elif MSP430X_DCOCLK_FREQ == 24000000
- #define MSP430X_DCOSEL (DCORSEL | DCOFSEL_6)
-#else
- #error "DCO frequency invalid"
-#endif
-
-#if MSP430X_LFXTCLK_FREQ > 50000
- #error "LFXT frequency too high - must be <= 5000"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-#define DIVIDER(x) DIV_HELPER(x)
-#define DIV_HELPER(x) DIVM__ ## x
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void hal_lld_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_pal_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_pal_lld.c deleted file mode 100644 index 97ad170..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_pal_lld.c +++ /dev/null @@ -1,229 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file MSP430X/hal_pal_lld.c
- * @brief MSP430X PAL subsystem low level driver source.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "hal.h"
-
-#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief MSP430X I/O ports configuration.
- * @details GPIO registers initialization
- *
- * @param[in] config the MSP430X ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
-#if defined(PA_BASE) || defined(__DOXYGEN__)
- PAOUT = config->porta.out;
- PADIR = config->porta.dir;
- PAREN = config->porta.ren;
- PASEL0 = config->porta.sel0;
- PASEL1 = config->porta.sel1;
- PAIES = config->porta.ies;
- PAIE = config->porta.ie;
- PAIFG = 0;
-#endif
-#if defined(PB_BASE) || defined(__DOXYGEN__)
- PBOUT = config->portb.out;
- PBDIR = config->portb.dir;
- PBREN = config->portb.ren;
- PBSEL0 = config->portb.sel0;
- PBSEL1 = config->portb.sel1;
- PBIES = config->portb.ies;
- PBIE = config->portb.ie;
- PBIFG = 0;
-#endif
-#if defined(PC_BASE) || defined(__DOXYGEN__)
- PCOUT = config->portc.out;
- PCDIR = config->portc.dir;
- PCREN = config->portc.ren;
- PCSEL0 = config->portc.sel0;
- PCSEL1 = config->portc.sel1;
-#if defined(PCIE) || defined(__DOXYGEN__)
- PCIES = config->portc.ies;
- PCIE = config->portc.ie;
- PCIFG = 0;
-#endif
-#endif
-#if defined(PD_BASE) || defined(__DOXYGEN__)
- PDOUT = config->portd.out;
- PDDIR = config->portd.dir;
- PDREN = config->portd.ren;
- PDSEL0 = config->portd.sel0;
- PDSEL1 = config->portd.sel1;
-#if defined(PDIE) || defined(__DOXYGEN__)
- PDIES = config->portd.ies;
- PDIE = config->portd.ie;
- PDIFG = 0;
-#endif
-#endif
-#if defined(PE_BASE) || defined(__DOXYGEN__)
- PEOUT = config->porte.out;
- PEDIR = config->porte.dir;
- PEREN = config->porte.ren;
- PESEL0 = config->porte.sel0;
- PESEL1 = config->porte.sel1;
-#if defined(PEIE) || defined(__DOXYGEN__)
- PEIES = config->porte.ies;
- PEIE = config->porte.ie;
- PEIFG = 0;
-#endif
-#endif
-#if defined(PF_BASE) || defined(__DOXYGEN__)
- PFOUT = config->portf.out;
- PFDIR = config->portf.dir;
- PFREN = config->portf.ren;
- PFSEL0 = config->portf.sel0;
- PFSEL1 = config->portf.sel1;
-#if defined(PFIE) || defined(__DOXYGEN__)
- PFIES = config->portf.ies;
- PFIE = config->portf.ie;
- PFIFG = 0;
-#endif
-#endif
- PJOUT = config->portj.out;
- PJDIR = config->portj.dir;
- PJREN = config->portj.ren;
- PJSEL0 = config->portj.sel0;
- PJSEL1 = config->portj.sel1;
-
- PM5CTL0 &= ~LOCKLPM5;
-}
-
-/**
- * @brief Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- * @note @p PAL_MODE_UNCONNECTED is implemented as input with pullup.
- *
- * @param[in] port the port identifier
- * @param[in] mask the group mask
- * @param[in] mode the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode) {
-
- switch (mode) {
- case PAL_MODE_RESET:
- case PAL_MODE_INPUT:
- port->dir &= ~mask;
- port->ren &= ~mask;
- if ((port->sel0 & mask) && (port->sel1 & mask))
- port->selc = mask;
- else {
- port->sel0 &= ~mask;
- port->sel1 &= ~mask;
- }
- break;
- case PAL_MODE_UNCONNECTED:
- case PAL_MODE_INPUT_PULLUP:
- port->dir &= ~mask;
- port->ren |= mask;
- port->out |= mask;
- if ((port->sel0 & mask) && (port->sel1 & mask))
- port->selc = mask;
- else {
- port->sel0 &= ~mask;
- port->sel1 &= ~mask;
- }
- break;
- case PAL_MODE_INPUT_PULLDOWN:
- port->dir &= ~mask;
- port->ren |= mask;
- port->out &= ~mask;
- if ((port->sel0 & mask) && (port->sel1 & mask))
- port->selc = mask;
- else {
- port->sel0 &= ~mask;
- port->sel1 &= ~mask;
- }
- break;
- case PAL_MODE_OUTPUT_PUSHPULL:
- port->dir |= mask;
- if ((port->sel0 & mask) && (port->sel1 & mask))
- port->selc = mask;
- else {
- port->sel0 &= ~mask;
- port->sel1 &= ~mask;
- }
- break;
- case PAL_MSP430X_ALTERNATE_1:
- if (!(port->sel0 & mask) && (port->sel1 & mask))
- port->selc = mask;
- else {
- port->sel0 |= mask;
- port->sel1 &= ~mask;
- }
- break;
- case PAL_MSP430X_ALTERNATE_2:
- if ((port->sel0 & mask) && !(port->sel1 & mask))
- port->selc = mask;
- else {
- port->sel0 &= ~mask;
- port->sel1 |= mask;
- }
- break;
- case PAL_MSP430X_ALTERNATE_3:
- if (!(port->sel0 & mask) && !(port->sel1 & mask))
- port->selc = mask;
- else {
- port->sel0 |= mask;
- port->sel1 |= mask;
- }
- break;
- }
-}
-
-#endif /* HAL_USE_PAL == TRUE */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_pal_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_pal_lld.h deleted file mode 100644 index 0b6363b..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_pal_lld.h +++ /dev/null @@ -1,385 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file MSP430X/hal_pal_lld.h
- * @brief MSP430X PAL subsystem low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef HAL_PAL_LLD_H
-#define HAL_PAL_LLD_H
-
-#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_ANALOG /* configure this through the ALTERNATE macros */
-#undef PAL_MODE_OUTPUT_OPENDRAIN
-
-/**
- * @name MSP430X-specific I/O mode flags
- * @{
- */
-
-/**
- * @brief Alternate mode 1
- */
-#define PAL_MSP430X_ALTERNATE_1 8
-
-/**
- * @brief Alternate mode 2
- */
-#define PAL_MSP430X_ALTERNATE_2 9
-
-/**
- * @brief Alternate mode 3
- */
-#define PAL_MSP430X_ALTERNATE_3 10
-
-#define ALTERNATE_HELP(n) (PAL_MSP430X_ALTERNATE_##n)
-/**
- * @brief Alternate function.
- *
- * @param[in] n alternate function selector - 1 through 3
- */
-#define PAL_MODE_ALTERNATE(n) (ALTERNATE_HELP(n))
-
-/** @} */
-
-/*===========================================================================*/
-/* I/O Ports Types and constants. */
-/*===========================================================================*/
-
-/**
- * @name Port related definitions
- * @{
- */
-/**
- * @brief Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 16U
-
-/**
- * @brief Whole port mask.
- * @details This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFU)
-
-/** @} */
-
-/**
- * @name Line handling macros
- * @{
- */
-/**
- * @brief Forms a line identifier.
- * @details A port/pad pair are encoded into an @p ioline_t type. The encoding
- * of this type is platform-dependent.
- * @note In this driver the pad number is encoded in the upper 4 bits of
- * the GPIO address which are guaranteed to be zero.
- */
-#define PAL_LINE(port, pad) \
- ((ioline_t)((uint16_t)(port)) | (((uint16_t)(pad)) << 12))
-
-/**
- * @brief Decodes a port identifier from a line identifier.
- */
-#define PAL_PORT(line) \
- ((msp430x_gpio_registers_t *)(((uint16_t)(line)) & 0x0FFFU))
-
-/**
- * @brief Decodes a pad identifier from a line identifier.
- */
-#define PAL_PAD(line) ((uint16_t)((uint16_t)(line) >> 12))
-
-/**
- * @brief Value identifying an invalid line.
- */
-#define PAL_NOLINE 0U
-/** @} */
-
-/**
- * @brief MSP430X register initialization
- */
-typedef struct {
- /** Initial value for OUT register.*/
- uint16_t out;
- /** Initial value for DIR register.*/
- uint16_t dir;
- /** Initial value for REN register.*/
- uint16_t ren;
- /** Initial value for SEL0 register.*/
- uint16_t sel0;
- /** Initial value for SEL1 register.*/
- uint16_t sel1;
- /** Initial value for IES register.*/
- uint16_t ies;
- /** Initial value for IE register.*/
- uint16_t ie;
-} msp430x_gpio_setup_t;
-
-/**
- * @brief MSP430X registers block
- * @note Some ports do not support all of these fields.
- */
-typedef struct {
- volatile uint16_t in;
- volatile uint16_t out;
- volatile uint16_t dir;
- volatile uint16_t _padding;
- volatile uint16_t ren;
- volatile uint16_t sel0;
- volatile uint16_t sel1;
- volatile uint16_t _padding1;
- volatile uint16_t _padding2;
- volatile uint16_t _padding3;
- volatile uint16_t _padding4;
- volatile uint16_t selc;
- volatile uint16_t ies;
- volatile uint16_t ie;
- volatile uint16_t ifg;
-} msp430x_gpio_registers_t;
-
-/**
- * @brief MSP430X I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- * system startup time in order to initialized the digital I/O
- * subsystem. This represents only the initial setup, specific pads
- * or whole ports can be reprogrammed at later time.
- */
-typedef struct {
-#if defined(PA_BASE) || defined(__DOXYGEN__)
- msp430x_gpio_setup_t porta;
-#endif
-#if defined(PB_BASE) || defined(__DOXYGEN__)
- msp430x_gpio_setup_t portb;
-#endif
-#if defined(PC_BASE) || defined(__DOXYGEN__)
- msp430x_gpio_setup_t portc;
-#endif
-#if defined(PD_BASE) || defined(__DOXYGEN__)
- msp430x_gpio_setup_t portd;
-#endif
-#if defined(PE_BASE) || defined(__DOXYGEN__)
- msp430x_gpio_setup_t porte;
-#endif
-#if defined(PF_BASE) || defined(__DOXYGEN__)
- msp430x_gpio_setup_t portf;
-#endif
- msp430x_gpio_setup_t portj;
-} PALConfig;
-
-/**
- * @brief Digital I/O port sized unsigned type.
- */
-typedef uint16_t ioportmask_t;
-
-/**
- * @brief Digital I/O modes.
- */
-typedef uint16_t iomode_t;
-
-/**
- * @brief Type of an I/O line.
- */
-typedef uint16_t ioline_t;
-
-/**
- * @brief Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- * any assumption about it, use the provided macros when populating
- * variables of this type.
- */
-typedef msp430x_gpio_registers_t * ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers. */
-/*===========================================================================*/
-
-/**
- * @brief GPIO port A identifier.
- */
-#if defined(PA_BASE) || defined(__DOXYGEN__)
-#define IOPORT1 ((volatile msp430x_gpio_registers_t *)PA_BASE)
-#endif
-
-/**
- * @brief GPIO port B identifier.
- */
-#if defined(PB_BASE) || defined(__DOXYGEN__)
-#define IOPORT2 ((volatile msp430x_gpio_registers_t *)PB_BASE)
-#endif
-
-/**
- * @brief GPIO port C identifier.
- */
-#if defined(PC_BASE) || defined(__DOXYGEN__)
-#define IOPORT3 ((volatile msp430x_gpio_registers_t *)PC_BASE)
-#endif
-
-/**
- * @brief GPIO port D identifier.
- */
-#if defined(PD_BASE) || defined(__DOXYGEN__)
-#define IOPORT4 ((volatile msp430x_gpio_registers_t *)PD_BASE)
-#endif
-
-/**
- * @brief GPIO port E identifier.
- */
-#if defined(PE_BASE) || defined(__DOXYGEN__)
-#define IOPORT5 ((volatile msp430x_gpio_registers_t *)PE_BASE)
-#endif
-
-/**
- * @brief GPIO port F identifier.
- */
-#if defined(PF_BASE) || defined(__DOXYGEN__)
-#define IOPORT6 ((volatile msp430x_gpio_registers_t *)PF_BASE
-#endif
-
-/**
- * @brief GPIO port J identifier.
- */
-#define IOPORT0 ((volatile msp430x_gpio_registers_t *)PJ_BASE)
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as */
-/* functions, if so please put them in pal_lld.c. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PAL subsystem initialization.
- *
- * @param[in] config architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief Reads the physical I/O port states.
- *
- * @param[in] port port identifier
- * @return The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->in)
-
-/**
- * @brief Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- * value.
- *
- * @param[in] port port identifier
- * @return The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->out)
-
-/**
- * @brief Writes a bits mask on a I/O port.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->out = (bits))
-
-/**
- * @brief Sets a bits mask on a I/O port.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) ((port)->out |= (bits))
-
-/**
- * @brief Clears a bits mask on a I/O port.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) ((port)->out &= ~(bits))
-
-/**
- * @brief Toggles a bits mask on a I/O port.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be XORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_toggleport(port, bits) ((port)->out ^= (bits))
-
-/**
- * @brief Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] mode group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode) \
- _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief Clears a pad logical state to @p PAL_LOW.
- * @details This function is implemented in a way which should
- * produce a BIC instruction rather than an AND
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad) ((port)->out &= ~(1 << pad))
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-void _pal_lld_init(const PALConfig * config);
-void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL == TRUE */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_serial_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_serial_lld.c deleted file mode 100644 index 0d9aa1c..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_serial_lld.c +++ /dev/null @@ -1,668 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file MSP430X/hal_serial_lld.c
- * @brief MSP430X serial subsystem low level driver source.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "hal.h"
-
-#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief USART0 serial driver identifier.*/
-#if (MSP430X_SERIAL_USE_USART0 == TRUE) || defined(__DOXYGEN__)
-#ifndef __MSP430_HAS_EUSCI_A0__
-#error "Cannot find USCI module to use for SD0"
-#endif
-#ifdef MSP430X_USCI_A0_USED
-#error "USCI module A0 already in use - USART0 not available"
-#endif
-SerialDriver SD0;
-#define MSP430X_USCI_A0_USED
-#endif
-
-/** @brief USART1 serial driver identifier.*/
-#if (MSP430X_SERIAL_USE_USART1 == TRUE) || defined(__DOXYGEN__)
-#ifndef __MSP430_HAS_EUSCI_A1__
-#error "Cannot find USCI module to use for SD1"
-#endif
-#ifdef MSP430X_USCI_A1_USED
-#error "USCI module A1 already in use - USART1 not available"
-#endif
-SerialDriver SD1;
-#define MSP430X_USCI_A1_USED
-#endif
-
-/** @brief USART2 serial driver identifier.*/
-#if (MSP430X_SERIAL_USE_USART2 == TRUE) || defined(__DOXYGEN__)
-#ifndef __MSP430_HAS_EUSCI_A2__
-#error "Cannot find USCI module to use for SD2"
-#endif
-#ifdef MSP430X_USCI_A2_USED
-#error "USCI module A2 already in use - USART2 not available"
-#endif
-SerialDriver SD2;
-#define MSP430X_USCI_A2_USED
-#endif
-
-/** @brief USART3 serial driver identifier.*/
-#if (MSP430X_SERIAL_USE_USART3 == TRUE) || defined(__DOXYGEN__)
-#ifndef __MSP430_HAS_EUSCI_A3__
-#error "Cannot find USCI module to use for SD3"
-#endif
-#ifdef MSP430X_USCI_A3_USED
-#error "USCI module A3 already in use - USART3 not available"
-#endif
-SerialDriver SD3;
-#define MSP430X_USCI_A3_USED
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Driver default configuration.
- */
-static const SerialConfig default_config = { SERIAL_DEFAULT_BITRATE };
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief UCBRS calculation.
- * @details This function calculates the UCBRS value for oversampled baud
- * rates.
- *
- * @param[in] frac Fractional part of baud rate division, times 10000.
- */
-static uint8_t UCBRS(uint16_t frac) {
- /* TODO there must be a better way */
- if (frac < 529)
- return 0x00;
- else if (frac < 715)
- return 0x01;
- else if (frac < 835)
- return 0x02;
- else if (frac < 1001)
- return 0x04;
- else if (frac < 1252)
- return 0x08;
- else if (frac < 1430)
- return 0x10;
- else if (frac < 1670)
- return 0x20;
- else if (frac < 2147)
- return 0x11;
- else if (frac < 2224)
- return 0x21;
- else if (frac < 2503)
- return 0x22;
- else if (frac < 3000)
- return 0x44;
- else if (frac < 3335)
- return 0x25;
- else if (frac < 3575)
- return 0x49;
- else if (frac < 3753)
- return 0x4A;
- else if (frac < 4003)
- return 0x52;
- else if (frac < 4286)
- return 0x92;
- else if (frac < 4378)
- return 0x53;
- else if (frac < 5002)
- return 0x55;
- else if (frac < 5715)
- return 0xAA;
- else if (frac < 6003)
- return 0x6B;
- else if (frac < 6254)
- return 0xAD;
- else if (frac < 6432)
- return 0xB5;
- else if (frac < 6667)
- return 0xB6;
- else if (frac < 7001)
- return 0xD6;
- else if (frac < 7147)
- return 0xB7;
- else if (frac < 7503)
- return 0xBB;
- else if (frac < 7861)
- return 0xDD;
- else if (frac < 8004)
- return 0xED;
- else if (frac < 8333)
- return 0xEE;
- else if (frac < 8464)
- return 0xBF;
- else if (frac < 8572)
- return 0xDF;
- else if (frac < 8751)
- return 0xEF;
- else if (frac < 9004)
- return 0xF7;
- else if (frac < 9170)
- return 0xFB;
- else if (frac < 9288)
- return 0xFD;
- else
- return 0xFE;
-}
-
-/**
- * @brief Modulation control word calculator.
- * @details This function calculates the modulation control word from the
- * input clock frequency and the requested baud rate.
- *
- * @param[in] baud Requested baud rate
- * @param[in] freq Frequency of the clock driving the USCI module
- */
-static uint16_t UCAxMCTLW(uint32_t baud, uint32_t freq) {
-
- uint16_t n = freq / baud;
- /*uint16_t frac = (freq * 10000 / baud) - ((freq / baud) * 10000);*/
- uint16_t frac = (freq - (n * baud)) * 10000 / baud;
- if (n > 16) {
- while (n > 16) {
- n -= 16;
- }
- return (UCBRS(frac) << 8) | (n << 4) | UCOS16;
- }
- return UCBRS(frac) << 8;
-}
-
-/**
- * @brief UCBRW calculation.
- * @details This function calculates the UCBRW value for all baud
- * rates.
- *
- * @param[in] baud Requested baud rate
- * @param[in] freq Frequency of the clock driving the USCI module
- */
-static uint16_t UCAxBRW(uint32_t baud, uint32_t freq) {
- uint16_t n = freq / baud;
- if (n > 16) {
- return n >> 4;
- }
- return n;
-}
-
-#if (MSP430X_SERIAL_USE_USART0 == TRUE) || defined(__DOXYGEN__)
-static void usart0_init(const SerialConfig * config) {
- UCA0BRW = UCAxBRW(config->sc_bitrate, MSP430X_USART0_CLK_FREQ);
- UCA0MCTLW = UCAxMCTLW(config->sc_bitrate, MSP430X_USART0_CLK_FREQ);
- UCA0STATW = 0;
- UCA0ABCTL = 0;
- UCA0IRCTL = 0;
- UCA0CTLW0 = (MSP430X_USART0_PARITY << 14) | (MSP430X_USART0_ORDER << 13) |
- (MSP430X_USART0_SIZE << 12) | (MSP430X_USART0_STOP << 11) |
- (MSP430X_USART0_UCSSEL);
- UCA0IE = UCRXIE;
-}
-#endif
-
-#if (MSP430X_SERIAL_USE_USART1 == TRUE) || defined(__DOXYGEN__)
-static void usart1_init(const SerialConfig * config) {
- UCA1BRW = UCAxBRW(config->sc_bitrate, MSP430X_USART1_CLK_FREQ);
- UCA1MCTLW = UCAxMCTLW(config->sc_bitrate, MSP430X_USART1_CLK_FREQ);
- UCA1STATW = 0;
- UCA1ABCTL = 0;
- UCA1IRCTL = 0;
- UCA1CTLW0 = (MSP430X_USART1_PARITY << 14) | (MSP430X_USART1_ORDER << 13) |
- (MSP430X_USART1_SIZE << 12) | (MSP430X_USART1_STOP << 11) |
- (MSP430X_USART1_UCSSEL);
- UCA1IE = UCRXIE;
-}
-#endif
-
-#if (MSP430X_SERIAL_USE_USART2 == TRUE) || defined(__DOXYGEN__)
-static void usart2_init(const SerialConfig * config) {
- UCA2BRW = UCAxBRW(config->sc_bitrate, MSP430X_USART2_CLK_FREQ);
- UCA2MCTLW = UCAxMCTLW(config->sc_bitrate);
- UCA2STATW = 0;
- UCA2ABCTL = 0;
- UCA2IRCTL = 0;
- UCA2CTLW0 = (MSP430X_USART2_PARITY << 14) | (MSP430X_USART2_ORDER << 13) |
- (MSP430X_USART2_SIZE << 12) | (MSP430X_USART2_STOP << 11) |
- (MSP430X_USART2_UCSSEL);
- UCA2IE = UCRXIE;
-}
-#endif
-
-#if (MSP430X_SERIAL_USE_USART3 == TRUE) || defined(__DOXYGEN__)
-static void usart3_init(const SerialConfig * config) {
- UCA3BRW = UCAxBRW(config->sc_bitrate, MSP430X_USART3_CLK_FREQ);
- UCA3MCTLW = UCAxMCTLW(config->sc_bitrate, MSP430X_USART3_CLK_FREQ);
- UCA3STATW = 0;
- UCA3ABCTL = 0;
- UCA3IRCTL = 0;
- UCA3CTLW0 = (MSP430X_USART3_PARITY << 14) | (MSP430X_USART3_ORDER << 13) |
- (MSP430X_USART3_SIZE << 12) | (MSP430X_USART3_STOP << 11) |
- (MSP430X_USART3_UCSSEL);
- UCA3IE = UCRXIE;
-}
-#endif
-
-#if (MSP430X_SERIAL_USE_USART0 == TRUE) || defined(__DOXYGEN__)
-static void notify0(io_queue_t * qp) {
-
- (void)qp;
- UCA0IE |= UCTXIE;
-}
-#endif
-
-#if (MSP430X_SERIAL_USE_USART1 == TRUE) || defined(__DOXYGEN__)
-static void notify1(io_queue_t * qp) {
-
- (void)qp;
- UCA1IE |= UCTXIE;
-}
-#endif
-
-#if (MSP430X_SERIAL_USE_USART2 == TRUE) || defined(__DOXYGEN__)
-static void notify2(io_queue_t * qp) {
-
- (void)qp;
- UCA2IE |= UCTXIE;
-}
-#endif
-
-#if (MSP430X_SERIAL_USE_USART3 == TRUE) || defined(__DOXYGEN__)
-static void notify3(io_queue_t * qp) {
-
- (void)qp;
- UCA3IE |= UCTXIE;
-}
-#endif
-
-/**
- * @brief Error handling routine.
- *
- * @param[in] sra USCI status register containing errors
- * @param[in] sdp pointer to a @p SerialDriver object
- */
-static void set_error(uint16_t sra, SerialDriver * sdp) {
- eventflags_t sts = 0;
-
- if (sra & UCOE)
- sts |= SD_OVERRUN_ERROR;
- if (sra & UCPE)
- sts |= SD_PARITY_ERROR;
- if (sra & UCFE)
- sts |= SD_FRAMING_ERROR;
- osalSysLockFromISR();
- chnAddFlagsI(sdp, sts);
- osalSysUnlockFromISR();
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if MSP430X_SERIAL_USE_USART0 || defined(__DOXYGEN__)
-/**
- * @brief USART0 interrupt handler.
- *
- * @isr
- */
-PORT_IRQ_HANDLER(USCI_A0_VECTOR) {
- msg_t b;
-
- OSAL_IRQ_PROLOGUE();
-
- switch (__even_in_range(UCA0IV, USCI_UART_UCTXCPTIFG)) {
- case USCI_UART_UCRXIFG: /* RX interrupt */
-
- /* Detect errors */
- if (UCA0STATW & UCRXERR)
- set_error(UCA0STATW, &SD0);
-
- /* Data available */
- osalSysLockFromISR();
- sdIncomingDataI(&SD0, UCA0RXBUF);
- osalSysUnlockFromISR();
- break;
-
- case USCI_UART_UCTXIFG: /* TX interrupt */
-
- /* Transmission buffer empty */
- osalSysLockFromISR();
- b = sdRequestDataI(&SD0);
- if (b < Q_OK) {
- chnAddFlagsI(&SD0, CHN_OUTPUT_EMPTY);
- UCA0IE = (UCA0IE & ~UCTXIE) | UCTXCPTIE;
- UCA0IFG |= UCTXIFG; /* If we don't write to TXBUF, IFG won't get set */
- }
- else
- UCA0TXBUF = b;
- osalSysUnlockFromISR();
- break;
-
- case USCI_UART_UCTXCPTIFG: /* TX complete interrupt */
-
- /* Physical transmission end */
- osalSysLockFromISR();
- if (oqIsEmptyI(&SD0.oqueue))
- chnAddFlagsI(&SD0, CHN_TRANSMISSION_END);
- UCA0IE &= ~UCTXCPTIE;
- break;
-
- default: /* other interrupts */
- while (1)
- ;
- break;
- }
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if MSP430X_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-/**
- * @brief USART1 interrupt handler.
- *
- * @isr
- */
-PORT_IRQ_HANDLER(USCI_A1_VECTOR) {
- msg_t b;
-
- OSAL_IRQ_PROLOGUE();
-
- switch (__even_in_range(UCA1IV, USCI_UART_UCTXCPTIFG)) {
- case USCI_UART_UCRXIFG: /* RX interrupt */
-
- /* Detect errors */
- if (UCA1STATW & UCRXERR)
- set_error(UCA1STATW, &SD1);
-
- /* Data available */
- osalSysLockFromISR();
- sdIncomingDataI(&SD1, UCA1RXBUF);
- osalSysUnlockFromISR();
- break;
-
- case USCI_UART_UCTXIFG: /* TX interrupt */
-
- /* Transmission buffer empty */
- osalSysLockFromISR();
- b = sdRequestDataI(&SD1);
- if (b < Q_OK) {
- chnAddFlagsI(&SD1, CHN_OUTPUT_EMPTY);
- UCA1IE = (UCA1IE & ~UCTXIE) | UCTXCPTIE;
- UCA1IFG |= UCTXIFG; /* If we don't write to TXBUF, IFG won't get set */
- }
- else
- UCA1TXBUF = b;
- osalSysUnlockFromISR();
- break;
-
- case USCI_UART_UCTXCPTIFG: /* TX complete interrupt */
-
- /* Physical transmission end */
- osalSysLockFromISR();
- if (oqIsEmptyI(&SD1.oqueue))
- chnAddFlagsI(&SD1, CHN_TRANSMISSION_END);
- UCA1IE &= ~UCTXCPTIE;
- break;
-
- default: /* other interrupts */
- while (1)
- ;
- break;
- }
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if MSP430X_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-/**
- * @brief USART2 interrupt handler.
- *
- * @isr
- */
-PORT_IRQ_HANDLER(USCI_A2_VECTOR) {
- msg_t b;
-
- OSAL_IRQ_PROLOGUE();
-
- switch (__even_in_range(UCA2IV, USCI_UART_UCTXCPTIFG)) {
- case USCI_UART_UCRXIFG: /* RX interrupt */
-
- /* Detect errors */
- if (UCA2STATW & UCRXERR)
- set_error(UCA2STATW, &SD2);
-
- /* Data available */
- osalSysLockFromISR();
- sdIncomingDataI(&SD2, UCA2RXBUF);
- osalSysUnlockFromISR();
- break;
-
- case USCI_UART_UCTXIFG: /* TX interrupt */
-
- /* Transmission buffer empty */
- osalSysLockFromISR();
- b = sdRequestDataI(&SD2);
- if (b < Q_OK) {
- chnAddFlagsI(&SD2, CHN_OUTPUT_EMPTY);
- UCA2IE = (UCA2IE & ~UCTXIE) | UCTXCPTIE;
- UCA2IFG |= UCTXIFG; /* If we don't write to TXBUF, IFG won't get set */
- }
- else
- UCA2TXBUF = b;
- osalSysUnlockFromISR();
- break;
-
- case USCI_UART_UCTXCPTIFG: /* TX complete interrupt */
-
- /* Physical transmission end */
- osalSysLockFromISR();
- if (oqIsEmptyI(&SD2.oqueue))
- chnAddFlagsI(&SD2, CHN_TRANSMISSION_END);
- UCA2IE &= ~UCTXCPTIE;
- break;
-
- default: /* other interrupts */
- while (1)
- ;
- break;
- }
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if MSP430X_SERIAL_USE_USART3 || defined(__DOXYGEN__)
-/**
- * @brief USART3 interrupt handler.
- *
- * @isr
- */
-PORT_IRQ_HANDLER(USCI_A3_VECTOR) {
- msg_t b;
-
- OSAL_IRQ_PROLOGUE();
-
- switch (__even_in_range(UCA3IV, USCI_UART_UCTXCPTIFG)) {
- case USCI_UART_UCRXIFG: /* RX interrupt */
-
- /* Detect errors */
- if (UCA3STATW & UCRXERR)
- set_error(UCA3STATW, &SD3);
-
- /* Data available */
- osalSysLockFromISR();
- sdIncomingDataI(&SD3, UCA3RXBUF);
- osalSysUnlockFromISR();
- break;
-
- case USCI_UART_UCTXIFG: /* TX interrupt */
-
- /* Transmission buffer empty */
- osalSysLockFromISR();
- b = sdRequestDataI(&SD3);
- if (b < Q_OK) {
- chnAddFlagsI(&SD3, CHN_OUTPUT_EMPTY);
- UCA3IE = (UCA3IE & ~UCTXIE) | UCTXCPTIE;
- UCA3IFG |= UCTXIFG; /* If we don't write to TXBUF, IFG won't get set */
- }
- else
- UCA3TXBUF = b;
- osalSysUnlockFromISR();
- break;
-
- case USCI_UART_UCTXCPTIFG: /* TX complete interrupt */
-
- /* Physical transmission end */
- osalSysLockFromISR();
- if (oqIsEmptyI(&SD3.oqueue))
- chnAddFlagsI(&SD3, CHN_TRANSMISSION_END);
- UCA3IE &= ~UCTXCPTIE;
- break;
-
- default: /* other interrupts */
- while (1)
- ;
- break;
- }
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if MSP430X_SERIAL_USE_USART0 == TRUE
- sdObjectInit(&SD0, NULL, notify0);
-#endif
-
-#if MSP430X_SERIAL_USE_USART1 == TRUE
- sdObjectInit(&SD1, NULL, notify1);
-#endif
-
-#if MSP430X_SERIAL_USE_USART2 == TRUE
- sdObjectInit(&SD2, NULL, notify2);
-#endif
-
-#if MSP430X_SERIAL_USE_USART3 == TRUE
- sdObjectInit(&SD3, NULL, notify3);
-#endif
-}
-
-/**
- * @brief Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration.
- * If this parameter is set to @p NULL then a default
- * configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver * sdp, const SerialConfig * config) {
-
- if (config == NULL) {
- config = &default_config;
- }
-
- if (sdp->state == SD_STOP) {
-#if MSP430X_SERIAL_USE_USART0 == TRUE
- if (&SD0 == sdp) {
- usart0_init(config);
- }
-#endif
-#if MSP430X_SERIAL_USE_USART1 == TRUE
- if (&SD1 == sdp) {
- usart1_init(config);
- }
-#endif
-#if MSP430X_SERIAL_USE_USART2 == TRUE
- if (&SD2 == sdp) {
- usart2_init(config);
- }
-#endif
-#if MSP430X_SERIAL_USE_USART3 == TRUE
- if (&SD3 == sdp) {
- usart3_init(config);
- }
-#endif
- }
-}
-
-/**
- * @brief Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- * interrupt vector.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver * sdp) {
-
- if (sdp->state == SD_READY) {
-#if MSP430X_SERIAL_USE_USART0 == TRUE
- if (&SD0 == sdp) {
- UCA0CTLW0 = UCSWRST;
- }
-#endif
-#if MSP430X_SERIAL_USE_USART1 == TRUE
- if (&SD1 == sdp) {
- UCA1CTLW0 = UCSWRST;
- }
-#endif
-#if MSP430X_SERIAL_USE_USART2 == TRUE
- if (&SD2 == sdp) {
- UCA2CTLW0 = UCSWRST;
- }
-#endif
-#if MSP430X_SERIAL_USE_USART3 == TRUE
- if (&SD3 == sdp) {
- UCA3CTLW0 = UCSWRST;
- }
-#endif
- }
-}
-
-#endif /* HAL_USE_SERIAL == TRUE */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_serial_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_serial_lld.h deleted file mode 100644 index 389e5c8..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_serial_lld.h +++ /dev/null @@ -1,320 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file MSP430X/hal_serial_lld.h
- * @brief MSP430X serial subsystem low level driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-#define NONE 0
-#define ODD 2
-#define EVEN 3
-
-#define MSB 1
-#define LSB 0
-
-#define SEVEN 1
-#define EIGHT 0
-
-#define ONE 0
-#define TWO 1
-
-#define MSP430X_SERIAL_SMCLK UCSSEL__SMCLK
-#define MSP430X_SERIAL_UCLK UCSSEL__UCLK
-#define MSP430X_SERIAL_ACLK UCSSEL__ACLK
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name USART0 configuration options
- * @{
- */
-/**
- * @brief USART0 driver enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(MSP430X_SERIAL_USE_USART0) || defined(__DOXYGEN__)
-#define MSP430X_SERIAL_USE_USART0 FALSE
-#endif
-/** @} */
-
-/**
- * @name USART1 configuration options
- * @{
- */
-/**
- * @brief USART1 driver enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(MSP430X_SERIAL_USE_USART1) || defined(__DOXYGEN__)
-#define MSP430X_SERIAL_USE_USART1 FALSE
-#endif
-/** @} */
-
-/**
- * @name USART2 configuration options
- * @{
- */
-/**
- * @brief USART2 driver enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(MSP430X_SERIAL_USE_USART2) || defined(__DOXYGEN__)
-#define MSP430X_SERIAL_USE_USART2 FALSE
-#endif
-/** @} */
-
-/**
- * @name USART3 configuration options
- * @{
- */
-/**
- * @brief USART3 driver enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(MSP430X_SERIAL_USE_USART3) || defined(__DOXYGEN__)
-#define MSP430X_SERIAL_USE_USART3 FALSE
-#endif
-
-#if MSP430X_SERIAL_USE_USART0
- #if !defined(MSP430X_USART0_PARITY)
- #define MSP430X_USART0_PARITY NONE
- #endif
- #if !defined(MSP430X_USART0_ORDER)
- #define MSP430X_USART0_ORDER LSB
- #endif
- #if !defined(MSP430X_USART0_SIZE)
- #define MSP430X_USART0_SIZE EIGHT
- #endif
- #if !defined(MSP430X_USART0_STOP)
- #define MSP430X_USART0_STOP ONE
- #endif
- #if !defined(MSP430X_USART0_CLK_SRC)
- #define MSP430X_USART0_CLK_SRC MSP430X_UCLK_SRC
- #ifndef MSP430X_USART0_CLK_FREQ
- #error "Requested external UART0 clock but no frequency given"
- #endif
- #define MSP430X_USART0_UCSSEL UCSSEL__UCLK
- #elif MSP430X_USART0_CLK_SRC == MSP430X_ACLK_SRC
- #define MSP430X_USART0_CLK_SRC MSP430X_ACLK_SRC
- #define MSP430X_USART0_CLK_FREQ MSP430X_ACLK_FREQ
- #define MSP430X_USART0_UCSSEL UCSSEL__ACLK
- #elif MSP430X_USART0_CLK_SRC == MSP430X_SMCLK_SRC
- #define MSP430X_USART0_CLK_SRC MSP430X_SMCLK_SRC
- #define MSP430X_USART0_CLK_FREQ MSP430X_SMCLK_FREQ
- #define MSP430X_USART0_UCSSEL UCSSEL__SMCLK
- #else
- #error "MSP430X_USART0_CLK_SRC invalid"
- #endif
-#endif
-
-#if MSP430X_SERIAL_USE_USART1
- #if !defined(MSP430X_USART1_PARITY)
- #define MSP430X_USART1_PARITY NONE
- #endif
- #if !defined(MSP430X_USART1_ORDER)
- #define MSP430X_USART1_ORDER LSB
- #endif
- #if !defined(MSP430X_USART1_SIZE)
- #define MSP430X_USART1_SIZE EIGHT
- #endif
- #if !defined(MSP430X_USART1_STOP)
- #define MSP430X_USART1_STOP ONE
- #endif
- #if !defined(MSP430X_USART1_CLK_SRC)
- #define MSP430X_USART1_CLK_SRC MSP430X_UCLK_SRC
- #ifndef MSP430X_USART1_CLK_FREQ
- #error "Requested external UART0 clock but no frequency given"
- #endif
- #define MSP430X_USART1_UCSSEL UCSSEL__UCLK
- #elif MSP430X_USART1_CLK_SRC == MSP430X_ACLK_SRC
- #define MSP430X_USART1_CLK_SRC MSP430X_ACLK_SRC
- #define MSP430X_USART1_CLK_FREQ MSP430X_ACLK_FREQ
- #define MSP430X_USART1_UCSSEL UCSSEL__ACLK
- #elif MSP430X_USART1_CLK_SRC == MSP430X_SMCLK_SRC
- #define MSP430X_USART1_CLK_SRC MSP430X_SMCLK_SRC
- #define MSP430X_USART1_CLK_FREQ MSP430X_SMCLK_FREQ
- #define MSP430X_USART1_UCSSEL UCSSEL__SMCLK
- #else
- #error "MSP430X_USART1_CLK_SRC invalid"
- #endif
-#endif
-
-#if MSP430X_SERIAL_USE_USART2
- #if !defined(MSP430X_USART2_PARITY)
- #define MSP430X_USART2_PARITY NONE
- #endif
- #if !defined(MSP430X_USART2_ORDER)
- #define MSP430X_USART2_ORDER LSB
- #endif
- #if !defined(MSP430X_USART2_SIZE)
- #define MSP430X_USART2_SIZE EIGHT
- #endif
- #if !defined(MSP430X_USART2_STOP)
- #define MSP430X_USART2_STOP ONE
- #endif
- #if !defined(MSP430X_USART2_CLK_SRC)
- #define MSP430X_USART2_CLK_SRC MSP430X_UCLK_SRC
- #ifndef MSP430X_USART2_CLK_FREQ
- #error "Requested external UART0 clock but no frequency given"
- #endif
- #define MSP430X_USART2_UCSSEL UCSSEL__UCLK
- #elif MSP430X_USART2_CLK_SRC == MSP430X_ACLK_SRC
- #define MSP430X_USART2_CLK_SRC MSP430X_ACLK_SRC
- #define MSP430X_USART2_CLK_FREQ MSP430X_ACLK_FREQ
- #define MSP430X_USART2_UCSSEL UCSSEL__ACLK
- #elif MSP430X_USART2_CLK_SRC == MSP430X_SMCLK_SRC
- #define MSP430X_USART2_CLK_SRC MSP430X_SMCLK_SRC
- #define MSP430X_USART2_CLK_FREQ MSP430X_SMCLK_FREQ
- #define MSP430X_USART2_UCSSEL UCSSEL__SMCLK
- #else
- #error "MSP430X_USART2_CLK_SRC invalid"
- #endif
-#endif
-
-#if MSP430X_SERIAL_USE_USART3
- #if !defined(MSP430X_USART3_PARITY)
- #define MSP430X_USART3_PARITY NONE
- #endif
- #if !defined(MSP430X_USART3_ORDER)
- #define MSP430X_USART3_ORDER LSB
- #endif
- #if !defined(MSP430X_USART3_SIZE)
- #define MSP430X_USART3_SIZE EIGHT
- #endif
- #if !defined(MSP430X_USART3_STOP)
- #define MSP430X_USART3_STOP ONE
- #endif
- #if !defined(MSP430X_USART3_CLK_SRC)
- #define MSP430X_USART3_CLK_SRC MSP430X_UCLK_SRC
- #ifndef MSP430X_USART3_CLK_FREQ
- #error "Requested external UART0 clock but no frequency given"
- #endif
- #define MSP430X_USART3_UCSSEL UCSSEL__UCLK
- #elif MSP430X_USART3_CLK_SRC == MSP430X_ACLK_SRC
- #define MSP430X_USART3_CLK_SRC MSP430X_ACLK_SRC
- #define MSP430X_USART3_CLK_FREQ MSP430X_ACLK_FREQ
- #define MSP430X_USART3_UCSSEL UCSSEL__ACLK
- #elif MSP430X_USART3_CLK_SRC == MSP430X_SMCLK_SRC
- #define MSP430X_USART3_CLK_SRC MSP430X_SMCLK_SRC
- #define MSP430X_USART3_CLK_FREQ MSP430X_SMCLK_FREQ
- #define MSP430X_USART3_UCSSEL UCSSEL__SMCLK
- #else
- #error "MSP430X_USART3_CLK_SRC invalid"
- #endif
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief MSP430X Serial Driver configuration structure.
- * @details An insance of this structure must be passed to @p sdStart()
- * in order to configure and start a serial driver operations.
- * @note This structure content is architecture dependent, each driver
- * implementation defines its own version and the custom static
- * initializers.
- */
-typedef struct {
- /**
- * @brief Bit rate.
- */
- uint32_t sc_bitrate;
-
- /* End of the mandatory fields.*/
-} SerialConfig;
-
-/**
- * @brief @p SerialDriver specific data.
- */
-#define _serial_driver_data \
- _base_asynchronous_channel_data \
- /* Driver state.*/ \
- sdstate_t state; \
- /* Input queue.*/ \
- input_queue_t iqueue; \
- /* Output queue.*/ \
- output_queue_t oqueue; \
- /* Input circular buffer.*/ \
- uint8_t ib[SERIAL_BUFFERS_SIZE]; \
- /* Output circular buffer.*/ \
- uint8_t ob[SERIAL_BUFFERS_SIZE]; \
- /* End of the mandatory fields.*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if (MSP430X_SERIAL_USE_USART0 == TRUE) && !defined(__DOXYGEN__)
-extern SerialDriver SD0;
-#endif
-
-#if (MSP430X_SERIAL_USE_USART1 == TRUE) && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#if (MSP430X_SERIAL_USE_USART2 == TRUE) && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#if (MSP430X_SERIAL_USE_USART3 == TRUE) && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void sd_lld_init(void);
- void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
- void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL == TRUE */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_spi_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_spi_lld.c deleted file mode 100644 index 70a357e..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_spi_lld.c +++ /dev/null @@ -1,578 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file hal_spi_lld.c
- * @brief MSP430X SPI subsystem low level driver source.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "hal.h"
-
-#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief SPIA0 driver identifier.
- */
-#if (MSP430X_SPI_USE_SPIA0 == TRUE) || defined(__DOXYGEN__)
-SPIDriver SPIDA0;
-#endif
-
-/**
- * @brief SPIA1 driver identifier.
- */
-#if (MSP430X_SPI_USE_SPIA1 == TRUE) || defined(__DOXYGEN__)
-SPIDriver SPIDA1;
-#endif
-
-/**
- * @brief SPIA2 driver identifier.
- */
-#if (MSP430X_SPI_USE_SPIA2 == TRUE) || defined(__DOXYGEN__)
-SPIDriver SPIDA2;
-#endif
-
-/**
- * @brief SPIA3 driver identifier.
- */
-#if (MSP430X_SPI_USE_SPIA3 == TRUE) || defined(__DOXYGEN__)
-SPIDriver SPIDA3;
-#endif
-
-/**
- * @brief SPIB0 driver identifier.
- */
-#if (MSP430X_SPI_USE_SPIB0 == TRUE) || defined(__DOXYGEN__)
-SPIDriver SPIDB0;
-#endif
-
-/**
- * @brief SPIB1 driver identifier.
- */
-#if (MSP430X_SPI_USE_SPIB1 == TRUE) || defined(__DOXYGEN__)
-SPIDriver SPIDB1;
-#endif
-
-/**
- * @brief SPIB2 driver identifier.
- */
-#if (MSP430X_SPI_USE_SPIB2 == TRUE) || defined(__DOXYGEN__)
-SPIDriver SPIDB2;
-#endif
-
-/**
- * @brief SPIB3 driver identifier.
- */
-#if (MSP430X_SPI_USE_SPIB3 == TRUE) || defined(__DOXYGEN__)
-SPIDriver SPIDB3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-static const uint16_t dummytx = 0xFFFFU;
-static uint16_t dummyrx;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-static void init_transfer(SPIDriver * spip) {
-
-#if MSP430X_SPI_EXCLUSIVE_DMA == TRUE || defined(__DOXYGEN__)
- if (spip->config->dmarx_index > MSP430X_DMA_CHANNELS) {
- dmaRequest(&(spip->rx_req), TIME_INFINITE);
- }
- else {
- dmaTransfer(&(spip->dmarx), &(spip->rx_req));
- }
- if (spip->config->dmatx_index > MSP430X_DMA_CHANNELS) {
- dmaRequest(&(spip->tx_req), TIME_INFINITE);
- }
- else {
- dmaTransfer(&(spip->dmatx), &(spip->tx_req));
- }
-#else
- dmaRequest(&(spip->rx_req), TIME_INFINITE);
- dmaRequest(&(spip->tx_req), TIME_INFINITE);
-#endif
-
- *(spip->ifg) |= UCTXIFG;
-}
-
-/**
- * @brief Shared end-of-transfer callback.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @note This function is called in ISR context by the DMA code.
- */
-static void spi_lld_end_of_transfer(void * spip) {
-
- /* So that future transfers will actually work */
- *(((SPIDriver *)spip)->ifg) &= ~(UCTXIFG);
- /* NOTE to future me - this macro sets the driver state and calls the
- * configured callback end_cb, if applicable. That callback doesn't seem to
- * be modifiable without reconfiguring the whole driver. */
- _spi_isr_code((SPIDriver *)spip);
-}
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if MSP430X_SPI_USE_SPIA0 == TRUE
- /* Driver initialization.*/
- spiObjectInit(&SPIDA0);
- SPIDA0.regs = (msp430x_spi_reg_t *)(&UCA0CTLW0);
- SPIDA0.ifg = (volatile uint16_t *)&UCA0IFG;
- SPIDA0.tx_req.trigger = DMA_TRIGGER_MNEM(UCA0TXIFG);
- SPIDA0.rx_req.trigger = DMA_TRIGGER_MNEM(UCA0RXIFG);
- SPIDA0.tx_req.dest_addr = &(SPIDA0.regs->txbuf);
- SPIDA0.rx_req.source_addr = &(SPIDA0.regs->rxbuf);
- SPIDA0.tx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDA0.rx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDA0.tx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDA0.rx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDA0.tx_req.callback.callback = NULL;
- SPIDA0.tx_req.callback.args = NULL;
- SPIDA0.rx_req.callback.callback = spi_lld_end_of_transfer;
- SPIDA0.rx_req.callback.args = &SPIDA0;
-/* NOTE to my future self - this must be SINGLE because BLOCK and BURST
- * don't wait for triggers and would overflow both buffers. Don't worry, it
- * still works - the transfer isn't complete until SZ bytes are transferred */
-#endif
-
-#if MSP430X_SPI_USE_SPIA1 == TRUE
- /* Driver initialization.*/
- spiObjectInit(&SPIDA1);
- SPIDA1.regs = (msp430x_spi_reg_t *)(&UCA1CTLW0);
- SPIDA1.ifg = (volatile uint16_t *)&UCA1IFG;
- SPIDA1.tx_req.trigger = DMA_TRIGGER_MNEM(UCA1TXIFG);
- SPIDA1.rx_req.trigger = DMA_TRIGGER_MNEM(UCA1RXIFG);
- SPIDA1.tx_req.dest_addr = &(SPIDA1.regs->txbuf);
- SPIDA1.rx_req.source_addr = &(SPIDA1.regs->rxbuf);
- SPIDA1.tx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDA1.rx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDA1.tx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDA1.rx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDA1.tx_req.callback.callback = NULL;
- SPIDA1.tx_req.callback.args = NULL;
- SPIDA1.rx_req.callback.callback = spi_lld_end_of_transfer;
- SPIDA1.rx_req.callback.args = &SPIDA1;
-#endif
-
-#if MSP430X_SPI_USE_SPIA2 == TRUE
- /* Driver initialization.*/
- spiObjectInit(&SPIDA2);
- SPIDA2.regs = (msp430x_spi_reg_t *)(&UCA2CTLW0);
- SPIDA2.ifg = (volatile uint16_t *)&UCA2IFG;
- SPIDA2.tx_req.trigger = DMA_TRIGGER_MNEM(UCA2TXIFG);
- SPIDA2.rx_req.trigger = DMA_TRIGGER_MNEM(UCA2RXIFG);
- SPIDA2.tx_req.dest_addr = &(SPIDA2.regs->txbuf);
- SPIDA2.rx_req.source_addr = &(SPIDA2.regs->rxbuf);
- SPIDA2.tx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDA2.rx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDA2.tx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDA2.rx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDA2.tx_req.callback.callback = NULL;
- SPIDA2.tx_req.callback.args = NULL;
- SPIDA2.rx_req.callback.callback = spi_lld_end_of_transfer;
- SPIDA2.rx_req.callback.args = &SPIDA2;
-#endif
-
-#if MSP430X_SPI_USE_SPIA3 == TRUE
- /* Driver initialization.*/
- spiObjectInit(&SPIDA3);
- SPIDA3.regs = (msp430x_spi_reg_t *)(&UCA3CTLW0);
- SPIDA3.ifg = (volatile uint16_t *)&UCA3IFG;
- SPIDA3.tx_req.trigger = DMA_TRIGGER_MNEM(UCA3TXIFG);
- SPIDA3.rx_req.trigger = DMA_TRIGGER_MNEM(UCA3RXIFG);
- SPIDA3.tx_req.dest_addr = &(SPIDA3.regs->txbuf);
- SPIDA3.rx_req.source_addr = &(SPIDA3.regs->rxbuf);
- SPIDA3.tx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDA3.rx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDA3.tx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDA3.rx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDA3.tx_req.callback.callback = NULL;
- SPIDA3.tx_req.callback.args = NULL;
- SPIDA3.rx_req.callback.callback = spi_lld_end_of_transfer;
- SPIDA3.rx_req.callback.args = &SPIDA3;
-#endif
-
-#if MSP430X_SPI_USE_SPIB0 == TRUE
- /* Driver initialization.*/
- spiObjectInit(&SPIDB0);
- SPIDB0.regs = (msp430x_spi_reg_t *)(&UCB0CTLW0);
- SPIDB0.ifg = (volatile uint16_t *)&UCB0IFG;
- SPIDB0.tx_req.trigger = DMA_TRIGGER_MNEM(UCB0TXIFG0);
- SPIDB0.rx_req.trigger = DMA_TRIGGER_MNEM(UCB0RXIFG0);
- SPIDB0.tx_req.dest_addr = &(SPIDB0.regs->txbuf);
- SPIDB0.rx_req.source_addr = &(SPIDB0.regs->rxbuf);
- SPIDB0.tx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDB0.rx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDB0.tx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDB0.rx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDB0.tx_req.callback.callback = NULL;
- SPIDB0.tx_req.callback.args = NULL;
- SPIDB0.rx_req.callback.callback = spi_lld_end_of_transfer;
- SPIDB0.rx_req.callback.args = &SPIDB0;
-#endif
-
-#if MSP430X_SPI_USE_SPIB1 == TRUE
- /* Driver initialization.*/
- spiObjectInit(&SPIDB1);
- SPIDB1.regs = (msp430x_spi_reg_t *)(&UCB1CTLW0);
- SPIDB1.ifg = (volatile uint16_t *)&UCB1IFG;
- SPIDB1.tx_req.trigger = DMA_TRIGGER_MNEM(UCB1TXIFG0);
- SPIDB1.rx_req.trigger = DMA_TRIGGER_MNEM(UCB1RXIFG0);
- SPIDB1.tx_req.dest_addr = &(SPIDB1.regs->txbuf);
- SPIDB1.rx_req.source_addr = &(SPIDB1.regs->rxbuf);
- SPIDB1.tx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDB1.rx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDB1.tx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDB1.rx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDB1.tx_req.callback.callback = NULL;
- SPIDB1.tx_req.callback.args = NULL;
- SPIDB1.rx_req.callback.callback = spi_lld_end_of_transfer;
- SPIDB1.rx_req.callback.args = &SPIDB1;
-#endif
-
-#if MSP430X_SPI_USE_SPIB2 == TRUE
- /* Driver initialization.*/
- spiObjectInit(&SPIDB2);
- SPIDB2.regs = (msp430x_spi_reg_t *)(&UCB2CTLW0);
- SPIDB2.ifg = (volatile uint16_t *)&UCB2IFG;
- SPIDB2.tx_req.trigger = DMA_TRIGGER_MNEM(UCB2TXIFG0);
- SPIDB2.rx_req.trigger = DMA_TRIGGER_MNEM(UCB2RXIFG0);
- SPIDB2.tx_req.dest_addr = &(SPIDB2.regs->txbuf);
- SPIDB2.rx_req.source_addr = &(SPIDB2.regs->rxbuf);
- SPIDB2.tx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDB2.rx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDB2.tx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDB2.rx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDB2.tx_req.callback.callback = NULL;
- SPIDB2.tx_req.callback.args = NULL;
- SPIDB2.rx_req.callback.callback = spi_lld_end_of_transfer;
- SPIDB2.rx_req.callback.args = &SPIDB2;
-#endif
-
-#if MSP430X_SPI_USE_SPIB3 == TRUE
- /* Driver initialization.*/
- spiObjectInit(&SPIDB3);
- SPIDB3.regs = (msp430x_spi_reg_t *)(&UCB3CTLW0);
- SPIDB3.ifg = (volatile uint16_t *)&UCB3IFG;
- SPIDB3.tx_req.trigger = DMA_TRIGGER_MNEM(UCB3TXIFG0);
- SPIDB3.rx_req.trigger = DMA_TRIGGER_MNEM(UCB3RXIFG0);
- SPIDB3.tx_req.dest_addr = &(SPIDB3.regs->txbuf);
- SPIDB3.rx_req.source_addr = &(SPIDB3.regs->rxbuf);
- SPIDB3.tx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDB3.rx_req.data_mode = MSP430X_DMA_SRCBYTE | MSP430X_DMA_DSTBYTE;
- SPIDB3.tx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDB3.rx_req.transfer_mode = MSP430X_DMA_SINGLE;
- SPIDB3.tx_req.callback.callback = NULL;
- SPIDB3.tx_req.callback.args = NULL;
- SPIDB3.rx_req.callback.callback = spi_lld_end_of_transfer;
- SPIDB3.rx_req.callback.args = &SPIDB3;
-#endif
-}
-
-/**
- * @brief Configures and activates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver * spip) {
-
- if (spip->state == SPI_STOP) {
-/* Enables the peripheral.*/
-#if MSP430X_SPI_EXCLUSIVE_DMA == TRUE
- /* Claim DMA streams here */
- bool b;
- if (spip->config->dmatx_index < MSP430X_DMA_CHANNELS) {
- b = dmaAcquire(&(spip->dmatx), spip->config->dmatx_index);
- osalDbgAssert(!b, "stream already allocated");
- }
- if (spip->config->dmarx_index < MSP430X_DMA_CHANNELS) {
- b = dmaAcquire(&(spip->dmarx), spip->config->dmarx_index);
- osalDbgAssert(!b, "stream already allocated");
- }
-#endif /* MSP430X_SPI_EXCLUSIVE_DMA */
- }
- uint16_t brw = 0;
- uint8_t ssel = 0;
-#if MSP430X_SPI_USE_SPIA0
- if (spip == &SPIDA0) {
- brw = MSP430X_SPIA0_CLK_FREQ / spip->config->bit_rate;
- ssel = MSP430X_SPIA0_UCSSEL;
- }
-#endif
-#if MSP430X_SPI_USE_SPIA1
- if (spip == &SPIDA1) {
- brw = MSP430X_SPIA1_CLK_FREQ / spip->config->bit_rate;
- ssel = MSP430X_SPIA1_UCSSEL;
- }
-#endif
-#if MSP430X_SPI_USE_SPIA2
- if (spip == &SPIDA2) {
- brw = MSP430X_SPIA2_CLK_FREQ / spip->config->bit_rate;
- ssel = MSP430X_SPIA2_UCSSEL;
- }
-#endif
-#if MSP430X_SPI_USE_SPIA3
- if (spip == &SPIDA3) {
- brw = MSP430X_SPIA3_CLK_FREQ / spip->config->bit_rate;
- ssel = MSP430X_SPIA3_UCSSEL;
- }
-#endif
-#if MSP430X_SPI_USE_SPIB0
- if (spip == &SPIDB0) {
- brw = MSP430X_SPIB0_CLK_FREQ / spip->config->bit_rate;
- ssel = MSP430X_SPIB0_UCSSEL;
- }
-#endif
-#if MSP430X_SPI_USE_SPIB1
- if (spip == &SPIDB1) {
- brw = MSP430X_SPIB1_CLK_FREQ / spip->config->bit_rate;
- ssel = MSP430X_SPIB1_UCSSEL;
- }
-#endif
-#if MSP430X_SPI_USE_SPIB2
- if (spip == &SPIDB2) {
- brw = MSP430X_SPIB2_CLK_FREQ / spip->config->bit_rate;
- ssel = MSP430X_SPIB2_UCSSEL;
- }
-#endif
-#if MSP430X_SPI_USE_SPIB3
- if (spip == &SPIDB3) {
- brw = MSP430X_SPIB3_CLK_FREQ / spip->config->bit_rate;
- ssel = MSP430X_SPIB3_UCSSEL;
- }
-#endif
- /* Configures the peripheral.*/
- spip->regs->ctlw0 = UCSWRST;
- spip->regs->brw = brw;
- spip->regs->ctlw0 =
- (spip->config->spi_mode << 14) | (spip->config->bit_order << 13) |
- (spip->config->data_size << 12) | (UCMST) |
- ((spip->config->ss_line ? 0 : 2) << 9) | (UCSYNC) | (ssel) | (UCSTEM);
- *(spip->ifg) = 0;
-}
-
-/**
- * @brief Deactivates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver * spip) {
-
- if (spip->state == SPI_READY) {
-/* Disables the peripheral.*/
-#if MSP430X_SPI_EXCLUSIVE_DMA == TRUE
- dmaRelease(&(spip->dmatx));
- dmaRelease(&(spip->dmarx));
-#endif
- spip->regs->ctlw0 = UCSWRST;
- }
-}
-
-/**
- * @brief Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver * spip) {
-
- if (spip->config->ss_line) {
- palClearLine(spip->config->ss_line);
- }
-}
-
-/**
- * @brief Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver * spip) {
-
- if (spip->config->ss_line) {
- palSetLine(spip->config->ss_line);
- }
-}
-
-/**
- * @brief Ignores data on the SPI bus.
- * @details This asynchronous function starts the transmission of a series of
- * idle bytes on the SPI bus and ignores the received data.
- * @post At the end of the operation the configured callback is invoked.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of bytes to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver * spip, size_t n) {
-
- spip->tx_req.source_addr = &dummytx;
- spip->tx_req.size = n;
- spip->tx_req.addr_mode = 0;
-
- spip->rx_req.dest_addr = &dummyrx;
- spip->rx_req.size = n;
- spip->rx_req.addr_mode = 0;
-
- init_transfer(spip);
-}
-
-/**
- * @brief Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- * operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver * spip,
- size_t n,
- const void * txbuf,
- void * rxbuf) {
-
- spip->tx_req.source_addr = txbuf;
- spip->tx_req.size = n;
- spip->tx_req.addr_mode = MSP430X_DMA_SRCINCR;
-
- spip->rx_req.dest_addr = rxbuf;
- spip->rx_req.size = n;
- spip->rx_req.addr_mode = MSP430X_DMA_DSTINCR;
-
- init_transfer(spip);
-}
-
-/**
- * @brief Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to send
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver * spip, size_t n, const void * txbuf) {
-
- spip->tx_req.source_addr = txbuf;
- spip->tx_req.size = n;
- spip->tx_req.addr_mode = MSP430X_DMA_SRCINCR;
-
- spip->rx_req.dest_addr = &dummyrx;
- spip->rx_req.size = n;
- spip->rx_req.addr_mode = 0;
-
- init_transfer(spip);
-}
-
-/**
- * @brief Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to receive
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver * spip, size_t n, void * rxbuf) {
-
- spip->tx_req.source_addr = &dummytx;
- spip->tx_req.size = n;
- spip->tx_req.addr_mode = 0;
-
- spip->rx_req.dest_addr = rxbuf;
- spip->rx_req.size = n;
- spip->rx_req.addr_mode = MSP430X_DMA_DSTINCR;
-
- init_transfer(spip);
-}
-
-/**
- * @brief Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- * synchronization method. This function is useful when exchanging
- * small amount of data on high speed channels, usually in this
- * situation is much more efficient just wait for completion using
- * polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] frame the data frame to send over the SPI bus
- * @return The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver * spip, uint16_t frame) {
-
- osalDbgAssert(!(frame & 0xFF00U), "16-bit transfers not supported");
-
- while (!(*(spip->ifg) & UCTXIFG))
- ;
- spip->regs->txbuf = frame;
- while (!(*(spip->ifg) & UCRXIFG))
- ;
- return spip->regs->rxbuf;
-}
-
-#endif /* HAL_USE_SPI == TRUE */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_spi_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_spi_lld.h deleted file mode 100644 index ebf14c8..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_spi_lld.h +++ /dev/null @@ -1,642 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file hal_spi_lld.h
- * @brief MSP430X SPI subsystem low level driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef HAL_SPI_LLD_H
-#define HAL_SPI_LLD_H
-
-#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__)
-
-#include "hal_dma_lld.h"
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name MSP430X configuration options
- * @{
- */
-/**
- * @brief SPIA0 driver enable switch.
- * @details If set to @p TRUE the support for SPIA0 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(MSP430X_SPI_USE_SPIA0) || defined(__DOXYGEN__)
-#define MSP430X_SPI_USE_SPIA0 FALSE
-#endif
-
-/**
- * @brief SPIA1 driver enable switch.
- * @details If set to @p TRUE the support for SPIA1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(MSP430X_SPI_USE_SPIA1) || defined(__DOXYGEN__)
-#define MSP430X_SPI_USE_SPIA1 FALSE
-#endif
-
-/**
- * @brief SPIA2 driver enable switch.
- * @details If set to @p TRUE the support for SPIA2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(MSP430X_SPI_USE_SPIA2) || defined(__DOXYGEN__)
-#define MSP430X_SPI_USE_SPIA2 FALSE
-#endif
-
-/**
- * @brief SPIA3 driver enable switch.
- * @details If set to @p TRUE the support for SPIA3 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(MSP430X_SPI_USE_SPIA3) || defined(__DOXYGEN__)
-#define MSP430X_SPI_USE_SPIA3 FALSE
-#endif
-
-/**
- * @brief SPIB0 driver enable switch.
- * @details If set to @p TRUE the support for SPIB0 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(MSP430X_SPI_USE_SPIB0) || defined(__DOXYGEN__)
-#define MSP430X_SPI_USE_SPIB0 FALSE
-#endif
-
-/**
- * @brief SPIB1 driver enable switch.
- * @details If set to @p TRUE the support for SPIB1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(MSP430X_SPI_USE_SPIB1) || defined(__DOXYGEN__)
-#define MSP430X_SPI_USE_SPIB1 FALSE
-#endif
-
-/**
- * @brief SPIB2 driver enable switch.
- * @details If set to @p TRUE the support for SPIB2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(MSP430X_SPI_USE_SPIB2) || defined(__DOXYGEN__)
-#define MSP430X_SPI_USE_SPIB2 FALSE
-#endif
-
-/**
- * @brief SPIB3 driver enable switch.
- * @details If set to @p TRUE the support for SPIB3 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(MSP430X_SPI_USE_SPIB3) || defined(__DOXYGEN__)
-#define MSP430X_SPI_USE_SPIB3 FALSE
-#endif
-
-/**
- * @brief Exclusive DMA enable switch.
- * @details If set to @p TRUE the support for exclusive DMA is included.
- * @note This increases the size of the compiled executable somewhat.
- * @note The default is @p FALSE.
- */
-#if !defined(MSP430X_SPI_EXCLUSIVE_DMA) | defined(__DOXYGEN__)
-#define MSP430X_SPI_EXCLUSIVE_DMA FALSE
-#endif
-
-/**
- * @brief SPIA0 clock source switch.
- * @details Sets the clock source for SPIA0.
- * @note Legal values are @p MSP430X_SMCLK_SRC or @p MSP430X_ACLK_SRC.
- * @note The default is @p MSP430X_SMCLK_SRC.
- */
-#if !defined(MSP430X_SPIA0_CLK_SRC)
- #define MSP430X_SPIA0_CLK_SRC MSP430X_SMCLK_SRC
-#endif
-
-/**
- * @brief SPIA1 clock source switch.
- * @details Sets the clock source for SPIA1.
- * @note Legal values are @p MSP430X_SMCLK_SRC or @p MSP430X_ACLK_SRC.
- * @note The default is @p MSP430X_SMCLK_SRC.
- */
-#if !defined(MSP430X_SPIA1_CLK_SRC)
- #define MSP430X_SPIA1_CLK_SRC MSP430X_SMCLK_SRC
-#endif
-
-/**
- * @brief SPIA2 clock source switch.
- * @details Sets the clock source for SPIA2.
- * @note Legal values are @p MSP430X_SMCLK_SRC or @p MSP430X_ACLK_SRC.
- * @note The default is @p MSP430X_SMCLK_SRC.
- */
-#if !defined(MSP430X_SPIA2_CLK_SRC)
- #define MSP430X_SPIA2_CLK_SRC MSP430X_SMCLK_SRC
-#endif
-
-/**
- * @brief SPIA3 clock source switch.
- * @details Sets the clock source for SPIA3.
- * @note Legal values are @p MSP430X_SMCLK_SRC or @p MSP430X_ACLK_SRC.
- * @note The default is @p MSP430X_SMCLK_SRC.
- */
-#if !defined(MSP430X_SPIA3_CLK_SRC)
- #define MSP430X_SPIA3_CLK_SRC MSP430X_SMCLK_SRC
-#endif
-
-/**
- * @brief SPIB0 clock source switch.
- * @details Sets the clock source for SPIB0.
- * @note Legal values are @p MSP430X_SMCLK_SRC or @p MSP430X_ACLK_SRC.
- * @note The default is @p MSP430X_SMCLK_SRC.
- */
-#if !defined(MSP430X_SPIB0_CLK_SRC)
- #define MSP430X_SPIB0_CLK_SRC MSP430X_SMCLK_SRC
-#endif
-
-/**
- * @brief SPIB1 clock source switch.
- * @details Sets the clock source for SPIB1.
- * @note Legal values are @p MSP430X_SMCLK_SRC or @p MSP430X_ACLK_SRC.
- * @note The default is @p MSP430X_SMCLK_SRC.
- */
-#if !defined(MSP430X_SPIB1_CLK_SRC)
- #define MSP430X_SPIB1_CLK_SRC MSP430X_SMCLK_SRC
-#endif
-
-/**
- * @brief SPIB2 clock source switch.
- * @details Sets the clock source for SPIB2.
- * @note Legal values are @p MSP430X_SMCLK_SRC or @p MSP430X_ACLK_SRC.
- * @note The default is @p MSP430X_SMCLK_SRC.
- */
-#if !defined(MSP430X_SPIB2_CLK_SRC)
- #define MSP430X_SPIB2_CLK_SRC MSP430X_SMCLK_SRC
-#endif
-
-/**
- * @brief SPIB3 clock source switch.
- * @details Sets the clock source for SPIB3.
- * @note Legal values are @p MSP430X_SMCLK_SRC or @p MSP430X_ACLK_SRC.
- * @note The default is @p MSP430X_SMCLK_SRC.
- */
-#if !defined(MSP430X_SPIB3_CLK_SRC)
- #define MSP430X_SPIB3_CLK_SRC MSP430X_SMCLK_SRC
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if MSP430X_SPI_USE_SPIA0 && !defined(__MSP430_HAS_EUSCI_A0__)
- #error "Cannot find MSP430X_USCI module to use for SPIA0"
-#endif
-
-#if MSP430X_SPI_USE_SPIA1 && !defined(__MSP430_HAS_EUSCI_A1__)
- #error "Cannot find MSP430X_USCI module to use for SPIA1"
-#endif
-
-#if MSP430X_SPI_USE_SPIA2 && !defined(__MSP430_HAS_EUSCI_A2__)
- #error "Cannot find MSP430X_USCI module to use for SPIA2"
-#endif
-
-#if MSP430X_SPI_USE_SPIA3 && !defined(__MSP430_HAS_EUSCI_A3__)
- #error "Cannot find MSP430X_USCI module to use for SPIA3"
-#endif
-
-#if MSP430X_SPI_USE_SPIB0 && !defined(__MSP430_HAS_EUSCI_B0__)
- #error "Cannot find MSP430X_USCI module to use for SPIB0"
-#endif
-
-#if MSP430X_SPI_USE_SPIB1 && !defined(__MSP430_HAS_EUSCI_B1__)
- #error "Cannot find MSP430X_USCI module to use for SPIB1"
-#endif
-
-#if MSP430X_SPI_USE_SPIB2 && !defined(__MSP430_HAS_EUSCI_B2__)
- #error "Cannot find MSP430X_USCI module to use for SPIB2"
-#endif
-
-#if MSP430X_SPI_USE_SPIB3 && !defined(__MSP430_HAS_EUSCI_B3__)
- #error "Cannot find MSP430X_USCI module to use for SPIB3"
-#endif
-
-#if MSP430X_SPI_USE_SPIA0
- #ifdef MSP430X_USCI_A0_USED
- #error "USCI module A0 already in use - SPIA0 not available"
- #else
- #define MSP430X_USCI_A0_USED
- #endif
-#endif
-
-#if MSP430X_SPI_USE_SPIA1
- #ifdef MSP430X_USCI_A1_USED
- #error "USCI module A1 already in use - SPIA1 not available"
- #else
- #define MSP430X_USCI_A1_USED
- #endif
-#endif
-
-#if MSP430X_SPI_USE_SPIA2
- #ifdef MSP430X_USCI_A2_USED
- #error "USCI module A2 already in use - SPIA2 not available"
- #else
- #define MSP430X_USCI_A2_USED
- #endif
-#endif
-
-#if MSP430X_SPI_USE_SPIA3
- #ifdef MSP430X_USCI_A3_USED
- #error "USCI module A3 already in use - SPIA3 not available"
- #else
- #define MSP430X_USCI_A3_USED
- #endif
-#endif
-
-#if MSP430X_SPI_USE_SPIB0
- #ifdef MSP430X_USCI_B0_USED
- #error "USCI module B0 already in use - SPIB0 not available"
- #else
- #define MSP430X_USCI_B0_USED
- #endif
-#endif
-
-#if MSP430X_SPI_USE_SPIB1
- #ifdef MSP430X_USCI_B1_USED
- #error "USCI module B1 already in use - SPIB1 not available"
- #else
- #define MSP430X_USCI_B1_USED
- #endif
-#endif
-
-#if MSP430X_SPI_USE_SPIB2
- #ifdef MSP430X_USCI_B2_USED
- #error "USCI module B2 already in use - SPIB2 not available"
- #else
- #define MSP430X_USCI_B2_USED
- #endif
-#endif
-
-#if MSP430X_SPI_USE_SPIB3
- #ifdef MSP430X_USCI_B3_USED
- #error "USCI module B3 already in use - SPIB3 not available"
- #else
- #define MSP430X_USCI_B3_USED
- #endif
-#endif
-
-#if defined(MSP430X_SPIA0_TX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIA0 TX, but requested index is invalid"
-#endif
-#if defined(MSP430X_SPIA0_RX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIA0 RX, but requested index is invalid"
-#endif
-
-#if defined(MSP430X_SPIA1_TX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIA1 TX, but requested index is invalid"
-#endif
-#if defined(MSP430X_SPIA1_RX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIA1 RX, but requested index is invalid"
-#endif
-
-#if defined(MSP430X_SPIA2_TX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIA2 TX, but requested index is invalid"
-#endif
-#if defined(MSP430X_SPIA2_RX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIA2 RX, but requested index is invalid"
-#endif
-
-#if defined(MSP430X_SPIA3_TX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIA3 TX, but requested index is invalid"
-#endif
-#if defined(MSP430X_SPIA3_RX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIA3 RX, but requested index is invalid"
-#endif
-
-#if defined(MSP430X_SPIB0_TX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIB0 TX, but requested index is invalid"
-#endif
-#if defined(MSP430X_SPIB0_RX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIB0 RX, but requested index is invalid"
-#endif
-
-#if defined(MSP430X_SPIB1_TX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIB1 TX, but requested index is invalid"
-#endif
-#if defined(MSP430X_SPIB1_RX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIB1 RX, but requested index is invalid"
-#endif
-
-#if defined(MSP430X_SPIB2_TX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIB2 TX, but requested index is invalid"
-#endif
-#if defined(MSP430X_SPIB2_RX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIB2 RX, but requested index is invalid"
-#endif
-
-#if defined(MSP430X_SPIB3_TX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIB3 TX, but requested index is invalid"
-#endif
-#if defined(MSP430X_SPIB3_RX_DMA) && (MSP430X_SPI_DMA >= MSP430X_DMA_CHANNELS)
- #error "Requested DMA for SPIB3 RX, but requested index is invalid"
-#endif
-
-/* TODO figure out a way to check for conflicting DMA channels */
-
-#if MSP430X_SPIA0_CLK_SRC == MSP430X_ACLK_SRC
- #define MSP430X_SPIA0_CLK_FREQ MSP430X_ACLK_FREQ
- #define MSP430X_SPIA0_UCSSEL UCSSEL__ACLK
-#elif MSP430X_SPIA0_CLK_SRC == MSP430X_SMCLK_SRC
- #define MSP430X_SPIA0_CLK_FREQ MSP430X_SMCLK_FREQ
- #define MSP430X_SPIA0_UCSSEL UCSSEL__SMCLK
-#endif
-
-#if MSP430X_SPIA1_CLK_SRC == MSP430X_ACLK_SRC
- #define MSP430X_SPIA1_CLK_FREQ MSP430X_ACLK_FREQ
- #define MSP430X_SPIA1_UCSSEL UCSSEL__ACLK
-#elif MSP430X_SPIA1_CLK_SRC == MSP430X_SMCLK_SRC
- #define MSP430X_SPIA1_CLK_FREQ MSP430X_SMCLK_FREQ
- #define MSP430X_SPIA1_UCSSEL UCSSEL__SMCLK
-#endif
-
-#if MSP430X_SPIA2_CLK_SRC == MSP430X_ACLK_SRC
- #define MSP430X_SPIA2_CLK_FREQ MSP430X_ACLK_FREQ
- #define MSP430X_SPIA2_UCSSEL UCSSEL__ACLK
-#elif MSP430X_SPIA2_CLK_SRC == MSP430X_SMCLK_SRC
- #define MSP430X_SPIA2_CLK_FREQ MSP430X_SMCLK_FREQ
- #define MSP430X_SPIA2_UCSSEL UCSSEL__SMCLK
-#endif
-
-#if MSP430X_SPIA3_CLK_SRC == MSP430X_ACLK_SRC
- #define MSP430X_SPIA3_CLK_FREQ MSP430X_ACLK_FREQ
- #define MSP430X_SPIA3_UCSSEL UCSSEL__ACLK
-#elif MSP430X_SPIA3_CLK_SRC == MSP430X_SMCLK_SRC
- #define MSP430X_SPIA3_CLK_FREQ MSP430X_SMCLK_FREQ
- #define MSP430X_SPIA3_UCSSEL UCSSEL__SMCLK
-#endif
-
-#if MSP430X_SPIB0_CLK_SRC == MSP430X_ACLK_SRC
- #define MSP430X_SPIB0_CLK_FREQ MSP430X_ACLK_FREQ
- #define MSP430X_SPIB0_UCSSEL UCSSEL__ACLK
-#elif MSP430X_SPIB0_CLK_SRC == MSP430X_SMCLK_SRC
- #define MSP430X_SPIB0_CLK_FREQ MSP430X_SMCLK_FREQ
- #define MSP430X_SPIB0_UCSSEL UCSSEL__SMCLK
-#endif
-
-#if MSP430X_SPIB1_CLK_SRC == MSP430X_ACLK_SRC
- #define MSP430X_SPIB1_CLK_FREQ MSP430X_ACLK_FREQ
- #define MSP430X_SPIB1_UCSSEL UCSSEL__ACLK
-#elif MSP430X_SPIB1_CLK_SRC == MSP430X_SMCLK_SRC
- #define MSP430X_SPIB1_CLK_FREQ MSP430X_SMCLK_FREQ
- #define MSP430X_SPIB1_UCSSEL UCSSEL__SMCLK
-#endif
-
-#if MSP430X_SPIB2_CLK_SRC == MSP430X_ACLK_SRC
- #define MSP430X_SPIB2_CLK_FREQ MSP430X_ACLK_FREQ
- #define MSP430X_SPIB2_UCSSEL UCSSEL__ACLK
-#elif MSP430X_SPIB2_CLK_SRC == MSP430X_SMCLK_SRC
- #define MSP430X_SPIB2_CLK_FREQ MSP430X_SMCLK_FREQ
- #define MSP430X_SPIB2_UCSSEL UCSSEL__SMCLK
-#endif
-
-#if MSP430X_SPIB3_CLK_SRC == MSP430X_ACLK_SRC
- #define MSP430X_SPIB3_CLK_FREQ MSP430X_ACLK_FREQ
- #define MSP430X_SPIB3_UCSSEL UCSSEL__ACLK
-#elif MSP430X_SPIB3_CLK_SRC == MSP430X_SMCLK_SRC
- #define MSP430X_SPIB3_CLK_FREQ MSP430X_SMCLK_FREQ
- #define MSP430X_SPIB3_UCSSEL UCSSEL__SMCLK
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief SPI notification callback type.
- *
- * @param[in] spip pointer to the @p SPIDriver object triggering the
- * callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief Enumerated type for SPI bit order.
- */
-typedef enum {
- MSP430X_SPI_BO_LSB = 0,
- MSP430X_SPI_BO_MSB = 1
-} msp430x_spi_bit_order_t;
-
-/**
- * @brief Enumerated type for SPI data size.
- */
-typedef enum {
- MSP430X_SPI_DS_EIGHT = 0,
- MSP430X_SPI_DS_SEVEN = 1
-} msp430x_spi_data_size_t;
-
-/**
- * @brief Driver configuration structure.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- /**
- * @brief Operation complete callback or @p NULL.
- */
- spicallback_t end_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief The chip select line.
- * @note This may be PAL_NOLINE to indicate that hardware chip select is used.
- */
- ioline_t ss_line;
- /**
- * @brief The bit rate of the SPI interface.
- * @note Nearest available rate is used.
- */
- uint32_t bit_rate;
- /**
- * @brief The bit order of the peripheral - LSB or MSB first.
- */
- msp430x_spi_bit_order_t bit_order;
- /**
- * @brief The data size of the peripheral - 7 or 8 bits.
- */
- msp430x_spi_data_size_t data_size;
- /**
- * @brief The SPI mode to use - 0 through 3.
- */
- uint8_t spi_mode;
-#if MSP430X_SPI_EXCLUSIVE_DMA == TRUE || defined(__DOXYGEN__)
- /**
- * @brief The index of the TX DMA channel.
- * @note This may be >MSP430X_DMA_CHANNELS to indicate that exclusive DMA is not used.
- */
- uint8_t dmatx_index;
- /**
- * @brief The index of the RX DMA channel.
- * @note This may be >MSP430X_DMA_CHANNELS to indicate that exclusive DMA is not used.
- */
- uint8_t dmarx_index;
-#endif
-} SPIConfig;
-
-/**
- * @brief MSP430X SPI register structure.
- */
-typedef struct {
- uint16_t ctlw0;
- uint16_t _padding0;
- uint16_t _padding1;
- uint16_t brw;
- uint16_t statw_b;
- uint16_t statw_a;
- uint16_t rxbuf;
- uint16_t txbuf;
-} msp430x_spi_reg_t;
-
-/**
- * @brief Structure representing an SPI driver.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-struct SPIDriver {
- /**
- * @brief Driver state.
- */
- spistate_t state;
- /**
- * @brief Current configuration data.
- */
- const SPIConfig *config;
-#if (SPI_USE_WAIT == TRUE) || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- thread_reference_t thread;
-#endif /* SPI_USE_WAIT */
-#if (SPI_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the peripheral.
- */
- mutex_t mutex;
-#endif
-#if defined(SPI_DRIVER_EXT_FIELDS)
- SPI_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Configuration registers.
- */
- msp430x_spi_reg_t * regs;
- /**
- * @brief Interrupt flag register.
- */
- volatile uint16_t * ifg;
- /**
- * @brief TX DMA request.
- */
- msp430x_dma_req_t tx_req;
- /**
- * @brief RX DMA request.
- */
- msp430x_dma_req_t rx_req;
-#if MSP430X_SPI_EXCLUSIVE_DMA == TRUE || defined(__DOXYGEN__)
- /**
- * @brief TX DMA stream.
- */
- msp430x_dma_ch_t dmatx;
- /**
- * @brief RX DMA stream.
- */
- msp430x_dma_ch_t dmarx;
-#endif
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if (MSP430X_SPI_USE_SPIA0 == TRUE) && !defined(__DOXYGEN__)
-extern SPIDriver SPIDA0;
-#endif
-
-#if (MSP430X_SPI_USE_SPIA1 == TRUE) && !defined(__DOXYGEN__)
-extern SPIDriver SPIDA1;
-#endif
-
-#if (MSP430X_SPI_USE_SPIA2 == TRUE) && !defined(__DOXYGEN__)
-extern SPIDriver SPIDA2;
-#endif
-
-#if (MSP430X_SPI_USE_SPIA3 == TRUE) && !defined(__DOXYGEN__)
-extern SPIDriver SPIDA3;
-#endif
-
-#if (MSP430X_SPI_USE_SPIB0 == TRUE) && !defined(__DOXYGEN__)
-extern SPIDriver SPIDB0;
-#endif
-
-#if (MSP430X_SPI_USE_SPIB1 == TRUE) && !defined(__DOXYGEN__)
-extern SPIDriver SPIDB1;
-#endif
-
-#if (MSP430X_SPI_USE_SPIB2 == TRUE) && !defined(__DOXYGEN__)
-extern SPIDriver SPIDB2;
-#endif
-
-#if (MSP430X_SPI_USE_SPIB3 == TRUE) && !defined(__DOXYGEN__)
-extern SPIDriver SPIDB3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void spi_lld_init(void);
- void spi_lld_start(SPIDriver *spip);
- void spi_lld_stop(SPIDriver *spip);
- void spi_lld_select(SPIDriver *spip);
- void spi_lld_unselect(SPIDriver *spip);
- void spi_lld_ignore(SPIDriver *spip, size_t n);
- void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf);
- void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
- void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
- uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI == TRUE */
-
-#endif /* HAL_SPI_LLD_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_st_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_st_lld.c deleted file mode 100644 index 8ea1b9d..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_st_lld.c +++ /dev/null @@ -1,206 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file MSP430X/hal_st_lld.c
- * @brief MSP430X ST subsystem low level driver source.
- *
- * @addtogroup ST
- * @{
- */
-
-#include "hal.h"
-#include <msp430.h>
-
-#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)
- #define MSP430X_ST_DIV_CALC(x) ((MSP430X_ST_CLK_FREQ / OSAL_ST_FREQUENCY) == x)
-#endif
-
-
-#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
- #if ((MSP430X_ST_CLK_FREQ / OSAL_ST_FREQUENCY / 64) > MSP_TIMER_COUNTER_MAX)
- #error "Frequency too low for timer - please set OSAL_ST_FREQUENCY to a higher value"
- #endif
-
- #define MSP430X_ST_DIV_CALC(x) ((MSP430X_ST_CLK_FREQ / OSAL_ST_FREQUENCY / x) <= MSP_TIMER_COUNTER_MAX)
-#endif
-
-/* Find suitable prescaler setting */
-#if MSP430X_ST_DIV_CALC(1)
- #define MSP430X_ST_DIV 1
- #define MSP430X_ST_DIV_BITS ID__1
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_0
-#elif MSP430X_ST_DIV_CALC(2)
- #define MSP430X_ST_DIV 2
- #define MSP430X_ST_DIV_BITS ID__1
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_1
-#elif MSP430X_ST_DIV_CALC(3)
- #define MSP430X_ST_DIV 3
- #define MSP430X_ST_DIV_BITS ID__1
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_2
-#elif MSP430X_ST_DIV_CALC(4)
- #define MSP430X_ST_DIV 4
- #define MSP430X_ST_DIV_BITS ID__1
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_3
-#elif MSP430X_ST_DIV_CALC(5)
- #define MSP430X_ST_DIV 5
- #define MSP430X_ST_DIV_BITS ID__1
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_4
-#elif MSP430X_ST_DIV_CALC(6)
- #define MSP430X_ST_DIV 6
- #define MSP430X_ST_DIV_BITS ID__1
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_5
-#elif MSP430X_ST_DIV_CALC(7)
- #define MSP430X_ST_DIV 7
- #define MSP430X_ST_DIV_BITS ID__1
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_6
-#elif MSP430X_ST_DIV_CALC(8)
- #define MSP430X_ST_DIV 8
- #define MSP430X_ST_DIV_BITS ID__1
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_7
-#elif MSP430X_ST_DIV_CALC(10)
- #define MSP430X_ST_DIV 10
- #define MSP430X_ST_DIV_BITS ID__2
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_4
-#elif MSP430X_ST_DIV_CALC(12)
- #define MSP430X_ST_DIV 12
- #define MSP430X_ST_DIV_BITS ID__2
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_5
-#elif MSP430X_ST_DIV_CALC(14)
- #define MSP430X_ST_DIV 14
- #define MSP430X_ST_DIV_BITS ID__2
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_6
-#elif MSP430X_ST_DIV_CALC(16)
- #define MSP430X_ST_DIV 16
- #define MSP430X_ST_DIV_BITS ID__2
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_7
-#elif MSP430X_ST_DIV_CALC(20)
- #define MSP430X_ST_DIV 20
- #define MSP430X_ST_DIV_BITS ID__4
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_4
-#elif MSP430X_ST_DIV_CALC(24)
- #define MSP430X_ST_DIV 24
- #define MSP430X_ST_DIV_BITS ID__4
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_5
-#elif MSP430X_ST_DIV_CALC(28)
- #define MSP430X_ST_DIV 28
- #define MSP430X_ST_DIV_BITS ID__4
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_6
-#elif MSP430X_ST_DIV_CALC(32)
- #define MSP430X_ST_DIV 32
- #define MSP430X_ST_DIV_BITS ID__4
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_7
-#elif MSP430X_ST_DIV_CALC(40)
- #define MSP430X_ST_DIV 40
- #define MSP430X_ST_DIV_BITS ID__8
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_4
-#elif MSP430X_ST_DIV_CALC(48)
- #define MSP430X_ST_DIV 48
- #define MSP430X_ST_DIV_BITS ID__8
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_5
-#elif MSP430X_ST_DIV_CALC(56)
- #define MSP430X_ST_DIV 56
- #define MSP430X_ST_DIV_BITS ID__8
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_6
-#elif MSP430X_ST_DIV_CALC(64)
- #define MSP430X_ST_DIV 64
- #define MSP430X_ST_DIV_BITS ID__8
- #define MSP430X_ST_DIV_EX_BITS TAIDEX_7
-#else
- #error "Error in calculating dividers - check OSAL_ST_FREQUENCY and frequency of input clock"
-#endif
-/* ugh never again*/
-
-#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
- #define MSP_TIMER_COUNTER (MSP430X_ST_CLK_FREQ / OSAL_ST_FREQUENCY / MSP430X_ST_DIV)
- #define MSP430X_ST_CLK_FREQ_ (MSP_TIMER_COUNTER * MSP430X_ST_DIV * OSAL_ST_FREQUENCY)
- #if (MSP430X_ST_CLK_FREQ != MSP430X_ST_CLK_FREQ_)
- #warning "OSAL_ST_FREQUENCY cannot be generated exactly using timer"
- #endif
- #undef MSP430X_ST_CLK_FREQ_
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/**
- * @brief Timer handler for both modes
- */
-
-PORT_IRQ_HANDLER( MSP430X_ST_ISR ) {
-
- OSAL_IRQ_PROLOGUE();
-
- osalSysLockFromISR();
- osalOsTimerHandlerI();
- osalSysUnlockFromISR();
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ST driver initialization.
- *
- * @notapi
- */
-void st_lld_init(void) {
- #if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined (__DOXYGEN__)
- /* Start disabled */
- MSP430X_ST_CCR(MSP430X_ST_TIMER) = 0;
- MSP430X_ST_CCTL(MSP430X_ST_TIMER) = 0;
- MSP430X_ST_EX(MSP430X_ST_TIMER) = MSP430X_ST_DIV_EX_BITS;
- MSP430X_ST_CTL(MSP430X_ST_TIMER) = (TACLR | MC_2 | MSP430X_ST_DIV_BITS | MSP430X_ST_TASSEL);
- #endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
-
- #if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined (__DOXYGEN__)
- /* Start enabled */
- MSP430X_ST_CCR(MSP430X_ST_TIMER) = MSP_TIMER_COUNTER - 1;
- MSP430X_ST_CCTL(MSP430X_ST_TIMER) = CCIE;
- MSP430X_ST_EX(MSP430X_ST_TIMER) = MSP430X_ST_DIV_EX_BITS;
- MSP430X_ST_CTL(MSP430X_ST_TIMER) = (TACLR | MC_1 | MSP430X_ST_DIV_BITS | MSP430X_ST_TASSEL);
- #endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
-}
-
-#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_st_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_st_lld.h deleted file mode 100644 index 32ad970..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/hal_st_lld.h +++ /dev/null @@ -1,216 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file MSP430X/hal_st_lld.h
- * @brief MSP430X ST subsystem low level driver header.
- * @details This header is designed to be include-able without having to
- * include other files from the HAL.
- *
- * @addtogroup MSP430X
- * @{
- */
-
-#ifndef _ST_LLD_H_
-#define _ST_LLD_H_
-
-#include <msp430.h>
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Timer maximum value
- */
-#define MSP_TIMER_COUNTER_MAX 65535
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief System timer clock source.
- *
- * @note Legal values are undefined, MSP430X_ACLK_SRC, and
- * MSP430X_SMCLK_SRC.
- * @note If undefined, must define MSP430X_ST_CLK_FREQ as frequency of
- * external clock and configure PAL appropriately.
- */
-#if !defined (MSP430X_ST_CLK_SRC)
- #ifndef MSP430X_ST_CLK_FREQ
- #warning "Requested external source for ST but no frequency given"
- #warning "- assuming OSAL_ST_FREQUENCY"
- #define MSP430X_ST_CLK_FREQ OSAL_ST_FREQUENCY
- #endif
- #define MSP430X_ST_TASSEL TASSEL__TACLK
-#elif MSP430X_ST_CLK_SRC == MSP430X_ACLK_SRC
- #define MSP430X_ST_CLK_FREQ MSP430X_ACLK_FREQ
- #define MSP430X_ST_TASSEL TASSEL__ACLK
-#elif MSP430X_ST_CLK_SRC == MSP430X_SMCLK_SRC
- #define MSP430X_ST_CLK_FREQ MSP430X_SMCLK_FREQ
- #define MSP430X_ST_TASSEL TASSEL__SMCLK
-#endif
-
-/* Timers */
-/**
- * @brief Timer type (by letter) to be used for ST.
- * @note Legal values are A and B. D support not yet implemented.
- * @note Defaults to A
- */
-#if !defined(MSP430X_ST_TIMER_TYPE)
- #define MSP430X_ST_TIMER_TYPE A
-#endif
-/**
- * @brief Timer instance (by number) to be used for ST.
- * @note Defaults to 0
- */
-#if !defined (MSP430X_ST_TIMER_INDEX)
- #define MSP430X_ST_TIMER_INDEX 0
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#define TIMER_HELPER2(x, y) x ## y
-#define TIMER_HELPER(x, y) TIMER_HELPER2(x, y)
-#define MSP430X_ST_TIMER TIMER_HELPER(MSP430X_ST_TIMER_TYPE, MSP430X_ST_TIMER_INDEX)
-#define CCR_HELPER(x) T ## x ## CCR0
-#define MSP430X_ST_CCR(x) CCR_HELPER(x)
-#define CCTL_HELPER(x) T ## x ## CCTL0
-#define MSP430X_ST_CCTL(x) CCTL_HELPER(x)
-#define EX_HELPER(x) T ## x ## EX0
-#define MSP430X_ST_EX(x) EX_HELPER(x)
-#define CTL_HELPER(x) T ## x ## CTL
-#define MSP430X_ST_CTL(x) CTL_HELPER(x)
-#define R_HELPER(x) T ## x ## R
-#define MSP430X_ST_R(x) R_HELPER(x)
-#define ISR_HELPER2(x, y) TIMER ## y ## _ ## x ## 0_VECTOR
-#define ISR_HELPER(x, y) ISR_HELPER2(x, y)
-#define MSP430X_ST_ISR ISR_HELPER(MSP430X_ST_TIMER_TYPE, MSP430X_ST_TIMER_INDEX)
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void st_lld_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-/*===========================================================================*/
-/* Driver inline functions. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the time counter value.
- *
- * @return The counter value.
- *
- * @notapi
- */
-static inline systime_t st_lld_get_counter(void) {
-
- return (systime_t)MSP430X_ST_R(MSP430X_ST_TIMER);
-}
-
-/**
- * @brief Starts the alarm.
- * @note Makes sure that no spurious alarms are triggered after
- * this call.
- *
- * @param[in] abstime the time to be set for the first alarm
- *
- * @notapi
- */
-static inline void st_lld_start_alarm(systime_t abstime) {
-
- MSP430X_ST_CCR(MSP430X_ST_TIMER) = abstime;
-
- /* Reset pending interrupt */
- MSP430X_ST_CCTL(MSP430X_ST_TIMER) &= (~CCIFG);
-
- /* Enable interrupt */
- MSP430X_ST_CCTL(MSP430X_ST_TIMER) |= CCIE;
-}
-
-/**
- * @brief Stops the alarm interrupt.
- *
- * @notapi
- */
-static inline void st_lld_stop_alarm(void) {
-
- MSP430X_ST_CCTL(MSP430X_ST_TIMER) &= (~CCIE);
-}
-
-/**
- * @brief Sets the alarm time.
- *
- * @param[in] abstime the time to be set for the next alarm
- *
- * @notapi
- */
-static inline void st_lld_set_alarm(systime_t abstime) {
-
- MSP430X_ST_CCR(MSP430X_ST_TIMER) = abstime;
-}
-
-/**
- * @brief Returns the current alarm time.
- *
- * @return The currently set alarm time.
- *
- * @notapi
- */
-static inline systime_t st_lld_get_alarm(void) {
-
- return MSP430X_ST_CCR(MSP430X_ST_TIMER);
-}
-
-/**
- * @brief Determines if the alarm is active.
- *
- * @return The alarm status.
- * @retval false if the alarm is not active.
- * @retval true is the alarm is active
- *
- * @notapi
- */
-static inline bool st_lld_is_alarm_active(void) {
-
- return (bool)((MSP430X_ST_CCTL(MSP430X_ST_TIMER) & CCIE) != 0);
-}
-
-#endif /* _ST_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/platform.mk b/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/platform.mk deleted file mode 100644 index 832814b..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/MSP430X/platform.mk +++ /dev/null @@ -1,10 +0,0 @@ -# List of all the MSP430X platform files.
-PLATFORMSRC = ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_st_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_serial_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_pal_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_dma_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_spi_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_adc_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_adc_lld.c deleted file mode 100644 index 7f3413c..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_adc_lld.c +++ /dev/null @@ -1,227 +0,0 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51Fx22/adc_lld.c
- * @brief NRF51Fx22 ADC subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-#define ADC_CHANNEL_MASK 0x7
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief ADC1 driver identifier.*/
-#if NRF51_ADC_USE_ADC1 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-static void adc_lld_config_next_channel(ADCDriver *adcp, uint32_t config) {
-
- /* Default to all analog input pins disabled */
- config &= ~ADC_CONFIG_PSEL_Msk;
-
- if (adcp->grpp->channel_mask) {
- /* Skip to the next channel */
- while (((1 << adcp->current_channel) & adcp->grpp->channel_mask) == 0)
- adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK;
- config |= (((1 << adcp->current_channel) << ADC_CONFIG_PSEL_Pos) & ADC_CONFIG_PSEL_Msk);
- }
-
- /* Setup analog input pin select and user config values */
- adcp->adc->CONFIG = config;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if NRF51_ADC_USE_ADC1 || defined(__DOXYGEN__)
-/**
- * @brief ADC interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector5C) {
-
- ADCDriver *adcp = &ADCD1;
- NRF_ADC_Type *adc = adcp->adc;
- bool more = true;
-
- OSAL_IRQ_PROLOGUE();
-
- /* Clear the ADC event */
- adc->EVENTS_END = 0;
-
- /* Read the sample into the buffer */
- adcp->samples[adcp->current_index++] = adc->RESULT;
-
- /* At the end of the buffer then we may be finished */
- if (adcp->current_index == adcp->number_of_samples) {
- _adc_isr_full_code(adcp);
-
- adcp->current_index = 0;
-
- /* We are never finished in circular mode */
- more = adcp->grpp->circular;
- }
-
- if (more) {
-
- /* Signal half completion in circular mode. */
- if (adcp->grpp->circular &&
- (adcp->current_index == (adcp->number_of_samples / 2))) {
-
- _adc_isr_half_code(adcp);
- }
-
- /* Skip to the next channel */
- adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK;
- adc_lld_config_next_channel(adcp, adcp->adc->CONFIG);
- adcp->adc->TASKS_START = 1;
- } else {
- adc_lld_stop_conversion(adcp);
- }
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-#if NRF51_ADC_USE_ADC1
- /* Driver initialization.*/
- adcObjectInit(&ADCD1);
- ADCD1.adc = NRF_ADC;
-#endif
-}
-
-/**
- * @brief Configures and activates the ADC peripheral.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
- /* If in stopped state then configures and enables the ADC. */
- if (adcp->state == ADC_STOP) {
-#if NRF51_ADC_USE_ADC1
- if (&ADCD1 == adcp) {
-
- adcp->adc->INTENSET = ADC_INTENSET_END_Enabled << ADC_INTENSET_END_Pos;
- nvicEnableVector(ADC_IRQn, NRF51_ADC_IRQ_PRIORITY);
- }
-#endif /* NRF51_ADC_USE_ADC1 */
- }
-}
-
-/**
- * @brief Deactivates the ADC peripheral.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
- /* If in ready state then disables the ADC clock and analog part.*/
- if (adcp->state == ADC_READY) {
-
-#if NRF51_ADC_USE_ADC1
- if (&ADCD1 == adcp) {
-
- nvicDisableVector(ADC_IRQn);
- adcp->adc->INTENCLR = ADC_INTENCLR_END_Clear << ADC_INTENCLR_END_Pos;
- adc_lld_stop_conversion(adcp);
- }
-#endif
- }
-}
-
-/**
- * @brief Starts an ADC conversion.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
-
- NRF_ADC_Type *adc = adcp->adc;
-
- adcp->number_of_samples = adcp->depth * adcp->grpp->num_channels;
- adcp->current_index = 0;
-
- /* At least one sample must be configured */
- osalDbgAssert(adcp->number_of_samples, "must configure at least one sample");
-
- /* Skip to the next channel */
- adcp->current_channel = 0;
- adc_lld_config_next_channel(adcp, adcp->grpp->cfg);
-
- /* Enable and start the conversion */
- adc->ENABLE = ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos;
- adc->TASKS_START = 1;
-}
-
-/**
- * @brief Stops an ongoing conversion.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
- NRF_ADC_Type *adc = adcp->adc;
-
- adc->TASKS_STOP = 1;
- adc->ENABLE = ADC_ENABLE_ENABLE_Disabled << ADC_ENABLE_ENABLE_Pos;
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_adc_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_adc_lld.h deleted file mode 100644 index 36854fb..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_adc_lld.h +++ /dev/null @@ -1,229 +0,0 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51x22/adc_lld.h
- * @brief NRF51x22 ADC subsystem low level driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef HAL_ADC_LLD_H
-#define HAL_ADC_LLD_H
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(NRF51_ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define NRF51_ADC_USE_ADC1 FALSE
-#endif
-
-/**
- * @brief ADC interrupt priority level setting.
- */
-#if !defined(NRF51_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_ADC_IRQ_PRIORITY 2
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !NRF51_ADC_USE_ADC1
-#error "ADC driver activated but no ADC peripheral assigned"
-#endif
-
-#if NRF51_ADC_USE_ADC1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_ADC_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC1"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief ADC sample data type.
- */
-typedef uint16_t adcsample_t;
-
-/**
- * @brief Channels number in a conversion group.
- */
-typedef uint8_t adc_channels_num_t;
-
-/**
- * @brief Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief ADC notification callback type.
- *
- * @param[in] adcp pointer to the @p ADCDriver object triggering the
- * callback
- * @param[in] buffer pointer to the most recent samples data
- * @param[in] n number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- * operation.
- * @note The use of this configuration structure requires knowledge of
- * STM32 ADC cell registers interface, please refer to the STM32
- * reference manual for details.
- */
-typedef struct {
- /**
- * @brief Enables the circular buffer mode for the group.
- */
- bool circular;
- /**
- * @brief Number of the analog channels belonging to the conversion group.
- */
- adc_channels_num_t num_channels;
- /**
- * @brief Callback function associated to the group or @p NULL.
- */
- adccallback_t end_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief Bitmask of channels for ADC conversion.
- */
- uint32_t channel_mask;
- /**
- * @brief ADC CONFIG register details.
- * @note All the required bits must be defined into this field.
- */
- uint32_t cfg;
-} ADCConversionGroup;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- uint32_t dummy;
-} ADCConfig;
-
-/**
- * @brief Structure representing an ADC driver.
- */
-struct ADCDriver {
- /**
- * @brief Driver state.
- */
- adcstate_t state;
- /**
- * @brief Current configuration data.
- */
- const ADCConfig *config;
- /**
- * @brief Current samples buffer pointer or @p NULL.
- */
- adcsample_t *samples;
- /**
- * @brief Current samples buffer depth or @p 0.
- */
- size_t depth;
- /**
- * @brief Current conversion group pointer or @p NULL.
- */
- const ADCConversionGroup *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- thread_reference_t thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the peripheral.
- */
- mutex_t mutex;
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
- ADC_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the ADCx registers block.
- */
- NRF_ADC_Type *adc;
- /**
- * @brief Number of samples expected.
- */
- size_t number_of_samples;
- /**
- * @brief Current position in the buffer.
- */
- size_t current_index;
- /**
- * @brief Current channel index into group channel_mask.
- */
- size_t current_channel;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if NRF51_ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void adc_lld_init(void);
- void adc_lld_start(ADCDriver *adcp);
- void adc_lld_stop(ADCDriver *adcp);
- void adc_lld_start_conversion(ADCDriver *adcp);
- void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* HAL_ADC_LLD_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_ext_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_ext_lld.c deleted file mode 100644 index 47736c7..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_ext_lld.c +++ /dev/null @@ -1,168 +0,0 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51822/ext_lld.c
- * @brief NRF51822 EXT subsystem low level driver source.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "hal_ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief EXTD1 driver identifier.
- */
-EXTDriver EXTD1;
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level EXT driver initialization.
- *
- * @notapi
- */
-void ext_lld_init(void) {
-
- /* Driver initialization.*/
- extObjectInit(&EXTD1);
-}
-
-/**
- * @brief Configures and activates the EXT peripheral.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_start(EXTDriver *extp) {
-
- unsigned i;
-
- ext_lld_exti_irq_enable();
-
- /* Configuration of automatic channels.*/
- for (i = 0; i < EXT_MAX_CHANNELS; i++) {
- uint32_t config = 0;
- uint32_t pad = (extp->config->channels[i].mode & EXT_MODE_GPIO_MASK)
- >> EXT_MODE_GPIO_OFFSET;
-
- if (extp->config->channels[i].mode & EXT_CH_MODE_BOTH_EDGES)
- config |= (GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
- else if (extp->config->channels[i].mode & EXT_CH_MODE_RISING_EDGE)
- config |= (GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos);
- else
- config |= (GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos);
-
- config |= (pad << GPIOTE_CONFIG_PSEL_Pos);
-
- NRF_GPIOTE->CONFIG[i] = config;
- NRF_GPIOTE->EVENTS_PORT = 0;
- NRF_GPIOTE->EVENTS_IN[i] = 0;
-
- if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART)
- ext_lld_channel_enable(extp, i);
- else
- ext_lld_channel_disable(extp, i);
- }
-}
-
-/**
- * @brief Deactivates the EXT peripheral.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_stop(EXTDriver *extp) {
-
- unsigned i;
-
- (void)extp;
- ext_lld_exti_irq_disable();
-
- for (i = 0; i < EXT_MAX_CHANNELS; i++)
- NRF_GPIOTE->CONFIG[i] = 0;
-
- NRF_GPIOTE->INTENCLR =
- (GPIOTE_INTENCLR_IN3_Msk | GPIOTE_INTENCLR_IN2_Msk |
- GPIOTE_INTENCLR_IN1_Msk | GPIOTE_INTENCLR_IN0_Msk);
-}
-
-/**
- * @brief Enables an EXT channel.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- * @param[in] channel channel to be enabled
- *
- * @notapi
- */
-void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
-
- uint32_t config = NRF_GPIOTE->CONFIG[channel] & ~GPIOTE_CONFIG_MODE_Msk;
-
- (void)extp;
- config |= (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos);
-
- NRF_GPIOTE->CONFIG[channel] = config;
- NRF_GPIOTE->INTENSET = (1 << channel);
-}
-
-/**
- * @brief Disables an EXT channel.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- * @param[in] channel channel to be disabled
- *
- * @notapi
- */
-void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
-
- (void)extp;
- NRF_GPIOTE->CONFIG[channel] &= ~GPIOTE_CONFIG_MODE_Msk;
- NRF_GPIOTE->INTENCLR = (1 << channel);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_ext_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_ext_lld.h deleted file mode 100644 index 37ae721..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_ext_lld.h +++ /dev/null @@ -1,139 +0,0 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51822/ext_lld.h
- * @brief NRF51822 GPIOTE subsystem low level driver header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef HAL_EXT_LLD_H
-#define HAL_EXT_LLD_H
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Available number of EXT channels.
- */
-#define EXT_MAX_CHANNELS 4
-#define EXT_MODE_GPIO_MASK 0xF8 /**< @brief Pad field mask. */
-#define EXT_MODE_GPIO_OFFSET 3 /**< @brief Pad field offset. */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief EXT channel identifier.
- */
-typedef uint32_t expchannel_t;
-
-/**
- * @brief Type of an EXT generic notification callback.
- *
- * @param[in] extp pointer to the @p EXPDriver object triggering the
- * callback
- */
-typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
-
-/**
- * @brief Channel configuration structure.
- */
-typedef struct {
- /**
- * @brief Channel mode.
- */
- uint32_t mode;
- /**
- * @brief Channel callback.
- * @details In the STM32 implementation a @p NULL callback pointer is
- * valid and configures the channel as an event sources instead
- * of an interrupt source.
- */
- extcallback_t cb;
-} EXTChannelConfig;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief Channel configurations.
- */
- EXTChannelConfig channels[EXT_MAX_CHANNELS];
- /* End of the mandatory fields.*/
-} EXTConfig;
-
-/**
- * @brief Structure representing an EXT driver.
- */
-struct EXTDriver {
- /**
- * @brief Driver state.
- */
- extstate_t state;
- /**
- * @brief Current configuration data.
- */
- const EXTConfig *config;
- /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern EXTDriver EXTD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void ext_lld_init(void);
- void ext_lld_start(EXTDriver *extp);
- void ext_lld_stop(EXTDriver *extp);
- void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
- void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* HAL_EXT_LLD_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.c b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.c deleted file mode 100644 index 52f07d6..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.c +++ /dev/null @@ -1,110 +0,0 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51x22/ext_lld_isr.h
- * @brief NRF51x22 EXT subsystem low level driver ISR code.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "hal_ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/**
- * @brief EXTI[0]...EXTI[1] interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector58) {
-
- OSAL_IRQ_PROLOGUE();
-
- if (NRF_GPIOTE->EVENTS_IN[0])
- {
- NRF_GPIOTE->EVENTS_IN[0] = 0;
- EXTD1.config->channels[0].cb(&EXTD1, 0);
- }
- if (NRF_GPIOTE->EVENTS_IN[1])
- {
- NRF_GPIOTE->EVENTS_IN[1] = 0;
- EXTD1.config->channels[1].cb(&EXTD1, 1);
- }
- if (NRF_GPIOTE->EVENTS_IN[2])
- {
- NRF_GPIOTE->EVENTS_IN[2] = 0;
- EXTD1.config->channels[2].cb(&EXTD1, 2);
- }
- if (NRF_GPIOTE->EVENTS_IN[3])
- {
- NRF_GPIOTE->EVENTS_IN[3] = 0;
- EXTD1.config->channels[3].cb(&EXTD1, 3);
- }
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Enables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_enable(void) {
-
- nvicEnableVector(GPIOTE_IRQn, NRF51_EXT_GPIOTE_IRQ_PRIORITY);
-}
-
-/**
- * @brief Disables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_disable(void) {
-
- nvicDisableVector(GPIOTE_IRQn);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.h deleted file mode 100644 index 736e55c..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.h +++ /dev/null @@ -1,79 +0,0 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51x22/ext_lld_isr.h
- * @brief NRF51x22 EXT subsystem low level driver ISR header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef HAL_EXT_LLD_ISR_H
-#define HAL_EXT_LLD_ISR_H
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief GPIOTE interrupt priority level setting.
- */
-#if !defined(NRF51_EXT_GPIOTE_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_EXT_GPIOTE_IRQ_PRIORITY 3
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void ext_lld_exti_irq_enable(void);
- void ext_lld_exti_irq_disable(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* HAL_EXT_LLD_ISR_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.c deleted file mode 100644 index f39470f..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.c +++ /dev/null @@ -1,358 +0,0 @@ -/*
- ChibiOS - 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51x22/gpt_lld.c
- * @brief NRF51x22 GPT subsystem low level driver source.
- *
- * @addtogroup GPT
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#define NRF51_TIMER_PRESCALER_NUM 10
-#define NRF51_TIMER_COMPARE_NUM 4
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief GPTD1 driver identifier.
- * @note The driver GPTD1 allocates the complex timer TIM1 when enabled.
- */
-#if NRF51_GPT_USE_TIMER0 || defined(__DOXYGEN__)
-GPTDriver GPTD1;
-#endif
-
-/**
- * @brief GPTD2 driver identifier.
- * @note The driver GPTD2 allocates the timer TIM2 when enabled.
- */
-#if NRF51_GPT_USE_TIMER1 || defined(__DOXYGEN__)
-GPTDriver GPTD2;
-#endif
-
-/**
- * @brief GPTD3 driver identifier.
- * @note The driver GPTD3 allocates the timer TIM3 when enabled.
- */
-#if NRF51_GPT_USE_TIMER2 || defined(__DOXYGEN__)
-GPTDriver GPTD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-static uint8_t prescaler(uint16_t freq)
-{
- uint8_t i;
- static const gptfreq_t frequencies[] = {
- NRF51_GPT_FREQ_16MHZ,
- NRF51_GPT_FREQ_8MHZ,
- NRF51_GPT_FREQ_4MHZ,
- NRF51_GPT_FREQ_2MHZ,
- NRF51_GPT_FREQ_1MHZ,
- NRF51_GPT_FREQ_500KHZ,
- NRF51_GPT_FREQ_250KHZ,
- NRF51_GPT_FREQ_125KHZ,
- NRF51_GPT_FREQ_62500HZ,
- NRF51_GPT_FREQ_31250HZ,
- };
-
- for (i = 0; i < NRF51_TIMER_PRESCALER_NUM; i++)
- if (freq == frequencies[i])
- return i;
-
- osalDbgAssert(FALSE, "invalid timer frequency");
-
- return 0;
-}
-
-/**
- * @brief Shared IRQ handler.
- *
- * @param[in] gptp pointer to a @p GPTDriver object
- */
-static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
-
- gptp->tim->EVENTS_COMPARE[gptp->cc_int] = 0;
- if (gptp->state == GPT_ONESHOT)
- gptp->state = GPT_READY; /* Back in GPT_READY state. */
- gptp->config->callback(gptp);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if NRF51_GPT_USE_TIMER0
-/**
- * @brief TIMER0 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector60) {
-
- OSAL_IRQ_PROLOGUE();
-
- gpt_lld_serve_interrupt(&GPTD1);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* NRF51_GPT_USE_TIMER0 */
-
-#if NRF51_GPT_USE_TIMER1
-/**
- * @brief TIMER1 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector64) {
-
- OSAL_IRQ_PROLOGUE();
-
- gpt_lld_serve_interrupt(&GPTD2);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* NRF51_GPT_USE_TIMER1 */
-
-#if NRF51_GPT_USE_TIMER2
-/**
- * @brief TIMER2 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector68) {
-
- OSAL_IRQ_PROLOGUE();
-
- gpt_lld_serve_interrupt(&GPTD3);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* NRF51_GPT_USE_TIMER2 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level GPT driver initialization.
- *
- * @notapi
- */
-void gpt_lld_init(void) {
-
-#if NRF51_GPT_USE_TIMER0
- /* Driver initialization.*/
- GPTD1.tim = NRF_TIMER0;
- gptObjectInit(&GPTD1);
-#endif
-
-#if NRF51_GPT_USE_TIMER1
- /* Driver initialization.*/
- GPTD2.tim = NRF_TIMER1;
- gptObjectInit(&GPTD2);
-#endif
-
-#if NRF51_GPT_USE_TIMER2
- /* Driver initialization.*/
- GPTD3.tim = NRF_TIMER2;
- gptObjectInit(&GPTD3);
-#endif
-}
-
-/**
- * @brief Configures and activates the GPT peripheral.
- *
- * @param[in] gptp pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_start(GPTDriver *gptp) {
-
- NRF_TIMER_Type *tim = gptp->tim;
-
- if (gptp->state == GPT_STOP) {
- osalDbgAssert(gptp->cc_int < NRF51_TIMER_COMPARE_NUM,
- "invalid capture/compare index");
-
- tim->INTENSET = TIMER_INTENSET_COMPARE0_Msk << gptp->cc_int;
-#if NRF51_GPT_USE_TIMER0
- if (&GPTD1 == gptp)
- nvicEnableVector(TIMER0_IRQn, NRF51_GPT_TIMER0_IRQ_PRIORITY);
-#endif
-#if NRF51_GPT_USE_TIMER1
- if (&GPTD2 == gptp)
- nvicEnableVector(TIMER1_IRQn, NRF51_GPT_TIMER1_IRQ_PRIORITY);
-#endif
-#if NRF51_GPT_USE_TIMER2
- if (&GPTD3 == gptp)
- nvicEnableVector(TIMER2_IRQn, NRF51_GPT_TIMER2_IRQ_PRIORITY);
-#endif
- }
-
- /* Prescaler value calculation.*/
- tim->PRESCALER = prescaler(gptp->config->frequency);
-
- /* Timer configuration.*/
- tim->MODE = TIMER_MODE_MODE_Timer << TIMER_MODE_MODE_Pos;
-
- switch (gptp->config->resolution) {
-
- case 8:
- tim->BITMODE = TIMER_BITMODE_BITMODE_08Bit << TIMER_BITMODE_BITMODE_Pos;
- break;
-
- case 16:
- tim->BITMODE = TIMER_BITMODE_BITMODE_16Bit << TIMER_BITMODE_BITMODE_Pos;
- break;
-
-#if NRF51_GPT_USE_TIMER0
- case 24:
- tim->BITMODE = TIMER_BITMODE_BITMODE_24Bit << TIMER_BITMODE_BITMODE_Pos;
- break;
-
- case 32:
- tim->BITMODE = TIMER_BITMODE_BITMODE_32Bit << TIMER_BITMODE_BITMODE_Pos;
- break;
-#endif
-
- default:
- osalDbgAssert(FALSE, "invalid timer resolution");
- break;
- };
-}
-
-/**
- * @brief Deactivates the GPT peripheral.
- *
- * @param[in] gptp pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop(GPTDriver *gptp) {
-
- if (gptp->state == GPT_READY) {
- gptp->tim->TASKS_SHUTDOWN = 1;
-
-#if NRF51_GPT_USE_TIMER0
- if (&GPTD1 == gptp)
- nvicDisableVector(TIMER0_IRQn);
-#endif
-#if NRF51_GPT_USE_TIMER1
- if (&GPTD2 == gptp)
- nvicDisableVector(TIMER1_IRQn);
-#endif
-#if NRF51_GPT_USE_TIMER2
- if (&GPTD3 == gptp)
- nvicDisableVector(TIMER2_IRQn);
-#endif
- gptp->tim->INTENCLR = TIMER_INTENSET_COMPARE0_Msk << gptp->cc_int;
- }
-}
-
-/**
- * @brief Starts the timer in continuous mode.
- *
- * @param[in] gptp pointer to the @p GPTDriver object
- * @param[in] interval period in ticks
- *
- * @notapi
- */
-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
-
- NRF_TIMER_Type *tim = gptp->tim;
-
- tim->TASKS_CLEAR = 1;
- tim->CC[gptp->cc_int] = (uint32_t)(interval - 1); /* Time constant. */
- if (gptp->state == GPT_ONESHOT)
- gptp->tim->SHORTS = TIMER_SHORTS_COMPARE0_STOP_Msk << gptp->cc_int;
- else if (gptp->state == GPT_CONTINUOUS)
- gptp->tim->SHORTS = TIMER_SHORTS_COMPARE0_CLEAR_Msk << gptp->cc_int;
- tim->TASKS_START = 1;
-}
-
-/**
- * @brief Stops the timer.
- *
- * @param[in] gptp pointer to the @p GPTDriver object
- *
- * @notapi
- */
-void gpt_lld_stop_timer(GPTDriver *gptp) {
-
- gptp->tim->TASKS_STOP = 1;
-}
-
-/**
- * @brief Starts the timer in one shot mode and waits for completion.
- * @details This function specifically polls the timer waiting for completion
- * in order to not have extra delays caused by interrupt servicing,
- * this function is only recommended for short delays.
- *
- * @param[in] gptp pointer to the @p GPTDriver object
- * @param[in] interval time interval in ticks
- *
- * @notapi
- */
-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
-
- NRF_TIMER_Type *tim = gptp->tim;
-
- tim->INTENCLR = (1UL << gptp->cc_int) << TIMER_INTENSET_COMPARE0_Pos;
- tim->TASKS_CLEAR = 1;
- tim->CC[gptp->cc_int] = (uint32_t)(interval - 1); /* Time constant. */
- tim->TASKS_START = 1;
- while (!(tim->INTENSET & (TIMER_INTENSET_COMPARE0_Msk << gptp->cc_int)))
- ;
- tim->INTENSET = TIMER_INTENSET_COMPARE0_Msk << gptp->cc_int;
-}
-
-/**
- * @brief Returns the counter value of GPT peripheral.
- * @pre The GPT unit must be running in continuous mode.
- * @note The nature of the counter is not defined, it may count upward
- * or downward, it could be continuously running or not.
- *
- * @param[in] gptp pointer to a @p GPTDriver object
- * @return The current counter value.
- *
- * @notapi
- */
-gptcnt_t gpt_lld_get_counter(GPTDriver *gptp) {
-
- gptp->tim->TASKS_CAPTURE[gptp->cc_get] = 1;
- return gptp->tim->CC[gptp->cc_get];
-}
-
-#endif /* HAL_USE_GPT */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.h deleted file mode 100644 index 9b4cc9b..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.h +++ /dev/null @@ -1,264 +0,0 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51x22/gpt_lld.h
- * @brief NRF51x22 GPT subsystem low level driver header.
- *
- * @addtogroup GPT
- * @{
- */
-
-#ifndef HAL_GPT_LLD_H
-#define HAL_GPT_LLD_H
-
-#if HAL_USE_GPT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief GPTD1 driver enable switch.
- * @details If set to @p TRUE the support for GPTD1 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(NRF51_GPT_USE_TIMER0) || defined(__DOXYGEN__)
-#define NRF51_GPT_USE_TIMER0 FALSE
-#endif
-
-/**
- * @brief GPTD2 driver enable switch.
- * @details If set to @p TRUE the support for GPTD2 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(NRF51_GPT_USE_TIMER1) || defined(__DOXYGEN__)
-#define NRF51_GPT_USE_TIMER1 FALSE
-#endif
-
-/**
- * @brief GPTD3 driver enable switch.
- * @details If set to @p TRUE the support for GPTD3 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(NRF51_GPT_USE_TIMER2) || defined(__DOXYGEN__)
-#define NRF51_GPT_USE_TIMER2 FALSE
-#endif
-
-/**
- * @brief GPTD1 interrupt priority level setting.
- */
-#if !defined(NRF51_GPT_TIMER0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_GPT_TIMER0_IRQ_PRIORITY 3
-#endif
-
-/**
- * @brief GPTD2 interrupt priority level setting.
- */
-#if !defined(NRF51_GPT_TIMER1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_GPT_TIMER1_IRQ_PRIORITY 3
-#endif
-
-/**
- * @brief GPTD3 interrupt priority level setting.
- */
-#if !defined(NRF51_GPT_TIMER2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_GPT_TIMER2_IRQ_PRIORITY 3
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !NRF51_GPT_USE_TIMER0 && !NRF51_GPT_USE_TIMER1 && \
- !NRF51_GPT_USE_TIMER2
-#error "GPT driver activated but no TIMER peripheral assigned"
-#endif
-
-#if NRF51_GPT_USE_TIMER0 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIMER0"
-#endif
-
-#if NRF51_GPT_USE_TIMER1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIMER1"
-#endif
-
-#if NRF51_GPT_USE_TIMER2 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIMER2"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief GPT frequency type.
- */
-typedef enum {
- NRF51_GPT_FREQ_31250HZ = 31250,
- NRF51_GPT_FREQ_62500HZ = 62500,
- NRF51_GPT_FREQ_125KHZ = 125000,
- NRF51_GPT_FREQ_250KHZ = 250000,
- NRF51_GPT_FREQ_500KHZ = 500000,
- NRF51_GPT_FREQ_1MHZ = 1000000,
- NRF51_GPT_FREQ_2MHZ = 2000000,
- NRF51_GPT_FREQ_4MHZ = 4000000,
- NRF51_GPT_FREQ_8MHZ = 8000000,
- NRF51_GPT_FREQ_16MHZ = 16000000,
-} gptfreq_t;
-
-/**
- * @brief GPT counter type.
- */
-typedef uint32_t gptcnt_t;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- gptfreq_t frequency;
- /**
- * @brief Timer callback pointer.
- * @note This callback is invoked on GPT counter events.
- * @note This callback can be set to @p NULL but in that case the
- * one-shot mode cannot be used.
- */
- gptcallback_t callback;
- /* End of the mandatory fields.*/
- /**
- * @brief The timer resolution in bits (8/16/24/32)
- * @note The default value of this field is 16 bits
- * @note The 24 and 32 bit modes are only valid for TIMER0
- */
- uint8_t resolution;
-} GPTConfig;
-
-/**
- * @brief Structure representing a GPT driver.
- */
-struct GPTDriver {
- /**
- * @brief Driver state.
- */
- gptstate_t state;
- /**
- * @brief Current configuration data.
- */
- const GPTConfig *config;
-#if defined(GPT_DRIVER_EXT_FIELDS)
- GPT_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the TIMERx registers block.
- */
- NRF_TIMER_Type *tim;
- /**
- * @brief Index of the TIMERx capture/compare register used for setting the
- * interval between compare events.
- */
- uint8_t cc_int;
- /**
- * @brief Index of the TIMERx capture/compare register used for getting the
- * current timer counter value.
- */
- uint8_t cc_get;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Changes the interval of GPT peripheral.
- * @details This function changes the interval of a running GPT unit.
- * @pre The GPT unit must be running in continuous mode.
- * @post The GPT unit interval is changed to the new value.
- * @note The function has effect at the next cycle start.
- *
- * @param[in] gptp pointer to a @p GPTDriver object
- * @param[in] interval new cycle time in timer ticks
- *
- * @notapi
- */
-#define gpt_lld_change_interval(gptp, interval) \
- ((gptp)->tim->CC[(gptp)->cc_int] = (uint32_t)((interval) - 1))
-
-/**
- * @brief Returns the interval of GPT peripheral.
- * @pre The GPT unit must be running in continuous mode.
- *
- * @param[in] gptp pointer to a @p GPTDriver object
- * @return The current interval.
- *
- * @notapi
- */
-#define gpt_lld_get_interval(gptp) \
- ((gptcnt_t)((gptp)->tim->CC[(gptp)->cc_int]) + 1)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if NRF51_GPT_USE_TIMER0 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD1;
-#endif
-
-#if NRF51_GPT_USE_TIMER1 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD2;
-#endif
-
-#if NRF51_GPT_USE_TIMER2 && !defined(__DOXYGEN__)
-extern GPTDriver GPTD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void gpt_lld_init(void);
- void gpt_lld_start(GPTDriver *gptp);
- void gpt_lld_stop(GPTDriver *gptp);
- void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
- void gpt_lld_stop_timer(GPTDriver *gptp);
- void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
- gptcnt_t gpt_lld_get_counter(GPTDriver *gptp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_GPT */
-
-#endif /* HAL_GPT_LLD_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.c deleted file mode 100644 index 611a004..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.c +++ /dev/null @@ -1,446 +0,0 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51822/i2c_lld.c
- * @brief NRF51822 I2C subsystem low level driver source.
- *
- * @addtogroup I2C
- * @{
- */
-
-#include "osal.h"
-#include "hal.h"
-#include "nrf51_delay.h"
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/* These macros are needed to see if the slave is stuck and we as master send dummy clock cycles to end its wait */
-#define I2C_HIGH(p) do { NRF_GPIO->OUTSET = (1UL << (p)); } while(0) /*!< Pulls I2C line high */
-#define I2C_LOW(p) do { NRF_GPIO->OUTCLR = (1UL << (p)); } while(0) /*!< Pulls I2C line low */
-#define I2C_INPUT(p) do { NRF_GPIO->DIRCLR = (1UL << (p)); } while(0) /*!< Configures I2C pin as input */
-#define I2C_OUTPUT(p) do { NRF_GPIO->DIRSET = (1UL << (p)); } while(0) /*!< Configures I2C pin as output */
-
-#define I2C_PIN_CNF \
- ((GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
- | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
- | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) \
- | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
- | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos))
-
-#define I2C_PIN_CNF_CLR \
- ((GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
- | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
- | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) \
- | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
- | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos))
-
-#if NRF51_I2C_USE_I2C0
-#define I2C_IRQ_NUM SPI0_TWI0_IRQn
-#define I2C_IRQ_PRI NRF51_I2C_I2C0_IRQ_PRIORITY
-#elif NRF51_I2C_USE_I2C1
-#define I2C_IRQ_NUM SPI1_TWI1_IRQn
-#define I2C_IRQ_PRI NRF51_I2C_I2C1_IRQ_PRIORITY
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief I2C0 driver identifier.
- */
-#if NRF51_I2C_USE_I2C0 || defined(__DOXYGEN__)
-I2CDriver I2CD1;
-#endif
-
-/**
- * @brief I2C1 driver identifier.
- */
-#if NRF51_I2C_USE_I2C1 || defined(__DOXYGEN__)
-I2CDriver I2CD2;
-#endif
-
-uint8_t tx_resume_count;
-uint8_t rx_resume_count;
-uint8_t stop_count;
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Function for detecting stuck slaves (SDA = 0 and SCL = 1) and tries to clear the bus.
- *
- * @return
- * @retval false Bus is stuck.
- * @retval true Bus is clear.
- */
-static void i2c_clear_bus(I2CDriver *i2cp)
-{
- const I2CConfig *cfg = i2cp->config;
- int i;
-
- NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;
- NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;
-
- I2C_HIGH(cfg->sda_pad);
- I2C_HIGH(cfg->scl_pad);
-
- NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;
- NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;
-
- nrf_delay_us(4);
-
- for(i = 0; i < 9; i++) {
- if (palReadPad(IOPORT1, cfg->sda_pad)) {
- if(i > 0)
- break;
- else
- return;
- }
-
- I2C_LOW(cfg->scl_pad);
- nrf_delay_us(4);
- I2C_HIGH(cfg->scl_pad);
- nrf_delay_us(4);
- }
-
- I2C_LOW(cfg->sda_pad);
- nrf_delay_us(4);
- I2C_HIGH(cfg->sda_pad);
-}
-
-static inline void i2c_setup_shortcut(I2CDriver *i2cp)
-{
- uint32_t rxbytes = i2cp->rxbytes;
- uint32_t txbytes = i2cp->txbytes;
-
- osalDbgAssert(rxbytes + txbytes, "transfer must be greater than zero");
-
- if (txbytes > 1 || (!txbytes && rxbytes > 1))
- i2cp->i2c->SHORTS = TWI_SHORTS_BB_SUSPEND_Enabled << TWI_SHORTS_BB_SUSPEND_Pos;
- else if (((txbytes == 1) && !rxbytes) || ((rxbytes == 1) && !txbytes))
- i2cp->i2c->SHORTS = TWI_SHORTS_BB_STOP_Enabled << TWI_SHORTS_BB_STOP_Pos;
- else
- i2cp->i2c->SHORTS = 0;
-}
-
-#if defined(__GNUC__)
-__attribute__((noinline))
-#endif
-/**
- * @brief Common IRQ handler.
- * @note Tries hard to clear all the pending interrupt sources, we don't
- * want to go through the whole ISR and have another interrupt soon
- * after.
- *
- * @param[in] i2cp pointer to an I2CDriver
- */
-static void serve_interrupt(I2CDriver *i2cp) {
-
- NRF_TWI_Type *i2c = i2cp->i2c;
-
- if(i2c->EVENTS_TXDSENT) {
-
- i2c->EVENTS_TXDSENT = 0;
-
- if(--i2cp->txbytes) {
-
- i2c->TXD = *i2cp->txptr++;
- i2c_setup_shortcut(i2cp);
- i2c->TASKS_RESUME = 1;
- tx_resume_count++;
- }
- else if (i2cp->rxbytes) {
-
- i2c_setup_shortcut(i2cp);
- i2c->TASKS_STARTRX = 1;
- }
- }
- if(i2c->EVENTS_RXDREADY) {
-
- i2c->EVENTS_RXDREADY = 0;
- *i2cp->rxptr++ = i2c->RXD;
-
- if(--i2cp->rxbytes) {
- i2c_setup_shortcut(i2cp);
- i2c->TASKS_RESUME = 1;
- rx_resume_count++;
- }
- }
- if(i2c->EVENTS_ERROR) {
-
- uint32_t err = i2c->ERRORSRC;
- i2c->EVENTS_ERROR = 0;
-
- if (err & TWI_ERRORSRC_OVERRUN_Msk)
- i2cp->errors |= I2C_OVERRUN;
- if (err & (TWI_ERRORSRC_ANACK_Msk | TWI_ERRORSRC_DNACK_Msk))
- i2cp->errors |= I2C_ACK_FAILURE;
-
- i2c->TASKS_STOP = 1;
- _i2c_wakeup_error_isr(i2cp);
- } else if(i2c->EVENTS_STOPPED) {
-
- stop_count++;
- i2c->EVENTS_STOPPED = 0;
- _i2c_wakeup_isr(i2cp);
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if NRF51_I2C_USE_I2C0 || defined(__DOXYGEN__)
-
-OSAL_IRQ_HANDLER(Vector4C) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&I2CD1);
- OSAL_IRQ_EPILOGUE();
-}
-
-#endif
-
-#if NRF51_I2C_USE_I2C1 || defined(__DOXYGEN__)
-
-OSAL_IRQ_HANDLER(Vector50) {
-
- OSAL_IRQ_PROLOGUE();
- serve_interrupt(&I2CD2);
- OSAL_IRQ_EPILOGUE();
-}
-
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level I2C driver initialization.
- *
- * @notapi
- */
-void i2c_lld_init(void) {
-
-#if NRF51_I2C_USE_I2C0
- i2cObjectInit(&I2CD1);
- I2CD1.thread = NULL;
- I2CD1.i2c = NRF_TWI0;
-#endif
-
-#if NRF51_I2C_USE_I2C1
- i2cObjectInit(&I2CD2);
- I2CD2.thread = NULL;
- I2CD2.i2c = NRF_TWI1;
-#endif
-
-}
-
-/**
- * @brief Configures and activates the I2C peripheral.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_start(I2CDriver *i2cp) {
-
- NRF_TWI_Type *i2c = i2cp->i2c;
- const I2CConfig *cfg = i2cp->config;
-
- if (i2cp->state != I2C_STOP)
- return;
-
- i2c_clear_bus(i2cp);
-
- NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;
- NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;
-
- i2c->EVENTS_RXDREADY = 0;
- i2c->EVENTS_TXDSENT = 0;
- i2c->PSELSCL = cfg->scl_pad;
- i2c->PSELSDA = cfg->sda_pad;
-
- switch (cfg->clock) {
- case 100000:
- i2c->FREQUENCY = TWI_FREQUENCY_FREQUENCY_K100 << TWI_FREQUENCY_FREQUENCY_Pos;
- break;
- case 250000:
- i2c->FREQUENCY = TWI_FREQUENCY_FREQUENCY_K250 << TWI_FREQUENCY_FREQUENCY_Pos;
- break;
- case 400000:
- i2c->FREQUENCY = TWI_FREQUENCY_FREQUENCY_K400 << TWI_FREQUENCY_FREQUENCY_Pos;
- break;
- default:
- osalDbgAssert(0, "invalid I2C frequency");
- break;
- };
-
- nvicEnableVector(I2C_IRQ_NUM, I2C_IRQ_PRI);
-
- i2c->INTENSET = TWI_INTENSET_TXDSENT_Msk | TWI_INTENSET_STOPPED_Msk |
- TWI_INTENSET_ERROR_Msk | TWI_INTENSET_RXDREADY_Msk;
-
- i2c->ENABLE = TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos;
-}
-
-/**
- * @brief Deactivates the I2C peripheral.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_stop(I2CDriver *i2cp) {
-
- NRF_TWI_Type *i2c = i2cp->i2c;
- const I2CConfig *cfg = i2cp->config;
-
- if (i2cp->state != I2C_STOP) {
-
- i2c->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
-
- i2c->INTENCLR = TWI_INTENSET_TXDSENT_Msk | TWI_INTENSET_STOPPED_Msk |
- TWI_INTENSET_ERROR_Msk | TWI_INTENSET_RXDREADY_Msk;
-
- nvicDisableVector(I2C_IRQ_NUM);
-
- NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;
- NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;
- }
-}
-
-static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr,
- const uint8_t *txbuf, size_t txbytes,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout) {
-
- NRF_TWI_Type *i2c = i2cp->i2c;
-
- (void)timeout;
- msg_t msg;
-
- i2cp->errors = I2C_NO_ERROR;
- i2cp->addr = addr;
-
- i2cp->txptr = txbuf;
- i2cp->txbytes = txbytes;
-
- i2cp->rxptr = rxbuf;
- i2cp->rxbytes = rxbytes;
-
- i2c->ADDRESS = addr;
-
- tx_resume_count = 0;
- rx_resume_count = 0;
- stop_count = 0;
-
- if (i2cp->txbytes) {
-
- i2c->TXD = *i2cp->txptr++;
- i2c_setup_shortcut(i2cp);
- i2c->TASKS_STARTTX = 1;
- } else if (i2cp->rxbytes) {
-
- i2c_setup_shortcut(i2cp);
- i2c->TASKS_STARTRX = 1;
- } else {
-
- osalDbgAssert(0, "no bytes to transfer");
- }
-
- msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
-
- if (msg == MSG_TIMEOUT)
- i2c->TASKS_STOP = 1;
-
- return msg;
-}
-
-/**
- * @brief Receives data via the I2C bus as master.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] addr slave device address
- * @param[out] rxbuf pointer to the receive buffer
- * @param[in] rxbytes number of bytes to be received
- * @param[in] timeout the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval MSG_OK if the function succeeded.
- * @retval MSG_RESET if one or more I2C errors occurred, the errors can
- * be retrieved using @p i2cGetErrors().
- * @retval MSG_TIMEOUT if a timeout occurred before operation end. <b>After a
- * timeout the driver must be stopped and restarted
- * because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout) {
-
- return _i2c_txrx_timeout(i2cp, addr, NULL, 0, rxbuf, rxbytes, timeout);
-}
-
-/**
- * @brief Transmits data via the I2C bus as master.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] addr slave device address
- * @param[in] txbuf pointer to the transmit buffer
- * @param[in] txbytes number of bytes to be transmitted
- * @param[out] rxbuf pointer to the receive buffer
- * @param[in] rxbytes number of bytes to be received
- * @param[in] timeout the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The operation status.
- * @retval MSG_OK if the function succeeded.
- * @retval MSG_RESET if one or more I2C errors occurred, the errors can
- * be retrieved using @p i2cGetErrors().
- * @retval MSG_TIMEOUT if a timeout occurred before operation end. <b>After a
- * timeout the driver must be stopped and restarted
- * because the bus is in an uncertain state</b>.
- *
- * @notapi
- */
-msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
- const uint8_t *txbuf, size_t txbytes,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout) {
-
- return _i2c_txrx_timeout(i2cp, addr, txbuf, txbytes, rxbuf, rxbytes, timeout);
-}
-
-#endif /* HAL_USE_I2C */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.h deleted file mode 100644 index e2c3d07..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.h +++ /dev/null @@ -1,232 +0,0 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51822/i2c_lld.h
- * @brief NRF51822 I2C subsystem low level driver header.
- *
- * @addtogroup I2C
- * @{
- */
-
-#ifndef HAL_I2C_LLD_H
-#define HAL_I2C_LLD_H
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-#define STATE_STOP 0x00
-#define STATE_SEND 0x01
-#define STATE_RECV 0x02
-#define STATE_DUMMY 0x03
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief I2C0 driver enable switch.
- * @details If set to @p TRUE the support for I2C0 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(NRF51_I2C_USE_I2C0) || defined(__DOXYGEN__)
-#define NRF51_I2C_USE_I2C0 FALSE
-#endif
-
-/**
- * @brief I2C1 driver enable switch.
- * @details If set to @p TRUE the support for I2C1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(NRF51_I2C_USE_I2C1) || defined(__DOXYGEN__)
-#define NRF51_I2C_USE_I2C1 FALSE
-#endif
-
-/**
- * @brief I2C0 interrupt priority level setting.
- */
-#if !defined(NRF51_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_I2C_I2C0_IRQ_PRIORITY 3
-#endif
-
-/**
- * @brief I2C1 interrupt priority level setting.
- */
-#if !defined(NRF51_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_I2C_I2C1_IRQ_PRIORITY 3
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if NRF51_I2C_USE_I2C0 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_I2C_I2C0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to I2C0"
-#endif
-
-#if NRF51_I2C_USE_I2C1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_I2C_I2C1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to I2C1"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/* @brief Type representing I2C address. */
-typedef uint8_t i2caddr_t;
-
-/* @brief Type of I2C Driver condition flags. */
-typedef uint32_t i2cflags_t;
-
-/* @brief Type used to control the ISR state machine. */
-typedef uint8_t intstate_t;
-
-/**
- * @brief Driver configuration structure.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
-
- /* @brief Clock to be used for the I2C bus. */
- uint32_t clock;
- /* @brief Pad number for SCL */
- uint8_t scl_pad;
- /* @brief Pad number for SDA */
- uint8_t sda_pad;
-
-} I2CConfig;
-
-/**
- * @brief Type of a structure representing an I2C driver.
- */
-typedef struct I2CDriver I2CDriver;
-
-/**
- * @brief Structure representing an I2C driver.
- */
-struct I2CDriver {
- /**
- * @brief Driver state.
- */
- i2cstate_t state;
- /**
- * @brief Current configuration data.
- */
- const I2CConfig *config;
- /**
- * @brief Error flags.
- */
- i2cflags_t errors;
-#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the bus.
- */
- mutex_t mutex;
-#elif CH_CFG_USE_SEMAPHORES
- semaphore_t semaphore;
-#endif
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
-#if defined(I2C_DRIVER_EXT_FIELDS)
- I2C_DRIVER_EXT_FIELDS
-#endif
- /* @brief Thread waiting for I/O completion. */
- thread_reference_t thread;
- /* @brief Current slave address without R/W bit. */
- i2caddr_t addr;
-
- /* End of the mandatory fields.*/
-
- /* @brief Pointer to the buffer with data to send. */
- const uint8_t *txptr;
- /* @brief Number of bytes of data to send. */
- size_t txbytes;
- /* @brief Pointer to the buffer to put received data. */
- uint8_t *rxptr;
- /* @brief Number of bytes of data to receive. */
- size_t rxbytes;
- /* @brief Tracks current ISR state. */
- intstate_t intstate;
- /* @brief Low-level register access. */
- NRF_TWI_Type *i2c;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Get errors from I2C driver.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-
-#if NRF51_I2C_USE_I2C0
-extern I2CDriver I2CD1;
-#endif
-
-#if NRF51_I2C_USE_I2C1
-extern I2CDriver I2CD2;
-#endif
-
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void i2c_lld_init(void);
- void i2c_lld_start(I2CDriver *i2cp);
- void i2c_lld_stop(I2CDriver *i2cp);
- msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
- const uint8_t *txbuf, size_t txbytes,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout);
- msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_I2C */
-
-#endif /* HAL_I2C_LLD_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_lld.c deleted file mode 100644 index af5e377..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_lld.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - Copyright (C) 2015 Fabio Utzig - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file NRF51/NRF51822/hal_lld.c - * @brief NRF51822 HAL Driver subsystem low level driver source. - * - * @addtogroup HAL - * @{ - */ - -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - * - * @notapi - */ -void hal_lld_init(void) -{ - /* High frequency clock initialisation - * (If NRF51_XTAL_VALUE is not defined assume its an RC oscillator) - */ - NRF_CLOCK->TASKS_HFCLKSTOP = 1; -#if defined(NRF51_XTAL_VALUE) -#if NRF51_XTAL_VALUE == 16000000 - NRF_CLOCK->XTALFREQ = 0xFF; -#elif NRF51_XTAL_VALUE == 32000000 - NRF_CLOCK->XTALFREQ = 0x00; -#endif -#endif - - - /* Low frequency clock initialisation - * Clock is only started if st driver requires it - */ - NRF_CLOCK->TASKS_LFCLKSTOP = 1; - NRF_CLOCK->LFCLKSRC = NRF51_LFCLK_SOURCE; - -#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) && \ - (NRF51_SYSTEM_TICKS == NRF51_SYSTEM_TICKS_AS_RTC) - NRF_CLOCK->TASKS_LFCLKSTART = 1; -#endif -} - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_lld.h deleted file mode 100644 index e404020..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_lld.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - Copyright (C) 2015 Fabio Utzig - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file NRF51/NRF51822/hal_lld.h - * @brief NRF51822 HAL subsystem low level driver header. - * - * @addtogroup HAL - * @{ - */ - -#ifndef HAL_LLD_H -#define HAL_LLD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Platform identification - * @{ - */ -#define PLATFORM_NAME "Nordic Semiconductor nRF51822" - -/** - * @} - */ - -/** - * @brief Frequency valuefor the Low Frequency Clock - */ -#define NRF51_LFCLK_FREQUENCY 32768 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Select source of Low Frequency Clock (LFCLK) - * @details Possible values for source are: - * 0 : RC oscillator - * 1 : External cristal - * 2 : Synthetized clock from High Frequency Clock (HFCLK) - * When cristal is not available it's preferable to use the - * internal RC oscillator that synthezing the clock. - */ -#if !defined(NRF51_LFCLK_SOURCE) || defined(__DOXYGEN__) -#define NRF51_LFCLK_SOURCE 0 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (NRF51_LFCLK_SOURCE < 0) || (NRF51_LFCLK_SOURCE > 2) -#error "Possible value for NRF51_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#include "nvic.h" - -#define NRF51_LFCLK_FREQUENCY 32768 -#define NRF51_HFCLK_FREQUENCY 16000000 - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void nrf51_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_LLD_H */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_pal_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_pal_lld.c deleted file mode 100644 index 69fc9fe..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_pal_lld.c +++ /dev/null @@ -1,158 +0,0 @@ -/*
- Copyright (C) 2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file pal_lld.c
- * @brief NRF51822 PAL subsystem low level driver source.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "osal.h"
-#include "hal.h"
-
-#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
-{
- (void)port;
- osalDbgAssert(pad <= 31, "pal_lld_setpadmode() - invalid pad");
-
- switch (mode) {
- case PAL_MODE_RESET:
- case PAL_MODE_UNCONNECTED:
- NRF_GPIO->PIN_CNF[pad] =
- (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |
- (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |
- (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
- (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) |
- (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
- break;
- case PAL_MODE_INPUT:
- case PAL_MODE_INPUT_ANALOG:
- NRF_GPIO->PIN_CNF[pad] =
- (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |
- (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |
- (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
- (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
- (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
- break;
- case PAL_MODE_INPUT_PULLUP:
- NRF_GPIO->PIN_CNF[pad] =
- (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |
- (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |
- (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) |
- (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
- (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
- break;
- case PAL_MODE_INPUT_PULLDOWN:
- NRF_GPIO->PIN_CNF[pad] =
- (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |
- (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |
- (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos) |
- (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
- (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
- break;
- case PAL_MODE_OUTPUT_PUSHPULL:
- NRF_GPIO->PIN_CNF[pad] =
- (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |
- (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |
- (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
- (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) |
- (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
- break;
- case PAL_MODE_OUTPUT_OPENDRAIN:
- NRF_GPIO->PIN_CNF[pad] =
- (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) |
- (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) |
- (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
- (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) |
- (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
- break;
- default:
- osalDbgAssert(FALSE, "invalid pal mode");
- break;
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief NRF51 I/O ports configuration.
- *
- * @param[in] config the NRF51 ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config)
-{
- uint8_t i;
-
- for (i = 0; i < TOTAL_GPIO_PADS; i++) {
- pal_lld_setpadmode(IOPORT1, i, config->pads[i]);
- }
-}
-
-/**
- * @brief Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- *
- * @param[in] port the port identifier
- * @param[in] mask the group mask
- * @param[in] mode the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode)
-{
- uint8_t i;
-
- for (i = 0; i < TOTAL_GPIO_PADS; i++, mask >>= 1) {
- if (mask & 1) {
- pal_lld_setpadmode(port, i, mode);
- }
- }
-}
-
-#endif /* HAL_USE_PAL == TRUE */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_pal_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_pal_lld.h deleted file mode 100644 index 5032916..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_pal_lld.h +++ /dev/null @@ -1,347 +0,0 @@ -/*
- Copyright (C) 2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file pal_lld.h
- * @brief NRF51822 PAL subsystem low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef HAL_PAL_LLD_H
-#define HAL_PAL_LLD_H
-
-#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* I/O Ports Types and constants. */
-/*===========================================================================*/
-
-#define TOTAL_GPIO_PADS 32
-
-/**
- * @name Port related definitions
- * @{
- */
-/**
- * @brief Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32U
-
-/**
- * @brief Whole port mask.
- * @brief This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFFU)
-/** @} */
-
-/**
- * @name Line handling macros
- * @{
- */
-/**
- * @brief Forms a line identifier.
- * @details A port/pad pair are encoded into an @p ioline_t type. The encoding
- * of this type is platform-dependent.
- */
-#define PAL_LINE(port, pad) \
- ((ioline_t)((uint32_t)(pad)))
-
-/**
- * @brief Decodes a port identifier from a line identifier.
- */
-#define PAL_PORT(line) \
- ((ioportid_t)(IOPORT1))
-
-/**
- * @brief Decodes a pad identifier from a line identifier.
- */
-#define PAL_PAD(line) \
- ((uint32_t)(line))
-
-/**
- * @brief Value identifying an invalid line.
- */
-#define PAL_NOLINE ((ioline_t)-1)
-/** @} */
-
-/**
- * @brief Generic I/O ports static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- * system startup time in order to initialized the digital I/O
- * subsystem. This represents only the initial setup, specific pads
- * or whole ports can be reprogrammed at later time.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- uint32_t pads[TOTAL_GPIO_PADS];
-} PALConfig;
-
-/**
- * @brief Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief Digital I/O modes.
- */
-typedef uint8_t iomode_t;
-
-/**
- * @brief Type of an I/O line.
- */
-typedef uint32_t ioline_t;
-
-/**
- * @brief Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- * any assumption about it, use the provided macros when populating
- * variables of this type.
- */
-typedef NRF_GPIO_Type *ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers. */
-/*===========================================================================*/
-
-/**
- * @brief First I/O port identifier.
- * @details Low level drivers can define multiple ports, it is suggested to
- * use this naming convention.
- */
-#define IOPORT1 NRF_GPIO
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as */
-/* functions, if so please put them in pal_lld.c. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PAL subsystem initialization.
- *
- * @param[in] config architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief Reads the physical I/O port states.
- *
- * @param[in] port port identifier
- * @return The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) (NRF_GPIO->IN)
-
-/**
- * @brief Reads the output latch.
- * @details The purpose of this function is to read back the latched output
- * value.
- *
- * @param[in] port port identifier
- * @return The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) (NRF_GPIO->OUT)
-
-/**
- * @brief Writes a bits mask on a I/O port.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) (NRF_GPIO->OUT = (bits))
-
-/**
- * @brief Sets a bits mask on a I/O port.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) (NRF_GPIO->OUTSET = (bits))
-
-
-/**
- * @brief Clears a bits mask on a I/O port.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) (NRF_GPIO->OUTCLR = (bits))
-
-/**
- * @brief Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] mode group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode) \
- _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief Reads a logical state from an I/O pad.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @return The logical state.
- * @retval PAL_LOW low logical state.
- * @retval PAL_HIGH high logical state.
- *
- * @notapi
- */
-#define pal_lld_readpad(port, pad) \
- ((NRF_GPIO->IN & ((uint32_t) 1 << pad)) ? PAL_HIGH : PAL_LOW)
-
-/**
- * @brief Writes a logical state on an output pad.
- * @note This function is not meant to be invoked directly by the
- * application code.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] bit logical value, the value must be @p PAL_LOW or
- * @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit) \
- do { \
- (void)port; \
- if (bit == PAL_HIGH) \
- NRF_GPIO->OUTSET = ((uint32_t) 1 << pad); \
- else \
- NRF_GPIO->OUTCLR = ((uint32_t) 1 << pad); \
- } while (false)
-
-/**
- * @brief Sets a pad logical state to @p PAL_HIGH.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_setpad(port, pad) (NRF_GPIO->OUTSET = (uint32_t) 1 << (pad))
-
-/**
- * @brief Clears a pad logical state to @p PAL_LOW.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_clearpad(port, pad) (NRF_GPIO->OUTCLR = (uint32_t) 1 << (pad))
-
-/**
- * @brief Toggles a pad logical state.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- *
- * @notapi
- */
-#define pal_lld_togglepad(port, pad) \
- do { \
- uint8_t bit = (NRF_GPIO->IN >> (pad)) & 1; \
- if (bit) \
- NRF_GPIO->OUTCLR = 1 << (pad); \
- else \
- NRF_GPIO->OUTSET = 1 << (pad); \
- } while (0)
-
-/**
- * @brief Pad mode setup.
- * @details This function programs a pad with the specified mode.
- * @note The @ref PAL provides a default software implementation of this
- * functionality, implement this function if can optimize it by using
- * special hardware functionalities or special coding.
- * @note Programming an unknown or unsupported mode is silently ignored.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] mode pad mode
- *
- * @notapi
- */
-#define pal_lld_setpadmode(port, pad, mode) _pal_lld_setpadmode(port, pad, mode)
-
-#if !defined(__DOXYGEN__)
-extern const PALConfig pal_default_config;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void _pal_lld_init(const PALConfig *config);
- void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode);
- void _pal_lld_setpadmode(ioportid_t port,
- uint8_t pad,
- iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL == TRUE */
-
-#endif /* HAL_PAL_LLD_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c deleted file mode 100644 index 456dcff..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c +++ /dev/null @@ -1,425 +0,0 @@ -/*
- ChibiOS/HAL - Copyright (C) 2016 Stéphane D'Alu
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file hal_pwm_lld.c
- * @brief NRF51 PWM subsystem low level driver source.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief PWMD1 driver identifier.
- * @note The driver PWMD1 allocates the timer TIMER0 when enabled.
- */
-#if NRF51_PWM_USE_TIMER0 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief PWMD2 driver identifier.
- * @note The driver PWMD2 allocates the timer TIMER1 when enabled.
- */
-#if NRF51_PWM_USE_TIMER1 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief PWMD3 driver identifier.
- * @note The driver PWMD3 allocates the timer TIMER2 when enabled.
- */
-#if NRF51_PWM_USE_TIMER2 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
- // Deal with PWM channels
- uint8_t n;
- for (n = 0 ; n < pwmp->channels ; n++) {
- if (pwmp->timer->EVENTS_COMPARE[n]) {
- pwmp->timer->EVENTS_COMPARE[n] = 0;
-
- if (pwmp->config->channels[n].callback != NULL) {
- pwmp->config->channels[n].callback(pwmp);
- }
- }
- }
-
- // Deal with PWM period
- if (pwmp->timer->EVENTS_COMPARE[pwmp->channels]) {
- pwmp->timer->EVENTS_COMPARE[pwmp->channels] = 0;
-
- if (pwmp->config->callback != NULL) {
- pwmp->config->callback(pwmp);
- }
- }
-
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if NRF51_PWM_USE_TIMER0
-/**
- * @brief TIMER0 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector60) {
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD1);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* NRF51_PWM_USE_TIMER0 */
-
-#if NRF51_PWM_USE_TIMER1
-/**
- * @brief TIMER1 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector64) {
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD2);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* NRF51_PWM_USE_TIMER1 */
-
-#if NRF51_PWM_USE_TIMER2
-/**
- * @brief TIMER2 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector68) {
- OSAL_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt(&PWMD3);
- OSAL_IRQ_EPILOGUE();
-}
-#endif /* NRF51_PWM_USE_TIMER2 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-
-#if NRF51_PWM_USE_TIMER0
- pwmObjectInit(&PWMD1);
- PWMD1.channels = PWM_CHANNELS;
- PWMD1.timer = NRF_TIMER0;
-#endif
-
-#if NRF51_PWM_USE_TIMER1
- pwmObjectInit(&PWMD2);
- PWMD2.channels = PWM_CHANNELS;
- PWMD2.timer = NRF_TIMER1;
-#endif
-
-#if NRF51_PWM_USE_TIMER2
- pwmObjectInit(&PWMD3);
- PWMD3.channels = PWM_CHANNELS;
- PWMD3.timer = NRF_TIMER2;
-#endif
-}
-
-/**
- * @brief Configures and activates the PWM peripheral.
- * @note Starting a driver that is already in the @p PWM_READY state
- * disables all the active channels.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
- // Prescaler value calculation: ftimer = 16MHz / 2^PRESCALER
- uint16_t psc_ratio = NRF51_HFCLK_FREQUENCY / pwmp->config->frequency;
- // Prescaler ratio must be between 1 and 512, and a power of two.
- osalDbgAssert(psc_ratio <= 512 && !(psc_ratio & (psc_ratio - 1)),
- "invalid frequency");
- // Prescaler value as a power of 2, must be 0..9
- uint32_t psc_value;
- for (psc_value = 0; psc_value < 10; psc_value++)
- if (psc_ratio == (unsigned)(1 << psc_value))
- break;
-
-
- // Configure as 16bits timer (only TIMER0 support 32bits)
- pwmp->timer->BITMODE = TIMER_BITMODE_BITMODE_16Bit;
- pwmp->timer->MODE = TIMER_MODE_MODE_Timer;
-
- // With clear shortcuts for period
- pwmp->timer->SHORTS =
- 0x1UL << (TIMER_SHORTS_COMPARE0_CLEAR_Pos + pwmp->channels);
-
- // Disable and reset interrupts for compare events
- pwmp->timer->INTENCLR = (TIMER_INTENCLR_COMPARE0_Msk |
- TIMER_INTENCLR_COMPARE1_Msk |
- TIMER_INTENCLR_COMPARE2_Msk |
- TIMER_INTENCLR_COMPARE3_Msk );
- pwmp->timer->EVENTS_COMPARE[0] = 0;
- pwmp->timer->EVENTS_COMPARE[1] = 0;
- pwmp->timer->EVENTS_COMPARE[2] = 0;
- pwmp->timer->EVENTS_COMPARE[3] = 0;
-
- // Set prescaler
- pwmp->timer->PRESCALER = psc_value;
-
- // Set period
- pwmp->timer->CC[pwmp->channels] = pwmp->period;
-
- // Clear everything
- pwmp->timer->TASKS_CLEAR = 1;
-
-
- // Enable interrupt
-#if NRF51_PWM_USE_TIMER0
- if (&PWMD1 == pwmp) {
- nvicEnableVector(TIMER0_IRQn, NRF51_PWM_TIMER0_PRIORITY);
- }
-#endif
-
-#if NRF51_PWM_USE_TIMER1
- if (&PWMD2 == pwmp) {
- nvicEnableVector(TIMER1_IRQn, NRF51_PWM_TIMER1_PRIORITY);
- }
-#endif
-
-#if NRF51_PWM_USE_TIMER2
- if (&PWMD3 == pwmp) {
- nvicEnableVector(TIMER2_IRQn, NRF51_PWM_TIMER2_PRIORITY);
- }
-#endif
-
- // Start timer
- pwmp->timer->TASKS_START = 1;
-}
-
-/**
- * @brief Deactivates the PWM peripheral.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
- pwmp->timer->TASKS_STOP = 1;
-
-#if NRF51_PWM_USE_TIMER0
- if (&PWMD1 == pwmp) {
- nvicDisableVector(TIMER0_IRQn);
- }
-#endif
-
-#if NRF51_PWM_USE_TIMER1
- if (&PWMD2 == pwmp) {
- nvicDisableVector(TIMER1_IRQn);
- }
-#endif
-
-#if NRF51_PWM_USE_TIMER2
- if (&PWMD3 == pwmp) {
- nvicDisableVector(TIMER2_IRQn);
- }
-#endif
-}
-
-/**
- * @brief Enables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is active using the specified configuration.
- * @note The function has effect at the next cycle start.
- * @note Channel notification is not enabled.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- * @param[in] width PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width) {
-#if NRF51_PWM_USE_GPIOTE_PPI
- const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];
-
- uint32_t outinit;
- switch(cfg_channel->mode & PWM_OUTPUT_MASK) {
- case PWM_OUTPUT_ACTIVE_LOW:
- outinit = GPIOTE_CONFIG_OUTINIT_Low;
- break;
- case PWM_OUTPUT_ACTIVE_HIGH:
- outinit = GPIOTE_CONFIG_OUTINIT_High;
- break;
- case PWM_OUTPUT_DISABLED:
- default:
- goto no_output_config;
- }
-
- const uint32_t gpio_pin = PAL_PAD(cfg_channel->ioline);
- const uint8_t gpiote_channel = cfg_channel->gpiote_channel;
- const uint8_t *ppi_channel = cfg_channel->ppi_channel;
- const uint32_t polarity = GPIOTE_CONFIG_POLARITY_Toggle;
-
- // Create GPIO Task
- NRF_GPIOTE->CONFIG[gpiote_channel] = GPIOTE_CONFIG_MODE_Task |
- ((gpio_pin << GPIOTE_CONFIG_PSEL_Pos ) & GPIOTE_CONFIG_PSEL_Msk) |
- ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
- ((outinit << GPIOTE_CONFIG_OUTINIT_Pos ) & GPIOTE_CONFIG_OUTINIT_Msk);
-
- // Program tasks (one for duty cycle, one for periode)
- NRF_PPI->CH[ppi_channel[0]].EEP =
- (uint32_t)&pwmp->timer->EVENTS_COMPARE[channel];
- NRF_PPI->CH[ppi_channel[0]].TEP =
- (uint32_t)&NRF_GPIOTE->TASKS_OUT[gpiote_channel];
- NRF_PPI->CH[ppi_channel[1]].EEP =
- (uint32_t)&pwmp->timer->EVENTS_COMPARE[pwmp->channels];
- NRF_PPI->CH[ppi_channel[1]].TEP =
- (uint32_t)&NRF_GPIOTE->TASKS_OUT[gpiote_channel];
- NRF_PPI->CHENSET = ((1 << ppi_channel[0]) | (1 << ppi_channel[1]));
-
- no_output_config:
-#endif
-
- pwmp->timer->CC[channel] = width;
-}
-
-/**
- * @brief Disables a PWM channel and its notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is disabled and its output line returned to the
- * idle state.
- * @note The function has effect at the next cycle start.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
- pwmp->timer->CC[channel] = 0;
-#if NRF51_PWM_USE_GPIOTE_PPI
- const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];
- switch(cfg_channel->mode & PWM_OUTPUT_MASK) {
- case PWM_OUTPUT_ACTIVE_LOW:
- case PWM_OUTPUT_ACTIVE_HIGH: {
- const uint8_t gpiote_channel = cfg_channel->gpiote_channel;
- const uint8_t *ppi_channel = cfg_channel->ppi_channel;
- NRF_PPI->CHENCLR = ((1 << ppi_channel[0]) | (1 << ppi_channel[1]));
- NRF_GPIOTE->CONFIG[gpiote_channel] = GPIOTE_CONFIG_MODE_Disabled;
- break;
- }
- case PWM_OUTPUT_DISABLED:
- default:
- break;
- }
-#endif
-}
-
-/**
- * @brief Enables the periodic activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @note If the notification is already enabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
- pwmp->timer->INTENSET =
- 0x1UL << (TIMER_INTENSET_COMPARE0_Pos + pwmp->channels);
-}
-
-/**
- * @brief Disables the periodic activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @note If the notification is already disabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
- pwmp->timer->INTENCLR =
- 0x1UL << (TIMER_INTENCLR_COMPARE0_Pos + pwmp->channels);
-}
-
-/**
- * @brief Enables a channel de-activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @pre The channel must have been activated using @p pwmEnableChannel().
- * @note If the notification is already enabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel) {
- pwmp->timer->INTENSET =
- 0x1UL << (TIMER_INTENSET_COMPARE0_Pos + channel);
-}
-
-/**
- * @brief Disables a channel de-activation edge notification.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @pre The channel must have been activated using @p pwmEnableChannel().
- * @note If the notification is already disabled then the call has no effect.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...channels-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel) {
- pwmp->timer->INTENCLR =
- 0x1UL << (TIMER_INTENCLR_COMPARE0_Pos + channel);
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.h deleted file mode 100644 index e2982d8..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.h +++ /dev/null @@ -1,333 +0,0 @@ -/*
- ChibiOS/HAL - Copyright (C) 2016 Stéphane D'Alu
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file hal_pwm_lld.h
- * @brief NRF51 PWM subsystem low level driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef HAL_PWM_LLD_H_
-#define HAL_PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS 3
-
-
-#define PWM_FREQUENCY_16MHZ 16000000 /** @brief 16MHz */
-#define PWM_FREQUENCY_8MHZ 8000000 /** @brief 8MHz */
-#define PWM_FREQUENCY_4MHZ 4000000 /** @brief 4MHz */
-#define PWM_FREQUENCY_2MHZ 2000000 /** @brief 2MHz */
-#define PWM_FREQUENCY_1MHZ 1000000 /** @brief 1MHz */
-#define PWM_FREQUENCY_500KHZ 500000 /** @brief 500kHz */
-#define PWM_FREQUENCY_250KHZ 250000 /** @brief 250kHz */
-#define PWM_FREQUENCY_125KHZ 125000 /** @brief 125kHz */
-#define PWM_FREQUENCY_62500HZ 62500 /** @brief 62500Hz */
-#define PWM_FREQUENCY_31250HZ 31250 /** @brief 31250Hz */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-
-/**
- * @brief TIMER0 as driver implementation
- */
-#if !defined(NRF51_PWM_USE_TIMER0)
-#define NRF51_PWM_USE_TIMER0 FALSE
-#endif
-
-/**
- * @brief TIMER1 as driver implementation
- */
-#if !defined(NRF51_PWM_USE_TIMER1)
-#define NRF51_PWM_USE_TIMER1 FALSE
-#endif
-
-/**
- * @brief TIMER2 as driver implementation
- */
-#if !defined(NRF51_PWM_USE_TIMER2)
-#define NRF51_PWM_USE_TIMER2 FALSE
-#endif
-
-/**
- * @brief TIMER0 interrupt priority level setting.
- */
-#if !defined(NRF51_PWM_TIMER0_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_PWM_TIMER0_PRIORITY 3
-#endif
-
-/**
- * @brief TIMER1 interrupt priority level setting.
- */
-#if !defined(NRF51_PWM_TIMER1_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_PWM_TIMER1_PRIORITY 3
-#endif
-
-/**
- * @brief TIMER2 interrupt priority level setting.
- */
-#if !defined(NRF51_PWM_TIMER2_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_PWM_TIMER2_PRIORITY 3
-#endif
-
-/**
- * @brief Allow driver to use GPIOTE/PPI to control PAL line
- */
-#if !defined(NRF51_PWM_USE_GPIOTE_PPI)
-#define NRF51_PWM_USE_GPIOTE_PPI FALSE
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Configuration checks. */
-/*===========================================================================*/
-
-#if !NRF51_PWM_USE_TIMER0 && !NRF51_PWM_USE_TIMER1 && !NRF51_PWM_USE_TIMER2
-#error "PWM driver activated but no TIMER peripheral assigned"
-#endif
-
-#if (NRF51_ST_USE_TIMER0 == TRUE) && (NRF51_PWM_USE_TIMER0 == TRUE)
-#error "TIMER0 used for ST and PWM"
-#endif
-
-#if NRF51_PWM_USE_TIMER0 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER0_PRIORITY)
-#error "Invalid IRQ priority assigned to TIMER0"
-#endif
-
-#if NRF51_PWM_USE_TIMER1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER1_PRIORITY)
-#error "Invalid IRQ priority assigned to TIMER1"
-#endif
-
-#if NRF51_PWM_USE_TIMER2 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER2_PRIORITY)
-#error "Invalid IRQ priority assigned to TIMER2"
-#endif
-
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a PWM mode.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief Type of a PWM channel.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief Type of a channels mask.
- */
-typedef uint32_t pwmchnmsk_t;
-
-/**
- * @brief Type of a PWM counter.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief Type of a PWM driver channel configuration structure.
- */
-typedef struct {
- /**
- * @brief Channel active logic level.
- */
- pwmmode_t mode;
-
- /**
- * @brief Channel callback pointer.
- * @note This callback is invoked on the channel compare event. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /* End of the mandatory fields.*/
-
- /**
- * @brief PAL line to toggle.
- * @note Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.
- * @note When NRF51_PWM_USE_GPIOTE_PPI is used and channel enabled,
- * it wont be possible to access this PAL line using the PAL
- * driver.
- */
- ioline_t ioline;
-
-#if NRF51_PWM_USE_GPIOTE_PPI || defined(__DOXYGEN__)
- /**
- * @brief Unique GPIOTE channel to use. (1 channel)
- * @note Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.
- * @note Only 4 GPIOTE channels are available on nRF51.
- */
- uint8_t gpiote_channel;
-
- /**
- * @brief Unique PPI channels to use. (2 channels)
- * @note Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.
- * @note Only 16 PPI channels are available on nRF51
- * (When Softdevice is enabled, only channels 0-7 are available)
- */
- uint8_t ppi_channel[2];
-#endif
-} PWMChannelConfig;
-
-/**
- * @brief Type of a PWM driver configuration structure.
- */
-typedef struct {
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- uint32_t frequency;
- /**
- * @brief PWM period in ticks.
- * @note The low level can use assertions in order to catch invalid
- * period specifications.
- */
- pwmcnt_t period;
- /**
- * @brief Periodic callback pointer.
- * @note This callback is invoked on PWM counter reset. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /**
- * @brief Channels configurations.
- */
- PWMChannelConfig channels[PWM_CHANNELS];
- /* End of the mandatory fields.*/
-} PWMConfig;
-
-/**
- * @brief Structure representing a PWM driver.
- */
-struct PWMDriver {
- /**
- * @brief Driver state.
- */
- pwmstate_t state;
- /**
- * @brief Current driver configuration data.
- */
- const PWMConfig *config;
- /**
- * @brief Current PWM period in ticks.
- */
- pwmcnt_t period;
- /**
- * @brief Mask of the enabled channels.
- */
- pwmchnmsk_t enabled;
- /**
- * @brief Number of channels in this instance.
- */
- pwmchannel_t channels;
-#if defined(PWM_DRIVER_EXT_FIELDS)
- PWM_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the TIMER registers block.
- */
- NRF_TIMER_Type *timer;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- * been activated using @p pwmStart().
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The PWM unit period is changed to the new value.
- * @note The function has effect at the next cycle start.
- * @note If a period is specified that is shorter than the pulse width
- * programmed in one of the channels then the behavior is not
- * guaranteed.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] period new cycle time in ticks
- *
- * @notapi
- */
-#define pwm_lld_change_period(pwmp, period) \
- do { \
- (pwmp)->timer->CC[(pwmp)->channels] = ((period) - 1); \
- } while(0)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if NRF51_PWM_USE_TIMER0 || defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-#if NRF51_PWM_USE_TIMER1 || defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-#if NRF51_PWM_USE_TIMER2 || defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void pwm_lld_init(void);
- void pwm_lld_start(PWMDriver *pwmp);
- void pwm_lld_stop(PWMDriver *pwmp);
- void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width);
- void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
- void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
- void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
- void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel);
- void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
- pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* HAL_PWM_LLD_H_ */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_rng_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_rng_lld.c deleted file mode 100644 index 5e501ed..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_rng_lld.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - RNG for ChibiOS - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file NRF51/RNGv1/rng_lld.c - * @brief NRF51 RNG subsystem low level driver source. - * - * @addtogroup RNG - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_RNG == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief RNG default configuration. - */ -static const RNGConfig default_config = { - .digital_error_correction = 1, -}; - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief RNG1 driver identifier.*/ -#if NRF51_RNG_USE_RNG1 || defined(__DOXYGEN__) -RNGDriver RNGD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level RNG driver initialization. - * - * @notapi - */ -void rng_lld_init(void) { - rngObjectInit(&RNGD1); - RNGD1.rng = NRF_RNG; -} - -/** - * @brief Configures and activates the RNG peripheral. - * - * @param[in] rngp pointer to the @p RNGDriver object - * - * @notapi - */ -void rng_lld_start(RNGDriver *rngp) { - if (rngp->config == NULL) - rngp->config = &default_config; - - rngp->rng->POWER = 1; - - if (rngp->config->digital_error_correction) - rngp->rng->CONFIG |= RNG_CONFIG_DERCEN_Msk; - else - rngp->rng->CONFIG &= ~RNG_CONFIG_DERCEN_Msk; - - rngp->rng->EVENTS_VALRDY = 0; - rngp->rng->INTENSET = RNG_INTENSET_VALRDY_Msk; - rngp->rng->TASKS_START = 1; -} - - -/** - * @brief Deactivates the RNG peripheral. - * - * @param[in] rngp pointer to the @p RNGDriver object - * - * @notapi - */ -void rng_lld_stop(RNGDriver *rngp) { - rngp->rng->TASKS_STOP = 1; - rngp->rng->POWER = 0; -} - - -/** - * @brief Write random bytes; - * - * @param[in] rngp pointer to the @p RNGDriver object - * @param[in] n size of buf in bytes - * @param[in] buf @p buffer location - * - * @notapi - */ -msg_t rng_lld_write(RNGDriver *rngp, uint8_t *buf, size_t n, - systime_t timeout) { - size_t i; - - for (i = 0 ; i < n ; i++) { - /* Wait for byte ready - * It take about 677µs to generate a new byte, not sure if - * forcing a context switch will be a benefit - */ - while (NRF_RNG->EVENTS_VALRDY == 0) { - /* Sleep and wakeup on ARM event (interrupt) */ - SCB->SCR |= SCB_SCR_SEVONPEND_Msk; - __SEV(); - __WFE(); - __WFE(); - } - - /* Read byte */ - buf[i] = (char)NRF_RNG->VALUE; - - /* Mark as read */ - NRF_RNG->EVENTS_VALRDY = 0; - - /* Clear interrupt so we can wake up again */ - nvicClearPending(RNG_IRQn); - } - return MSG_OK; -} - -#endif /* HAL_USE_RNG */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_rng_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_rng_lld.h deleted file mode 100644 index 0ad0bc6..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_rng_lld.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - RNG for ChibiOS - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file NRF51/NRF51822/rng_lld.h - * @brief NRF51 RNG subsystem low level driver header. - * - * @addtogroup RNG - * @{ - */ - -#ifndef HAL_RNG_LLD_H -#define HAL_RNG_LLD_H - -#if (HAL_USE_RNG == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief RNG1 driver enable switch. - * @details If set to @p TRUE the support for RNG1 is included. - * @note The default is @p FALSE. - */ -#if !defined(NRF51_RNG_USE_RNG1) || defined(__DOXYGEN__) -#define NRF51_RNG_USE_RNG1 FALSE -#endif - -/** - * @brief RNG1 driver enable switch. - * @details If set to @p TRUE the support for RNG1 is included. - * @note The default is @p FALSE. - */ -#if !defined(NRF51_RNG_USE_RNG1) || defined(__DOXYGEN__) -#define NRF51_RNG_USE_POWER_ON_WRITE FALSE -#endif - -/** - * @brief RNG1 interrupt priority level setting. - */ -#if !defined(NRF51_RNG_RNG1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define NRF51_RNG_RNG1_IRQ_PRIORITY 3 -#endif - - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if NRF51_RNG_USE_RNG1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_RNG_RNG1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to RNG1" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an RNG driver. - */ -typedef struct RNGDriver RNGDriver; - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /* End of the mandatory fields.*/ - /** - * @brief Activate the digital error correction - * - * @details A digital corrector algorithm is employed to remove any - * bias toward '1' or '0'. Disabling it offers a substantial - * speed advantage, but may result in a statistical distribution - * that is not perfectly uniform. - * - * @note On average, it take 167µs to get a byte without digitial - * error correction and 677µs with, but no garantee is made - * on the necessary time to generate one byte. - */ - uint8_t digital_error_correction:1; - /** - * @brief Only power the RNG device when requeting random bytes - * - * @details Device will not be powered when started/stopped - * but only when writint bytes. - */ - uint8_t power_on_write:1; -} RNGConfig; - - -/** - * @brief Structure representing an RNG driver. - */ -struct RNGDriver { - /** - * @brief Driver state. - */ - rngstate_t state; - /** - * @brief Current configuration data. - */ - const RNGConfig *config; -#if RNG_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* RNG_USE_MUTUAL_EXCLUSION */ - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the RNGx registers block. - */ - NRF_RNG_Type *rng; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if NRF51_RNG_USE_RNG1 && !defined(__DOXYGEN__) -extern RNGDriver RNGD1; -#endif /* NRF51_RNG_USE_RNG1 */ - -#ifdef __cplusplus -extern "C" { -#endif - void rng_lld_init(void); - void rng_lld_start(RNGDriver *rngp); - void rng_lld_stop(RNGDriver *rngp); - msg_t rng_lld_write(RNGDriver *rngp, uint8_t *buf, size_t n, - systime_t timeout); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_RNG */ - -#endif /* HAL_RNG_LLD_H */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_serial_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_serial_lld.c deleted file mode 100644 index 029c5da..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_serial_lld.c +++ /dev/null @@ -1,325 +0,0 @@ -/*
- Copyright (C) 2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file serial_lld.c
- * @brief NRF51822 serial subsystem low level driver source.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "hal.h"
-
-#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__)
-
-#include "nrf51.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief USART1 serial driver identifier.*/
-#if (NRF51_SERIAL_USE_UART0 == TRUE) || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Driver default configuration.
- */
-static const SerialConfig default_config = {
- .speed = 38400,
- .tx_pad = NRF51_SERIAL_PAD_DISCONNECTED,
- .rx_pad = NRF51_SERIAL_PAD_DISCONNECTED,
-#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
- .rts_pad = NRF51_SERIAL_PAD_DISCONNECTED,
- .cts_pad = NRF51_SERIAL_PAD_DISCONNECTED,
-#endif
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*
- * @brief Maps a baudrate speed to a BAUDRATE register value.
- */
-
-/**
- * @brief Common UART configuration.
- *
- */
-static void configure_uart(const SerialConfig *config)
-{
- uint32_t speed = UART_BAUDRATE_BAUDRATE_Baud250000;
-
- switch (config->speed) {
- case 1200: speed = UART_BAUDRATE_BAUDRATE_Baud1200; break;
- case 2400: speed = UART_BAUDRATE_BAUDRATE_Baud2400; break;
- case 4800: speed = UART_BAUDRATE_BAUDRATE_Baud4800; break;
- case 9600: speed = UART_BAUDRATE_BAUDRATE_Baud9600; break;
- case 14400: speed = UART_BAUDRATE_BAUDRATE_Baud14400; break;
- case 19200: speed = UART_BAUDRATE_BAUDRATE_Baud19200; break;
- case 28800: speed = UART_BAUDRATE_BAUDRATE_Baud28800; break;
- case 38400: speed = UART_BAUDRATE_BAUDRATE_Baud38400; break;
- case 57600: speed = UART_BAUDRATE_BAUDRATE_Baud57600; break;
- case 76800: speed = UART_BAUDRATE_BAUDRATE_Baud76800; break;
- case 115200: speed = UART_BAUDRATE_BAUDRATE_Baud115200; break;
- case 230400: speed = UART_BAUDRATE_BAUDRATE_Baud230400; break;
- case 250000: speed = UART_BAUDRATE_BAUDRATE_Baud250000; break;
- case 460800: speed = UART_BAUDRATE_BAUDRATE_Baud460800; break;
- case 921600: speed = UART_BAUDRATE_BAUDRATE_Baud921600; break;
- case 1000000: speed = UART_BAUDRATE_BAUDRATE_Baud1M; break;
- default: osalDbgAssert(0, "invalid baudrate"); break;
- };
-
- /* Configure PINs mode */
- if (config->tx_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
- palSetPadMode(IOPORT1, config->tx_pad, PAL_MODE_OUTPUT_PUSHPULL);
- }
- if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
- palSetPadMode(IOPORT1, config->rx_pad, PAL_MODE_INPUT);
- }
-#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
- if (config->rts_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
- palSetPadMode(IOPORT1, config->rts_pad, PAL_MODE_OUTPUT_PUSHPULL);
- }
- if (config->cts_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
- palSetPadMode(IOPORT1, config->cts_pad, PAL_MODE_INPUT);
- }
-#endif
-
- /* Select PINs used by UART */
- NRF_UART0->PSELTXD = config->tx_pad;
- NRF_UART0->PSELRXD = config->rx_pad;
-#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
- NRF_UART0->PSELRTS = config->rts_pad;
- NRF_UART0->PSELCTS = config->cts_pad;
-#else
- NRF_UART0->PSELRTS = NRF51_SERIAL_PAD_DISCONNECTED;
- NRF_UART0->PSELCTS = NRF51_SERIAL_PAD_DISCONNECTED;
-#endif
-
- /* Set baud rate */
- NRF_UART0->BAUDRATE = speed;
-
- /* Set config */
- NRF_UART0->CONFIG = (UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos);
-
- /* Adjust flow control */
-#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
- if ((config->rts_pad < TOTAL_GPIO_PADS) ||
- (config->cts_pad < TOTAL_GPIO_PADS)) {
- NRF_UART0->CONFIG |= UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos;
- } else {
- NRF_UART0->CONFIG &= ~(UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos);
- }
-#else
- NRF_UART0->CONFIG &= ~(UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos);
-#endif
-
- /* Enable UART and clear events */
- NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Enabled;
- NRF_UART0->EVENTS_RXDRDY = 0;
- NRF_UART0->EVENTS_TXDRDY = 0;
-
-
- if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
- while (NRF_UART0->EVENTS_RXDRDY != 0) {
- (void)NRF_UART0->RXD;
- }
- }
-}
-
-
-/**
- * @brief Driver output notification.
- */
-#if NRF51_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(io_queue_t *qp)
-{
- SerialDriver *sdp = &SD1;
-
- (void)qp;
-
- if (NRF_UART0->PSELTXD == NRF51_SERIAL_PAD_DISCONNECTED)
- return;
-
- if (!sdp->tx_busy) {
- msg_t b = oqGetI(&sdp->oqueue);
-
- if (b < Q_OK) {
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- NRF_UART0->TASKS_STOPTX = 1;
- return;
- }
- sdp->tx_busy = 1;
- NRF_UART0->TASKS_STARTTX = 1;
- NRF_UART0->TXD = b;
- }
-}
-#endif
-
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if NRF51_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-OSAL_IRQ_HANDLER(Vector48) {
-
- OSAL_IRQ_PROLOGUE();
-
- SerialDriver *sdp = &SD1;
- uint32_t isr = NRF_UART0->INTENSET;
-
- if ((NRF_UART0->EVENTS_RXDRDY != 0) && (isr & UART_INTENSET_RXDRDY_Msk)) {
- // Clear UART RX event flag
- NRF_UART0->EVENTS_RXDRDY = 0;
-
- osalSysLockFromISR();
- if (iqIsEmptyI(&sdp->iqueue))
- chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
- if (iqPutI(&sdp->iqueue, NRF_UART0->RXD) < Q_OK)
- chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
- osalSysUnlockFromISR();
- }
-
- if ((NRF_UART0->EVENTS_TXDRDY != 0) && (isr & UART_INTENSET_TXDRDY_Msk)) {
- msg_t b;
-
- // Clear UART TX event flag.
- NRF_UART0->EVENTS_TXDRDY = 0;
-
- osalSysLockFromISR();
- b = oqGetI(&sdp->oqueue);
- osalSysUnlockFromISR();
-
- if (b < Q_OK) {
- osalSysLockFromISR();
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- osalSysUnlockFromISR();
- NRF_UART0->TASKS_STOPTX = 1;
- sdp->tx_busy = 0;
- } else {
- sdp->tx_busy = 1;
- NRF_UART0->TXD = b;
- }
- }
-
- /* TODO: Error handling for EVENTS_ERROR */
- if ((NRF_UART0->EVENTS_ERROR != 0) && (isr & UART_INTENSET_ERROR_Msk)) {
- // Clear UART ERROR event flag.
- NRF_UART0->EVENTS_ERROR = 0;
- }
-
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if NRF51_SERIAL_USE_UART0 == TRUE
- sdObjectInit(&SD1, NULL, notify1);
-#endif
-}
-
-/**
- * @brief Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration.
- * If this parameter is set to @p NULL then a default
- * configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
- if (config == NULL)
- config = &default_config;
-
- osalDbgAssert(
- (config->rx_pad < TOTAL_GPIO_PADS) || (config->tx_pad < TOTAL_GPIO_PADS),
- "must configure at least an RX or TX pad");
-
- if (sdp->state == SD_STOP) {
-
-#if NRF51_SERIAL_USE_UART0 == TRUE
- if (sdp == &SD1) {
- configure_uart(config);
-
- // Enable UART interrupt
- NRF_UART0->INTENCLR = (uint32_t)-1;
- NRF_UART0->INTENSET = UART_INTENSET_ERROR_Msk;
- if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED)
- NRF_UART0->INTENSET |= UART_INTENSET_RXDRDY_Msk;
- if (config->tx_pad != NRF51_SERIAL_PAD_DISCONNECTED)
- NRF_UART0->INTENSET |= UART_INTENSET_TXDRDY_Msk;
-
- nvicEnableVector(UART0_IRQn, NRF51_SERIAL_UART0_PRIORITY);
-
- if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED)
- NRF_UART0->TASKS_STARTRX = 1;
- }
-#endif
-
- }
-}
-
-/**
- * @brief Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- * interrupt vector.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
- if (sdp->state == SD_READY) {
-
-#if NRF51_SERIAL_USE_UART0 == TRUE
- if (&SD1 == sdp) {
- nvicDisableVector(UART0_IRQn);
- NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Disabled;
- }
-#endif
- }
-}
-
-#endif /* HAL_USE_SERIAL == TRUE */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_serial_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_serial_lld.h deleted file mode 100644 index 79955b1..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_serial_lld.h +++ /dev/null @@ -1,155 +0,0 @@ -/*
- Copyright (C) 2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file serial_lld.h
- * @brief NRF51822 serial subsystem low level driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef HAL_SERIAL_LLD_H
-#define HAL_SERIAL_LLD_H
-
-#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name PLATFORM configuration options
- * @{
- */
-/**
- * @brief SD flow control enable switch.
- * @details If set to @p TRUE the support for hardware flow control
- * is included.
- * @note The default is @p FALSE.
- */
-#if !defined(NRF51_SERIAL_USE_HWFLOWCTRL) || defined(__DOXYGEN__)
-#define NRF51_SERIAL_USE_HWFLOWCTRL FALSE
-#endif
-
-/**
- * @brief SD1 driver enable switch.
- * @details If set to @p TRUE the support for SD1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(NRF51_SERIAL_USE_UART0) || defined(__DOXYGEN__)
-#define NRF51_SERIAL_USE_UART0 FALSE
-#endif
-
-/**
- * @brief UART0 interrupt priority level setting.
- */
-#if !defined(NRF51_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_SERIAL_UART0_PRIORITY 3
-#endif
-
-/* Value indicating that no pad is connected to this UART register. */
-#define NRF51_SERIAL_PAD_DISCONNECTED 0xFFFFFFFFU
-#define NRF51_SERIAL_INVALID_BAUDRATE 0xFFFFFFFFU
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if NRF51_SERIAL_USE_UART0 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SERIAL_UART0_PRIORITY)
-#error "Invalid IRQ priority assigned to UART0"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief NRF51 Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- * in order to configure and start a serial driver operations.
- * @note This structure content is architecture dependent, each driver
- * implementation defines its own version and the custom static
- * initializers.
- */
-typedef struct {
- /**
- * @brief Bit rate.
- */
- uint32_t speed;
- /* End of the mandatory fields.*/
- uint32_t tx_pad;
- uint32_t rx_pad;
-#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
- uint32_t rts_pad;
- uint32_t cts_pad;
-#endif
-} SerialConfig;
-
-/**
- * @brief @p SerialDriver specific data.
- */
-#define _serial_driver_data \
- _base_asynchronous_channel_data \
- /* Driver state.*/ \
- sdstate_t state; \
- /* Input queue.*/ \
- input_queue_t iqueue; \
- /* Output queue.*/ \
- output_queue_t oqueue; \
- /* Input circular buffer.*/ \
- uint8_t ib[SERIAL_BUFFERS_SIZE]; \
- /* Output circular buffer.*/ \
- uint8_t ob[SERIAL_BUFFERS_SIZE]; \
- /* 1 if port is busy transmitting, 0 otherwise. */ \
- uint8_t tx_busy; \
- /* End of the mandatory fields.*/ \
- thread_t *thread;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if (NRF51_SERIAL_USE_UART0 == TRUE) && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void sd_lld_init(void);
- void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
- void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL == TRUE */
-
-#endif /* HAL_SERIAL_LLD_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_spi_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_spi_lld.c deleted file mode 100644 index 7a70c13..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_spi_lld.c +++ /dev/null @@ -1,374 +0,0 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51822/spi_lld.c
- * @brief NRF51822 low level SPI driver code.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-#if NRF51_SPI_USE_SPI0 || defined(__DOXYGEN__)
-/** @brief SPI1 driver identifier.*/
-SPIDriver SPID1;
-#endif
-
-#if NRF51_SPI_USE_SPI1 || defined(__DOXYGEN__)
-/** @brief SPI2 driver identifier.*/
-SPIDriver SPID2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Preloads the transmit FIFO.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- */
-static void port_fifo_preload(SPIDriver *spip) {
- NRF_SPI_Type *port = spip->port;
-
- if (spip->txcnt > 0 && spip->txptr != NULL)
- port->TXD = *(uint8_t *)spip->txptr++;
- else
- port->TXD = 0xFF;
- spip->txcnt--;
-}
-
-#if defined(__GNUC__)
-__attribute__((noinline))
-#endif
-/**
- * @brief Common IRQ handler.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- */
-static void serve_interrupt(SPIDriver *spip) {
- NRF_SPI_Type *port = spip->port;
-
- // Clear SPI READY event flag
- port->EVENTS_READY = 0;
-
- if (spip->rxptr != NULL) {
- *(uint8_t *)spip->rxptr++ = port->RXD;
- }
- else {
- (void)port->RXD;
- if (--spip->rxcnt == 0) {
- osalDbgAssert(spip->txcnt == 0, "counter out of synch");
- /* Stops the IRQ sources.*/
- spip->port->INTENCLR = (SPI_INTENCLR_READY_Clear << SPI_INTENCLR_READY_Pos);
- /* Portable SPI ISR code defined in the high level driver, note, it is
- a macro.*/
- _spi_isr_code(spip);
- return;
- }
- }
- if (spip->txcnt > 0) {
- port_fifo_preload(spip);
- }
- else {
- spip->port->INTENCLR = (SPI_INTENCLR_READY_Clear << SPI_INTENCLR_READY_Pos);
- /* Portable SPI ISR code defined in the high level driver, note, it is
- a macro.*/
- _spi_isr_code(spip);
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if NRF51_SPI_USE_SPI0 || defined(__DOXYGEN__)
-/**
- * @brief SPI0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector4C) {
-
- CH_IRQ_PROLOGUE();
- serve_interrupt(&SPID1);
- CH_IRQ_EPILOGUE();
-}
-#endif
-#if NRF51_SPI_USE_SPI1 || defined(__DOXYGEN__)
-/**
- * @brief SPI1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(Vector50) {
-
- CH_IRQ_PROLOGUE();
- serve_interrupt(&SPID2);
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if NRF51_SPI_USE_SPI0
- spiObjectInit(&SPID1);
- SPID1.port = NRF_SPI0;
-#endif
-#if NRF51_SPI_USE_SPI1
- spiObjectInit(&SPID2);
- SPID2.port = NRF_SPI1;
-#endif
-}
-
-/**
- * @brief Configures and activates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
- uint32_t config;
-
- if (spip->state == SPI_STOP) {
-#if NRF51_SPI_USE_SPI0
- if (&SPID1 == spip)
- nvicEnableVector(SPI0_TWI0_IRQn, NRF51_SPI_SPI0_IRQ_PRIORITY);
-#endif
-#if NRF51_SPI_USE_SPI1
- if (&SPID2 == spip)
- nvicEnableVector(SPI1_TWI1_IRQn, NRF51_SPI_SPI1_IRQ_PRIORITY);
-#endif
- }
-
- config = spip->config->lsbfirst ?
- (SPI_CONFIG_ORDER_LsbFirst << SPI_CONFIG_ORDER_Pos) :
- (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos);
-
- switch (spip->config->mode) {
- case 1:
- config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
- config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
- break;
- case 2:
- config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
- config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
- break;
- case 3:
- config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
- config |= (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos);
- break;
- default:
- config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
- config |= (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos);
- break;
- }
-
- /* Configuration.*/
- spip->port->CONFIG = config;
- spip->port->PSELSCK = spip->config->sckpad;
- spip->port->PSELMOSI = spip->config->mosipad;
- spip->port->PSELMISO = spip->config->misopad;
- spip->port->FREQUENCY = spip->config->freq;
- spip->port->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
-
- /* clear events flag */
- spip->port->EVENTS_READY = 0;
-}
-
-/**
- * @brief Deactivates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
- if (spip->state != SPI_STOP) {
- spip->port->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
- spip->port->INTENCLR = (SPI_INTENCLR_READY_Clear << SPI_INTENCLR_READY_Pos);
-#if NRF51_SPI_USE_SPI0
- if (&SPID1 == spip)
- nvicDisableVector(SPI0_TWI0_IRQn);
-#endif
-#if NRF51_SPI_USE_SPI1
- if (&SPID2 == spip)
- nvicDisableVector(SPI1_TWI1_IRQn);
-#endif
- }
-}
-
-/**
- * @brief Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
- palClearPad(IOPORT1, spip->config->sspad);
-}
-
-/**
- * @brief Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
- palSetPad(IOPORT1, spip->config->sspad);
-}
-
-/**
- * @brief Ignores data on the SPI bus.
- * @details This function transmits a series of idle words on the SPI bus and
- * ignores the received data. This function can be invoked even
- * when a slave select signal has not been yet asserted.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
- spip->rxptr = NULL;
- spip->txptr = NULL;
- spip->rxcnt = spip->txcnt = n;
- port_fifo_preload(spip);
- spip->port->INTENSET = (SPI_INTENCLR_READY_Enabled << SPI_INTENCLR_READY_Pos);
-}
-
-/**
- * @brief Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- * operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf) {
-
- spip->rxptr = rxbuf;
- spip->txptr = txbuf;
- spip->rxcnt = spip->txcnt = n;
- port_fifo_preload(spip);
- spip->port->INTENSET = (SPI_INTENCLR_READY_Enabled << SPI_INTENCLR_READY_Pos);
-}
-
-/**
- * @brief Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to send
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
- spip->rxptr = NULL;
- spip->txptr = txbuf;
- spip->rxcnt = spip->txcnt = n;
- port_fifo_preload(spip);
- spip->port->INTENSET = (SPI_INTENCLR_READY_Enabled << SPI_INTENCLR_READY_Pos);
-}
-
-/**
- * @brief Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to receive
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
- spip->rxptr = rxbuf;
- spip->txptr = NULL;
- spip->rxcnt = spip->txcnt = n;
- port_fifo_preload(spip);
- spip->port->INTENSET = (SPI_INTENCLR_READY_Enabled << SPI_INTENCLR_READY_Pos);
-}
-
-/**
- * @brief Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- * synchronization method. This function is useful when exchanging
- * small amount of data on high speed channels, usually in this
- * situation is much more efficient just wait for completion using
- * polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] frame the data frame to send over the SPI bus
- * @return The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
- spip->port->TXD = (uint8_t)frame;
- while (spip->port->EVENTS_READY == 0)
- ;
- spip->port->EVENTS_READY = 0;
- return spip->port->RXD;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_spi_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_spi_lld.h deleted file mode 100644 index 4d1c452..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_spi_lld.h +++ /dev/null @@ -1,238 +0,0 @@ -/*
- Copyright (C) 2015 Stephen Caudle
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51822/spi_lld.h
- * @brief NRF51822 low level SPI driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef HAL_SPI_LLD_H
-#define HAL_SPI_LLD_H
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @brief SPI0 interrupt priority level setting.
- */
-#if !defined(NRF51_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_SPI_SPI0_IRQ_PRIORITY 3
-#endif
-
-/**
- * @brief SPI1 interrupt priority level setting.
- */
-#if !defined(NRF51_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NRF51_SPI_SPI1_IRQ_PRIORITY 3
-#endif
-
-/**
- * @brief Overflow error hook.
- * @details The default action is to stop the system.
- */
-#if !defined(NRF51_SPI_SPI_ERROR_HOOK) || defined(__DOXYGEN__)
-#define NRF51_SPI_SPI_ERROR_HOOK() chSysHalt()
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !NRF51_SPI_USE_SPI0 && !NRF51_SPI_USE_SPI1
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-#if NRF51_SPI_USE_SPI0 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SPI_SPI0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI0"
-#endif
-
-#if NRF51_SPI_USE_SPI1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SPI_SPI1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to SPI1"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief SPI notification callback type.
- *
- * @param[in] spip pointer to the @p SPIDriver object triggering the
- * callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief SPI frequency
- */
-typedef enum {
- NRF51_SPI_FREQ_125KBPS = (SPI_FREQUENCY_FREQUENCY_K125 << SPI_FREQUENCY_FREQUENCY_Pos),
- NRF51_SPI_FREQ_250KBPS = (SPI_FREQUENCY_FREQUENCY_K250 << SPI_FREQUENCY_FREQUENCY_Pos),
- NRF51_SPI_FREQ_500KBPS = (SPI_FREQUENCY_FREQUENCY_K500 << SPI_FREQUENCY_FREQUENCY_Pos),
- NRF51_SPI_FREQ_1MBPS = (SPI_FREQUENCY_FREQUENCY_M1 << SPI_FREQUENCY_FREQUENCY_Pos),
- NRF51_SPI_FREQ_2MBPS = (SPI_FREQUENCY_FREQUENCY_M2 << SPI_FREQUENCY_FREQUENCY_Pos),
- NRF51_SPI_FREQ_4MBPS = (SPI_FREQUENCY_FREQUENCY_M4 << SPI_FREQUENCY_FREQUENCY_Pos),
- NRF51_SPI_FREQ_8MBPS = (SPI_FREQUENCY_FREQUENCY_M8 << SPI_FREQUENCY_FREQUENCY_Pos),
-} spifreq_t;
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
- /**
- * @brief Operation complete callback or @p NULL.
- */
- spicallback_t end_cb;
- /**
- * @brief The frequency of the SPI peripheral
- */
- spifreq_t freq;
- /**
- * @brief The SCK pad
- */
- uint16_t sckpad;
- /**
- * @brief The MOSI pad
- */
- uint16_t mosipad;
- /**
- * @brief The MOSI pad
- */
- uint16_t misopad;
- /* End of the mandatory fields.*/
- /**
- * @brief The chip select line pad number.
- */
- uint16_t sspad;
- /**
- * @brief Shift out least significant bit first
- */
- uint8_t lsbfirst;
- /**
- * @brief SPI mode
- */
- uint8_t mode;
-} SPIConfig;
-
-/**
- * @brief Structure representing a SPI driver.
- */
-struct SPIDriver {
- /**
- * @brief Driver state.
- */
- spistate_t state;
- /**
- * @brief Current configuration data.
- */
- const SPIConfig *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- thread_reference_t thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the bus.
- */
- mutex_t mutex;
-#elif CH_CFG_USE_SEMAPHORES
- semaphore_t semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
- SPI_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the SPI port.
- */
- NRF_SPI_Type *port;
- /**
- * @brief Number of bytes yet to be received.
- */
- uint32_t rxcnt;
- /**
- * @brief Receive pointer or @p NULL.
- */
- void *rxptr;
- /**
- * @brief Number of bytes yet to be transmitted.
- */
- uint32_t txcnt;
- /**
- * @brief Transmit pointer or @p NULL.
- */
- const void *txptr;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if NRF51_SPI_USE_SPI0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-#if NRF51_SPI_USE_SPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void spi_lld_init(void);
- void spi_lld_start(SPIDriver *spip);
- void spi_lld_stop(SPIDriver *spip);
- void spi_lld_select(SPIDriver *spip);
- void spi_lld_unselect(SPIDriver *spip);
- void spi_lld_ignore(SPIDriver *spip, size_t n);
- void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf);
- void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
- void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
- uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* HAL_SPI_LLD_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_st_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_st_lld.c deleted file mode 100644 index 181bc06..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_st_lld.c +++ /dev/null @@ -1,294 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2015 Fabio Utzig
- 2016 Stephane D'Alu
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file st_lld.c
- * @brief NRF51822 ST subsystem low level driver source.
- *
- * @addtogroup ST
- * @{
- */
-
-#include "hal.h"
-
-#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
-#if NRF51_ST_USE_RTC0 == TRUE
-/**
- * @brief System Timer vector (RTC0)
- * @details This interrupt is used for system tick in periodic mode
- * if selected with NRF51_ST_USE_RTC0
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector6C) {
-
- OSAL_IRQ_PROLOGUE();
-
- NRF_RTC0->EVENTS_TICK = 0;
-
- osalSysLockFromISR();
- osalOsTimerHandlerI();
- osalSysUnlockFromISR();
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if NRF51_ST_USE_RTC1 == TRUE
-/**
- * @brief System Timer vector (RTC1)
- * @details This interrupt is used for system tick in periodic mode
- * if selected with NRF51_ST_USE_RTC1
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector84) {
-
- OSAL_IRQ_PROLOGUE();
-
- NRF_RTC1->EVENTS_TICK = 0;
-
- osalSysLockFromISR();
- osalOsTimerHandlerI();
- osalSysUnlockFromISR();
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if NRF51_ST_USE_TIMER0 == TRUE
-/**
- * @brief System Timer vector. (TIMER0)
- * @details This interrupt is used for system tick in periodic mode
- * if selected with NRF51_ST_USE_TIMER0
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector60) {
-
- OSAL_IRQ_PROLOGUE();
-
- /* Clear timer compare event */
- if (NRF_TIMER0->EVENTS_COMPARE[0] != 0)
- NRF_TIMER0->EVENTS_COMPARE[0] = 0;
-
- osalSysLockFromISR();
- osalOsTimerHandlerI();
- osalSysUnlockFromISR();
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
-
-#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)
-#if NRF51_ST_USE_RTC0 == TRUE
-/**
- * @brief System Timer vector (RTC0)
- * @details This interrupt is used for freerunning mode (tick-less)
- * if selected with NRF51_ST_USE_RTC0
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector6C) {
-
- OSAL_IRQ_PROLOGUE();
-
- if (NRF_RTC0->EVENTS_COMPARE[0]) {
- NRF_RTC0->EVENTS_COMPARE[0] = 0;
-
- osalSysLockFromISR();
- osalOsTimerHandlerI();
- osalSysUnlockFromISR();
- }
-
-#if OSAL_ST_RESOLUTION == 16
- if (NRF_RTC0->EVENTS_COMPARE[1]) {
- NRF_RTC0->EVENTS_COMPARE[1] = 0;
- NRF_RTC0->TASKS_CLEAR = 1;
- }
-#endif
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if NRF51_ST_USE_RTC1 == TRUE
-/**
- * @brief System Timer vector (RTC1)
- * @details This interrupt is used for freerunning mode (tick-less)
- * if selected with NRF51_ST_USE_RTC1
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector84) {
-
- OSAL_IRQ_PROLOGUE();
-
- if (NRF_RTC1->EVENTS_COMPARE[0]) {
- NRF_RTC1->EVENTS_COMPARE[0] = 0;
-
- osalSysLockFromISR();
- osalOsTimerHandlerI();
- osalSysUnlockFromISR();
- }
-
-#if OSAL_ST_RESOLUTION == 16
- if (NRF_RTC1->EVENTS_COMPARE[1]) {
- NRF_RTC1->EVENTS_COMPARE[1] = 0;
- NRF_RTC1->TASKS_CLEAR = 1;
- }
-#endif
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ST driver initialization.
- *
- * @notapi
- */
-void st_lld_init(void) {
-#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
-
-#if NRF51_ST_USE_RTC0 == TRUE
- /* Using RTC with prescaler */
- NRF_RTC0->TASKS_STOP = 1;
- NRF_RTC0->PRESCALER = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
- NRF_RTC0->EVTENCLR = RTC_EVTENSET_COMPARE0_Msk;
- NRF_RTC0->EVENTS_COMPARE[0] = 0;
- NRF_RTC0->INTENSET = RTC_INTENSET_COMPARE0_Msk;
-#if OSAL_ST_RESOLUTION == 16
- NRF_RTC0->CC[1] = 0x10000; /* 2^16 */
- NRF_RTC0->EVENTS_COMPARE[1] = 0;
- NRF_RTC0->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
- NRF_RTC0->INTENSET = RTC_INTENSET_COMPARE1_Msk;
-#endif
- NRF_RTC0->TASKS_CLEAR = 1;
-
- /* Start timer */
- nvicEnableVector(RTC0_IRQn, NRF51_ST_PRIORITY);
- NRF_RTC0->TASKS_START = 1;
-#endif /* NRF51_ST_USE_RTC0 == TRUE */
-
-#if NRF51_ST_USE_RTC1 == TRUE
- /* Using RTC with prescaler */
- NRF_RTC1->TASKS_STOP = 1;
- NRF_RTC1->PRESCALER = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
- NRF_RTC1->EVTENCLR = RTC_EVTENSET_COMPARE0_Msk;
- NRF_RTC1->EVENTS_COMPARE[0] = 0;
- NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE0_Msk;
-#if OSAL_ST_RESOLUTION == 16
- NRF_RTC1->CC[1] = 0x10000; /* 2^16 */
- NRF_RTC1->EVENTS_COMPARE[1] = 0;
- NRF_RTC1->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
- NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE1_Msk;
-#endif
- NRF_RTC1->TASKS_CLEAR = 1;
-
- /* Start timer */
- nvicEnableVector(RTC1_IRQn, NRF51_ST_PRIORITY);
- NRF_RTC1->TASKS_START = 1;
-#endif /* NRF51_ST_USE_RTC1 == TRUE */
-
-#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
-
-#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
-
-#if NRF51_ST_USE_RTC0 == TRUE
- /* Using RTC with prescaler */
- NRF_RTC0->TASKS_STOP = 1;
- NRF_RTC0->PRESCALER = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
- NRF_RTC0->INTENSET = RTC_INTENSET_TICK_Msk;
-
- /* Start timer */
- nvicEnableVector(RTC0_IRQn, NRF51_ST_PRIORITY);
- NRF_RTC0->TASKS_START = 1;
-#endif /* NRF51_ST_USE_RTC0 == TRUE */
-
-#if NRF51_ST_USE_RTC1 == TRUE
- /* Using RTC with prescaler */
- NRF_RTC1->TASKS_STOP = 1;
- NRF_RTC1->PRESCALER = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
- NRF_RTC1->INTENSET = RTC_INTENSET_TICK_Msk;
-
- /* Start timer */
- nvicEnableVector(RTC1_IRQn, NRF51_ST_PRIORITY);
- NRF_RTC1->TASKS_START = 1;
-#endif /* NRF51_ST_USE_RTC1 == TRUE */
-
-#if NRF51_ST_USE_TIMER0 == TRUE
- NRF_TIMER0->TASKS_CLEAR = 1;
-
- /*
- * Using 32-bit mode with prescaler 16 configures this
- * timer with a 1MHz clock.
- */
- NRF_TIMER0->BITMODE = 3;
- NRF_TIMER0->PRESCALER = 4;
-
- /*
- * Configure timer 0 compare capture 0 to generate interrupt
- * and clear timer value when event is generated.
- */
- NRF_TIMER0->CC[0] = (1000000 / OSAL_ST_FREQUENCY) - 1;
- NRF_TIMER0->SHORTS = 1;
- NRF_TIMER0->INTENSET = 0x10000;
-
- /* Start timer */
- nvicEnableVector(TIMER0_IRQn, NRF51_ST_PRIORITY);
- NRF_TIMER0->TASKS_START = 1;
-#endif /* NRF51_ST_USE_TIMER0 == TRUE */
-
-#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
-}
-
-#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_st_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_st_lld.h deleted file mode 100644 index 8d12d2e..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_st_lld.h +++ /dev/null @@ -1,275 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2015 Fabio Utzig
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file st_lld.h
- * @brief NRF51822 ST subsystem low level driver header.
- * @details This header is designed to be include-able without having to
- * include other files from the HAL.
- *
- * @addtogroup ST
- * @{
- */
-
-#ifndef HAL_ST_LLD_H
-#define HAL_ST_LLD_H
-
-#include "halconf.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @brief Use RTC0 to generates system ticks
- */
-#if !defined(NRF51_ST_USE_RTC0) || defined(__DOXYGEN__)
-#if !defined(SOFTDEVICE_PRESENT)
-#define NRF51_ST_USE_RTC0 TRUE
-#else
-#define NRF51_ST_USE_RTC0 FALSE
-#endif
-#endif
-
-/**
- * @brief Use RTC1 to generates system ticks
- */
-#if !defined(NRF51_ST_USE_RTC1) || defined(__DOXYGEN__)
-#if !defined(SOFTDEVICE_PRESENT)
-#define NRF51_ST_USE_RTC1 FALSE
-#else
-#define NRF51_ST_USE_RTC1 TRUE
-#endif
-#endif
-
-/**
- * @brief Use TIMER0 to generates system ticks
- */
-#if !defined(NRF51_ST_USE_TIMER0) || defined(__DOXYGEN__)
-#define NRF51_ST_USE_TIMER0 FALSE
-#endif
-
-/**
- * @brief ST interrupt priority level setting.
- */
-#if !defined(NRF51_ST_PRIORITY) || defined(__DOXYGEN__)
-#if !defined(SOFTDEVICE_PRESENT)
-#define NRF51_ST_PRIORITY 1
-#else
-#define NRF51_ST_PRIORITY 1
-#endif
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if OSAL_ST_MODE != OSAL_ST_MODE_NONE
-#if (NRF51_ST_USE_TIMER0 == TRUE) && (NRF51_GPT_USE_TIMER0 == TRUE)
-#error "TIMER0 already used by GPT driver"
-#endif
-
-#if (NRF51_ST_USE_RTC0 == FALSE) && \
- (NRF51_ST_USE_RTC1 == FALSE) && \
- (NRF51_ST_USE_TIMER0 == FALSE)
-#error "One clock source is needed, enable one (RTC0, RTC1, or TIMER0)"
-#endif
-
-#if ((NRF51_ST_USE_RTC0 == TRUE ? 1 : 0) + \
- (NRF51_ST_USE_RTC1 == TRUE ? 1 : 0) + \
- (NRF51_ST_USE_TIMER0 == TRUE ? 1 : 0)) > 1
-#error "Only one clock source can be used (RTC0, RTC1, or TIMER0)"
-#endif
-
-#if defined(SOFTDEVICE_PRESENT)
-#if NRF51_ST_USE_RTC0 == TRUE
-#error "RTC0 cannot be used for system ticks when SOFTDEVICE present"
-#endif
-
-#if NRF51_ST_USE_TIMER0 == TRUE
-#error "TIMER0 cannot be used for system ticks when SOFTDEVICE present"
-#endif
-
-#if NRF51_ST_PRIORITY != 1
-#error "ST priority must be 1 when SOFTDEVICE present"
-#endif
-
-#endif /* defined(SOFTDEVICE_PRESENT) */
-#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
-
-#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
-#if defined(CH_CFG_ST_TIMEDELTA) && (CH_CFG_ST_TIMEDELTA < 5)
-#error "CH_CFG_ST_TIMEDELTA is too low"
-#endif
-#if NRF51_ST_USE_TIMER0 == TRUE
-#error "Freeruning (tick-less) mode not supported with TIMER, use RTC"
-#endif
-#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
-
-#if !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_ST_PRIORITY)
-#error "Invalid IRQ priority assigned to ST driver"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void st_lld_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-/*===========================================================================*/
-/* Driver inline functions. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the time counter value.
- *
- * @return The counter value.
- *
- * @notapi
- */
-static inline systime_t st_lld_get_counter(void) {
-#if NRF51_ST_USE_RTC0 == TRUE
- return (systime_t)NRF_RTC0->COUNTER;
-#endif
-#if NRF51_ST_USE_RTC1 == TRUE
- return (systime_t)NRF_RTC1->COUNTER;
-#endif
-#if NRF51_ST_USE_TIMER0 == TRUE
- return (systime_t)0;
-#endif
-}
-
-/**
- * @brief Starts the alarm.
- * @note Makes sure that no spurious alarms are triggered after
- * this call.
- *
- * @param[in] abstime the time to be set for the first alarm
- *
- * @notapi
- */
-static inline void st_lld_start_alarm(systime_t abstime) {
-#if NRF51_ST_USE_RTC0 == TRUE
- NRF_RTC0->CC[0] = abstime;
- NRF_RTC0->EVENTS_COMPARE[0] = 0;
- NRF_RTC0->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
-#endif
-#if NRF51_ST_USE_RTC1 == TRUE
- NRF_RTC1->CC[0] = abstime;
- NRF_RTC1->EVENTS_COMPARE[0] = 0;
- NRF_RTC1->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
-#endif
-#if NRF51_ST_USE_TIMER0 == TRUE
- (void)abstime;
-#endif
-}
-
-/**
- * @brief Stops the alarm interrupt.
- *
- * @notapi
- */
-static inline void st_lld_stop_alarm(void) {
-#if NRF51_ST_USE_RTC0 == TRUE
- NRF_RTC0->EVTENCLR = RTC_EVTENCLR_COMPARE0_Msk;
- NRF_RTC0->EVENTS_COMPARE[0] = 0;
-#endif
-#if NRF51_ST_USE_RTC1 == TRUE
- NRF_RTC1->EVTENCLR = RTC_EVTENCLR_COMPARE0_Msk;
- NRF_RTC1->EVENTS_COMPARE[0] = 0;
-#endif
-}
-
-/**
- * @brief Sets the alarm time.
- *
- * @param[in] abstime the time to be set for the next alarm
- *
- * @notapi
- */
-static inline void st_lld_set_alarm(systime_t abstime) {
-#if NRF51_ST_USE_RTC0 == TRUE
- NRF_RTC0->CC[0] = abstime;
-#endif
-#if NRF51_ST_USE_RTC1 == TRUE
- NRF_RTC1->CC[0] = abstime;
-#endif
-#if NRF51_ST_USE_TIMER0 == TRUE
- (void)abstime;
-#endif
-}
-
-/**
- * @brief Returns the current alarm time.
- *
- * @return The currently set alarm time.
- *
- * @notapi
- */
-static inline systime_t st_lld_get_alarm(void) {
-#if NRF51_ST_USE_RTC0 == TRUE
- return (systime_t)NRF_RTC0->CC[0];
-#endif
-#if NRF51_ST_USE_RTC1 == TRUE
- return (systime_t)NRF_RTC1->CC[0];
-#endif
-#if NRF51_ST_USE_TIMER0 == TRUE
- return (systime_t)0;
-#endif
-}
-
-/**
- * @brief Determines if the alarm is active.
- *
- * @return The alarm status.
- * @retval false if the alarm is not active.
- * @retval true is the alarm is active
- *
- * @notapi
- */
-static inline bool st_lld_is_alarm_active(void) {
-#if NRF51_ST_USE_RTC0 == TRUE
- return NRF_RTC0->EVTEN & RTC_EVTEN_COMPARE0_Msk;
-#endif
-#if NRF51_ST_USE_RTC1 == TRUE
- return NRF_RTC1->EVTEN & RTC_EVTEN_COMPARE0_Msk;
-#endif
-#if NRF51_ST_USE_TIMER0 == TRUE
- return false;
-#endif
-}
-
-#endif /* HAL_ST_LLD_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.c deleted file mode 100644 index 0ce37ee..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.c +++ /dev/null @@ -1,150 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Stephane D'Alu
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51822/wdg_lld.c
- * @brief WDG Driver subsystem low level driver source template.
- *
- * @addtogroup WDG
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_WDG || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#define RELOAD_REQUEST_VALUE 0x6E524635
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-WDGDriver WDGD1;
-
-/*===========================================================================*/
-/* Driver local variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if WDG_USE_TIMEOUT_CALLBACK == TRUE
-/**
- * @brief Watchdog vector.
- * @details This interrupt is used when watchdog timeout.
- *
- * @note Only 2 cycles at NRF51_LFCLK_FREQUENCY are available
- * to they good bye.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector84) {
-
- OSAL_IRQ_PROLOGUE();
- osalSysLockFromISR();
-
- /* Notify */
- if (WDGD1.config->callback)
- WDGD1.config->callback();
-
- /* Wait for reboot */
- while (1) { /* */ }
-
- osalSysUnlockFromISR();
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level WDG driver initialization.
- *
- * @notapi
- */
-void wdg_lld_init(void) {
- WDGD1.state = WDG_STOP;
- WDGD1.wdt = NRF_WDT;
-}
-
-/**
- * @brief Configures and activates the WDG peripheral.
- *
- * @note Once started there is no way out.
- *
- * @param[in] wdgp pointer to the @p WDGDriver object
- *
- * @notapi
- */
-void wdg_lld_start(WDGDriver *wdgp) {
-#if WDG_USE_TIMEOUT_CALLBACK == TRUE
- wdgp->wdt->INTENSET = WDT_INTENSET_TIMEOUT_Msk;
-#endif
-
- /* When to pause? (halt, sleep) */
- wdgp->wdt->CONFIG =
- (wdgp->config->flags.pause_on_sleep * WDT_CONFIG_SLEEP_Msk) |
- (wdgp->config->flags.pause_on_halt * WDT_CONFIG_HALT_Msk );
-
- /* Timeout in milli-seconds */
- uint64_t tout = (NRF51_LFCLK_FREQUENCY * wdgp->config->timeout_ms / 1000) - 1;
- osalDbgAssert(tout <= 0xFFFFFFFF, "watchdog timout value exceeded");
- wdgp->wdt->CRV = (uint32_t)tout;
-
- /* Reload request (using RR0) */
- wdgp->wdt->RREN = WDT_RREN_RR0_Msk;
-
- /* Say your prayers, little one. */
- wdgp->wdt->TASKS_START = 1;
-}
-
-/**
- * @brief Deactivates the WDG peripheral.
- *
- * @param[in] wdgp pointer to the @p WDGDriver object
- *
- * @api
- */
-void wdg_lld_stop(WDGDriver *wdgp) {
- (void)wdgp;
- osalDbgAssert(false, "WDG cannot be stopped once activated");
-}
-
-/**
- * @brief Reloads WDG's counter.
- *
- * @param[in] wdgp pointer to the @p WDGDriver object
- *
- * @notapi
- */
-void wdg_lld_reset(WDGDriver * wdgp) {
- wdgp->wdt->RR[0] = RELOAD_REQUEST_VALUE;
-}
-
-#endif /* HAL_USE_WDG */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.h deleted file mode 100644 index 8fea304..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.h +++ /dev/null @@ -1,127 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Stephane D'Alu
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file NRF51822/wdg_lld.h
- * @brief WDG Driver subsystem low level driver header template.
- *
- * @addtogroup WDG
- * @{
- */
-
-#ifndef HAL_WDG_LLD_H
-#define HAL_WDG_LLD_H
-
-#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-#define WDG_MAX_TIMEOUT_MS \
- ((uint32_t)(0xFFFFFFFFu * 1000 / NRF51_LFCLK_FREQUENCY))
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-
-/**
- * @brief WDG driver implement timeout callback.
- * @note The default is @p FALSE.
- */
-#if !defined(WDG_USE_TIMEOUT_CALLBACK) || defined(__DOXYGEN__)
-#define WDG_USE_TIMEOUT_CALLBACK FALSE
-#endif
-/** @} */
-
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a structure representing an WDG driver.
- */
-typedef struct WDGDriver WDGDriver;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- struct {
- uint8_t pause_on_sleep : 1;
- uint8_t pause_on_halt : 1;
- } flags;
- uint32_t timeout_ms;
-#if WDG_USE_TIMEOUT_CALLBACK == TRUE
- void (*callback)(void);
-#endif
-} WDGConfig;
-
-
-
-/**
- * @brief Structure representing an WDG driver.
- */
-struct WDGDriver {
- /**
- * @brief Driver state.
- */
- wdgstate_t state;
- /**
- * @brief Current configuration data.
- */
- const WDGConfig *config;
- /* End of the mandatory fields.*/
- NRF_WDT_Type *wdt;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-extern WDGDriver WDGD1;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void wdg_lld_init(void);
- void wdg_lld_start(WDGDriver *wdgp);
- void wdg_lld_stop(WDGDriver *wdgp);
- void wdg_lld_reset(WDGDriver *wdgp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_WDG == TRUE */
-
-#endif /* HAL_WDG_LLD_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/nrf51.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/nrf51.h deleted file mode 100644 index 1ed33d6..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/nrf51.h +++ /dev/null @@ -1,1315 +0,0 @@ -
-/****************************************************************************************************//**
- * @file nrf51.h
- *
- * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
- * nrf51 from Nordic Semiconductor.
- *
- * @version V522
- * @date 26. January 2015
- *
- * @note Generated with SVDConv V2.81d
- * from CMSIS SVD File 'nrf51.xml' Version 522,
- *
- * @par Copyright (c) 2013, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * * Neither the name of Nordic Semiconductor ASA nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- *******************************************************************************************************/
-
-
-
-/** @addtogroup Nordic Semiconductor
- * @{
- */
-
-/** @addtogroup nrf51
- * @{
- */
-
-#ifndef NRF51_H
-#define NRF51_H
-
-#include "nrf51_bitfields.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* ------------------------- Interrupt Number Definition ------------------------ */
-
-typedef enum {
-/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
- POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
- RADIO_IRQn = 1, /*!< 1 RADIO */
- UART0_IRQn = 2, /*!< 2 UART0 */
- SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
- SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
- GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
- ADC_IRQn = 7, /*!< 7 ADC */
- TIMER0_IRQn = 8, /*!< 8 TIMER0 */
- TIMER1_IRQn = 9, /*!< 9 TIMER1 */
- TIMER2_IRQn = 10, /*!< 10 TIMER2 */
- RTC0_IRQn = 11, /*!< 11 RTC0 */
- TEMP_IRQn = 12, /*!< 12 TEMP */
- RNG_IRQn = 13, /*!< 13 RNG */
- ECB_IRQn = 14, /*!< 14 ECB */
- CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
- WDT_IRQn = 16, /*!< 16 WDT */
- RTC1_IRQn = 17, /*!< 17 RTC1 */
- QDEC_IRQn = 18, /*!< 18 QDEC */
- LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
- SWI0_IRQn = 20, /*!< 20 SWI0 */
- SWI1_IRQn = 21, /*!< 21 SWI1 */
- SWI2_IRQn = 22, /*!< 22 SWI2 */
- SWI3_IRQn = 23, /*!< 23 SWI3 */
- SWI4_IRQn = 24, /*!< 24 SWI4 */
- SWI5_IRQn = 25 /*!< 25 SWI5 */
-} IRQn_Type;
-
-
-/** @addtogroup Configuration_of_CMSIS
- * @{
- */
-
-
-/* ================================================================================ */
-/* ================ Processor and Core Peripheral Section ================ */
-/* ================================================================================ */
-
-/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
-#define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
-#define __MPU_PRESENT 0 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
-
-
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/** @addtogroup Device_Peripheral_Registers
- * @{
- */
-
-
-/* ------------------- Start of section using anonymous unions ------------------ */
-#if defined(__CC_ARM)
- #pragma push
- #pragma anon_unions
-#elif defined(__ICCARM__)
- #pragma language=extended
-#elif defined(__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
-/* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
- #pragma warning 586
-#else
- #warning Not supported compiler type
-#endif
-
-
-typedef struct {
- __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
- __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
- __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
- __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
- __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
- __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
-} AMLI_RAMPRI_Type;
-
-typedef struct {
- __IO uint32_t SCK; /*!< Pin select for SCK. */
- __IO uint32_t MOSI; /*!< Pin select for MOSI. */
- __IO uint32_t MISO; /*!< Pin select for MISO. */
-} SPIM_PSEL_Type;
-
-typedef struct {
- __IO uint32_t PTR; /*!< Data pointer. */
- __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
- __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
-} SPIM_RXD_Type;
-
-typedef struct {
- __IO uint32_t PTR; /*!< Data pointer. */
- __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
- __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
-} SPIM_TXD_Type;
-
-typedef struct {
- __O uint32_t EN; /*!< Enable channel group. */
- __O uint32_t DIS; /*!< Disable channel group. */
-} PPI_TASKS_CHG_Type;
-
-typedef struct {
- __IO uint32_t EEP; /*!< Channel event end-point. */
- __IO uint32_t TEP; /*!< Channel task end-point. */
-} PPI_CH_Type;
-
-
-/* ================================================================================ */
-/* ================ POWER ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Power Control. (POWER)
- */
-
-typedef struct { /*!< POWER Structure */
- __I uint32_t RESERVED0[30];
- __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
- __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
- __I uint32_t RESERVED1[34];
- __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
- __I uint32_t RESERVED2[126];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __IO uint32_t RESETREAS; /*!< Reset reason. */
- __I uint32_t RESERVED4[9];
- __I uint32_t RAMSTATUS; /*!< Ram status register. */
- __I uint32_t RESERVED5[53];
- __O uint32_t SYSTEMOFF; /*!< System off register. */
- __I uint32_t RESERVED6[3];
- __IO uint32_t POFCON; /*!< Power failure configuration. */
- __I uint32_t RESERVED7[2];
- __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
- register. */
- __I uint32_t RESERVED8;
- __IO uint32_t RAMON; /*!< Ram on/off. */
- __I uint32_t RESERVED9[7];
- __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
- is a retained register. */
- __I uint32_t RESERVED10[3];
- __IO uint32_t RAMONB; /*!< Ram on/off. */
- __I uint32_t RESERVED11[8];
- __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
- __I uint32_t RESERVED12[291];
- __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
-} NRF_POWER_Type;
-
-
-/* ================================================================================ */
-/* ================ CLOCK ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Clock control. (CLOCK)
- */
-
-typedef struct { /*!< CLOCK Structure */
- __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
- __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
- __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
- __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
- __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
- __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
- __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
- __I uint32_t RESERVED0[57];
- __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
- __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
- __I uint32_t RESERVED1;
- __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
- __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
- __I uint32_t RESERVED2[124];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[63];
- __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
- __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
- __I uint32_t RESERVED4;
- __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
- __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
- __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
- triggered. */
- __I uint32_t RESERVED5[62];
- __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
- __I uint32_t RESERVED6[7];
- __IO uint32_t CTIV; /*!< Calibration timer interval. */
- __I uint32_t RESERVED7[5];
- __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
-} NRF_CLOCK_Type;
-
-
-/* ================================================================================ */
-/* ================ MPU ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Memory Protection Unit. (MPU)
- */
-
-typedef struct { /*!< MPU Structure */
- __I uint32_t RESERVED0[330];
- __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
- __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
- __I uint32_t RESERVED1[52];
- __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
- __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
- __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
- __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
-} NRF_MPU_Type;
-
-
-/* ================================================================================ */
-/* ================ PU ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Patch unit. (PU)
- */
-
-typedef struct { /*!< PU Structure */
- __I uint32_t RESERVED0[448];
- __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
- __I uint32_t RESERVED1[24];
- __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
- __I uint32_t RESERVED2[24];
- __IO uint32_t PATCHEN; /*!< Patch enable register. */
- __IO uint32_t PATCHENSET; /*!< Patch enable register. */
- __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
-} NRF_PU_Type;
-
-
-/* ================================================================================ */
-/* ================ AMLI ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief AHB Multi-Layer Interface. (AMLI)
- */
-
-typedef struct { /*!< AMLI Structure */
- __I uint32_t RESERVED0[896];
- AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
-} NRF_AMLI_Type;
-
-
-/* ================================================================================ */
-/* ================ RADIO ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief The radio. (RADIO)
- */
-
-typedef struct { /*!< RADIO Structure */
- __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
- __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
- __O uint32_t TASKS_START; /*!< Start radio. */
- __O uint32_t TASKS_STOP; /*!< Stop radio. */
- __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
- __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
- __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
- __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
- __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
- __I uint32_t RESERVED0[55];
- __IO uint32_t EVENTS_READY; /*!< Ready event. */
- __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
- __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
- __IO uint32_t EVENTS_END; /*!< End event. */
- __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
- __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
- __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
- __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
- sample is ready for readout at the RSSISAMPLE register. */
- __I uint32_t RESERVED1[2];
- __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
- __I uint32_t RESERVED2[53];
- __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
- __I uint32_t RESERVED3[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED4[61];
- __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
- __I uint32_t CD; /*!< Carrier detect. */
- __I uint32_t RXMATCH; /*!< Received address. */
- __I uint32_t RXCRC; /*!< Received CRC. */
- __I uint32_t DAI; /*!< Device address match index. */
- __I uint32_t RESERVED5[60];
- __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
- __IO uint32_t FREQUENCY; /*!< Frequency. */
- __IO uint32_t TXPOWER; /*!< Output power. */
- __IO uint32_t MODE; /*!< Data rate and modulation. */
- __IO uint32_t PCNF0; /*!< Packet configuration 0. */
- __IO uint32_t PCNF1; /*!< Packet configuration 1. */
- __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
- __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
- __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
- __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
- __IO uint32_t TXADDRESS; /*!< Transmit address select. */
- __IO uint32_t RXADDRESSES; /*!< Receive address select. */
- __IO uint32_t CRCCNF; /*!< CRC configuration. */
- __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
- __IO uint32_t CRCINIT; /*!< CRC initial value. */
- __IO uint32_t TEST; /*!< Test features enable register. */
- __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
- __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
- __I uint32_t RESERVED6;
- __I uint32_t STATE; /*!< Current radio state. */
- __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
- __I uint32_t RESERVED7[2];
- __IO uint32_t BCC; /*!< Bit counter compare. */
- __I uint32_t RESERVED8[39];
- __IO uint32_t DAB[8]; /*!< Device address base segment. */
- __IO uint32_t DAP[8]; /*!< Device address prefix. */
- __IO uint32_t DACNF; /*!< Device address match configuration. */
- __I uint32_t RESERVED9[56];
- __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
- __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
- __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
- __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
- __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
- __I uint32_t RESERVED10[561];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_RADIO_Type;
-
-
-/* ================================================================================ */
-/* ================ UART ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Universal Asynchronous Receiver/Transmitter. (UART)
- */
-
-typedef struct { /*!< UART Structure */
- __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
- __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
- __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
- __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
- __I uint32_t RESERVED0[3];
- __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
- __I uint32_t RESERVED1[56];
- __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
- __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
- __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
- __I uint32_t RESERVED2[4];
- __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
- __I uint32_t RESERVED3;
- __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
- __I uint32_t RESERVED4[7];
- __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
- __I uint32_t RESERVED5[46];
- __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
- __I uint32_t RESERVED6[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED7[93];
- __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
- __I uint32_t RESERVED8[31];
- __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
- __I uint32_t RESERVED9;
- __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
- __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
- __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
- __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
- __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
- Once read the character is consumed. If read when no character
- available, the UART will stop working. */
- __O uint32_t TXD; /*!< TXD register. */
- __I uint32_t RESERVED10;
- __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
- __I uint32_t RESERVED11[17];
- __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
- __I uint32_t RESERVED12[675];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_UART_Type;
-
-
-/* ================================================================================ */
-/* ================ SPI ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief SPI master 0. (SPI)
- */
-
-typedef struct { /*!< SPI Structure */
- __I uint32_t RESERVED0[66];
- __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
- __I uint32_t RESERVED1[126];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[125];
- __IO uint32_t ENABLE; /*!< Enable SPI. */
- __I uint32_t RESERVED3;
- __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
- __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
- __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
- __I uint32_t RESERVED4;
- __I uint32_t RXD; /*!< RX data. */
- __IO uint32_t TXD; /*!< TX data. */
- __I uint32_t RESERVED5;
- __IO uint32_t FREQUENCY; /*!< SPI frequency */
- __I uint32_t RESERVED6[11];
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t RESERVED7[681];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_SPI_Type;
-
-
-/* ================================================================================ */
-/* ================ TWI ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Two-wire interface master 0. (TWI)
- */
-
-typedef struct { /*!< TWI Structure */
- __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
- __I uint32_t RESERVED0;
- __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
- __I uint32_t RESERVED1[2];
- __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
- __I uint32_t RESERVED2;
- __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
- __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
- __I uint32_t RESERVED3[56];
- __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
- __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
- __I uint32_t RESERVED4[4];
- __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
- __I uint32_t RESERVED5;
- __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
- __I uint32_t RESERVED6[4];
- __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
- __I uint32_t RESERVED7[3];
- __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
- __I uint32_t RESERVED8[45];
- __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
- __I uint32_t RESERVED9[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED10[110];
- __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
- __I uint32_t RESERVED11[14];
- __IO uint32_t ENABLE; /*!< Enable two-wire master. */
- __I uint32_t RESERVED12;
- __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
- __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
- __I uint32_t RESERVED13[2];
- __I uint32_t RXD; /*!< RX data register. */
- __IO uint32_t TXD; /*!< TX data register. */
- __I uint32_t RESERVED14;
- __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
- __I uint32_t RESERVED15[24];
- __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
- __I uint32_t RESERVED16[668];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_TWI_Type;
-
-
-/* ================================================================================ */
-/* ================ SPIS ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief SPI slave 1. (SPIS)
- */
-
-typedef struct { /*!< SPIS Structure */
- __I uint32_t RESERVED0[9];
- __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
- __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
- __I uint32_t RESERVED1[54];
- __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
- __I uint32_t RESERVED2[8];
- __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
- __I uint32_t RESERVED3[53];
- __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
- __I uint32_t RESERVED4[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED5[61];
- __I uint32_t SEMSTAT; /*!< Semaphore status. */
- __I uint32_t RESERVED6[15];
- __IO uint32_t STATUS; /*!< Status from last transaction. */
- __I uint32_t RESERVED7[47];
- __IO uint32_t ENABLE; /*!< Enable SPIS. */
- __I uint32_t RESERVED8;
- __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
- __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
- __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
- __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
- __I uint32_t RESERVED9[7];
- __IO uint32_t RXDPTR; /*!< RX data pointer. */
- __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
- __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
- __I uint32_t RESERVED10;
- __IO uint32_t TXDPTR; /*!< TX data pointer. */
- __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
- __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
- __I uint32_t RESERVED11;
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t RESERVED12;
- __IO uint32_t DEF; /*!< Default character. */
- __I uint32_t RESERVED13[24];
- __IO uint32_t ORC; /*!< Over-read character. */
- __I uint32_t RESERVED14[654];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_SPIS_Type;
-
-
-/* ================================================================================ */
-/* ================ SPIM ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief SPI master with easyDMA 1. (SPIM)
- */
-
-typedef struct { /*!< SPIM Structure */
- __I uint32_t RESERVED0[4];
- __O uint32_t TASKS_START; /*!< Start SPI transaction. */
- __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
- __I uint32_t RESERVED1;
- __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
- __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
- __I uint32_t RESERVED2[56];
- __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
- __I uint32_t RESERVED3[2];
- __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
- __I uint32_t RESERVED4;
- __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
- __I uint32_t RESERVED5;
- __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
- __I uint32_t RESERVED6[10];
- __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
- __I uint32_t RESERVED7[44];
- __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
- __I uint32_t RESERVED8[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED9[125];
- __IO uint32_t ENABLE; /*!< Enable SPIM. */
- __I uint32_t RESERVED10;
- SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
- __I uint32_t RESERVED11[4];
- __IO uint32_t FREQUENCY; /*!< SPI frequency. */
- __I uint32_t RESERVED12[3];
- SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
- __I uint32_t RESERVED13;
- SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
- __I uint32_t RESERVED14;
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t RESERVED15[26];
- __IO uint32_t ORC; /*!< Over-read character. */
- __I uint32_t RESERVED16[654];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_SPIM_Type;
-
-
-/* ================================================================================ */
-/* ================ GPIOTE ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief GPIO tasks and events. (GPIOTE)
- */
-
-typedef struct { /*!< GPIOTE Structure */
- __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
- __I uint32_t RESERVED0[60];
- __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
- __I uint32_t RESERVED1[27];
- __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
- __I uint32_t RESERVED2[97];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[129];
- __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
- __I uint32_t RESERVED4[695];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_GPIOTE_Type;
-
-
-/* ================================================================================ */
-/* ================ ADC ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Analog to digital converter. (ADC)
- */
-
-typedef struct { /*!< ADC Structure */
- __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
- __O uint32_t TASKS_STOP; /*!< Stop ADC. */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
- __I uint32_t RESERVED1[128];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[61];
- __I uint32_t BUSY; /*!< ADC busy register. */
- __I uint32_t RESERVED3[63];
- __IO uint32_t ENABLE; /*!< ADC enable. */
- __IO uint32_t CONFIG; /*!< ADC configuration register. */
- __I uint32_t RESULT; /*!< Result of ADC conversion. */
- __I uint32_t RESERVED4[700];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_ADC_Type;
-
-
-/* ================================================================================ */
-/* ================ TIMER ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Timer 0. (TIMER)
- */
-
-typedef struct { /*!< TIMER Structure */
- __O uint32_t TASKS_START; /*!< Start Timer. */
- __O uint32_t TASKS_STOP; /*!< Stop Timer. */
- __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
- __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
- __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
- __I uint32_t RESERVED0[11];
- __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
- __I uint32_t RESERVED1[60];
- __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
- __I uint32_t RESERVED2[44];
- __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
- __I uint32_t RESERVED3[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED4[126];
- __IO uint32_t MODE; /*!< Timer Mode selection. */
- __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
- __I uint32_t RESERVED5;
- __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
- clock frequency is divided by 2^SCALE. */
- __I uint32_t RESERVED6[11];
- __IO uint32_t CC[4]; /*!< Capture/compare registers. */
- __I uint32_t RESERVED7[683];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_TIMER_Type;
-
-
-/* ================================================================================ */
-/* ================ RTC ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Real time counter 0. (RTC)
- */
-
-typedef struct { /*!< RTC Structure */
- __O uint32_t TASKS_START; /*!< Start RTC Counter. */
- __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
- __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
- __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
- __I uint32_t RESERVED0[60];
- __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
- __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
- __I uint32_t RESERVED1[14];
- __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
- __I uint32_t RESERVED2[109];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[13];
- __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
- __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
- the value of EVTEN. */
- __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
- gives the value of EVTEN. */
- __I uint32_t RESERVED4[110];
- __I uint32_t COUNTER; /*!< Current COUNTER value. */
- __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
- Must be written when RTC is STOPed. */
- __I uint32_t RESERVED5[13];
- __IO uint32_t CC[4]; /*!< Capture/compare registers. */
- __I uint32_t RESERVED6[683];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_RTC_Type;
-
-
-/* ================================================================================ */
-/* ================ TEMP ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Temperature Sensor. (TEMP)
- */
-
-typedef struct { /*!< TEMP Structure */
- __O uint32_t TASKS_START; /*!< Start temperature measurement. */
- __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
- __I uint32_t RESERVED1[128];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[127];
- __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
- __I uint32_t RESERVED3[700];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_TEMP_Type;
-
-
-/* ================================================================================ */
-/* ================ RNG ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Random Number Generator. (RNG)
- */
-
-typedef struct { /*!< RNG Structure */
- __O uint32_t TASKS_START; /*!< Start the random number generator. */
- __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
- __I uint32_t RESERVED1[63];
- __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
- __I uint32_t RESERVED3[126];
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t VALUE; /*!< RNG random number. */
- __I uint32_t RESERVED4[700];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_RNG_Type;
-
-
-/* ================================================================================ */
-/* ================ ECB ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief AES ECB Mode Encryption. (ECB)
- */
-
-typedef struct { /*!< ECB Structure */
- __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
- will not initiate a new encryption and the ERRORECB event will
- be triggered. */
- __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
- this will will trigger the ERRORECB event. */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
- __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
- error. */
- __I uint32_t RESERVED1[127];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[126];
- __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
- __I uint32_t RESERVED3[701];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_ECB_Type;
-
-
-/* ================================================================================ */
-/* ================ AAR ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Accelerated Address Resolver. (AAR)
- */
-
-typedef struct { /*!< AAR Structure */
- __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
- data structure. */
- __I uint32_t RESERVED0;
- __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
- __I uint32_t RESERVED1[61];
- __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
- __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
- __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
- __I uint32_t RESERVED2[126];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __I uint32_t STATUS; /*!< Resolution status. */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< Enable AAR. */
- __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
- __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
- __I uint32_t RESERVED5;
- __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
- __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
- during resolution. A minimum of 3 bytes must be reserved. */
- __I uint32_t RESERVED6[697];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_AAR_Type;
-
-
-/* ================================================================================ */
-/* ================ CCM ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief AES CCM Mode Encryption. (CCM)
- */
-
-typedef struct { /*!< CCM Structure */
- __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
- itself when completed. */
- __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
- completed. */
- __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
- __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
- __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
- __I uint32_t RESERVED1[61];
- __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< CCM enable. */
- __IO uint32_t MODE; /*!< Operation mode. */
- __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
- __IO uint32_t INPTR; /*!< Pointer to the input packet. */
- __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
- __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
- during resolution. A minimum of 43 bytes must be reserved. */
- __I uint32_t RESERVED5[697];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_CCM_Type;
-
-
-/* ================================================================================ */
-/* ================ WDT ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Watchdog Timer. (WDT)
- */
-
-typedef struct { /*!< WDT Structure */
- __O uint32_t TASKS_START; /*!< Start the watchdog. */
- __I uint32_t RESERVED0[63];
- __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
- __I uint32_t RESERVED1[128];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[61];
- __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
- __I uint32_t REQSTATUS; /*!< Request status. */
- __I uint32_t RESERVED3[63];
- __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
- __IO uint32_t RREN; /*!< Reload request enable. */
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t RESERVED4[60];
- __O uint32_t RR[8]; /*!< Reload requests registers. */
- __I uint32_t RESERVED5[631];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_WDT_Type;
-
-
-/* ================================================================================ */
-/* ================ QDEC ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Rotary decoder. (QDEC)
- */
-
-typedef struct { /*!< QDEC Structure */
- __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
- __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
- __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
- and clears the ACC registers. */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
- __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
- ACC register different than zero. */
- __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
- __I uint32_t RESERVED1[61];
- __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[125];
- __IO uint32_t ENABLE; /*!< Enable the QDEC. */
- __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
- __IO uint32_t SAMPLEPER; /*!< Sample period. */
- __I int32_t SAMPLE; /*!< Motion sample value. */
- __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
- __I int32_t ACC; /*!< Accumulated valid transitions register. */
- __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
- task. */
- __IO uint32_t PSELLED; /*!< Pin select for LED output. */
- __IO uint32_t PSELA; /*!< Pin select for phase A input. */
- __IO uint32_t PSELB; /*!< Pin select for phase B input. */
- __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
- __I uint32_t RESERVED4[5];
- __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
- __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
- __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
- task. */
- __I uint32_t RESERVED5[684];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_QDEC_Type;
-
-
-/* ================================================================================ */
-/* ================ LPCOMP ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Low power comparator. (LPCOMP)
- */
-
-typedef struct { /*!< LPCOMP Structure */
- __O uint32_t TASKS_START; /*!< Start the comparator. */
- __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
- __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
- __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
- __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
- __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
- __I uint32_t RESERVED1[60];
- __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __I uint32_t RESULT; /*!< Result of last compare. */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
- __IO uint32_t PSEL; /*!< Input pin select. */
- __IO uint32_t REFSEL; /*!< Reference select. */
- __IO uint32_t EXTREFSEL; /*!< External reference select. */
- __I uint32_t RESERVED5[4];
- __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
- __I uint32_t RESERVED6[694];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_LPCOMP_Type;
-
-
-/* ================================================================================ */
-/* ================ SWI ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief SW Interrupts. (SWI)
- */
-
-typedef struct { /*!< SWI Structure */
- __I uint32_t UNUSED; /*!< Unused. */
-} NRF_SWI_Type;
-
-
-/* ================================================================================ */
-/* ================ NVMC ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Non Volatile Memory Controller. (NVMC)
- */
-
-typedef struct { /*!< NVMC Structure */
- __I uint32_t RESERVED0[256];
- __I uint32_t READY; /*!< Ready flag. */
- __I uint32_t RESERVED1[64];
- __IO uint32_t CONFIG; /*!< Configuration register. */
-
- union {
- __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
- __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
- };
- __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
-
- union {
- __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
- __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
- };
- __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
-} NRF_NVMC_Type;
-
-
-/* ================================================================================ */
-/* ================ PPI ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief PPI controller. (PPI)
- */
-
-typedef struct { /*!< PPI Structure */
- PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
- __I uint32_t RESERVED0[312];
- __IO uint32_t CHEN; /*!< Channel enable. */
- __IO uint32_t CHENSET; /*!< Channel enable set. */
- __IO uint32_t CHENCLR; /*!< Channel enable clear. */
- __I uint32_t RESERVED1;
- PPI_CH_Type CH[16]; /*!< PPI Channel. */
- __I uint32_t RESERVED2[156];
- __IO uint32_t CHG[4]; /*!< Channel group configuration. */
-} NRF_PPI_Type;
-
-
-/* ================================================================================ */
-/* ================ FICR ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Factory Information Configuration. (FICR)
- */
-
-typedef struct { /*!< FICR Structure */
- __I uint32_t RESERVED0[4];
- __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
- __I uint32_t CODESIZE; /*!< Code memory size in pages. */
- __I uint32_t RESERVED1[4];
- __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
- __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
- __I uint32_t RESERVED2;
- __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
-
- union {
- __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
- kept for backward compatinility purposes. Use SIZERAMBLOCKS
- instead. */
- __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
- };
- __I uint32_t RESERVED3[5];
- __I uint32_t CONFIGID; /*!< Configuration identifier. */
- __I uint32_t DEVICEID[2]; /*!< Device identifier. */
- __I uint32_t RESERVED4[6];
- __I uint32_t ER[4]; /*!< Encryption root. */
- __I uint32_t IR[4]; /*!< Identity root. */
- __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
- __I uint32_t DEVICEADDR[2]; /*!< Device address. */
- __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
- __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
- mode. */
- __I uint32_t RESERVED5[10];
- __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
- mode. */
-} NRF_FICR_Type;
-
-
-/* ================================================================================ */
-/* ================ UICR ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief User Information Configuration. (UICR)
- */
-
-typedef struct { /*!< UICR Structure */
- __IO uint32_t CLENR0; /*!< Length of code region 0. */
- __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
- __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
- __I uint32_t RESERVED0;
- __I uint32_t FWID; /*!< Firmware ID. */
-
- union {
- __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
- __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
- };
- __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
- __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
-} NRF_UICR_Type;
-
-
-/* ================================================================================ */
-/* ================ GPIO ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief General purpose input and output. (GPIO)
- */
-
-typedef struct { /*!< GPIO Structure */
- __I uint32_t RESERVED0[321];
- __IO uint32_t OUT; /*!< Write GPIO port. */
- __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
- __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
- __I uint32_t IN; /*!< Read GPIO port. */
- __IO uint32_t DIR; /*!< Direction of GPIO pins. */
- __IO uint32_t DIRSET; /*!< DIR set register. */
- __IO uint32_t DIRCLR; /*!< DIR clear register. */
- __I uint32_t RESERVED1[120];
- __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
-} NRF_GPIO_Type;
-
-
-/* -------------------- End of section using anonymous unions ------------------- */
-#if defined(__CC_ARM)
- #pragma pop
-#elif defined(__ICCARM__)
- /* leave anonymous unions enabled */
-#elif defined(__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
- /* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
- #pragma warning restore
-#else
- #warning Not supported compiler type
-#endif
-
-
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-
-#define NRF_POWER_BASE 0x40000000UL
-#define NRF_CLOCK_BASE 0x40000000UL
-#define NRF_MPU_BASE 0x40000000UL
-#define NRF_PU_BASE 0x40000000UL
-#define NRF_AMLI_BASE 0x40000000UL
-#define NRF_RADIO_BASE 0x40001000UL
-#define NRF_UART0_BASE 0x40002000UL
-#define NRF_SPI0_BASE 0x40003000UL
-#define NRF_TWI0_BASE 0x40003000UL
-#define NRF_SPI1_BASE 0x40004000UL
-#define NRF_TWI1_BASE 0x40004000UL
-#define NRF_SPIS1_BASE 0x40004000UL
-#define NRF_SPIM1_BASE 0x40004000UL
-#define NRF_GPIOTE_BASE 0x40006000UL
-#define NRF_ADC_BASE 0x40007000UL
-#define NRF_TIMER0_BASE 0x40008000UL
-#define NRF_TIMER1_BASE 0x40009000UL
-#define NRF_TIMER2_BASE 0x4000A000UL
-#define NRF_RTC0_BASE 0x4000B000UL
-#define NRF_TEMP_BASE 0x4000C000UL
-#define NRF_RNG_BASE 0x4000D000UL
-#define NRF_ECB_BASE 0x4000E000UL
-#define NRF_AAR_BASE 0x4000F000UL
-#define NRF_CCM_BASE 0x4000F000UL
-#define NRF_WDT_BASE 0x40010000UL
-#define NRF_RTC1_BASE 0x40011000UL
-#define NRF_QDEC_BASE 0x40012000UL
-#define NRF_LPCOMP_BASE 0x40013000UL
-#define NRF_SWI_BASE 0x40014000UL
-#define NRF_NVMC_BASE 0x4001E000UL
-#define NRF_PPI_BASE 0x4001F000UL
-#define NRF_FICR_BASE 0x10000000UL
-#define NRF_UICR_BASE 0x10001000UL
-#define NRF_GPIO_BASE 0x50000000UL
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-
-#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
-#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
-#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
-#define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
-#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
-#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
-#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
-#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
-#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
-#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
-#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
-#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
-#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
-#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
-#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
-#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
-#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
-#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
-#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
-#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
-#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
-#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
-#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
-#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
-#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
-#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
-#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
-#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
-#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
-#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
-#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
-#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
-#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
-#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group nrf51 */
-/** @} */ /* End of group Nordic Semiconductor */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* nrf51_H */
-
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/nrf51_bitfields.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/nrf51_bitfields.h deleted file mode 100644 index 0ab4598..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/nrf51_bitfields.h +++ /dev/null @@ -1,7088 +0,0 @@ -/* Copyright (c) 2015, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef __NRF51_BITS_H -#define __NRF51_BITS_H - -/*lint ++flb "Enter library region" */ - -/* Peripheral: AAR */ -/* Description: Accelerated Address Resolver. */ - -/* Register: AAR_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on NOTRESOLVED event. */ -#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ -#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ -#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on RESOLVED event. */ -#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ -#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ -#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on END event. */ -#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ -#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: AAR_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on NOTRESOLVED event. */ -#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ -#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ -#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on RESOLVED event. */ -#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ -#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ -#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on ENDKSGEN event. */ -#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ -#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: AAR_STATUS */ -/* Description: Resolution status. */ - -/* Bits 3..0 : The IRK used last time an address was resolved. */ -#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ - -/* Register: AAR_ENABLE */ -/* Description: Enable AAR. */ - -/* Bits 1..0 : Enable AAR. */ -#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */ -#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */ - -/* Register: AAR_NIRK */ -/* Description: Number of Identity root Keys in the IRK data structure. */ - -/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */ -#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ -#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ - -/* Register: AAR_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: ADC */ -/* Description: Analog to digital converter. */ - -/* Register: ADC_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 0 : Enable interrupt on END event. */ -#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */ -#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: ADC_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 0 : Disable interrupt on END event. */ -#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ -#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: ADC_BUSY */ -/* Description: ADC busy register. */ - -/* Bit 0 : ADC busy register. */ -#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */ -#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */ -#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */ -#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */ - -/* Register: ADC_ENABLE */ -/* Description: ADC enable. */ - -/* Bits 1..0 : ADC enable. */ -#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */ -#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */ - -/* Register: ADC_CONFIG */ -/* Description: ADC configuration register. */ - -/* Bits 17..16 : ADC external reference pin selection. */ -#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */ -#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ -#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */ -#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */ -#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */ - -/* Bits 15..8 : ADC analog pin selection. */ -#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ -#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ -#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */ -#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */ - -/* Bits 6..5 : ADC reference selection. */ -#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */ -#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */ -#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */ -#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */ -#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */ - -/* Bits 4..2 : ADC input selection. */ -#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */ -#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */ -#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */ -#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */ -#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */ -#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */ -#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */ - -/* Bits 1..0 : ADC resolution. */ -#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */ -#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */ -#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */ -#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */ -#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */ - -/* Register: ADC_RESULT */ -/* Description: Result of ADC conversion. */ - -/* Bits 9..0 : Result of ADC conversion. */ -#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ -#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ - -/* Register: ADC_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: AMLI */ -/* Description: AHB Multi-Layer Interface. */ - -/* Register: AMLI_RAMPRI_CPU0 */ -/* Description: Configurable priority configuration register for CPU0. */ - -/* Bits 31..28 : Configuration field for RAM block 7. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 27..24 : Configuration field for RAM block 6. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 23..20 : Configuration field for RAM block 5. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 19..16 : Configuration field for RAM block 4. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_SPIS1 */ -/* Description: Configurable priority configuration register for SPIS1. */ - -/* Bits 31..28 : Configuration field for RAM block 7. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 27..24 : Configuration field for RAM block 6. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 23..20 : Configuration field for RAM block 5. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 19..16 : Configuration field for RAM block 4. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_RADIO */ -/* Description: Configurable priority configuration register for RADIO. */ - -/* Bits 31..28 : Configuration field for RAM block 7. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 27..24 : Configuration field for RAM block 6. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 23..20 : Configuration field for RAM block 5. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 19..16 : Configuration field for RAM block 4. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_ECB */ -/* Description: Configurable priority configuration register for ECB. */ - -/* Bits 31..28 : Configuration field for RAM block 7. */ -#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 27..24 : Configuration field for RAM block 6. */ -#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 23..20 : Configuration field for RAM block 5. */ -#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 19..16 : Configuration field for RAM block 4. */ -#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_CCM */ -/* Description: Configurable priority configuration register for CCM. */ - -/* Bits 31..28 : Configuration field for RAM block 7. */ -#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 27..24 : Configuration field for RAM block 6. */ -#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 23..20 : Configuration field for RAM block 5. */ -#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 19..16 : Configuration field for RAM block 4. */ -#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_AAR */ -/* Description: Configurable priority configuration register for AAR. */ - -/* Bits 31..28 : Configuration field for RAM block 7. */ -#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 27..24 : Configuration field for RAM block 6. */ -#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 23..20 : Configuration field for RAM block 5. */ -#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 19..16 : Configuration field for RAM block 4. */ -#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - - -/* Peripheral: CCM */ -/* Description: AES CCM Mode Encryption. */ - -/* Register: CCM_SHORTS */ -/* Description: Shortcuts for the CCM. */ - -/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: CCM_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on ERROR event. */ -#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ -#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on ENDCRYPT event. */ -#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ -#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ -#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on ENDKSGEN event. */ -#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ -#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ -#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: CCM_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on ERROR event. */ -#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ -#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on ENDCRYPT event. */ -#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ -#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ -#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on ENDKSGEN event. */ -#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ -#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ -#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: CCM_MICSTATUS */ -/* Description: CCM RX MIC check result. */ - -/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */ -#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ -#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ -#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */ -#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */ - -/* Register: CCM_ENABLE */ -/* Description: CCM enable. */ - -/* Bits 1..0 : CCM enable. */ -#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */ -#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */ - -/* Register: CCM_MODE */ -/* Description: Operation mode. */ - -/* Bit 0 : CCM mode operation. */ -#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */ -#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */ - -/* Register: CCM_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: CLOCK */ -/* Description: Clock control. */ - -/* Register: CLOCK_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 4 : Enable interrupt on CTTO event. */ -#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ -#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ -#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 3 : Enable interrupt on DONE event. */ -#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ -#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ -#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: CLOCK_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 4 : Disable interrupt on CTTO event. */ -#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ -#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ -#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 3 : Disable interrupt on DONE event. */ -#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ -#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ -#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: CLOCK_HFCLKRUN */ -/* Description: Task HFCLKSTART trigger status. */ - -/* Bit 0 : Task HFCLKSTART trigger status. */ -#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */ -#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */ - -/* Register: CLOCK_HFCLKSTAT */ -/* Description: High frequency clock status. */ - -/* Bit 16 : State for the HFCLK. */ -#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ -#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ -#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */ -#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */ - -/* Bit 0 : Active clock source for the HF clock. */ -#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */ -#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */ - -/* Register: CLOCK_LFCLKRUN */ -/* Description: Task LFCLKSTART triggered status. */ - -/* Bit 0 : Task LFCLKSTART triggered status. */ -#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */ -#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */ - -/* Register: CLOCK_LFCLKSTAT */ -/* Description: Low frequency clock status. */ - -/* Bit 16 : State for the LF clock. */ -#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ -#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ -#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */ -#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */ - -/* Bits 1..0 : Active clock source for the LF clock. */ -#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */ -#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */ -#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */ - -/* Register: CLOCK_LFCLKSRCCOPY */ -/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ - -/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ -#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ -#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ -#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ - -/* Register: CLOCK_LFCLKSRC */ -/* Description: Clock source for the LFCLK clock. */ - -/* Bits 1..0 : Clock source. */ -#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ -#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ -#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ - -/* Register: CLOCK_CTIV */ -/* Description: Calibration timer interval. */ - -/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */ -#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ -#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ - -/* Register: CLOCK_XTALFREQ */ -/* Description: Crystal frequency. */ - -/* Bits 7..0 : External Xtal frequency selection. */ -#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ -#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ -#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */ -#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */ - - -/* Peripheral: ECB */ -/* Description: AES ECB Mode Encryption. */ - -/* Register: ECB_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 1 : Enable interrupt on ERRORECB event. */ -#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ -#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ -#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ -#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ -#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on ENDECB event. */ -#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ -#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ -#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ -#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ -#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: ECB_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 1 : Disable interrupt on ERRORECB event. */ -#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ -#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ -#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ -#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ -#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on ENDECB event. */ -#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ -#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ -#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ -#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ -#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: ECB_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: FICR */ -/* Description: Factory Information Configuration. */ - -/* Register: FICR_PPFC */ -/* Description: Pre-programmed factory code present. */ - -/* Bits 7..0 : Pre-programmed factory code present. */ -#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */ -#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */ -#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */ -#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */ - -/* Register: FICR_CONFIGID */ -/* Description: Configuration identifier. */ - -/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */ -#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */ -#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */ - -/* Bits 15..0 : Hardware Identification Number. */ -#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */ -#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */ - -/* Register: FICR_DEVICEADDRTYPE */ -/* Description: Device address type. */ - -/* Bit 0 : Device address type. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */ - -/* Register: FICR_OVERRIDEEN */ -/* Description: Radio calibration override enable. */ - -/* Bit 3 : Override default values for BLE_1Mbit mode. */ -#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */ -#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */ -#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */ -#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */ - -/* Bit 0 : Override default values for NRF_1Mbit mode. */ -#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */ -#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */ -#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */ -#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */ - - -/* Peripheral: GPIO */ -/* Description: General purpose input and output. */ - -/* Register: GPIO_OUT */ -/* Description: Write GPIO port. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */ - -/* Register: GPIO_OUTSET */ -/* Description: Set individual bits in GPIO port. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */ - -/* Register: GPIO_OUTCLR */ -/* Description: Clear individual bits in GPIO port. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */ - -/* Register: GPIO_IN */ -/* Description: Read GPIO port. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */ - -/* Register: GPIO_DIR */ -/* Description: Direction of GPIO pins. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */ - -/* Register: GPIO_DIRSET */ -/* Description: DIR set register. */ - -/* Bit 31 : Set as output pin 31. */ -#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */ - -/* Bit 30 : Set as output pin 30. */ -#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */ - -/* Bit 29 : Set as output pin 29. */ -#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */ - -/* Bit 28 : Set as output pin 28. */ -#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */ - -/* Bit 27 : Set as output pin 27. */ -#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */ - -/* Bit 26 : Set as output pin 26. */ -#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */ - -/* Bit 25 : Set as output pin 25. */ -#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */ - -/* Bit 24 : Set as output pin 24. */ -#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */ - -/* Bit 23 : Set as output pin 23. */ -#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */ - -/* Bit 22 : Set as output pin 22. */ -#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */ - -/* Bit 21 : Set as output pin 21. */ -#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */ - -/* Bit 20 : Set as output pin 20. */ -#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */ - -/* Bit 19 : Set as output pin 19. */ -#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */ - -/* Bit 18 : Set as output pin 18. */ -#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */ - -/* Bit 17 : Set as output pin 17. */ -#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */ - -/* Bit 16 : Set as output pin 16. */ -#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */ - -/* Bit 15 : Set as output pin 15. */ -#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */ - -/* Bit 14 : Set as output pin 14. */ -#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */ - -/* Bit 13 : Set as output pin 13. */ -#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */ - -/* Bit 12 : Set as output pin 12. */ -#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */ - -/* Bit 11 : Set as output pin 11. */ -#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */ - -/* Bit 10 : Set as output pin 10. */ -#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */ - -/* Bit 9 : Set as output pin 9. */ -#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */ - -/* Bit 8 : Set as output pin 8. */ -#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */ - -/* Bit 7 : Set as output pin 7. */ -#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */ - -/* Bit 6 : Set as output pin 6. */ -#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */ - -/* Bit 5 : Set as output pin 5. */ -#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */ - -/* Bit 4 : Set as output pin 4. */ -#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */ - -/* Bit 3 : Set as output pin 3. */ -#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */ - -/* Bit 2 : Set as output pin 2. */ -#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */ - -/* Bit 1 : Set as output pin 1. */ -#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */ - -/* Bit 0 : Set as output pin 0. */ -#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */ - -/* Register: GPIO_DIRCLR */ -/* Description: DIR clear register. */ - -/* Bit 31 : Set as input pin 31. */ -#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 30 : Set as input pin 30. */ -#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 29 : Set as input pin 29. */ -#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 28 : Set as input pin 28. */ -#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 27 : Set as input pin 27. */ -#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 26 : Set as input pin 26. */ -#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 25 : Set as input pin 25. */ -#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 24 : Set as input pin 24. */ -#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 23 : Set as input pin 23. */ -#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 22 : Set as input pin 22. */ -#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 21 : Set as input pin 21. */ -#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 20 : Set as input pin 20. */ -#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 19 : Set as input pin 19. */ -#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 18 : Set as input pin 18. */ -#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 17 : Set as input pin 17. */ -#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 16 : Set as input pin 16. */ -#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 15 : Set as input pin 15. */ -#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 14 : Set as input pin 14. */ -#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 13 : Set as input pin 13. */ -#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 12 : Set as input pin 12. */ -#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 11 : Set as input pin 11. */ -#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 10 : Set as input pin 10. */ -#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 9 : Set as input pin 9. */ -#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 8 : Set as input pin 8. */ -#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 7 : Set as input pin 7. */ -#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 6 : Set as input pin 6. */ -#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 5 : Set as input pin 5. */ -#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 4 : Set as input pin 4. */ -#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 3 : Set as input pin 3. */ -#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 2 : Set as input pin 2. */ -#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 1 : Set as input pin 1. */ -#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 0 : Set as input pin 0. */ -#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */ - -/* Register: GPIO_PIN_CNF */ -/* Description: Configuration of GPIO pins. */ - -/* Bits 17..16 : Pin sensing mechanism. */ -#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ -#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ -#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */ -#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */ -#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */ - -/* Bits 10..8 : Drive configuration. */ -#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ -#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ -#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */ -#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */ -#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */ -#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */ -#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */ -#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */ -#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */ -#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */ - -/* Bits 3..2 : Pull-up or -down configuration. */ -#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ -#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ -#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */ -#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */ -#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */ - -/* Bit 1 : Connect or disconnect input path. */ -#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ -#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ -#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */ -#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */ - -/* Bit 0 : Pin direction. */ -#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ -#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ -#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */ -#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */ - - -/* Peripheral: GPIOTE */ -/* Description: GPIO tasks and events. */ - -/* Register: GPIOTE_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 31 : Enable interrupt on PORT event. */ -#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ -#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ -#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 3 : Enable interrupt on IN[3] event. */ -#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ -#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ -#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on IN[2] event. */ -#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ -#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ -#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on IN[1] event. */ -#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ -#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ -#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on IN[0] event. */ -#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ -#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ -#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: GPIOTE_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 31 : Disable interrupt on PORT event. */ -#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ -#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ -#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 3 : Disable interrupt on IN[3] event. */ -#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ -#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ -#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on IN[2] event. */ -#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ -#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ -#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on IN[1] event. */ -#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ -#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ -#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on IN[0] event. */ -#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ -#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ -#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: GPIOTE_CONFIG */ -/* Description: Channel configuration registers. */ - -/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */ -#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ -#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ -#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */ -#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */ - -/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */ -#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ -#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ -#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */ -#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */ -#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */ -#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */ - -/* Bits 12..8 : Pin select. */ -#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ -#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ - -/* Bits 1..0 : Mode */ -#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ -#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */ -#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */ -#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */ - -/* Register: GPIOTE_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: LPCOMP */ -/* Description: Low power comparator. */ - -/* Register: LPCOMP_SHORTS */ -/* Description: Shortcuts for the LPCOMP. */ - -/* Bit 4 : Shortcut between CROSS event and STOP task. */ -#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ -#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ -#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Shortcut between UP event and STOP task. */ -#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ -#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ -#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 2 : Shortcut between DOWN event and STOP task. */ -#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ -#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ -#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 1 : Shortcut between RADY event and STOP task. */ -#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ -#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ -#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Shortcut between READY event and SAMPLE task. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: LPCOMP_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 3 : Enable interrupt on CROSS event. */ -#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on UP event. */ -#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ -#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ -#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on DOWN event. */ -#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on READY event. */ -#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: LPCOMP_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 3 : Disable interrupt on CROSS event. */ -#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on UP event. */ -#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ -#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ -#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on DOWN event. */ -#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on READY event. */ -#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: LPCOMP_RESULT */ -/* Description: Result of last compare. */ - -/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ -#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */ -#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ - -/* Register: LPCOMP_ENABLE */ -/* Description: Enable the LPCOMP. */ - -/* Bits 1..0 : Enable or disable LPCOMP. */ -#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */ -#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */ - -/* Register: LPCOMP_PSEL */ -/* Description: Input pin select. */ - -/* Bits 2..0 : Analog input pin select. */ -#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ -#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ -#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */ - -/* Register: LPCOMP_REFSEL */ -/* Description: Reference select. */ - -/* Bits 2..0 : Reference select. */ -#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ -#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */ - -/* Register: LPCOMP_EXTREFSEL */ -/* Description: External reference select. */ - -/* Bit 0 : External analog reference pin selection. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */ - -/* Register: LPCOMP_ANADETECT */ -/* Description: Analog detect configuration. */ - -/* Bits 1..0 : Analog detect configuration. */ -#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ -#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ -#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */ -#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */ -#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */ - -/* Register: LPCOMP_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: MPU */ -/* Description: Memory Protection Unit. */ - -/* Register: MPU_PERR0 */ -/* Description: Configuration of peripherals in mpu regions. */ - -/* Bit 31 : PPI region configuration. */ -#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */ -#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */ -#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 30 : NVMC region configuration. */ -#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */ -#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */ -#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 19 : LPCOMP region configuration. */ -#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */ -#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ -#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 18 : QDEC region configuration. */ -#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */ -#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */ -#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 17 : RTC1 region configuration. */ -#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */ -#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */ -#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 16 : WDT region configuration. */ -#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */ -#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */ -#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 15 : CCM and AAR region configuration. */ -#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */ -#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */ -#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 14 : ECB region configuration. */ -#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */ -#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */ -#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 13 : RNG region configuration. */ -#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */ -#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */ -#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 12 : TEMP region configuration. */ -#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */ -#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */ -#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 11 : RTC0 region configuration. */ -#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */ -#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */ -#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 10 : TIMER2 region configuration. */ -#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */ -#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */ -#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 9 : TIMER1 region configuration. */ -#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */ -#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */ -#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 8 : TIMER0 region configuration. */ -#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */ -#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */ -#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 7 : ADC region configuration. */ -#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */ -#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */ -#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 6 : GPIOTE region configuration. */ -#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */ -#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */ -#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 4 : SPI1 and TWI1 region configuration. */ -#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */ -#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */ -#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 3 : SPI0 and TWI0 region configuration. */ -#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */ -#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */ -#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 2 : UART0 region configuration. */ -#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */ -#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */ -#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 1 : RADIO region configuration. */ -#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */ -#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */ -#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 0 : POWER_CLOCK region configuration. */ -#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */ -#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */ -#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Register: MPU_PROTENSET0 */ -/* Description: Erase and write protection bit enable set register. */ - -/* Bit 31 : Protection enable for region 31. */ -#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */ -#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */ -#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 30 : Protection enable for region 30. */ -#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */ -#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */ -#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 29 : Protection enable for region 29. */ -#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */ -#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */ -#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 28 : Protection enable for region 28. */ -#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */ -#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */ -#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 27 : Protection enable for region 27. */ -#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */ -#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */ -#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 26 : Protection enable for region 26. */ -#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */ -#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */ -#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 25 : Protection enable for region 25. */ -#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */ -#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */ -#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 24 : Protection enable for region 24. */ -#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */ -#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */ -#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 23 : Protection enable for region 23. */ -#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */ -#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */ -#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 22 : Protection enable for region 22. */ -#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */ -#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */ -#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 21 : Protection enable for region 21. */ -#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */ -#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */ -#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 20 : Protection enable for region 20. */ -#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */ -#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */ -#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 19 : Protection enable for region 19. */ -#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */ -#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */ -#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 18 : Protection enable for region 18. */ -#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */ -#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */ -#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 17 : Protection enable for region 17. */ -#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */ -#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */ -#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 16 : Protection enable for region 16. */ -#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */ -#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */ -#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 15 : Protection enable for region 15. */ -#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */ -#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */ -#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 14 : Protection enable for region 14. */ -#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */ -#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */ -#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 13 : Protection enable for region 13. */ -#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */ -#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */ -#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 12 : Protection enable for region 12. */ -#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */ -#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */ -#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 11 : Protection enable for region 11. */ -#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */ -#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */ -#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 10 : Protection enable for region 10. */ -#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */ -#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */ -#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 9 : Protection enable for region 9. */ -#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */ -#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */ -#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 8 : Protection enable for region 8. */ -#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */ -#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */ -#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 7 : Protection enable for region 7. */ -#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */ -#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */ -#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 6 : Protection enable for region 6. */ -#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */ -#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */ -#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 5 : Protection enable for region 5. */ -#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */ -#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */ -#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 4 : Protection enable for region 4. */ -#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */ -#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */ -#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 3 : Protection enable for region 3. */ -#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */ -#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */ -#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 2 : Protection enable for region 2. */ -#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */ -#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */ -#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 1 : Protection enable for region 1. */ -#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */ -#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */ -#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 0 : Protection enable for region 0. */ -#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */ -#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */ -#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */ - -/* Register: MPU_PROTENSET1 */ -/* Description: Erase and write protection bit enable set register. */ - -/* Bit 31 : Protection enable for region 63. */ -#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */ -#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */ -#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 30 : Protection enable for region 62. */ -#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */ -#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */ -#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 29 : Protection enable for region 61. */ -#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */ -#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */ -#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 28 : Protection enable for region 60. */ -#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */ -#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */ -#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 27 : Protection enable for region 59. */ -#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */ -#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */ -#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 26 : Protection enable for region 58. */ -#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */ -#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */ -#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 25 : Protection enable for region 57. */ -#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */ -#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */ -#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 24 : Protection enable for region 56. */ -#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */ -#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */ -#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 23 : Protection enable for region 55. */ -#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */ -#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */ -#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 22 : Protection enable for region 54. */ -#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */ -#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */ -#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 21 : Protection enable for region 53. */ -#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */ -#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */ -#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 20 : Protection enable for region 52. */ -#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */ -#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */ -#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 19 : Protection enable for region 51. */ -#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */ -#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */ -#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 18 : Protection enable for region 50. */ -#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */ -#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */ -#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 17 : Protection enable for region 49. */ -#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */ -#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */ -#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 16 : Protection enable for region 48. */ -#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */ -#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */ -#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 15 : Protection enable for region 47. */ -#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */ -#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */ -#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 14 : Protection enable for region 46. */ -#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */ -#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */ -#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 13 : Protection enable for region 45. */ -#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */ -#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */ -#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 12 : Protection enable for region 44. */ -#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */ -#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */ -#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 11 : Protection enable for region 43. */ -#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */ -#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */ -#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 10 : Protection enable for region 42. */ -#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */ -#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */ -#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 9 : Protection enable for region 41. */ -#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */ -#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */ -#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 8 : Protection enable for region 40. */ -#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */ -#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */ -#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 7 : Protection enable for region 39. */ -#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */ -#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */ -#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 6 : Protection enable for region 38. */ -#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */ -#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */ -#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 5 : Protection enable for region 37. */ -#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */ -#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */ -#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 4 : Protection enable for region 36. */ -#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */ -#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */ -#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 3 : Protection enable for region 35. */ -#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */ -#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */ -#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 2 : Protection enable for region 34. */ -#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */ -#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */ -#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 1 : Protection enable for region 33. */ -#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */ -#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */ -#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 0 : Protection enable for region 32. */ -#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */ -#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */ -#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */ - -/* Register: MPU_DISABLEINDEBUG */ -/* Description: Disable erase and write protection mechanism in debug mode. */ - -/* Bit 0 : Disable protection mechanism in debug mode. */ -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */ -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */ - -/* Register: MPU_PROTBLOCKSIZE */ -/* Description: Erase and write protection block size. */ - -/* Bits 1..0 : Erase and write protection block size. */ -#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */ -#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */ -#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */ - - -/* Peripheral: NVMC */ -/* Description: Non Volatile Memory Controller. */ - -/* Register: NVMC_READY */ -/* Description: Ready flag. */ - -/* Bit 0 : NVMC ready. */ -#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ -#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ -#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */ -#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */ - -/* Register: NVMC_CONFIG */ -/* Description: Configuration register. */ - -/* Bits 1..0 : Program write enable. */ -#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ -#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ -#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */ -#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */ -#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */ - -/* Register: NVMC_ERASEALL */ -/* Description: Register for erasing all non-volatile user memory. */ - -/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */ -#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ -#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ -#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */ -#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */ - -/* Register: NVMC_ERASEUICR */ -/* Description: Register for start erasing User Information Congfiguration Registers. */ - -/* Bit 0 : It can only be used when all contents of code region 1 are erased. */ -#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ -#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ -#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */ -#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */ - - -/* Peripheral: POWER */ -/* Description: Power Control. */ - -/* Register: POWER_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on POFWARN event. */ -#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ -#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ -#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ -#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ -#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: POWER_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on POFWARN event. */ -#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ -#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ -#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ -#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ -#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: POWER_RESETREAS */ -/* Description: Reset reason. */ - -/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */ -#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ -#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ -#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */ - -/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */ -#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ -#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ -#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */ - -/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */ -#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ -#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ -#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */ - -/* Bit 3 : Reset from CPU lock-up detected. */ -#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ -#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ -#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */ - -/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */ -#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ -#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ -#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */ - -/* Bit 1 : Reset from watchdog detected. */ -#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ -#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ -#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */ - -/* Bit 0 : Reset from pin-reset detected. */ -#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ -#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ -#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */ - -/* Register: POWER_RAMSTATUS */ -/* Description: Ram status register. */ - -/* Bit 3 : RAM block 3 status. */ -#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ -#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ -#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */ -#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */ - -/* Bit 2 : RAM block 2 status. */ -#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ -#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ -#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */ -#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */ - -/* Bit 1 : RAM block 1 status. */ -#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ -#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ -#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */ -#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */ - -/* Bit 0 : RAM block 0 status. */ -#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ -#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ -#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */ -#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */ - -/* Register: POWER_SYSTEMOFF */ -/* Description: System off register. */ - -/* Bit 0 : Enter system off mode. */ -#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ -#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ -#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */ - -/* Register: POWER_POFCON */ -/* Description: Power failure configuration. */ - -/* Bits 2..1 : Set threshold level. */ -#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ -#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ -#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */ -#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */ -#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */ -#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */ - -/* Bit 0 : Power failure comparator enable. */ -#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ -#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ -#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */ -#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */ - -/* Register: POWER_GPREGRET */ -/* Description: General purpose retention register. This register is a retained register. */ - -/* Bits 7..0 : General purpose retention register. */ -#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ -#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ - -/* Register: POWER_RAMON */ -/* Description: Ram on/off. */ - -/* Bit 17 : RAM block 1 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ -#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ -#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */ - -/* Bit 16 : RAM block 0 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ -#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ -#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */ - -/* Bit 1 : RAM block 1 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ -#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ -#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */ -#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */ - -/* Bit 0 : RAM block 0 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ -#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ -#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */ -#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */ - -/* Register: POWER_RESET */ -/* Description: Pin reset functionality configuration register. This register is a retained register. */ - -/* Bit 0 : Enable or disable pin reset in debug interface mode. */ -#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ -#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ -#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */ -#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */ - -/* Register: POWER_RAMONB */ -/* Description: Ram on/off. */ - -/* Bit 17 : RAM block 3 behaviour in OFF mode. */ -#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ -#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ -#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ -#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ - -/* Bit 16 : RAM block 2 behaviour in OFF mode. */ -#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ -#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ -#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ -#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ - -/* Bit 1 : RAM block 3 behaviour in ON mode. */ -#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ -#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ -#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */ -#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ - -/* Bit 0 : RAM block 2 behaviour in ON mode. */ -#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ -#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ -#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ -#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ - -/* Register: POWER_DCDCEN */ -/* Description: DCDC converter enable configuration register. */ - -/* Bit 0 : Enable DCDC converter. */ -#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ -#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ -#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */ -#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */ - -/* Register: POWER_DCDCFORCE */ -/* Description: DCDC power-up force register. */ - -/* Bit 1 : DCDC power-up force on. */ -#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */ -#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */ -#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */ -#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */ - -/* Bit 0 : DCDC power-up force off. */ -#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ -#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ -#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */ -#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */ - - -/* Peripheral: PPI */ -/* Description: PPI controller. */ - -/* Register: PPI_CHEN */ -/* Description: Channel enable. */ - -/* Bit 31 : Enable PPI channel 31. */ -#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 30 : Enable PPI channel 30. */ -#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 29 : Enable PPI channel 29. */ -#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 28 : Enable PPI channel 28. */ -#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 27 : Enable PPI channel 27. */ -#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 26 : Enable PPI channel 26. */ -#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 25 : Enable PPI channel 25. */ -#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 24 : Enable PPI channel 24. */ -#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 23 : Enable PPI channel 23. */ -#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 22 : Enable PPI channel 22. */ -#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 21 : Enable PPI channel 21. */ -#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 20 : Enable PPI channel 20. */ -#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 15 : Enable PPI channel 15. */ -#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 14 : Enable PPI channel 14. */ -#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 13 : Enable PPI channel 13. */ -#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 12 : Enable PPI channel 12. */ -#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 11 : Enable PPI channel 11. */ -#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 10 : Enable PPI channel 10. */ -#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 9 : Enable PPI channel 9. */ -#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 8 : Enable PPI channel 8. */ -#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 7 : Enable PPI channel 7. */ -#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 6 : Enable PPI channel 6. */ -#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 5 : Enable PPI channel 5. */ -#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 4 : Enable PPI channel 4. */ -#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 3 : Enable PPI channel 3. */ -#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */ -#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */ - -/* Bit 2 : Enable PPI channel 2. */ -#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 1 : Enable PPI channel 1. */ -#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 0 : Enable PPI channel 0. */ -#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */ - -/* Register: PPI_CHENSET */ -/* Description: Channel enable set. */ - -/* Bit 31 : Enable PPI channel 31. */ -#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 30 : Enable PPI channel 30. */ -#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 29 : Enable PPI channel 29. */ -#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 28 : Enable PPI channel 28. */ -#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 27 : Enable PPI channel 27. */ -#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 26 : Enable PPI channel 26. */ -#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 25 : Enable PPI channel 25. */ -#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 24 : Enable PPI channel 24. */ -#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 23 : Enable PPI channel 23. */ -#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 22 : Enable PPI channel 22. */ -#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 21 : Enable PPI channel 21. */ -#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 20 : Enable PPI channel 20. */ -#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 15 : Enable PPI channel 15. */ -#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 14 : Enable PPI channel 14. */ -#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 13 : Enable PPI channel 13. */ -#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 12 : Enable PPI channel 12. */ -#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 11 : Enable PPI channel 11. */ -#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 10 : Enable PPI channel 10. */ -#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 9 : Enable PPI channel 9. */ -#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 8 : Enable PPI channel 8. */ -#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 7 : Enable PPI channel 7. */ -#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 6 : Enable PPI channel 6. */ -#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 5 : Enable PPI channel 5. */ -#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 4 : Enable PPI channel 4. */ -#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 3 : Enable PPI channel 3. */ -#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 2 : Enable PPI channel 2. */ -#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 1 : Enable PPI channel 1. */ -#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 0 : Enable PPI channel 0. */ -#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */ - -/* Register: PPI_CHENCLR */ -/* Description: Channel enable clear. */ - -/* Bit 31 : Disable PPI channel 31. */ -#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 30 : Disable PPI channel 30. */ -#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 29 : Disable PPI channel 29. */ -#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 28 : Disable PPI channel 28. */ -#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 27 : Disable PPI channel 27. */ -#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 26 : Disable PPI channel 26. */ -#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 25 : Disable PPI channel 25. */ -#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 24 : Disable PPI channel 24. */ -#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 23 : Disable PPI channel 23. */ -#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 22 : Disable PPI channel 22. */ -#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 21 : Disable PPI channel 21. */ -#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 20 : Disable PPI channel 20. */ -#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 15 : Disable PPI channel 15. */ -#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 14 : Disable PPI channel 14. */ -#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 13 : Disable PPI channel 13. */ -#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 12 : Disable PPI channel 12. */ -#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 11 : Disable PPI channel 11. */ -#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 10 : Disable PPI channel 10. */ -#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 9 : Disable PPI channel 9. */ -#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 8 : Disable PPI channel 8. */ -#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 7 : Disable PPI channel 7. */ -#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 6 : Disable PPI channel 6. */ -#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 5 : Disable PPI channel 5. */ -#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 4 : Disable PPI channel 4. */ -#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 3 : Disable PPI channel 3. */ -#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 2 : Disable PPI channel 2. */ -#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 1 : Disable PPI channel 1. */ -#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 0 : Disable PPI channel 0. */ -#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */ - -/* Register: PPI_CHG */ -/* Description: Channel group configuration. */ - -/* Bit 31 : Include CH31 in channel group. */ -#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */ - -/* Bit 30 : Include CH30 in channel group. */ -#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */ - -/* Bit 29 : Include CH29 in channel group. */ -#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */ - -/* Bit 28 : Include CH28 in channel group. */ -#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */ - -/* Bit 27 : Include CH27 in channel group. */ -#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */ - -/* Bit 26 : Include CH26 in channel group. */ -#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */ - -/* Bit 25 : Include CH25 in channel group. */ -#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */ - -/* Bit 24 : Include CH24 in channel group. */ -#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */ - -/* Bit 23 : Include CH23 in channel group. */ -#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */ - -/* Bit 22 : Include CH22 in channel group. */ -#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */ - -/* Bit 21 : Include CH21 in channel group. */ -#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */ - -/* Bit 20 : Include CH20 in channel group. */ -#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */ - -/* Bit 15 : Include CH15 in channel group. */ -#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */ - -/* Bit 14 : Include CH14 in channel group. */ -#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */ - -/* Bit 13 : Include CH13 in channel group. */ -#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */ - -/* Bit 12 : Include CH12 in channel group. */ -#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */ - -/* Bit 11 : Include CH11 in channel group. */ -#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */ - -/* Bit 10 : Include CH10 in channel group. */ -#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */ - -/* Bit 9 : Include CH9 in channel group. */ -#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */ - -/* Bit 8 : Include CH8 in channel group. */ -#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */ - -/* Bit 7 : Include CH7 in channel group. */ -#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */ - -/* Bit 6 : Include CH6 in channel group. */ -#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */ - -/* Bit 5 : Include CH5 in channel group. */ -#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */ - -/* Bit 4 : Include CH4 in channel group. */ -#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */ - -/* Bit 3 : Include CH3 in channel group. */ -#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */ - -/* Bit 2 : Include CH2 in channel group. */ -#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */ - -/* Bit 1 : Include CH1 in channel group. */ -#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */ - -/* Bit 0 : Include CH0 in channel group. */ -#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */ - - -/* Peripheral: PU */ -/* Description: Patch unit. */ - -/* Register: PU_PATCHADDR */ -/* Description: Relative address of patch instructions. */ - -/* Bits 24..0 : Relative address of patch instructions. */ -#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */ -#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */ - -/* Register: PU_PATCHEN */ -/* Description: Patch enable register. */ - -/* Bit 7 : Patch 7 enabled. */ -#define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ -#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ -#define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 6 : Patch 6 enabled. */ -#define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ -#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ -#define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 5 : Patch 5 enabled. */ -#define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ -#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ -#define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 4 : Patch 4 enabled. */ -#define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ -#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ -#define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 3 : Patch 3 enabled. */ -#define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ -#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ -#define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 2 : Patch 2 enabled. */ -#define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ -#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ -#define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 1 : Patch 1 enabled. */ -#define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ -#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ -#define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */ - -/* Bit 0 : Patch 0 enabled. */ -#define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ -#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ -#define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */ - -/* Register: PU_PATCHENSET */ -/* Description: Patch enable register. */ - -/* Bit 7 : Patch 7 enabled. */ -#define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ -#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ -#define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 6 : Patch 6 enabled. */ -#define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ -#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ -#define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 5 : Patch 5 enabled. */ -#define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ -#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ -#define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 4 : Patch 4 enabled. */ -#define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ -#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ -#define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 3 : Patch 3 enabled. */ -#define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ -#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ -#define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 2 : Patch 2 enabled. */ -#define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ -#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ -#define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 1 : Patch 1 enabled. */ -#define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ -#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ -#define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */ - -/* Bit 0 : Patch 0 enabled. */ -#define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ -#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ -#define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */ - -/* Register: PU_PATCHENCLR */ -/* Description: Patch disable register. */ - -/* Bit 7 : Patch 7 enabled. */ -#define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ -#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ -#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 6 : Patch 6 enabled. */ -#define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ -#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ -#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 5 : Patch 5 enabled. */ -#define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ -#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ -#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 4 : Patch 4 enabled. */ -#define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ -#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ -#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 3 : Patch 3 enabled. */ -#define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ -#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ -#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 2 : Patch 2 enabled. */ -#define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ -#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ -#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 1 : Patch 1 enabled. */ -#define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ -#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ -#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */ - -/* Bit 0 : Patch 0 enabled. */ -#define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ -#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ -#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */ -#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */ -#define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */ - - -/* Peripheral: QDEC */ -/* Description: Rotary decoder. */ - -/* Register: QDEC_SHORTS */ -/* Description: Shortcuts for the QDEC. */ - -/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: QDEC_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on ACCOF event. */ -#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ -#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ -#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on REPORTRDY event. */ -#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ -#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ -#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on SAMPLERDY event. */ -#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ -#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ -#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: QDEC_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on ACCOF event. */ -#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ -#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ -#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on REPORTRDY event. */ -#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ -#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ -#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on SAMPLERDY event. */ -#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ -#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ -#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: QDEC_ENABLE */ -/* Description: Enable the QDEC. */ - -/* Bit 0 : Enable or disable QDEC. */ -#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */ -#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */ - -/* Register: QDEC_LEDPOL */ -/* Description: LED output pin polarity. */ - -/* Bit 0 : LED output pin polarity. */ -#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ -#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ -#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */ -#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */ - -/* Register: QDEC_SAMPLEPER */ -/* Description: Sample period. */ - -/* Bits 2..0 : Sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ -#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ -#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */ - -/* Register: QDEC_SAMPLE */ -/* Description: Motion sample value. */ - -/* Bits 31..0 : Last sample taken in compliment to 2. */ -#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ -#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ - -/* Register: QDEC_REPORTPER */ -/* Description: Number of samples to generate an EVENT_REPORTRDY. */ - -/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */ -#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */ - -/* Register: QDEC_DBFEN */ -/* Description: Enable debouncer input filters. */ - -/* Bit 0 : Enable debounce input filters. */ -#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ -#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ -#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */ -#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */ - -/* Register: QDEC_LEDPRE */ -/* Description: Time LED is switched ON before the sample. */ - -/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */ -#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ -#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ - -/* Register: QDEC_ACCDBL */ -/* Description: Accumulated double (error) transitions register. */ - -/* Bits 3..0 : Accumulated double (error) transitions. */ -#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ -#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ - -/* Register: QDEC_ACCDBLREAD */ -/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */ - -/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */ -#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ -#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ - -/* Register: QDEC_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: RADIO */ -/* Description: The radio. */ - -/* Register: RADIO_SHORTS */ -/* Description: Shortcuts for the radio. */ - -/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 5 : Shortcut between END event and START task. */ -#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ -#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ -#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Shortcut between DISABLED event and RXEN task. */ -#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ -#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ -#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 2 : Shortcut between DISABLED event and TXEN task. */ -#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ -#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ -#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 1 : Shortcut between END event and DISABLE task. */ -#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ -#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ -#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Shortcut between READY event and START task. */ -#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ -#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ -#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: RADIO_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 10 : Enable interrupt on BCMATCH event. */ -#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ -#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ -#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 7 : Enable interrupt on RSSIEND event. */ -#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ -#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ -#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 6 : Enable interrupt on DEVMISS event. */ -#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ -#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ -#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 5 : Enable interrupt on DEVMATCH event. */ -#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ -#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ -#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 4 : Enable interrupt on DISABLED event. */ -#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ -#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ -#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 3 : Enable interrupt on END event. */ -#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ -#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on PAYLOAD event. */ -#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ -#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ -#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on ADDRESS event. */ -#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ -#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ -#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on READY event. */ -#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: RADIO_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 10 : Disable interrupt on BCMATCH event. */ -#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ -#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ -#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 7 : Disable interrupt on RSSIEND event. */ -#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ -#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ -#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 6 : Disable interrupt on DEVMISS event. */ -#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ -#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ -#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 5 : Disable interrupt on DEVMATCH event. */ -#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ -#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ -#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 4 : Disable interrupt on DISABLED event. */ -#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ -#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ -#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 3 : Disable interrupt on END event. */ -#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ -#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on PAYLOAD event. */ -#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ -#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ -#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on ADDRESS event. */ -#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ -#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ -#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on READY event. */ -#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: RADIO_CRCSTATUS */ -/* Description: CRC status of received packet. */ - -/* Bit 0 : CRC status of received packet. */ -#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ -#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ -#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */ -#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */ - -/* Register: RADIO_CD */ -/* Description: Carrier detect. */ - -/* Bit 0 : Carrier detect. */ -#define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */ -#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */ - -/* Register: RADIO_RXMATCH */ -/* Description: Received address. */ - -/* Bits 2..0 : Logical address in which previous packet was received. */ -#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ -#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ - -/* Register: RADIO_RXCRC */ -/* Description: Received CRC. */ - -/* Bits 23..0 : CRC field of previously received packet. */ -#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ -#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ - -/* Register: RADIO_DAI */ -/* Description: Device address match index. */ - -/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */ -#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ -#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ - -/* Register: RADIO_FREQUENCY */ -/* Description: Frequency. */ - -/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */ -#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ - -/* Register: RADIO_TXPOWER */ -/* Description: Output power. */ - -/* Bits 7..0 : Radio output power. Decision point: TXEN task. */ -#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ -#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ -#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */ -#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */ - -/* Register: RADIO_MODE */ -/* Description: Data rate and modulation. */ - -/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */ -#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */ -#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */ -#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */ -#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */ - -/* Register: RADIO_PCNF0 */ -/* Description: Packet configuration 0. */ - -/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */ -#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ -#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ - -/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */ -#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ -#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ - -/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */ -#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ -#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ - -/* Register: RADIO_PCNF1 */ -/* Description: Packet configuration 1. */ - -/* Bit 25 : Packet whitening enable. */ -#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ -#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ -#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */ -#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */ - -/* Bit 24 : On air endianness of packet length field. Decision point: START task. */ -#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ -#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ -#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ -#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ - -/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */ -#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ -#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ - -/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */ -#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ -#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ - -/* Bits 7..0 : Maximum length of packet payload in number of bytes. */ -#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ -#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ - -/* Register: RADIO_PREFIX0 */ -/* Description: Prefixes bytes for logical addresses 0 to 3. */ - -/* Bits 31..24 : Address prefix 3. Decision point: START task. */ -#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ -#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ - -/* Bits 23..16 : Address prefix 2. Decision point: START task. */ -#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ -#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ - -/* Bits 15..8 : Address prefix 1. Decision point: START task. */ -#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ -#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ - -/* Bits 7..0 : Address prefix 0. Decision point: START task. */ -#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ -#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ - -/* Register: RADIO_PREFIX1 */ -/* Description: Prefixes bytes for logical addresses 4 to 7. */ - -/* Bits 31..24 : Address prefix 7. Decision point: START task. */ -#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ -#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ - -/* Bits 23..16 : Address prefix 6. Decision point: START task. */ -#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ -#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ - -/* Bits 15..8 : Address prefix 5. Decision point: START task. */ -#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ -#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ - -/* Bits 7..0 : Address prefix 4. Decision point: START task. */ -#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ -#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ - -/* Register: RADIO_TXADDRESS */ -/* Description: Transmit address select. */ - -/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */ -#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ -#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ - -/* Register: RADIO_RXADDRESSES */ -/* Description: Receive address select. */ - -/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ -#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ -#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ -#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ -#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ -#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ -#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ -#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ -#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ -#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ -#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ -#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ -#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ -#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ -#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ -#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ -#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */ - -/* Register: RADIO_CRCCNF */ -/* Description: CRC configuration. */ - -/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */ -#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ -#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ -#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ -#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ - -/* Bits 1..0 : CRC length. Decision point: START task. */ -#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ -#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ -#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */ -#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */ -#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */ -#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */ - -/* Register: RADIO_CRCPOLY */ -/* Description: CRC polynomial. */ - -/* Bits 23..0 : CRC polynomial. Decision point: START task. */ -#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ -#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ - -/* Register: RADIO_CRCINIT */ -/* Description: CRC initial value. */ - -/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */ -#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ -#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ - -/* Register: RADIO_TEST */ -/* Description: Test features enable register. */ - -/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */ -#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */ -#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */ -#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */ -#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */ - -/* Bit 0 : Constant carrier. Decision point: TXEN task. */ -#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */ -#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */ -#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ -#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ - -/* Register: RADIO_TIFS */ -/* Description: Inter Frame Spacing in microseconds. */ - -/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */ -#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ -#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ - -/* Register: RADIO_RSSISAMPLE */ -/* Description: RSSI sample. */ - -/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */ -#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ -#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ - -/* Register: RADIO_STATE */ -/* Description: Current radio state. */ - -/* Bits 3..0 : Current radio state. */ -#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ -#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ -#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */ -#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */ -#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */ -#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */ -#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */ -#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */ -#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */ -#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */ -#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */ - -/* Register: RADIO_DATAWHITEIV */ -/* Description: Data whitening initial value. */ - -/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ -#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ -#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ - -/* Register: RADIO_DAP */ -/* Description: Device address prefix. */ - -/* Bits 15..0 : Device address prefix. */ -#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ -#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ - -/* Register: RADIO_DACNF */ -/* Description: Device address match configuration. */ - -/* Bit 15 : TxAdd for device address 7. */ -#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ -#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ - -/* Bit 14 : TxAdd for device address 6. */ -#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ -#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ - -/* Bit 13 : TxAdd for device address 5. */ -#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ -#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ - -/* Bit 12 : TxAdd for device address 4. */ -#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ -#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ - -/* Bit 11 : TxAdd for device address 3. */ -#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ -#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ - -/* Bit 10 : TxAdd for device address 2. */ -#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ -#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ - -/* Bit 9 : TxAdd for device address 1. */ -#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ -#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ - -/* Bit 8 : TxAdd for device address 0. */ -#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ -#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ - -/* Bit 7 : Enable or disable device address matching using device address 7. */ -#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ -#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ -#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */ - -/* Bit 6 : Enable or disable device address matching using device address 6. */ -#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ -#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ -#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */ - -/* Bit 5 : Enable or disable device address matching using device address 5. */ -#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ -#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ -#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */ - -/* Bit 4 : Enable or disable device address matching using device address 4. */ -#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ -#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ -#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */ - -/* Bit 3 : Enable or disable device address matching using device address 3. */ -#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ -#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ -#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */ - -/* Bit 2 : Enable or disable device address matching using device address 2. */ -#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ -#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ -#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */ - -/* Bit 1 : Enable or disable device address matching using device address 1. */ -#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ -#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ -#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */ - -/* Bit 0 : Enable or disable device address matching using device address 0. */ -#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ -#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ -#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */ - -/* Register: RADIO_OVERRIDE0 */ -/* Description: Trim value override register 0. */ - -/* Bits 31..0 : Trim value override 0. */ -#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */ -#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */ - -/* Register: RADIO_OVERRIDE1 */ -/* Description: Trim value override register 1. */ - -/* Bits 31..0 : Trim value override 1. */ -#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */ -#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */ - -/* Register: RADIO_OVERRIDE2 */ -/* Description: Trim value override register 2. */ - -/* Bits 31..0 : Trim value override 2. */ -#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */ -#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */ - -/* Register: RADIO_OVERRIDE3 */ -/* Description: Trim value override register 3. */ - -/* Bits 31..0 : Trim value override 3. */ -#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */ -#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */ - -/* Register: RADIO_OVERRIDE4 */ -/* Description: Trim value override register 4. */ - -/* Bit 31 : Enable or disable override of default trim values. */ -#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */ -#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */ -#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */ - -/* Bits 27..0 : Trim value override 4. */ -#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */ -#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */ - -/* Register: RADIO_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: RNG */ -/* Description: Random Number Generator. */ - -/* Register: RNG_SHORTS */ -/* Description: Shortcuts for the RNG. */ - -/* Bit 0 : Shortcut between VALRDY event and STOP task. */ -#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ -#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ -#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: RNG_INTENSET */ -/* Description: Interrupt enable set register */ - -/* Bit 0 : Enable interrupt on VALRDY event. */ -#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ -#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ -#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: RNG_INTENCLR */ -/* Description: Interrupt enable clear register */ - -/* Bit 0 : Disable interrupt on VALRDY event. */ -#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ -#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ -#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: RNG_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 0 : Digital error correction enable. */ -#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ -#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ -#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */ -#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */ - -/* Register: RNG_VALUE */ -/* Description: RNG random number. */ - -/* Bits 7..0 : Generated random number. */ -#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ -#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ - -/* Register: RNG_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: RTC */ -/* Description: Real time counter 0. */ - -/* Register: RTC_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 19 : Enable interrupt on COMPARE[3] event. */ -#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 18 : Enable interrupt on COMPARE[2] event. */ -#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 17 : Enable interrupt on COMPARE[1] event. */ -#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 16 : Enable interrupt on COMPARE[0] event. */ -#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on OVRFLW event. */ -#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on TICK event. */ -#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: RTC_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 19 : Disable interrupt on COMPARE[3] event. */ -#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 18 : Disable interrupt on COMPARE[2] event. */ -#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 17 : Disable interrupt on COMPARE[1] event. */ -#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 16 : Disable interrupt on COMPARE[0] event. */ -#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on OVRFLW event. */ -#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on TICK event. */ -#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: RTC_EVTEN */ -/* Description: Configures event enable routing to PPI for each RTC event. */ - -/* Bit 19 : COMPARE[3] event enable. */ -#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 18 : COMPARE[2] event enable. */ -#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 17 : COMPARE[1] event enable. */ -#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 16 : COMPARE[0] event enable. */ -#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 1 : OVRFLW event enable. */ -#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 0 : TICK event enable. */ -#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */ - -/* Register: RTC_EVTENSET */ -/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */ - -/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */ -#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */ - -/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */ -#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */ - -/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */ -#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */ - -/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */ -#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */ - -/* Bit 1 : Enable routing to PPI of OVRFLW event. */ -#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */ - -/* Bit 0 : Enable routing to PPI of TICK event. */ -#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */ - -/* Register: RTC_EVTENCLR */ -/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */ - -/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */ -#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */ -#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */ -#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */ -#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 1 : Disable routing to PPI of OVRFLW event. */ -#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 0 : Disable routing to PPI of TICK event. */ -#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */ - -/* Register: RTC_COUNTER */ -/* Description: Current COUNTER value. */ - -/* Bits 23..0 : Counter value. */ -#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ -#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ - -/* Register: RTC_PRESCALER */ -/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */ - -/* Bits 11..0 : RTC PRESCALER value. */ -#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ -#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ - -/* Register: RTC_CC */ -/* Description: Capture/compare registers. */ - -/* Bits 23..0 : Compare value. */ -#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ -#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ - -/* Register: RTC_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: SPI */ -/* Description: SPI master 0. */ - -/* Register: SPI_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on READY event. */ -#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ -#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: SPI_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on READY event. */ -#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ -#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: SPI_ENABLE */ -/* Description: Enable SPI. */ - -/* Bits 2..0 : Enable or disable SPI. */ -#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */ -#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */ - -/* Register: SPI_RXD */ -/* Description: RX data. */ - -/* Bits 7..0 : RX data from last transfer. */ -#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ -#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ - -/* Register: SPI_TXD */ -/* Description: TX data. */ - -/* Bits 7..0 : TX data for next transfer. */ -#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ -#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ - -/* Register: SPI_FREQUENCY */ -/* Description: SPI frequency */ - -/* Bits 31..0 : SPI data rate. */ -#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ -#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */ -#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */ -#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */ -#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */ -#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */ -#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */ -#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */ - -/* Register: SPI_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 2 : Serial clock (SCK) polarity. */ -#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ -#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ -#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ -#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ - -/* Bit 1 : Serial clock (SCK) phase. */ -#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ -#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ -#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ -#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ - -/* Bit 0 : Bit order. */ -#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ -#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ -#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ -#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ - -/* Register: SPI_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: SPIM */ -/* Description: SPI master with easyDMA 1. */ - -/* Register: SPIM_SHORTS */ -/* Description: Shortcuts for SPIM. */ - -/* Bit 17 : Shortcut between END event and START task. */ -#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ -#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ -#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ -#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: SPIM_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 19 : Enable interrupt on STARTED event. */ -#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ -#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 8 : Enable interrupt on ENDTX event. */ -#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ -#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 6 : Enable interrupt on END event. */ -#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ -#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 4 : Enable interrupt on ENDRX event. */ -#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ -#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on STOPPED event. */ -#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: SPIM_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 19 : Disable interrupt on STARTED event. */ -#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ -#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 8 : Disable interrupt on ENDTX event. */ -#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ -#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 6 : Disable interrupt on END event. */ -#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ -#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 4 : Disable interrupt on ENDRX event. */ -#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ -#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on STOPPED event. */ -#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: SPIM_ENABLE */ -/* Description: Enable SPIM. */ - -/* Bits 3..0 : Enable or disable SPIM. */ -#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */ -#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */ - -/* Register: SPIM_FREQUENCY */ -/* Description: SPI frequency. */ - -/* Bits 31..0 : SPI master data rate. */ -#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ -#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */ -#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ -#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */ -#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */ -#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */ -#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */ -#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */ - -/* Register: SPIM_RXD_PTR */ -/* Description: Data pointer. */ - -/* Bits 31..0 : Data pointer. */ -#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: SPIM_RXD_MAXCNT */ -/* Description: Maximum number of buffer bytes to receive. */ - -/* Bits 7..0 : Maximum number of buffer bytes to receive. */ -#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: SPIM_RXD_AMOUNT */ -/* Description: Number of bytes received in the last transaction. */ - -/* Bits 7..0 : Number of bytes received in the last transaction. */ -#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: SPIM_TXD_PTR */ -/* Description: Data pointer. */ - -/* Bits 31..0 : Data pointer. */ -#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: SPIM_TXD_MAXCNT */ -/* Description: Maximum number of buffer bytes to send. */ - -/* Bits 7..0 : Maximum number of buffer bytes to send. */ -#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: SPIM_TXD_AMOUNT */ -/* Description: Number of bytes sent in the last transaction. */ - -/* Bits 7..0 : Number of bytes sent in the last transaction. */ -#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: SPIM_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 2 : Serial clock (SCK) polarity. */ -#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ -#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ -#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ -#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ - -/* Bit 1 : Serial clock (SCK) phase. */ -#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ -#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ -#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ -#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ - -/* Bit 0 : Bit order. */ -#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ -#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ -#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ -#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ - -/* Register: SPIM_ORC */ -/* Description: Over-read character. */ - -/* Bits 7..0 : Over-read character. */ -#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ -#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ - -/* Register: SPIM_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: SPIS */ -/* Description: SPI slave 1. */ - -/* Register: SPIS_SHORTS */ -/* Description: Shortcuts for SPIS. */ - -/* Bit 2 : Shortcut between END event and the ACQUIRE task. */ -#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ -#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ -#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */ -#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: SPIS_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 10 : Enable interrupt on ACQUIRED event. */ -#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ -#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ -#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on END event. */ -#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ -#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: SPIS_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 10 : Disable interrupt on ACQUIRED event. */ -#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ -#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ -#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on END event. */ -#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ -#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: SPIS_SEMSTAT */ -/* Description: Semaphore status. */ - -/* Bits 1..0 : Semaphore status. */ -#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ -#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ -#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */ -#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */ -#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */ -#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */ - -/* Register: SPIS_STATUS */ -/* Description: Status from last transaction. */ - -/* Bit 1 : RX buffer overflow detected, and prevented. */ -#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ -#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ -#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */ -#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */ -#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */ - -/* Bit 0 : TX buffer overread detected, and prevented. */ -#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ -#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ -#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */ -#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */ -#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */ - -/* Register: SPIS_ENABLE */ -/* Description: Enable SPIS. */ - -/* Bits 2..0 : Enable or disable SPIS. */ -#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */ -#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */ - -/* Register: SPIS_MAXRX */ -/* Description: Maximum number of bytes in the receive buffer. */ - -/* Bits 7..0 : Maximum number of bytes in the receive buffer. */ -#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */ -#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */ - -/* Register: SPIS_AMOUNTRX */ -/* Description: Number of bytes received in last granted transaction. */ - -/* Bits 7..0 : Number of bytes received in last granted transaction. */ -#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */ -#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */ - -/* Register: SPIS_MAXTX */ -/* Description: Maximum number of bytes in the transmit buffer. */ - -/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */ -#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */ -#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */ - -/* Register: SPIS_AMOUNTTX */ -/* Description: Number of bytes transmitted in last granted transaction. */ - -/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */ -#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */ -#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */ - -/* Register: SPIS_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 2 : Serial clock (SCK) polarity. */ -#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ -#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ -#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ -#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ - -/* Bit 1 : Serial clock (SCK) phase. */ -#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ -#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ -#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ -#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ - -/* Bit 0 : Bit order. */ -#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ -#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ -#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ -#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ - -/* Register: SPIS_DEF */ -/* Description: Default character. */ - -/* Bits 7..0 : Default character. */ -#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ -#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ - -/* Register: SPIS_ORC */ -/* Description: Over-read character. */ - -/* Bits 7..0 : Over-read character. */ -#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ -#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ - -/* Register: SPIS_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: TEMP */ -/* Description: Temperature Sensor. */ - -/* Register: TEMP_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 0 : Enable interrupt on DATARDY event. */ -#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ -#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ -#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: TEMP_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 0 : Disable interrupt on DATARDY event. */ -#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ -#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ -#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: TEMP_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: TIMER */ -/* Description: Timer 0. */ - -/* Register: TIMER_SHORTS */ -/* Description: Shortcuts for Timer. */ - -/* Bit 11 : Shortcut between CC[3] event and the STOP task. */ -#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ -#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ -#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 10 : Shortcut between CC[2] event and the STOP task. */ -#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ -#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ -#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 9 : Shortcut between CC[1] event and the STOP task. */ -#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ -#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ -#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 8 : Shortcut between CC[0] event and the STOP task. */ -#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ -#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ -#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: TIMER_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 19 : Enable interrupt on COMPARE[3] */ -#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 18 : Enable interrupt on COMPARE[2] */ -#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 17 : Enable interrupt on COMPARE[1] */ -#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 16 : Enable interrupt on COMPARE[0] */ -#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: TIMER_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 19 : Disable interrupt on COMPARE[3] */ -#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 18 : Disable interrupt on COMPARE[2] */ -#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 17 : Disable interrupt on COMPARE[1] */ -#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 16 : Disable interrupt on COMPARE[0] */ -#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: TIMER_MODE */ -/* Description: Timer Mode selection. */ - -/* Bit 0 : Select Normal or Counter mode. */ -#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */ -#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */ - -/* Register: TIMER_BITMODE */ -/* Description: Sets timer behaviour. */ - -/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */ -#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ -#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ -#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */ -#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */ -#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */ -#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */ - -/* Register: TIMER_PRESCALER */ -/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */ - -/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */ -#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ -#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ - -/* Register: TIMER_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: TWI */ -/* Description: Two-wire interface master 0. */ - -/* Register: TWI_SHORTS */ -/* Description: Shortcuts for TWI. */ - -/* Bit 1 : Shortcut between BB event and the STOP task. */ -#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ -#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ -#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Shortcut between BB event and the SUSPEND task. */ -#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ -#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ -#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */ -#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: TWI_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 18 : Enable interrupt on SUSPENDED event. */ -#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ -#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 14 : Enable interrupt on BB event. */ -#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ -#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ -#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 9 : Enable interrupt on ERROR event. */ -#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 7 : Enable interrupt on TXDSENT event. */ -#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ -#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ -#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on READY event. */ -#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ -#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ -#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on STOPPED event. */ -#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: TWI_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 18 : Disable interrupt on SUSPENDED event. */ -#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ -#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 14 : Disable interrupt on BB event. */ -#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ -#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ -#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 9 : Disable interrupt on ERROR event. */ -#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 7 : Disable interrupt on TXDSENT event. */ -#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ -#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ -#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on RXDREADY event. */ -#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ -#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ -#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on STOPPED event. */ -#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: TWI_ERRORSRC */ -/* Description: Two-wire error source. Write error field to 1 to clear error. */ - -/* Bit 2 : NACK received after sending a data byte. */ -#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ -#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ -#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */ -#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */ -#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 1 : NACK received after sending the address. */ -#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ -#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ -#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */ -#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */ -#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */ -#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ -#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ -#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ -#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ - -/* Register: TWI_ENABLE */ -/* Description: Enable two-wire master. */ - -/* Bits 2..0 : Enable or disable W2M */ -#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */ -#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */ - -/* Register: TWI_RXD */ -/* Description: RX data register. */ - -/* Bits 7..0 : RX data from last transfer. */ -#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ -#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ - -/* Register: TWI_TXD */ -/* Description: TX data register. */ - -/* Bits 7..0 : TX data for next transfer. */ -#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ -#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ - -/* Register: TWI_FREQUENCY */ -/* Description: Two-wire frequency. */ - -/* Bits 31..0 : Two-wire master clock frequency. */ -#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ -#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */ -#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ -#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */ - -/* Register: TWI_ADDRESS */ -/* Description: Address used in the two-wire transfer. */ - -/* Bits 6..0 : Two-wire address. */ -#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ -#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ - -/* Register: TWI_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: UART */ -/* Description: Universal Asynchronous Receiver/Transmitter. */ - -/* Register: UART_SHORTS */ -/* Description: Shortcuts for UART. */ - -/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */ -#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ -#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ -#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */ -#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Shortcut between CTS event and the STARTRX task. */ -#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ -#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ -#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */ -#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: UART_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 17 : Enable interrupt on RXTO event. */ -#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ -#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 9 : Enable interrupt on ERROR event. */ -#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 7 : Enable interrupt on TXRDY event. */ -#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on RXRDY event. */ -#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on NCTS event. */ -#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ -#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on CTS event. */ -#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ -#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: UART_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 17 : Disable interrupt on RXTO event. */ -#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ -#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 9 : Disable interrupt on ERROR event. */ -#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 7 : Disable interrupt on TXRDY event. */ -#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on RXRDY event. */ -#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on NCTS event. */ -#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ -#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on CTS event. */ -#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ -#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: UART_ERRORSRC */ -/* Description: Error source. Write error field to 1 to clear error. */ - -/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */ -#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ -#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ -#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */ -#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */ -#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */ -#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ -#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ -#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */ -#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */ -#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */ -#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ -#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ -#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */ -#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */ -#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */ -#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ -#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ -#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ -#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ - -/* Register: UART_ENABLE */ -/* Description: Enable UART and acquire IOs. */ - -/* Bits 2..0 : Enable or disable UART and acquire IOs. */ -#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */ -#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */ - -/* Register: UART_RXD */ -/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */ - -/* Bits 7..0 : RX data from previous transfer. Double buffered. */ -#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ -#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ - -/* Register: UART_TXD */ -/* Description: TXD register. */ - -/* Bits 7..0 : TX data for transfer. */ -#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ -#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ - -/* Register: UART_BAUDRATE */ -/* Description: UART Baudrate. */ - -/* Bits 31..0 : UART baudrate. */ -#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ -#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ -#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */ - -/* Register: UART_CONFIG */ -/* Description: Configuration of parity and hardware flow control register. */ - -/* Bits 3..1 : Include parity bit. */ -#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ -#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ -#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */ -#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */ - -/* Bit 0 : Hardware flow control. */ -#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ -#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ -#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */ -#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */ - -/* Register: UART_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: UICR */ -/* Description: User Information Configuration. */ - -/* Register: UICR_RBPCONF */ -/* Description: Readback protection configuration. */ - -/* Bits 15..8 : Readback protect all code in the device. */ -#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */ -#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */ -#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */ -#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */ - -/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */ -#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */ -#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */ -#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */ -#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */ - -/* Register: UICR_XTALFREQ */ -/* Description: Reset value for CLOCK XTALFREQ register. */ - -/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */ -#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ -#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ -#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */ -#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */ - -/* Register: UICR_FWID */ -/* Description: Firmware ID. */ - -/* Bits 15..0 : Identification number for the firmware loaded into the chip. */ -#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */ -#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */ - - -/* Peripheral: WDT */ -/* Description: Watchdog Timer. */ - -/* Register: WDT_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 0 : Enable interrupt on TIMEOUT event. */ -#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ -#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ -#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ -#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ -#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: WDT_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 0 : Disable interrupt on TIMEOUT event. */ -#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ -#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ -#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ -#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ -#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: WDT_RUNSTATUS */ -/* Description: Watchdog running status. */ - -/* Bit 0 : Watchdog running status. */ -#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ -#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ -#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */ -#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */ - -/* Register: WDT_REQSTATUS */ -/* Description: Request status. */ - -/* Bit 7 : Request status for RR[7]. */ -#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ -#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ -#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */ - -/* Bit 6 : Request status for RR[6]. */ -#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ -#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ -#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */ - -/* Bit 5 : Request status for RR[5]. */ -#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ -#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ -#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */ - -/* Bit 4 : Request status for RR[4]. */ -#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ -#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ -#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */ - -/* Bit 3 : Request status for RR[3]. */ -#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ -#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ -#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */ - -/* Bit 2 : Request status for RR[2]. */ -#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ -#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ -#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */ - -/* Bit 1 : Request status for RR[1]. */ -#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ -#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ -#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */ - -/* Bit 0 : Request status for RR[0]. */ -#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ -#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ -#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */ - -/* Register: WDT_RREN */ -/* Description: Reload request enable. */ - -/* Bit 7 : Enable or disable RR[7] register. */ -#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ -#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ -#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */ -#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */ - -/* Bit 6 : Enable or disable RR[6] register. */ -#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ -#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ -#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */ -#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */ - -/* Bit 5 : Enable or disable RR[5] register. */ -#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ -#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ -#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */ -#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */ - -/* Bit 4 : Enable or disable RR[4] register. */ -#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ -#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ -#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */ -#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */ - -/* Bit 3 : Enable or disable RR[3] register. */ -#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ -#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ -#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */ -#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */ - -/* Bit 2 : Enable or disable RR[2] register. */ -#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ -#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ -#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */ -#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */ - -/* Bit 1 : Enable or disable RR[1] register. */ -#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ -#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ -#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */ -#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */ - -/* Bit 0 : Enable or disable RR[0] register. */ -#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ -#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ -#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */ -#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */ - -/* Register: WDT_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */ -#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ -#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ -#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */ -#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */ - -/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */ -#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ -#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ -#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */ -#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */ - -/* Register: WDT_RR */ -/* Description: Reload requests registers. */ - -/* Bits 31..0 : Reload register. */ -#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ -#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ -#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */ - -/* Register: WDT_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/*lint --flb "Leave library region" */ -#endif diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/nrf51_delay.h b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/nrf51_delay.h deleted file mode 100644 index 2a672db..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/nrf51_delay.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - Copyright (C) 2015 Stephen Caudle - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file NRF51822/nrf51_delay.h - * @brief NRF51822 Delay routines - * - * @{ - */ - -#ifndef _NRF_DELAY_H -#define _NRF_DELAY_H - -inline static void nrf_delay_us(uint32_t volatile number_of_us) __attribute__((always_inline)); -inline static void nrf_delay_us(uint32_t volatile number_of_us) -{ -register uint32_t delay asm ("r0") = number_of_us; -__asm volatile ( -".syntax unified\n" - "1:\n" - " SUBS %0, %0, #1\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " NOP\n" - " BNE 1b\n" - ".syntax divided\n" - : "+r" (delay)); -} -#endif //__NRF_DELAY_H diff --git a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/platform.mk b/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/platform.mk deleted file mode 100644 index b937e39..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/NRF51/NRF51822/platform.mk +++ /dev/null @@ -1,61 +0,0 @@ -ifeq ($(USE_SMART_BUILD),yes) -HALCONF := $(strip $(shell cat halconf.h halconf_community.h 2>/dev/null | egrep -e "define")) - -# List of all the NRF51x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_st_lld.c - -ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_pal_lld.c -endif -ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_serial_lld.c -endif -ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_spi_lld.c -endif -ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_ext_lld.c -endif -ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.c -endif -ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_adc_lld.c -endif -ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.c -endif -ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.c -endif -ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_rng_lld.c -endif -ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c -endif -else -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_pal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_serial_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_st_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_spi_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_ext_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_adc_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_rng_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c -endif - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ - ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822 - - diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c deleted file mode 100644 index 601deca..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c +++ /dev/null @@ -1,328 +0,0 @@ -/* - ChibiOS - Copyright (C) 2015 Michael D. Spradling - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/CRCv1/crc_lld.c - * @brief STM32 CRC subsystem low level driver source. - * - * @addtogroup CRC - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__) - -/** - * Allow CRC Software override for ST drivers. Some ST CRC implimentations - * have limited capabilities. - */ -#if CRCSW_USE_CRC1 != TRUE - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief CRC default configuration. - */ -static const CRCConfig default_config = { - .poly_size = 32, - .poly = 0x04C11DB7, - .initial_val = 0xFFFFFFFF, - .final_val = 0xFFFFFFFF, - .reflect_data = 1, - .reflect_remainder = 1 -}; - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief CRC1 driver identifier.*/ -#if STM32_CRC_USE_CRC1 || defined(__DOXYGEN__) -CRCDriver CRCD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -void _crc_lld_calc_byte(CRCDriver *crcp, uint8_t data) { - __IO uint8_t *crc8 = (__IO uint8_t*)&(crcp->crc->DR); - *crc8 = data; -} - -/* - * @brief Returns calculated CRC from last reset - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] data data to be added to crc - * - * @notapi - */ -void _crc_lld_calc_halfword(CRCDriver *crcp, uint16_t data) { - __IO uint16_t *crc16 = (__IO uint16_t*)&(crcp->crc->DR); - *crc16 = data; -} - -/* - * @brief Returns calculated CRC from last reset - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] data data to be added to crc - * - * @notapi - */ -void _crc_lld_calc_word(CRCDriver *crcp, uint32_t data) { - crcp->crc->DR = data; -} - - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief Shared end-of-rx service routine. - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -#if CRC_USE_DMA == TRUE -static void crc_lld_serve_interrupt(CRCDriver *crcp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_CRC_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_CRC_DMA_ERROR_HOOK(crcp); - } -#else - (void)flags; -#endif - - /* Stop everything.*/ - dmaStreamDisable(crcp->dma); - - /* Portable CRC ISR code defined in the high level driver, note, it is - a macro.*/ - _crc_isr_code(crcp, crcp->crc->DR ^ crcp->config->final_val); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level CRC driver initialization. - * - * @notapi - */ -void crc_lld_init(void) { - crcObjectInit(&CRCD1); - CRCD1.crc = CRC; -#if CRC_USE_DMA == TRUE - CRCD1.dma = STM32_CRC_CRC1_DMA_STREAM; -#endif -} - -/** - * @brief Configures and activates the CRC peripheral. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @notapi - */ -void crc_lld_start(CRCDriver *crcp) { - if (crcp->config == NULL) - crcp->config = &default_config; - - rccEnableCRC(FALSE); - -#if STM32_CRC_PROGRAMMABLE == TRUE - crcp->crc->INIT = crcp->config->initial_val; - crcp->crc->POL = crcp->config->poly; - - crcp->crc->CR = 0; - switch(crcp->config->poly_size) { - case 32: - break; - case 16: - crcp->crc->CR |= CRC_CR_POLYSIZE_0; - break; - case 8: - crcp->crc->CR |= CRC_CR_POLYSIZE_1; - break; - case 7: - crcp->crc->CR |= CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0; - break; - default: - osalDbgAssert(false, "hardware doesn't support polynomial size"); - break; - }; - if (crcp->config->reflect_data) { - crcp->crc->CR |= CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0; - } - if (crcp->config->reflect_remainder) { - crcp->crc->CR |= CRC_CR_REV_OUT; - } -#else - osalDbgAssert(crcp->config->initial_val != default_config.initial_val, - "hardware doesn't support programmable initial value"); - osalDbgAssert(crcp->config->poly_size != default_config.poly_size, - "hardware doesn't support programmable polynomial size"); - osalDbgAssert(crcp->config->poly != default_config.poly, - "hardware doesn't support programmable polynomial"); - osalDbgAssert(crcp->config->reflect_data != default_config.reflect_data, - "hardware doesn't support reflect of input data"); - osalDbgAssert(crcp->config->reflect_remainder != default_config.reflect_remainder, - "hardware doesn't support reflect of output remainder"); -#endif - -#if CRC_USE_DMA == TRUE -#if STM32_CRC_PROGRAMMABLE == TRUE - crcp->dmamode = STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_PINC | - STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE | - STM32_DMA_CR_PL(STM32_CRC_CRC1_DMA_PRIORITY); -#else - crcp->dmamode = STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_PINC | - STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD | - STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE | - STM32_DMA_CR_PL(STM32_CRC_CRC1_DMA_PRIORITY); -#endif - { - bool b; - b = dmaStreamAllocate(crcp->dma, - STM32_CRC_CRC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)crc_lld_serve_interrupt, - (void *)crcp); - osalDbgAssert(!b, "stream already allocated"); - } -#endif -} - - -/** - * @brief Deactivates the CRC peripheral. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @notapi - */ -void crc_lld_stop(CRCDriver *crcp) { -#if CRC_USE_DMA == TRUE - dmaStreamRelease(crcp->dma); -#else - (void)crcp; -#endif - rccDisableCRC(FALSE); -} - -/** - * @brief Resets current CRC calculation. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @notapi - */ -void crc_lld_reset(CRCDriver *crcp) { - crcp->crc->CR |= CRC_CR_RESET; -} - -/** - * @brief Returns calculated CRC from last reset - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] n size of buf in bytes - * @param[in] buf @p buffer location - * - * @notapi - */ -uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) { -#if CRC_USE_DMA == TRUE - crc_lld_start_calc(crcp, n, buf); - (void) osalThreadSuspendS(&crcp->thread); -#else - /** - * BUG: Only peform byte writes to DR reg if reflect_data is disabled. - * The STM32 hardware unit seems to incorrectly calculate CRCs when all - * of the following is true: reflect_data(rev_in) is 0, dma is disable, and - * you are writing more than a byte into the DR register. - */ - if (crcp->config->reflect_data != 0) { - while(n > 3) { - _crc_lld_calc_word(crcp, *(uint32_t*)buf); - buf+=4; - n-=4; - } - } - -#if STM32_CRC_PROGRAMMABLE == TRUE - /* Programmable CRC units allow variable register width accesses.*/ - - /** - * BUG: Only peform byte writes to DR reg if reflect_data is disabled. - * The STM32 hardware unit seems to incorrectly calculate CRCs when all - * of the following is true: reflect_data(rev_in) is 0, dma is disable, and - * you are writing more than a byte into the DR register. - */ - if (crcp->config->reflect_data != 0) { - while(n > 1) { - _crc_lld_calc_halfword(crcp, *(uint16_t*)buf); - buf+=2; - n-=2; - } - } - - while(n > 0) { - _crc_lld_calc_byte(crcp, *(uint8_t*)buf); - buf++; - n--; - } -#else - osalDbgAssert(n != 0, "STM32 CRC Unit only supports WORD accesses"); -#endif - -#endif - return crcp->crc->DR ^ crcp->config->final_val; -} - -#if CRC_USE_DMA == TRUE -void crc_lld_start_calc(CRCDriver *crcp, size_t n, const void *buf) { - dmaStreamSetPeripheral(crcp->dma, buf); - dmaStreamSetMemory0(crcp->dma, &crcp->crc->DR); -#if STM32_CRC_PROGRAMMABLE == TRUE - dmaStreamSetTransactionSize(crcp->dma, n); -#else - dmaStreamSetTransactionSize(crcp->dma, (n / 4)); -#endif - dmaStreamSetMode(crcp->dma, crcp->dmamode); - - dmaStreamEnable(crcp->dma); -} -#endif - -#endif /* CRCSW_USE_CRC1 */ - -#endif /* HAL_USE_CRC */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h deleted file mode 100644 index ecdaf81..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h +++ /dev/null @@ -1,249 +0,0 @@ -/* - ChibiOS - Copyright (C) 2015 Michael D. Spradling - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/CRCv1/crc_lld.h - * @brief STM32 CRC subsystem low level driver header. - * - * @addtogroup CRC - * @{ - */ - -#ifndef _CRC_LLD_H_ -#define _CRC_LLD_H_ - -#if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__) - -/* - * This error check must occur outsite of CRCSW_USE_CRC1 to check if - * two LLD drivers are enabled at the same time - */ -#if STM32_CRC_USE_CRC1 == TRUE && \ - CRCSW_USE_CRC1 == TRUE -#error "Software CRC can't be enable with STM32_CRC_USE_CRC1" -#endif - -/** - * Allow CRC Software override for ST drivers. Some ST CRC implimentations - * have limited capabilities. - */ -#if CRCSW_USE_CRC1 != TRUE - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief CRC1 driver enable switch. - * @details If set to @p TRUE the support for CRC1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_CRC_USE_CRC1) || defined(__DOXYGEN__) -#define STM32_CRC_USE_CRC1 FALSE -#endif - -/** - * @brief CRC1 DMA priority (0..3|lowest..highest). - * @note The priority level is for CRC DMA stream. - */ -#if !defined(STM32_CRC_CRC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_CRC_CRC1_DMA_PRIORITY 2 -#endif - -/** - * @brief CRC1 DMA interrupt priority level setting. - */ -#if !defined(STM32_CRC_CRC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_CRC_CRC1_DMA_IRQ_PRIORITY 1 -#endif - -/** - * @brief CRC1 DMA STREAM to use when performing CRC calculation. - */ -#if !defined(STM32_CRC_CRC1_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_CRC_CRC1_DMA_STREAM STM32_DMA1_STREAM2 -#endif - -/** - * @brief CRC DMA error hook. - */ -#if !defined(STM32_CRC_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_CRC_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_CRC_USE_CRC1 && !STM32_HAS_CRC -#error "Hardware CRC not present in the selected device" -#error "Use CRCSW_USE_CRC1 for software implementation" -#endif - -#if CRC_USE_DMA -#if STM32_CRC_USE_CRC1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_CRC_CRC1_DMA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to CRC1" -#endif - -#if STM32_CRC_USE_CRC1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_CRC_CRC1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to CRC1" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an CRC driver. - */ -typedef struct CRCDriver CRCDriver; - -/** - * @brief CRC notification callback type - * - * @param[in] crcp pointer to the @ CRCDriver object triggering the - * callback - */ -typedef void (*crccallback_t)(CRCDriver *crcp, uint32_t crc); - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief The size of polynomial to be used for CRC. - */ - uint32_t poly_size; - /** - * @brief The coefficients of the polynomial to be used for CRC. - */ - uint32_t poly; - /** - * @brief The inital value - */ - uint32_t initial_val; - /** - * @brief The final XOR value - */ - uint32_t final_val; - /** - * @brief Reflect bit order data going into CRC - */ - bool reflect_data; - /** - * @brief Reflect bit order of final remainder - */ - bool reflect_remainder; - /* End of the mandatory fields.*/ - /** - * @brief Operation complete callback or @p NULL - */ - crccallback_t end_cb; -} CRCConfig; - - -/** - * @brief Structure representing an CRC driver. - */ -struct CRCDriver { - /** - * @brief Driver state. - */ - crcstate_t state; - /** - * @brief Current configuration data. - */ - const CRCConfig *config; -#if CRC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* CRC_USE_MUTUAL_EXCLUSION */ -#if defined(CRC_DRIVER_EXT_FIELDS) - CRC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the CRCx registers block. - */ - CRC_TypeDef *crc; - -#if CRC_USE_DMA == TRUE - /** - * @brief Waiting thread. - */ - thread_reference_t thread; - /** - * @brief CRC DMA stream - */ - const stm32_dma_stream_t *dma; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; -#endif -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_CRC_USE_CRC1 && !defined(__DOXYGEN__) -extern CRCDriver CRCD1; -#endif /* STM32_CRC_USE_CRC1 */ - -#ifdef __cplusplus -extern "C" { -#endif - void crc_lld_init(void); - void crc_lld_start(CRCDriver *crcp); - void crc_lld_stop(CRCDriver *crcp); - void crc_lld_reset(CRCDriver *crcp); - uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf); -#if CRC_USE_DMA - void crc_lld_start_calc(CRCDriver *crcp, size_t n, const void *buf); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* CRCSW_USE_CRC1 */ - -#endif /* HAL_USE_CRC */ - -#endif /* _CRC_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c deleted file mode 100644 index aba029f..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c +++ /dev/null @@ -1,3130 +0,0 @@ -/* - Copyright (C) 2013-2015 Andrea Zoppi - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file stm32_dma2d.c - * @brief DMA2D/Chrom-ART driver. - */ - -#include "ch.h" -#include "hal.h" - -#include "hal_stm32_dma2d.h" - -#if STM32_DMA2D_USE_DMA2D || defined(__DOXYGEN__) - -/* Ignore annoying warning messages for actually safe code.*/ -#if defined(__GNUC__) && !defined(__DOXYGEN__) -#pragma GCC diagnostic ignored "-Wtype-limits" -#endif - -/** - * @addtogroup dma2d - * @{ - */ - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief DMA2DD1 driver identifier.*/ -DMA2DDriver DMA2DD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Bits per pixel lookup table. - */ -static const uint8_t dma2d_bpp[DMA2D_MAX_PIXFMT_ID + 1] = { - 32, /* DMA2D_FMT_ARGB8888 */ - 24, /* DMA2D_FMT_RGB888 */ - 16, /* DMA2D_FMT_RGB565 */ - 16, /* DMA2D_FMT_ARGB1555 */ - 16, /* DMA2D_FMT_ARGB4444 */ - 8, /* DMA2D_FMT_L8 */ - 8, /* DMA2D_FMT_AL44 */ - 16, /* DMA2D_FMT_AL88 */ - 4, /* DMA2D_FMT_L4 */ - 8, /* DMA2D_FMT_A8 */ - 4 /* DMA2D_FMT_A4 */ -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @name DMA2D interrupt handlers - * @{ - */ - -/** - * @brief DMA2D global interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_DMA2D_HANDLER) { - - DMA2DDriver *const dma2dp = &DMA2DD1; - bool job_done = false; - thread_t *tp = NULL; - - OSAL_IRQ_PROLOGUE(); - - /* Handle Configuration Error ISR.*/ - if ((DMA2D->ISR & DMA2D_ISR_CEIF) && (DMA2D->CR & DMA2D_CR_CEIE)) { - if (dma2dp->config->cfgerr_isr != NULL) - dma2dp->config->cfgerr_isr(dma2dp); - job_done = true; - DMA2D->IFCR |= DMA2D_IFSR_CCEIF; - } - - /* Handle CLUT (Palette) Transfer Complete ISR.*/ - if ((DMA2D->ISR & DMA2D_ISR_CTCIF) && (DMA2D->CR & DMA2D_CR_CTCIE)) { - if (dma2dp->config->paltrfdone_isr != NULL) - dma2dp->config->paltrfdone_isr(dma2dp); - job_done = true; - DMA2D->IFCR |= DMA2D_IFSR_CCTCIF; - } - - /* Handle CLUT (Palette) Access Error ISR.*/ - if ((DMA2D->ISR & DMA2D_ISR_CAEIF) && (DMA2D->CR & DMA2D_CR_CAEIE)) { - if (dma2dp->config->palacserr_isr != NULL) - dma2dp->config->palacserr_isr(dma2dp); - job_done = true; - DMA2D->IFCR |= DMA2D_IFSR_CCAEIF; - } - - /* Handle Transfer Watermark ISR.*/ - if ((DMA2D->ISR & DMA2D_ISR_TWIF) && (DMA2D->CR & DMA2D_CR_TWIE)) { - if (dma2dp->config->trfwmark_isr != NULL) - dma2dp->config->trfwmark_isr(dma2dp); - DMA2D->IFCR |= DMA2D_IFSR_CTWIF; - } - - /* Handle Transfer Complete ISR.*/ - if ((DMA2D->ISR & DMA2D_ISR_TCIF) && (DMA2D->CR & DMA2D_CR_TCIE)) { - if (dma2dp->config->trfdone_isr != NULL) - dma2dp->config->trfdone_isr(dma2dp); - job_done = true; - DMA2D->IFCR |= DMA2D_IFSR_CTCIF; - } - - /* Handle Transfer Error ISR.*/ - if ((DMA2D->ISR & DMA2D_ISR_TEIF) && (DMA2D->CR & DMA2D_CR_TEIE)) { - if (dma2dp->config->trferr_isr != NULL) - dma2dp->config->trferr_isr(dma2dp); - job_done = true; - DMA2D->IFCR |= DMA2D_IFSR_CTEIF; - } - - if (job_done) { - osalSysLockFromISR(); - osalDbgAssert(dma2dp->state == DMA2D_ACTIVE, "invalid state"); - - #if DMA2D_USE_WAIT - /* Wake the waiting thread up.*/ - if (dma2dp->thread != NULL) { - tp = dma2dp->thread; - dma2dp->thread = NULL; - tp->u.rdymsg = MSG_OK; - chSchReadyI(tp); - } - #endif /* DMA2D_USE_WAIT */ - - dma2dp->state = DMA2D_READY; - osalSysUnlockFromISR(); - } - - OSAL_IRQ_EPILOGUE(); -} - -/** @} */ - -/** - * @name DMA2D driver-specific methods - * @{ - */ - -/** - * @brief DMA2D Driver initialization. - * @details Initializes the DMA2D subsystem and chosen drivers. Should be - * called at board initialization. - * - * @init - */ -void dma2dInit(void) { - - /* Reset the DMA2D hardware module.*/ - rccResetDMA2D(); - - /* Enable the DMA2D clock.*/ - rccEnableDMA2D(false); - - /* Driver struct initialization.*/ - dma2dObjectInit(&DMA2DD1); - DMA2DD1.state = DMA2D_STOP; -} - -/** - * @brief Initializes the standard part of a @p DMA2DDriver structure. - * - * @param[out] dma2dp pointer to the @p DMA2DDriver object - * - * @init - */ -void dma2dObjectInit(DMA2DDriver *dma2dp) { - - osalDbgCheck(dma2dp == &DMA2DD1); - - dma2dp->state = DMA2D_UNINIT; - dma2dp->config = NULL; -#if DMA2D_USE_WAIT - dma2dp->thread = NULL; -#endif /* DMA2D_USE_WAIT */ -#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION) -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxObjectInit(&dma2dp->lock); -#else - chSemObjectInit(&dma2dp->lock, 1); -#endif -#endif /* (TRUE == DMA2D_USE_MUTUAL_EXCLUSION) */ -} - -/** - * @brief Get the driver state. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @retun driver state - * - * @iclass - */ -dma2d_state_t dma2dGetStateI(DMA2DDriver *dma2dp) { - - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheckClassI(); - - return dma2dp->state; -} - -/** - * @brief Get the driver state. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @retun driver state - * - * @api - */ -dma2d_state_t dma2dGetState(DMA2DDriver *dma2dp) { - - dma2d_state_t state; - chSysLock(); - state = dma2dGetStateI(dma2dp); - chSysUnlock(); - return state; -} - -/** - * @brief Configures and activates the DMA2D peripheral. - * @pre DMA2D is stopped. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] configp pointer to the @p DMA2DConfig object - * - * @api - */ -void dma2dStart(DMA2DDriver *dma2dp, const DMA2DConfig *configp) { - - chSysLock(); - - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(configp != NULL); - osalDbgAssert(dma2dp->state == DMA2D_STOP, "invalid state"); - - dma2dp->config = configp; - - /* Turn off the controller and its interrupts.*/ - DMA2D->CR = 0; - - /* Enable interrupts, except Line Watermark.*/ - nvicEnableVector(STM32_DMA2D_NUMBER, STM32_DMA2D_IRQ_PRIORITY); - - DMA2D->CR = (DMA2D_CR_CEIE | DMA2D_CR_CTCIE | DMA2D_CR_CAEIE | - DMA2D_CR_TCIE | DMA2D_CR_TEIE); - - dma2dp->state = DMA2D_READY; - chSysUnlock(); -} - -/** - * @brief Deactivates the DMA2D peripheral. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dStop(DMA2DDriver *dma2dp) { - - chSysLock(); - - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "invalid state"); -#if DMA2D_USE_WAIT - osalDbgAssert(dma2dp->thread == NULL, "still waiting"); -#endif /* DMA2D_USE_WAIT */ - - dma2dp->state = DMA2D_STOP; - chSysUnlock(); -} - -#if DMA2D_USE_MUTUAL_EXCLUSION - -/** - * @brief Gains exclusive access to the DMA2D module. - * @details This function tries to gain ownership to the DMA2D module, if the - * module is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p DMA2D_USE_MUTUAL_EXCLUSION must be enabled. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @sclass - */ -void dma2dAcquireBusS(DMA2DDriver *dma2dp) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxLockS(&dma2dp->lock); -#else - chSemWaitS(&dma2dp->lock); -#endif -} - -/** - * @brief Gains exclusive access to the DMA2D module. - * @details This function tries to gain ownership to the DMA2D module, if the - * module is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p DMA2D_USE_MUTUAL_EXCLUSION must be enabled. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dAcquireBus(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dAcquireBusS(dma2dp); - chSysUnlock(); -} - -/** - * @brief Releases exclusive access to the DMA2D module. - * @pre In order to use this function the option - * @p DMA2D_USE_MUTUAL_EXCLUSION must be enabled. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @sclass - */ -void dma2dReleaseBusS(DMA2DDriver *dma2dp) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxUnlockS(&dma2dp->lock); -#else - chSemSignalI(&dma2dp->lock); -#endif -} - -/** - * @brief Releases exclusive access to the DMA2D module. - * @pre In order to use this function the option - * @p DMA2D_USE_MUTUAL_EXCLUSION must be enabled. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dReleaseBus(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dReleaseBusS(dma2dp); - chSysUnlock(); -} - -#endif /* DMA2D_USE_MUTUAL_EXCLUSION */ - -/** @} */ - -/** - * @name DMA2D global methods - * @{ - */ - -/** - * @brief Get watermark position. - * @details Gets the watermark line position. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return watermark line position - * - * @iclass - */ -uint16_t dma2dGetWatermarkPosI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (uint16_t)(DMA2D->LWR & DMA2D_LWR_LW); -} - -/** - * @brief Get watermark position. - * @details Gets the watermark line position. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return watermark line position - * - * @api - */ -uint16_t dma2dGetWatermarkPos(DMA2DDriver *dma2dp) { - - uint16_t line; - chSysLock(); - line = dma2dGetWatermarkPosI(dma2dp); - chSysUnlock(); - return line; -} - -/** - * @brief Set watermark position. - * @details Sets the watermark line position. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] line watermark line position - * - * @iclass - */ -void dma2dSetWatermarkPosI(DMA2DDriver *dma2dp, uint16_t line) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - (void)dma2dp; - - DMA2D->LWR = ((DMA2D->LWR & ~DMA2D_LWR_LW) | - ((uint32_t)line & DMA2D_LWR_LW)); -} - -/** - * @brief Set watermark position. - * @details Sets the watermark line position. - * @note The interrupt is invoked after the last pixel of the watermark line - * is written. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] line watermark line position - * - * @iclass - */ -void dma2dSetWatermarkPos(DMA2DDriver *dma2dp, uint16_t line) { - - chSysLock(); - dma2dSetWatermarkPosI(dma2dp, line); - chSysUnlock(); -} - -/** - * @brief Watermark interrupt enabled. - * @details Tells whether the watermark interrupt is enabled. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return enabled - * - * @iclass - */ -bool dma2dIsWatermarkEnabledI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (DMA2D->CR & DMA2D_CR_TWIE) != 0; -} - -/** - * @brief Watermark interrupt enabled. - * @details Tells whether the watermark interrupt is enabled. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return enabled - * - * @api - */ -bool dma2dIsWatermarkEnabled(DMA2DDriver *dma2dp) { - - bool enabled; - chSysLock(); - enabled = dma2dIsWatermarkEnabledI(dma2dp); - chSysUnlock(); - return enabled; -} - -/** - * @brief Enable watermark interrupt. - * @details Enables the watermark interrupt. The interrupt is invoked after the - * last pixel of the watermark line is written to the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dEnableWatermarkI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - DMA2D->CR |= DMA2D_CR_TWIE; -} - -/** - * @brief Enable watermark interrupt. - * @details Enables the watermark interrupt. The interrupt is invoked after the - * last pixel of the watermark line is written to the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dEnableWatermark(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dEnableWatermarkI(dma2dp); - chSysUnlock(); -} - -/** - * @brief Disable watermark interrupt. - * @details Disables the watermark interrupt. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dDisableWatermarkI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - DMA2D->CR &= ~DMA2D_CR_TWIE; -} - -/** - * @brief Disable watermark interrupt. - * @details Disables the watermark interrupt. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dDisableWatermark(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dDisableWatermarkI(dma2dp); - chSysUnlock(); -} - -/** - * @brief Get dead time cycles. - * @details Gets the minimum dead time DMA2D clock cycles between DMA2D - * transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return dead time, in DMA2D clock cycles - * - * @iclass - */ -uint32_t dma2dGetDeadTimeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (DMA2D->AMTCR & DMA2D_AMTCR_DT) >> 8; -} - -/** - * @brief Get dead time cycles. - * @details Gets the minimum dead time DMA2D clock cycles between DMA2D - * transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return dead time, in DMA2D clock cycles - * - * @api - */ -uint32_t dma2dGetDeadTime(DMA2DDriver *dma2dp) { - - uint32_t cycles; - chSysLock(); - cycles = dma2dGetDeadTimeI(dma2dp); - chSysUnlock(); - return cycles; -} - -/** - * @brief Set dead time cycles. - * @details Sets the minimum dead time DMA2D clock cycles between DMA2D - * transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cycles dead time, in DMA2D clock cycles - * - * @iclass - */ -void dma2dSetDeadTimeI(DMA2DDriver *dma2dp, uint32_t cycles) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(cycles <= DMA2D_MAX_DEADTIME_CYCLES, "bounds"); - (void)dma2dp; - - DMA2D->AMTCR = ((DMA2D->AMTCR & ~DMA2D_AMTCR_DT) | - ((cycles << 8) & DMA2D_AMTCR_DT)); -} - -/** - * @brief Set dead time cycles. - * @details Sets the minimum dead time DMA2D clock cycles between DMA2D - * transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cycles dead time, in DMA2D clock cycles - * - * @api - */ -void dma2dSetDeadTime(DMA2DDriver *dma2dp, uint32_t cycles) { - - chSysLock(); - dma2dSetDeadTimeI(dma2dp, cycles); - chSysUnlock(); -} - -/** - * @brief Dead time enabled. - * @details Tells whether the dead time between DMA2D transactions is enabled. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return enabled - * - * @iclass - */ -bool dma2dIsDeadTimeEnabledI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (DMA2D->AMTCR & DMA2D_AMTCR_EN) != 0; -} - -/** - * @brief Dead time enabled. - * @details Tells whether the dead time between DMA2D transactions is enabled. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return enabled - * - * @api - */ -bool dma2dIsDeadTimeEnabled(DMA2DDriver *dma2dp) { - - bool enabled; - chSysLock(); - enabled = dma2dIsDeadTimeEnabledI(dma2dp); - chSysUnlock(); - return enabled; -} - -/** - * @brief Enable dead time. - * @details Enables the dead time between DMA2D transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dEnableDeadTimeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - DMA2D->AMTCR |= DMA2D_AMTCR_EN; -} - -/** - * @brief Enable dead time. - * @details Enables the dead time between DMA2D transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dEnableDeadTime(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dEnableDeadTimeI(dma2dp); - chSysUnlock(); -} - -/** - * @brief Disable dead time. - * @details Disables the dead time between DMA2D transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dDisableDeadTimeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - DMA2D->AMTCR &= ~DMA2D_AMTCR_EN; -} - -/** - * @brief Disable dead time. - * @details Disables the dead time between DMA2D transactions. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dDisableDeadTime(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dDisableDeadTimeI(dma2dp); - chSysUnlock(); -} - -/** @} */ - -/** - * @name DMA2D job (transaction) methods - * @{ - */ - -/** - * @brief Get job mode. - * @details Gets the job mode. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return job mode - * - * @iclass - */ -dma2d_jobmode_t dma2dJobGetModeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_jobmode_t)(DMA2D->CR & DMA2D_CR_MODE); -} - -/** - * @brief Get job mode. - * @details Gets the job mode. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return job mode - * - * @api - */ -dma2d_jobmode_t dma2dJobGetMode(DMA2DDriver *dma2dp) { - - dma2d_jobmode_t mode; - chSysLock(); - mode = dma2dJobGetModeI(dma2dp); - chSysUnlock(); - return mode; -} - -/** - * @brief Set job mode. - * @details Sets the job mode. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] mode job mode - * - * @iclass - */ -void dma2dJobSetModeI(DMA2DDriver *dma2dp, dma2d_jobmode_t mode) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert((mode & ~DMA2D_CR_MODE) == 0, "bounds"); - (void)dma2dp; - - DMA2D->CR = ((DMA2D->CR & ~DMA2D_CR_MODE) | - ((uint32_t)mode & DMA2D_CR_MODE)); -} - -/** - * @brief Set job mode. - * @details Sets the job mode. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] mode job mode - * - * @api - */ -void dma2dJobSetMode(DMA2DDriver *dma2dp, dma2d_jobmode_t mode) { - - chSysLock(); - dma2dJobSetModeI(dma2dp, mode); - chSysUnlock(); -} - -/** - * @brief Get job size. - * @details Gets the job size. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] widthp pointer to the job width, in pixels - * @param[out] heightp pointer to the job height, in pixels - * - * @iclass - */ -void dma2dJobGetSizeI(DMA2DDriver *dma2dp, - uint16_t *widthp, uint16_t *heightp) { - - uint32_t r; - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(widthp != NULL); - osalDbgCheck(heightp != NULL); - (void)dma2dp; - - r = DMA2D->NLR; - *widthp = (uint16_t)((r & DMA2D_NLR_PL) >> 16); - *heightp = (uint16_t)((r & DMA2D_NLR_NL) >> 0); -} - -/** - * @brief Get job size. - * @details Gets the job size. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] widthp pointer to the job width, in pixels - * @param[out] heightp pointer to the job height, in pixels - * - * @api - */ -void dma2dJobGetSize(DMA2DDriver *dma2dp, - uint16_t *widthp, uint16_t *heightp) { - - chSysLock(); - dma2dJobGetSizeI(dma2dp, widthp, heightp); - chSysUnlock(); -} - -/** - * @brief Set job size. - * @details Sets the job size. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] widthp job width, in pixels - * @param[in] heightp job height, in pixels - * - * @iclass - */ -void dma2dJobSetSizeI(DMA2DDriver *dma2dp, uint16_t width, uint16_t height) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(width <= DMA2D_MAX_WIDTH, "bounds"); - osalDbgAssert(height <= DMA2D_MAX_HEIGHT, "bounds"); - (void)dma2dp; - - DMA2D->NLR = ((((uint32_t)width << 16) & DMA2D_NLR_PL) | - (((uint32_t)height << 0) & DMA2D_NLR_NL)); -} - -/** - * @brief Set job size. - * @details Sets the job size. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] widthp job width, in pixels - * @param[in] heightp job height, in pixels - * - * @api - */ -void dma2dJobSetSize(DMA2DDriver *dma2dp, uint16_t width, uint16_t height) { - - chSysLock(); - dma2dJobSetSizeI(dma2dp, width, height); - chSysUnlock(); -} - -/** - * @brief Job executing. - * @details Tells whether a job (transaction) is active or paused. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return executing - * - * @iclass - */ -bool dma2dJobIsExecutingI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - - return dma2dp->state > DMA2D_READY; -} - -/** - * @brief Job executing. - * @details Tells whether a job (transaction) is active or paused. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return executing - * - * @api - */ -bool dma2dJobIsExecuting(DMA2DDriver *dma2dp) { - - bool executing; - chSysLock(); - executing = dma2dJobIsExecutingI(dma2dp); - chSysUnlock(); - return executing; -} - -/** - * @brief Start job. - * @details The job is started, and the DMA2D is set to active. - * @note Should there be invalid parameters, the appropriate interrupt - * handler will be invoked, and the DMA2D set back to ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dJobStartI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - - dma2dp->state = DMA2D_ACTIVE; - DMA2D->CR |= DMA2D_CR_START; -} - -/** - * @brief Start job. - * @details The job is started, and the DMA2D is set to active. - * @note Should there be invalid parameters, the appropriate interrupt - * handler will be invoked, and the DMA2D set back to ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dJobStart(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dJobStartI(dma2dp); - chSysUnlock(); -} - -/** - * @brief Execute job. - * @details Starts the job and waits for its completion, synchronously. - * @note Should there be invalid parameters, the appropriate interrupt - * handler will be invoked, and the DMA2D set back to ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @sclass - */ -void dma2dJobExecuteS(DMA2DDriver *dma2dp) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - - dma2dJobStartI(dma2dp); -#if DMA2D_USE_WAIT - dma2dp->thread = chThdGetSelfX(); - chSchGoSleepS(CH_STATE_SUSPENDED); -#else - while (DMA2D->CR & DMA2D_CR_START) - chSchDoYieldS(); -#endif -} - -/** - * @brief Execute job. - * @details Starts the job and waits for its completion, synchronously. - * @note Should there be invalid parameters, the appropriate interrupt - * handler will be invoked, and the DMA2D set back to ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dJobExecute(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dJobExecuteS(dma2dp); - chSysUnlock(); -} - -/** - * @brief Suspend current job. - * @details Suspends the current job. The driver is set to a paused state. - * @pre There is an active job. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dJobSuspendI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck((DMA2D->CR & DMA2D_CR_SUSP) == 0); - osalDbgAssert(dma2dp->state == DMA2D_ACTIVE, "invalid state"); - - dma2dp->state = DMA2D_PAUSED; - DMA2D->CR |= DMA2D_CR_SUSP; -} - -/** - * @brief Suspend current job. - * @details Suspends the current job. The driver is set to a paused state. - * @pre There is an active job. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dJobSuspend(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dJobSuspendI(dma2dp); - chSysUnlock(); -} - -/** - * @brief Resume current job. - * @details Resumes the current job. - * @pre There is a paused job. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dJobResumeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck((DMA2D->CR & DMA2D_CR_SUSP) != 0); - osalDbgAssert(dma2dp->state == DMA2D_PAUSED, "invalid state"); - - dma2dp->state = DMA2D_ACTIVE; - DMA2D->CR &= ~DMA2D_CR_SUSP; -} - -/** - * @brief Resume current job. - * @details Resumes the current job. - * @pre There is a paused job. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dJobResume(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dJobResumeI(dma2dp); - chSysUnlock(); -} - -/** - * @brief Abort current job. - * @details Abots the current job (if any), and the driver becomes ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @iclass - */ -void dma2dJobAbortI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck((DMA2D->CR & DMA2D_CR_SUSP) == 0); - osalDbgAssert(dma2dp->state >= DMA2D_READY, "invalid state"); - - dma2dp->state = DMA2D_READY; - DMA2D->CR |= DMA2D_CR_ABORT; -} - -/** - * @brief Abort current job. - * @details Abots the current job (if any), and the driver becomes ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @api - */ -void dma2dJobAbort(DMA2DDriver *dma2dp) { - - chSysLock(); - dma2dJobAbortI(dma2dp); - chSysUnlock(); -} - -/** @} */ - -/** - * @name DMA2D background layer methods - * @{ - */ - -/** - * @brief Get background layer buffer address. - * @details Gets the buffer address of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return buffer address - * - * @iclass - */ -void *dma2dBgGetAddressI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (void *)DMA2D->BGMAR; -} - -/** - * @brief Get background layer buffer address. - * @details Gets the buffer address of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return buffer address - * - * @api - */ -void *dma2dBgGetAddress(DMA2DDriver *dma2dp) { - - void *bufferp; - chSysLock(); - bufferp = dma2dBgGetAddressI(dma2dp); - chSysUnlock(); - return bufferp; -} - -/** - * @brief Set background layer buffer address. - * @details Sets the buffer address of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] bufferp buffer address - * - * @iclass - */ -void dma2dBgSetAddressI(DMA2DDriver *dma2dp, void *bufferp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(dma2dIsAligned(bufferp, dma2dBgGetPixelFormatI(dma2dp))); - (void)dma2dp; - - DMA2D->BGMAR = (uint32_t)bufferp; -} - -/** - * @brief Set background layer buffer address. - * @details Sets the buffer address of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] bufferp buffer address - * - * @api - */ -void dma2dBgSetAddress(DMA2DDriver *dma2dp, void *bufferp) { - - chSysLock(); - dma2dBgSetAddressI(dma2dp, bufferp); - chSysUnlock(); -} - -/** - * @brief Get background layer wrap offset. - * @details Gets the buffer line wrap offset of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return wrap offset, in pixels - * - * @iclass - */ -size_t dma2dBgGetWrapOffsetI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (size_t)(DMA2D->BGOR & DMA2D_BGOR_LO); -} - -/** - * @brief Get background layer wrap offset. - * @details Gets the buffer line wrap offset of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return wrap offset, in pixels - * - * @api - */ -size_t dma2dBgGetWrapOffset(DMA2DDriver *dma2dp) { - - size_t offset; - chSysLock(); - offset = dma2dBgGetWrapOffsetI(dma2dp); - chSysUnlock(); - return offset; -} - -/** - * @brief Set background layer wrap offset. - * @details Sets the buffer line wrap offset of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] offset wrap offset, in pixels - * - * @iclass - */ -void dma2dBgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(offset <= DMA2D_MAX_OFFSET, "bounds"); - (void)dma2dp; - - DMA2D->BGOR = ((DMA2D->BGOR & ~DMA2D_BGOR_LO) | - ((uint32_t)offset & DMA2D_BGOR_LO)); -} - -/** - * @brief Set background layer wrap offset. - * @details Sets the buffer line wrap offset of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] offset wrap offset, in pixels - * - * @api - */ -void dma2dBgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset) { - - chSysLock(); - dma2dBgSetWrapOffsetI(dma2dp, offset); - chSysUnlock(); -} - -/** - * @brief Get background layer constant alpha. - * @details Gets the constant alpha component of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return constant alpha component, A-8 - * - * @iclass - */ -uint8_t dma2dBgGetConstantAlphaI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (uint8_t)((DMA2D->BGPFCCR & DMA2D_BGPFCCR_ALPHA) >> 24); -} - -/** - * @brief Get background layer constant alpha. - * @details Gets the constant alpha component of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return constant alpha component, A-8 - * - * @api - */ -uint8_t dma2dBgGetConstantAlpha(DMA2DDriver *dma2dp) { - - uint8_t a; - chSysLock(); - a = dma2dBgGetConstantAlphaI(dma2dp); - chSysUnlock(); - return a; -} - -/** - * @brief Set background layer constant alpha. - * @details Sets the constant alpha component of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] a constant alpha component, A-8 - * - * @iclass - */ -void dma2dBgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - (void)dma2dp; - - DMA2D->BGPFCCR = ((DMA2D->BGPFCCR & ~DMA2D_BGPFCCR_ALPHA) | - (((uint32_t)a << 24) & DMA2D_BGPFCCR_ALPHA)); -} - -/** - * @brief Set background layer constant alpha. - * @details Sets the constant alpha component of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] a constant alpha component, A-8 - * - * @api - */ -void dma2dBgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a) { - - chSysLock(); - dma2dBgSetConstantAlphaI(dma2dp, a); - chSysUnlock(); -} - -/** - * @brief Get background layer alpha mode. - * @details Gets the alpha mode of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return alpha mode - * - * @iclass - */ -dma2d_amode_t dma2dBgGetAlphaModeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_amode_t)(DMA2D->BGPFCCR & DMA2D_BGPFCCR_AM); -} - -/** - * @brief Get background layer alpha mode. - * @details Gets the alpha mode of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return alpha mode - * - * @api - */ -dma2d_amode_t dma2dBgGetAlphaMode(DMA2DDriver *dma2dp) { - - dma2d_amode_t mode; - chSysLock(); - mode = dma2dBgGetAlphaModeI(dma2dp); - chSysUnlock(); - return mode; -} - -/** - * @brief Set background layer alpha mode. - * @details Sets the alpha mode of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] mode alpha mode - * - * @iclass - */ -void dma2dBgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert((mode & ~DMA2D_BGPFCCR_AM) == 0, "bounds"); - osalDbgAssert((mode & DMA2D_BGPFCCR_AM) != DMA2D_BGPFCCR_AM, "bounds"); - (void)dma2dp; - - DMA2D->BGPFCCR = ((DMA2D->BGPFCCR & ~DMA2D_BGPFCCR_AM) | - ((uint32_t)mode & DMA2D_BGPFCCR_AM)); -} - -/** - * @brief Set background layer alpha mode. - * @details Sets the alpha mode of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] mode alpha mode - * - * @api - */ -void dma2dBgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode) { - - chSysLock(); - dma2dBgSetAlphaModeI(dma2dp, mode); - chSysUnlock(); -} - -/** - * @brief Get background layer pixel format. - * @details Gets the pixel format of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return pixel format - * - * @iclass - */ -dma2d_pixfmt_t dma2dBgGetPixelFormatI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_pixfmt_t)(DMA2D->BGPFCCR & DMA2D_BGPFCCR_CM); -} - -/** - * @brief Get background layer pixel format. - * @details Gets the pixel format of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return pixel format - * - * @api - */ -dma2d_pixfmt_t dma2dBgGetPixelFormat(DMA2DDriver *dma2dp) { - - dma2d_pixfmt_t fmt; - chSysLock(); - fmt = dma2dBgGetPixelFormatI(dma2dp); - chSysUnlock(); - return fmt; -} - -/** - * @brief Set background layer pixel format. - * @details Sets the pixel format of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] fmt pixel format - * - * @iclass - */ -void dma2dBgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(fmt <= DMA2D_MAX_PIXFMT_ID, "bounds"); - (void)dma2dp; - - DMA2D->BGPFCCR = ((DMA2D->BGPFCCR & ~DMA2D_BGPFCCR_CM) | - ((uint32_t)fmt & DMA2D_BGPFCCR_CM)); -} - -/** - * @brief Set background layer pixel format. - * @details Sets the pixel format of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] fmt pixel format - * - * @api - */ -void dma2dBgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) { - - chSysLock(); - dma2dBgSetPixelFormatI(dma2dp, fmt); - chSysUnlock(); -} - -/** - * @brief Get background layer default color. - * @details Gets the default color of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return default color, RGB-888 - * - * @iclass - */ -dma2d_color_t dma2dBgGetDefaultColorI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_color_t)(DMA2D->BGCOLR & 0x00FFFFFF); -} - -/** - * @brief Get background layer default color. - * @details Gets the default color of the background layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return default color, RGB-888 - * - * @api - */ -dma2d_color_t dma2dBgGetDefaultColor(DMA2DDriver *dma2dp) { - - dma2d_color_t c; - chSysLock(); - c = dma2dBgGetDefaultColorI(dma2dp); - chSysUnlock(); - return c; -} - -/** - * @brief Set background layer default color. - * @details Sets the default color of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] c default color, RGB-888 - * - * @iclass - */ -void dma2dBgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - (void)dma2dp; - - DMA2D->BGCOLR = (uint32_t)c & 0x00FFFFFF; -} - -/** - * @brief Set background layer default color. - * @details Sets the default color of the background layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] c default color, RGB-888 - * - * @api - */ -void dma2dBgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c) { - - chSysLock(); - dma2dBgSetDefaultColorI(dma2dp, c); - chSysUnlock(); -} - -/** - * @brief Get background layer palette specifications. - * @details Gets the palette specifications of the background layer. - * @note The palette colors pointer is actually addressed to a @p volatile - * memory zone. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] palettep pointer to the palette specifications - * - * @iclass - */ -void dma2dBgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep) { - - uint32_t r; - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(palettep != NULL); - (void)dma2dp; - - r = DMA2D->BGPFCCR; - palettep->colorsp = (const void *)DMA2D->BGCLUT; - palettep->length = (uint16_t)((r & DMA2D_BGPFCCR_CS) >> 8) + 1; - palettep->fmt = (dma2d_pixfmt_t)((r & DMA2D_BGPFCCR_CCM) >> 4); -} - -/** - * @brief Get background layer palette specifications. - * @details Gets the palette specifications of the background layer. - * @note The palette colors pointer is actually addressed to a @p volatile - * memory zone. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] palettep pointer to the palette specifications - * - * @api - */ -void dma2dBgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep) { - - chSysLock(); - dma2dBgGetPaletteI(dma2dp, palettep); - chSysUnlock(); -} - -/** - * @brief Set background layer palette specifications. - * @details Sets the palette specifications of the background layer. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] palettep pointer to the palette specifications - * - * @sclass - */ -void dma2dBgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(palettep != NULL); - osalDbgCheck(palettep->colorsp != NULL); - osalDbgAssert(palettep->length > 0, "bounds"); - osalDbgAssert(palettep->length <= DMA2D_MAX_PALETTE_LENGTH, "bounds"); - osalDbgAssert(((palettep->fmt == DMA2D_FMT_ARGB8888) || - (palettep->fmt == DMA2D_FMT_RGB888)), "invalid format"); - - DMA2D->BGCMAR = (uint32_t)palettep->colorsp; - DMA2D->BGPFCCR = ( - (DMA2D->BGPFCCR & ~(DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM)) | - ((((uint32_t)palettep->length - 1) << 8) & DMA2D_BGPFCCR_CS) | - ((uint32_t)palettep->fmt << 4) - ); - - dma2dp->state = DMA2D_ACTIVE; - DMA2D->BGPFCCR |= DMA2D_BGPFCCR_START; - -#if DMA2D_USE_WAIT - dma2dp->thread = chThdGetSelfX(); - chSchGoSleepS(CH_STATE_SUSPENDED); -#else - while (DMA2D->BGPFCCR & DMA2D_BGPFCCR_START) - chSchDoYieldS(); -#endif /* DMA2D_USE_WAIT */ -} - -/** - * @brief Set background layer palette specifications. - * @details Sets the palette specifications of the background layer. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] palettep pointer to the palette specifications - * - * @api - */ -void dma2dBgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep) { - - chSysLock(); - dma2dBgSetPaletteS(dma2dp, palettep); - chSysUnlock(); -} - -/** - * @brief Get background layer specifications. - * @details Gets the background layer specifications at once. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @iclass - */ -void dma2dBgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(cfgp != NULL); - - cfgp->bufferp = dma2dBgGetAddressI(dma2dp); - cfgp->wrap_offset = dma2dBgGetWrapOffsetI(dma2dp); - cfgp->fmt = dma2dBgGetPixelFormatI(dma2dp); - cfgp->def_color = dma2dBgGetDefaultColorI(dma2dp); - cfgp->const_alpha = dma2dBgGetConstantAlphaI(dma2dp); - if (cfgp->palettep != NULL) - dma2dBgGetPaletteI(dma2dp, (dma2d_palcfg_t *)cfgp->palettep); -} - -/** - * @brief Get background layer specifications. - * @details Gets the background layer specifications at once. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @api - */ -void dma2dBgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) { - - chSysLock(); - dma2dBgGetLayerI(dma2dp, cfgp); - chSysUnlock(); -} - -/** - * @brief Set background layer specifications. - * @details Sets the background layer specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @sclass - */ -void dma2dBgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(cfgp != NULL); - - dma2dBgSetAddressI(dma2dp, cfgp->bufferp); - dma2dBgSetWrapOffsetI(dma2dp, cfgp->wrap_offset); - dma2dBgSetPixelFormatI(dma2dp, cfgp->fmt); - dma2dBgSetDefaultColorI(dma2dp, cfgp->def_color); - dma2dBgSetConstantAlphaI(dma2dp, cfgp->const_alpha); - if (cfgp->palettep != NULL) - dma2dBgSetPaletteS(dma2dp, cfgp->palettep); -} - -/** - * @brief Set background layer specifications. - * @details Sets the background layer specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @api - */ -void dma2dBgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) { - - chSysLock(); - dma2dBgSetConfigS(dma2dp, cfgp); - chSysUnlock(); -} - -/** @} */ - -/** - * @name DMA2D foreground layer methods - * @{ - */ - -/** - * @brief Get foreground layer buffer address. - * @details Gets the buffer address of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return buffer address - * - * @iclass - */ -void *dma2dFgGetAddressI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (void *)DMA2D->FGMAR; -} - -/** - * @brief Get foreground layer buffer address. - * @details Gets the buffer address of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return buffer address - * - * @api - */ -void *dma2dFgGetAddress(DMA2DDriver *dma2dp) { - - void *bufferp; - chSysLock(); - bufferp = dma2dFgGetAddressI(dma2dp); - chSysUnlock(); - return bufferp; -} - -/** - * @brief Set foreground layer buffer address. - * @details Sets the buffer address of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] bufferp buffer address - * - * @iclass - */ -void dma2dFgSetAddressI(DMA2DDriver *dma2dp, void *bufferp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(dma2dIsAligned(bufferp, dma2dFgGetPixelFormatI(dma2dp))); - (void)dma2dp; - - DMA2D->FGMAR = (uint32_t)bufferp; -} - -/** - * @brief Set foreground layer buffer address. - * @details Sets the buffer address of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] bufferp buffer address - * - * @api - */ -void dma2dFgSetAddress(DMA2DDriver *dma2dp, void *bufferp) { - - chSysLock(); - dma2dFgSetAddressI(dma2dp, bufferp); - chSysUnlock(); -} - -/** - * @brief Get foreground layer wrap offset. - * @details Gets the buffer line wrap offset of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return wrap offset, in pixels - * - * @iclass - */ -size_t dma2dFgGetWrapOffsetI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (size_t)(DMA2D->FGOR & DMA2D_FGOR_LO); -} - -/** - * @brief Get foreground layer wrap offset. - * @details Gets the buffer line wrap offset of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return wrap offset, in pixels - * - * @api - */ -size_t dma2dFgGetWrapOffset(DMA2DDriver *dma2dp) { - - size_t offset; - chSysLock(); - offset = dma2dFgGetWrapOffsetI(dma2dp); - chSysUnlock(); - return offset; -} - -/** - * @brief Set foreground layer wrap offset. - * @details Sets the buffer line wrap offset of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] offset wrap offset, in pixels - * - * @iclass - */ -void dma2dFgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(offset <= DMA2D_MAX_OFFSET, "bounds"); - (void)dma2dp; - - DMA2D->FGOR = ((DMA2D->FGOR & ~DMA2D_FGOR_LO) | - ((uint32_t)offset & DMA2D_FGOR_LO)); -} - -/** - * @brief Set foreground layer wrap offset. - * @details Sets the buffer line wrap offset of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] offset wrap offset, in pixels - * - * @api - */ -void dma2dFgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset) { - - chSysLock(); - dma2dFgSetWrapOffsetI(dma2dp, offset); - chSysUnlock(); -} - -/** - * @brief Get foreground layer constant alpha. - * @details Gets the constant alpha component of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return constant alpha component, A-8 - * - * @iclass - */ -uint8_t dma2dFgGetConstantAlphaI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (uint8_t)((DMA2D->FGPFCCR & DMA2D_FGPFCCR_ALPHA) >> 24); -} - -/** - * @brief Get foreground layer constant alpha. - * @details Gets the constant alpha component of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return constant alpha component, A-8 - * - * @api - */ -uint8_t dma2dFgGetConstantAlpha(DMA2DDriver *dma2dp) { - - uint8_t a; - chSysLock(); - a = dma2dFgGetConstantAlphaI(dma2dp); - chSysUnlock(); - return a; -} - -/** - * @brief Set foreground layer constant alpha. - * @details Sets the constant alpha component of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] a constant alpha component, A-8 - * - * @iclass - */ -void dma2dFgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - (void)dma2dp; - - DMA2D->FGPFCCR = ((DMA2D->FGPFCCR & ~DMA2D_FGPFCCR_ALPHA) | - (((uint32_t)a << 24) & DMA2D_FGPFCCR_ALPHA)); -} - -/** - * @brief Set foreground layer constant alpha. - * @details Sets the constant alpha component of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] a constant alpha component, A-8 - * - * @api - */ -void dma2dFgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a) { - - chSysLock(); - dma2dFgSetConstantAlphaI(dma2dp, a); - chSysUnlock(); -} - -/** - * @brief Get foreground layer alpha mode. - * @details Gets the alpha mode of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return alpha mode - * - * @iclass - */ -dma2d_amode_t dma2dFgGetAlphaModeI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_amode_t)(DMA2D->FGPFCCR & DMA2D_FGPFCCR_AM); -} - -/** - * @brief Get foreground layer alpha mode. - * @details Gets the alpha mode of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return alpha mode - * - * @api - */ -dma2d_amode_t dma2dFgGetAlphaMode(DMA2DDriver *dma2dp) { - - dma2d_amode_t mode; - chSysLock(); - mode = dma2dFgGetAlphaModeI(dma2dp); - chSysUnlock(); - return mode; -} - -/** - * @brief Set foreground layer alpha mode. - * @details Sets the alpha mode of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] mode alpha mode - * - * @iclass - */ -void dma2dFgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert((mode & ~DMA2D_FGPFCCR_AM) == 0, "bounds"); - osalDbgAssert((mode & DMA2D_FGPFCCR_AM) != DMA2D_FGPFCCR_AM, "bounds"); - (void)dma2dp; - - DMA2D->FGPFCCR = ((DMA2D->FGPFCCR & ~DMA2D_FGPFCCR_AM) | - ((uint32_t)mode & DMA2D_FGPFCCR_AM)); -} - -/** - * @brief Set foreground layer alpha mode. - * @details Sets the alpha mode of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] mode alpha mode - * - * @api - */ -void dma2dFgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode) { - - chSysLock(); - dma2dFgSetAlphaModeI(dma2dp, mode); - chSysUnlock(); -} - -/** - * @brief Get foreground layer pixel format. - * @details Gets the pixel format of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return pixel format - * - * @iclass - */ -dma2d_pixfmt_t dma2dFgGetPixelFormatI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_pixfmt_t)(DMA2D->FGPFCCR & DMA2D_FGPFCCR_CM); -} - -/** - * @brief Get foreground layer pixel format. - * @details Gets the pixel format of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return pixel format - * - * @api - */ -dma2d_pixfmt_t dma2dFgGetPixelFormat(DMA2DDriver *dma2dp) { - - dma2d_pixfmt_t fmt; - chSysLock(); - fmt = dma2dFgGetPixelFormatI(dma2dp); - chSysUnlock(); - return fmt; -} - -/** - * @brief Set foreground layer pixel format. - * @details Sets the pixel format of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] fmt pixel format - * - * @iclass - */ -void dma2dFgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(fmt <= DMA2D_MAX_PIXFMT_ID, "bounds"); - (void)dma2dp; - - DMA2D->FGPFCCR = ((DMA2D->FGPFCCR & ~DMA2D_FGPFCCR_CM) | - ((uint32_t)fmt & DMA2D_FGPFCCR_CM)); -} - -/** - * @brief Set foreground layer pixel format. - * @details Sets the pixel format of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] fmt pixel format - * - * @api - */ -void dma2dFgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) { - - chSysLock(); - dma2dFgSetPixelFormatI(dma2dp, fmt); - chSysUnlock(); -} - -/** - * @brief Get foreground layer default color. - * @details Gets the default color of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return default color, RGB-888 - * - * @iclass - */ -dma2d_color_t dma2dFgGetDefaultColorI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_color_t)(DMA2D->FGCOLR & 0x00FFFFFF); -} - -/** - * @brief Get foreground layer default color. - * @details Gets the default color of the foreground layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return default color, RGB-888 - * - * @api - */ -dma2d_color_t dma2dFgGetDefaultColor(DMA2DDriver *dma2dp) { - - dma2d_color_t c; - chSysLock(); - c = dma2dFgGetDefaultColorI(dma2dp); - chSysUnlock(); - return c; -} - -/** - * @brief Set foreground layer default color. - * @details Sets the default color of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] c default color, RGB-888 - * - * @iclass - */ -void dma2dFgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - (void)dma2dp; - - DMA2D->FGCOLR = (uint32_t)c & 0x00FFFFFF; -} - -/** - * @brief Set foreground layer default color. - * @details Sets the default color of the foreground layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] c default color, RGB-888 - * - * @api - */ -void dma2dFgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c) { - - chSysLock(); - dma2dFgSetDefaultColorI(dma2dp, c); - chSysUnlock(); -} - -/** - * @brief Get foreground layer palette specifications. - * @details Gets the palette specifications of the foreground layer. - * @note The palette colors pointer is actually addressed to a @p volatile - * memory zone. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] palettep pointer to the palette specifications - * - * @iclass - */ -void dma2dFgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep) { - - uint32_t r; - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(palettep != NULL); - (void)dma2dp; - - r = DMA2D->FGPFCCR; - palettep->colorsp = (const void *)DMA2D->FGCLUT; - palettep->length = (uint16_t)((r & DMA2D_FGPFCCR_CS) >> 8) + 1; - palettep->fmt = (dma2d_pixfmt_t)((r & DMA2D_FGPFCCR_CCM) >> 4); -} - -/** - * @brief Get foreground layer palette specifications. - * @details Gets the palette specifications of the foreground layer. - * @note The palette colors pointer is actually addressed to a @p volatile - * memory zone. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] palettep pointer to the palette specifications - * - * @api - */ -void dma2dFgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep) { - - chSysLock(); - dma2dFgGetPaletteI(dma2dp, palettep); - chSysUnlock(); -} - -/** - * @brief Set foreground layer palette specifications. - * @details Sets the palette specifications of the foreground layer. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] palettep pointer to the palette specifications - * - * @sclass - */ -void dma2dFgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(palettep != NULL); - osalDbgCheck(palettep->colorsp != NULL); - osalDbgAssert(palettep->length > 0, "bounds"); - osalDbgAssert(palettep->length <= DMA2D_MAX_PALETTE_LENGTH, "bounds"); - osalDbgAssert(((palettep->fmt == DMA2D_FMT_ARGB8888) || - (palettep->fmt == DMA2D_FMT_RGB888)), "invalid format"); - - DMA2D->FGCMAR = (uint32_t)palettep->colorsp; - DMA2D->FGPFCCR = ( - (DMA2D->FGPFCCR & ~(DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM)) | - ((((uint32_t)palettep->length - 1) << 8) & DMA2D_FGPFCCR_CS) | - ((uint32_t)palettep->fmt << 4) - ); - - dma2dp->state = DMA2D_ACTIVE; - DMA2D->FGPFCCR |= DMA2D_FGPFCCR_START; - -#if DMA2D_USE_WAIT - dma2dp->thread = chThdGetSelfX(); - chSchGoSleepS(CH_STATE_SUSPENDED); -#else - while (DMA2D->FGPFCCR & DMA2D_FGPFCCR_START) - chSchDoYieldS(); -#endif /* DMA2D_USE_WAIT */ -} - -/** - * @brief Set foreground layer palette specifications. - * @details Sets the palette specifications of the foreground layer. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] palettep pointer to the palette specifications - * - * @api - */ -void dma2dFgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep) { - - chSysLock(); - dma2dFgSetPaletteS(dma2dp, palettep); - chSysUnlock(); -} - -/** - * @brief Get foreground layer specifications. - * @details Gets the foreground layer specifications at once. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @iclass - */ -void dma2dFgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(cfgp != NULL); - - cfgp->bufferp = dma2dFgGetAddressI(dma2dp); - cfgp->wrap_offset = dma2dFgGetWrapOffsetI(dma2dp); - cfgp->fmt = dma2dFgGetPixelFormatI(dma2dp); - cfgp->def_color = dma2dFgGetDefaultColorI(dma2dp); - cfgp->const_alpha = dma2dFgGetConstantAlphaI(dma2dp); - if (cfgp->palettep != NULL) - dma2dFgGetPaletteI(dma2dp, (dma2d_palcfg_t *)cfgp->palettep); -} - -/** - * @brief Get foreground layer specifications. - * @details Gets the foreground layer specifications at once. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @api - */ -void dma2dFgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) { - - chSysLock(); - dma2dFgGetLayerI(dma2dp, cfgp); - chSysUnlock(); -} - -/** - * @brief Set foreground layer specifications. - * @details Sets the foreground layer specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @sclass - */ -void dma2dFgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) { - - osalDbgCheckClassS(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(cfgp != NULL); - - dma2dFgSetAddressI(dma2dp, cfgp->bufferp); - dma2dFgSetWrapOffsetI(dma2dp, cfgp->wrap_offset); - dma2dFgSetPixelFormatI(dma2dp, cfgp->fmt); - dma2dFgSetDefaultColorI(dma2dp, cfgp->def_color); - dma2dFgSetConstantAlphaI(dma2dp, cfgp->const_alpha); - if (cfgp->palettep != NULL) - dma2dFgSetPaletteS(dma2dp, cfgp->palettep); -} - -/** - * @brief Set foreground layer specifications. - * @details Sets the foreground layer specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * @note This function should not be called while the DMA2D is already - * executing a job, otherwise the appropriate error interrupt might be - * invoked. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @api - */ -void dma2dFgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) { - - chSysLock(); - dma2dFgSetConfigS(dma2dp, cfgp); - chSysUnlock(); -} - -/** @} */ - -/** - * @name DMA2D output layer methods - * @{ - */ - -/** - * @brief Get output layer buffer address. - * @details Gets the buffer address of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return buffer address - * - * @iclass - */ -void *dma2dOutGetAddressI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (void *)DMA2D->OMAR; -} - -/** - * @brief Get output layer buffer address. - * @details Gets the buffer address of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return buffer address - * - * @api - */ -void *dma2dOutGetAddress(DMA2DDriver *dma2dp) { - - void *bufferp; - chSysLock(); - bufferp = dma2dOutGetAddressI(dma2dp); - chSysUnlock(); - return bufferp; -} - -/** - * @brief Set output layer buffer address. - * @details Sets the buffer address of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] bufferp buffer address - * - * @iclass - */ -void dma2dOutSetAddressI(DMA2DDriver *dma2dp, void *bufferp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(dma2dIsAligned(bufferp, dma2dOutGetPixelFormatI(dma2dp))); - (void)dma2dp; - - DMA2D->OMAR = (uint32_t)bufferp; -} - -/** - * @brief Set output layer buffer address. - * @details Sets the buffer address of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] bufferp buffer address - * - * @api - */ -void dma2dOutSetAddress(DMA2DDriver *dma2dp, void *bufferp) { - - chSysLock(); - dma2dOutSetAddressI(dma2dp, bufferp); - chSysUnlock(); -} - -/** - * @brief Get output layer wrap offset. - * @details Gets the buffer line wrap offset of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return wrap offset, in pixels - * - * @iclass - */ -size_t dma2dOutGetWrapOffsetI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (size_t)(DMA2D->OOR & DMA2D_OOR_LO); -} - -/** - * @brief Get output layer wrap offset. - * @details Gets the buffer line wrap offset of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return wrap offset, in pixels - * - * @api - */ -size_t dma2dOutGetWrapOffset(DMA2DDriver *dma2dp) { - - size_t offset; - chSysLock(); - offset = dma2dOutGetWrapOffsetI(dma2dp); - chSysUnlock(); - return offset; -} - -/** - * @brief Set output layer wrap offset. - * @details Sets the buffer line wrap offset of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] offset wrap offset, in pixels - * - * @iclass - */ -void dma2dOutSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(offset <= DMA2D_MAX_OFFSET, "bounds"); - (void)dma2dp; - - DMA2D->OOR = ((DMA2D->OOR & ~DMA2D_OOR_LO) | - ((uint32_t)offset & DMA2D_OOR_LO)); -} - -/** - * @brief Set output layer wrap offset. - * @details Sets the buffer line wrap offset of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] offset wrap offset, in pixels - * - * @api - */ -void dma2dOutSetWrapOffset(DMA2DDriver *dma2dp, size_t offset) { - - chSysLock(); - dma2dOutSetWrapOffsetI(dma2dp, offset); - chSysUnlock(); -} - -/** - * @brief Get output layer pixel format. - * @details Gets the pixel format of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return pixel format - * - * @iclass - */ -dma2d_pixfmt_t dma2dOutGetPixelFormatI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_pixfmt_t)(DMA2D->OPFCCR & DMA2D_OPFCCR_CM); -} - -/** - * @brief Get output layer pixel format. - * @details Gets the pixel format of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return pixel format - * - * @api - */ -dma2d_pixfmt_t dma2dOutGetPixelFormat(DMA2DDriver *dma2dp) { - - dma2d_pixfmt_t fmt; - chSysLock(); - fmt = dma2dOutGetPixelFormatI(dma2dp); - chSysUnlock(); - return fmt; -} - -/** - * @brief Set output layer pixel format. - * @details Sets the pixel format of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] fmt pixel format - * - * @iclass - */ -void dma2dOutSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgAssert(fmt <= DMA2D_MAX_OUTPIXFMT_ID, "bounds"); - (void)dma2dp; - - DMA2D->OPFCCR = ((DMA2D->OPFCCR & ~DMA2D_OPFCCR_CM) | - ((uint32_t)fmt & DMA2D_OPFCCR_CM)); -} - -/** - * @brief Set output layer pixel format. - * @details Sets the pixel format of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] fmt pixel format - * - * @api - */ -void dma2dOutSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt) { - - chSysLock(); - dma2dOutSetPixelFormatI(dma2dp, fmt); - chSysUnlock(); -} - -/** - * @brief Get output layer default color. - * @details Gets the default color of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return default color, chosen output format - * - * @iclass - */ -dma2d_color_t dma2dOutGetDefaultColorI(DMA2DDriver *dma2dp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - (void)dma2dp; - - return (dma2d_color_t)(DMA2D->OCOLR & 0x00FFFFFF); -} - -/** - * @brief Get output layer default color. - * @details Gets the default color of the output layer. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * - * @return default color, chosen output format - * - * @api - */ -dma2d_color_t dma2dOutGetDefaultColor(DMA2DDriver *dma2dp) { - - dma2d_color_t c; - chSysLock(); - c = dma2dOutGetDefaultColorI(dma2dp); - chSysUnlock(); - return c; -} - -/** - * @brief Set output layer default color. - * @details Sets the default color of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] c default color, chosen output format - * - * @iclass - */ -void dma2dOutSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - (void)dma2dp; - - DMA2D->OCOLR = (uint32_t)c & 0x00FFFFFF; -} - -/** - * @brief Set output layer default color. - * @details Sets the default color of the output layer. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] c default color, chosen output format - * - * @api - */ -void dma2dOutSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c) { - - chSysLock(); - dma2dOutSetDefaultColorI(dma2dp, c); - chSysUnlock(); -} - -/** - * @brief Get output layer specifications. - * @details Gets the output layer specifications at once. - * @note Constant alpha and palette specifications are ignored. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @iclass - */ -void dma2dOutGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgCheck(cfgp != NULL); - - cfgp->bufferp = dma2dOutGetAddressI(dma2dp); - cfgp->wrap_offset = dma2dOutGetWrapOffsetI(dma2dp); - cfgp->fmt = dma2dOutGetPixelFormatI(dma2dp); - cfgp->def_color = dma2dOutGetDefaultColorI(dma2dp); -} - -/** - * @brief Get output layer specifications. - * @details Gets the output layer specifications at once. - * @note Constant alpha and palette specifications are ignored. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @api - */ -void dma2dOutGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp) { - - chSysLock(); - dma2dOutGetLayerI(dma2dp, cfgp); - chSysUnlock(); -} - -/** - * @brief Set output layer specifications. - * @details Sets the output layer specifications at once. - * @note Constant alpha and palette specifications are ignored. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @iclass - */ -void dma2dOutSetConfigI(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(dma2dp == &DMA2DD1); - osalDbgAssert(dma2dp->state == DMA2D_READY, "not ready"); - osalDbgCheck(cfgp != NULL); - - dma2dOutSetAddressI(dma2dp, cfgp->bufferp); - dma2dOutSetWrapOffsetI(dma2dp, cfgp->wrap_offset); - dma2dOutSetPixelFormatI(dma2dp, cfgp->fmt); - dma2dOutSetDefaultColorI(dma2dp, cfgp->def_color); -} - -/** - * @brief Set output layer specifications. - * @details Sets the output layer specifications at once. - * @note Constant alpha and palette specifications are ignored. - * @pre DMA2D is ready. - * - * @param[in] dma2dp pointer to the @p DMA2DDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @api - */ -void dma2dOutSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp) { - - chSysLock(); - dma2dOutSetConfigI(dma2dp, cfgp); - chSysUnlock(); -} - -/** @} */ - -/** - * @name DMA2D helper functions - * @{ - */ - -/** - * @brief Compute pixel address. - * @details Computes the buffer address of a pixel, given the buffer - * specifications. - * - * @param[in] originp buffer origin address - * @param[in] pitch buffer pitch, in bytes - * @param[in] fmt buffer pixel format - * @param[in] x horizontal pixel coordinate - * @param[in] y vertical pixel coordinate - * - * @return pixel address, constant data - * - * @api - */ -const void *dma2dComputeAddressConst(const void *originp, size_t pitch, - dma2d_pixfmt_t fmt, - uint16_t x, uint16_t y) { - - osalDbgCheck(pitch > 0); - - switch (fmt) { - case DMA2D_FMT_ARGB8888: - return (const void *)((uintptr_t)originp + - (uintptr_t)y * pitch + (uintptr_t)x * 4); - case DMA2D_FMT_RGB888: - return (const void *)((uintptr_t)originp + - (uintptr_t)y * pitch + (uintptr_t)x * 3); - case DMA2D_FMT_RGB565: - case DMA2D_FMT_ARGB1555: - case DMA2D_FMT_ARGB4444: - case DMA2D_FMT_AL88: - return (const void *)((uintptr_t)originp + - (uintptr_t)y * pitch + (uintptr_t)x * 2); - case DMA2D_FMT_L8: - case DMA2D_FMT_AL44: - case DMA2D_FMT_A8: - return (const void *)((uintptr_t)originp + - (uintptr_t)y * pitch + (uintptr_t)x); - case DMA2D_FMT_L4: - case DMA2D_FMT_A4: - osalDbgAssert((x & 1) == 0, "not aligned"); - return (const void *)((uintptr_t)originp + - (uintptr_t)y * pitch + (uintptr_t)x / 2); - default: - osalDbgAssert(false, "invalid format"); - return NULL; - } -} - -/** - * @brief Address is aligned. - * @details Tells whether the address is aligned with the provided pixel format. - * - * @param[in] bufferp address - * @param[in] fmt pixel format - * - * @return address is aligned - * - * @api - */ -bool dma2dIsAligned(const void *bufferp, dma2d_pixfmt_t fmt) { - - switch (fmt) { - case DMA2D_FMT_ARGB8888: - case DMA2D_FMT_RGB888: - return ((uintptr_t)bufferp & 3) == 0; /* 32-bit alignment.*/ - case DMA2D_FMT_RGB565: - case DMA2D_FMT_ARGB1555: - case DMA2D_FMT_ARGB4444: - case DMA2D_FMT_AL88: - return ((uintptr_t)bufferp & 1) == 0; /* 16-bit alignment.*/ - case DMA2D_FMT_L8: - case DMA2D_FMT_AL44: - case DMA2D_FMT_L4: - case DMA2D_FMT_A8: - case DMA2D_FMT_A4: - return true; /* 8-bit alignment.*/ - default: - osalDbgAssert(false, "invalid format"); - return false; - } -} - -/** - * @brief Compute bits per pixel. - * @details Computes the bits per pixel for the specified pixel format. - * - * @param[in] fmt pixel format - * - * @retuen bits per pixel - * - * @api - */ -size_t dma2dBitsPerPixel(dma2d_pixfmt_t fmt) { - - osalDbgAssert(fmt < DMA2D_MAX_PIXFMT_ID, "invalid format"); - - return (size_t)dma2d_bpp[(unsigned)fmt]; -} - -#if DMA2D_USE_SOFTWARE_CONVERSIONS || defined(__DOXYGEN__) - -/** - * @brief Convert from ARGB-8888. - * @details Converts an ARGB-8888 color to the specified pixel format. - * - * @param[in] c color, ARGB-8888 - * @param[in] fmt target pixel format - * - * @return raw color value for the target pixel format, left - * padded with zeros. - * - * @api - */ -dma2d_color_t dma2dFromARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt) { - - switch (fmt) { - case DMA2D_FMT_ARGB8888: { - return c; - } - case DMA2D_FMT_RGB888: { - return (c & 0x00FFFFFF); - } - case DMA2D_FMT_RGB565: { - return (((c & 0x000000F8) >> ( 8 - 5)) | - ((c & 0x0000FC00) >> (16 - 11)) | - ((c & 0x00F80000) >> (24 - 16))); - } - case DMA2D_FMT_ARGB1555: { - return (((c & 0x000000F8) >> ( 8 - 5)) | - ((c & 0x0000F800) >> (16 - 10)) | - ((c & 0x00F80000) >> (24 - 15)) | - ((c & 0x80000000) >> (32 - 16))); - } - case DMA2D_FMT_ARGB4444: { - return (((c & 0x000000F0) >> ( 8 - 4)) | - ((c & 0x0000F000) >> (16 - 8)) | - ((c & 0x00F00000) >> (24 - 12)) | - ((c & 0xF0000000) >> (32 - 16))); - } - case DMA2D_FMT_L8: { - return (c & 0x000000FF); - } - case DMA2D_FMT_AL44: { - return (((c & 0x000000F0) >> ( 8 - 4)) | - ((c & 0xF0000000) >> (32 - 8))); - } - case DMA2D_FMT_AL88: { - return (((c & 0x000000FF) >> ( 8 - 8)) | - ((c & 0xFF000000) >> (32 - 16))); - } - case DMA2D_FMT_L4: { - return (c & 0x0000000F); - } - case DMA2D_FMT_A8: { - return ((c & 0xFF000000) >> (32 - 8)); - } - case DMA2D_FMT_A4: { - return ((c & 0xF0000000) >> (32 - 4)); - } - default: - osalDbgAssert(false, "invalid format"); - return 0; - } -} - -/** - * @brief Convert to ARGB-8888. - * @details Converts color of the specified pixel format to an ARGB-8888 color. - * - * @param[in] c color for the source pixel format, left padded with - * zeros. - * @param[in] fmt source pixel format - * - * @return color in ARGB-8888 format - * - * @api - */ -dma2d_color_t dma2dToARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt) { - - switch (fmt) { - case DMA2D_FMT_ARGB8888: { - return c; - } - case DMA2D_FMT_RGB888: { - return ((c & 0x00FFFFFF) | 0xFF000000); - } - case DMA2D_FMT_RGB565: { - register dma2d_color_t output = 0xFF000000; - if (c & 0x001F) output |= (((c & 0x001F) << ( 8 - 5)) | 0x00000007); - if (c & 0x07E0) output |= (((c & 0x07E0) << (16 - 11)) | 0x00000300); - if (c & 0xF800) output |= (((c & 0xF800) << (24 - 16)) | 0x00070000); - return output; - } - case DMA2D_FMT_ARGB1555: { - register dma2d_color_t output = 0x00000000; - if (c & 0x001F) output |= (((c & 0x001F) << ( 8 - 5)) | 0x00000007); - if (c & 0x03E0) output |= (((c & 0x03E0) << (16 - 10)) | 0x00000700); - if (c & 0x7C00) output |= (((c & 0x7C00) << (24 - 15)) | 0x00070000); - if (c & 0x8000) output |= 0xFF000000; - return output; - } - case DMA2D_FMT_ARGB4444: { - register dma2d_color_t output = 0x00000000; - if (c & 0x000F) output |= (((c & 0x000F) << ( 8 - 4)) | 0x0000000F); - if (c & 0x00F0) output |= (((c & 0x00F0) << (16 - 8)) | 0x00000F00); - if (c & 0x0F00) output |= (((c & 0x0F00) << (24 - 12)) | 0x000F0000); - if (c & 0xF000) output |= (((c & 0xF000) << (32 - 16)) | 0x0F000000); - return output; - } - case DMA2D_FMT_L8: { - return (c & 0xFF) | 0xFF000000; - } - case DMA2D_FMT_AL44: { - register dma2d_color_t output = 0x00000000; - if (c & 0x0F) output |= (((c & 0x0F) << ( 8 - 4)) | 0x0000000F); - if (c & 0xF0) output |= (((c & 0xF0) << (32 - 8)) | 0x0F000000); - return output; - } - case DMA2D_FMT_AL88: { - return (((c & 0x00FF) << ( 8 - 8)) | - ((c & 0xFF00) << (32 - 16))); - } - case DMA2D_FMT_L4: { - return ((c & 0x0F) | 0xFF000000); - } - case DMA2D_FMT_A8: { - return ((c & 0xFF) << (32 - 8)); - } - case DMA2D_FMT_A4: { - return ((c & 0x0F) << (32 - 4)); - } - default: - osalDbgAssert(false, "invalid format"); - return 0; - } -} - -#endif /* DMA2D_NEED_CONVERSIONS */ - -/** @} */ - -/** @} */ - -#endif /* STM32_DMA2D_USE_DMA2D */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h deleted file mode 100644 index 01f0941..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h +++ /dev/null @@ -1,664 +0,0 @@ -/* - Copyright (C) 2013-2015 Andrea Zoppi - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file stm32_dma2d.h - * @brief DMA2D/Chrom-ART driver. - * - * @addtogroup dma2d - * @{ - */ - -#ifndef _STM32_DMA2D_H_ -#define _STM32_DMA2D_H_ - -/** - * @brief Using the DMA2D driver. - */ -#if !defined(STM32_DMA2D_USE_DMA2D) || defined(__DOXYGEN__) -#define STM32_DMA2D_USE_DMA2D (FALSE) -#endif - -#if (TRUE == STM32_DMA2D_USE_DMA2D) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name DMA2D job modes - * @{ - */ -#define DMA2D_JOB_COPY (0 << 16) /**< Copy, replace(FG only).*/ -#define DMA2D_JOB_CONVERT (1 << 16) /**< Copy, convert (FG + PFC).*/ -#define DMA2D_JOB_BLEND (2 << 16) /**< Copy, blend (FG + BG + PFC).*/ -#define DMA2D_JOB_CONST (3 << 16) /**< Default color only (FG REG).*/ -/** @} */ - -/** - * @name DMA2D enable flag - * @{ - */ -#define DMA2D_EF_ENABLE (1 << 0) /**< DMA2D enabled.*/ -#define DMA2D_EF_DITHER (1 << 16) /**< Dithering enabled.*/ -#define DMA2D_EF_PIXCLK_INVERT (1 << 28) /**< Inverted pixel clock.*/ -#define DMA2D_EF_DATAEN_HIGH (1 << 29) /**< Active-high data enable.*/ -#define DMA2D_EF_VSYNC_HIGH (1 << 30) /**< Active-high vsync.*/ -#define DMA2D_EF_HSYNC_HIGH (1 << 31) /**< Active-high hsync.*/ - -/** Enable flags mask. */ -#define DMA2D_EF_MASK \ - (DMA2D_EF_ENABLE | DMA2D_EF_DITHER | DMA2D_EF_PIXCLK_INVERT | \ - DMA2D_EF_DATAEN_HIGH | DMA2D_EF_VSYNC_HIGH | DMA2D_EF_HSYNC_HIGH) -/** @} */ - -/** - * @name DMA2D layer enable flags - * @{ - */ -#define DMA2D_LEF_ENABLE (1 << 0) /**< Layer enabled*/ -#define DMA2D_LEF_KEYING (1 << 1) /**< Color keying enabled.*/ -#define DMA2D_LEF_PALETTE (1 << 4) /**< Palette enabled.*/ - -/** Layer enable flag masks. */ -#define DMA2D_LEF_MASK \ - (DMA2D_LEF_ENABLE | DMA2D_LEF_KEYING | DMA2D_LEF_PALETTE) -/** @} */ - -/** - * @name DMA2D pixel formats - * @{ - */ -#define DMA2D_FMT_ARGB8888 (0) /**< ARGB-8888 format.*/ -#define DMA2D_FMT_RGB888 (1) /**< RGB-888 format.*/ -#define DMA2D_FMT_RGB565 (2) /**< RGB-565 format.*/ -#define DMA2D_FMT_ARGB1555 (3) /**< ARGB-1555 format.*/ -#define DMA2D_FMT_ARGB4444 (4) /**< ARGB-4444 format.*/ -#define DMA2D_FMT_L8 (5) /**< L-8 format.*/ -#define DMA2D_FMT_AL44 (6) /**< AL-44 format.*/ -#define DMA2D_FMT_AL88 (7) /**< AL-88 format.*/ -#define DMA2D_FMT_L4 (8) /**< L-4 format.*/ -#define DMA2D_FMT_A8 (9) /**< A-8 format.*/ -#define DMA2D_FMT_A4 (10) /**< A-4 format.*/ -/** @} */ - -/** - * @name DMA2D pixel format aliased raw masks - * @{ - */ -#define DMA2D_XMASK_ARGB8888 (0xFFFFFFFF) /**< ARGB-8888 aliased mask.*/ -#define DMA2D_XMASK_RGB888 (0x00FFFFFF) /**< RGB-888 aliased mask.*/ -#define DMA2D_XMASK_RGB565 (0x00F8FCF8) /**< RGB-565 aliased mask.*/ -#define DMA2D_XMASK_ARGB1555 (0x80F8F8F8) /**< ARGB-1555 aliased mask.*/ -#define DMA2D_XMASK_ARGB4444 (0xF0F0F0F0) /**< ARGB-4444 aliased mask.*/ -#define DMA2D_XMASK_L8 (0x000000FF) /**< L-8 aliased mask.*/ -#define DMA2D_XMASK_AL44 (0xF00000F0) /**< AL-44 aliased mask.*/ -#define DMA2D_XMASK_AL88 (0xFF0000FF) /**< AL-88 aliased mask.*/ -#define DMA2D_XMASK_L4 (0x0000000F) /**< L-4 aliased mask.*/ -#define DMA2D_XMASK_A8 (0xFF000000) /**< A-8 aliased mask.*/ -#define DMA2D_XMASK_A4 (0xF0000000) /**< A-4 aliased mask.*/ -/** @} */ - -/** - * @name DMA2D alpha modes - * @{ - */ -#define DMA2D_ALPHA_KEEP (0x00000000) /**< Original alpha channel.*/ -#define DMA2D_ALPHA_REPLACE (0x00010000) /**< Replace with constant.*/ -#define DMA2D_ALPHA_MODULATE (0x00020000) /**< Modulate with constant.*/ -/** @} */ - -/** - * @name DMA2D parameter bounds - * @{ - */ - -#define DMA2D_MIN_PIXFMT_ID (0) /**< Minimum pixel format ID.*/ -#define DMA2D_MAX_PIXFMT_ID (11) /**< Maximum pixel format ID.*/ -#define DMA2D_MIN_OUTPIXFMT_ID (0) /**< Minimum output pixel format ID.*/ -#define DMA2D_MAX_OUTPIXFMT_ID (4) /**< Maximum output pixel format ID.*/ - -#define DMA2D_MAX_OFFSET ((1 << 14) - 1) - -#define DMA2D_MAX_PALETTE_LENGTH (256) /***/ - -#define DMA2D_MAX_WIDTH ((1 << 14) - 1) -#define DMA2D_MAX_HEIGHT ((1 << 16) - 1) - -#define DMA2D_MAX_WATERMARK_POS ((1 << 16) - 1) - -#define DMA2D_MAX_DEADTIME_CYCLES ((1 << 8) - 1) - -/** @} */ - -/** - * @name DMA2D basic ARGB-8888 colors. - * @{ - */ -/* Microsoft Windows default 16-color palette.*/ -#define DMA2D_COLOR_BLACK (0xFF000000) -#define DMA2D_COLOR_MAROON (0xFF800000) -#define DMA2D_COLOR_GREEN (0xFF008000) -#define DMA2D_COLOR_OLIVE (0xFF808000) -#define DMA2D_COLOR_NAVY (0xFF000080) -#define DMA2D_COLOR_PURPLE (0xFF800080) -#define DMA2D_COLOR_TEAL (0xFF008080) -#define DMA2D_COLOR_SILVER (0xFFC0C0C0) -#define DMA2D_COLOR_GRAY (0xFF808080) -#define DMA2D_COLOR_RED (0xFFFF0000) -#define DMA2D_COLOR_LIME (0xFF00FF00) -#define DMA2D_COLOR_YELLOW (0xFFFFFF00) -#define DMA2D_COLOR_BLUE (0xFF0000FF) -#define DMA2D_COLOR_FUCHSIA (0xFFFF00FF) -#define DMA2D_COLOR_AQUA (0xFF00FFFF) -#define DMA2D_COLOR_WHITE (0xFFFFFFFF) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name DMA2D configuration options - * @{ - */ - -/** - * @brief DMA2D event interrupt priority level setting. - */ -#if !defined(STM32_DMA2D_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_DMA2D_IRQ_PRIORITY (11) -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DMA2D_USE_WAIT) || defined(__DOXYGEN__) -#define DMA2D_USE_WAIT (TRUE) -#endif - -/** - * @brief Enables the @p dma2dAcquireBus() and @p dma2dReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DMA2D_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define DMA2D_USE_MUTUAL_EXCLUSION (TRUE) -#endif - -/** - * @brief Provides software color conversion functions. - * @note Disabling this option saves both code and data space. - */ -#if !defined(DMA2D_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__) -#define DMA2D_USE_SOFTWARE_CONVERSIONS (TRUE) -#endif - -/** - * @brief Enables checks for DMA2D functions. - * @note Disabling this option saves both code and data space. - * @note Disabling checks by ChibiOS will automatically disable DMA2D checks. - */ -#if !defined(DMA2D_USE_CHECKS) || defined(__DOXYGEN__) -#define DMA2D_USE_CHECKS (TRUE) -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (TRUE != STM32_HAS_DMA2D) -#error "DMA2D must be present when using the DMA2D subsystem" -#endif - -#if (TRUE != STM32_DMA2D_USE_DMA2D) && (TRUE != STM32_HAS_DMA2D) -#error "DMA2D not present in the selected device" -#endif - -#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION) -#if (TRUE != CH_CFG_USE_MUTEXES) && (TRUE != CH_CFG_USE_SEMAPHORES) -#error "DMA2D_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES" -#endif -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/* Complex types forwarding.*/ -typedef union dma2d_coloralias_t dma2d_coloralias_t; -typedef struct dma2d_palcfg_t dma2d_palcfg_t; -typedef struct dma2d_laycfg_t dma2d_layercfg_t; -typedef struct DMA2DConfig DMA2DConfig; -typedef enum dma2d_state_t dma2d_state_t; -typedef struct DMA2DDriver DMA2DDriver; - -/** - * @name DMA2D Data types - * @{ - */ - -/** - * @brief DMA2D generic color. - */ -typedef uint32_t dma2d_color_t; - -/** - * @brief DMA2D color aliases. - * @detail Mapped with ARGB-8888, except for luminance (L mapped onto B). - * Padding fields are prefixed with <tt>'x'</tt>, and should be clear - * (all 0) before compression and set (all 1) after expansion. - */ -typedef union dma2d_coloralias_t { - struct { - unsigned b : 8; - unsigned g : 8; - unsigned r : 8; - unsigned a : 8; - } argb8888; /**< Mapped ARGB-8888 bits.*/ - struct { - unsigned b : 8; - unsigned g : 8; - unsigned r : 8; - unsigned xa : 8; - } rgb888; /**< Mapped RGB-888 bits.*/ - struct { - unsigned xb : 3; - unsigned b : 5; - unsigned xg : 2; - unsigned g : 6; - unsigned xr : 3; - unsigned r : 5; - unsigned xa : 8; - } rgb565; /**< Mapped RGB-565 bits.*/ - struct { - unsigned xb : 3; - unsigned b : 5; - unsigned xg : 3; - unsigned g : 5; - unsigned xr : 3; - unsigned r : 5; - unsigned xa : 7; - unsigned a : 1; - } argb1555; /**< Mapped ARGB-1555 values.*/ - struct { - unsigned xb : 4; - unsigned b : 4; - unsigned xg : 4; - unsigned g : 4; - unsigned xr : 4; - unsigned r : 4; - unsigned xa : 4; - unsigned a : 4; - } argb4444; /**< Mapped ARGB-4444 values.*/ - struct { - unsigned l : 8; - unsigned x : 16; - unsigned xa : 8; - } l8; /**< Mapped L-8 bits.*/ - struct { - unsigned xl : 4; - unsigned l : 4; - unsigned x : 16; - unsigned xa : 4; - unsigned a : 4; - } al44; /**< Mapped AL-44 bits.*/ - struct { - unsigned l : 8; - unsigned x : 16; - unsigned a : 8; - } al88; /**< Mapped AL-88 bits.*/ - struct { - unsigned l : 4; - unsigned xl : 4; - unsigned x : 16; - unsigned xa : 8; - } l4; /**< Mapped L-4 bits.*/ - struct { - unsigned x : 24; - unsigned a : 8; - } a8; /**< Mapped A-8 bits.*/ - struct { - unsigned x : 24; - unsigned xa : 4; - unsigned a : 4; - } a4; /**< Mapped A-4 bits.*/ - dma2d_color_t aliased; /**< Aliased raw bits.*/ -} dma2d_coloralias_t; - -/** - * @brief DMA2D job (transfer) mode. - */ -typedef uint32_t dma2d_jobmode_t; - -/** - * @brief DMA2D pixel format. - */ -typedef uint32_t dma2d_pixfmt_t; - -/** - * @brief DMA2D alpha mode. - */ -typedef uint32_t dma2d_amode_t; - -/** - * @brief DMA2D ISR callback. - */ -typedef void (*dma2d_isrcb_t)(DMA2DDriver *dma2dp); - -/** - * @brief DMA2D palette specifications. - */ -typedef struct dma2d_palcfg_t { - const void *colorsp; /**< Pointer to color entries.*/ - uint16_t length; /**< Number of color entries.*/ - dma2d_pixfmt_t fmt; /**< Format, RGB-888 or ARGB-8888.*/ -} dma2d_palcfg_t; - -/** - * @brief DMA2D layer specifications. - */ -typedef struct dma2d_layercfg_t { - void *bufferp; /**< Frame buffer address.*/ - size_t wrap_offset; /**< Offset between lines, in pixels.*/ - dma2d_pixfmt_t fmt; /**< Pixel format.*/ - dma2d_color_t def_color; /**< Default color, RGB-888.*/ - uint8_t const_alpha; /**< Constant alpha factor.*/ - const dma2d_palcfg_t *palettep; /**< Palette specs, or @p NULL.*/ -} dma2d_laycfg_t; - -/** - * @brief DMA2D driver configuration. - */ -typedef struct DMA2DConfig { - /* ISR callbacks.*/ - dma2d_isrcb_t cfgerr_isr; /**< Configuration error, or @p NULL.*/ - dma2d_isrcb_t paltrfdone_isr; /**< Palette transfer done, or @p NULL.*/ - dma2d_isrcb_t palacserr_isr; /**< Palette access error, or @p NULL.*/ - dma2d_isrcb_t trfwmark_isr; /**< Transfer watermark, or @p NULL.*/ - dma2d_isrcb_t trfdone_isr; /**< Transfer complete, or @p NULL.*/ - dma2d_isrcb_t trferr_isr; /**< Transfer error, or @p NULL.*/ -} DMA2DConfig; - -/** - * @brief DMA2D driver state. - */ -typedef enum dma2d_state_t { - DMA2D_UNINIT = (0), /**< Not initialized.*/ - DMA2D_STOP = (1), /**< Stopped.*/ - DMA2D_READY = (2), /**< Ready.*/ - DMA2D_ACTIVE = (3), /**< Executing commands.*/ - DMA2D_PAUSED = (4), /**< Transfer suspended.*/ -} dma2d_state_t; - -/** - * @brief DMA2D driver. - */ -typedef struct DMA2DDriver { - dma2d_state_t state; /**< Driver state.*/ - const DMA2DConfig *config; /**< Driver configuration.*/ - - /* Multithreading stuff.*/ -#if (TRUE == DMA2D_USE_WAIT) || defined(__DOXYGEN__) - thread_t *thread; /**< Waiting thread.*/ -#endif /* DMA2D_USE_WAIT */ -#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION) -#if (TRUE == CH_CFG_USE_MUTEXES) - mutex_t lock; /**< Multithreading lock.*/ -#elif (TRUE == CH_CFG_USE_SEMAPHORES) - semaphore_t lock; /**< Multithreading lock.*/ -#endif -#endif /* DMA2D_USE_MUTUAL_EXCLUSION */ -} DMA2DDriver; - -/** @} */ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Makes an ARGB-8888 value from byte components. - * - * @param[in] a alpha byte component - * @param[in] r red byte component - * @param[in] g green byte component - * @param[in] b blue byte component - * - * @return color in ARGB-8888 format - * - * @api - */ -#define dma2dMakeARGB8888(a, r, g, b) \ - ((((dma2d_color_t)(a) & 0xFF) << 24) | \ - (((dma2d_color_t)(r) & 0xFF) << 16) | \ - (((dma2d_color_t)(g) & 0xFF) << 8) | \ - (((dma2d_color_t)(b) & 0xFF) << 0)) - -/** - * @brief Compute bytes per pixel. - * @details Computes the bytes per pixel for the specified pixel format. - * Rounds to the ceiling. - * - * @param[in] fmt pixel format - * - * @return bytes per pixel - * - * @api - */ -#define dma2dBytesPerPixel(fmt) \ - ((dma2dBitsPerPixel(fmt) + 7) >> 3) - -/** - * @brief Compute pixel address. - * @details Computes the buffer address of a pixel, given the buffer - * specifications. - * - * @param[in] originp buffer origin address - * @param[in] pitch buffer pitch, in bytes - * @param[in] fmt buffer pixel format - * @param[in] x horizontal pixel coordinate - * @param[in] y vertical pixel coordinate - * - * @return pixel address - * - * @api - */ -#define dma2dComputeAddress(originp, pitch, fmt, x, y) \ - ((void *)dma2dComputeAddressConst(originp, pitch, fmt, x, y)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern DMA2DDriver DMA2DD1; - -#ifdef __cplusplus -extern "C" { -#endif - - /* Driver methods.*/ - void dma2dInit(void); - void dma2dObjectInit(DMA2DDriver *dma2dp); - dma2d_state_t dma2dGetStateI(DMA2DDriver *dma2dp); - dma2d_state_t dma2dGetState(DMA2DDriver *dma2dp); - void dma2dStart(DMA2DDriver *dma2dp, const DMA2DConfig *configp); - void dma2dStop(DMA2DDriver *dma2dp); -#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION) - void dma2dAcquireBusS(DMA2DDriver *dma2dp); - void dma2dAcquireBus(DMA2DDriver *dma2dp); - void dma2dReleaseBusS(DMA2DDriver *dma2dp); - void dma2dReleaseBus(DMA2DDriver *dma2dp); -#endif /* DMA2D_USE_MUTUAL_EXCLUSION */ - - /* Global methods.*/ - uint16_t dma2dGetWatermarkPosI(DMA2DDriver *dma2dp); - uint16_t dma2dGetWatermarkPos(DMA2DDriver *dma2dp); - void dma2dSetWatermarkPosI(DMA2DDriver *dma2dp, uint16_t line); - void dma2dSetWatermarkPos(DMA2DDriver *dma2dp, uint16_t line); - bool dma2dIsWatermarkEnabledI(DMA2DDriver *dma2dp); - bool dma2dIsWatermarkEnabled(DMA2DDriver *dma2dp); - void dma2dEnableWatermarkI(DMA2DDriver *dma2dp); - void dma2dEnableWatermark(DMA2DDriver *dma2dp); - void dma2dDisableWatermarkI(DMA2DDriver *dma2dp); - void dma2dDisableWatermark(DMA2DDriver *dma2dp); - uint32_t dma2dGetDeadTimeI(DMA2DDriver *dma2dp); - uint32_t dma2dGetDeadTime(DMA2DDriver *dma2dp); - void dma2dSetDeadTimeI(DMA2DDriver *dma2dp, uint32_t cycles); - void dma2dSetDeadTime(DMA2DDriver *dma2dp, uint32_t cycles); - bool dma2dIsDeadTimeEnabledI(DMA2DDriver *dma2dp); - bool dma2dIsDeadTimeEnabled(DMA2DDriver *dma2dp); - void dma2dEnableDeadTimeI(DMA2DDriver *dma2dp); - void dma2dEnableDeadTime(DMA2DDriver *dma2dp); - void dma2dDisableDeadTimeI(DMA2DDriver *dma2dp); - void dma2dDisableDeadTime(DMA2DDriver *dma2dp); - - /* Job methods.*/ - dma2d_jobmode_t dma2dJobGetModeI(DMA2DDriver *dma2dp); - dma2d_jobmode_t dma2dJobGetMode(DMA2DDriver *dma2dp); - void dma2dJobSetModeI(DMA2DDriver *dma2dp, dma2d_jobmode_t mode); - void dma2dJobSetMode(DMA2DDriver *dma2dp, dma2d_jobmode_t mode); - void dma2dJobGetSizeI(DMA2DDriver *dma2dp, - uint16_t *widthp, uint16_t *heightp); - void dma2dJobGetSize(DMA2DDriver *dma2dp, - uint16_t *widthp, uint16_t *heightp); - void dma2dJobSetSizeI(DMA2DDriver *dma2dp, uint16_t width, uint16_t height); - void dma2dJobSetSize(DMA2DDriver *dma2dp, uint16_t width, uint16_t height); - bool dma2dJobIsExecutingI(DMA2DDriver *dma2dp); - bool dma2dJobIsExecuting(DMA2DDriver *dma2dp); - void dma2dJobStartI(DMA2DDriver *dma2dp); - void dma2dJobStart(DMA2DDriver *dma2dp); - void dma2dJobExecuteS(DMA2DDriver *dma2dp); - void dma2dJobExecute(DMA2DDriver *dma2dp); - void dma2dJobSuspendI(DMA2DDriver *dma2dp); - void dma2dJobSuspend(DMA2DDriver *dma2dp); - void dma2dJobResumeI(DMA2DDriver *dma2dp); - void dma2dJobResume(DMA2DDriver *dma2dp); - void dma2dJobAbortI(DMA2DDriver *dma2dp); - void dma2dJobAbort(DMA2DDriver *dma2dp); - - /* Background layer methods.*/ - void *dma2dBgGetAddressI(DMA2DDriver *dma2dp); - void *dma2dBgGetAddress(DMA2DDriver *dma2dp); - void dma2dBgSetAddressI(DMA2DDriver *dma2dp, void *bufferp); - void dma2dBgSetAddress(DMA2DDriver *dma2dp, void *bufferp); - size_t dma2dBgGetWrapOffsetI(DMA2DDriver *dma2dp); - size_t dma2dBgGetWrapOffset(DMA2DDriver *dma2dp); - void dma2dBgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset); - void dma2dBgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset); - uint8_t dma2dBgGetConstantAlphaI(DMA2DDriver *dma2dp); - uint8_t dma2dBgGetConstantAlpha(DMA2DDriver *dma2dp); - void dma2dBgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a); - void dma2dBgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a); - dma2d_amode_t dma2dBgGetAlphaModeI(DMA2DDriver *dma2dp); - dma2d_amode_t dma2dBgGetAlphaMode(DMA2DDriver *dma2dp); - void dma2dBgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode); - void dma2dBgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode); - dma2d_pixfmt_t dma2dBgGetPixelFormatI(DMA2DDriver *dma2dp); - dma2d_pixfmt_t dma2dBgGetPixelFormat(DMA2DDriver *dma2dp); - void dma2dBgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt); - void dma2dBgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt); - dma2d_color_t dma2dBgGetDefaultColorI(DMA2DDriver *dma2dp); - dma2d_color_t dma2dBgGetDefaultColor(DMA2DDriver *dma2dp); - void dma2dBgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c); - void dma2dBgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c); - void dma2dBgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep); - void dma2dBgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep); - void dma2dBgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep); - void dma2dBgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep); - void dma2dBgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp); - void dma2dBgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp); - void dma2dBgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp); - void dma2dBgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp); - - /* Foreground layer methods.*/ - void *dma2dFgGetAddressI(DMA2DDriver *dma2dp); - void *dma2dFgGetAddress(DMA2DDriver *dma2dp); - void dma2dFgSetAddressI(DMA2DDriver *dma2dp, void *bufferp); - void dma2dFgSetAddress(DMA2DDriver *dma2dp, void *bufferp); - size_t dma2dFgGetWrapOffsetI(DMA2DDriver *dma2dp); - size_t dma2dFgGetWrapOffset(DMA2DDriver *dma2dp); - void dma2dFgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset); - void dma2dFgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset); - uint8_t dma2dFgGetConstantAlphaI(DMA2DDriver *dma2dp); - uint8_t dma2dFgGetConstantAlpha(DMA2DDriver *dma2dp); - void dma2dFgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a); - void dma2dFgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a); - dma2d_amode_t dma2dFgGetAlphaModeI(DMA2DDriver *dma2dp); - dma2d_amode_t dma2dFgGetAlphaMode(DMA2DDriver *dma2dp); - void dma2dFgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode); - void dma2dFgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode); - dma2d_pixfmt_t dma2dFgGetPixelFormatI(DMA2DDriver *dma2dp); - dma2d_pixfmt_t dma2dFgGetPixelFormat(DMA2DDriver *dma2dp); - void dma2dFgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt); - void dma2dFgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt); - dma2d_color_t dma2dFgGetDefaultColorI(DMA2DDriver *dma2dp); - dma2d_color_t dma2dFgGetDefaultColor(DMA2DDriver *dma2dp); - void dma2dFgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c); - void dma2dFgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c); - void dma2dFgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep); - void dma2dFgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep); - void dma2dFgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep); - void dma2dFgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep); - void dma2dFgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp); - void dma2dFgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp); - void dma2dFgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp); - void dma2dFgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp); - - /* Output layer methods.*/ - void *dma2dOutGetAddressI(DMA2DDriver *dma2dp); - void *dma2dOutGetAddress(DMA2DDriver *dma2dp); - void dma2dOutSetAddressI(DMA2DDriver *dma2dp, void *bufferp); - void dma2dOutSetAddress(DMA2DDriver *dma2dp, void *bufferp); - size_t dma2dOutGetWrapOffsetI(DMA2DDriver *dma2dp); - size_t dma2dOutGetWrapOffset(DMA2DDriver *dma2dp); - void dma2dOutSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset); - void dma2dOutSetWrapOffset(DMA2DDriver *dma2dp, size_t offset); - dma2d_pixfmt_t dma2dOutGetPixelFormatI(DMA2DDriver *dma2dp); - dma2d_pixfmt_t dma2dOutGetPixelFormat(DMA2DDriver *dma2dp); - void dma2dOutSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt); - void dma2dOutSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt); - dma2d_color_t dma2dOutGetDefaultColorI(DMA2DDriver *dma2dp); - dma2d_color_t dma2dOutGetDefaultColor(DMA2DDriver *dma2dp); - void dma2dOutSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c); - void dma2dOutSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c); - void dma2dOutGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp); - void dma2dOutGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp); - void dma2dOutSetConfigI(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp); - void dma2dOutSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp); - - /* Helper functions.*/ - const void *dma2dComputeAddressConst(const void *originp, size_t pitch, - dma2d_pixfmt_t fmt, - uint16_t x, uint16_t y); - bool dma2dIsAligned(const void *bufferp, dma2d_pixfmt_t fmt); - size_t dma2dBitsPerPixel(dma2d_pixfmt_t fmt); -#if (TRUE == DMA2D_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__) - dma2d_color_t dma2dFromARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt); - dma2d_color_t dma2dToARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt); -#endif /* DMA2D_USE_SOFTWARE_CONVERSIONS */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32_DMA2D_USE_DMA2D */ - -#endif /* _STM32_DMA2D_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c deleted file mode 100644 index 8b1082c..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file fsmc.c - * @brief FSMC Driver subsystem low level driver source template. - * - * @addtogroup FSMC - * @{ - */ -#include "hal.h" -#include "hal_fsmc.h" - -#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief FSMC1 driver identifier. - */ -#if STM32_FSMC_USE_FSMC1 || defined(__DOXYGEN__) -FSMCDriver FSMCD1; -#endif - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level FSMC driver initialization. - * - * @notapi - */ -void fsmc_init(void) { - - if (FSMCD1.state == FSMC_UNINIT) { - FSMCD1.state = FSMC_STOP; - -#if STM32_SRAM_USE_FSMC_SRAM1 - FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE); -#endif - -#if STM32_SRAM_USE_FSMC_SRAM2 - FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8); -#endif - -#if STM32_SRAM_USE_FSMC_SRAM3 - FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2); -#endif - -#if STM32_SRAM_USE_FSMC_SRAM4 - FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3); -#endif - -#if STM32_NAND_USE_FSMC_NAND1 - FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; -#endif - -#if STM32_NAND_USE_FSMC_NAND2 - FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; -#endif - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) - #if STM32_USE_FSMC_SDRAM - FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; - #endif -#endif - } -} - -/** - * @brief Configures and activates the FSMC peripheral. - * - * @param[in] fsmcp pointer to the @p FSMCDriver object - * - * @notapi - */ -void fsmc_start(FSMCDriver *fsmcp) { - - osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY), - "invalid state"); - - if (fsmcp->state == FSMC_STOP) { - /* Enables the peripheral.*/ -#if STM32_FSMC_USE_FSMC1 - if (&FSMCD1 == fsmcp) { -#ifdef rccResetFSMC - rccResetFSMC(); -#endif - rccEnableFSMC(FALSE); -#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND) - nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY); -#endif - } -#endif /* STM32_FSMC_USE_FSMC1 */ - - fsmcp->state = FSMC_READY; - } -} - -/** - * @brief Deactivates the FSMC peripheral. - * - * @param[in] emcp pointer to the @p FSMCDriver object - * - * @notapi - */ -void fsmc_stop(FSMCDriver *fsmcp) { - - if (fsmcp->state == FSMC_READY) { - /* Resets the peripheral.*/ -#ifdef rccResetFSMC - rccResetFSMC(); -#endif - - /* Disables the peripheral.*/ -#if STM32_FSMC_USE_FSMC1 - if (&FSMCD1 == fsmcp) { -#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND) - nvicDisableVector(STM32_FSMC_NUMBER); -#endif - rccDisableFSMC(FALSE); - } -#endif /* STM32_FSMC_USE_FSMC1 */ - - fsmcp->state = FSMC_STOP; - } -} - -#if !STM32_NAND_USE_EXT_INT -/** - * @brief FSMC shared interrupt handler. - * - * @notapi - */ -CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { - - CH_IRQ_PROLOGUE(); -#if STM32_NAND_USE_FSMC_NAND1 - if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) { - NANDD1.isr_handler(&NANDD1); - } -#endif -#if STM32_NAND_USE_FSMC_NAND2 - if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) { - NANDD2.isr_handler(&NANDD2); - } -#endif - CH_IRQ_EPILOGUE(); -} -#endif /* !STM32_NAND_USE_EXT_INT */ - -#endif /* HAL_USE_FSMC */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h deleted file mode 100644 index 7889b01..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h +++ /dev/null @@ -1,339 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file fsmc.h - * @brief FSMC Driver subsystem low level driver header. - * - * @addtogroup FSMC - * @{ - */ - -#ifndef _FSMC_H_ -#define _FSMC_H_ - -#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * (Re)define if needed base address constants supplied in ST's CMSIS - */ -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) - #if !defined(FSMC_Bank1_R_BASE) - #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) - #endif - #if !defined(FSMC_Bank1E_R_BASE) - #define FSMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) - #endif - #if !defined(FSMC_Bank2_R_BASE) - #define FSMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) - #endif - #if !defined(FSMC_Bank3_R_BASE) - #define FSMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) - #endif - #if !defined(FSMC_Bank4_R_BASE) - #define FSMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) - #endif - #if !defined(FSMC_Bank5_R_BASE) - #define FSMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) - #endif -#else - #if !defined(FSMC_Bank1_R_BASE) - #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) - #endif - #if !defined(FSMC_Bank1E_R_BASE) - #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) - #endif - #if !defined(FSMC_Bank2_R_BASE) - #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) - #endif - #if !defined(FSMC_Bank3_R_BASE) - #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) - #endif - #if !defined(FSMC_Bank4_R_BASE) - #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) - #endif -#endif - -/* - * Base bank mappings - */ -#define FSMC_Bank1_MAP_BASE ((uint32_t) 0x60000000) -#define FSMC_Bank2_MAP_BASE ((uint32_t) 0x70000000) -#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000) -#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000) -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) - #define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000) - #define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000) -#endif - -/* - * Subbunks of bank1 - */ -#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64) -#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE) -#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET) -#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET) -#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET) - -/* - * Bank 2 (NAND) - */ -#define FSMC_Bank2_MAP_COMMON (FSMC_Bank2_MAP_BASE + 0) -#define FSMC_Bank2_MAP_ATTR (FSMC_Bank2_MAP_BASE + 0x8000000) - -#define FSMC_Bank2_MAP_COMMON_DATA (FSMC_Bank2_MAP_COMMON + 0) -#define FSMC_Bank2_MAP_COMMON_CMD (FSMC_Bank2_MAP_COMMON + 0x10000) -#define FSMC_Bank2_MAP_COMMON_ADDR (FSMC_Bank2_MAP_COMMON + 0x20000) - -#define FSMC_Bank2_MAP_ATTR_DATA (FSMC_Bank2_MAP_ATTR + 0) -#define FSMC_Bank2_MAP_ATTR_CMD (FSMC_Bank2_MAP_ATTR + 0x10000) -#define FSMC_Bank2_MAP_ATTR_ADDR (FSMC_Bank2_MAP_ATTR + 0x20000) - -/* - * Bank 3 (NAND) - */ -#define FSMC_Bank3_MAP_COMMON (FSMC_Bank3_MAP_BASE + 0) -#define FSMC_Bank3_MAP_ATTR (FSMC_Bank3_MAP_BASE + 0x8000000) - -#define FSMC_Bank3_MAP_COMMON_DATA (FSMC_Bank3_MAP_COMMON + 0) -#define FSMC_Bank3_MAP_COMMON_CMD (FSMC_Bank3_MAP_COMMON + 0x10000) -#define FSMC_Bank3_MAP_COMMON_ADDR (FSMC_Bank3_MAP_COMMON + 0x20000) - -#define FSMC_Bank3_MAP_ATTR_DATA (FSMC_Bank3_MAP_ATTR + 0) -#define FSMC_Bank3_MAP_ATTR_CMD (FSMC_Bank3_MAP_ATTR + 0x10000) -#define FSMC_Bank3_MAP_ATTR_ADDR (FSMC_Bank3_MAP_ATTR + 0x20000) - -/* - * Bank 4 (PC card) - */ -#define FSMC_Bank4_MAP_COMMON (FSMC_Bank4_MAP_BASE + 0) -#define FSMC_Bank4_MAP_ATTR (FSMC_Bank4_MAP_BASE + 0x8000000) -#define FSMC_Bank4_MAP_IO (FSMC_Bank4_MAP_BASE + 0xC000000) - -/* - * More convenient typedefs than CMSIS has - */ -typedef struct { - __IO uint32_t PCR; /**< NAND Flash control */ - __IO uint32_t SR; /**< NAND Flash FIFO status and interrupt */ - __IO uint32_t PMEM; /**< NAND Flash Common memory space timing */ - __IO uint32_t PATT; /**< NAND Flash Attribute memory space timing */ - uint32_t RESERVED0; /**< Reserved, 0x70 */ - __IO uint32_t ECCR; /**< NAND Flash ECC result registers */ -} FSMC_NAND_TypeDef; - -typedef struct { - __IO uint32_t PCR; /**< PC Card control */ - __IO uint32_t SR; /**< PC Card FIFO status and interrupt */ - __IO uint32_t PMEM; /**< PC Card Common memory space timing */ - __IO uint32_t PATT; /**< PC Card Attribute memory space timing */ - __IO uint32_t PIO; /**< PC Card I/O space timing */ -} FSMC_PCCard_TypeDef; - -typedef struct { - __IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */ - __IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */ - uint32_t RESERVED[63]; /**< Reserved */ - __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */ -} FSMC_SRAM_NOR_TypeDef; - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) - -typedef struct { - __IO uint32_t SDCR1; /**< SDRAM control register (bank 1) */ - __IO uint32_t SDCR2; /**< SDRAM control register (bank 2) */ - __IO uint32_t SDTR1; /**< SDRAM timing register (bank 1) */ - __IO uint32_t SDTR2; /**< SDRAM timing register (bank 2) */ - __IO uint32_t SDCMR; /**< SDRAM comand mode register */ - __IO uint32_t SDRTR; /**< SDRAM refresh timer register */ - __IO uint32_t SDSR; /**< SDRAM status register */ -} FSMC_SDRAM_TypeDef; - -#endif - -/** - * @brief PCR register - */ -#define FSMC_PCR_PWAITEN ((uint32_t)0x00000002) -#define FSMC_PCR_PBKEN ((uint32_t)0x00000004) -#define FSMC_PCR_PTYP ((uint32_t)0x00000008) -#define FSMC_PCR_ECCEN ((uint32_t)0x00000040) -#define FSMC_PCR_PTYP_PCCARD 0 -#define FSMC_PCR_PTYP_NAND FSMC_PCR_PTYP - -/** - * @brief SR register - */ -#define FSMC_SR_IRS ((uint8_t)0x01) -#define FSMC_SR_ILS ((uint8_t)0x02) -#define FSMC_SR_IFS ((uint8_t)0x04) -#define FSMC_SR_IREN ((uint8_t)0x08) -#define FSMC_SR_ILEN ((uint8_t)0x10) -#define FSMC_SR_IFEN ((uint8_t)0x20) -#define FSMC_SR_FEMPT ((uint8_t)0x40) -#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS) - -/** - * @brief BCR register - */ -#define FSMC_BCR_MBKEN ((uint32_t)1 << 0) -#define FSMC_BCR_MUXEN ((uint32_t)1 << 1) -#define FSMC_BCR_MTYP_SRAM ((uint32_t)0 << 2) -#define FSMC_BCR_MTYP_PSRAM ((uint32_t)1 << 2) -#define FSMC_BCR_MTYP_NOR_NAND ((uint32_t)2 << 2) -#define FSMC_BCR_MTYP_RESERVED ((uint32_t)3 << 2) -#define FSMC_BCR_MWID_8 ((uint32_t)0 << 4) -#define FSMC_BCR_MWID_16 ((uint32_t)1 << 4) -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) -#define FSMC_BCR_MWID_32 ((uint32_t)2 << 4) -#else -#define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4) -#endif -#define FSMC_BCR_MWID_RESERVED2 ((uint32_t)3 << 4) -#define FSMC_BCR_FACCEN ((uint32_t)1 << 6) -#define FSMC_BCR_BURSTEN ((uint32_t)1 << 8) -#define FSMC_BCR_WAITPOL ((uint32_t)1 << 9) -#define FSMC_BCR_WRAPMOD ((uint32_t)1 << 10) -#define FSMC_BCR_WAITCFG ((uint32_t)1 << 11) -#define FSMC_BCR_WREN ((uint32_t)1 << 12) -#define FSMC_BCR_WAITEN ((uint32_t)1 << 13) -#define FSMC_BCR_EXTMOD ((uint32_t)1 << 14) -#define FSMC_BCR_ASYNCWAIT ((uint32_t)1 << 15) -#define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief FSMC driver enable switch. - * @details If set to @p TRUE the support for FSMC is included. - */ -#if !defined(STM32_FSMC_USE_FSMC1) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_FSMC1 FALSE -#endif - -/** - * @brief Internal FSMC interrupt enable switch - * @details MCUs in 100-pin package has no dedicated interrupt pin for FSMC. - * You have to use EXTI module instead to workaround this issue. - */ -#if !defined(STM32_NAND_USE_EXT_INT) || defined(__DOXYGEN__) -#define STM32_NAND_USE_EXT_INT FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ -#if !STM32_FSMC_USE_FSMC1 -#error "FSMC driver activated but no FSMC peripheral assigned" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an FSMC driver. - */ -typedef struct FSMCDriver FSMCDriver; - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - FSMC_UNINIT = 0, /**< Not initialized. */ - FSMC_STOP = 1, /**< Stopped. */ - FSMC_READY = 2, /**< Ready. */ -} fsmcstate_t; - -/** - * @brief Structure representing an FSMC driver. - */ -struct FSMCDriver { - /** - * @brief Driver state. - */ - fsmcstate_t state; - /* End of the mandatory fields.*/ - -#if STM32_SRAM_USE_FSMC_SRAM1 - FSMC_SRAM_NOR_TypeDef *sram1; -#endif -#if STM32_SRAM_USE_FSMC_SRAM2 - FSMC_SRAM_NOR_TypeDef *sram2; -#endif -#if STM32_SRAM_USE_FSMC_SRAM3 - FSMC_SRAM_NOR_TypeDef *sram3; -#endif -#if STM32_SRAM_USE_FSMC_SRAM4 - FSMC_SRAM_NOR_TypeDef *sram4; -#endif -#if STM32_NAND_USE_FSMC_NAND1 - FSMC_NAND_TypeDef *nand1; -#endif -#if STM32_NAND_USE_FSMC_NAND2 - FSMC_NAND_TypeDef *nand2; -#endif -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) - #if STM32_USE_FSMC_SDRAM - FSMC_SDRAM_TypeDef *sdram; - #endif -#endif -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_FSMC_USE_FSMC1 && !defined(__DOXYGEN__) -extern FSMCDriver FSMCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void fsmc_init(void); - void fsmc_start(FSMCDriver *fsmcp); - void fsmc_stop(FSMCDriver *fsmcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_FSMC */ - -#endif /* _FSMC_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c deleted file mode 100644 index 95f47d5..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - SDRAM routines added by Nick Klimov aka progfin. - */ - -/** - * @file fsmc_sdram.c - * @brief SDRAM Driver subsystem low level driver source. - * - * @addtogroup SDRAM - * @{ - */ - -#include "hal.h" - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) - -#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) - -#include "hal_fsmc_sdram.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * FMC_Command_Mode - */ -#define FMCCM_NORMAL ((uint32_t)0x00000000) -#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001) -#define FMCCM_PALL ((uint32_t)0x00000002) -#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003) -#define FMCCM_LOAD_MODE ((uint32_t)0x00000004) -#define FMCCM_SELFREFRESH ((uint32_t)0x00000005) -#define FMCCM_POWER_DOWN ((uint32_t)0x00000006) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -/** - * @brief SDRAM driver identifier. - */ -SDRAMDriver SDRAMD; - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Wait until the SDRAM controller is ready. - * - * @notapi - */ -static void _sdram_wait_ready(void) { - /* Wait until the SDRAM controller is ready */ - while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY); -} - -/** - * @brief Executes the SDRAM memory initialization sequence. - * - * @param[in] cfgp pointer to the @p SDRAMConfig object - * - * @notapi - */ -static void _sdram_init_sequence(const SDRAMConfig *cfgp) { - - uint32_t command_target = 0; - -#if STM32_SDRAM_USE_FSMC_SDRAM1 - command_target |= FMC_SDCMR_CTB1; -#endif -#if STM32_SDRAM_USE_FSMC_SDRAM2 - command_target |= FMC_SDCMR_CTB2; -#endif - - /* Step 3: Configure a clock configuration enable command.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target; - - /* Step 4: Insert delay (tipically 100uS).*/ - osalThreadSleepMilliseconds(1); - - /* Step 5: Configure a PALL (precharge all) command.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_PALL | command_target; - - /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | - (cfgp->sdcmr & FMC_SDCMR_NRFS); - - /* Step 6.2: Send the second command.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | - (cfgp->sdcmr & FMC_SDCMR_NRFS); - - /* Step 7: Program the external memory mode register.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_LOAD_MODE | command_target | - (cfgp->sdcmr & FMC_SDCMR_MRD); - - /* Step 8: Set clock.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT; - - _sdram_wait_ready(); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SDRAM driver initialization. - */ -void fsmcSdramInit(void) { - - fsmc_init(); - - SDRAMD.sdram = FSMCD1.sdram; - SDRAMD.state = SDRAM_STOP; -} - -/** - * @brief Configures and activates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * @param[in] cfgp pointer to the @p SDRAMConfig object - */ -void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) { - - if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); - - osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), - "SDRAM. Invalid state."); - - if (sdramp->state == SDRAM_STOP) { - - /* Even if you need only bank2 you must properly set up SDCR and SDTR - regitsters for bank1 too. Both banks will be tuned equally assuming - connected memory ICs are equal.*/ - sdramp->sdram->SDCR1 = cfgp->sdcr; - sdramp->sdram->SDTR1 = cfgp->sdtr; - sdramp->sdram->SDCR2 = cfgp->sdcr; - sdramp->sdram->SDTR2 = cfgp->sdtr; - - _sdram_init_sequence(cfgp); - - sdramp->state = SDRAM_READY; - } -} - -/** - * @brief Deactivates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * - * @notapi - */ -void fsmcSdramStop(SDRAMDriver *sdramp) { - - uint32_t command_target = 0; - -#if STM32_SDRAM_USE_FSMC_SDRAM1 - command_target |= FMC_SDCMR_CTB1; -#endif -#if STM32_SDRAM_USE_FSMC_SDRAM2 - command_target |= FMC_SDCMR_CTB2; -#endif - - if (sdramp->state == SDRAM_READY) { - SDRAMD.sdram->SDCMR = FMCCM_POWER_DOWN | command_target; - sdramp->state = SDRAM_STOP; - } -} - -#endif /* STM32_USE_FSMC_SDRAM */ - -#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ - -/** @} */ - diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h deleted file mode 100644 index cef6772..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - SDRAM routines added by Nick Klimov aka progfin. - */ - -/** - * @file fsmc_sdram.h - * @brief SDRAM Driver subsystem low level driver header. - * - * @addtogroup SDRAM - * @{ - */ - -#ifndef _FMC_SDRAM_H_ -#define _FMC_SDRAM_H_ - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) - -#include "hal_fsmc.h" - -#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM1 is included. - */ -#if !defined(STM32_SDRAM_USE_FSMC_SDRAM1) || defined(__DOXYGEN__) -#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE -#else -#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE -#endif - -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM2 is included. - */ -#if !defined(STM32_SDRAM_USE_FSMC_SDRAM2) || defined(__DOXYGEN__) -#define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE -#else -#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_SDRAM_USE_FSMC_SDRAM1 && !STM32_SDRAM_USE_FSMC_SDRAM2 -#error "SDRAM driver activated but no SDRAM peripheral assigned" -#endif - -#if (STM32_SDRAM_USE_FSMC_SDRAM1 || STM32_SDRAM_USE_FSMC_SDRAM2) && !STM32_HAS_FSMC -#error "FMC not present in the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SDRAM_UNINIT = 0, /**< Not initialized. */ - SDRAM_STOP = 1, /**< Stopped. */ - SDRAM_READY = 2, /**< Ready. */ -} sdramstate_t; - -/** - * @brief Type of a structure representing an SDRAM driver. - */ -typedef struct SDRAMDriver SDRAMDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief SDRAM control register. - * @note Its value will be used for both banks. - */ - uint32_t sdcr; - - /** - * @brief SDRAM timing register. - * @note Its value will be used for both banks. - */ - uint32_t sdtr; - - /** - * @brief SDRAM command mode register. - * @note Only its MRD and NRFS bits will be used. - */ - uint32_t sdcmr; - - /** - * @brief SDRAM refresh timer register. - * @note Only its COUNT bits will be used. - */ - uint32_t sdrtr; -} SDRAMConfig; - -/** - * @brief Structure representing an SDRAM driver. - */ -struct SDRAMDriver { - /** - * @brief Driver state. - */ - sdramstate_t state; - /** - * @brief Pointer to the FMC SDRAM registers block. - */ - FSMC_SDRAM_TypeDef *sdram; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern SDRAMDriver SDRAMD; - -#ifdef __cplusplus -extern "C" { -#endif - void fsmcSdramInit(void); - void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); - void fsmcSdramStop(SDRAMDriver *sdramp); -#ifdef __cplusplus -} -#endif - -#endif /* STM32_USE_FSMC_SDRAM */ - -#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ - -#endif /* _FMC_SDRAM_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c deleted file mode 100644 index 6f710d4..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file fsmc_sram.c - * @brief SRAM Driver subsystem low level driver source. - * - * @addtogroup SRAM - * @{ - */ -#include "hal.h" -#include "hal_fsmc_sram.h" - -#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -/** - * @brief SRAM1 driver identifier. - */ -#if STM32_SRAM_USE_FSMC_SRAM1 || defined(__DOXYGEN__) -SRAMDriver SRAMD1; -#endif - -/** - * @brief SRAM2 driver identifier. - */ -#if STM32_SRAM_USE_FSMC_SRAM2 || defined(__DOXYGEN__) -SRAMDriver SRAMD2; -#endif - -/** - * @brief SRAM3 driver identifier. - */ -#if STM32_SRAM_USE_FSMC_SRAM3 || defined(__DOXYGEN__) -SRAMDriver SRAMD3; -#endif - -/** - * @brief SRAM4 driver identifier. - */ -#if STM32_SRAM_USE_FSMC_SRAM4 || defined(__DOXYGEN__) -SRAMDriver SRAMD4; -#endif - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SRAM driver initialization. - * - * @notapi - */ -void fsmcSramInit(void) { - - fsmc_init(); - -#if STM32_SRAM_USE_FSMC_SRAM1 - SRAMD1.sram = FSMCD1.sram1; - SRAMD1.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM1 */ - -#if STM32_SRAM_USE_FSMC_SRAM2 - SRAMD2.sram = FSMCD1.sram2; - SRAMD2.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM2 */ - -#if STM32_SRAM_USE_FSMC_SRAM3 - SRAMD3.sram = FSMCD1.sram3; - SRAMD3.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM3 */ - -#if STM32_SRAM_USE_FSMC_SRAM4 - SRAMD4.sram = FSMCD1.sram4; - SRAMD4.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM4 */ -} - -/** - * @brief Configures and activates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * @param[in] cfgp pointer to the @p SRAMConfig object - * - * @notapi - */ -void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { - - if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); - - osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), - "invalid state"); - - if (sramp->state == SRAM_STOP) { - sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN; - sramp->sram->BTR = cfgp->btr; - sramp->sram->BWTR = cfgp->bwtr; - sramp->state = SRAM_READY; - } -} - -/** - * @brief Deactivates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * - * @notapi - */ -void fsmcSramStop(SRAMDriver *sramp) { - - if (sramp->state == SRAM_READY) { - sramp->sram->BCR &= ~FSMC_BCR_MBKEN; - sramp->state = SRAM_STOP; - } -} - -#endif /* STM32_USE_FSMC_SRAM */ - -/** @} */ - diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h deleted file mode 100644 index 529bdc7..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file fsmc_sram.h - * @brief SRAM Driver subsystem low level driver header. - * - * @addtogroup SRAM - * @{ - */ - -#ifndef _FSMC_SRAM_H_ -#define _FSMC_SRAM_H_ - -#include "hal_fsmc.h" - -#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM1 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM2 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM3 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM4 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \ - !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4 -#error "SRAM driver activated but no SRAM peripheral assigned" -#endif - -#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \ - STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC -#error "FSMC not present in the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SRAM_UNINIT = 0, /**< Not initialized. */ - SRAM_STOP = 1, /**< Stopped. */ - SRAM_READY = 2, /**< Ready. */ -} sramstate_t; - -/** - * @brief Type of a structure representing an NAND driver. - */ -typedef struct SRAMDriver SRAMDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - * @note Some bits in BCR register will be forced by driver. - */ -typedef struct { - uint32_t bcr; - uint32_t btr; - uint32_t bwtr; -} SRAMConfig; - -/** - * @brief Structure representing an NAND driver. - */ -struct SRAMDriver { - /** - * @brief Driver state. - */ - sramstate_t state; - /** - * @brief Pointer to the FSMC SRAM registers block. - */ - FSMC_SRAM_NOR_TypeDef *sram; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD1; -#endif - -#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD2; -#endif - -#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD3; -#endif - -#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD4; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void fsmcSramInit(void); - void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); - void fsmcSramStop(SRAMDriver *sramp); -#ifdef __cplusplus -} -#endif - -#endif /* STM32_USE_FSMC_SRAM */ - -#endif /* _FSMC_SRAM_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c deleted file mode 100644 index b37c026..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c +++ /dev/null @@ -1,515 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file nand_lld.c - * @brief NAND Driver subsystem low level driver source. - * - * @addtogroup NAND - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ -#define NAND_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_NAND_DMA_STREAM, \ - STM32_FSMC_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief NAND1 driver identifier. - */ -#if STM32_NAND_USE_FSMC_NAND1 || defined(__DOXYGEN__) -NANDDriver NANDD1; -#endif - -/** - * @brief NAND2 driver identifier. - */ -#if STM32_NAND_USE_FSMC_NAND2 || defined(__DOXYGEN__) -NANDDriver NANDD2; -#endif - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ -/** - * @brief Wakes up the waiting thread. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] msg wakeup message - * - * @notapi - */ -static void wakeup_isr(NANDDriver *nandp) { - - osalDbgCheck(nandp->thread != NULL); - osalThreadResumeI(&nandp->thread, MSG_OK); -} - -/** - * @brief Put calling thread in suspend and switch driver state - * - * @param[in] nandp pointer to the @p NANDDriver object - */ -static void nand_lld_suspend_thread(NANDDriver *nandp) { - - osalThreadSuspendS(&nandp->thread); -} - -/** - * @brief Caclulate ECCPS register value - * - * @param[in] nandp pointer to the @p NANDDriver object - */ -static uint32_t calc_eccps(NANDDriver *nandp) { - - uint32_t i = 0; - uint32_t eccps = nandp->config->page_data_size; - - eccps = eccps >> 9; - while (eccps > 0){ - i++; - eccps >>= 1; - } - - return i << 17; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief Enable interrupts from NAND - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_ready_isr_enable(NANDDriver *nandp) { -#if STM32_NAND_USE_EXT_INT - nandp->config->ext_nand_isr_enable(); -#else - nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS | - FSMC_SR_ILEN | FSMC_SR_IFEN); - nandp->nand->SR |= FSMC_SR_IREN; -#endif -} - -/** - * @brief Disable interrupts from NAND - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_ready_isr_disable(NANDDriver *nandp) { -#if STM32_NAND_USE_EXT_INT - nandp->config->ext_nand_isr_disable(); -#else - nandp->nand->SR &= ~FSMC_SR_IREN; -#endif -} - -/** - * @brief Ready interrupt handler - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_isr_handler (NANDDriver *nandp) { - - osalSysLockFromISR(); - -#if !STM32_NAND_USE_EXT_INT - osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */ - nandp->nand->SR &= ~FSMC_SR_IRS; -#endif - - switch (nandp->state){ - case NAND_READ: - nandp->state = NAND_DMA_RX; - dmaStartMemCopy(nandp->dma, nandp->dmamode, - nandp->map_data, nandp->rxdata, nandp->datalen); - /* thread will be waked up from DMA ISR */ - break; - - case NAND_ERASE: - /* NAND reports about erase finish */ - nandp->state = NAND_READY; - wakeup_isr(nandp); - break; - - case NAND_PROGRAM: - /* NAND reports about page programming finish */ - nandp->state = NAND_READY; - wakeup_isr(nandp); - break; - - default: - osalSysHalt("Unhandled case"); - break; - } - osalSysUnlockFromISR(); -} - -/** - * @brief DMA RX end IRQ handler. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] flags pre-shifted content of the ISR register - * - * @notapi - */ -static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) { - /* DMA errors handling.*/ -#if defined(STM32_NAND_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_NAND_DMA_ERROR_HOOK(nandp); - } -#else - (void)flags; -#endif - - osalSysLockFromISR(); - - dmaStreamDisable(nandp->dma); - - switch (nandp->state){ - case NAND_DMA_TX: - nandp->state = NAND_PROGRAM; - nandp->map_cmd[0] = NAND_CMD_PAGEPROG; - /* thread will be woken from ready_isr() */ - break; - - case NAND_DMA_RX: - nandp->state = NAND_READY; - nandp->rxdata = NULL; - nandp->datalen = 0; - wakeup_isr(nandp); - break; - - default: - osalSysHalt("Unhandled case"); - break; - } - - osalSysUnlockFromISR(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level NAND driver initialization. - * - * @notapi - */ -void nand_lld_init(void) { - - fsmc_init(); - -#if STM32_NAND_USE_FSMC_NAND1 - /* Driver initialization.*/ - nandObjectInit(&NANDD1); - NANDD1.rxdata = NULL; - NANDD1.datalen = 0; - NANDD1.thread = NULL; - NANDD1.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); - NANDD1.nand = FSMCD1.nand1; - NANDD1.map_data = (uint8_t*)FSMC_Bank2_MAP_COMMON_DATA; - NANDD1.map_cmd = (uint8_t*)FSMC_Bank2_MAP_COMMON_CMD; - NANDD1.map_addr = (uint8_t*)FSMC_Bank2_MAP_COMMON_ADDR; - NANDD1.bb_map = NULL; -#endif /* STM32_NAND_USE_FSMC_NAND1 */ - -#if STM32_NAND_USE_FSMC_NAND2 - /* Driver initialization.*/ - nandObjectInit(&NANDD2); - NANDD2.rxdata = NULL; - NANDD2.datalen = 0; - NANDD2.thread = NULL; - NANDD2.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); - NANDD2.nand = FSMCD1.nand2; - NANDD2.map_data = (uint8_t*)FSMC_Bank3_MAP_COMMON_DATA; - NANDD2.map_cmd = (uint8_t*)FSMC_Bank3_MAP_COMMON_CMD; - NANDD2.map_addr = (uint8_t*)FSMC_Bank3_MAP_COMMON_ADDR; - NANDD2.bb_map = NULL; -#endif /* STM32_NAND_USE_FSMC_NAND2 */ -} - -/** - * @brief Configures and activates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -void nand_lld_start(NANDDriver *nandp) { - - bool b; - - if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); - - if (nandp->state == NAND_STOP) { - b = dmaStreamAllocate(nandp->dma, - STM32_EMC_FSMC1_IRQ_PRIORITY, - (stm32_dmaisr_t)nand_lld_serve_transfer_end_irq, - (void *)nandp); - osalDbgAssert(!b, "stream already allocated"); - nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_TCIE; - /* dmaStreamSetFIFO(nandp->dma, - STM32_DMA_FCR_DMDIS | NAND_STM32_DMA_FCR_FTH_LVL); */ - nandp->nand->PCR = calc_eccps(nandp) | FSMC_PCR_PTYP | FSMC_PCR_PBKEN; - nandp->nand->PMEM = nandp->config->pmem; - nandp->nand->PATT = nandp->config->pmem; - nandp->isr_handler = nand_isr_handler; - nand_ready_isr_enable(nandp); - } -} - -/** - * @brief Deactivates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -void nand_lld_stop(NANDDriver *nandp) { - - if (nandp->state == NAND_READY) { - dmaStreamRelease(nandp->dma); - nandp->nand->PCR &= ~FSMC_PCR_PBKEN; - nand_ready_isr_disable(nandp); - nandp->isr_handler = NULL; - } -} - -/** - * @brief Read data from NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[out] data pointer to data buffer - * @param[in] datalen size of data buffer - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * @param[out] ecc pointer to store computed ECC. Ignored when NULL. - * - * @notapi - */ -void nand_lld_read_data(NANDDriver *nandp, uint8_t *data, size_t datalen, - uint8_t *addr, size_t addrlen, uint32_t *ecc){ - - nandp->state = NAND_READ; - nandp->rxdata = data; - nandp->datalen = datalen; - - nand_lld_write_cmd (nandp, NAND_CMD_READ0); - nand_lld_write_addr(nandp, addr, addrlen); - osalSysLock(); - nand_lld_write_cmd (nandp, NAND_CMD_READ0_CONFIRM); - - /* Here NAND asserts busy signal and starts transferring from memory - array to page buffer. After the end of transmission ready_isr functions - starts DMA transfer from page buffer to MCU's RAM.*/ - osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, - "State machine broken. ECCEN must be previously disabled."); - - if (NULL != ecc){ - nandp->nand->PCR |= FSMC_PCR_ECCEN; - } - - nand_lld_suspend_thread(nandp); - osalSysUnlock(); - - /* thread was woken up from DMA ISR */ - if (NULL != ecc){ - while (! (nandp->nand->SR & FSMC_SR_FEMPT)) - ; - *ecc = nandp->nand->ECCR; - nandp->nand->PCR &= ~FSMC_PCR_ECCEN; - } -} - -/** - * @brief Write data to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] data buffer with data to be written - * @param[in] datalen size of data buffer - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * @param[out] ecc pointer to store computed ECC. Ignored when NULL. - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @notapi - */ -uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc) { - - nandp->state = NAND_WRITE; - - nand_lld_write_cmd (nandp, NAND_CMD_WRITE); - osalSysLock(); - nand_lld_write_addr(nandp, addr, addrlen); - - /* Now start DMA transfer to NAND buffer and put thread in sleep state. - Tread will be woken up from ready ISR. */ - nandp->state = NAND_DMA_TX; - osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, - "State machine broken. ECCEN must be previously disabled."); - - if (NULL != ecc){ - nandp->nand->PCR |= FSMC_PCR_ECCEN; - } - - dmaStartMemCopy(nandp->dma, nandp->dmamode, data, nandp->map_data, datalen); - - nand_lld_suspend_thread(nandp); - osalSysUnlock(); - - if (NULL != ecc){ - while (! (nandp->nand->SR & FSMC_SR_FEMPT)) - ; - *ecc = nandp->nand->ECCR; - nandp->nand->PCR &= ~FSMC_PCR_ECCEN; - } - - return nand_lld_read_status(nandp); -} - -/** - * @brief Erase block. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @notapi - */ -uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen) { - - nandp->state = NAND_ERASE; - - nand_lld_write_cmd (nandp, NAND_CMD_ERASE); - nand_lld_write_addr(nandp, addr, addrlen); - osalSysLock(); - nand_lld_write_cmd (nandp, NAND_CMD_ERASE_CONFIRM); - nand_lld_suspend_thread(nandp); - osalSysUnlock(); - - return nand_lld_read_status(nandp); -} - -/** - * @brief Read data from NAND using polling approach. - * - * @detatils Use this function to read data when no waiting expected. For - * Example read status word after 0x70 command - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[out] data pointer to output buffer - * @param[in] len length of data to be read - * - * @notapi - */ -void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len) { - size_t i = 0; - - for (i=0; i<len; i++) - data[i] = nandp->map_data[i]; -} - -/** - * @brief Send addres to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] len length of address array - * @param[in] addr pointer to address array - * - * @notapi - */ -void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len) { - size_t i = 0; - - for (i=0; i<len; i++) - nandp->map_addr[i] = addr[i]; -} - -/** - * @brief Send command to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] cmd command value - * - * @notapi - */ -void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd) { - nandp->map_cmd[0] = cmd; -} - -/** - * @brief Read status byte from NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @return Status byte. - * - * @notapi - */ -uint8_t nand_lld_read_status(NANDDriver *nandp) { - - uint8_t status[1] = {0x01}; /* presume worse */ - - nand_lld_write_cmd(nandp, NAND_CMD_STATUS); - nand_lld_polled_read_data(nandp, status, 1); - - return status[0]; -} - -#endif /* HAL_USE_NAND */ - -/** @} */ - diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h deleted file mode 100644 index 8dca42f..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file nand_lld.h - * @brief NAND Driver subsystem low level driver header. - * - * @addtogroup NAND - * @{ - */ - -#ifndef _NAND_LLD_H_ -#define _NAND_LLD_H_ - -#include "hal_fsmc.h" -#include "bitmap.h" - -#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ -#define NAND_MIN_PAGE_SIZE 256 -#define NAND_MAX_PAGE_SIZE 8192 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief FSMC1 interrupt priority level setting. - */ -#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EMC_FSMC1_IRQ_PRIORITY 10 -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND1 is included. - */ -#if !defined(STM32_NAND_USE_NAND1) || defined(__DOXYGEN__) -#define STM32_NAND_USE_NAND1 FALSE -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND2 is included. - */ -#if !defined(STM32_NAND_USE_NAND2) || defined(__DOXYGEN__) -#define STM32_NAND_USE_NAND2 FALSE -#endif - -/** - * @brief NAND DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") -#endif - -/** - * @brief NAND interrupt enable switch. - * @details If set to @p TRUE the support for internal FSMC interrupt included. - */ -#if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__) -#define STM32_NAND_USE_INT FALSE -#endif - -/** -* @brief NAND1 DMA priority (0..3|lowest..highest). -*/ -#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_NAND_NAND1_DMA_PRIORITY 0 -#endif - -/** -* @brief NAND2 DMA priority (0..3|lowest..highest). -*/ -#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_NAND_NAND2_DMA_PRIORITY 0 -#endif - -/** - * @brief DMA stream used for NAND operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_NAND_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_NAND_USE_FSMC_NAND1 && !STM32_NAND_USE_FSMC_NAND2 -#error "NAND driver activated but no NAND peripheral assigned" -#endif - -#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && !STM32_HAS_FSMC -#error "FSMC not present in the selected device" -#endif - -#if STM32_NAND_USE_EXT_INT && !HAL_USE_EXT -#error "External interrupt controller must be enabled to use this feature" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief NAND driver condition flags type. - */ -typedef uint32_t nandflags_t; - -/** - * @brief Type of a structure representing an NAND driver. - */ -typedef struct NANDDriver NANDDriver; - -/** - * @brief Type of interrupt handler function - */ -typedef void (*nandisrhandler_t)(NANDDriver *nandp); - -#if STM32_NAND_USE_EXT_INT -/** - * @brief Type of function switching external interrupts on and off. - */ -typedef void (*nandisrswitch_t)(void); -#endif /* STM32_NAND_USE_EXT_INT */ - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Pointer to lower level driver. - */ - //const FSMCDriver *fsmcp; - /** - * @brief Number of erase blocks in NAND device. - */ - uint32_t blocks; - /** - * @brief Number of data bytes in page. - */ - uint32_t page_data_size; - /** - * @brief Number of spare bytes in page. - */ - uint32_t page_spare_size; - /** - * @brief Number of pages in block. - */ - uint32_t pages_per_block; - /** - * @brief Number of write cycles for row addressing. - */ - uint8_t rowcycles; - /** - * @brief Number of write cycles for column addressing. - */ - uint8_t colcycles; - - /* End of the mandatory fields.*/ - /** - * @brief Number of wait cycles. This value will be used both for - * PMEM and PATTR registers - * - * @note For proper calculation procedure please look at AN2784 document - * from STMicroelectronics. - */ - uint32_t pmem; -#if STM32_NAND_USE_EXT_INT - /** - * @brief Function enabling interrupts from EXTI - */ - nandisrswitch_t ext_nand_isr_enable; - /** - * @brief Function disabling interrupts from EXTI - */ - nandisrswitch_t ext_nand_isr_disable; -#endif /* STM32_NAND_USE_EXT_INT */ -} NANDConfig; - -/** - * @brief Structure representing an NAND driver. - */ -struct NANDDriver { - /** - * @brief Driver state. - */ - nandstate_t state; - /** - * @brief Current configuration data. - */ - const NANDConfig *config; - /** - * @brief Array to store bad block map. - */ -#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#elif CH_CFG_USE_SEMAPHORES - semaphore_t semaphore; -#endif -#endif /* NAND_USE_MUTUAL_EXCLUSION */ - /* End of the mandatory fields.*/ - /** - * @brief Function enabling interrupts from FSMC - */ - nandisrhandler_t isr_handler; - /** - * @brief Pointer to current transaction buffer - */ - uint8_t *rxdata; - /** - * @brief Current transaction length - */ - size_t datalen; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief DMA channel. - */ - const stm32_dma_stream_t *dma; - /** - * @brief Thread waiting for I/O completion. - */ - thread_t *thread; - /** - * @brief Pointer to the FSMC NAND registers block. - */ - FSMC_NAND_TypeDef *nand; - /** - * @brief Memory mapping for data. - */ - uint8_t *map_data; - /** - * @brief Memory mapping for commands. - */ - uint8_t *map_cmd; - /** - * @brief Memory mapping for addresses. - */ - uint8_t *map_addr; - /** - * @brief Pointer to bad block map. - * @details One bit per block. All memory allocation is user's responsibility. - */ - bitmap_t *bb_map; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_NAND_USE_FSMC_NAND1 && !defined(__DOXYGEN__) -extern NANDDriver NANDD1; -#endif - -#if STM32_NAND_USE_FSMC_NAND2 && !defined(__DOXYGEN__) -extern NANDDriver NANDD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void nand_lld_init(void); - void nand_lld_start(NANDDriver *nandp); - void nand_lld_stop(NANDDriver *nandp); - void nand_lld_read_data(NANDDriver *nandp, uint8_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len); - void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); - void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); - uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); - uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - uint8_t nand_lld_read_status(NANDDriver *nandp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_NAND */ - -#endif /* _NAND_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c deleted file mode 100644 index e5f9a09..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c +++ /dev/null @@ -1,3792 +0,0 @@ -/* - Copyright (C) 2013-2015 Andrea Zoppi - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file stm32_ltdc.c - * @brief LCD-TFT Controller Driver. - */ - -#include "ch.h" -#include "hal.h" - -#include "hal_stm32_ltdc.h" - -#if (TRUE == STM32_LTDC_USE_LTDC) || defined(__DOXYGEN__) - -/* TODO: Check preconditions (e.g., LTDC is ready).*/ - -/* Ignore annoying warning messages for actually safe code.*/ -#if defined(__GNUC__) && !defined(__DOXYGEN__) -#pragma GCC diagnostic ignored "-Wtype-limits" -#endif - -/** - * @addtogroup ltdc - * @{ - */ - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if !defined(LTDC_LxBFCR_BF) && !defined(__DOXYGEN__) -#define LTDC_LxBFCR_BF (LTDC_LxBFCR_BF1 | LTDC_LxBFCR_BF2) -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief LTDC1 driver identifier. - */ -LTDCDriver LTDCD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Bits per pixel lookup table. - */ -static const uint8_t ltdc_bpp[LTDC_MAX_PIXFMT_ID + 1] = { - 32, /* LTDC_FMT_ARGB8888 */ - 24, /* LTDC_FMT_RGB888 */ - 16, /* LTDC_FMT_RGB565 */ - 16, /* LTDC_FMT_ARGB1555 */ - 16, /* LTDC_FMT_ARGB4444 */ - 8, /* LTDC_FMT_L8 */ - 8, /* LTDC_FMT_AL44 */ - 16 /* LTDC_FMT_AL88 */ -}; - -/** - * @brief Invalid frame. - */ -static const ltdc_frame_t ltdc_invalid_frame = { - NULL, - 1, - 1, - 1, - LTDC_FMT_L8 -}; - -/** - * @brief Invalid window. - * @details Pixel size, located at the origin of the screen. - */ -static const ltdc_window_t ltdc_invalid_window = { - 0, - 1, - 0, - 1 -}; - -/** - * @brief Default layer specifications. - */ -static const ltdc_laycfg_t ltdc_default_laycfg = { - <dc_invalid_frame, - <dc_invalid_window, - LTDC_COLOR_BLACK, - 0x00, - LTDC_COLOR_BLACK, - NULL, - 0, - LTDC_BLEND_FIX1_FIX2, - 0 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Forces LTDC register reload. - * @details Blocking function. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @sclass - * @notapi - */ -static void ltdc_force_reload_s(LTDCDriver *ltdcp) { - - osalDbgCheckClassS(); - osalDbgCheck(ltdcp == <DCD1); - - LTDC->SRCR |= LTDC_SRCR_IMR; - while (LTDC->SRCR & (LTDC_SRCR_IMR | LTDC_SRCR_VBR)) - chSchDoYieldS(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @name LTDC interrupt handlers - * @{ - */ - -/** - * @brief LTDC event interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_LTDC_EV_HANDLER) { - - LTDCDriver *const ltdcp = <DCD1; - thread_t *tp = NULL; - - OSAL_IRQ_PROLOGUE(); - - /* Handle Line Interrupt ISR.*/ - if ((LTDC->ISR & LTDC_ISR_LIF) && (LTDC->IER & LTDC_IER_LIE)) { - osalDbgAssert(ltdcp->config->line_isr != NULL, "invalid state"); - ltdcp->config->line_isr(ltdcp); - LTDC->ICR |= LTDC_ICR_CLIF; - } - - /* Handle Register Reload ISR.*/ - if ((LTDC->ISR & LTDC_ISR_RRIF) && (LTDC->IER & LTDC_IER_RRIE)) { - if (ltdcp->config->rr_isr != NULL) - ltdcp->config->rr_isr(ltdcp); - - osalSysLockFromISR(); - osalDbgAssert(ltdcp->state == LTDC_ACTIVE, "invalid state"); -#if (TRUE == LTDC_USE_WAIT) - /* Wake the waiting thread up.*/ - if (ltdcp->thread != NULL) { - tp = ltdcp->thread; - ltdcp->thread = NULL; - tp->u.rdymsg = MSG_OK; - chSchReadyI(tp); - } -#endif /* LTDC_USE_WAIT */ - ltdcp->state = LTDC_READY; - osalSysUnlockFromISR(); - - LTDC->ICR |= LTDC_ICR_CRRIF; - } - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief LTDC error interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_LTDC_ER_HANDLER) { - - static LTDCDriver *const ltdcp = <DCD1; - - OSAL_IRQ_PROLOGUE(); - - /* Handle FIFO Underrun ISR.*/ - if ((LTDC->ISR & LTDC_ISR_FUIF) && (LTDC->IER & LTDC_IER_FUIE)) { - osalDbgAssert(ltdcp->config->fuerr_isr != NULL, "invalid state"); - ltdcp->config->fuerr_isr(ltdcp); - LTDC->ICR |= LTDC_ICR_CFUIF; - } - - /* Handle Transfer Error ISR.*/ - if ((LTDC->ISR & LTDC_ISR_TERRIF) && (LTDC->IER & LTDC_IER_TERRIE)) { - osalDbgAssert(ltdcp->config->terr_isr != NULL, "invalid state"); - ltdcp->config->terr_isr(ltdcp); - LTDC->ICR |= LTDC_ICR_CTERRIF; - } - - OSAL_IRQ_EPILOGUE(); -} - -/** @} */ - -/** - * @name LTDC driver-specific methods - * @{ - */ - -/** - * @brief LTDC Driver initialization. - * @details Initializes the LTDC subsystem and chosen drivers. Should be - * called at board initialization. - * - * @init - */ -void ltdcInit(void) { - - /* Reset the LTDC hardware module.*/ - rccResetLTDC(); - - /* Enable the LTDC clock.*/ - RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | (2 << 16); /* /8 */ - rccEnableLTDC(false); - - /* Driver struct initialization.*/ - ltdcObjectInit(<DCD1); - LTDCD1.state = LTDC_STOP; -} - -/** - * @brief Initializes the standard part of a @p LTDCDriver structure. - * - * @param[out] ltdcp pointer to the @p LTDCDriver object - * - * @init - */ -void ltdcObjectInit(LTDCDriver *ltdcp) { - - osalDbgCheck(ltdcp == <DCD1); - - ltdcp->state = LTDC_UNINIT; - ltdcp->config = NULL; - ltdcp->active_window = ltdc_invalid_window; -#if (TRUE == LTDC_USE_WAIT) - ltdcp->thread = NULL; -#endif /* LTDC_USE_WAIT */ -#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION) -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxObjectInit(<dcp->lock); -#else - chSemObjectInit(<dcp->lock, 1); -#endif -#endif /* LTDC_USE_MUTUAL_EXCLUSION */ -} - -/** - * @brief Get the driver state. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @retun driver state - * - * @iclass - */ -ltdc_state_t ltdcGetStateI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - - return ltdcp->state; -} - -/** - * @brief Get the driver state. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @retun driver state - * - * @api - */ -ltdc_state_t ltdcGetState(LTDCDriver *ltdcp) { - - ltdc_state_t state; - osalSysLock(); - state = ltdcGetStateI(ltdcp); - osalSysUnlock(); - return state; -} - -/** - * @brief Configures and activates the LTDC peripheral. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] configp pointer to the @p LTDCConfig object - * - * @api - */ -void ltdcStart(LTDCDriver *ltdcp, const LTDCConfig *configp) { - - uint32_t hacc, vacc, flags; - - osalSysLock(); - - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(configp != NULL); - osalDbgAssert(ltdcp->state == LTDC_STOP, "invalid state"); - - ltdcp->config = configp; - - /* Turn off the controller and its interrupts.*/ - LTDC->GCR = 0; - LTDC->IER = 0; - ltdc_force_reload_s(ltdcp); - - /* Set synchronization params.*/ - osalDbgAssert(configp->hsync_width >= LTDC_MIN_HSYNC_WIDTH, "bounds"); - osalDbgAssert(configp->hsync_width <= LTDC_MAX_HSYNC_WIDTH, "bounds"); - osalDbgAssert(configp->vsync_height >= LTDC_MIN_VSYNC_HEIGHT, "bounds"); - osalDbgAssert(configp->vsync_height <= LTDC_MAX_VSYNC_HEIGHT, "bounds"); - - hacc = configp->hsync_width - 1; - vacc = configp->vsync_height - 1; - - LTDC->SSCR = (((hacc << 16) & LTDC_SSCR_HSW) | - ((vacc << 0) & LTDC_SSCR_VSH)); - - /* Set accumulated back porch params.*/ - osalDbgAssert(configp->hbp_width >= LTDC_MIN_HBP_WIDTH, "bounds"); - osalDbgAssert(configp->hbp_width <= LTDC_MAX_HBP_WIDTH, "bounds"); - osalDbgAssert(configp->vbp_height >= LTDC_MIN_VBP_HEIGHT, "bounds"); - osalDbgAssert(configp->vbp_height <= LTDC_MAX_VBP_HEIGHT, "bounds"); - - hacc += configp->hbp_width; - vacc += configp->vbp_height; - - osalDbgAssert(hacc + 1 >= LTDC_MIN_ACC_HBP_WIDTH, "bounds"); - osalDbgAssert(hacc + 1 <= LTDC_MAX_ACC_HBP_WIDTH, "bounds"); - osalDbgAssert(vacc + 1 >= LTDC_MIN_ACC_VBP_HEIGHT, "bounds"); - osalDbgAssert(vacc + 1 <= LTDC_MAX_ACC_VBP_HEIGHT, "bounds"); - - LTDC->BPCR = (((hacc << 16) & LTDC_BPCR_AHBP) | - ((vacc << 0) & LTDC_BPCR_AVBP)); - - ltdcp->active_window.hstart = hacc + 1; - ltdcp->active_window.vstart = vacc + 1; - - /* Set accumulated active params.*/ - osalDbgAssert(configp->screen_width >= LTDC_MIN_SCREEN_WIDTH, "bounds"); - osalDbgAssert(configp->screen_width <= LTDC_MAX_SCREEN_WIDTH, "bounds"); - osalDbgAssert(configp->screen_height >= LTDC_MIN_SCREEN_HEIGHT, "bounds"); - osalDbgAssert(configp->screen_height <= LTDC_MAX_SCREEN_HEIGHT, "bounds"); - - hacc += configp->screen_width; - vacc += configp->screen_height; - - osalDbgAssert(hacc + 1 >= LTDC_MIN_ACC_ACTIVE_WIDTH, "bounds"); - osalDbgAssert(hacc + 1 <= LTDC_MAX_ACC_ACTIVE_WIDTH, "bounds"); - osalDbgAssert(vacc + 1 >= LTDC_MIN_ACC_ACTIVE_HEIGHT, "bounds"); - osalDbgAssert(vacc + 1 <= LTDC_MAX_ACC_ACTIVE_HEIGHT, "bounds"); - - LTDC->AWCR = (((hacc << 16) & LTDC_AWCR_AAW) | - ((vacc << 0) & LTDC_AWCR_AAH)); - - ltdcp->active_window.hstop = hacc; - ltdcp->active_window.vstop = vacc; - - /* Set accumulated total params.*/ - osalDbgAssert(configp->hfp_width >= LTDC_MIN_HFP_WIDTH, "bounds"); - osalDbgAssert(configp->hfp_width <= LTDC_MAX_HFP_WIDTH, "bounds"); - osalDbgAssert(configp->vfp_height >= LTDC_MIN_VFP_HEIGHT, "bounds"); - osalDbgAssert(configp->vfp_height <= LTDC_MAX_VFP_HEIGHT, "bounds"); - - hacc += configp->hfp_width; - vacc += configp->vfp_height; - - osalDbgAssert(hacc + 1 >= LTDC_MIN_ACC_TOTAL_WIDTH, "bounds"); - osalDbgAssert(hacc + 1 <= LTDC_MAX_ACC_TOTAL_WIDTH, "bounds"); - osalDbgAssert(vacc + 1 >= LTDC_MIN_ACC_TOTAL_HEIGHT, "bounds"); - osalDbgAssert(vacc + 1 <= LTDC_MAX_ACC_TOTAL_HEIGHT, "bounds"); - - LTDC->TWCR = (((hacc << 16) & LTDC_TWCR_TOTALW) | - ((vacc << 0) & LTDC_TWCR_TOTALH)); - - /* Set signal polarities and other flags.*/ - ltdcSetEnableFlagsI(ltdcp, configp->flags & ~LTDC_EF_ENABLE); - - /* Color settings.*/ - ltdcSetClearColorI(ltdcp, configp->clear_color); - - /* Load layer configurations.*/ - ltdcBgSetConfigI(ltdcp, configp->bg_laycfg); - ltdcFgSetConfigI(ltdcp, configp->fg_laycfg); - - /* Enable only the assigned interrupt service routines.*/ - nvicEnableVector(STM32_LTDC_EV_NUMBER, STM32_LTDC_EV_IRQ_PRIORITY); - nvicEnableVector(STM32_LTDC_ER_NUMBER, STM32_LTDC_ER_IRQ_PRIORITY); - - flags = LTDC_IER_RRIE; - if (configp->line_isr != NULL) - flags |= LTDC_IER_LIE; - if (configp->fuerr_isr != NULL) - flags |= LTDC_IER_FUIE; - if (configp->terr_isr != NULL) - flags |= LTDC_IER_TERRIE; - LTDC->IER = flags; - - /* Apply settings.*/ - ltdc_force_reload_s(ltdcp); - - /* Turn on the controller.*/ - LTDC->GCR |= LTDC_GCR_LTDCEN; - ltdc_force_reload_s(ltdcp); - - ltdcp->state = LTDC_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the LTDC peripheral. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcStop(LTDCDriver *ltdcp) { - - osalDbgCheck(ltdcp == <DCD1); - - osalSysLock(); - osalDbgAssert(ltdcp->state == LTDC_READY, "invalid state"); - - /* Turn off the controller and its interrupts.*/ - LTDC->GCR &= ~LTDC_GCR_LTDCEN; - LTDC->IER = 0; -#if (TRUE == LTDC_USE_WAIT) - ltdcReloadS(ltdcp, true); -#else - ltdcStartReloadI(ltdcp, true); - while (ltdcIsReloadingI(ltdcp)) - chSchDoYieldS(); -#endif /* LTDC_USE_WAIT */ - - ltdcp->state = LTDC_STOP; - osalSysUnlock(); -} - -#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION) - -/** - * @brief Gains exclusive access to the LTDC module. - * @details This function tries to gain ownership to the LTDC module, if the - * module is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p LTDC_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @sclass - */ -void ltdcAcquireBusS(LTDCDriver *ltdcp) { - - osalDbgCheckClassS(); - osalDbgCheck(ltdcp == <DCD1); - -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxLockS(<dcp->lock); -#else - chSemWaitS(<dcp->lock); -#endif -} - -/** - * @brief Gains exclusive access to the LTDC module. - * @details This function tries to gain ownership to the LTDC module, if the - * module is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p LTDC_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcAcquireBus(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcAcquireBusS(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Releases exclusive access to the LTDC module. - * @pre In order to use this function the option - * @p LTDC_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @sclass - */ -void ltdcReleaseBusS(LTDCDriver *ltdcp) { - - osalDbgCheckClassS(); - osalDbgCheck(ltdcp == <DCD1); - -#if (TRUE == CH_CFG_USE_MUTEXES) - chMtxUnlockS(<dcp->lock); -#else - chSemSignalI(<dcp->lock); -#endif -} - -/** - * @brief Releases exclusive access to the LTDC module. - * @pre In order to use this function the option - * @p LTDC_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcReleaseBus(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcReleaseBusS(ltdcp); - osalSysUnlock(); -} - -#endif /* LTDC_USE_MUTUAL_EXCLUSION */ - -/** @} */ - -/** - * @name LTDC global methods - * @{ - */ - -/** - * @brief Get enabled flags. - * @details Returns all the flags of the <tt>LTDC_EF_*</tt> group at once. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled flags - * - * @iclass - */ -ltdc_flags_t ltdcGetEnableFlagsI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return LTDC->GCR & LTDC_EF_MASK; -} - -/** - * @brief Get enabled flags. - * @details Returns all the flags of the <tt>LTDC_EF_*</tt> group at once. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled flags - * - * @api - */ -ltdc_flags_t ltdcGetEnableFlags(LTDCDriver *ltdcp) { - - ltdc_flags_t flags; - osalSysLock(); - flags = ltdcGetEnableFlagsI(ltdcp); - osalSysUnlock(); - return flags; -} - -/** - * @brief Set enabled flags. - * @details Sets all the flags of the <tt>LTDC_EF_*</tt> group at once. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] flags enabled flags - * - * @iclass - */ -void ltdcSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->GCR = flags & LTDC_EF_MASK; -} - -/** - * @brief Set enabled flags. - * @details Sets all the flags of the <tt>LTDC_EF_*</tt> group at once. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] flags enabled flags - * - * @api - */ -void ltdcSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags) { - - osalSysLock(); - ltdcSetEnableFlagsI(ltdcp, flags); - osalSysUnlock(); -} - -/** - * @brief Reloading shadow registers. - * @details Tells whether the LTDC is reloading shadow registers. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return reloading - * - * @iclass - */ -bool ltdcIsReloadingI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC->SRCR & (LTDC_SRCR_IMR | LTDC_SRCR_VBR)) != 0; -} - -/** - * @brief Reloading shadow registers. - * @details Tells whether the LTDC is reloading shadow registers. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return reloading - * - * @api - */ -bool ltdcIsReloading(LTDCDriver *ltdcp) { - - bool reloading; - osalSysLock(); - reloading = ltdcIsReloadingI(ltdcp); - osalSysUnlock(); - return reloading; -} - -/** - * @brief Reload shadow registers. - * @details Starts reloading LTDC shadow registers, upon vsync or immediately. - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] immediately reload immediately, not upon vsync - * - * @iclass - */ -void ltdcStartReloadI(LTDCDriver *ltdcp, bool immediately) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgAssert(ltdcp->state == LTDC_READY, "not ready"); - (void)ltdcp; - - ltdcp->state = LTDC_ACTIVE; - if (immediately) - LTDC->SRCR |= LTDC_SRCR_IMR; - else - LTDC->SRCR |= LTDC_SRCR_VBR; -} - -/** - * @brief Reload shadow registers. - * @details Starts reloading LTDC shadow registers, upon vsync or immediately. - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] immediately reload immediately, not upon vsync - * - * @api - */ -void ltdcStartReload(LTDCDriver *ltdcp, bool immediately) { - - osalSysLock(); - ltdcStartReloadI(ltdcp, immediately); - osalSysUnlock(); -} - -/** - * @brief Reload shadow registers. - * @details Reloads LTDC shadow registers, upon vsync or immediately. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] immediately reload immediately, not upon vsync - * - * @sclass - */ -void ltdcReloadS(LTDCDriver *ltdcp, bool immediately) { - - osalDbgCheckClassS(); - osalDbgCheck(ltdcp == <DCD1); - - ltdcStartReloadI(ltdcp, immediately); - -#if (TRUE == LTDC_USE_WAIT) - osalDbgAssert(ltdcp->thread == NULL, "already waiting"); - - if (immediately) { - while (LTDC->SRCR & LTDC_SRCR_IMR) - chSchDoYieldS(); - ltdcp->state = LTDC_READY; - } else { - ltdcp->thread = chThdGetSelfX(); - chSchGoSleepS(CH_STATE_SUSPENDED); - } -#else - while (LTDC->SRCR & LTDC_SRCR_IMR) - chSchDoYieldS(); - ltdcp->state = LTDC_READY; -#endif -} - -/** - * @brief Reload shadow registers. - * @details Reloads LTDC shadow registers, upon vsync or immediately. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] immediately reload immediately, not upon vsync - * - * @api - */ -void ltdcReload(LTDCDriver *ltdcp, bool immediately) { - - osalSysLock(); - ltdcReloadS(ltdcp, immediately); - osalSysUnlock(); -} - -/** - * @brief Dithering enabled. - * @details Tells whether the dithering is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcIsDitheringEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC->GCR & LTDC_GCR_DTEN) != 0; -} - -/** - * @brief Dithering enabled. - * @details Tells whether the dithering is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcIsDitheringEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcIsDitheringEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Enable dithering. - * @details Enables dithering capabilities for pixel formats with less than - * 8 bits per channel. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcEnableDitheringI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->GCR |= LTDC_GCR_DTEN; -} - -/** - * @brief Enable dithering. - * @details Enables dithering capabilities for pixel formats with less than - * 8 bits per channel. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcEnableDithering(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcEnableDitheringI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Disable dithering. - * @details Disables dithering capabilities for pixel formats with less than - * 8 bits per channel. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcDisableDitheringI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->GCR &= ~LTDC_GCR_DTEN; -} - -/** - * @brief Disable dithering. - * @details Disables dithering capabilities for pixel formats with less than - * 8 bits per channel. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcDisableDithering(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcDisableDitheringI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Get clear screen color. - * @details Gets the clear screen (actual background) color. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return clear screen color, RGB-888 - * - * @iclass - */ -ltdc_color_t ltdcGetClearColorI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_color_t)(LTDC->BCCR & 0x00FFFFFF); -} - -/** - * @brief Get clear screen color. - * @details Gets the clear screen (actual background) color. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return clear screen color, RGB-888 - * - * @api - */ -ltdc_color_t ltdcGetClearColor(LTDCDriver *ltdcp) { - - ltdc_color_t color; - osalSysLock(); - color = ltdcGetClearColorI(ltdcp); - osalSysUnlock(); - return color; -} - -/** - * @brief Set clear screen color. - * @details Sets the clear screen (actual background) color. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c clear screen color, RGB-888 - * - * @iclass - */ -void ltdcSetClearColorI(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->BCCR = (LTDC->BCCR & ~0x00FFFFFF) | (c & 0x00FFFFFF); -} - -/** - * @brief Set clear screen color. - * @details Sets the clear screen (actual background) color. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c clear screen color, RGB-888 - * - * @api - */ -void ltdcSetClearColor(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalSysLock(); - ltdcSetClearColorI(ltdcp, c); - osalSysUnlock(); -} - -/** - * @brief Get line interrupt position. - * @details Gets the line interrupt position. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return line interrupt position - * - * @iclass - */ -uint16_t ltdcGetLineInterruptPosI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (uint16_t)(LTDC->LIPCR & LTDC_LIPCR_LIPOS); -} - -/** - * @brief Get line interrupt position. - * @details Gets the line interrupt position. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return line interrupt position - * - * @api - */ -uint16_t ltdcGetLineInterruptPos(LTDCDriver *ltdcp) { - - uint16_t line; - osalSysLock(); - line = ltdcGetLineInterruptPosI(ltdcp); - osalSysUnlock(); - return line; -} - -/** - * @brief Set line interrupt position. - * @details Sets the line interrupt position. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcSetLineInterruptPosI(LTDCDriver *ltdcp, uint16_t line) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->LIPCR = ((LTDC->LIPCR & ~LTDC_LIPCR_LIPOS) | - ((uint32_t)line & LTDC_LIPCR_LIPOS)); -} - -/** - * @brief Set line interrupt position. - * @details Sets the line interrupt position. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcSetLineInterruptPos(LTDCDriver *ltdcp, uint16_t line) { - - osalSysLock(); - ltdcSetLineInterruptPosI(ltdcp, line); - osalSysUnlock(); -} - -/** - * @brief Line interrupt enabled. - * @details Tells whether the line interrupt is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcIsLineInterruptEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC->IER & LTDC_IER_LIE) != 0; -} - -/** - * @brief Line interrupt enabled. - * @details Tells whether the line interrupt is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcIsLineInterruptEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcIsLineInterruptEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Enable line interrupt. - * @details Enables line interrupt. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcEnableLineInterruptI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->IER |= LTDC_IER_LIE; -} - -/** - * @brief Enable line interrupt. - * @details Enables line interrupt. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcEnableLineInterrupt(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcEnableLineInterruptI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Disable line interrupt. - * @details Disables line interrupt. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcDisableLineInterruptI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC->IER &= ~LTDC_IER_LIE; -} - -/** - * @brief Disable line interrupt. - * @details Disables line interrupt. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcDisableLineInterrupt(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcDisableLineInterruptI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Get current position. - * @details Gets the current position. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] xp pointer to the destination horizontal coordinate - * @param[out] yp pointer to the destination vertical coordinate - * - * @iclass - */ -void ltdcGetCurrentPosI(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp) { - - const uint32_t r = LTDC->CPSR; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - *xp = (uint16_t)((r & LTDC_CPSR_CXPOS) >> 16); - *yp = (uint16_t)((r & LTDC_CPSR_CYPOS) >> 0); -} - -/** - * @brief Get current position. - * @details Gets the current position. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] xp pointer to the destination horizontal coordinate - * @param[out] yp pointer to the destination vertical coordinate - * - * @api - */ -void ltdcGetCurrentPos(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp) { - - osalSysLock(); - ltdcGetCurrentPosI(ltdcp, xp, yp); - osalSysUnlock(); -} - -/** @} */ - -/** - * @name LTDC background layer (layer 1) methods - * @{ - */ - -/** - * @brief Get background layer enabled flags. - * @details Returns all the flags of the <tt>LTDC_LEF_*</tt> group at once. - * Targeting the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled flags - * - * @iclass - */ -ltdc_flags_t ltdcBgGetEnableFlagsI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return LTDC_Layer1->CR & LTDC_LEF_MASK; -} - -/** - * @brief Get background layer enabled flags. - * @details Returns all the flags of the <tt>LTDC_LEF_*</tt> group at once. - * Targeting the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled flags - * - * @api - */ -ltdc_flags_t ltdcBgGetEnableFlags(LTDCDriver *ltdcp) { - - ltdc_flags_t flags; - osalSysLock(); - flags = ltdcBgGetEnableFlagsI(ltdcp); - osalSysUnlock(); - return flags; -} - -/** - * @brief Set background layer enabled flags. - * @details Sets all the flags of the <tt>LTDC_LEF_*</tt> group at once. - * Targeting the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] flags enabled flags - * - * @iclass - */ -void ltdcBgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR = ((LTDC_Layer1->CR & ~LTDC_LEF_MASK) | - ((uint32_t)flags & LTDC_LEF_MASK)); -} - -/** - * @brief Set background layer enabled flags. - * @details Sets all the flags of the <tt>LTDC_LEF_*</tt> group at once. - * Targeting the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] flags enabled flags - * - * @api - */ -void ltdcBgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags) { - - osalSysLock(); - ltdcBgSetEnableFlagsI(ltdcp, flags); - osalSysUnlock(); -} - -/** - * @brief Background layer enabled. - * @details Tells whether the background layer (layer 1) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcBgIsEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC_Layer1->CR & ~LTDC_LxCR_LEN) != 0; -} - -/** - * @brief Background layer enabled. - * @details Tells whether the background layer (layer 1) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcBgIsEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcBgIsEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Background layer enable. - * @details Enables the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgEnableI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR |= LTDC_LxCR_LEN; -} - -/** - * @brief Background layer enable. - * @details Enables the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgEnable(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgEnableI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Background layer disable. - * @details Disables the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgDisableI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR &= ~LTDC_LxCR_LEN; -} - -/** - * @brief Background layer disable. - * @details Disables the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgDisable(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgDisableI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Background layer palette enabled. - * @details Tells whether the background layer (layer 1) palette (color lookup - * table) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcBgIsPaletteEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC_Layer1->CR & ~LTDC_LxCR_CLUTEN) != 0; -} - -/** - * @brief Background layer palette enabled. - * @details Tells whether the background layer (layer 1) palette (color lookup - * table) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcBgIsPaletteEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcBgIsPaletteEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Enable background layer palette. - * @details Enables the palette (color lookup table) of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgEnablePaletteI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR |= LTDC_LxCR_CLUTEN; -} - -/** - * @brief Enable background layer palette. - * @details Enables the palette (color lookup table) of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgEnablePalette(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgEnablePaletteI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Disable background layer palette. - * @details Disables the palette (color lookup table) of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgDisablePaletteI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR &= ~LTDC_LxCR_CLUTEN; -} - -/** - * @brief Disable background layer palette. - * @details Disables the palette (color lookup table) of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgDisablePalette(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgDisablePaletteI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Set background layer palette color. - * @details Sets the color of a palette (color lookup table) slot to the - * background layer (layer 1). - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] slot palette slot - * @param[in] c color, RGB-888 - * - * @iclass - */ -void ltdcBgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgAssert(!ltdcBgIsEnabledI(ltdcp), "invalid state"); - (void)ltdcp; - - LTDC_Layer1->CLUTWR = (((uint32_t)slot << 24) | (c & 0x00FFFFFF)); -} - -/** - * @brief Set background layer palette color. - * @details Sets the color of a palette (color lookup table) slot to the - * background layer (layer 1). - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] slot palette slot - * @param[in] c color, RGB-888 - * - * @api - */ -void ltdcBgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c) { - - osalSysLock(); - ltdcBgSetPaletteColorI(ltdcp, slot, c); - osalSysUnlock(); -} - -/** - * @brief Set background layer palette. - * @details Sets the entire palette color (color lookup table) slot. - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] colors array of palette colors, RGB-888 - * @param[in] length number of palette colors - * - * @iclass - */ -void ltdcBgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length) { - - uint16_t i; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck((colors == NULL) == (length == 0)); - osalDbgAssert(length <= LTDC_MAX_PALETTE_LENGTH, "bounds"); - osalDbgAssert(!ltdcBgIsEnabledI(ltdcp), "invalid state"); - (void)ltdcp; - - for (i = 0; i < length; ++i) - LTDC_Layer1->CLUTWR = (((uint32_t)i << 24) | (colors[i] & 0x00FFFFFF)); -} - -/** - * @brief Set background layer palette. - * @details Sets the entire palette color (color lookup table) slot. - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] colors array of palette colors, RGB-888 - * @param[in] length number of palette colors - * - * @api - */ -void ltdcBgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length) { - - osalSysLock(); - ltdcBgSetPaletteI(ltdcp, colors, length); - osalSysUnlock(); -} - -/** - * @brief Get background layer pixel format. - * @details Gets the pixel format of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return pixel format - * - * @iclass - */ -ltdc_pixfmt_t ltdcBgGetPixelFormatI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_pixfmt_t)(LTDC_Layer1->PFCR & LTDC_LxPFCR_PF); -} - -/** - * @brief Get background layer pixel format. - * @details Gets the pixel format of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return pixel format - * - * @api - */ -ltdc_pixfmt_t ltdcBgGetPixelFormat(LTDCDriver *ltdcp) { - - ltdc_pixfmt_t fmt; - osalSysLock(); - fmt = ltdcBgGetPixelFormatI(ltdcp); - osalSysUnlock(); - return fmt; -} - -/** - * @brief Set background layer pixel format. - * @details Sets the pixel format of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] fmt pixel format - * - * @iclass - */ -void ltdcBgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgAssert(fmt >= LTDC_MIN_PIXFMT_ID, "bounds"); - osalDbgAssert(fmt <= LTDC_MAX_PIXFMT_ID, "bounds"); - (void)ltdcp; - - LTDC_Layer1->PFCR = ((LTDC_Layer1->PFCR & ~LTDC_LxPFCR_PF) | - ((uint32_t)fmt & LTDC_LxPFCR_PF)); -} - -/** - * @brief Set background layer pixel format. - * @details Sets the pixel format of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] fmt pixel format - * - * @api - */ -void ltdcBgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt) { - - osalSysLock(); - ltdcBgSetPixelFormatI(ltdcp, fmt); - osalSysUnlock(); -} - -/** - * @brief Background layer color keying enabled. - * @details Tells whether the background layer (layer 1) has color keying - * enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcBgIsKeyingEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC_Layer1->CR & ~LTDC_LxCR_COLKEN) != 0; -} - -/** - * @brief Background layer color keying enabled. - * @details Tells whether the background layer (layer 1) has color keying - * enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcBgIsKeyingEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcBgIsKeyingEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Enable background layer color keying. - * @details Enables color keying capabilities of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgEnableKeyingI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR |= LTDC_LxCR_COLKEN; -} - -/** - * @brief Enable background layer color keying. - * @details Enables color keying capabilities of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgEnableKeying(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgEnableKeyingI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Disable background layer color keying. - * @details Disables color keying capabilities of the background layer (layer - * 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgDisableKeyingI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CR &= ~LTDC_LxCR_COLKEN; -} - -/** - * @brief Disable background layer color keying. - * @details Disables color keying capabilities of the background layer (layer - * 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgDisableKeying(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgDisableKeyingI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Get background layer color key. - * @details Gets the color key of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return color key, RGB-888 - * - * @iclass - */ -ltdc_color_t ltdcBgGetKeyingColorI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_color_t)(LTDC_Layer1->CKCR & 0x00FFFFFF); -} - -/** - * @brief Get background layer color key. - * @details Gets the color key of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return color key, RGB-888 - * - * @api - */ -ltdc_color_t ltdcBgGetKeyingColor(LTDCDriver *ltdcp) { - - ltdc_color_t color; - osalSysLock(); - color = ltdcBgGetKeyingColorI(ltdcp); - osalSysUnlock(); - return color; -} - -/** - * @brief Set background layer color key. - * @details Sets the color key of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c color key, RGB-888 - * - * @iclass - */ -void ltdcBgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CKCR = ((LTDC_Layer1->CKCR & ~0x00FFFFFF) | - ((uint32_t)c & 0x00FFFFFF)); -} - -/** - * @brief Set background layer color key. - * @details Sets the color key of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c color key, RGB-888 - * - * @api - */ -void ltdcBgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalSysLock(); - ltdcBgSetKeyingColorI(ltdcp, c); - osalSysUnlock(); -} - -/** - * @brief Get background layer constant alpha. - * @details Gets the constant alpha component of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return constant alpha component, A-8 - * - * @iclass - */ -uint8_t ltdcBgGetConstantAlphaI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (uint8_t)(LTDC_Layer1->CACR & LTDC_LxCACR_CONSTA); -} - -/** - * @brief Get background layer constant alpha. - * @details Gets the constant alpha component of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return constant alpha component, A-8 - * - * @api - */ -uint8_t ltdcBgGetConstantAlpha(LTDCDriver *ltdcp) { - - uint8_t a; - osalSysLock(); - a = ltdcBgGetConstantAlphaI(ltdcp); - osalSysUnlock(); - return a; -} - -/** - * @brief Set background layer constant alpha. - * @details Sets the constant alpha component of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] a constant alpha component, A-8 - * - * @iclass - */ -void ltdcBgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CACR = ((LTDC_Layer1->CACR & ~LTDC_LxCACR_CONSTA) | - ((uint32_t)a & LTDC_LxCACR_CONSTA)); -} - -/** - * @brief Set background layer constant alpha. - * @details Sets the constant alpha component of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] a constant alpha component, A-8 - * - * @api - */ -void ltdcBgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a) { - - osalSysLock(); - ltdcBgSetConstantAlphaI(ltdcp, a); - osalSysUnlock(); -} - -/** - * @brief Get background layer default color. - * @details Gets the default color of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return default color, RGB-888 - * - * @iclass - */ -ltdc_color_t ltdcBgGetDefaultColorI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_color_t)LTDC_Layer1->DCCR; -} - -/** - * @brief Get background layer default color. - * @details Gets the default color of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return default color, RGB-888 - * - * @api - */ -ltdc_color_t ltdcBgGetDefaultColor(LTDCDriver *ltdcp) { - - ltdc_color_t color; - osalSysLock(); - color = ltdcBgGetDefaultColorI(ltdcp); - osalSysUnlock(); - return color; -} - -/** - * @brief Set background layer default color. - * @details Sets the default color of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c default color, RGB-888 - * - * @iclass - */ -void ltdcBgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->DCCR = (uint32_t)c; -} - -/** - * @brief Set background layer default color. - * @details Sets the default color of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c default color, RGB-888 - * - * @api - */ -void ltdcBgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalSysLock(); - ltdcBgSetDefaultColorI(ltdcp, c); - osalSysUnlock(); -} - -/** - * @brief Get background layer blending factors. - * @details Gets the blending factors of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return blending factors - * - * @iclass - */ -ltdc_blendf_t ltdcBgGetBlendingFactorsI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_blendf_t)(LTDC_Layer1->BFCR & LTDC_LxBFCR_BF); -} - -/** - * @brief Get background layer blending factors. - * @details Gets the blending factors of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return blending factors - * - * @api - */ -ltdc_blendf_t ltdcBgGetBlendingFactors(LTDCDriver *ltdcp) { - - ltdc_blendf_t bf; - osalSysLock(); - bf = ltdcBgGetBlendingFactorsI(ltdcp); - osalSysUnlock(); - return bf; -} - -/** - * @brief Set background layer blending factors. - * @details Sets the blending factors of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] factors blending factors - * - * @iclass - */ -void ltdcBgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->BFCR = ((LTDC_Layer1->BFCR & ~LTDC_LxBFCR_BF) | - ((uint32_t)bf & LTDC_LxBFCR_BF)); -} - -/** - * @brief Set background layer blending factors. - * @details Sets the blending factors of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] factors blending factors - * - * @api - */ -void ltdcBgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf) { - - osalSysLock(); - ltdcBgSetBlendingFactorsI(ltdcp, bf); - osalSysUnlock(); -} - -/** - * @brief Get background layer window specs. - * @details Gets the window specifications of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] windowp pointer to the window specifications - * - * @iclass - */ -void ltdcBgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(windowp != NULL); - (void)ltdcp; - - windowp->hstart = - (uint16_t)((LTDC_Layer1->WHPCR & LTDC_LxWHPCR_WHSTPOS) >> 0); - windowp->hstop = - (uint16_t)((LTDC_Layer1->WHPCR & LTDC_LxWHPCR_WHSPPOS) >> 16); - windowp->vstart = - (uint16_t)((LTDC_Layer1->WVPCR & LTDC_LxWVPCR_WVSTPOS) >> 0); - windowp->vstop = - (uint16_t)((LTDC_Layer1->WVPCR & LTDC_LxWVPCR_WVSPPOS) >> 16); -} - -/** - * @brief Get background layer window specs. - * @details Gets the window specifications of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] windowp pointer to the window specifications - * - * @api - */ -void ltdcBgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp) { - - osalSysLock(); - ltdcBgGetWindowI(ltdcp, windowp); - osalSysUnlock(); -} - -/** - * @brief Set background layer window specs. - * @details Sets the window specifications of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] windowp pointer to the window specifications - * - * @iclass - */ -void ltdcBgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp) { - - uint32_t start, stop; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(windowp != NULL); - (void)ltdcp; - - osalDbgAssert(windowp->hstop < ltdcp->config->screen_width, "bounds"); - osalDbgAssert(windowp->vstop < ltdcp->config->screen_height, "bounds"); - - /* Horizontal boundaries.*/ - start = (uint32_t)windowp->hstart + ltdcp->active_window.hstart; - stop = (uint32_t)windowp->hstop + ltdcp->active_window.hstart; - - osalDbgAssert(start >= ltdcp->active_window.hstart, "bounds"); - osalDbgAssert(stop <= ltdcp->active_window.hstop, "bounds"); - - LTDC_Layer1->WHPCR = (((start << 0) & LTDC_LxWHPCR_WHSTPOS) | - ((stop << 16) & LTDC_LxWHPCR_WHSPPOS)); - - /* Vertical boundaries.*/ - start = (uint32_t)windowp->vstart + ltdcp->active_window.vstart; - stop = (uint32_t)windowp->vstop + ltdcp->active_window.vstart; - - osalDbgAssert(start >= ltdcp->active_window.vstart, "bounds"); - osalDbgAssert(stop <= ltdcp->active_window.vstop, "bounds"); - - LTDC_Layer1->WVPCR = (((start << 0) & LTDC_LxWVPCR_WVSTPOS) | - ((stop << 16) & LTDC_LxWVPCR_WVSPPOS)); -} - -/** - * @brief Set background layer window specs. - * @details Sets the window specifications of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] windowp pointer to the window specifications - * - * @api - */ -void ltdcBgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp) { - - osalSysLock(); - ltdcBgSetWindowI(ltdcp, windowp); - osalSysUnlock(); -} - -/** - * @brief Set background layer window as invalid. - * @details Sets the window specifications of the background layer (layer 1) - * so that the window is pixel sized at the screen origin. - * @note Useful before reconfiguring the frame specifications of the layer, - * to avoid errors. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcBgSetInvalidWindowI(LTDCDriver *ltdcp) { - - ltdcBgSetWindowI(ltdcp, <dc_invalid_window); -} - -/** - * @brief Set background layer window as invalid. - * @details Sets the window specifications of the background layer (layer 1) - * so that the window is pixel sized at the screen origin. - * @note Useful before reconfiguring the frame specifications of the layer, - * to avoid errors. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcBgSetInvalidWindow(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcBgSetWindowI(ltdcp, <dc_invalid_window); - osalSysUnlock(); -} - -/** - * @brief Get background layer frame buffer specs. - * @details Gets the frame buffer specifications of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] framep pointer to the frame buffer specifications - * - * @iclass - */ -void ltdcBgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(framep != NULL); - - framep->bufferp = (void *)(LTDC_Layer1->CFBAR & LTDC_LxCFBAR_CFBADD); - framep->pitch = (size_t)((LTDC_Layer1->CFBLR & LTDC_LxCFBLR_CFBP) >> 16); - framep->width = (uint16_t)(((LTDC_Layer1->CFBLR & LTDC_LxCFBLR_CFBLL) - 3) / - ltdcBytesPerPixel(ltdcBgGetPixelFormatI(ltdcp))); - framep->height = (uint16_t)(LTDC_Layer1->CFBLNR & LTDC_LxCFBLNR_CFBLNBR); -} - -/** - * @brief Get background layer frame buffer specs. - * @details Gets the frame buffer specifications of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] framep pointer to the frame buffer specifications - * - * @api - */ -void ltdcBgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep) { - - osalSysLock(); - ltdcBgGetFrameI(ltdcp, framep); - osalSysUnlock(); -} - -/** - * @brief Set background layer frame buffer specs. - * @details Sets the frame buffer specifications of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] framep pointer to the frame buffer specifications - * - * @iclass - */ -void ltdcBgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep) { - - size_t linesize; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(framep != NULL); - - ltdcBgSetPixelFormatI(ltdcp, framep->fmt); - - linesize = ltdcBytesPerPixel(framep->fmt) * framep->width; - - osalDbgAssert(framep->width <= ltdcp->config->screen_width, "bounds"); - osalDbgAssert(framep->height <= ltdcp->config->screen_height, "bounds"); - osalDbgAssert(linesize >= LTDC_MIN_FRAME_WIDTH_BYTES, "bounds"); - osalDbgAssert(linesize <= LTDC_MAX_FRAME_WIDTH_BYTES, "bounds"); - osalDbgAssert(framep->height >= LTDC_MIN_FRAME_HEIGHT_LINES, "bounds"); - osalDbgAssert(framep->height <= LTDC_MAX_FRAME_HEIGHT_LINES, "bounds"); - osalDbgAssert(framep->pitch >= linesize, "bounds"); - - LTDC_Layer1->CFBAR = (uint32_t)framep->bufferp & LTDC_LxCFBAR_CFBADD; - LTDC_Layer1->CFBLR = ((((uint32_t)framep->pitch << 16) & LTDC_LxCFBLR_CFBP) | - ((linesize + 3) & LTDC_LxCFBLR_CFBLL)); - LTDC_Layer1->CFBLNR = (uint32_t)framep->height & LTDC_LxCFBLNR_CFBLNBR; -} - -/** - * @brief Set background layer frame buffer specs. - * @details Sets the frame buffer specifications of the background layer - * (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] framep pointer to the frame buffer specifications - * - * @api - */ -void ltdcBgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep) { - - osalSysLock(); - ltdcBgSetFrameI(ltdcp, framep); - osalSysUnlock(); -} - -/** - * @brief Get background layer frame buffer address. - * @details Gets the frame buffer address of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return frame buffer address - * - * @iclass - */ -void *ltdcBgGetFrameAddressI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (void *)LTDC_Layer1->CFBAR; -} - -/** - * @brief Get background layer frame buffer address. - * @details Gets the frame buffer address of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return frame buffer address - * - * @api - */ -void *ltdcBgGetFrameAddress(LTDCDriver *ltdcp) { - - void *bufferp; - osalSysLock(); - bufferp = ltdcBgGetFrameAddressI(ltdcp); - osalSysUnlock(); - return bufferp; -} - -/** - * @brief Set background layer frame buffer address. - * @details Sets the frame buffer address of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] bufferp frame buffer address - * - * @iclass - */ -void ltdcBgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer1->CFBAR = (uint32_t)bufferp; -} - -/** - * @brief Set background layer frame buffer address. - * @details Sets the frame buffer address of the background layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] bufferp frame buffer address - * - * @api - */ -void ltdcBgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp) { - - osalSysLock(); - ltdcBgSetFrameAddressI(ltdcp, bufferp); - osalSysUnlock(); -} - -/** - * @brief Get background layer specifications. - * @details Gets the background layer (layer 1) specifications at once. - * @note If palette specifications cannot be retrieved, they are set to - * @p NULL. This is not an error. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @iclass - */ -void ltdcBgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(cfgp != NULL); - - ltdcBgGetFrameI(ltdcp, (ltdc_frame_t *)cfgp->frame); - ltdcBgGetWindowI(ltdcp, (ltdc_window_t *)cfgp->window); - cfgp->def_color = ltdcBgGetDefaultColorI(ltdcp); - cfgp->key_color = ltdcBgGetKeyingColorI(ltdcp); - cfgp->const_alpha = ltdcBgGetConstantAlphaI(ltdcp); - cfgp->blending = ltdcBgGetBlendingFactorsI(ltdcp); - - cfgp->pal_colors = NULL; - cfgp->pal_length = 0; - - cfgp->flags = ltdcBgGetEnableFlagsI(ltdcp); -} - -/** - * @brief Get background layer specifications. - * @details Gets the background layer (layer 1) specifications at once. - * @note If palette specifications cannot be retrieved, they are set to - * @p NULL. This is not an error. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @api - */ -void ltdcBgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp) { - - osalSysLock(); - ltdcBgGetLayerI(ltdcp, cfgp); - osalSysUnlock(); -} - -/** - * @brief Set background layer specifications. - * @details Sets the background layer (layer 1) specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @iclass - */ -void ltdcBgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - - if (cfgp == NULL) - cfgp = <dc_default_laycfg; - - osalDbgCheck((cfgp->pal_colors == NULL) == (cfgp->pal_length == 0)); - - ltdcBgSetFrameI(ltdcp, cfgp->frame); - ltdcBgSetWindowI(ltdcp, cfgp->window); - ltdcBgSetDefaultColorI(ltdcp, cfgp->def_color); - ltdcBgSetKeyingColorI(ltdcp, cfgp->key_color); - ltdcBgSetConstantAlphaI(ltdcp, cfgp->const_alpha); - ltdcBgSetBlendingFactorsI(ltdcp, cfgp->blending); - - if (cfgp->pal_length > 0) - ltdcBgSetPaletteI(ltdcp, cfgp->pal_colors, cfgp->pal_length); - - ltdcBgSetEnableFlagsI(ltdcp, cfgp->flags); -} - -/** - * @brief Set background layer specifications. - * @details Sets the background layer (layer 1) specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @api - */ -void ltdcBgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp) { - - osalSysLock(); - ltdcBgSetConfigI(ltdcp, cfgp); - osalSysUnlock(); -} - -/** @} */ - -/** - * @name LTDC foreground layer (layer 2) methods - * @{ - */ - -/** - * @brief Get foreground layer enabled flags. - * @details Returns all the flags of the <tt>LTDC_LEF_*</tt> group at once. - * Targeting the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled flags - * - * @iclass - */ -ltdc_flags_t ltdcFgGetEnableFlagsI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return LTDC_Layer2->CR & LTDC_LEF_MASK; -} - -/** - * @brief Get foreground layer enabled flags. - * @details Returns all the flags of the <tt>LTDC_LEF_*</tt> group at once. - * Targeting the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled flags - * - * @api - */ -ltdc_flags_t ltdcFgGetEnableFlags(LTDCDriver *ltdcp) { - - ltdc_flags_t flags; - osalSysLock(); - flags = ltdcFgGetEnableFlagsI(ltdcp); - osalSysUnlock(); - return flags; -} - -/** - * @brief Set foreground layer enabled flags. - * @details Sets all the flags of the <tt>LTDC_LEF_*</tt> group at once. - * Targeting the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] flags enabled flags - * - * @iclass - */ -void ltdcFgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR = ((LTDC_Layer2->CR & ~LTDC_LEF_MASK) | - ((uint32_t)flags & LTDC_LEF_MASK)); -} - -/** - * @brief Set foreground layer enabled flags. - * @details Sets all the flags of the <tt>LTDC_LEF_*</tt> group at once. - * Targeting the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] flags enabled flags - * - * @api - */ -void ltdcFgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags) { - - osalSysLock(); - ltdcFgSetEnableFlagsI(ltdcp, flags); - osalSysUnlock(); -} - -/** - * @brief Foreground layer enabled. - * @details Tells whether the foreground layer (layer 2) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcFgIsEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC_Layer2->CR & ~LTDC_LxCR_LEN) != 0; -} - -/** - * @brief Foreground layer enabled. - * @details Tells whether the foreground layer (layer 2) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcFgIsEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcFgIsEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Foreground layer enable. - * @details Enables the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgEnableI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR |= LTDC_LxCR_LEN; -} - -/** - * @brief Foreground layer enable. - * @details Enables the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgEnable(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgEnableI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Foreground layer disable. - * @details Disables the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgDisableI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR &= ~LTDC_LxCR_LEN; -} - -/** - * @brief Foreground layer disable. - * @details Disables the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgDisable(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgDisableI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Foreground layer palette enabled. - * @details Tells whether the foreground layer (layer 2) palette (color lookup - * table) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcFgIsPaletteEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC_Layer2->CR & ~LTDC_LxCR_CLUTEN) != 0; -} - -/** - * @brief Foreground layer palette enabled. - * @details Tells whether the foreground layer (layer 2) palette (color lookup - * table) is enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcFgIsPaletteEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcFgIsPaletteEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Enable foreground layer palette. - * @details Enables the palette (color lookup table) of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgEnablePaletteI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR |= LTDC_LxCR_CLUTEN; -} - -/** - * @brief Enable foreground layer palette. - * @details Enables the palette (color lookup table) of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgEnablePalette(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgEnablePaletteI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Disable foreground layer palette. - * @details Disables the palette (color lookup table) of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgDisablePaletteI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR &= ~LTDC_LxCR_CLUTEN; -} - -/** - * @brief Disable foreground layer palette. - * @details Disables the palette (color lookup table) of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgDisablePalette(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgDisablePaletteI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Set foreground layer palette color. - * @details Sets the color of a palette (color lookup table) slot to the - * foreground layer (layer 2). - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] slot palette slot - * @param[in] c color, RGB-888 - * - * @iclass - */ -void ltdcFgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgAssert(!ltdcFgIsEnabledI(ltdcp), "invalid state"); - (void)ltdcp; - - LTDC_Layer2->CLUTWR = (((uint32_t)slot << 24) | (c & 0x00FFFFFF)); -} - -/** - * @brief Set foreground layer palette color. - * @details Sets the color of a palette (color lookup table) slot to the - * foreground layer (layer 2). - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] slot palette slot - * @param[in] c color, RGB-888 - * - * @api - */ -void ltdcFgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c) { - - osalSysLock(); - ltdcFgSetPaletteColorI(ltdcp, slot, c); - osalSysUnlock(); -} - -/** - * @brief Set foreground layer palette. - * @details Sets the entire palette color (color lookup table) slot. - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] colors array of palette colors, RGB-888 - * @param[in] length number of palette colors - * - * @iclass - */ -void ltdcFgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length) { - - uint16_t i; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck((colors == NULL) == (length == 0)); - osalDbgAssert(length <= LTDC_MAX_PALETTE_LENGTH, "bounds"); - osalDbgAssert(!ltdcFgIsEnabledI(ltdcp), "invalid state"); - (void)ltdcp; - - for (i = 0; i < length; ++i) - LTDC_Layer2->CLUTWR = (((uint32_t)i << 24) | (colors[i] & 0x00FFFFFF)); -} - -/** - * @brief Set foreground layer palette. - * @details Sets the entire palette color (color lookup table) slot. - * @pre The layer must be disabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] colors array of palette colors, RGB-888 - * @param[in] length number of palette colors - * - * @api - */ -void ltdcFgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length) { - - osalSysLock(); - ltdcFgSetPaletteI(ltdcp, colors, length); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer pixel format. - * @details Gets the pixel format of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return pixel format - * - * @iclass - */ -ltdc_pixfmt_t ltdcFgGetPixelFormatI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_pixfmt_t)(LTDC_Layer2->PFCR & LTDC_LxPFCR_PF); -} - -/** - * @brief Get foreground layer pixel format. - * @details Gets the pixel format of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return pixel format - * - * @api - */ -ltdc_pixfmt_t ltdcFgGetPixelFormat(LTDCDriver *ltdcp) { - - ltdc_pixfmt_t fmt; - osalSysLock(); - fmt = ltdcFgGetPixelFormatI(ltdcp); - osalSysUnlock(); - return fmt; -} - -/** - * @brief Set foreground layer pixel format. - * @details Sets the pixel format of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] fmt pixel format - * - * @iclass - */ -void ltdcFgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgAssert(fmt >= LTDC_MIN_PIXFMT_ID, "bounds"); - osalDbgAssert(fmt <= LTDC_MAX_PIXFMT_ID, "bounds"); - (void)ltdcp; - - LTDC_Layer2->PFCR = ((LTDC_Layer2->PFCR & ~LTDC_LxPFCR_PF) | - ((uint32_t)fmt & LTDC_LxPFCR_PF)); -} - -/** - * @brief Set foreground layer pixel format. - * @details Sets the pixel format of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] fmt pixel format - * - * @api - */ -void ltdcFgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt) { - - osalSysLock(); - ltdcFgSetPixelFormatI(ltdcp, fmt); - osalSysUnlock(); -} - -/** - * @brief Foreground layer color keying enabled. - * @details Tells whether the foreground layer (layer 2) has color keying - * enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @iclass - */ -bool ltdcFgIsKeyingEnabledI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (LTDC_Layer2->CR & ~LTDC_LxCR_COLKEN) != 0; -} - -/** - * @brief Foreground layer color keying enabled. - * @details Tells whether the foreground layer (layer 2) has color keying - * enabled. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return enabled - * - * @api - */ -bool ltdcFgIsKeyingEnabled(LTDCDriver *ltdcp) { - - bool enabled; - osalSysLock(); - enabled = ltdcFgIsKeyingEnabledI(ltdcp); - osalSysUnlock(); - return enabled; -} - -/** - * @brief Enable foreground layer color keying. - * @details Enables color keying capabilities of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgEnableKeyingI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR |= LTDC_LxCR_COLKEN; -} - -/** - * @brief Enable foreground layer color keying. - * @details Enables color keying capabilities of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgEnableKeying(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgEnableKeyingI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Disable foreground layer color keying. - * @details Disables color keying capabilities of the foreground layer (layer - * 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgDisableKeyingI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CR &= ~LTDC_LxCR_COLKEN; -} - -/** - * @brief Disable foreground layer color keying. - * @details Disables color keying capabilities of the foreground layer (layer - * 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgDisableKeying(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgDisableKeyingI(ltdcp); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer color key. - * @details Gets the color key of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return color key, RGB-888 - * - * @iclass - */ -ltdc_color_t ltdcFgGetKeyingColorI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_color_t)(LTDC_Layer2->CKCR & 0x00FFFFFF); -} - -/** - * @brief Get foreground layer color key. - * @details Gets the color key of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return color key, RGB-888 - * - * @api - */ -ltdc_color_t ltdcFgGetKeyingColor(LTDCDriver *ltdcp) { - - ltdc_color_t color; - osalSysLock(); - color = ltdcFgGetKeyingColorI(ltdcp); - osalSysUnlock(); - return color; -} - -/** - * @brief Set foreground layer color key. - * @details Sets the color key of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c color key, RGB-888 - * - * @iclass - */ -void ltdcFgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CKCR = ((LTDC_Layer2->CKCR & ~0x00FFFFFF) | - ((uint32_t)c & 0x00FFFFFF)); -} - -/** - * @brief Set foreground layer color key. - * @details Sets the color key of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c color key, RGB-888 - * - * @api - */ -void ltdcFgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalSysLock(); - ltdcFgSetKeyingColorI(ltdcp, c); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer constant alpha. - * @details Gets the constant alpha component of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return constant alpha component, A-8 - * - * @iclass - */ -uint8_t ltdcFgGetConstantAlphaI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (uint8_t)(LTDC_Layer2->CACR & LTDC_LxCACR_CONSTA); -} - -/** - * @brief Get foreground layer constant alpha. - * @details Gets the constant alpha component of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return constant alpha component, A-8 - * - * @api - */ -uint8_t ltdcFgGetConstantAlpha(LTDCDriver *ltdcp) { - - uint8_t a; - osalSysLock(); - a = ltdcFgGetConstantAlphaI(ltdcp); - osalSysUnlock(); - return a; -} - -/** - * @brief Set foreground layer constant alpha. - * @details Sets the constant alpha component of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] a constant alpha component, A-8 - * - * @iclass - */ -void ltdcFgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CACR = ((LTDC_Layer2->CACR & ~LTDC_LxCACR_CONSTA) | - ((uint32_t)a & LTDC_LxCACR_CONSTA)); -} - -/** - * @brief Set foreground layer constant alpha. - * @details Sets the constant alpha component of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] a constant alpha component, A-8 - * - * @api - */ -void ltdcFgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a) { - - osalSysLock(); - ltdcFgSetConstantAlphaI(ltdcp, a); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer default color. - * @details Gets the default color of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return default color, RGB-888 - * - * @iclass - */ -ltdc_color_t ltdcFgGetDefaultColorI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_color_t)LTDC_Layer2->DCCR; -} - -/** - * @brief Get foreground layer default color. - * @details Gets the default color of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return default color, RGB-888 - * - * @api - */ -ltdc_color_t ltdcFgGetDefaultColor(LTDCDriver *ltdcp) { - - ltdc_color_t color; - osalSysLock(); - color = ltdcFgGetDefaultColorI(ltdcp); - osalSysUnlock(); - return color; -} - -/** - * @brief Set foreground layer default color. - * @details Sets the default color of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c default color, RGB-888 - * - * @iclass - */ -void ltdcFgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->DCCR = (uint32_t)c; -} - -/** - * @brief Set foreground layer default color. - * @details Sets the default color of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] c default color, RGB-888 - * - * @api - */ -void ltdcFgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c) { - - osalSysLock(); - ltdcFgSetDefaultColorI(ltdcp, c); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer blending factors. - * @details Gets the blending factors of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return blending factors - * - * @iclass - */ -ltdc_blendf_t ltdcFgGetBlendingFactorsI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (ltdc_blendf_t)(LTDC_Layer2->BFCR & LTDC_LxBFCR_BF); -} - -/** - * @brief Get foreground layer blending factors. - * @details Gets the blending factors of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return blending factors - * - * @api - */ -ltdc_blendf_t ltdcFgGetBlendingFactors(LTDCDriver *ltdcp) { - - ltdc_blendf_t bf; - osalSysLock(); - bf = ltdcFgGetBlendingFactorsI(ltdcp); - osalSysUnlock(); - return bf; -} - -/** - * @brief Set foreground layer blending factors. - * @details Sets the blending factors of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] factors blending factors - * - * @iclass - */ -void ltdcFgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->BFCR = ((LTDC_Layer2->BFCR & ~LTDC_LxBFCR_BF) | - ((uint32_t)bf & LTDC_LxBFCR_BF)); -} - -/** - * @brief Set foreground layer blending factors. - * @details Sets the blending factors of the foreground layer (layer 1). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] factors blending factors - * - * @api - */ -void ltdcFgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf) { - - osalSysLock(); - ltdcFgSetBlendingFactorsI(ltdcp, bf); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer window specs. - * @details Gets the window specifications of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] windowp pointer to the window specifications - * - * @iclass - */ -void ltdcFgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(windowp != NULL); - (void)ltdcp; - - windowp->hstart = - (uint16_t)((LTDC_Layer2->WHPCR & LTDC_LxWHPCR_WHSTPOS) >> 0); - windowp->hstop = - (uint16_t)((LTDC_Layer2->WHPCR & LTDC_LxWHPCR_WHSPPOS) >> 16); - windowp->vstart = - (uint16_t)((LTDC_Layer2->WVPCR & LTDC_LxWVPCR_WVSTPOS) >> 0); - windowp->vstop = - (uint16_t)((LTDC_Layer2->WVPCR & LTDC_LxWVPCR_WVSPPOS) >> 16); -} - -/** - * @brief Get foreground layer window specs. - * @details Gets the window specifications of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] windowp pointer to the window specifications - * - * @api - */ -void ltdcFgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp) { - - osalSysLock(); - ltdcFgGetWindowI(ltdcp, windowp); - osalSysUnlock(); -} - -/** - * @brief Set foreground layer window specs. - * @details Sets the window specifications of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] windowp pointer to the window specifications - * - * @iclass - */ -void ltdcFgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp) { - - uint32_t start, stop; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(windowp != NULL); - (void)ltdcp; - - osalDbgAssert(windowp->hstop < ltdcp->config->screen_width, "bounds"); - osalDbgAssert(windowp->vstop < ltdcp->config->screen_height, "bounds"); - - /* Horizontal boundaries.*/ - start = (uint32_t)windowp->hstart + ltdcp->active_window.hstart; - stop = (uint32_t)windowp->hstop + ltdcp->active_window.hstart; - - osalDbgAssert(start >= ltdcp->active_window.hstart, "bounds"); - osalDbgAssert(stop <= ltdcp->active_window.hstop, "bounds"); - - LTDC_Layer2->WHPCR = (((start << 0) & LTDC_LxWHPCR_WHSTPOS) | - ((stop << 16) & LTDC_LxWHPCR_WHSPPOS)); - - /* Vertical boundaries.*/ - start = (uint32_t)windowp->vstart + ltdcp->active_window.vstart; - stop = (uint32_t)windowp->vstop + ltdcp->active_window.vstart; - - osalDbgAssert(start >= ltdcp->active_window.vstart, "bounds"); - osalDbgAssert(stop <= ltdcp->active_window.vstop, "bounds"); - - LTDC_Layer2->WVPCR = (((start << 0) & LTDC_LxWVPCR_WVSTPOS) | - ((stop << 16) & LTDC_LxWVPCR_WVSPPOS)); -} - -/** - * @brief Set foreground layer window specs. - * @details Sets the window specifications of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] windowp pointer to the window specifications - * - * @api - */ -void ltdcFgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp) { - - osalSysLock(); - ltdcFgSetWindowI(ltdcp, windowp); - osalSysUnlock(); -} - -/** - * @brief Set foreground layer window as invalid. - * @details Sets the window specifications of the foreground layer (layer 2) - * so that the window is pixel sized at the screen origin. - * @note Useful before reconfiguring the frame specifications of the layer, - * to avoid errors. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @iclass - */ -void ltdcFgSetInvalidWindowI(LTDCDriver *ltdcp) { - - ltdcFgSetWindowI(ltdcp, <dc_invalid_window); -} - -/** - * @brief Set foreground layer window as invalid. - * @details Sets the window specifications of the foreground layer (layer 2) - * so that the window is pixel sized at the screen origin. - * @note Useful before reconfiguring the frame specifications of the layer, - * to avoid errors. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @api - */ -void ltdcFgSetInvalidWindow(LTDCDriver *ltdcp) { - - osalSysLock(); - ltdcFgSetWindowI(ltdcp, <dc_invalid_window); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer frame buffer specs. - * @details Gets the frame buffer specifications of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] framep pointer to the frame buffer specifications - * - * @iclass - */ -void ltdcFgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(framep != NULL); - - framep->bufferp = (void *)(LTDC_Layer2->CFBAR & LTDC_LxCFBAR_CFBADD); - framep->pitch = (size_t)((LTDC_Layer2->CFBLR & LTDC_LxCFBLR_CFBP) >> 16); - framep->width = (uint16_t)(((LTDC_Layer2->CFBLR & LTDC_LxCFBLR_CFBLL) - 3) / - ltdcBytesPerPixel(ltdcFgGetPixelFormatI(ltdcp))); - framep->height = (uint16_t)(LTDC_Layer2->CFBLNR & LTDC_LxCFBLNR_CFBLNBR); -} - -/** - * @brief Get foreground layer frame buffer specs. - * @details Gets the frame buffer specifications of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] framep pointer to the frame buffer specifications - * - * @api - */ -void ltdcFgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep) { - - osalSysLock(); - ltdcFgGetFrameI(ltdcp, framep); - osalSysUnlock(); -} - -/** - * @brief Set foreground layer frame buffer specs. - * @details Sets the frame buffer specifications of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] framep pointer to the frame buffer specifications - * - * @iclass - */ -void ltdcFgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep) { - - size_t linesize; - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(framep != NULL); - - ltdcFgSetPixelFormatI(ltdcp, framep->fmt); - - linesize = ltdcBytesPerPixel(framep->fmt) * framep->width; - - osalDbgAssert(framep->width <= ltdcp->config->screen_width, "bounds"); - osalDbgAssert(framep->height <= ltdcp->config->screen_height, "bounds"); - osalDbgAssert(linesize >= LTDC_MIN_FRAME_WIDTH_BYTES, "bounds"); - osalDbgAssert(linesize <= LTDC_MAX_FRAME_WIDTH_BYTES, "bounds"); - osalDbgAssert(framep->height >= LTDC_MIN_FRAME_HEIGHT_LINES, "bounds"); - osalDbgAssert(framep->height <= LTDC_MAX_FRAME_HEIGHT_LINES, "bounds"); - osalDbgAssert(framep->pitch >= linesize, "bounds"); - - LTDC_Layer2->CFBAR = (uint32_t)framep->bufferp & LTDC_LxCFBAR_CFBADD; - LTDC_Layer2->CFBLR = ((((uint32_t)framep->pitch << 16) & LTDC_LxCFBLR_CFBP) | - ((linesize + 3) & LTDC_LxCFBLR_CFBLL)); - LTDC_Layer2->CFBLNR = (uint32_t)framep->height & LTDC_LxCFBLNR_CFBLNBR; -} - -/** - * @brief Set foreground layer frame buffer specs. - * @details Sets the frame buffer specifications of the foreground layer - * (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] framep pointer to the frame buffer specifications - * - * @api - */ -void ltdcFgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep) { - - osalSysLock(); - ltdcFgSetFrameI(ltdcp, framep); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer frame buffer address. - * @details Gets the frame buffer address of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return frame buffer address - * - * @iclass - */ -void *ltdcFgGetFrameAddressI(LTDCDriver *ltdcp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - return (void *)LTDC_Layer2->CFBAR; -} - -/** - * @brief Get foreground layer frame buffer address. - * @details Gets the frame buffer address of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * - * @return frame buffer address - * - * @api - */ -void *ltdcFgGetFrameAddress(LTDCDriver *ltdcp) { - - void *bufferp; - osalSysLock(); - bufferp = ltdcFgGetFrameAddressI(ltdcp); - osalSysUnlock(); - return bufferp; -} - -/** - * @brief Set foreground layer frame buffer address. - * @details Sets the frame buffer address of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] bufferp frame buffer address - * - * @iclass - */ -void ltdcFgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - (void)ltdcp; - - LTDC_Layer2->CFBAR = (uint32_t)bufferp; -} - -/** - * @brief Set foreground layer frame buffer address. - * @details Sets the frame buffer address of the foreground layer (layer 2). - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] bufferp frame buffer address - * - * @api - */ -void ltdcFgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp) { - - osalSysLock(); - ltdcFgSetFrameAddressI(ltdcp, bufferp); - osalSysUnlock(); -} - -/** - * @brief Get foreground layer specifications. - * @details Gets the foreground layer (layer 2) specifications at once. - * @note If palette specifications cannot be retrieved, they are set to - * @p NULL. This is not an error. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @iclass - */ -void ltdcFgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - osalDbgCheck(cfgp != NULL); - - ltdcFgGetFrameI(ltdcp, (ltdc_frame_t *)cfgp->frame); - ltdcFgGetWindowI(ltdcp, (ltdc_window_t *)cfgp->window); - cfgp->def_color = ltdcFgGetDefaultColorI(ltdcp); - cfgp->key_color = ltdcFgGetKeyingColorI(ltdcp); - cfgp->const_alpha = ltdcFgGetConstantAlphaI(ltdcp); - cfgp->blending = ltdcFgGetBlendingFactorsI(ltdcp); - - cfgp->pal_colors = NULL; - cfgp->pal_length = 0; - - cfgp->flags = ltdcFgGetEnableFlagsI(ltdcp); -} - -/** - * @brief Get foreground layer specifications. - * @details Gets the foreground layer (layer 2) specifications at once. - * @note If palette specifications cannot be retrieved, they are set to - * @p NULL. This is not an error. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[out] cfgp pointer to the layer specifications - * - * @api - */ -void ltdcFgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp) { - - osalSysLock(); - ltdcFgGetLayerI(ltdcp, cfgp); - osalSysUnlock(); -} - -/** - * @brief Set foreground layer specifications. - * @details Sets the foreground layer (layer 2) specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @iclass - */ -void ltdcFgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp) { - - osalDbgCheckClassI(); - osalDbgCheck(ltdcp == <DCD1); - - if (cfgp == NULL) - cfgp = <dc_default_laycfg; - - osalDbgCheck((cfgp->pal_colors == NULL) == (cfgp->pal_length == 0)); - - ltdcFgSetFrameI(ltdcp, cfgp->frame); - ltdcFgSetWindowI(ltdcp, cfgp->window); - ltdcFgSetDefaultColorI(ltdcp, cfgp->def_color); - ltdcFgSetKeyingColorI(ltdcp, cfgp->key_color); - ltdcFgSetConstantAlphaI(ltdcp, cfgp->const_alpha); - ltdcFgSetBlendingFactorsI(ltdcp, cfgp->blending); - - if (cfgp->pal_length > 0) - ltdcFgSetPaletteI(ltdcp, cfgp->pal_colors, cfgp->pal_length); - - ltdcFgSetEnableFlagsI(ltdcp, cfgp->flags); -} - -/** - * @brief Set foreground layer specifications. - * @details Sets the foreground layer (layer 2) specifications at once. - * @note If the palette is unspecified, the layer palette is unmodified. - * - * @param[in] ltdcp pointer to the @p LTDCDriver object - * @param[in] cfgp pointer to the layer specifications - * - * @api - */ -void ltdcFgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp) { - - osalSysLock(); - ltdcFgSetConfigI(ltdcp, cfgp); - osalSysUnlock(); -} - -/** @} */ - -/** - * @name LTDC helper functions - */ - -/** - * @brief Compute bits per pixel. - * @details Computes the bits per pixel for the specified pixel format. - * - * @param[in] fmt pixel format - * - * @retuen bits per pixel - * - * @api - */ -size_t ltdcBitsPerPixel(ltdc_pixfmt_t fmt) { - - osalDbgAssert(fmt < LTDC_MAX_PIXFMT_ID, "invalid format"); - - return (size_t)ltdc_bpp[(unsigned)fmt]; -} - -#if (TRUE == LTDC_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__) - -/** - * @brief Convert from ARGB-8888. - * @details Converts an ARGB-8888 color to the specified pixel format. - * - * @param[in] c color, ARGB-8888 - * @param[in] fmt target pixel format - * - * @return raw color value for the target pixel format, left - * padded with zeros. - * - * @api - */ -ltdc_color_t ltdcFromARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt) { - - switch (fmt) { - case LTDC_FMT_ARGB8888: { - return c; - } - case LTDC_FMT_RGB888: { - return (c & 0x00FFFFFF); - } - case LTDC_FMT_RGB565: { - return (((c & 0x000000F8) >> ( 8 - 5)) | - ((c & 0x0000FC00) >> (16 - 11)) | - ((c & 0x00F80000) >> (24 - 16))); - } - case LTDC_FMT_ARGB1555: { - return (((c & 0x000000F8) >> ( 8 - 5)) | - ((c & 0x0000F800) >> (16 - 10)) | - ((c & 0x00F80000) >> (24 - 15)) | - ((c & 0x80000000) >> (32 - 16))); - } - case LTDC_FMT_ARGB4444: { - return (((c & 0x000000F0) >> ( 8 - 4)) | - ((c & 0x0000F000) >> (16 - 8)) | - ((c & 0x00F00000) >> (24 - 12)) | - ((c & 0xF0000000) >> (32 - 16))); - } - case LTDC_FMT_L8: { - return (c & 0x000000FF); - } - case LTDC_FMT_AL44: { - return (((c & 0x000000F0) >> ( 8 - 4)) | - ((c & 0xF0000000) >> (32 - 8))); - } - case LTDC_FMT_AL88: { - return (((c & 0x000000FF) >> ( 8 - 8)) | - ((c & 0xFF000000) >> (32 - 16))); - } - default: - osalDbgAssert(false, "invalid format"); - return 0; - } -} - -/** - * @brief Convert to ARGB-8888. - * @details Converts color of the specified pixel format to an ARGB-8888 color. - * - * @param[in] c color for the source pixel format, left padded with - * zeros. - * @param[in] fmt source pixel format - * - * @return color in ARGB-8888 format - * - * @api - */ -ltdc_color_t ltdcToARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt) { - - switch (fmt) { - case LTDC_FMT_ARGB8888: { - return c; - } - case LTDC_FMT_RGB888: { - return ((c & 0x00FFFFFF) | 0xFF000000); - } - case LTDC_FMT_RGB565: { - register ltdc_color_t output = 0xFF000000; - if (c & 0x001F) output |= (((c & 0x001F) << ( 8 - 5)) | 0x00000007); - if (c & 0x07E0) output |= (((c & 0x07E0) << (16 - 11)) | 0x00000300); - if (c & 0xF800) output |= (((c & 0xF800) << (24 - 16)) | 0x00070000); - return output; - } - case LTDC_FMT_ARGB1555: { - register ltdc_color_t output = 0x00000000; - if (c & 0x001F) output |= (((c & 0x001F) << ( 8 - 5)) | 0x00000007); - if (c & 0x03E0) output |= (((c & 0x03E0) << (16 - 10)) | 0x00000700); - if (c & 0x7C00) output |= (((c & 0x7C00) << (24 - 15)) | 0x00070000); - if (c & 0x8000) output |= 0xFF000000; - return output; - } - case LTDC_FMT_ARGB4444: { - register ltdc_color_t output = 0x00000000; - if (c & 0x000F) output |= (((c & 0x000F) << ( 8 - 4)) | 0x0000000F); - if (c & 0x00F0) output |= (((c & 0x00F0) << (16 - 8)) | 0x00000F00); - if (c & 0x0F00) output |= (((c & 0x0F00) << (24 - 12)) | 0x000F0000); - if (c & 0xF000) output |= (((c & 0xF000) << (32 - 16)) | 0x0F000000); - return output; - } - case LTDC_FMT_L8: { - return ((c & 0xFF) | 0xFF000000); - } - case LTDC_FMT_AL44: { - register ltdc_color_t output = 0x00000000; - if (c & 0x0F) output |= (((c & 0x0F) << ( 8 - 4)) | 0x0000000F); - if (c & 0xF0) output |= (((c & 0xF0) << (32 - 8)) | 0x0F000000); - return output; - } - case LTDC_FMT_AL88: { - return (((c & 0x00FF) << ( 8 - 8)) | - ((c & 0xFF00) << (32 - 16))); - } - default: - osalDbgAssert(false, "invalid format"); - return 0; - } -} - -#endif /* LTDC_USE_SOFTWARE_CONVERSIONS */ - -/** @} */ - -/** @} */ - -#endif /* STM32_LTDC_USE_LTDC */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h deleted file mode 100644 index 16b38ca..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h +++ /dev/null @@ -1,736 +0,0 @@ -/* - Copyright (C) 2013-2015 Andrea Zoppi - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file stm32_ltdc.h - * @brief LCD-TFT Controller Driver. - * - * @addtogroup ltdc - * @{ - */ - -#ifndef _STM32_LTDC_H_ -#define _STM32_LTDC_H_ - -/** - * @brief Using the LTDC driver. - */ -#if !defined(STM32_LTDC_USE_LTDC) || defined(__DOXYGEN__) -#define STM32_LTDC_USE_LTDC (FALSE) -#endif - -#if (TRUE == STM32_LTDC_USE_LTDC) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name LTDC enable flags - * @{ - */ -#define LTDC_EF_ENABLE (1 << 0) /**< LTDC enabled.*/ -#define LTDC_EF_DITHER (1 << 16) /**< Dithering enabled.*/ -#define LTDC_EF_PIXCLK_INVERT (1 << 28) /**< Inverted pixel clock.*/ -#define LTDC_EF_DATAEN_HIGH (1 << 29) /**< Active-high data enable.*/ -#define LTDC_EF_VSYNC_HIGH (1 << 30) /**< Active-high vsync.*/ -#define LTDC_EF_HSYNC_HIGH (1 << 31) /**< Active-high hsync.*/ - -#define LTDC_EF_MASK \ - (LTDC_EF_ENABLE | LTDC_EF_DITHER | LTDC_EF_PIXCLK_INVERT | \ - LTDC_EF_DATAEN_HIGH | LTDC_EF_VSYNC_HIGH | LTDC_EF_HSYNC_HIGH) -/** @} */ - -/** - * @name LTDC layer enable flags - * @{ - */ -#define LTDC_LEF_ENABLE (1 << 0) /**< Layer enabled*/ -#define LTDC_LEF_KEYING (1 << 1) /**< Color keying enabled.*/ -#define LTDC_LEF_PALETTE (1 << 4) /**< Palette enabled.*/ - -#define LTDC_LEF_MASK \ - (LTDC_LEF_ENABLE | LTDC_LEF_KEYING | LTDC_LEF_PALETTE) -/** @} */ - -/** - * @name LTDC pixel formats - * @{ - */ -#define LTDC_FMT_ARGB8888 (0) /**< ARGB-8888 format.*/ -#define LTDC_FMT_RGB888 (1) /**< RGB-888 format.*/ -#define LTDC_FMT_RGB565 (2) /**< RGB-565 format.*/ -#define LTDC_FMT_ARGB1555 (3) /**< ARGB-1555 format.*/ -#define LTDC_FMT_ARGB4444 (4) /**< ARGB-4444 format.*/ -#define LTDC_FMT_L8 (5) /**< L-8 format.*/ -#define LTDC_FMT_AL44 (6) /**< AL-44 format.*/ -#define LTDC_FMT_AL88 (7) /**< AL-88 format.*/ -/** @} */ - -/** - * @name LTDC pixel format aliased raw masks - * @{ - */ -#define LTDC_XMASK_ARGB8888 (0xFFFFFFFF) /**< ARGB-8888 aliased mask.*/ -#define LTDC_XMASK_RGB888 (0x00FFFFFF) /**< RGB-888 aliased mask.*/ -#define LTDC_XMASK_RGB565 (0x00F8FCF8) /**< RGB-565 aliased mask.*/ -#define LTDC_XMASK_ARGB1555 (0x80F8F8F8) /**< ARGB-1555 aliased mask.*/ -#define LTDC_XMASK_ARGB4444 (0xF0F0F0F0) /**< ARGB-4444 aliased mask.*/ -#define LTDC_XMASK_L8 (0x000000FF) /**< L-8 aliased mask.*/ -#define LTDC_XMASK_AL44 (0xF00000F0) /**< AL-44 aliased mask.*/ -#define LTDC_XMASK_AL88 (0xFF0000FF) /**< AL-88 aliased mask.*/ -/** @} */ - -/** - * @name LTDC blending factors - * @{ - */ -#define LTDC_BLEND_FIX1_FIX2 (0x0405) /**< cnst1; 1 - cnst2 */ -#define LTDC_BLEND_FIX1_MOD2 (0x0407) /**< cnst1; 1 - a2 * cnst2 */ -#define LTDC_BLEND_MOD1_FIX2 (0x0605) /**< a1 * cnst1; 1 - cnst2 */ -#define LTDC_BLEND_MOD1_MOD2 (0x0607) /**< a1 * cnst1; 1 - a2 * cnst2 */ -/** @} */ - -/** - * @name LTDC parameter bounds - * @{ - */ - -#define LTDC_MIN_SCREEN_WIDTH (1) -#define LTDC_MIN_SCREEN_HEIGHT (1) -#define LTDC_MAX_SCREEN_WIDTH (800) -#define LTDC_MAX_SCREEN_HEIGHT (600) - -#define LTDC_MIN_HSYNC_WIDTH (1) -#define LTDC_MIN_VSYNC_HEIGHT (1) -#define LTDC_MAX_HSYNC_WIDTH (1 << 12) -#define LTDC_MAX_VSYNC_HEIGHT (1 << 11) - -#define LTDC_MIN_HBP_WIDTH (0) -#define LTDC_MIN_VBP_HEIGHT (0) -#define LTDC_MAX_HBP_WIDTH (1 << 12) -#define LTDC_MAX_VBP_HEIGHT (1 << 11) - -#define LTDC_MIN_ACC_HBP_WIDTH (1) -#define LTDC_MIN_ACC_VBP_HEIGHT (1) -#define LTDC_MAX_ACC_HBP_WIDTH (1 << 12) -#define LTDC_MAX_ACC_VBP_HEIGHT (1 << 11) - -#define LTDC_MIN_HFP_WIDTH (0) -#define LTDC_MIN_VFP_HEIGHT (0) -#define LTDC_MAX_HFP_WIDTH (1 << 12) -#define LTDC_MAX_VFP_HEIGHT (1 << 11) - -#define LTDC_MIN_ACTIVE_WIDTH (0) -#define LTDC_MIN_ACTIVE_HEIGHT (0) -#define LTDC_MAX_ACTIVE_WIDTH (1 << 12) -#define LTDC_MAX_ACTIVE_HEIGHT (1 << 11) - -#define LTDC_MIN_ACC_ACTIVE_WIDTH (1) -#define LTDC_MIN_ACC_ACTIVE_HEIGHT (1) -#define LTDC_MAX_ACC_ACTIVE_WIDTH (1 << 12) -#define LTDC_MAX_ACC_ACTIVE_HEIGHT (1 << 11) - -#define LTDC_MIN_ACC_TOTAL_WIDTH (1) -#define LTDC_MIN_ACC_TOTAL_HEIGHT (1) -#define LTDC_MAX_ACC_TOTAL_WIDTH (1 << 12) -#define LTDC_MAX_ACC_TOTAL_HEIGHT (1 << 11) - -#define LTDC_MIN_LINE_INTERRUPT_POS (0) -#define LTDC_MAX_LINE_INTERRUPT_POS ((1 << 11) - 1) - -#define LTDC_MIN_WINDOW_HSTART (0) -#define LTDC_MIN_WINDOW_HSTART (0) -#define LTDC_MAX_WINDOW_HSTOP ((1 << 12) - 1) -#define LTDC_MAX_WINDOW_HSTOP ((1 << 12) - 1) - -#define LTDC_MIN_WINDOW_VSTART (0) -#define LTDC_MIN_WINDOW_VSTART (0) -#define LTDC_MAX_WINDOW_VSTOP ((1 << 11) - 1) -#define LTDC_MAX_WINDOW_VSTOP ((1 << 11) - 1) - -#define LTDC_MIN_FRAME_WIDTH_BYTES (0) -#define LTDC_MIN_FRAME_HEIGHT_LINES (0) -#define LTDC_MIN_FRAME_PITCH_BYTES (0) -#define LTDC_MAX_FRAME_WIDTH_BYTES ((1 << 13) - 1 - 3) -#define LTDC_MAX_FRAME_HEIGHT_LINES ((1 << 11) - 1) -#define LTDC_MAX_FRAME_PITCH_BYTES ((1 << 13) - 1) - -#define LTDC_MIN_PIXFMT_ID (0) -#define LTDC_MAX_PIXFMT_ID (7) - -#define LTDC_MAX_PALETTE_LENGTH (256) - -/** @} */ - -/** - * @name LTDC basic ARGB-8888 colors. - * @{ - */ -/* Microsoft Windows default 16-color palette.*/ -#define LTDC_COLOR_BLACK (0xFF000000) -#define LTDC_COLOR_MAROON (0xFF800000) -#define LTDC_COLOR_GREEN (0xFF008000) -#define LTDC_COLOR_OLIVE (0xFF808000) -#define LTDC_COLOR_NAVY (0xFF000080) -#define LTDC_COLOR_PURPLE (0xFF800080) -#define LTDC_COLOR_TEAL (0xFF008080) -#define LTDC_COLOR_SILVER (0xFFC0C0C0) -#define LTDC_COLOR_GRAY (0xFF808080) -#define LTDC_COLOR_RED (0xFFFF0000) -#define LTDC_COLOR_LIME (0xFF00FF00) -#define LTDC_COLOR_YELLOW (0xFFFFFF00) -#define LTDC_COLOR_BLUE (0xFF0000FF) -#define LTDC_COLOR_FUCHSIA (0xFFFF00FF) -#define LTDC_COLOR_AQUA (0xFF00FFFF) -#define LTDC_COLOR_WHITE (0xFFFFFFFF) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name LTDC configuration options - * @{ - */ - -/** - * @brief LTDC event interrupt priority level setting. - */ -#if !defined(STM32_LTDC_EV_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_LTDC_EV_IRQ_PRIORITY (11) -#endif - -/** - * @brief LTDC error interrupt priority level setting. - */ -#if !defined(STM32_LTDC_ER_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_LTDC_ER_IRQ_PRIORITY (11) -#endif - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(LTDC_USE_WAIT) || defined(__DOXYGEN__) -#define LTDC_USE_WAIT (TRUE) -#endif - -/** - * @brief Enables the @p ltdcAcquireBus() and @p ltdcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(LTDC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define LTDC_USE_MUTUAL_EXCLUSION (TRUE) -#endif - -/** - * @brief Provides software color conversion functions. - * @note Disabling this option saves both code and data space. - */ -#if !defined(LTDC_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__) -#define LTDC_USE_SOFTWARE_CONVERSIONS (TRUE) -#endif - -/** - * @brief Enables checks for LTDC functions. - * @note Disabling this option saves both code and data space. - * @note Disabling checks by ChibiOS will automatically disable LTDC checks. - */ -#if !defined(LTDC_USE_CHECKS) || defined(__DOXYGEN__) -#define LTDC_USE_CHECKS (TRUE) -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (TRUE != STM32_HAS_LTDC) -#error "LTDC must be present when using the LTDC subsystem" -#endif - -#if (TRUE == STM32_LTDC_USE_LTDC) && (TRUE != STM32_HAS_LTDC) -#error "LTDC not present in the selected device" -#endif - -#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION) -#if (TRUE != CH_CFG_USE_MUTEXES) && (TRUE != CH_CFG_USE_SEMAPHORES) -#error "LTDC_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES" -#endif -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/* Complex types forwarding.*/ -typedef union ltdc_coloralias_t ltdc_coloralias_t; -typedef struct ltdc_window_t ltdc_window_t; -typedef struct ltdc_frame_t ltdc_frame_t; -typedef struct ltdc_laycfg_t ltdc_laycfg_t; -typedef struct LTDCConfig LTDCConfig; -typedef enum ltdc_state_t ltdc_state_t; -typedef struct LTDCDriver LTDCDriver; - -/** - * @name LTDC Data types - * @{ - */ - -/** - * @brief LTDC generic color. - */ -typedef uint32_t ltdc_color_t; - -/** - * @brief LTDC color aliases. - * @detail Mapped with ARGB-8888, except for luminance (L mapped onto B). - * Padding fields are prefixed with <tt>'x'</tt>, and should be clear - * (all 0) before compression and set (all 1) after expansion. - */ -typedef union ltdc_coloralias_t { - struct { - unsigned b : 8; - unsigned g : 8; - unsigned r : 8; - unsigned a : 8; - } argb8888; /**< Mapped ARGB-8888 bits.*/ - struct { - unsigned b : 8; - unsigned g : 8; - unsigned r : 8; - unsigned xa : 8; - } rgb888; /**< Mapped RGB-888 bits.*/ - struct { - unsigned xb : 3; - unsigned b : 5; - unsigned xg : 2; - unsigned g : 6; - unsigned xr : 3; - unsigned r : 5; - unsigned xa : 8; - } rgb565; /**< Mapped RGB-565 bits.*/ - struct { - unsigned xb : 3; - unsigned b : 5; - unsigned xg : 3; - unsigned g : 5; - unsigned xr : 3; - unsigned r : 5; - unsigned xa : 7; - unsigned a : 1; - } argb1555; /**< Mapped ARGB-1555 values.*/ - struct { - unsigned xb : 4; - unsigned b : 4; - unsigned xg : 4; - unsigned g : 4; - unsigned xr : 4; - unsigned r : 4; - unsigned xa : 4; - unsigned a : 4; - } argb4444; /**< Mapped ARGB-4444 values.*/ - struct { - unsigned l : 8; - unsigned x : 16; - unsigned xa : 8; - } l8; /**< Mapped L-8 bits.*/ - struct { - unsigned xl : 4; - unsigned l : 4; - unsigned x : 16; - unsigned xa : 4; - unsigned a : 4; - } al44; /**< Mapped AL-44 bits.*/ - struct { - unsigned l : 8; - unsigned x : 16; - unsigned a : 8; - } al88; /**< Mapped AL-88 bits.*/ - ltdc_color_t aliased; /**< Aliased raw bits.*/ -} ltdc_coloralias_t; - -/** - * @brief LTDC layer identifier. - */ -typedef uint32_t ltdc_layerid_t; - -/** - * @brief LTDC pixel format. - */ -typedef uint32_t ltdc_pixfmt_t; - -/** - * @brief LTDC blending factor. - */ -typedef uint32_t ltdc_blendf_t; - -/** - * @brief LTDC ISR callback. - */ -typedef void (*ltdc_isrcb_t)(LTDCDriver *ltdcp); - -/** - * @brief LTDC window specifications. - */ -typedef struct ltdc_window_t { - uint16_t hstart; /**< Horizontal start pixel (left).*/ - uint16_t hstop; /**< Horizontal stop pixel (right).*/ - uint16_t vstart; /**< Vertical start pixel (top).*/ - uint16_t vstop; /**< Vertical stop pixel (bottom).*/ -} ltdc_window_t; - -/** - * @brief LTDC frame specifications. - */ -typedef struct ltdc_frame_t { - void *bufferp; /**< Frame buffer address.*/ - uint16_t width; /**< Frame width, in pixels.*/ - uint16_t height; /**< Frame height, in pixels.*/ - size_t pitch; /**< Line pitch, in bytes.*/ - ltdc_pixfmt_t fmt; /**< Pixel format.*/ -} ltdc_frame_t; - -/** - * @brief LTDC configuration flags. - */ -typedef uint8_t ltdc_flags_t; - -/** - * @brief LTDC startup layer configuration. - */ -typedef struct ltdc_laycfg_t { - const ltdc_frame_t *frame; /**< Frame buffer specifications.*/ - const ltdc_window_t *window; /**< Window specifications.*/ - ltdc_color_t def_color; /**< Default color, ARGB-8888.*/ - uint8_t const_alpha; /**< Constant alpha factor.*/ - ltdc_color_t key_color; /**< Color key.*/ - const ltdc_color_t *pal_colors; /**< Palette colors, or @p NULL.*/ - uint16_t pal_length; /**< Palette length, or @p 0.*/ - ltdc_blendf_t blending; /**< Blending factors.*/ - ltdc_flags_t flags; /**< Layer configuration flags.*/ -} ltdc_laycfg_t; - -/** - * @brief LTDC driver configuration. - */ -typedef struct LTDCConfig { - /* Display specifications.*/ - uint16_t screen_width; /**< Screen pixel width.*/ - uint16_t screen_height; /**< Screen pixel height.*/ - uint16_t hsync_width; /**< Horizontal sync pixel width.*/ - uint16_t vsync_height; /**< Vertical sync pixel height.*/ - uint16_t hbp_width; /**< Horizontal back porch pixel width.*/ - uint16_t vbp_height; /**< Vertical back porch pixel height.*/ - uint16_t hfp_width; /**< Horizontal front porch pixel width.*/ - uint16_t vfp_height; /**< Vertical front porch pixel height.*/ - ltdc_flags_t flags; /**< Driver configuration flags.*/ - - /* ISR callbacks.*/ - ltdc_isrcb_t line_isr; /**< Line Interrupt ISR, or @p NULL.*/ - ltdc_isrcb_t rr_isr; /**< Register Reload ISR, or @p NULL.*/ - ltdc_isrcb_t fuerr_isr; /**< FIFO Underrun ISR, or @p NULL.*/ - ltdc_isrcb_t terr_isr; /**< Transfer Error ISR, or @p NULL.*/ - - /* Layer and color settings.*/ - ltdc_color_t clear_color; /**< Clear screen color, RGB-888.*/ - const ltdc_laycfg_t *bg_laycfg; /**< Background layer specs, or @p NULL.*/ - const ltdc_laycfg_t *fg_laycfg; /**< Foreground layer specs, or @p NULL.*/ -} LTDCConfig; - -/** - * @brief LTDC driver state. - */ -typedef enum ltdc_state_t { - LTDC_UNINIT = (0), /**< Not initialized.*/ - LTDC_STOP = (1), /**< Stopped.*/ - LTDC_READY = (2), /**< Ready.*/ - LTDC_ACTIVE = (3), /**< Executing commands.*/ -} ltdc_state_t; - -/** - * @brief LTDC driver. - */ -typedef struct LTDCDriver { - ltdc_state_t state; /**< Driver state.*/ - const LTDCConfig *config; /**< Driver configuration.*/ - - /* Handy computations.*/ - ltdc_window_t active_window; /**< Active window coordinates.*/ - - /* Multithreading stuff.*/ -#if (TRUE == LTDC_USE_WAIT) || defined(__DOXYGEN__) - thread_t *thread; /**< Waiting thread.*/ -#endif /* LTDC_USE_WAIT */ -#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION) -#if (TRUE == CH_CFG_USE_MUTEXES) - mutex_t lock; /**< Multithreading lock.*/ -#elif (TRUE == CH_CFG_USE_SEMAPHORES) - semaphore_t lock; /**< Multithreading lock.*/ -#endif -#endif /* LTDC_USE_MUTUAL_EXCLUSION */ -} LTDCDriver; - -/** @} */ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Makes an ARGB-8888 value from byte components. - * - * @param[in] a alpha byte component - * @param[in] r red byte component - * @param[in] g green byte component - * @param[in] b blue byte component - * - * @return color in ARGB-8888 format - * - * @api - */ -#define ltdcMakeARGB8888(a, r, g, b) \ - ((((ltdc_color_t)(a) & 0xFF) << 24) | \ - (((ltdc_color_t)(r) & 0xFF) << 16) | \ - (((ltdc_color_t)(g) & 0xFF) << 8) | \ - (((ltdc_color_t)(b) & 0xFF) << 0)) - -/** - * @brief Compute bytes per pixel. - * @details Computes the bytes per pixel for the specified pixel format. - * Rounds to the ceiling. - * - * @param[in] fmt pixel format - * - * @return bytes per pixel - * - * @api - */ -#define ltdcBytesPerPixel(fmt) \ - ((ltdcBitsPerPixel(fmt) + 7) >> 3) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern LTDCDriver LTDCD1; - -#ifdef __cplusplus -extern "C" { -#endif - /* Driver methods.*/ - void ltdcInit(void); - void ltdcObjectInit(LTDCDriver *ltdcp); - ltdc_state_t ltdcGetStateI(LTDCDriver *ltdcp); - ltdc_state_t ltdcGetState(LTDCDriver *ltdcp); - void ltdcStart(LTDCDriver *ltdcp, const LTDCConfig *configp); - void ltdcStop(LTDCDriver *ltdcp); -#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION) - void ltdcAcquireBusS(LTDCDriver *ltdcp); - void ltdcAcquireBus(LTDCDriver *ltdcp); - void ltdcReleaseBusS(LTDCDriver *ltdcp); - void ltdcReleaseBus(LTDCDriver *ltdcp); -#endif /* LTDC_USE_MUTUAL_EXCLUSION */ - - /* Global methods.*/ - ltdc_flags_t ltdcGetEnableFlagsI(LTDCDriver *ltdcp); - ltdc_flags_t ltdcGetEnableFlags(LTDCDriver *ltdcp); - void ltdcSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags); - void ltdcSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags); - bool ltdcIsReloadingI(LTDCDriver *ltdcp); - bool ltdcIsReloading(LTDCDriver *ltdcp); - void ltdcStartReloadI(LTDCDriver *ltdcp, bool immediately); - void ltdcStartReload(LTDCDriver *ltdcp, bool immediately); - void ltdcReloadS(LTDCDriver *ltdcp, bool immediately); - void ltdcReload(LTDCDriver *ltdcp, bool immediately); - bool ltdcIsDitheringEnabledI(LTDCDriver *ltdcp); - bool ltdcIsDitheringEnabled(LTDCDriver *ltdcp); - void ltdcEnableDitheringI(LTDCDriver *ltdcp); - void ltdcEnableDithering(LTDCDriver *ltdcp); - void ltdcDisableDitheringI(LTDCDriver *ltdcp); - void ltdcDisableDithering(LTDCDriver *ltdcp); - ltdc_color_t ltdcGetClearColorI(LTDCDriver *ltdcp); - ltdc_color_t ltdcGetClearColor(LTDCDriver *ltdcp); - void ltdcSetClearColorI(LTDCDriver *ltdcp, ltdc_color_t c); - void ltdcSetClearColor(LTDCDriver *ltdcp, ltdc_color_t c); - uint16_t ltdcGetLineInterruptPosI(LTDCDriver *ltdcp); - uint16_t ltdcGetLineInterruptPos(LTDCDriver *ltdcp); - void ltdcSetLineInterruptPosI(LTDCDriver *ltdcp, uint16_t line); - void ltdcSetLineInterruptPos(LTDCDriver *ltdcp, uint16_t line); - bool ltdcIsLineInterruptEnabledI(LTDCDriver *ltdcp); - bool ltdcIsLineInterruptEnabled(LTDCDriver *ltdcp); - void ltdcEnableLineInterruptI(LTDCDriver *ltdcp); - void ltdcEnableLineInterrupt(LTDCDriver *ltdcp); - void ltdcDisableLineInterruptI(LTDCDriver *ltdcp); - void ltdcDisableLineInterrupt(LTDCDriver *ltdcp); - void ltdcGetCurrentPosI(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp); - void ltdcGetCurrentPos(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp); - - /* Background layer methods.*/ - ltdc_flags_t ltdcBgGetEnableFlagsI(LTDCDriver *ltdcp); - ltdc_flags_t ltdcBgGetEnableFlags(LTDCDriver *ltdcp); - void ltdcBgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags); - void ltdcBgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags); - bool ltdcBgIsEnabledI(LTDCDriver *ltdcp); - bool ltdcBgIsEnabled(LTDCDriver *ltdcp); - void ltdcBgEnableI(LTDCDriver *ltdcp); - void ltdcBgEnable(LTDCDriver *ltdcp); - void ltdcBgDisableI(LTDCDriver *ltdcp); - void ltdcBgDisable(LTDCDriver *ltdcp); - bool ltdcBgIsPaletteEnabledI(LTDCDriver *ltdcp); - bool ltdcBgIsPaletteEnabled(LTDCDriver *ltdcp); - void ltdcBgEnablePaletteI(LTDCDriver *ltdcp); - void ltdcBgEnablePalette(LTDCDriver *ltdcp); - void ltdcBgDisablePaletteI(LTDCDriver *ltdcp); - void ltdcBgDisablePalette(LTDCDriver *ltdcp); - void ltdcBgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c); - void ltdcBgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c); - void ltdcBgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length); - void ltdcBgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length); - ltdc_pixfmt_t ltdcBgGetPixelFormatI(LTDCDriver *ltdcp); - ltdc_pixfmt_t ltdcBgGetPixelFormat(LTDCDriver *ltdcp); - void ltdcBgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt); - void ltdcBgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt); - bool ltdcBgIsKeyingEnabledI(LTDCDriver *ltdcp); - bool ltdcBgIsKeyingEnabled(LTDCDriver *ltdcp); - void ltdcBgEnableKeyingI(LTDCDriver *ltdcp); - void ltdcBgEnableKeying(LTDCDriver *ltdcp); - void ltdcBgDisableKeyingI(LTDCDriver *ltdcp); - void ltdcBgDisableKeying(LTDCDriver *ltdcp); - ltdc_color_t ltdcBgGetKeyingColorI(LTDCDriver *ltdcp); - ltdc_color_t ltdcBgGetKeyingColor(LTDCDriver *ltdcp); - void ltdcBgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c); - void ltdcBgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c); - uint8_t ltdcBgGetConstantAlphaI(LTDCDriver *ltdcp); - uint8_t ltdcBgGetConstantAlpha(LTDCDriver *ltdcp); - void ltdcBgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a); - void ltdcBgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a); - ltdc_color_t ltdcBgGetDefaultColorI(LTDCDriver *ltdcp); - ltdc_color_t ltdcBgGetDefaultColor(LTDCDriver *ltdcp); - void ltdcBgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c); - void ltdcBgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c); - ltdc_blendf_t ltdcBgGetBlendingFactorsI(LTDCDriver *ltdcp); - ltdc_blendf_t ltdcBgGetBlendingFactors(LTDCDriver *ltdcp); - void ltdcBgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf); - void ltdcBgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf); - void ltdcBgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp); - void ltdcBgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp); - void ltdcBgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp); - void ltdcBgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp); - void ltdcBgSetInvalidWindowI(LTDCDriver *ltdcp); - void ltdcBgSetInvalidWindow(LTDCDriver *ltdcp); - void ltdcBgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep); - void ltdcBgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep); - void ltdcBgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep); - void ltdcBgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep); - void *ltdcBgGetFrameAddressI(LTDCDriver *ltdcp); - void *ltdcBgGetFrameAddress(LTDCDriver *ltdcp); - void ltdcBgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp); - void ltdcBgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp); - void ltdcBgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp); - void ltdcBgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp); - void ltdcBgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp); - void ltdcBgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp); - - /* Foreground layer methods.*/ - ltdc_flags_t ltdcFgGetEnableFlagsI(LTDCDriver *ltdcp); - ltdc_flags_t ltdcFgGetEnableFlags(LTDCDriver *ltdcp); - void ltdcFgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags); - void ltdcFgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags); - bool ltdcFgIsEnabledI(LTDCDriver *ltdcp); - bool ltdcFgIsEnabled(LTDCDriver *ltdcp); - void ltdcFgEnableI(LTDCDriver *ltdcp); - void ltdcFgEnable(LTDCDriver *ltdcp); - void ltdcFgDisableI(LTDCDriver *ltdcp); - void ltdcFgDisable(LTDCDriver *ltdcp); - bool ltdcFgIsPaletteEnabledI(LTDCDriver *ltdcp); - bool ltdcFgIsPaletteEnabled(LTDCDriver *ltdcp); - void ltdcFgEnablePaletteI(LTDCDriver *ltdcp); - void ltdcFgEnablePalette(LTDCDriver *ltdcp); - void ltdcFgDisablePaletteI(LTDCDriver *ltdcp); - void ltdcFgDisablePalette(LTDCDriver *ltdcp); - void ltdcFgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c); - void ltdcFgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c); - void ltdcFgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length); - void ltdcFgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[], - uint16_t length); - ltdc_pixfmt_t ltdcFgGetPixelFormatI(LTDCDriver *ltdcp); - ltdc_pixfmt_t ltdcFgGetPixelFormat(LTDCDriver *ltdcp); - void ltdcFgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt); - void ltdcFgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt); - bool ltdcFgIsKeyingEnabledI(LTDCDriver *ltdcp); - bool ltdcFgIsKeyingEnabled(LTDCDriver *ltdcp); - void ltdcFgEnableKeyingI(LTDCDriver *ltdcp); - void ltdcFgEnableKeying(LTDCDriver *ltdcp); - void ltdcFgDisableKeyingI(LTDCDriver *ltdcp); - void ltdcFgDisableKeying(LTDCDriver *ltdcp); - ltdc_color_t ltdcFgGetKeyingColorI(LTDCDriver *ltdcp); - ltdc_color_t ltdcFgGetKeyingColor(LTDCDriver *ltdcp); - void ltdcFgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c); - void ltdcFgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c); - uint8_t ltdcFgGetConstantAlphaI(LTDCDriver *ltdcp); - uint8_t ltdcFgGetConstantAlpha(LTDCDriver *ltdcp); - void ltdcFgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a); - void ltdcFgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a); - ltdc_color_t ltdcFgGetDefaultColorI(LTDCDriver *ltdcp); - ltdc_color_t ltdcFgGetDefaultColor(LTDCDriver *ltdcp); - void ltdcFgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c); - void ltdcFgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c); - ltdc_blendf_t ltdcFgGetBlendingFactorsI(LTDCDriver *ltdcp); - ltdc_blendf_t ltdcFgGetBlendingFactors(LTDCDriver *ltdcp); - void ltdcFgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf); - void ltdcFgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf); - void ltdcFgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp); - void ltdcFgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp); - void ltdcFgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp); - void ltdcFgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp); - void ltdcFgSetInvalidWindowI(LTDCDriver *ltdcp); - void ltdcFgSetInvalidWindow(LTDCDriver *ltdcp); - void ltdcFgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep); - void ltdcFgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep); - void ltdcFgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep); - void ltdcFgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep); - void *ltdcFgGetFrameAddressI(LTDCDriver *ltdcp); - void *ltdcFgGetFrameAddress(LTDCDriver *ltdcp); - void ltdcFgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp); - void ltdcFgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp); - void ltdcFgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp); - void ltdcFgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp); - void ltdcFgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp); - void ltdcFgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp); - - /* Helper functions.*/ - size_t ltdcBitsPerPixel(ltdc_pixfmt_t fmt); -#if (TRUE == LTDC_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__) - ltdc_color_t ltdcFromARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt); - ltdc_color_t ltdcToARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt); -#endif /* LTDC_USE_SOFTWARE_CONVERSIONS */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32_LTDC_USE_LTDC */ - -#endif /* _STM32_LTDC_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c deleted file mode 100644 index c04278e..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c +++ /dev/null @@ -1,1176 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Fabio Utzig and - Xo Wang. -*/ -/* - Rewritten by Emil Fresk (1/5 - 2014) for extended input capture - functionality. And fix for spurious callbacks in the interrupt handler. -*/ -/* - Improved by Uladzimir Pylinsky aka barthess (1/3 - 2015) for support of - 32-bit timers and timers with single capture/compare channels. -*/ - -/* - * Hardware Abstraction Layer for Extended Input Capture Unit - */ -#include "hal.h" - -#if (HAL_USE_EICU == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ -/** - * @brief Inverts the polarity for the given channel. - * - * @param[in] eicup Pointer to the EICUDriver object. - * @param[in] channel The timer channel to invert. - * - * @notapi - */ -#define eicu_lld_invert_polarity(eicup, channel) \ - (eicup)->tim->CCER ^= ((uint16_t)(STM32_TIM_CCER_CC1P << ((channel) * 4))) - -/** - * @brief Returns the compare value of the latest cycle. - * - * @param[in] chp Pointer to channel structure that fired the interrupt. - * @return The number of ticks. - * - * @notapi - */ -#define eicu_lld_get_compare(chp) (*((chp)->ccrp) + 1) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EICUD1 driver identifier. - * @note The driver EICUD1 allocates the complex timer TIM1 when enabled. - */ -#if STM32_EICU_USE_TIM1 && !defined(__DOXYGEN__) -EICUDriver EICUD1; -#endif - -/** - * @brief EICUD2 driver identifier. - * @note The driver EICUD2 allocates the timer TIM2 when enabled. - */ -#if STM32_EICU_USE_TIM2 && !defined(__DOXYGEN__) -EICUDriver EICUD2; -#endif - -/** - * @brief EICUD3 driver identifier. - * @note The driver EICUD3 allocates the timer TIM3 when enabled. - */ -#if STM32_EICU_USE_TIM3 && !defined(__DOXYGEN__) -EICUDriver EICUD3; -#endif - -/** - * @brief EICUD4 driver identifier. - * @note The driver EICUD4 allocates the timer TIM4 when enabled. - */ -#if STM32_EICU_USE_TIM4 && !defined(__DOXYGEN__) -EICUDriver EICUD4; -#endif - -/** - * @brief EICUD5 driver identifier. - * @note The driver EICUD5 allocates the timer TIM5 when enabled. - */ -#if STM32_EICU_USE_TIM5 && !defined(__DOXYGEN__) -EICUDriver EICUD5; -#endif - -/** - * @brief EICUD8 driver identifier. - * @note The driver EICUD8 allocates the timer TIM8 when enabled. - */ -#if STM32_EICU_USE_TIM8 && !defined(__DOXYGEN__) -EICUDriver EICUD8; -#endif - -/** - * @brief EICUD9 driver identifier. - * @note The driver EICUD9 allocates the timer TIM9 when enabled. - */ -#if STM32_EICU_USE_TIM9 && !defined(__DOXYGEN__) -EICUDriver EICUD9; -#endif - -/** - * @brief EICUD12 driver identifier. - * @note The driver EICUD12 allocates the timer TIM12 when enabled. - */ -#if STM32_EICU_USE_TIM12 && !defined(__DOXYGEN__) -EICUDriver EICUD12; -#endif - -/** - * @brief EICUD10 driver identifier. - * @note The driver EICUD10 allocates the timer TIM10 when enabled. - */ -#if STM32_EICU_USE_TIM10 && !defined(__DOXYGEN__) -EICUDriver EICUD10; -#endif - -/** - * @brief EICUD11 driver identifier. - * @note The driver EICUD11 allocates the timer TIM11 when enabled. - */ -#if STM32_EICU_USE_TIM11 && !defined(__DOXYGEN__) -EICUDriver EICUD11; -#endif - -/** - * @brief EICUD13 driver identifier. - * @note The driver EICUD13 allocates the timer TIM13 when enabled. - */ -#if STM32_EICU_USE_TIM13 && !defined(__DOXYGEN__) -EICUDriver EICUD13; -#endif - -/** - * @brief EICUD14 driver identifier. - * @note The driver EICUD14 allocates the timer TIM14 when enabled. - */ -#if STM32_EICU_USE_TIM14 && !defined(__DOXYGEN__) -EICUDriver EICUD14; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ -/** - * @brief Returns both pulse width and period. - * @details The time is defined as number of ticks. - * - * @param[in] eicup Pointer to the EICUDriver object. - * @param[in] channel The timer channel that fired the interrupt. - * @param[in] compare Content of the CCR register. - * @return The number of ticks. - * - * @notapi - */ -static eicuresult_t get_time_both(const EICUDriver *eicup, - eicuchannel_t channel, - eicucnt_t compare) { - - const EICUChannel *chp = &eicup->channel[channel]; - eicuresult_t ret; - - /* Note! there is no overflow check because it handles under the hood of - unsigned subtraction math.*/ - - /* 16-bit timer */ - if (EICU_WIDTH_16 == eicup->width) { - uint16_t cmp = compare; - uint16_t la = chp->last_active; - uint16_t li = chp->last_idle; - uint16_t w = li - la; - uint16_t p = cmp - la; - ret.width = w; - ret.period = p; - } - /* 32-bit timer */ - else if (EICU_WIDTH_32 == eicup->width) { - ret.width = chp->last_idle - chp->last_active; - ret.period = compare - chp->last_active; - } - /* error trap */ - else { - osalSysHalt("Unhandled width value"); - } - - return ret; -} - -/** - * @brief Returns pulse width. - * @details The time is defined as number of ticks. - * - * @param[in] eicup Pointer to the EICUDriver object. - * @param[in] channel The timer channel that fired the interrupt. - * @param[in] compare Content of the CCR register. - * @return The number of ticks. - * - * @notapi - */ -static eicucnt_t get_time_width(const EICUDriver *eicup, - eicuchannel_t channel, - eicucnt_t compare) { - - const EICUChannel *chp = &eicup->channel[channel]; - - /* Note! there is no overflow check because it handles under the hood of - unsigned subtraction math.*/ - - /* 16-bit timer */ - if (EICU_WIDTH_16 == eicup->width) { - uint16_t cmp = compare; - uint16_t la = chp->last_active; - uint16_t ret = cmp - la; - return ret; - } - /* 32-bit timer */ - else if (EICU_WIDTH_32 == eicup->width) { - return compare - chp->last_active; - } - /* error trap */ - else { - osalSysHalt("Unhandled width value"); - return 0; - } -} - -/** - * @brief Returns pulse period. - * @details The time is defined as number of ticks. - * - * @param[in] eicup Pointer to the EICUDriver object. - * @param[in] channel The timer channel that fired the interrupt. - * @param[in] compare Content of the CCR register. - * @return The number of ticks. - * - * @notapi - */ -static eicucnt_t get_time_period(const EICUDriver *eicup, - eicuchannel_t channel, - eicucnt_t compare) { - - const EICUChannel *chp = &eicup->channel[channel]; - - /* Note! there is no overflow check because it handles under the hood of - unsigned subtraction math.*/ - - /* 16-bit timer */ - if (EICU_WIDTH_16 == eicup->width) { - uint16_t cmp = compare; - uint16_t li = chp->last_idle; - uint16_t ret = cmp - li; - return ret; - } - /* 32-bit timer */ - else if (EICU_WIDTH_32 == eicup->width) { - return compare - chp->last_idle; - } - /* error trap */ - else { - osalSysHalt("Unhandled width value"); - return 0; - } -} - -/** - * @brief EICU width or (width + period) event. - * @note Needs special care since it needs to invert the - * correct polarity bit to detect pulses. - * @note Assumes that the polarity is not changed by some - * external user. It must only be changed using the HAL. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * @param[in] channel The timer channel that fired the interrupt. - * - * @notapi - */ -static void isr_invoke_pulse_cb(EICUDriver *eicup, eicuchannel_t channel) { - EICUChannel *chp = &eicup->channel[channel]; - eicucnt_t compare = eicu_lld_get_compare(chp); - - if (EICU_CH_ACTIVE == chp->state) { - chp->state = EICU_CH_IDLE; - eicu_lld_invert_polarity(eicup, channel); - if (EICU_INPUT_PULSE == chp->config->mode) { - uint32_t width = get_time_width(eicup, channel, compare); - chp->config->capture_cb(eicup, channel, width, 0); - } - chp->last_idle = compare; - } - else { - chp->state = EICU_CH_ACTIVE; - eicu_lld_invert_polarity(eicup, channel); - if (EICU_INPUT_BOTH == chp->config->mode) { - eicuresult_t both = get_time_both(eicup, channel, compare); - chp->config->capture_cb(eicup, channel, both.width, both.period); - } - chp->last_active = compare; - } -} - -/** - * @brief EICU Edge detect event. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * @param[in] channel The timer channel that fired the interrupt. - * - * @notapi - */ -static void isr_invoke_edge_cb(EICUDriver *eicup, eicuchannel_t channel) { - EICUChannel *chp = &eicup->channel[channel]; - eicucnt_t compare = eicu_lld_get_compare(chp); - uint32_t period = get_time_period(eicup, channel, compare); - - chp->config->capture_cb(eicup, channel, 0, period); - chp->last_idle = compare; -} - -/** - * @brief Common EICU detect call. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * @param[in] channel The timer channel that fired the interrupt. - * - * @notapi - */ -static void eicu_isr_invoke_cb(EICUDriver *eicup, eicuchannel_t channel) { - - if (EICU_INPUT_EDGE == eicup->channel[channel].config->mode) - isr_invoke_edge_cb(eicup, channel); - else /* EICU_INPUT_PULSE || EICU_INPUT_BOTH */ - isr_invoke_pulse_cb(eicup, channel); -} - -/** - * @brief Shared IRQ handler. - * - * @param[in] eicup Pointer to the @p EICUDriver object - */ -static void eicu_lld_serve_interrupt(EICUDriver *eicup) { - uint16_t sr; - sr = eicup->tim->SR; - - /* Pick out the interrupts we are interested in by using - the interrupt enable bits as mask */ - sr &= (eicup->tim->DIER & STM32_TIM_DIER_IRQ_MASK); - - /* Clear interrupts */ - eicup->tim->SR = ~sr; - - if ((sr & STM32_TIM_SR_CC1IF) != 0) - eicu_isr_invoke_cb(eicup, EICU_CHANNEL_1); - if ((sr & STM32_TIM_SR_CC2IF) != 0) - eicu_isr_invoke_cb(eicup, EICU_CHANNEL_2); - if ((sr & STM32_TIM_SR_CC3IF) != 0) - eicu_isr_invoke_cb(eicup, EICU_CHANNEL_3); - if ((sr & STM32_TIM_SR_CC4IF) != 0) - eicu_isr_invoke_cb(eicup, EICU_CHANNEL_4); -} - -/** - * @brief Starts every channel. - * - * @param[in] eicup Pointer to the @p EICUDriver object - */ -static void start_channels(EICUDriver *eicup) { - - /* Set each input channel that is used as: a normal input capture channel, - link the corresponding CCR register and set polarity. */ - - /* Input capture channel 1 */ - if (eicup->config->iccfgp[0] != NULL) { - /* Normal capture input input */ - eicup->tim->CCMR1 |= STM32_TIM_CCMR1_CC1S(1); - - /* Link CCR register */ - eicup->channel[0].ccrp = &eicup->tim->CCR[0]; - - /* Set input polarity */ - if (eicup->config->iccfgp[0]->alvl == EICU_INPUT_ACTIVE_HIGH) - eicup->tim->CCER |= STM32_TIM_CCER_CC1E; - else - eicup->tim->CCER |= STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P; - } - - /* Input capture channel 2 */ - if (eicup->config->iccfgp[1] != NULL) { - /* Normal capture input input */ - eicup->tim->CCMR1 |= STM32_TIM_CCMR1_CC2S(1); - - /* Link CCR register */ - eicup->channel[1].ccrp = &eicup->tim->CCR[1]; - - /* Set input polarity */ - if (eicup->config->iccfgp[1]->alvl == EICU_INPUT_ACTIVE_HIGH) - eicup->tim->CCER |= STM32_TIM_CCER_CC2E; - else - eicup->tim->CCER |= STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P; - } - - /* Input capture channel 3 (not for TIM 9 and 12) */ - if (eicup->config->iccfgp[2] != NULL) { - /* Normal capture input input */ - eicup->tim->CCMR2 |= STM32_TIM_CCMR2_CC3S(1); - - /* Link CCR register */ - eicup->channel[2].ccrp = &eicup->tim->CCR[2]; - - /* Set input polarity */ - if (eicup->config->iccfgp[2]->alvl == EICU_INPUT_ACTIVE_HIGH) - eicup->tim->CCER |= STM32_TIM_CCER_CC3E; - else - eicup->tim->CCER |= STM32_TIM_CCER_CC3E | STM32_TIM_CCER_CC3P; - } - - /* Input capture channel 4 (not for TIM 9 and 12) */ - if (eicup->config->iccfgp[3] != NULL) { - /* Normal capture input input */ - eicup->tim->CCMR2 |= STM32_TIM_CCMR2_CC4S(1); - - /* Link CCR register */ - eicup->channel[3].ccrp = &eicup->tim->CCR[3]; - - /* Set input polarity */ - if (eicup->config->iccfgp[3]->alvl == EICU_INPUT_ACTIVE_HIGH) - eicup->tim->CCER |= STM32_TIM_CCER_CC4E; - else - eicup->tim->CCER |= STM32_TIM_CCER_CC4E | STM32_TIM_CCER_CC4P; - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_EICU_USE_TIM1 -#if !defined(STM32_TIM1_UP_HANDLER) -#error "STM32_TIM1_UP_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD1); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM1_CC_HANDLER) -#error "STM32_TIM1_CC_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM1 */ - -#if STM32_EICU_USE_TIM2 - -#if !defined(STM32_TIM2_HANDLER) -#error "STM32_TIM2_HANDLER not defined" -#endif -/** - * @brief TIM2 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM2 */ - -#if STM32_EICU_USE_TIM3 -#if !defined(STM32_TIM3_HANDLER) -#error "STM32_TIM3_HANDLER not defined" -#endif -/** - * @brief TIM3 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD3); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM3 */ - -#if STM32_EICU_USE_TIM4 -#if !defined(STM32_TIM4_HANDLER) -#error "STM32_TIM4_HANDLER not defined" -#endif -/** - * @brief TIM4 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD4); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM4 */ - -#if STM32_EICU_USE_TIM5 -#if !defined(STM32_TIM5_HANDLER) -#error "STM32_TIM5_HANDLER not defined" -#endif -/** - * @brief TIM5 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD5); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM5 */ - -#if STM32_EICU_USE_TIM8 -#if !defined(STM32_TIM8_UP_HANDLER) -#error "STM32_TIM8_UP_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD8); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM8_CC_HANDLER) -#error "STM32_TIM8_CC_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD8); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM8 */ - -#if STM32_EICU_USE_TIM9 -#if !defined(STM32_TIM9_HANDLER) -#error "STM32_TIM9_HANDLER not defined" -#endif -/** - * @brief TIM9 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD9); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM9 */ - -#if STM32_EICU_USE_TIM12 -#if !defined(STM32_TIM12_HANDLER) -#error "STM32_TIM12_HANDLER not defined" -#endif -/** - * @brief TIM12 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM12_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD12); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM12 */ - -#if STM32_EICU_USE_TIM10 -#if !defined(STM32_TIM10_HANDLER) -#error "STM32_TIM10_HANDLER not defined" -#endif -/** - * @brief TIM10 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM10_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD10); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM10 */ - -#if STM32_EICU_USE_TIM11 -#if !defined(STM32_TIM11_HANDLER) -#error "STM32_TIM11_HANDLER not defined" -#endif -/** - * @brief TIM11 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM11_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD11); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM11 */ - -#if STM32_EICU_USE_TIM13 -#if !defined(STM32_TIM13_HANDLER) -#error "STM32_TIM13_HANDLER not defined" -#endif -/** - * @brief TIM13 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM13_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD13); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM13 */ - -#if STM32_EICU_USE_TIM14 -#if !defined(STM32_TIM14_HANDLER) -#error "STM32_TIM14_HANDLER not defined" -#endif -/** - * @brief TIM14 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_TIM14_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - eicu_lld_serve_interrupt(&EICUD14); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_EICU_USE_TIM14 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level EICU driver initialization. - * - * @notapi - */ -void eicu_lld_init(void) { -#if STM32_EICU_USE_TIM1 - /* Driver initialization.*/ - eicuObjectInit(&EICUD1); - EICUD1.tim = STM32_TIM1; -#endif - -#if STM32_EICU_USE_TIM2 - /* Driver initialization.*/ - eicuObjectInit(&EICUD2); - EICUD2.tim = STM32_TIM2; -#endif - -#if STM32_EICU_USE_TIM3 - /* Driver initialization.*/ - eicuObjectInit(&EICUD3); - EICUD3.tim = STM32_TIM3; -#endif - -#if STM32_EICU_USE_TIM4 - /* Driver initialization.*/ - eicuObjectInit(&EICUD4); - EICUD4.tim = STM32_TIM4; -#endif - -#if STM32_EICU_USE_TIM5 - /* Driver initialization.*/ - eicuObjectInit(&EICUD5); - EICUD5.tim = STM32_TIM5; -#endif - -#if STM32_EICU_USE_TIM8 - /* Driver initialization.*/ - eicuObjectInit(&EICUD8); - EICUD8.tim = STM32_TIM8; -#endif - -#if STM32_EICU_USE_TIM9 - /* Driver initialization.*/ - eicuObjectInit(&EICUD9); - EICUD9.tim = STM32_TIM9; -#endif - -#if STM32_EICU_USE_TIM12 - /* Driver initialization.*/ - eicuObjectInit(&EICUD12); - EICUD12.tim = STM32_TIM12; -#endif - -#if STM32_EICU_USE_TIM10 - /* Driver initialization.*/ - eicuObjectInit(&EICUD10); - EICUD10.tim = STM32_TIM10; -#endif - -#if STM32_EICU_USE_TIM11 - /* Driver initialization.*/ - eicuObjectInit(&EICUD11); - EICUD11.tim = STM32_TIM11; -#endif - -#if STM32_EICU_USE_TIM13 - /* Driver initialization.*/ - eicuObjectInit(&EICUD13); - EICUD13.tim = STM32_TIM13; -#endif - -#if STM32_EICU_USE_TIM14 - /* Driver initialization.*/ - eicuObjectInit(&EICUD14); - EICUD14.tim = STM32_TIM14; -#endif -} - -/** - * @brief Configures and activates the EICU peripheral. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @notapi - */ -void eicu_lld_start(EICUDriver *eicup) { - uint32_t psc; - size_t ch; - - osalDbgAssert((eicup->config->iccfgp[0] != NULL) || - (eicup->config->iccfgp[1] != NULL) || - (eicup->config->iccfgp[2] != NULL) || - (eicup->config->iccfgp[3] != NULL), - "invalid input configuration"); - - if (eicup->state == EICU_STOP) { - /* Clock activation and timer reset.*/ -#if STM32_EICU_USE_TIM1 - if (&EICUD1 == eicup) { - rccEnableTIM1(FALSE); - rccResetTIM1(); - nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_EICU_TIM1_IRQ_PRIORITY); - nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_EICU_TIM1_IRQ_PRIORITY); - eicup->channels = 4; -#if defined(STM32_TIM1CLK) - eicup->clock = STM32_TIM1CLK; -#else - eicup->clock = STM32_TIMCLK2; -#endif - } -#endif -#if STM32_EICU_USE_TIM2 - if (&EICUD2 == eicup) { - rccEnableTIM2(FALSE); - rccResetTIM2(); - nvicEnableVector(STM32_TIM2_NUMBER, STM32_EICU_TIM2_IRQ_PRIORITY); - eicup->channels = 4; - eicup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_EICU_USE_TIM3 - if (&EICUD3 == eicup) { - rccEnableTIM3(FALSE); - rccResetTIM3(); - nvicEnableVector(STM32_TIM3_NUMBER, STM32_EICU_TIM3_IRQ_PRIORITY); - eicup->channels = 4; - eicup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_EICU_USE_TIM4 - if (&EICUD4 == eicup) { - rccEnableTIM4(FALSE); - rccResetTIM4(); - nvicEnableVector(STM32_TIM4_NUMBER, STM32_EICU_TIM4_IRQ_PRIORITY); - eicup->channels = 4; - eicup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_EICU_USE_TIM5 - if (&EICUD5 == eicup) { - rccEnableTIM5(FALSE); - rccResetTIM5(); - nvicEnableVector(STM32_TIM5_NUMBER, STM32_EICU_TIM5_IRQ_PRIORITY); - eicup->channels = 4; - eicup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_EICU_USE_TIM8 - if (&EICUD8 == eicup) { - rccEnableTIM8(FALSE); - rccResetTIM8(); - nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_EICU_TIM8_IRQ_PRIORITY); - nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_EICU_TIM8_IRQ_PRIORITY); - eicup->channels = 4; -#if defined(STM32_TIM8CLK) - eicup->clock = STM32_TIM8CLK; -#else - eicup->clock = STM32_TIMCLK2; -#endif - } -#endif -#if STM32_EICU_USE_TIM9 - if (&EICUD9 == eicup) { - rccEnableTIM9(FALSE); - rccResetTIM9(); - nvicEnableVector(STM32_TIM9_NUMBER, STM32_EICU_TIM9_IRQ_PRIORITY); - eicup->channels = 2; - eicup->clock = STM32_TIMCLK2; - } -#endif -#if STM32_EICU_USE_TIM12 - if (&EICUD12 == eicup) { - rccEnableTIM12(FALSE); - rccResetTIM12(); - nvicEnableVector(STM32_TIM12_NUMBER, STM32_EICU_TIM12_IRQ_PRIORITY); - eicup->channels = 2; - eicup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_EICU_USE_TIM10 - if (&EICUD10 == eicup) { - rccEnableTIM10(FALSE); - rccResetTIM10(); - nvicEnableVector(STM32_TIM10_NUMBER, STM32_EICU_TIM10_IRQ_PRIORITY); - eicup->channels = 1; - eicup->clock = STM32_TIMCLK2; - } -#endif -#if STM32_EICU_USE_TIM11 - if (&EICUD11 == eicup) { - rccEnableTIM11(FALSE); - rccResetTIM11(); - nvicEnableVector(STM32_TIM11_NUMBER, STM32_EICU_TIM11_IRQ_PRIORITY); - eicup->channels = 1; - eicup->clock = STM32_TIMCLK2; - } -#endif -#if STM32_EICU_USE_TIM13 - if (&EICUD13 == eicup) { - rccEnableTIM13(FALSE); - rccResetTIM13(); - nvicEnableVector(STM32_TIM13_NUMBER, STM32_EICU_TIM13_IRQ_PRIORITY); - eicup->channels = 1; - eicup->clock = STM32_TIMCLK1; - } -#endif -#if STM32_EICU_USE_TIM14 - if (&EICUD14 == eicup) { - rccEnableTIM14(FALSE); - rccResetTIM14(); - nvicEnableVector(STM32_TIM14_NUMBER, STM32_EICU_TIM14_IRQ_PRIORITY); - eicup->channels = 1; - eicup->clock = STM32_TIMCLK1; - } -#endif - } - else { - /* Driver re-configuration scenario, it must be stopped first.*/ - eicup->tim->CR1 = 0; /* Timer disabled. */ - eicup->tim->DIER = eicup->config->dier &/* DMA-related DIER settings. */ - ~STM32_TIM_DIER_IRQ_MASK; - eicup->tim->SR = 0; /* Clear eventual pending IRQs. */ - eicup->tim->CCR[0] = 0; /* Comparator 1 disabled. */ - eicup->tim->CCR[1] = 0; /* Comparator 2 disabled. */ - eicup->tim->CNT = 0; /* Counter reset to zero. */ - } - - /* Timer configuration.*/ - psc = (eicup->clock / eicup->config->frequency) - 1; - chDbgAssert((psc <= 0xFFFF) && - ((psc + 1) * eicup->config->frequency) == eicup->clock, - "invalid frequency"); - eicup->tim->PSC = (uint16_t)psc; - eicup->tim->ARR = (eicucnt_t)-1; - - /* Detect width.*/ - if (0xFFFFFFFF == eicup->tim->ARR) - eicup->width = EICU_WIDTH_32; - else if (0xFFFF == eicup->tim->ARR) - eicup->width = EICU_WIDTH_16; - else - osalSysHalt("Unsupported width"); - - /* Reset registers */ - eicup->tim->SMCR = 0; - eicup->tim->CCMR1 = 0; - if (eicup->channels > 2) - eicup->tim->CCMR2 = 0; - - /* clean channel structures and set pointers to channel configs */ - for (ch=0; ch<EICU_CHANNEL_ENUM_END; ch++) { - eicup->channel[ch].last_active = 0; - eicup->channel[ch].last_idle = 0; - eicup->channel[ch].config = eicup->config->iccfgp[ch]; - eicup->channel[ch].state = EICU_CH_IDLE; - } - - /* TIM9 and TIM12 have only 2 channels.*/ - if (eicup->channels == 2) { - osalDbgCheck((eicup->config->iccfgp[2] == NULL) && - (eicup->config->iccfgp[3] == NULL)); - } - - /* TIM10, TIM11, TIM13 and TIM14 have only 1 channel.*/ - if (eicup->channels == 1) { - osalDbgCheck((eicup->config->iccfgp[1] == NULL) && - (eicup->config->iccfgp[2] == NULL) && - (eicup->config->iccfgp[3] == NULL)); - } - - start_channels(eicup); -} - -/** - * @brief Deactivates the EICU peripheral. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @notapi - */ -void eicu_lld_stop(EICUDriver *eicup) { - - if (eicup->state == EICU_READY) { - - /* Clock deactivation.*/ - eicup->tim->CR1 = 0; /* Timer disabled. */ - eicup->tim->DIER = 0; /* All IRQs disabled. */ - eicup->tim->SR = 0; /* Clear eventual pending IRQs. */ - -#if STM32_EICU_USE_TIM1 - if (&EICUD1 == eicup) { - nvicDisableVector(STM32_TIM1_UP_NUMBER); - nvicDisableVector(STM32_TIM1_CC_NUMBER); - rccDisableTIM1(FALSE); - } -#endif -#if STM32_EICU_USE_TIM2 - if (&EICUD2 == eicup) { - nvicDisableVector(STM32_TIM2_NUMBER); - rccDisableTIM2(FALSE); - } -#endif -#if STM32_EICU_USE_TIM3 - if (&EICUD3 == eicup) { - nvicDisableVector(STM32_TIM3_NUMBER); - rccDisableTIM3(FALSE); - } -#endif -#if STM32_EICU_USE_TIM4 - if (&EICUD4 == eicup) { - nvicDisableVector(STM32_TIM4_NUMBER); - rccDisableTIM4(FALSE); - } -#endif -#if STM32_EICU_USE_TIM5 - if (&EICUD5 == eicup) { - nvicDisableVector(STM32_TIM5_NUMBER); - rccDisableTIM5(FALSE); - } -#endif -#if STM32_EICU_USE_TIM8 - if (&EICUD8 == eicup) { - nvicDisableVector(STM32_TIM8_UP_NUMBER); - nvicDisableVector(STM32_TIM8_CC_NUMBER); - rccDisableTIM8(FALSE); - } -#endif -#if STM32_EICU_USE_TIM9 - if (&EICUD9 == eicup) { - nvicDisableVector(STM32_TIM9_NUMBER); - rccDisableTIM9(FALSE); - } -#endif -#if STM32_EICU_USE_TIM12 - if (&EICUD12 == eicup) { - nvicDisableVector(STM32_TIM12_NUMBER); - rccDisableTIM12(FALSE); - } -#endif - } -#if STM32_EICU_USE_TIM10 - if (&EICUD10 == eicup) { - nvicDisableVector(STM32_TIM10_NUMBER); - rccDisableTIM10(FALSE); - } -#endif -#if STM32_EICU_USE_TIM11 - if (&EICUD11 == eicup) { - nvicDisableVector(STM32_TIM11_NUMBER); - rccDisableTIM11(FALSE); - } -#endif -#if STM32_EICU_USE_TIM13 - if (&EICUD13 == eicup) { - nvicDisableVector(STM32_TIM13_NUMBER); - rccDisableTIM13(FALSE); - } -#endif -#if STM32_EICU_USE_TIM14 - if (&EICUD14 == eicup) { - nvicDisableVector(STM32_TIM14_NUMBER); - rccDisableTIM14(FALSE); - } -#endif -} - -/** - * @brief Enables the EICU. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @notapi - */ -void eicu_lld_enable(EICUDriver *eicup) { - - eicup->tim->EGR = STM32_TIM_EGR_UG; - eicup->tim->SR = 0; /* Clear pending IRQs (if any). */ - - if ((eicup->config->iccfgp[EICU_CHANNEL_1] != NULL) && - (eicup->config->iccfgp[EICU_CHANNEL_1]->capture_cb != NULL)) - eicup->tim->DIER |= STM32_TIM_DIER_CC1IE; - if ((eicup->config->iccfgp[EICU_CHANNEL_2] != NULL) && - (eicup->config->iccfgp[EICU_CHANNEL_2]->capture_cb != NULL)) - eicup->tim->DIER |= STM32_TIM_DIER_CC2IE; - if ((eicup->config->iccfgp[EICU_CHANNEL_3] != NULL) && - (eicup->config->iccfgp[EICU_CHANNEL_3]->capture_cb != NULL)) - eicup->tim->DIER |= STM32_TIM_DIER_CC3IE; - if ((eicup->config->iccfgp[EICU_CHANNEL_4] != NULL) && - (eicup->config->iccfgp[EICU_CHANNEL_4]->capture_cb != NULL)) - eicup->tim->DIER |= STM32_TIM_DIER_CC4IE; - - eicup->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; -} - -/** - * @brief Disables the EICU. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @notapi - */ -void eicu_lld_disable(EICUDriver *eicup) { - eicup->tim->CR1 = 0; /* Initially stopped. */ - eicup->tim->SR = 0; /* Clear pending IRQs (if any). */ - - /* All interrupts disabled.*/ - eicup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK; -} - -#endif /* HAL_USE_EICU */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h deleted file mode 100644 index 927eb6f..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h +++ /dev/null @@ -1,554 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Rewritten by Emil Fresk (1/5 - 2014) for extended input capture - functionality. And fix for spurious callbacks in the interrupt handler. -*/ -/* - Improved by Uladzimir Pylinsky aka barthess (1/3 - 2015) for support of - 32-bit timers and timers with single capture/compare channels. -*/ - -#ifndef __EICU_LLD_H -#define __EICU_LLD_H - -#include "stm32_tim.h" - -#if (HAL_USE_EICU == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EICUD1 driver enable switch. - * @details If set to @p TRUE the support for EICUD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM1) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM1 FALSE -#endif - -/** - * @brief EICUD2 driver enable switch. - * @details If set to @p TRUE the support for EICUD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM2) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM2 FALSE -#endif - -/** - * @brief EICUD3 driver enable switch. - * @details If set to @p TRUE the support for EICUD3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM3) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM3 FALSE -#endif - -/** - * @brief EICUD4 driver enable switch. - * @details If set to @p TRUE the support for EICUD4 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM4) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM4 FALSE -#endif - -/** - * @brief EICUD5 driver enable switch. - * @details If set to @p TRUE the support for EICUD5 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM5) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM5 FALSE -#endif - -/** - * @brief EICUD8 driver enable switch. - * @details If set to @p TRUE the support for EICUD8 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM8) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM8 FALSE -#endif - -/** - * @brief EICUD9 driver enable switch. - * @details If set to @p TRUE the support for EICUD9 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM9) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM9 FALSE -#endif - -/** - * @brief EICUD12 driver enable switch. - * @details If set to @p TRUE the support for EICUD12 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_EICU_USE_TIM12) || defined(__DOXYGEN__) -#define STM32_EICU_USE_TIM12 FALSE -#endif - -/** - * @brief EICUD1 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM1_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD2 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM2_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD3 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM3_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD4 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM4_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD5 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM5_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD8 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM8_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD9 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM9_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD12 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM12_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD10 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM10_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM10_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD11 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM11_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD13 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM13_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM13_IRQ_PRIORITY 7 -#endif - -/** - * @brief EICUD14 interrupt priority level setting. - */ -#if !defined(STM32_EICU_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EICU_TIM14_IRQ_PRIORITY 7 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_EICU_USE_TIM1 && !STM32_HAS_TIM1 -#error "TIM1 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM2 && !STM32_HAS_TIM2 -#error "TIM2 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM3 && !STM32_HAS_TIM3 -#error "TIM3 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM4 && !STM32_HAS_TIM4 -#error "TIM4 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM5 && !STM32_HAS_TIM5 -#error "TIM5 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM8 && !STM32_HAS_TIM8 -#error "TIM8 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM9 && !STM32_HAS_TIM9 -#error "TIM9 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM12 && !STM32_HAS_TIM12 -#error "TIM12 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM10 && !STM32_HAS_TIM10 -#error "TIM10 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM11 && !STM32_HAS_TIM11 -#error "TIM11 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM13 && !STM32_HAS_TIM13 -#error "TIM13 not present in the selected device" -#endif - -#if STM32_EICU_USE_TIM14 && !STM32_HAS_TIM14 -#error "TIM14 not present in the selected device" -#endif - -#if !STM32_EICU_USE_TIM1 && !STM32_EICU_USE_TIM2 && \ - !STM32_EICU_USE_TIM3 && !STM32_EICU_USE_TIM4 && \ - !STM32_EICU_USE_TIM5 && !STM32_EICU_USE_TIM8 && \ - !STM32_EICU_USE_TIM9 && !STM32_EICU_USE_TIM12 && \ - !STM32_EICU_USE_TIM10 && !STM32_EICU_USE_TIM11 && \ - !STM32_EICU_USE_TIM13 && !STM32_EICU_USE_TIM14 -#error "EICU driver activated but no TIM peripheral assigned" -#endif - -#if STM32_EICU_USE_TIM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM1" -#endif - -#if STM32_EICU_USE_TIM2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM2" -#endif - -#if STM32_EICU_USE_TIM3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM3" -#endif - -#if STM32_EICU_USE_TIM4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM4" -#endif - -#if STM32_EICU_USE_TIM5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM5" -#endif - -#if STM32_EICU_USE_TIM8 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM8" -#endif - -#if STM32_EICU_USE_TIM9 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM9_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM9" -#endif - -#if STM32_EICU_USE_TIM12 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM12_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM12" -#endif - -#if STM32_EICU_USE_TIM10 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM10_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM10" -#endif - -#if STM32_EICU_USE_TIM11 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM11_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM11" -#endif - -#if STM32_EICU_USE_TIM13 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM13_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM13" -#endif - -#if STM32_EICU_USE_TIM14 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM14_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM14" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -/** - * @brief Active level selector. - */ -typedef enum { - EICU_INPUT_ACTIVE_HIGH, /**< Trigger on rising edge. */ - EICU_INPUT_ACTIVE_LOW, /**< Trigger on falling edge. */ -} eicuactivelevel_t; - -/** - * @brief Input type selector. - */ -typedef enum { - /** - * @brief Measures time between consequent edges. - * @details Callback fires on every _active_ edge. - */ - EICU_INPUT_EDGE, - /** - * @brief Measures pulse width. - * @details Callback fires on _idle_ edge of pulse. - */ - EICU_INPUT_PULSE, - /** - * @brief Measures both period and width.. - * @details Callback fires on _active_ edge of pulse. - */ - EICU_INPUT_BOTH -} eicucapturemode_t; - -/** - * @brief Timer registers width in bits. - */ -typedef enum { - EICU_WIDTH_16, - EICU_WIDTH_32 -} eicutimerwidth_t; - -/** - * @brief EICU frequency type. - */ -typedef uint32_t eicufreq_t; - -/** - * @brief EICU counter type. - */ -typedef uint32_t eicucnt_t; - -/** - * @brief EICU captured width and (or) period. - */ -typedef struct { - /** - * @brief Pulse width. - */ - eicucnt_t width; - /** - * @brief Pulse period. - */ - eicucnt_t period; -} eicuresult_t; - -/** - * @brief EICU Capture Channel Config structure definition. - */ -typedef struct { - /** - * @brief Specifies the active level of the input signal. - */ - eicuactivelevel_t alvl; - /** - * @brief Specifies the channel capture mode. - */ - eicucapturemode_t mode; - /** - * @brief Capture event callback. Used for PWM width, pulse width and - * pulse period capture event. - */ - eicucallback_t capture_cb; -} EICUChannelConfig; - -/** - * @brief EICU Capture Channel structure definition. - */ -typedef struct { - /** - * @brief Channel state for the internal state machine. - */ - eicuchannelstate_t state; - /** - * @brief Cached value for pulse width calculation. - */ - eicucnt_t last_active; - /** - * @brief Cached value for period calculation. - */ - eicucnt_t last_idle; - /** - * @brief Pointer to Input Capture channel configuration. - */ - const EICUChannelConfig *config; - /** - * @brief CCR register pointer for faster access. - */ - volatile uint32_t *ccrp; -} EICUChannel; - -/** - * @brief EICU Config structure definition. - */ -typedef struct { - /** - * @brief Specifies the Timer clock in Hz. - */ - eicufreq_t frequency; - /** - * @brief Pointer to each Input Capture channel configuration. - * @note A NULL parameter indicates the channel as unused. - * @note In PWM mode, only Channel 1 OR Channel 2 may be used. - */ - const EICUChannelConfig *iccfgp[EICU_CHANNEL_ENUM_END]; - /** - * @brief TIM DIER register initialization data. - */ - uint32_t dier; -} EICUConfig; - -/** - * @brief EICU Driver structure definition - */ -struct EICUDriver { - /** - * @brief STM32 timer peripheral for Input Capture. - */ - stm32_tim_t *tim; - /** - * @brief Driver state for the internal state machine. - */ - eicustate_t state; - /** - * @brief Channels' data structures. - */ - EICUChannel channel[EICU_CHANNEL_ENUM_END]; - /** - * @brief Timer base clock. - */ - uint32_t clock; - /** - * @brief Number of available capture compare channels in timer. - */ - size_t channels; - /** - * @brief Timer registers width in bits. - */ - eicutimerwidth_t width; - /** - * @brief Pointer to configuration for the driver. - */ - const EICUConfig *config; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ -#if STM32_EICU_USE_TIM1 && !defined(__DOXYGEN__) -extern EICUDriver EICUD1; -#endif - -#if STM32_EICU_USE_TIM2 && !defined(__DOXYGEN__) -extern EICUDriver EICUD2; -#endif - -#if STM32_EICU_USE_TIM3 && !defined(__DOXYGEN__) -extern EICUDriver EICUD3; -#endif - -#if STM32_EICU_USE_TIM4 && !defined(__DOXYGEN__) -extern EICUDriver EICUD4; -#endif - -#if STM32_EICU_USE_TIM5 && !defined(__DOXYGEN__) -extern EICUDriver EICUD5; -#endif - -#if STM32_EICU_USE_TIM8 && !defined(__DOXYGEN__) -extern EICUDriver EICUD8; -#endif - -#if STM32_EICU_USE_TIM9 && !defined(__DOXYGEN__) -extern EICUDriver EICUD9; -#endif - -#if STM32_EICU_USE_TIM12 && !defined(__DOXYGEN__) -extern EICUDriver EICUD12; -#endif - -#if STM32_EICU_USE_TIM10 && !defined(__DOXYGEN__) -extern EICUDriver EICUD10; -#endif - -#if STM32_EICU_USE_TIM11 && !defined(__DOXYGEN__) -extern EICUDriver EICUD11; -#endif - -#if STM32_EICU_USE_TIM13 && !defined(__DOXYGEN__) -extern EICUDriver EICUD13; -#endif - -#if STM32_EICU_USE_TIM14 && !defined(__DOXYGEN__) -extern EICUDriver EICUD14; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void eicu_lld_init(void); - void eicu_lld_start(EICUDriver *eicup); - void eicu_lld_stop(EICUDriver *eicup); - void eicu_lld_enable(EICUDriver *eicup); - void eicu_lld_disable(EICUDriver *eicup); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EICU */ - -#endif /* __EICU_LLD_H */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c deleted file mode 100644 index ea051f7..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c +++ /dev/null @@ -1,293 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2016 Martino Migliavacca
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file TIMv1/hal_qei_lld.c
- * @brief STM32 QEI subsystem low level driver header.
- *
- * @addtogroup QEI
- * @{
- */
-
-#include "hal.h"
-
-#if (HAL_USE_QEI == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief QEID1 driver identifier.
- * @note The driver QEID1 allocates the complex timer TIM1 when enabled.
- */
-#if STM32_QEI_USE_TIM1 || defined(__DOXYGEN__)
-QEIDriver QEID1;
-#endif
-
-/**
- * @brief QEID2 driver identifier.
- * @note The driver QEID1 allocates the timer TIM2 when enabled.
- */
-#if STM32_QEI_USE_TIM2 || defined(__DOXYGEN__)
-QEIDriver QEID2;
-#endif
-
-/**
- * @brief QEID3 driver identifier.
- * @note The driver QEID1 allocates the timer TIM3 when enabled.
- */
-#if STM32_QEI_USE_TIM3 || defined(__DOXYGEN__)
-QEIDriver QEID3;
-#endif
-
-/**
- * @brief QEID4 driver identifier.
- * @note The driver QEID4 allocates the timer TIM4 when enabled.
- */
-#if STM32_QEI_USE_TIM4 || defined(__DOXYGEN__)
-QEIDriver QEID4;
-#endif
-
-/**
- * @brief QEID5 driver identifier.
- * @note The driver QEID5 allocates the timer TIM5 when enabled.
- */
-#if STM32_QEI_USE_TIM5 || defined(__DOXYGEN__)
-QEIDriver QEID5;
-#endif
-
-/**
- * @brief QEID8 driver identifier.
- * @note The driver QEID8 allocates the timer TIM8 when enabled.
- */
-#if STM32_QEI_USE_TIM8 || defined(__DOXYGEN__)
-QEIDriver QEID8;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level QEI driver initialization.
- *
- * @notapi
- */
-void qei_lld_init(void) {
-
-#if STM32_QEI_USE_TIM1
- /* Driver initialization.*/
- qeiObjectInit(&QEID1);
- QEID1.tim = STM32_TIM1;
-#endif
-
-#if STM32_QEI_USE_TIM2
- /* Driver initialization.*/
- qeiObjectInit(&QEID2);
- QEID2.tim = STM32_TIM2;
-#endif
-
-#if STM32_QEI_USE_TIM3
- /* Driver initialization.*/
- qeiObjectInit(&QEID3);
- QEID3.tim = STM32_TIM3;
-#endif
-
-#if STM32_QEI_USE_TIM4
- /* Driver initialization.*/
- qeiObjectInit(&QEID4);
- QEID4.tim = STM32_TIM4;
-#endif
-
-#if STM32_QEI_USE_TIM5
- /* Driver initialization.*/
- qeiObjectInit(&QEID5);
- QEID5.tim = STM32_TIM5;
-#endif
-
-#if STM32_QEI_USE_TIM8
- /* Driver initialization.*/
- qeiObjectInit(&QEID8);
- QEID8.tim = STM32_TIM8;
-#endif
-}
-
-/**
- * @brief Configures and activates the QEI peripheral.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- *
- * @notapi
- */
-void qei_lld_start(QEIDriver *qeip) {
-
- if (qeip->state == QEI_STOP) {
- /* Clock activation and timer reset.*/
-#if STM32_QEI_USE_TIM1
- if (&QEID1 == qeip) {
- rccEnableTIM1(FALSE);
- rccResetTIM1();
- }
-#endif
-#if STM32_QEI_USE_TIM2
- if (&QEID2 == qeip) {
- rccEnableTIM2(FALSE);
- rccResetTIM2();
- }
-#endif
-#if STM32_QEI_USE_TIM3
- if (&QEID3 == qeip) {
- rccEnableTIM3(FALSE);
- rccResetTIM3();
- }
-#endif
-#if STM32_QEI_USE_TIM4
- if (&QEID4 == qeip) {
- rccEnableTIM4(FALSE);
- rccResetTIM4();
- }
-#endif
-
-#if STM32_QEI_USE_TIM5
- if (&QEID5 == qeip) {
- rccEnableTIM5(FALSE);
- rccResetTIM5();
- }
-#endif
-#if STM32_QEI_USE_TIM8
- if (&QEID8 == qeip) {
- rccEnableTIM8(FALSE);
- rccResetTIM8();
- }
-#endif
- }
- /* Timer configuration.*/
- qeip->tim->CR1 = 0; /* Initially stopped. */
- qeip->tim->CR2 = 0;
- qeip->tim->PSC = 0;
- qeip->tim->DIER = 0;
- qeip->tim->ARR = 0xFFFF;
-
- /* Set Capture Compare 1 and Capture Compare 2 as input. */
- qeip->tim->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
-
- if (qeip->config->mode == QEI_MODE_QUADRATURE) {
- if (qeip->config->resolution == QEI_BOTH_EDGES)
- qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;
- else
- qeip->tim->SMCR = TIM_SMCR_SMS_0;
- } else {
- /* Direction/Clock mode.
- * Direction input on TI1, Clock input on TI2. */
- qeip->tim->SMCR = TIM_SMCR_SMS_0;
- }
-
- if (qeip->config->dirinv == QEI_DIRINV_TRUE)
- qeip->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC2E;
- else
- qeip->tim->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E;
-}
-
-/**
- * @brief Deactivates the QEI peripheral.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- *
- * @notapi
- */
-void qei_lld_stop(QEIDriver *qeip) {
-
- if (qeip->state == QEI_READY) {
- qeip->tim->CR1 = 0; /* Timer disabled. */
-
- /* Clock deactivation.*/
-#if STM32_QEI_USE_TIM1
- if (&QEID1 == qeip) {
- rccDisableTIM1(FALSE);
- }
-#endif
-#if STM32_QEI_USE_TIM2
- if (&QEID2 == qeip) {
- rccDisableTIM2(FALSE);
- }
-#endif
-#if STM32_QEI_USE_TIM3
- if (&QEID3 == qeip) {
- rccDisableTIM3(FALSE);
- }
-#endif
-#if STM32_QEI_USE_TIM4
- if (&QEID4 == qeip) {
- rccDisableTIM4(FALSE);
- }
-#endif
-#if STM32_QEI_USE_TIM5
- if (&QEID5 == qeip) {
- rccDisableTIM5(FALSE);
- }
-#endif
- }
-#if STM32_QEI_USE_TIM8
- if (&QEID8 == qeip) {
- rccDisableTIM8(FALSE);
- }
-#endif
-}
-
-/**
- * @brief Enables the input capture.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- *
- * @notapi
- */
-void qei_lld_enable(QEIDriver *qeip) {
-
- qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */
-}
-
-/**
- * @brief Disables the input capture.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- *
- * @notapi
- */
-void qei_lld_disable(QEIDriver *qeip) {
-
- qeip->tim->CR1 = 0; /* Timer disabled. */
-}
-
-#endif /* HAL_USE_QEI */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h deleted file mode 100644 index d0cb683..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h +++ /dev/null @@ -1,347 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2016 Martino Migliavacca
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file TIMv1/hal_qei_lld.h
- * @brief STM32 QEI subsystem low level driver header.
- *
- * @addtogroup QEI
- * @{
- */
-
-#ifndef HAL_QEI_LLD_H
-#define HAL_QEI_LLD_H
-
-#if (HAL_USE_QEI == TRUE) || defined(__DOXYGEN__)
-
-#include "stm32_tim.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief QEID1 driver enable switch.
- * @details If set to @p TRUE the support for QEID1 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(STM32_QEI_USE_TIM1) || defined(__DOXYGEN__)
-#define STM32_QEI_USE_TIM1 FALSE
-#endif
-
-/**
- * @brief QEID2 driver enable switch.
- * @details If set to @p TRUE the support for QEID2 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(STM32_QEI_USE_TIM2) || defined(__DOXYGEN__)
-#define STM32_QEI_USE_TIM2 FALSE
-#endif
-
-/**
- * @brief QEID3 driver enable switch.
- * @details If set to @p TRUE the support for QEID3 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(STM32_QEI_USE_TIM3) || defined(__DOXYGEN__)
-#define STM32_QEI_USE_TIM3 FALSE
-#endif
-
-/**
- * @brief QEID4 driver enable switch.
- * @details If set to @p TRUE the support for QEID4 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(STM32_QEI_USE_TIM4) || defined(__DOXYGEN__)
-#define STM32_QEI_USE_TIM4 FALSE
-#endif
-
-/**
- * @brief QEID5 driver enable switch.
- * @details If set to @p TRUE the support for QEID5 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(STM32_QEI_USE_TIM5) || defined(__DOXYGEN__)
-#define STM32_QEI_USE_TIM5 FALSE
-#endif
-
-/**
- * @brief QEID8 driver enable switch.
- * @details If set to @p TRUE the support for QEID8 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(STM32_QEI_USE_TIM8) || defined(__DOXYGEN__)
-#define STM32_QEI_USE_TIM8 FALSE
-#endif
-
-/**
- * @brief QEID1 interrupt priority level setting.
- */
-#if !defined(STM32_QEI_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_QEI_TIM1_IRQ_PRIORITY 7
-#endif
-
-/**
- * @brief QEID2 interrupt priority level setting.
- */
-#if !defined(STM32_QEI_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_QEI_TIM2_IRQ_PRIORITY 7
-#endif
-
-/**
- * @brief QEID3 interrupt priority level setting.
- */
-#if !defined(STM32_QEI_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_QEI_TIM3_IRQ_PRIORITY 7
-#endif
-
-/**
- * @brief QEID4 interrupt priority level setting.
- */
-#if !defined(STM32_QEI_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_QEI_TIM4_IRQ_PRIORITY 7
-#endif
-
-/**
- * @brief QEID5 interrupt priority level setting.
- */
-#if !defined(STM32_QEI_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_QEI_TIM5_IRQ_PRIORITY 7
-#endif
-
-/**
- * @brief QEID8 interrupt priority level setting.
- */
-#if !defined(STM32_QEI_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_QEI_TIM8_IRQ_PRIORITY 7
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if STM32_QEI_USE_TIM1 && !STM32_HAS_TIM1
-#error "TIM1 not present in the selected device"
-#endif
-
-#if STM32_QEI_USE_TIM2 && !STM32_HAS_TIM2
-#error "TIM2 not present in the selected device"
-#endif
-
-#if STM32_QEI_USE_TIM3 && !STM32_HAS_TIM3
-#error "TIM3 not present in the selected device"
-#endif
-
-#if STM32_QEI_USE_TIM4 && !STM32_HAS_TIM4
-#error "TIM4 not present in the selected device"
-#endif
-
-#if STM32_QEI_USE_TIM5 && !STM32_HAS_TIM5
-#error "TIM5 not present in the selected device"
-#endif
-
-#if STM32_QEI_USE_TIM8 && !STM32_HAS_TIM8
-#error "TIM8 not present in the selected device"
-#endif
-
-#if !STM32_QEI_USE_TIM1 && !STM32_QEI_USE_TIM2 && \
- !STM32_QEI_USE_TIM3 && !STM32_QEI_USE_TIM4 && \
- !STM32_QEI_USE_TIM5 && !STM32_QEI_USE_TIM8
-#error "QEI driver activated but no TIM peripheral assigned"
-#endif
-
-#if STM32_QEI_USE_TIM1 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM1"
-#endif
-
-#if STM32_QEI_USE_TIM2 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM2"
-#endif
-
-#if STM32_QEI_USE_TIM3 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM3"
-#endif
-
-#if STM32_QEI_USE_TIM4 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM4_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM4"
-#endif
-
-#if STM32_QEI_USE_TIM5 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM5_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM5"
-#endif
-
-#if STM32_QEI_USE_TIM8 && \
- !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM8_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to TIM8"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief QEI count mode.
- */
-typedef enum {
- QEI_MODE_QUADRATURE = 0, /**< Quadrature encoder mode. */
- QEI_MODE_DIRCLOCK = 1, /**< Direction/Clock mode. */
-} qeimode_t;
-
-/**
- * @brief QEI resolution.
- */
-typedef enum {
- QEI_SINGLE_EDGE = 0, /**< Count only on edges from first channel. */
- QEI_BOTH_EDGES = 1, /**< Count on both edges (resolution doubles).*/
-} qeiresolution_t;
-
-/**
- * @brief QEI direction inversion.
- */
-typedef enum {
- QEI_DIRINV_FALSE = 0, /**< Do not invert counter direction. */
- QEI_DIRINV_TRUE = 1, /**< Invert counter direction. */
-} qeidirinv_t;
-
-/**
- * @brief QEI counter type.
- */
-typedef uint16_t qeicnt_t;
-
-/**
- * @brief QEI delta type.
- */
-typedef int32_t qeidelta_t;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief Count mode.
- */
- qeimode_t mode;
- /**
- * @brief Resolution.
- */
- qeiresolution_t resolution;
- /**
- * @brief Direction inversion.
- */
- qeidirinv_t dirinv;
- /* End of the mandatory fields.*/
-} QEIConfig;
-
-/**
- * @brief Structure representing an QEI driver.
- */
-struct QEIDriver {
- /**
- * @brief Driver state.
- */
- qeistate_t state;
- /**
- * @brief Last count value.
- */
- qeicnt_t last;
- /**
- * @brief Current configuration data.
- */
- const QEIConfig *config;
-#if defined(QEI_DRIVER_EXT_FIELDS)
- QEI_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the TIMx registers block.
- */
- stm32_tim_t *tim;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the counter value.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- * @return The current counter value.
- *
- * @notapi
- */
-#define qei_lld_get_count(qeip) ((qeip)->tim->CNT)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if STM32_QEI_USE_TIM1 && !defined(__DOXYGEN__)
-extern QEIDriver QEID1;
-#endif
-
-#if STM32_QEI_USE_TIM2 && !defined(__DOXYGEN__)
-extern QEIDriver QEID2;
-#endif
-
-#if STM32_QEI_USE_TIM3 && !defined(__DOXYGEN__)
-extern QEIDriver QEID3;
-#endif
-
-#if STM32_QEI_USE_TIM4 && !defined(__DOXYGEN__)
-extern QEIDriver QEID4;
-#endif
-
-#if STM32_QEI_USE_TIM5 && !defined(__DOXYGEN__)
-extern QEIDriver QEID5;
-#endif
-
-#if STM32_QEI_USE_TIM8 && !defined(__DOXYGEN__)
-extern QEIDriver QEID8;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void qei_lld_init(void);
- void qei_lld_start(QEIDriver *qeip);
- void qei_lld_stop(QEIDriver *qeip);
- void qei_lld_enable(QEIDriver *qeip);
- void qei_lld_disable(QEIDriver *qeip);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_QEI */
-
-#endif /* HAL_QEI_LLD_H */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c deleted file mode 100644 index 8ab6176..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c +++ /dev/null @@ -1,818 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - This file was derived from the ICU subsystem code, modified to achieve - timing measurements on 2 and/or 4 channel STM32 timers by Dave Camarillo. - */ -/* - Concepts and parts of this file have been contributed by Fabio Utzig and - Xo Wang. - */ - - -/** - * @file STM32/timcap_lld.c - * @brief STM32 TIMCAP subsystem low level driver header. - * - * @addtogroup TIMCAP - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_TIMCAP || defined(__DOXYGEN__) - -#include "stm32_tim.h" -#include "hal_timcap.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief TIMCAPD1 driver identifier. - * @note The driver TIMCAPD1 allocates the complex timer TIM1 when enabled. - */ -#if STM32_TIMCAP_USE_TIM1 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD1; -#endif - -/** - * @brief TIMCAPD2 driver identifier. - * @note The driver TIMCAPD1 allocates the timer TIM2 when enabled. - */ -#if STM32_TIMCAP_USE_TIM2 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD2; -#endif - -/** - * @brief TIMCAPD3 driver identifier. - * @note The driver TIMCAPD1 allocates the timer TIM3 when enabled. - */ -#if STM32_TIMCAP_USE_TIM3 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD3; -#endif - -/** - * @brief TIMCAPD4 driver identifier. - * @note The driver TIMCAPD4 allocates the timer TIM4 when enabled. - */ -#if STM32_TIMCAP_USE_TIM4 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD4; -#endif - -/** - * @brief TIMCAPD5 driver identifier. - * @note The driver TIMCAPD5 allocates the timer TIM5 when enabled. - */ -#if STM32_TIMCAP_USE_TIM5 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD5; -#endif - -/** - * @brief TIMCAPD8 driver identifier. - * @note The driver TIMCAPD8 allocates the timer TIM8 when enabled. - */ -#if STM32_TIMCAP_USE_TIM8 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD8; -#endif - -/** - * @brief TIMCAPD9 driver identifier. - * @note The driver TIMCAPD9 allocates the timer TIM9 when enabled. - */ -#if STM32_TIMCAP_USE_TIM9 || defined(__DOXYGEN__) -TIMCAPDriver TIMCAPD9; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - - -/** - * @brief Returns the maximum channel number for the respective TIMCAP driver. - * Note: different timer perepherials on the STM32 have between 1 and 4 - * CCR registers. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - */ -static timcapchannel_t timcap_get_max_timer_channel(const TIMCAPDriver *timcapp) { - //Choose a sane default value -#if STM32_TIMCAP_USE_TIM1 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD1 ) { - return(TIMCAP_CHANNEL_4); - } -#endif - -#if STM32_TIMCAP_USE_TIM2 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD2 ) { - return(TIMCAP_CHANNEL_4); - } -#endif - -#if STM32_TIMCAP_USE_TIM3 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD3 ) { - return(TIMCAP_CHANNEL_4); - } -#endif - -#if STM32_TIMCAP_USE_TIM4 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD4 ) { - return(TIMCAP_CHANNEL_4); - } -#endif - -#if STM32_TIMCAP_USE_TIM5 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD5 ) { - return(TIMCAP_CHANNEL_4); - } -#endif - -#if STM32_TIMCAP_USE_TIM8 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD8 ) { - return(TIMCAP_CHANNEL_4); - } -#endif - -#if STM32_TIMCAP_USE_TIM9 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD9 ) { - return(TIMCAP_CHANNEL_2); - } -#endif - - /*Return a conservative default value.*/ - return(TIMCAP_CHANNEL_1); -} - - -/** - * @brief Returns the maximum value for the ARR register of a given timer. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - */ -static uint32_t timcap_get_max_arr(const TIMCAPDriver *timcapp) { - //Choose a sane default value -#if STM32_TIMCAP_USE_TIM1 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD1 ) { - return(UINT16_MAX); - } -#endif - -#if STM32_TIMCAP_USE_TIM2 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD2 ) { - return(UINT32_MAX); - } -#endif - -#if STM32_TIMCAP_USE_TIM3 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD3 ) { - return(UINT16_MAX); - } -#endif - -#if STM32_TIMCAP_USE_TIM4 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD4 ) { - return(UINT16_MAX); - } -#endif - -#if STM32_TIMCAP_USE_TIM5 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD5 ) { - return(UINT32_MAX); - } -#endif - -#if STM32_TIMCAP_USE_TIM8 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD8 ) { - return(UINT16_MAX); - } -#endif - -#if STM32_TIMCAP_USE_TIM9 || defined(__DOXYGEN__) - if( timcapp == &TIMCAPD9 ) { - return(UINT16_MAX); - } -#endif - - /*Return a conservative default value.*/ - return(UINT16_MAX); -} - -/** - * @brief Shared IRQ handler. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - */ -static void timcap_lld_serve_interrupt(TIMCAPDriver *timcapp) { - uint16_t sr; - - sr = timcapp->tim->SR; - sr &= timcapp->tim->DIER & STM32_TIM_DIER_IRQ_MASK; - timcapp->tim->SR = ~sr; - - if ((sr & STM32_TIM_SR_CC1IF) != 0 && timcapp->config->capture_cb_array[TIMCAP_CHANNEL_1] != NULL ) - _timcap_isr_invoke_channel1_cb(timcapp); - - if ((sr & STM32_TIM_SR_CC2IF) != 0 && timcapp->config->capture_cb_array[TIMCAP_CHANNEL_2] != NULL ) - _timcap_isr_invoke_channel2_cb(timcapp); - - if ((sr & STM32_TIM_SR_CC3IF) != 0 && timcapp->config->capture_cb_array[TIMCAP_CHANNEL_3] != NULL ) - _timcap_isr_invoke_channel3_cb(timcapp); - - if ((sr & STM32_TIM_SR_CC4IF) != 0 && timcapp->config->capture_cb_array[TIMCAP_CHANNEL_4] != NULL ) - _timcap_isr_invoke_channel4_cb(timcapp); - - if ((sr & STM32_TIM_SR_UIF) != 0 && timcapp->config->overflow_cb != NULL) - _timcap_isr_invoke_overflow_cb(timcapp); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_TIMCAP_USE_TIM1 -#if !defined(STM32_TIM1_UP_HANDLER) -#error "STM32_TIM1_UP_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD1); - - CH_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM1_CC_HANDLER) -#error "STM32_TIM1_CC_HANDLER not defined" -#endif -/** - * @brief TIM1 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD1); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM1 */ - -#if STM32_TIMCAP_USE_TIM2 -#if !defined(STM32_TIM2_HANDLER) -#error "STM32_TIM2_HANDLER not defined" -#endif -/** - * @brief TIM2 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM2_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD2); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM2 */ - -#if STM32_TIMCAP_USE_TIM3 -#if !defined(STM32_TIM3_HANDLER) -#error "STM32_TIM3_HANDLER not defined" -#endif -/** - * @brief TIM3 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM3_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD3); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM3 */ - -#if STM32_TIMCAP_USE_TIM4 -#if !defined(STM32_TIM4_HANDLER) -#error "STM32_TIM4_HANDLER not defined" -#endif -/** - * @brief TIM4 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM4_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD4); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM4 */ - -#if STM32_TIMCAP_USE_TIM5 -#if !defined(STM32_TIM5_HANDLER) -#error "STM32_TIM5_HANDLER not defined" -#endif -/** - * @brief TIM5 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM5_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD5); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM5 */ - -#if STM32_TIMCAP_USE_TIM8 -#if !defined(STM32_TIM8_UP_HANDLER) -#error "STM32_TIM8_UP_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD8); - - CH_IRQ_EPILOGUE(); -} - -#if !defined(STM32_TIM8_CC_HANDLER) -#error "STM32_TIM8_CC_HANDLER not defined" -#endif -/** - * @brief TIM8 compare interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD8); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM8 */ - -#if STM32_TIMCAP_USE_TIM9 -#if !defined(STM32_TIM9_HANDLER) -#error "STM32_TIM9_HANDLER not defined" -#endif -/** - * @brief TIM9 interrupt handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(STM32_TIM9_HANDLER) { - - CH_IRQ_PROLOGUE(); - - timcap_lld_serve_interrupt(&TIMCAPD9); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_TIMCAP_USE_TIM9 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level TIMCAP driver initialization. - * - * @notapi - */ -void timcap_lld_init(void) { - -#if STM32_TIMCAP_USE_TIM1 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD1); - TIMCAPD1.tim = STM32_TIM1; -#endif - -#if STM32_TIMCAP_USE_TIM2 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD2); - TIMCAPD2.tim = STM32_TIM2; -#endif - -#if STM32_TIMCAP_USE_TIM3 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD3); - TIMCAPD3.tim = STM32_TIM3; -#endif - -#if STM32_TIMCAP_USE_TIM4 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD4); - TIMCAPD4.tim = STM32_TIM4; -#endif - -#if STM32_TIMCAP_USE_TIM5 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD5); - TIMCAPD5.tim = STM32_TIM5; -#endif - -#if STM32_TIMCAP_USE_TIM8 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD8); - TIMCAPD8.tim = STM32_TIM8; -#endif - -#if STM32_TIMCAP_USE_TIM9 - /* Driver initialization.*/ - timcapObjectInit(&TIMCAPD9); - TIMCAPD9.tim = STM32_TIM9; -#endif -} - -/** - * @brief Configures and activates the TIMCAP peripheral. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -void timcap_lld_start(TIMCAPDriver *timcapp) { - uint32_t psc; - - const timcapchannel_t tim_max_channel = timcap_get_max_timer_channel(timcapp); - - if (timcapp->state == TIMCAP_STOP) { - /* Clock activation and timer reset.*/ -#if STM32_TIMCAP_USE_TIM1 - if (&TIMCAPD1 == timcapp) { - rccEnableTIM1(FALSE); - rccResetTIM1(); - nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_TIMCAP_TIM1_IRQ_PRIORITY); - nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_TIMCAP_TIM1_IRQ_PRIORITY); -#if defined(STM32_TIM1CLK) - timcapp->clock = STM32_TIM1CLK; -#else - timcapp->clock = STM32_TIMCLK2; -#endif - } -#endif -#if STM32_TIMCAP_USE_TIM2 - if (&TIMCAPD2 == timcapp) { - rccEnableTIM2(FALSE); - rccResetTIM2(); - nvicEnableVector(STM32_TIM2_NUMBER, STM32_TIMCAP_TIM2_IRQ_PRIORITY); - timcapp->clock = STM32_TIMCLK1; - } -#endif -#if STM32_TIMCAP_USE_TIM3 - if (&TIMCAPD3 == timcapp) { - rccEnableTIM3(FALSE); - rccResetTIM3(); - nvicEnableVector(STM32_TIM3_NUMBER, STM32_TIMCAP_TIM3_IRQ_PRIORITY); - timcapp->clock = STM32_TIMCLK1; - } -#endif -#if STM32_TIMCAP_USE_TIM4 - if (&TIMCAPD4 == timcapp) { - rccEnableTIM4(FALSE); - rccResetTIM4(); - nvicEnableVector(STM32_TIM4_NUMBER, STM32_TIMCAP_TIM4_IRQ_PRIORITY); - timcapp->clock = STM32_TIMCLK1; - } -#endif -#if STM32_TIMCAP_USE_TIM5 - if (&TIMCAPD5 == timcapp) { - rccEnableTIM5(FALSE); - rccResetTIM5(); - nvicEnableVector(STM32_TIM5_NUMBER, STM32_TIMCAP_TIM5_IRQ_PRIORITY); - timcapp->clock = STM32_TIMCLK1; - } -#endif -#if STM32_TIMCAP_USE_TIM8 - if (&TIMCAPD8 == timcapp) { - rccEnableTIM8(FALSE); - rccResetTIM8(); - nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_TIMCAP_TIM8_IRQ_PRIORITY); - nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_TIMCAP_TIM8_IRQ_PRIORITY); -#if defined(STM32_TIM8CLK) - timcapp->clock = STM32_TIM8CLK; -#else - timcapp->clock = STM32_TIMCLK2; -#endif - } -#endif -#if STM32_TIMCAP_USE_TIM9 - if (&TIMCAPD9 == timcapp) { - rccEnableTIM9(FALSE); - rccResetTIM9(); - nvicEnableVector(STM32_TIM9_NUMBER, STM32_TIMCAP_TIM9_IRQ_PRIORITY); - timcapp->clock = STM32_TIMCLK1; - } -#endif - } - else { - /* Driver re-configuration scenario, it must be stopped first.*/ - timcapp->tim->CR1 = 0; /* Timer disabled. */ - timcapp->tim->DIER = timcapp->config->dier &/* DMA-related DIER settings. */ - ~STM32_TIM_DIER_IRQ_MASK; - timcapp->tim->SR = 0; /* Clear eventual pending IRQs. */ - timcapp->tim->CCR[0] = 0; /* Comparator 1 disabled. */ - timcapp->tim->CCR[1] = 0; /* Comparator 2 disabled. */ - if( tim_max_channel >= TIMCAP_CHANNEL_3 ) - timcapp->tim->CCR[2] = 0; /* Comparator 3 disabled. */ - if( tim_max_channel >= TIMCAP_CHANNEL_4 ) - timcapp->tim->CCR[3] = 0; /* Comparator 4 disabled. */ - timcapp->tim->CNT = 0; /* Counter reset to zero. */ - } - - /* Timer configuration.*/ - psc = (timcapp->clock / timcapp->config->frequency) - 1; - osalDbgAssert((psc <= 0xFFFF) && - ((psc + 1) * timcapp->config->frequency) == timcapp->clock, - "invalid frequency"); - timcapp->tim->PSC = (uint16_t)psc; - timcapp->tim->ARR = timcap_get_max_arr(timcapp); - - timcapp->tim->CCMR1 = 0; - timcapp->tim->CCMR2 = 0; - timcapp->tim->CCER = 0; - - timcapchannel_t chan = TIMCAP_CHANNEL_1; - - /*go through each non-NULL callback channel and enable the capture register on rising/falling edge*/ - for( chan = TIMCAP_CHANNEL_1; chan <= tim_max_channel; chan++ ) { - if( timcapp->config->capture_cb_array[chan] == NULL ) { - continue; - } - - switch (chan) { - case TIMCAP_CHANNEL_1: - /*CCMR1_CC1S = 01 = CH1 Input on TI1.*/ - timcapp->tim->CCMR1 |= STM32_TIM_CCMR1_CC1S(1); - break; - case TIMCAP_CHANNEL_2: - /*CCMR1_CC2S = 10 = CH2 Input on TI1.*/ - timcapp->tim->CCMR1 |= STM32_TIM_CCMR1_CC2S(1); - break; - case TIMCAP_CHANNEL_3: - timcapp->tim->CCMR2 |= STM32_TIM_CCMR2_CC3S(1); - break; - case TIMCAP_CHANNEL_4: - timcapp->tim->CCMR2 |= STM32_TIM_CCMR2_CC4S(1); - break; - } - - /* The CCER settings depend on the selected trigger mode. - TIMCAP_INPUT_DISABLED: Input not used. - TIMCAP_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. - TIMCAP_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/ - if (timcapp->config->modes[chan] == TIMCAP_INPUT_ACTIVE_HIGH) { - switch (chan) { - case TIMCAP_CHANNEL_1: - timcapp->tim->CCER |= STM32_TIM_CCER_CC1E; - break; - case TIMCAP_CHANNEL_2: - timcapp->tim->CCER |= STM32_TIM_CCER_CC2E; - break; - case TIMCAP_CHANNEL_3: - timcapp->tim->CCER |= STM32_TIM_CCER_CC3E; - break; - case TIMCAP_CHANNEL_4: - timcapp->tim->CCER |= STM32_TIM_CCER_CC4E; - break; - } - } - else if (timcapp->config->modes[chan] == TIMCAP_INPUT_ACTIVE_LOW) { - switch (chan) { - case TIMCAP_CHANNEL_1: - timcapp->tim->CCER |= STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P; - break; - case TIMCAP_CHANNEL_2: - timcapp->tim->CCER |= STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P; - break; - case TIMCAP_CHANNEL_3: - timcapp->tim->CCER |= STM32_TIM_CCER_CC3E | STM32_TIM_CCER_CC3P; - break; - case TIMCAP_CHANNEL_4: - timcapp->tim->CCER |= STM32_TIM_CCER_CC4E | STM32_TIM_CCER_CC4P; - break; - } - } - else { - switch (chan) { - case TIMCAP_CHANNEL_1: - timcapp->tim->CCER &= ~STM32_TIM_CCER_CC1E; - break; - case TIMCAP_CHANNEL_2: - timcapp->tim->CCER &= ~STM32_TIM_CCER_CC2E; - break; - case TIMCAP_CHANNEL_3: - timcapp->tim->CCER &= ~STM32_TIM_CCER_CC3E; - break; - case TIMCAP_CHANNEL_4: - timcapp->tim->CCER &= ~STM32_TIM_CCER_CC4E; - break; - } - } - /* Direct pointers to the capture registers in order to make reading - data faster from within callbacks.*/ - timcapp->ccr_p[chan] = &timcapp->tim->CCR[chan]; - } - - /* SMCR_TS = 101, input is TI1FP1.*/ - timcapp->tim->SMCR = STM32_TIM_SMCR_TS(5); -} - -/** - * @brief Deactivates the TIMCAP peripheral. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -void timcap_lld_stop(TIMCAPDriver *timcapp) { - - if (timcapp->state == TIMCAP_READY) { - /* Clock deactivation.*/ - timcapp->tim->CR1 = 0; /* Timer disabled. */ - timcapp->tim->DIER = 0; /* All IRQs disabled. */ - timcapp->tim->SR = 0; /* Clear eventual pending IRQs. */ - -#if STM32_TIMCAP_USE_TIM1 - if (&TIMCAPD1 == timcapp) { - nvicDisableVector(STM32_TIM1_UP_NUMBER); - nvicDisableVector(STM32_TIM1_CC_NUMBER); - rccDisableTIM1(FALSE); - } -#endif -#if STM32_TIMCAP_USE_TIM2 - if (&TIMCAPD2 == timcapp) { - nvicDisableVector(STM32_TIM2_NUMBER); - rccDisableTIM2(FALSE); - } -#endif -#if STM32_TIMCAP_USE_TIM3 - if (&TIMCAPD3 == timcapp) { - nvicDisableVector(STM32_TIM3_NUMBER); - rccDisableTIM3(FALSE); - } -#endif -#if STM32_TIMCAP_USE_TIM4 - if (&TIMCAPD4 == timcapp) { - nvicDisableVector(STM32_TIM4_NUMBER); - rccDisableTIM4(FALSE); - } -#endif -#if STM32_TIMCAP_USE_TIM5 - if (&TIMCAPD5 == timcapp) { - nvicDisableVector(STM32_TIM5_NUMBER); - rccDisableTIM5(FALSE); - } -#endif -#if STM32_TIMCAP_USE_TIM8 - if (&TIMCAPD8 == timcapp) { - nvicDisableVector(STM32_TIM8_UP_NUMBER); - nvicDisableVector(STM32_TIM8_CC_NUMBER); - rccDisableTIM8(FALSE); - } -#endif -#if STM32_TIMCAP_USE_TIM9 - if (&TIMCAPD9 == timcapp) { - nvicDisableVector(STM32_TIM9_NUMBER); - rccDisableTIM9(FALSE); - } -#endif - } -} - -/** - * @brief Enables the input capture. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -void timcap_lld_enable(TIMCAPDriver *timcapp) { - - timcapp->tim->EGR |= STM32_TIM_EGR_UG; - timcapp->tim->SR = 0; /* Clear pending IRQs (if any). */ - - timcapchannel_t chan = TIMCAP_CHANNEL_1; - const timcapchannel_t tim_max_channel = timcap_get_max_timer_channel(timcapp); - for( chan = TIMCAP_CHANNEL_1; chan <= tim_max_channel; chan++ ) { - if( timcapp->config->capture_cb_array[chan] != NULL - && timcapp->config->modes[chan] != TIMCAP_INPUT_DISABLED ) { - switch (chan) { - case TIMCAP_CHANNEL_1: - timcapp->tim->DIER |= STM32_TIM_DIER_CC1IE; - break; - case TIMCAP_CHANNEL_2: - timcapp->tim->DIER |= STM32_TIM_DIER_CC2IE; - break; - case TIMCAP_CHANNEL_3: - timcapp->tim->DIER |= STM32_TIM_DIER_CC3IE; - break; - case TIMCAP_CHANNEL_4: - timcapp->tim->DIER |= STM32_TIM_DIER_CC4IE; - break; - } - } - } - - if (timcapp->config->overflow_cb != NULL) - timcapp->tim->DIER |= STM32_TIM_DIER_UIE; - - timcapp->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN | timcapp->config->cr1; -} - -/** - * @brief Disables the input capture. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @notapi - */ -void timcap_lld_disable(TIMCAPDriver *timcapp) { - - timcapp->tim->CR1 = 0; /* Initially stopped. */ - timcapp->tim->SR = 0; /* Clear pending IRQs (if any). */ - - /* All interrupts disabled.*/ - timcapp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK; -} - -#endif /* HAL_USE_TIMCAP */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h deleted file mode 100644 index d39c438..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32/timcap_lld.h - * @brief STM32 TIMCAP subsystem low level driver header. - * - * @addtogroup TIMCAP - * @{ - */ - -#ifndef _TIMCAP_LLD_H_ -#define _TIMCAP_LLD_H_ - -#include "ch.h" -#include "hal.h" -#include "stm32_tim.h" - - -#if HAL_USE_TIMCAP || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief TIMCAPD1 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM1) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM1 FALSE -#endif - -/** - * @brief TIMCAPD2 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM2) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM2 FALSE -#endif - -/** - * @brief TIMCAPD3 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM3) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM3 FALSE -#endif - -/** - * @brief TIMCAPD4 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD4 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM4) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM4 FALSE -#endif - -/** - * @brief TIMCAPD5 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD5 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM5) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM5 FALSE -#endif - -/** - * @brief TIMCAPD8 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD8 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM8) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM8 FALSE -#endif - -/** - * @brief TIMCAPD9 driver enable switch. - * @details If set to @p TRUE the support for TIMCAPD9 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_TIMCAP_USE_TIM9) || defined(__DOXYGEN__) -#define STM32_TIMCAP_USE_TIM9 FALSE -#endif - -/** - * @brief TIMCAPD1 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM1_IRQ_PRIORITY 7 -#endif - -/** - * @brief TIMCAPD2 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM2_IRQ_PRIORITY 7 -#endif - -/** - * @brief TIMCAPD3 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM3_IRQ_PRIORITY 7 -#endif - -/** - * @brief TIMCAPD4 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM4_IRQ_PRIORITY 7 -#endif - -/** - * @brief TIMCAPD5 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM5_IRQ_PRIORITY 7 -#endif - -/** - * @brief TIMCAPD8 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM8_IRQ_PRIORITY 7 -#endif - -/** - * @brief TIMCAPD9 interrupt priority level setting. - */ -#if !defined(STM32_TIMCAP_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_TIMCAP_TIM9_IRQ_PRIORITY 7 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_TIMCAP_USE_TIM1 && !STM32_HAS_TIM1 -#error "TIM1 not present in the selected device" -#endif - -#if STM32_TIMCAP_USE_TIM2 && !STM32_HAS_TIM2 -#error "TIM2 not present in the selected device" -#endif - -#if STM32_TIMCAP_USE_TIM3 && !STM32_HAS_TIM3 -#error "TIM3 not present in the selected device" -#endif - -#if STM32_TIMCAP_USE_TIM4 && !STM32_HAS_TIM4 -#error "TIM4 not present in the selected device" -#endif - -#if STM32_TIMCAP_USE_TIM5 && !STM32_HAS_TIM5 -#error "TIM5 not present in the selected device" -#endif - -#if STM32_TIMCAP_USE_TIM8 && !STM32_HAS_TIM8 -#error "TIM8 not present in the selected device" -#endif - -#if STM32_TIMCAP_USE_TIM9 && !STM32_HAS_TIM9 -#error "TIM9 not present in the selected device" -#endif - -#if !STM32_TIMCAP_USE_TIM1 && !STM32_TIMCAP_USE_TIM2 && \ - !STM32_TIMCAP_USE_TIM3 && !STM32_TIMCAP_USE_TIM4 && \ - !STM32_TIMCAP_USE_TIM5 && !STM32_TIMCAP_USE_TIM8 && \ - !STM32_TIMCAP_USE_TIM9 -#error "TIMCAP driver activated but no TIM peripheral assigned" -#endif - -#if STM32_TIMCAP_USE_TIM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM1" -#endif - -#if STM32_TIMCAP_USE_TIM2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM2" -#endif - -#if STM32_TIMCAP_USE_TIM3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM3" -#endif - -#if STM32_TIMCAP_USE_TIM4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM4" -#endif - -#if STM32_TIMCAP_USE_TIM5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM5" -#endif - -#if STM32_TIMCAP_USE_TIM8 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM8" -#endif - -#if STM32_TIMCAP_USE_TIM9 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM9_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to TIM9" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief TIMCAP driver mode. - */ -typedef enum { - TIMCAP_INPUT_DISABLED = 0, - TIMCAP_INPUT_ACTIVE_HIGH = 1, /**< Trigger on rising edge. */ - TIMCAP_INPUT_ACTIVE_LOW = 2, /**< Trigger on falling edge. */ -} timcapmode_t; - -/** - * @brief TIMCAP frequency type. - */ -typedef uint32_t timcapfreq_t; - -/** - * @brief TIMCAP channel type. - */ -typedef enum { - TIMCAP_CHANNEL_1 = 0, /**< Use TIMxCH1. */ - TIMCAP_CHANNEL_2 = 1, /**< Use TIMxCH2. */ - TIMCAP_CHANNEL_3 = 2, /**< Use TIMxCH3. */ - TIMCAP_CHANNEL_4 = 3, /**< Use TIMxCH4. */ -} timcapchannel_t; - - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Driver mode. - */ - timcapmode_t modes[4]; - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - timcapfreq_t frequency; - - /** - * @brief Callback when a capture occurs - */ - timcapcallback_t capture_cb_array[4]; - - /** - * @brief Callback for timer overflow. - */ - timcapcallback_t overflow_cb; - - /* End of the mandatory fields.*/ - - /** - * @brief TIM DIER register initialization data. - * @note The value of this field should normally be equal to zero. - * @note Only the DMA-related bits can be specified in this field. - */ - uint32_t dier; - - /** - * @brief TIM CR1 register initialization data. - * @note The value of this field should normally be equal to zero. - */ - uint32_t cr1; -} TIMCAPConfig; - -/** - * @brief Structure representing an TIMCAP driver. - */ -struct TIMCAPDriver { - /** - * @brief Driver state. - */ - timcapstate_t state; - /** - * @brief Current configuration data. - */ - const TIMCAPConfig *config; -#if defined(TIMCAP_DRIVER_EXT_FIELDS) - TIMCAP_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Timer base clock. - */ - uint32_t clock; - /** - * @brief Pointer to the TIMx registers block. - */ - stm32_tim_t *tim; - /** - * @brief CCR register used for capture. - */ - volatile uint32_t *ccr_p[4]; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -//FIXME document this -#define timcap_lld_get_ccr(timcapp, channel) (*((timcapp)->ccr_p[channel]) + 1) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_TIMCAP_USE_TIM1 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD1; -#endif - -#if STM32_TIMCAP_USE_TIM2 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD2; -#endif - -#if STM32_TIMCAP_USE_TIM3 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD3; -#endif - -#if STM32_TIMCAP_USE_TIM4 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD4; -#endif - -#if STM32_TIMCAP_USE_TIM5 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD5; -#endif - -#if STM32_TIMCAP_USE_TIM8 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD8; -#endif - -#if STM32_TIMCAP_USE_TIM9 && !defined(__DOXYGEN__) -extern TIMCAPDriver TIMCAPD9; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void timcap_lld_init(void); - void timcap_lld_start(TIMCAPDriver *timcapp); - void timcap_lld_stop(TIMCAPDriver *timcapp); - void timcap_lld_enable(TIMCAPDriver *timcapp); - void timcap_lld_disable(TIMCAPDriver *timcapp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_TIMCAP */ - -#endif /* _TIMCAP_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h deleted file mode 100644 index ca2dc49..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h +++ /dev/null @@ -1,929 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file stm32_otg.h - * @brief STM32 OTG registers layout header. - * - * @addtogroup USB - * @{ - */ - - -#ifndef _STM32_OTG_H_ -#define _STM32_OTG_H_ - -/** - * @brief Number of the implemented endpoints in OTG_FS. - * @details This value does not include the endpoint 0 that is always present. - */ -#define STM32_OTG1_ENDOPOINTS_NUMBER 3 - -/** - * @brief Number of the implemented endpoints in OTG_HS. - * @details This value does not include the endpoint 0 that is always present. - */ -#define STM32_OTG2_ENDOPOINTS_NUMBER 5 - -/** - * @brief OTG_FS FIFO memory size in words. - */ -#define STM32_OTG1_FIFO_MEM_SIZE 320 - -/** - * @brief OTG_HS FIFO memory size in words. - */ -#define STM32_OTG2_FIFO_MEM_SIZE 1024 - -/** - * @brief Host channel registers group. - */ -typedef struct { - volatile uint32_t HCCHAR; /**< @brief Host channel characteristics - register. */ - volatile uint32_t resvd8; - volatile uint32_t HCINT; /**< @brief Host channel interrupt register.*/ - volatile uint32_t HCINTMSK; /**< @brief Host channel interrupt mask - register. */ - volatile uint32_t HCTSIZ; /**< @brief Host channel transfer size - register. */ - volatile uint32_t resvd14; - volatile uint32_t resvd18; - volatile uint32_t resvd1c; -} stm32_otg_host_chn_t; - -/** - * @brief Device input endpoint registers group. - */ -typedef struct { - volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint - control register. */ - volatile uint32_t resvd4; - volatile uint32_t DIEPINT; /**< @brief Device IN endpoint interrupt - register. */ - volatile uint32_t resvdC; - volatile uint32_t DIEPTSIZ; /**< @brief Device IN endpoint transfer size - register. */ - volatile uint32_t resvd14; - volatile uint32_t DTXFSTS; /**< @brief Device IN endpoint transmit FIFO - status register. */ - volatile uint32_t resvd1C; -} stm32_otg_in_ep_t; - -/** - * @brief Device output endpoint registers group. - */ -typedef struct { - volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint - control register. */ - volatile uint32_t resvd4; - volatile uint32_t DOEPINT; /**< @brief Device OUT endpoint interrupt - register. */ - volatile uint32_t resvdC; - volatile uint32_t DOEPTSIZ; /**< @brief Device OUT endpoint transfer - size register. */ - volatile uint32_t resvd14; - volatile uint32_t resvd18; - volatile uint32_t resvd1C; -} stm32_otg_out_ep_t; - -/** - * @brief USB registers memory map. - */ -typedef struct { - volatile uint32_t GOTGCTL; /**< @brief OTG control and status register.*/ - volatile uint32_t GOTGINT; /**< @brief OTG interrupt register. */ - volatile uint32_t GAHBCFG; /**< @brief AHB configuration register. */ - volatile uint32_t GUSBCFG; /**< @brief USB configuration register. */ - volatile uint32_t GRSTCTL; /**< @brief Reset register size. */ - volatile uint32_t GINTSTS; /**< @brief Interrupt register. */ - volatile uint32_t GINTMSK; /**< @brief Interrupt mask register. */ - volatile uint32_t GRXSTSR; /**< @brief Receive status debug read - register. */ - volatile uint32_t GRXSTSP; /**< @brief Receive status read/pop - register. */ - volatile uint32_t GRXFSIZ; /**< @brief Receive FIFO size register. */ - volatile uint32_t DIEPTXF0; /**< @brief Endpoint 0 transmit FIFO size - register. */ - volatile uint32_t HNPTXSTS; /**< @brief Non-periodic transmit FIFO/queue - status register. */ - volatile uint32_t resvd30; - volatile uint32_t resvd34; - volatile uint32_t GCCFG; /**< @brief General core configuration. */ - volatile uint32_t CID; /**< @brief Core ID register. */ - volatile uint32_t resvd58[48]; - volatile uint32_t HPTXFSIZ; /**< @brief Host periodic transmit FIFO size - register. */ - volatile uint32_t DIEPTXF[15];/**< @brief Device IN endpoint transmit FIFO - size registers. */ - volatile uint32_t resvd140[176]; - volatile uint32_t HCFG; /**< @brief Host configuration register. */ - volatile uint32_t HFIR; /**< @brief Host frame interval register. */ - volatile uint32_t HFNUM; /**< @brief Host frame number/frame time - Remaining register. */ - volatile uint32_t resvd40C; - volatile uint32_t HPTXSTS; /**< @brief Host periodic transmit FIFO/queue - status register. */ - volatile uint32_t HAINT; /**< @brief Host all channels interrupt - register. */ - volatile uint32_t HAINTMSK; /**< @brief Host all channels interrupt mask - register. */ - volatile uint32_t resvd41C[9]; - volatile uint32_t HPRT; /**< @brief Host port control and status - register. */ - volatile uint32_t resvd444[47]; - stm32_otg_host_chn_t hc[16]; /**< @brief Host channels array. */ - volatile uint32_t resvd700[64]; - volatile uint32_t DCFG; /**< @brief Device configuration register. */ - volatile uint32_t DCTL; /**< @brief Device control register. */ - volatile uint32_t DSTS; /**< @brief Device status register. */ - volatile uint32_t resvd80C; - volatile uint32_t DIEPMSK; /**< @brief Device IN endpoint common - interrupt mask register. */ - volatile uint32_t DOEPMSK; /**< @brief Device OUT endpoint common - interrupt mask register. */ - volatile uint32_t DAINT; /**< @brief Device all endpoints interrupt - register. */ - volatile uint32_t DAINTMSK; /**< @brief Device all endpoints interrupt - mask register. */ - volatile uint32_t resvd820; - volatile uint32_t resvd824; - volatile uint32_t DVBUSDIS; /**< @brief Device VBUS discharge time - register. */ - volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS pulsing time - register. */ - volatile uint32_t resvd830; - volatile uint32_t DIEPEMPMSK; /**< @brief Device IN endpoint FIFO empty - interrupt mask register. */ - volatile uint32_t resvd838; - volatile uint32_t resvd83C; - volatile uint32_t resvd840[16]; - volatile uint32_t resvd880[16]; - volatile uint32_t resvd8C0[16]; - stm32_otg_in_ep_t ie[16]; /**< @brief Input endpoints. */ - stm32_otg_out_ep_t oe[16]; /**< @brief Output endpoints. */ - volatile uint32_t resvdD00[64]; - volatile uint32_t PCGCCTL; /**< @brief Power and clock gating control - register. */ - volatile uint32_t resvdE04[127]; - volatile uint32_t FIFO[16][1024]; -} stm32_otg_t; - -/** - * @name GOTGCTL register bit definitions - * @{ - */ -#define GOTGCTL_BSVLD (1U<<19) /**< B-Session Valid. */ -#define GOTGCTL_ASVLD (1U<<18) /**< A-Session Valid. */ -#define GOTGCTL_DBCT (1U<<17) /**< Long/Short debounce time. */ -#define GOTGCTL_CIDSTS (1U<<16) /**< Connector ID status. */ -#define GOTGCTL_EHEN (1U<<12) -#define GOTGCTL_DHNPEN (1U<<11) /**< Device HNP enabled. */ -#define GOTGCTL_HSHNPEN (1U<<10) /**< Host Set HNP enable. */ -#define GOTGCTL_HNPRQ (1U<<9) /**< HNP request. */ -#define GOTGCTL_HNGSCS (1U<<8) /**< Host negotiation success. */ -#define GOTGCTL_BVALOVAL (1U<<7) -#define GOTGCTL_BVALOEN (1U<<6) -#define GOTGCTL_AVALOVAL (1U<<5) -#define GOTGCTL_AVALOEN (1U<<4) -#define GOTGCTL_VBVALOVAL (1U<<3) -#define GOTGCTL_VBVALOEN (1U<<2) -#define GOTGCTL_SRQ (1U<<1) /**< Session request. */ -#define GOTGCTL_SRQSCS (1U<<0) /**< Session request success. */ -/** @} */ - -/** - * @name GOTGINT register bit definitions - * @{ - */ -#define GOTGINT_DBCDNE (1U<<19) /**< Debounce done. */ -#define GOTGINT_ADTOCHG (1U<<18) /**< A-Device timeout change. */ -#define GOTGINT_HNGDET (1U<<17) /**< Host negotiation detected. */ -#define GOTGINT_HNSSCHG (1U<<9) /**< Host negotiation success - status change. */ -#define GOTGINT_SRSSCHG (1U<<8) /**< Session request success - status change. */ -#define GOTGINT_SEDET (1U<<2) /**< Session end detected. */ -/** @} */ - -/** - * @name GAHBCFG register bit definitions - * @{ - */ -#define GAHBCFG_PTXFELVL (1U<<8) /**< Periodic TxFIFO empty - level. */ -#define GAHBCFG_TXFELVL (1U<<7) /**< Non-periodic TxFIFO empty - level. */ -#define GAHBCFG_DMAEN (1U<<5) /**< DMA enable (HS only). */ -#define GAHBCFG_HBSTLEN_MASK (15U<<1) /**< Burst length/type mask (HS - only). */ -#define GAHBCFG_HBSTLEN(n) ((n)<<1) /**< Burst length/type (HS - only). */ -#define GAHBCFG_GINTMSK (1U<<0) /**< Global interrupt mask. */ -/** @} */ - -/** - * @name GUSBCFG register bit definitions - * @{ - */ -#define GUSBCFG_CTXPKT (1U<<31) /**< Corrupt Tx packet. */ -#define GUSBCFG_FDMOD (1U<<30) /**< Force Device Mode. */ -#define GUSBCFG_FHMOD (1U<<29) /**< Force Host Mode. */ -#define GUSBCFG_TRDT_MASK (15U<<10) /**< USB Turnaround time field - mask. */ -#define GUSBCFG_TRDT(n) ((n)<<10) /**< USB Turnaround time field - value. */ -#define GUSBCFG_HNPCAP (1U<<9) /**< HNP-Capable. */ -#define GUSBCFG_SRPCAP (1U<<8) /**< SRP-Capable. */ -#define GUSBCFG_PHYSEL (1U<<6) /**< USB 2.0 High-Speed PHY or - USB 1.1 Full-Speed serial - transceiver Select. */ -#define GUSBCFG_TOCAL_MASK (7U<<0) /**< HS/FS timeout calibration - field mask. */ -#define GUSBCFG_TOCAL(n) ((n)<<0) /**< HS/FS timeout calibration - field value. */ -/** @} */ - -/** - * @name GRSTCTL register bit definitions - * @{ - */ -#define GRSTCTL_AHBIDL (1U<<31) /**< AHB Master Idle. */ -#define GRSTCTL_TXFNUM_MASK (31U<<6) /**< TxFIFO number field mask. */ -#define GRSTCTL_TXFNUM(n) ((n)<<6) /**< TxFIFO number field value. */ -#define GRSTCTL_TXFFLSH (1U<<5) /**< TxFIFO flush. */ -#define GRSTCTL_RXFFLSH (1U<<4) /**< RxFIFO flush. */ -#define GRSTCTL_FCRST (1U<<2) /**< Host frame counter reset. */ -#define GRSTCTL_HSRST (1U<<1) /**< HClk soft reset. */ -#define GRSTCTL_CSRST (1U<<0) /**< Core soft reset. */ -/** @} */ - -/** - * @name GINTSTS register bit definitions - * @{ - */ -#define GINTSTS_WKUPINT (1U<<31) /**< Resume/Remote wakeup - detected interrupt. */ -#define GINTSTS_SRQINT (1U<<30) /**< Session request/New session - detected interrupt. */ -#define GINTSTS_DISCINT (1U<<29) /**< Disconnect detected - interrupt. */ -#define GINTSTS_CIDSCHG (1U<<28) /**< Connector ID status change.*/ -#define GINTSTS_PTXFE (1U<<26) /**< Periodic TxFIFO empty. */ -#define GINTSTS_HCINT (1U<<25) /**< Host channels interrupt. */ -#define GINTSTS_HPRTINT (1U<<24) /**< Host port interrupt. */ -#define GINTSTS_IPXFR (1U<<21) /**< Incomplete periodic - transfer. */ -#define GINTSTS_IISOOXFR (1U<<21) /**< Incomplete isochronous OUT - transfer. */ -#define GINTSTS_IISOIXFR (1U<<20) /**< Incomplete isochronous IN - transfer. */ -#define GINTSTS_OEPINT (1U<<19) /**< OUT endpoints interrupt. */ -#define GINTSTS_IEPINT (1U<<18) /**< IN endpoints interrupt. */ -#define GINTSTS_EOPF (1U<<15) /**< End of periodic frame - interrupt. */ -#define GINTSTS_ISOODRP (1U<<14) /**< Isochronous OUT packet - dropped interrupt. */ -#define GINTSTS_ENUMDNE (1U<<13) /**< Enumeration done. */ -#define GINTSTS_USBRST (1U<<12) /**< USB reset. */ -#define GINTSTS_USBSUSP (1U<<11) /**< USB suspend. */ -#define GINTSTS_ESUSP (1U<<10) /**< Early suspend. */ -#define GINTSTS_GONAKEFF (1U<<7) /**< Global OUT NAK effective. */ -#define GINTSTS_GINAKEFF (1U<<6) /**< Global IN non-periodic NAK - effective. */ -#define GINTSTS_NPTXFE (1U<<5) /**< Non-periodic TxFIFO empty. */ -#define GINTSTS_RXFLVL (1U<<4) /**< RxFIFO non-empty. */ -#define GINTSTS_SOF (1U<<3) /**< Start of frame. */ -#define GINTSTS_OTGINT (1U<<2) /**< OTG interrupt. */ -#define GINTSTS_MMIS (1U<<1) /**< Mode Mismatch interrupt. */ -#define GINTSTS_CMOD (1U<<0) /**< Current mode of operation. */ -/** @} */ - -/** - * @name GINTMSK register bit definitions - * @{ - */ -#define GINTMSK_WKUM (1U<<31) /**< Resume/remote wakeup - detected interrupt mask. */ -#define GINTMSK_SRQM (1U<<30) /**< Session request/New session - detected interrupt mask. */ -#define GINTMSK_DISCM (1U<<29) /**< Disconnect detected - interrupt mask. */ -#define GINTMSK_CIDSCHGM (1U<<28) /**< Connector ID status change - mask. */ -#define GINTMSK_PTXFEM (1U<<26) /**< Periodic TxFIFO empty mask.*/ -#define GINTMSK_HCM (1U<<25) /**< Host channels interrupt - mask. */ -#define GINTMSK_HPRTM (1U<<24) /**< Host port interrupt mask. */ -#define GINTMSK_IPXFRM (1U<<21) /**< Incomplete periodic - transfer mask. */ -#define GINTMSK_IISOOXFRM (1U<<21) /**< Incomplete isochronous OUT - transfer mask. */ -#define GINTMSK_IISOIXFRM (1U<<20) /**< Incomplete isochronous IN - transfer mask. */ -#define GINTMSK_OEPM (1U<<19) /**< OUT endpoints interrupt - mask. */ -#define GINTMSK_IEPM (1U<<18) /**< IN endpoints interrupt - mask. */ -#define GINTMSK_EOPFM (1U<<15) /**< End of periodic frame - interrupt mask. */ -#define GINTMSK_ISOODRPM (1U<<14) /**< Isochronous OUT packet - dropped interrupt mask. */ -#define GINTMSK_ENUMDNEM (1U<<13) /**< Enumeration done mask. */ -#define GINTMSK_USBRSTM (1U<<12) /**< USB reset mask. */ -#define GINTMSK_USBSUSPM (1U<<11) /**< USB suspend mask. */ -#define GINTMSK_ESUSPM (1U<<10) /**< Early suspend mask. */ -#define GINTMSK_GONAKEFFM (1U<<7) /**< Global OUT NAK effective - mask. */ -#define GINTMSK_GINAKEFFM (1U<<6) /**< Global non-periodic IN NAK - effective mask. */ -#define GINTMSK_NPTXFEM (1U<<5) /**< Non-periodic TxFIFO empty - mask. */ -#define GINTMSK_RXFLVLM (1U<<4) /**< Receive FIFO non-empty - mask. */ -#define GINTMSK_SOFM (1U<<3) /**< Start of (micro)frame mask.*/ -#define GINTMSK_OTGM (1U<<2) /**< OTG interrupt mask. */ -#define GINTMSK_MMISM (1U<<1) /**< Mode Mismatch interrupt - mask. */ -/** @} */ - -/** - * @name GRXSTSR register bit definitions - * @{ - */ -#define GRXSTSR_PKTSTS_MASK (15U<<17) /**< Packet status mask. */ -#define GRXSTSR_PKTSTS(n) ((n)<<17) /**< Packet status value. */ -#define GRXSTSR_OUT_GLOBAL_NAK GRXSTSR_PKTSTS(1) -#define GRXSTSR_OUT_DATA GRXSTSR_PKTSTS(2) -#define GRXSTSR_OUT_COMP GRXSTSR_PKTSTS(3) -#define GRXSTSR_SETUP_COMP GRXSTSR_PKTSTS(4) -#define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6) -#define GRXSTSR_DPID_MASK (3U<<15) /**< Data PID mask. */ -#define GRXSTSR_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ -#define GRXSTSR_BCNT(n) ((n)<<4) /**< Byte count value. */ -#define GRXSTSR_CHNUM_MASK (15U<<0) /**< Channel number mask. */ -#define GRXSTSR_CHNUM(n) ((n)<<0) /**< Channel number value. */ -#define GRXSTSR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ -#define GRXSTSR_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ -/** @} */ - -/** - * @name GRXSTSP register bit definitions - * @{ - */ -#define GRXSTSP_PKTSTS_MASK (15<<17) /**< Packet status mask. */ -#define GRXSTSP_PKTSTS(n) ((n)<<17) /**< Packet status value. */ -#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1) -#define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2) -#define GRXSTSP_OUT_COMP GRXSTSP_PKTSTS(3) -#define GRXSTSP_SETUP_COMP GRXSTSP_PKTSTS(4) -#define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6) -#define GRXSTSP_DPID_MASK (3U<<15) /**< Data PID mask. */ -#define GRXSTSP_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ -#define GRXSTSP_BCNT_OFF 4 /**< Byte count offset. */ -#define GRXSTSP_BCNT(n) ((n)<<4) /**< Byte count value. */ -#define GRXSTSP_CHNUM_MASK (15U<<0) /**< Channel number mask. */ -#define GRXSTSP_CHNUM(n) ((n)<<0) /**< Channel number value. */ -#define GRXSTSP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ -#define GRXSTSP_EPNUM_OFF 0 /**< Endpoint number offset. */ -#define GRXSTSP_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ -/** @} */ - -/** - * @name GRXFSIZ register bit definitions - * @{ - */ -#define GRXFSIZ_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */ -#define GRXFSIZ_RXFD(n) ((n)<<0) /**< RxFIFO depth value. */ -/** @} */ - -/** - * @name DIEPTXFx register bit definitions - * @{ - */ -#define DIEPTXF_INEPTXFD_MASK (0xFFFFU<<16)/**< IN endpoint TxFIFO depth - mask. */ -#define DIEPTXF_INEPTXFD(n) ((n)<<16) /**< IN endpoint TxFIFO depth - value. */ -#define DIEPTXF_INEPTXSA_MASK (0xFFFF<<0) /**< IN endpoint FIFOx transmit - RAM start address mask. */ -#define DIEPTXF_INEPTXSA(n) ((n)<<0) /**< IN endpoint FIFOx transmit - RAM start address value. */ -/** @} */ - -/** - * @name GCCFG register bit definitions - * @{ - */ -#define GCCFG_NOVBUSSENS (1U<<21) /**< VBUS sensing disable. */ -#define GCCFG_SOFOUTEN (1U<<20) /**< SOF output enable. */ -#define GCCFG_VBUSBSEN (1U<<19) /**< Enable the VBUS sensing "B" - device. */ -#define GCCFG_VBUSASEN (1U<<18) /**< Enable the VBUS sensing "A" - device. */ -#define GCCFG_PWRDWN (1U<<16) /**< Power down. */ -/** @} */ - -/** - * @name HPTXFSIZ register bit definitions - * @{ - */ -#define HPTXFSIZ_PTXFD_MASK (0xFFFFU<<16)/**< Host periodic TxFIFO - depth mask. */ -#define HPTXFSIZ_PTXFD(n) ((n)<<16) /**< Host periodic TxFIFO - depth value. */ -#define HPTXFSIZ_PTXSA_MASK (0xFFFFU<<0)/**< Host periodic TxFIFO - Start address mask. */ -#define HPTXFSIZ_PTXSA(n) ((n)<<0) /**< Host periodic TxFIFO - start address value. */ -/** @} */ - -/** - * @name HCFG register bit definitions - * @{ - */ -#define HCFG_FSLSS (1U<<2) /**< FS- and LS-only support. */ -#define HCFG_FSLSPCS_MASK (3U<<0) /**< FS/LS PHY clock select - mask. */ -#define HCFG_FSLSPCS_48 (1U<<0) /**< PHY clock is running at - 48 MHz. */ -#define HCFG_FSLSPCS_6 (2U<<0) /**< PHY clock is running at - 6 MHz. */ -/** @} */ - -/** - * @name HFIR register bit definitions - * @{ - */ -#define HFIR_FRIVL_MASK (0xFFFFU<<0)/**< Frame interval mask. */ -#define HFIR_FRIVL(n) ((n)<<0) /**< Frame interval value. */ -/** @} */ - -/** - * @name HFNUM register bit definitions - * @{ - */ -#define HFNUM_FTREM_MASK (0xFFFFU<<16)/**< Frame time Remaining mask.*/ -#define HFNUM_FTREM(n) ((n)<<16) /**< Frame time Remaining value.*/ -#define HFNUM_FRNUM_MASK (0xFFFFU<<0)/**< Frame number mask. */ -#define HFNUM_FRNUM(n) ((n)<<0) /**< Frame number value. */ -/** @} */ - -/** - * @name HPTXSTS register bit definitions - * @{ - */ -#define HPTXSTS_PTXQTOP_MASK (0xFFU<<24) /**< Top of the periodic - transmit request queue - mask. */ -#define HPTXSTS_PTXQTOP(n) ((n)<<24) /**< Top of the periodic - transmit request queue - value. */ -#define HPTXSTS_PTXQSAV_MASK (0xFF<<16) /**< Periodic transmit request - queue Space Available - mask. */ -#define HPTXSTS_PTXQSAV(n) ((n)<<16) /**< Periodic transmit request - queue Space Available - value. */ -#define HPTXSTS_PTXFSAVL_MASK (0xFFFF<<0) /**< Periodic transmit Data - FIFO Space Available - mask. */ -#define HPTXSTS_PTXFSAVL(n) ((n)<<0) /**< Periodic transmit Data - FIFO Space Available - value. */ -/** @} */ - -/** - * @name HAINT register bit definitions - * @{ - */ -#define HAINT_HAINT_MASK (0xFFFFU<<0)/**< Channel interrupts mask. */ -#define HAINT_HAINT(n) ((n)<<0) /**< Channel interrupts value. */ -/** @} */ - -/** - * @name HAINTMSK register bit definitions - * @{ - */ -#define HAINTMSK_HAINTM_MASK (0xFFFFU<<0)/**< Channel interrupt mask - mask. */ -#define HAINTMSK_HAINTM(n) ((n)<<0) /**< Channel interrupt mask - value. */ -/** @} */ - -/** - * @name HPRT register bit definitions - * @{ - */ -#define HPRT_PSPD_MASK (3U<<17) /**< Port speed mask. */ -#define HPRT_PSPD_FS (1U<<17) /**< Full speed value. */ -#define HPRT_PSPD_LS (2U<<17) /**< Low speed value. */ -#define HPRT_PTCTL_MASK (15<<13) /**< Port Test control mask. */ -#define HPRT_PTCTL(n) ((n)<<13) /**< Port Test control value. */ -#define HPRT_PPWR (1U<<12) /**< Port power. */ -#define HPRT_PLSTS_MASK (3U<<11) /**< Port Line status mask. */ -#define HPRT_PLSTS_DM (1U<<11) /**< Logic level of D-. */ -#define HPRT_PLSTS_DP (1U<<10) /**< Logic level of D+. */ -#define HPRT_PRST (1U<<8) /**< Port reset. */ -#define HPRT_PSUSP (1U<<7) /**< Port suspend. */ -#define HPRT_PRES (1U<<6) /**< Port Resume. */ -#define HPRT_POCCHNG (1U<<5) /**< Port overcurrent change. */ -#define HPRT_POCA (1U<<4) /**< Port overcurrent active. */ -#define HPRT_PENCHNG (1U<<3) /**< Port enable/disable change.*/ -#define HPRT_PENA (1U<<2) /**< Port enable. */ -#define HPRT_PCDET (1U<<1) /**< Port Connect detected. */ -#define HPRT_PCSTS (1U<<0) /**< Port connect status. */ -/** @} */ - -/** - * @name HCCHAR register bit definitions - * @{ - */ -#define HCCHAR_CHENA (1U<<31) /**< Channel enable. */ -#define HCCHAR_CHDIS (1U<<30) /**< Channel Disable. */ -#define HCCHAR_ODDFRM (1U<<29) /**< Odd frame. */ -#define HCCHAR_DAD_MASK (0x7FU<<22) /**< Device Address mask. */ -#define HCCHAR_DAD(n) ((n)<<22) /**< Device Address value. */ -#define HCCHAR_MCNT_MASK (3U<<20) /**< Multicount mask. */ -#define HCCHAR_MCNT(n) ((n)<<20) /**< Multicount value. */ -#define HCCHAR_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */ -#define HCCHAR_EPTYP(n) ((n)<<18) /**< Endpoint type value. */ -#define HCCHAR_EPTYP_CTL (0U<<18) /**< Control endpoint value. */ -#define HCCHAR_EPTYP_ISO (1U<<18) /**< Isochronous endpoint value.*/ -#define HCCHAR_EPTYP_BULK (2U<<18) /**< Bulk endpoint value. */ -#define HCCHAR_EPTYP_INTR (3U<<18) /**< Interrupt endpoint value. */ -#define HCCHAR_LSDEV (1U<<17) /**< Low-Speed device. */ -#define HCCHAR_EPDIR (1U<<15) /**< Endpoint direction. */ -#define HCCHAR_EPNUM_MASK (15U<<11) /**< Endpoint number mask. */ -#define HCCHAR_EPNUM(n) ((n)<<11) /**< Endpoint number value. */ -#define HCCHAR_MPS_MASK (0x7FFU<<0) /**< Maximum packet size mask. */ -#define HCCHAR_MPS(n) ((n)<<0) /**< Maximum packet size value. */ -/** @} */ - -/** - * @name HCINT register bit definitions - * @{ - */ -#define HCINT_DTERR (1U<<10) /**< Data toggle error. */ -#define HCINT_FRMOR (1U<<9) /**< Frame overrun. */ -#define HCINT_BBERR (1U<<8) /**< Babble error. */ -#define HCINT_TRERR (1U<<7) /**< Transaction Error. */ -#define HCINT_ACK (1U<<5) /**< ACK response - received/transmitted - interrupt. */ -#define HCINT_NAK (1U<<4) /**< NAK response received - interrupt. */ -#define HCINT_STALL (1U<<3) /**< STALL response received - interrupt. */ -#define HCINT_CHH (1U<<1) /**< Channel halted. */ -#define HCINT_XFRC (1U<<0) /**< Transfer completed. */ -/** @} */ - -/** - * @name HCINTMSK register bit definitions - * @{ - */ -#define HCINTMSK_DTERRM (1U<<10) /**< Data toggle error mask. */ -#define HCINTMSK_FRMORM (1U<<9) /**< Frame overrun mask. */ -#define HCINTMSK_BBERRM (1U<<8) /**< Babble error mask. */ -#define HCINTMSK_TRERRM (1U<<7) /**< Transaction error mask. */ -#define HCINTMSK_NYET (1U<<6) /**< NYET response received - interrupt mask. */ -#define HCINTMSK_ACKM (1U<<5) /**< ACK Response - received/transmitted - interrupt mask. */ -#define HCINTMSK_NAKM (1U<<4) /**< NAK response received - interrupt mask. */ -#define HCINTMSK_STALLM (1U<<3) /**< STALL response received - interrupt mask. */ -#define HCINTMSK_AHBERRM (1U<<2) -#define HCINTMSK_CHHM (1U<<1) /**< Channel halted mask. */ -#define HCINTMSK_XFRCM (1U<<0) /**< Transfer completed mask. */ -/** @} */ - -/** - * @name HCTSIZ register bit definitions - * @{ - */ -#define HCTSIZ_DPID_MASK (3U<<29) /**< PID mask. */ -#define HCTSIZ_DPID_DATA0 (0U<<29) /**< DATA0. */ -#define HCTSIZ_DPID_DATA2 (1U<<29) /**< DATA2. */ -#define HCTSIZ_DPID_DATA1 (2U<<29) /**< DATA1. */ -#define HCTSIZ_DPID_MDATA (3U<<29) /**< MDATA. */ -#define HCTSIZ_DPID_SETUP (3U<<29) /**< SETUP. */ -#define HCTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */ -#define HCTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define HCTSIZ_XFRSIZ_MASK (0x7FFFF<<0)/**< Transfer size mask. */ -#define HCTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ -/** @} */ - -/** - * @name DCFG register bit definitions - * @{ - */ -#define DCFG_PFIVL_MASK (3U<<11) /**< Periodic frame interval - mask. */ -#define DCFG_PFIVL(n) ((n)<<11) /**< Periodic frame interval - value. */ -#define DCFG_DAD_MASK (0x7FU<<4) /**< Device address mask. */ -#define DCFG_DAD(n) ((n)<<4) /**< Device address value. */ -#define DCFG_NZLSOHSK (1U<<2) /**< Non-Zero-Length status - OUT handshake. */ -#define DCFG_DSPD_MASK (3U<<0) /**< Device speed mask. */ -#define DCFG_DSPD_HS (0U<<0) /**< High speed (USB 2.0). */ -#define DCFG_DSPD_HS_FS (1U<<0) /**< High speed (USB 2.0) in FS - mode. */ -#define DCFG_DSPD_FS11 (3U<<0) /**< Full speed (USB 1.1 - transceiver clock is 48 - MHz). */ -/** @} */ - -/** - * @name DCTL register bit definitions - * @{ - */ -#define DCTL_POPRGDNE (1U<<11) /**< Power-on programming done. */ -#define DCTL_CGONAK (1U<<10) /**< Clear global OUT NAK. */ -#define DCTL_SGONAK (1U<<9) /**< Set global OUT NAK. */ -#define DCTL_CGINAK (1U<<8) /**< Clear global non-periodic - IN NAK. */ -#define DCTL_SGINAK (1U<<7) /**< Set global non-periodic - IN NAK. */ -#define DCTL_TCTL_MASK (7U<<4) /**< Test control mask. */ -#define DCTL_TCTL(n) ((n)<<4 /**< Test control value. */ -#define DCTL_GONSTS (1U<<3) /**< Global OUT NAK status. */ -#define DCTL_GINSTS (1U<<2) /**< Global non-periodic IN - NAK status. */ -#define DCTL_SDIS (1U<<1) /**< Soft disconnect. */ -#define DCTL_RWUSIG (1U<<0) /**< Remote wakeup signaling. */ -/** @} */ - -/** - * @name DSTS register bit definitions - * @{ - */ -#define DSTS_FNSOF_MASK (0x3FFU<<8) /**< Frame number of the received - SOF mask. */ -#define DSTS_FNSOF(n) ((n)<<8) /**< Frame number of the received - SOF value. */ -#define DSTS_FNSOF_ODD (1U<<8) /**< Frame parity of the received - SOF value. */ -#define DSTS_EERR (1U<<3) /**< Erratic error. */ -#define DSTS_ENUMSPD_MASK (3U<<1) /**< Enumerated speed mask. */ -#define DSTS_ENUMSPD_FS_48 (3U<<1) /**< Full speed (PHY clock is - running at 48 MHz). */ -#define DSTS_ENUMSPD_HS_480 (0U<<1) /**< High speed. */ -#define DSTS_SUSPSTS (1U<<0) /**< Suspend status. */ -/** @} */ - -/** - * @name DIEPMSK register bit definitions - * @{ - */ -#define DIEPMSK_TXFEM (1U<<6) /**< Transmit FIFO empty mask. */ -#define DIEPMSK_INEPNEM (1U<<6) /**< IN endpoint NAK effective - mask. */ -#define DIEPMSK_ITTXFEMSK (1U<<4) /**< IN token received when - TxFIFO empty mask. */ -#define DIEPMSK_TOCM (1U<<3) /**< Timeout condition mask. */ -#define DIEPMSK_EPDM (1U<<1) /**< Endpoint disabled - interrupt mask. */ -#define DIEPMSK_XFRCM (1U<<0) /**< Transfer completed - interrupt mask. */ -/** @} */ - -/** - * @name DOEPMSK register bit definitions - * @{ - */ -#define DOEPMSK_OTEPDM (1U<<4) /**< OUT token received when - endpoint disabled mask. */ -#define DOEPMSK_STUPM (1U<<3) /**< SETUP phase done mask. */ -#define DOEPMSK_EPDM (1U<<1) /**< Endpoint disabled - interrupt mask. */ -#define DOEPMSK_XFRCM (1U<<0) /**< Transfer completed - interrupt mask. */ -/** @} */ - -/** - * @name DAINT register bit definitions - * @{ - */ -#define DAINT_OEPINT_MASK (0xFFFFU<<16)/**< OUT endpoint interrupt - bits mask. */ -#define DAINT_OEPINT(n) ((n)<<16) /**< OUT endpoint interrupt - bits value. */ -#define DAINT_IEPINT_MASK (0xFFFFU<<0)/**< IN endpoint interrupt - bits mask. */ -#define DAINT_IEPINT(n) ((n)<<0) /**< IN endpoint interrupt - bits value. */ -/** @} */ - -/** - * @name DAINTMSK register bit definitions - * @{ - */ -#define DAINTMSK_OEPM_MASK (0xFFFFU<<16)/**< OUT EP interrupt mask - bits mask. */ -#define DAINTMSK_OEPM(n) (1U<<(16+(n)))/**< OUT EP interrupt mask - bits value. */ -#define DAINTMSK_IEPM_MASK (0xFFFFU<<0)/**< IN EP interrupt mask - bits mask. */ -#define DAINTMSK_IEPM(n) (1U<<(n)) /**< IN EP interrupt mask - bits value. */ -/** @} */ - -/** - * @name DVBUSDIS register bit definitions - * @{ - */ -#define DVBUSDIS_VBUSDT_MASK (0xFFFFU<<0)/**< Device VBUS discharge - time mask. */ -#define DVBUSDIS_VBUSDT(n) ((n)<<0) /**< Device VBUS discharge - time value. */ -/** @} */ - -/** - * @name DVBUSPULSE register bit definitions - * @{ - */ -#define DVBUSPULSE_DVBUSP_MASK (0xFFFU<<0) /**< Device VBUSpulsing time - mask. */ -#define DVBUSPULSE_DVBUSP(n) ((n)<<0) /**< Device VBUS pulsing time - value. */ -/** @} */ - -/** - * @name DIEPEMPMSK register bit definitions - * @{ - */ -#define DIEPEMPMSK_INEPTXFEM(n) (1U<<(n)) /**< IN EP Tx FIFO empty - interrupt mask bit. */ -/** @} */ - -/** - * @name DIEPCTL register bit definitions - * @{ - */ -#define DIEPCTL_EPENA (1U<<31) /**< Endpoint enable. */ -#define DIEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */ -#define DIEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */ -#define DIEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */ -#define DIEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */ -#define DIEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */ -#define DIEPCTL_SNAK (1U<<27) /**< Set NAK. */ -#define DIEPCTL_CNAK (1U<<26) /**< Clear NAK. */ -#define DIEPCTL_TXFNUM_MASK (15U<<22) /**< TxFIFO number mask. */ -#define DIEPCTL_TXFNUM(n) ((n)<<22) /**< TxFIFO number value. */ -#define DIEPCTL_STALL (1U<<21) /**< STALL handshake. */ -#define DIEPCTL_SNPM (1U<<20) /**< Snoop mode. */ -#define DIEPCTL_EPTYP_MASK (3<<18) /**< Endpoint type mask. */ -#define DIEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */ -#define DIEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */ -#define DIEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */ -#define DIEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */ -#define DIEPCTL_NAKSTS (1U<<17) /**< NAK status. */ -#define DIEPCTL_EONUM (1U<<16) /**< Even/odd frame. */ -#define DIEPCTL_DPID (1U<<16) /**< Endpoint data PID. */ -#define DIEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */ -#define DIEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */ -#define DIEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */ -/** @} */ - -/** - * @name DIEPINT register bit definitions - * @{ - */ -#define DIEPINT_TXFE (1U<<7) /**< Transmit FIFO empty. */ -#define DIEPINT_INEPNE (1U<<6) /**< IN endpoint NAK effective. */ -#define DIEPINT_ITTXFE (1U<<4) /**< IN Token received when - TxFIFO is empty. */ -#define DIEPINT_TOC (1U<<3) /**< Timeout condition. */ -#define DIEPINT_EPDISD (1U<<1) /**< Endpoint disabled - interrupt. */ -#define DIEPINT_XFRC (1U<<0) /**< Transfer completed. */ -/** @} */ - -/** - * @name DIEPTSIZ register bit definitions - * @{ - */ -#define DIEPTSIZ_MCNT_MASK (3U<<29) /**< Multi count mask. */ -#define DIEPTSIZ_MCNT(n) ((n)<<29) /**< Multi count value. */ -#define DIEPTSIZ_PKTCNT_MASK (0x3FF<<19) /**< Packet count mask. */ -#define DIEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */ -#define DIEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ -/** @} */ - -/** - * @name DTXFSTS register bit definitions. - * @{ - */ -#define DTXFSTS_INEPTFSAV_MASK (0xFFFF<<0) /**< IN endpoint TxFIFO space - available. */ -/** @} */ - -/** - * @name DOEPCTL register bit definitions. - * @{ - */ -#define DOEPCTL_EPENA (1U<<31) /**< Endpoint enable. */ -#define DOEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */ -#define DOEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */ -#define DOEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */ -#define DOEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */ -#define DOEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */ -#define DOEPCTL_SNAK (1U<<27) /**< Set NAK. */ -#define DOEPCTL_CNAK (1U<<26) /**< Clear NAK. */ -#define DOEPCTL_STALL (1U<<21) /**< STALL handshake. */ -#define DOEPCTL_SNPM (1U<<20) /**< Snoop mode. */ -#define DOEPCTL_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */ -#define DOEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */ -#define DOEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */ -#define DOEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */ -#define DOEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */ -#define DOEPCTL_NAKSTS (1U<<17) /**< NAK status. */ -#define DOEPCTL_EONUM (1U<<16) /**< Even/odd frame. */ -#define DOEPCTL_DPID (1U<<16) /**< Endpoint data PID. */ -#define DOEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */ -#define DOEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */ -#define DOEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */ -/** @} */ - -/** - * @name DOEPINT register bit definitions - * @{ - */ -#define DOEPINT_B2BSTUP (1U<<6) /**< Back-to-back SETUP packets - received. */ -#define DOEPINT_OTEPDIS (1U<<4) /**< OUT token received when - endpoint disabled. */ -#define DOEPINT_STUP (1U<<3) /**< SETUP phase done. */ -#define DOEPINT_EPDISD (1U<<1) /**< Endpoint disabled - interrupt. */ -#define DOEPINT_XFRC (1U<<0) /**< Transfer completed - interrupt. */ -/** @} */ - -/** - * @name DOEPTSIZ register bit definitions - * @{ - */ -#define DOEPTSIZ_RXDPID_MASK (3U<<29) /**< Received data PID mask. */ -#define DOEPTSIZ_RXDPID(n) ((n)<<29) /**< Received data PID value. */ -#define DOEPTSIZ_STUPCNT_MASK (3U<<29) /**< SETUP packet count mask. */ -#define DOEPTSIZ_STUPCNT(n) ((n)<<29) /**< SETUP packet count value. */ -#define DOEPTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */ -#define DOEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ -#define DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */ -#define DOEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */ -/** @} */ - -/** - * @name PCGCCTL register bit definitions - * @{ - */ -#define PCGCCTL_PHYSUSP (1U<<4) /**< PHY Suspended. */ -#define PCGCCTL_GATEHCLK (1U<<1) /**< Gate HCLK. */ -#define PCGCCTL_STPPCLK (1U<<0) /**< Stop PCLK. */ -/** @} */ - -/** - * @brief OTG_FS registers block memory address. - */ -#define OTG_FS_ADDR 0x50000000 - -/** - * @brief OTG_HS registers block memory address. - */ -#define OTG_HS_ADDR 0x40040000 - -/** - * @brief Accesses to the OTG_FS registers block. - */ -#define OTG_FS ((stm32_otg_t *)OTG_FS_ADDR) - -/** - * @brief Accesses to the OTG_HS registers block. - */ -#define OTG_HS ((stm32_otg_t *)OTG_HS_ADDR) - -#endif /* _STM32_OTG_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c deleted file mode 100644 index 3abab1c..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c +++ /dev/null @@ -1,1604 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -#if HAL_USE_USBH -#include "usbh/internal.h" -#include <string.h> - -#if USBH_LLD_DEBUG_ENABLE_TRACE -#define udbgf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define udbg(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define udbgf(f, ...) do {} while(0) -#define udbg(f, ...) do {} while(0) -#endif - -#if USBH_LLD_DEBUG_ENABLE_INFO -#define uinfof(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uinfo(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uinfof(f, ...) do {} while(0) -#define uinfo(f, ...) do {} while(0) -#endif - -#if USBH_LLD_DEBUG_ENABLE_WARNINGS -#define uwarnf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uwarn(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uwarnf(f, ...) do {} while(0) -#define uwarn(f, ...) do {} while(0) -#endif - -#if USBH_LLD_DEBUG_ENABLE_ERRORS -#define uerrf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uerr(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uerrf(f, ...) do {} while(0) -#define uerr(f, ...) do {} while(0) -#endif - -static void _transfer_completedI(usbh_ep_t *ep, usbh_urb_t *urb, usbh_urbstatus_t status); -static void _try_commit_np(USBHDriver *host); -static void otg_rxfifo_flush(USBHDriver *usbp); -static void otg_txfifo_flush(USBHDriver *usbp, uint32_t fifo); - -/*===========================================================================*/ -/* Little helper functions. */ -/*===========================================================================*/ -static inline void _move_to_pending_queue(usbh_ep_t *ep) { - list_move_tail(&ep->node, ep->pending_list); -} - -static inline usbh_urb_t *_active_urb(usbh_ep_t *ep) { - return list_first_entry(&ep->urb_list, usbh_urb_t, node); -} - -static inline void _save_dt_mask(usbh_ep_t *ep, uint32_t hctsiz) { - ep->dt_mask = hctsiz & HCTSIZ_DPID_MASK; -} - -#if 1 -#define _transfer_completed _transfer_completedI -#else -static inline void _transfer_completed(usbh_ep_t *ep, usbh_urb_t *urb, usbh_urbstatus_t status) { - osalSysLockFromISR(); - _transfer_completedI(ep, urb, status); - osalSysUnlockFromISR(); -} -#endif - -/*===========================================================================*/ -/* Functions called from many places. */ -/*===========================================================================*/ -static void _transfer_completedI(usbh_ep_t *ep, usbh_urb_t *urb, usbh_urbstatus_t status) { - osalDbgCheckClassI(); - - urb->queued = FALSE; - - /* remove URB from EP's queue */ - list_del_init(&urb->node); - - /* Call the callback function now, so that if it calls usbhURBSubmitI, - * the list_empty check below will be false. Also, note that the - * if (list_empty(&ep->node)) { - * ... - * } - * in usbh_lld_urb_submit will be false, since the endpoint is - * still in the active queue. - */ - _usbh_urb_completeI(urb, status); - - if (list_empty(&ep->urb_list)) { - /* no more URBs to process in this EP, remove EP from the host's queue */ - list_del_init(&ep->node); - } else { - /* more URBs to process */ - _move_to_pending_queue(ep); - } -} - -static void _halt_channel(USBHDriver *host, stm32_hc_management_t *hcm, usbh_lld_halt_reason_t reason) { - (void)host; - - if (hcm->halt_reason != USBH_LLD_HALTREASON_NONE) { - uwarnf("\t%s: Repeated halt (original=%d, new=%d)", hcm->ep->name, hcm->halt_reason, reason); - return; - } - -#if CH_DBG_ENABLE_CHECKS - if (usbhEPIsPeriodic(hcm->ep)) { - osalDbgCheck(host->otg->HPTXSTS & HPTXSTS_PTXQSAV_MASK); - } else { - osalDbgCheck(host->otg->HNPTXSTS & HPTXSTS_PTXQSAV_MASK); - } -#endif - - hcm->halt_reason = reason; - hcm->hc->HCCHAR |= HCCHAR_CHENA | HCCHAR_CHDIS; -} - -static void _release_channel(USBHDriver *host, stm32_hc_management_t *hcm) { -// static const char *reason[] = {"XFRC", "XFRC", "NAK", "STALL", "ERROR", "ABORT"}; -// udbgf("\t%s: release (%s)", hcm->ep->name, reason[hcm->halt_reason]); - hcm->hc->HCINTMSK = 0; - host->otg->HAINTMSK &= ~hcm->haintmsk; - hcm->halt_reason = USBH_LLD_HALTREASON_NONE; - if (usbhEPIsPeriodic(hcm->ep)) { - list_add(&hcm->node, &host->ch_free[0]); - } else { - list_add(&hcm->node, &host->ch_free[1]); - } - hcm->ep->xfer.hcm = 0; - hcm->ep = 0; -} - -static bool _activate_ep(USBHDriver *host, usbh_ep_t *ep) { - struct list_head *list; - uint16_t spc; - - osalDbgCheck(ep->xfer.hcm == NULL); - - if (usbhEPIsPeriodic(ep)) { - list = &host->ch_free[0]; - spc = (host->otg->HPTXSTS >> 16) & 0xff; - } else { - list = &host->ch_free[1]; - spc = (host->otg->HNPTXSTS >> 16) & 0xff; - } - - if (list_empty(list)) { - uwarnf("\t%s: No free %s channels", ep->name, usbhEPIsPeriodic(ep) ? "P" : "NP"); - return FALSE; - } - - if (spc <= STM32_USBH_MIN_QSPACE) { - uwarnf("\t%s: No space in %s Queue (spc=%d)", ep->name, usbhEPIsPeriodic(ep) ? "P" : "NP", spc); - return FALSE; - } - - /* get the first channel */ - stm32_hc_management_t *hcm = list_first_entry(list, stm32_hc_management_t, node); - osalDbgCheck((hcm->halt_reason == USBH_LLD_HALTREASON_NONE) && (hcm->ep == NULL)); - - usbh_urb_t *const urb = _active_urb(ep); - uint32_t hcintmsk = ep->hcintmsk; - uint32_t hcchar = ep->hcchar; - uint16_t mps = ep->wMaxPacketSize; - - uint32_t xfer_packets; - uint32_t xfer_len = 0; //Initialize just to shut up a compiler warning - - osalDbgCheck(urb->status == USBH_URBSTATUS_PENDING); - - /* check if the URB is a new one, or we must continue a previously started URB */ - if (urb->queued == FALSE) { - /* prepare EP for a new URB */ - if (ep->type == USBH_EPTYPE_CTRL) { - xfer_len = 8; - ep->xfer.buf = (uint8_t *)urb->setup_buff; - ep->dt_mask = HCTSIZ_DPID_SETUP; - ep->in = FALSE; - ep->xfer.u.ctrl_phase = USBH_LLD_CTRLPHASE_SETUP; - } else { - xfer_len = urb->requestedLength; - ep->xfer.buf = urb->buff; - } - ep->xfer.error_count = 0; - //urb->status = USBH_URBSTATUS_QUEUED; - } else { - osalDbgCheck(urb->requestedLength >= urb->actualLength); - - if (ep->type == USBH_EPTYPE_CTRL) { - switch (ep->xfer.u.ctrl_phase) { - case USBH_LLD_CTRLPHASE_SETUP: - xfer_len = 8; - ep->xfer.buf = (uint8_t *)urb->setup_buff; - ep->dt_mask = HCTSIZ_DPID_SETUP; - break; - case USBH_LLD_CTRLPHASE_DATA: - xfer_len = urb->requestedLength - urb->actualLength; - ep->xfer.buf = (uint8_t *) urb->buff + urb->actualLength; - break; - case USBH_LLD_CTRLPHASE_STATUS: - xfer_len = 0; - ep->dt_mask = HCTSIZ_DPID_DATA1; - ep->xfer.error_count = 0; - break; - default: - osalDbgCheck(0); - } - if (ep->in) { - hcintmsk |= HCINTMSK_DTERRM | HCINTMSK_BBERRM; - hcchar |= HCCHAR_EPDIR; - } - } else { - xfer_len = urb->requestedLength - urb->actualLength; - ep->xfer.buf = (uint8_t *) urb->buff + urb->actualLength; - } - - if (ep->xfer.error_count) - hcintmsk |= HCINTMSK_ACKM; - - } - ep->xfer.partial = 0; - - if (ep->type == USBH_EPTYPE_ISO) { - ep->dt_mask = HCTSIZ_DPID_DATA0; - - /* [USB 2.0 spec, 5.6.4]: A host must not issue more than 1 - * transaction in a (micro)frame for an isochronous endpoint - * unless the endpoint is high-speed, high-bandwidth. - */ - if (xfer_len > mps) - xfer_len = mps; - } else if (xfer_len > 0x7FFFF) { - xfer_len = 0x7FFFF - mps + 1; - } - - /* calculate required packets */ - if (xfer_len) { - xfer_packets = (xfer_len + mps - 1) / mps; - - if (xfer_packets > 0x3FF) { - xfer_packets = 0x3FF; - xfer_len = xfer_packets * mps; - } - } else { - xfer_packets = 1; /* Need 1 packet for transfer length of 0 */ - } - - if (ep->in) - xfer_len = xfer_packets * mps; - - /* Clear old interrupt conditions, - * configure transfer size, - * enable required interrupts */ - stm32_otg_host_chn_t *const hc = hcm->hc; - hc->HCINT = 0xffffffff; - hc->HCTSIZ = ep->dt_mask - | HCTSIZ_PKTCNT(xfer_packets) - | HCTSIZ_XFRSIZ(xfer_len); - hc->HCINTMSK = hcintmsk; - - /* Queue the transfer for the next frame (no effect for non-periodic transfers) */ - if (!(host->otg->HFNUM & 1)) - hcchar |= HCCHAR_ODDFRM; - - /* configure channel characteristics and queue a request */ - hc->HCCHAR = hcchar; - if (ep->in && (xfer_packets > 1)) { - /* For IN transfers, try to queue two back-to-back packets. - * This results in a 1% performance gain for Full Speed transfers - */ - if (--spc > STM32_USBH_MIN_QSPACE) { - hc->HCCHAR |= HCCHAR_CHENA; - } else { - uwarnf("\t%s: Could not queue back-to-back packets", ep->name); - } - } - - if (urb->queued == FALSE) { - urb->queued = TRUE; - udbgf("\t%s: Start (%dB)", ep->name, xfer_len); - } else { - udbgf("\t%s: Restart (%dB)", ep->name, xfer_len); - } - - ep->xfer.len = xfer_len; - ep->xfer.packets = (uint16_t)xfer_packets; - - /* remove the channel from the free list, link endpoint <-> channel and move to the active queue*/ - list_del(&hcm->node); - ep->xfer.hcm = hcm; - hcm->ep = ep; - list_move_tail(&ep->node, ep->active_list); - - - stm32_otg_t *const otg = host->otg; - - /* enable this channel's interrupt and global channel interrupt */ - otg->HAINTMSK |= hcm->haintmsk; - if (ep->in) { - otg->GINTMSK |= GINTMSK_HCM; - } else if (usbhEPIsPeriodic(ep)) { - otg->GINTMSK |= GINTMSK_HCM | GINTMSK_PTXFEM; - } else { - //TODO: write to the FIFO now - otg->GINTMSK |= GINTMSK_HCM | GINTMSK_NPTXFEM; - } - - return TRUE; -} - -static bool _update_urb(usbh_ep_t *ep, uint32_t hctsiz, usbh_urb_t *urb, bool completed) { - uint32_t len; - - if (!completed) { - len = ep->wMaxPacketSize * (ep->xfer.packets - ((hctsiz & HCTSIZ_PKTCNT_MASK) >> 19)); - } else { - if (ep->in) { - len = ep->xfer.len - ((hctsiz & HCTSIZ_XFRSIZ_MASK) >> 0); - } else { - len = ep->xfer.len; - } - osalDbgCheck(len == ep->xfer.partial); //TODO: if len == ep->xfer.partial, use this instead of the above code - } - -#if 1 - osalDbgAssert(urb->actualLength + len <= urb->requestedLength, "what happened?"); -#else - if (urb->actualLength + len > urb->requestedLength) { - uerrf("\t%s: Trimming actualLength %u -> %u", ep->name, urb->actualLength + len, urb->requestedLength); - urb->actualLength = urb->requestedLength; - return TRUE; - } -#endif - - urb->actualLength += len; - if ((urb->actualLength == urb->requestedLength) - || (ep->in && completed && (hctsiz & HCTSIZ_XFRSIZ_MASK))) - return TRUE; - - return FALSE; -} - -static void _try_commit_np(USBHDriver *host) { - usbh_ep_t *item, *tmp; - - list_for_each_entry_safe(item, usbh_ep_t, tmp, &host->ep_pending_lists[USBH_EPTYPE_CTRL], node) { - if (!_activate_ep(host, item)) - return; - } - - list_for_each_entry_safe(item, usbh_ep_t, tmp, &host->ep_pending_lists[USBH_EPTYPE_BULK], node) { - if (!_activate_ep(host, item)) - return; - } -} - -static void _try_commit_p(USBHDriver *host, bool sof) { - usbh_ep_t *item, *tmp; - - list_for_each_entry_safe(item, usbh_ep_t, tmp, &host->ep_pending_lists[USBH_EPTYPE_ISO], node) { - if (!_activate_ep(host, item)) - return; - } - - list_for_each_entry_safe(item, usbh_ep_t, tmp, &host->ep_pending_lists[USBH_EPTYPE_INT], node) { - osalDbgCheck(item); - /* TODO: improve this */ - if (sof && item->xfer.u.frame_counter) - --item->xfer.u.frame_counter; - - if (item->xfer.u.frame_counter == 0) { - if (!_activate_ep(host, item)) - return; - item->xfer.u.frame_counter = item->bInterval; - } - } - - if (list_empty(&host->ep_pending_lists[USBH_EPTYPE_ISO]) - && list_empty(&host->ep_pending_lists[USBH_EPTYPE_INT])) { - host->otg->GINTMSK &= ~GINTMSK_SOFM; - } else { - host->otg->GINTMSK |= GINTMSK_SOFM; - } -} - -static void _purge_queue(USBHDriver *host, struct list_head *list) { - usbh_ep_t *ep, *tmp; - list_for_each_entry_safe(ep, usbh_ep_t, tmp, list, node) { - usbh_urb_t *const urb = _active_urb(ep); - stm32_hc_management_t *const hcm = ep->xfer.hcm; - uwarnf("\t%s: Abort URB, USBH_URBSTATUS_DISCONNECTED", ep->name); - if (hcm) { - uwarnf("\t%s: URB had channel %d assigned, halt_reason = %d", ep->name, hcm - host->channels, hcm->halt_reason); - _release_channel(host, hcm); - _update_urb(ep, hcm->hc->HCTSIZ, urb, FALSE); - } - _transfer_completed(ep, urb, USBH_URBSTATUS_DISCONNECTED); - } -} - -static void _purge_active(USBHDriver *host) { - _purge_queue(host, &host->ep_active_lists[0]); - _purge_queue(host, &host->ep_active_lists[1]); - _purge_queue(host, &host->ep_active_lists[2]); - _purge_queue(host, &host->ep_active_lists[3]); -} - -static void _purge_pending(USBHDriver *host) { - _purge_queue(host, &host->ep_pending_lists[0]); - _purge_queue(host, &host->ep_pending_lists[1]); - _purge_queue(host, &host->ep_pending_lists[2]); - _purge_queue(host, &host->ep_pending_lists[3]); -} - -static uint32_t _write_packet(struct list_head *list, uint32_t space_available) { - usbh_ep_t *ep; - - uint32_t remaining = 0; - - list_for_each_entry(ep, usbh_ep_t, list, node) { - if (ep->in || (ep->xfer.hcm->halt_reason != USBH_LLD_HALTREASON_NONE)) - continue; - - int32_t rem = ep->xfer.len - ep->xfer.partial; - osalDbgCheck(rem >= 0); - if (rem <= 0) - continue; - - remaining += rem; - - if (!space_available) { - if (remaining) - break; - - continue; - } - - /* write one packet only */ - if (rem > ep->wMaxPacketSize) - rem = ep->wMaxPacketSize; - - /* round up to dwords */ - uint32_t words = (rem + 3) / 4; - - if (words > space_available) - words = space_available; - - space_available -= words; - - uint32_t written = words * 4; - if ((int32_t)written > rem) - written = rem; - - volatile uint32_t *dest = ep->xfer.hcm->fifo; - uint32_t *src = (uint32_t *)ep->xfer.buf; - udbgf("\t%s: write %d words (%dB), partial=%d", ep->name, words, written, ep->xfer.partial); - while (words--) { - *dest = *src++; - } - - ep->xfer.buf += written; - ep->xfer.partial += written; - - remaining -= written; - } - - return remaining; -} - - -/*===========================================================================*/ -/* API. */ -/*===========================================================================*/ - -void usbh_lld_ep_object_init(usbh_ep_t *ep) { -/* CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) - * STALL si sólo DAT/STAT si si si si no no ep->type != ISO && (ep->type != CTRL || ctrlphase != SETUP) - * ACK si si si si si si no no ep->type != ISO - * NAK si si si si si si no no ep->type != ISO - * BBERR si no si no si no si no ep->in - * TRERR si si si si si si si no ep->type != ISO || ep->in - * DTERR si no si no si no no no ep->type != ISO && ep->in - * FRMOR no no si si no no si si ep->type = PERIODIC - */ - USBHDriver *host = ep->device->host; - uint32_t hcintmsk = HCINTMSK_CHHM | HCINTMSK_XFRCM | HCINTMSK_AHBERRM; - - switch (ep->type) { - case USBH_EPTYPE_ISO: - hcintmsk |= HCINTMSK_FRMORM; - if (ep->in) { - hcintmsk |= HCINTMSK_TRERRM | HCINTMSK_BBERRM; - } - break; - case USBH_EPTYPE_INT: - hcintmsk |= HCINTMSK_TRERRM | HCINTMSK_FRMORM | HCINTMSK_STALLM | HCINTMSK_NAKM; - if (ep->in) { - hcintmsk |= HCINTMSK_DTERRM | HCINTMSK_BBERRM; - } - ep->xfer.u.frame_counter = 1; - break; - case USBH_EPTYPE_CTRL: - hcintmsk |= HCINTMSK_TRERRM | HCINTMSK_STALLM | HCINTMSK_NAKM; - break; - case USBH_EPTYPE_BULK: - hcintmsk |= HCINTMSK_TRERRM | HCINTMSK_STALLM | HCINTMSK_NAKM; - if (ep->in) { - hcintmsk |= HCINTMSK_DTERRM | HCINTMSK_BBERRM; - } - break; - default: - chDbgCheck(0); - } - ep->active_list = &host->ep_active_lists[ep->type]; - ep->pending_list = &host->ep_pending_lists[ep->type]; - INIT_LIST_HEAD(&ep->urb_list); - INIT_LIST_HEAD(&ep->node); - - ep->hcintmsk = hcintmsk; - ep->hcchar = HCCHAR_CHENA - | HCCHAR_DAD(ep->device->address) - | HCCHAR_MCNT(1) - | HCCHAR_EPTYP(ep->type) - | ((ep->device->speed == USBH_DEVSPEED_LOW) ? HCCHAR_LSDEV : 0) - | (ep->in ? HCCHAR_EPDIR : 0) - | HCCHAR_EPNUM(ep->address) - | HCCHAR_MPS(ep->wMaxPacketSize); -} - -void usbh_lld_ep_open(usbh_ep_t *ep) { - uinfof("\t%s: Open EP", ep->name); - ep->status = USBH_EPSTATUS_OPEN; - osalOsRescheduleS(); -} - -void usbh_lld_ep_close(usbh_ep_t *ep) { - usbh_urb_t *urb, *tmp; - uinfof("\t%s: Closing EP...", ep->name); - list_for_each_entry_safe(urb, usbh_urb_t, tmp, &ep->urb_list, node) { - uinfof("\t%s: Abort URB, USBH_URBSTATUS_DISCONNECTED", ep->name); - _usbh_urb_abort_and_waitS(urb, USBH_URBSTATUS_DISCONNECTED); - } - uinfof("\t%s: Closed", ep->name); - ep->status = USBH_EPSTATUS_CLOSED; - osalOsRescheduleS(); -} - -void usbh_lld_urb_submit(usbh_urb_t *urb) { - usbh_ep_t *const ep = urb->ep; - - /* add the URB to the EP's queue */ - list_add_tail(&urb->node, &ep->urb_list); - - /* check if the EP wasn't in any queue (pending nor active) */ - if (list_empty(&ep->node)) { - - /* add the EP to the pending queue */ - _move_to_pending_queue(ep); - - if (usbhEPIsPeriodic(ep)) { - ep->device->host->otg->GINTMSK |= GINTMSK_SOFM; - } else { - /* try to queue non-periodic transfers */ - _try_commit_np(ep->device->host); - } - } -} - -bool usbh_lld_urb_abort(usbh_urb_t *urb, usbh_urbstatus_t status) { - osalDbgCheck(usbhURBIsBusy(urb)); - - usbh_ep_t *const ep = urb->ep; - osalDbgCheck(ep); - stm32_hc_management_t *const hcm = ep->xfer.hcm; - - if ((hcm != NULL) && (urb == _active_urb(ep))) { - /* This URB is active (channel assigned, top of the EP's URB list) */ - - if (hcm->halt_reason == USBH_LLD_HALTREASON_NONE) { - /* The channel is not being halted */ - urb->status = status; - _halt_channel(ep->device->host, hcm, USBH_LLD_HALTREASON_ABORT); - } else { - /* The channel is being halted, so we can't re-halt it. The CHH interrupt will - * be in charge of completing the transfer, but the URB will not have the specified status. - */ - } - return FALSE; - } - - /* This URB is active, we can cancel it now */ - _transfer_completedI(ep, urb, status); - - return TRUE; -} - - -/*===========================================================================*/ -/* Channel Interrupts. */ -/*===========================================================================*/ - -//CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// si si si si si si no no ep->type != ISO && !ep->in -static inline void _ack_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - (void)host; - osalDbgAssert(hcm->ep->type != USBH_EPTYPE_ISO, "ACK should not happen in ISO endpoints"); - hcm->ep->xfer.error_count = 0; - hc->HCINTMSK &= ~HCINTMSK_ACKM; - udbgf("\t%s: ACK", hcm->ep->name); -} - -//CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// si no si no si no no no ep->type != ISO && ep->in -static inline void _dterr_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - (void)host; - osalDbgAssert(hcm->ep->in && (hcm->ep->type != USBH_EPTYPE_ISO), "DTERR should not happen in OUT or ISO endpoints"); -#if 0 - hc->HCINTMSK &= ~(HCINTMSK_DTERRM | HCINTMSK_ACKM); - hcm->ep->xfer.error_count = 0; - _halt_channel(host, hcm, USBH_LLD_HALTREASON_ERROR); -#else - /* restart directly, no need to halt it in this case */ - hcm->ep->xfer.error_count = 0; - hc->HCINTMSK &= ~HCINTMSK_ACKM; - hc->HCCHAR |= HCCHAR_CHENA; -#endif - uerrf("\t%s: DTERR", hcm->ep->name); -} - -//CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// si no si no si no si no ep->in -static inline void _bberr_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - osalDbgAssert(hcm->ep->in, "BBERR should not happen in OUT endpoints"); - hc->HCINTMSK &= ~HCINTMSK_BBERRM; - hcm->ep->xfer.error_count = 3; - _halt_channel(host, hcm, USBH_LLD_HALTREASON_ERROR); - uerrf("\t%s: BBERR", hcm->ep->name); -} - -///CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// si si si si si si si no ep->type != ISO || ep->in -static inline void _trerr_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - osalDbgAssert(hcm->ep->in || (hcm->ep->type != USBH_EPTYPE_ISO), "TRERR should not happen in ISO OUT endpoints"); - hc->HCINTMSK &= ~HCINTMSK_TRERRM; - ++hcm->ep->xfer.error_count; - _halt_channel(host, hcm, USBH_LLD_HALTREASON_ERROR); - uerrf("\t%s: TRERR", hcm->ep->name); -} - -//CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// no no si si no no si si ep->type = PERIODIC -static inline void _frmor_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - osalDbgAssert(usbhEPIsPeriodic(hcm->ep), "FRMOR should not happen in non-periodic endpoints"); - hc->HCINTMSK &= ~HCINTMSK_FRMORM; - hcm->ep->xfer.error_count = 3; - _halt_channel(host, hcm, USBH_LLD_HALTREASON_ERROR); - uerrf("\t%s: FRMOR", hcm->ep->name); -} - -//CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// si si si si si si no no ep->type != ISO -static inline void _nak_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - osalDbgAssert(hcm->ep->type != USBH_EPTYPE_ISO, "NAK should not happen in ISO endpoints"); - if (!hcm->ep->in || (hcm->ep->type == USBH_EPTYPE_INT)) { - hc->HCINTMSK &= ~HCINTMSK_NAKM; - _halt_channel(host, hcm, USBH_LLD_HALTREASON_NAK); - } else { - /* restart directly, no need to halt it in this case */ - hcm->ep->xfer.error_count = 0; - hc->HCINTMSK &= ~HCINTMSK_ACKM; - hc->HCCHAR |= HCCHAR_CHENA; - } - udbgf("\t%s: NAK", hcm->ep->name); -} - -//CTRL(IN) CTRL(OUT) INT(IN) INT(OUT) BULK(IN) BULK(OUT) ISO(IN) ISO(OUT) -// si sólo DAT/STAT si si si si no no ep->type != ISO && (ep->type != CTRL || ctrlphase != SETUP) -static inline void _stall_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - osalDbgAssert(hcm->ep->type != USBH_EPTYPE_ISO, "STALL should not happen in ISO endpoints"); - hc->HCINTMSK &= ~HCINTMSK_STALLM; - _halt_channel(host, hcm, USBH_LLD_HALTREASON_STALL); - uwarnf("\t%s: STALL", hcm->ep->name); -} - -static void _complete_bulk_int(USBHDriver *host, stm32_hc_management_t *hcm, usbh_ep_t *ep, usbh_urb_t *urb, uint32_t hctsiz) { - _release_channel(host, hcm); - _save_dt_mask(ep, hctsiz); - if (_update_urb(ep, hctsiz, urb, TRUE)) { - udbgf("\t%s: done", ep->name); - _transfer_completed(ep, urb, USBH_URBSTATUS_OK); - } else { - osalDbgCheck(urb->requestedLength > 0x7FFFF); - uwarnf("\t%s: incomplete", ep->name); - _move_to_pending_queue(ep); - } - if (usbhEPIsPeriodic(ep)) { - _try_commit_p(host, FALSE); - } else { - _try_commit_np(host); - } -} - -static void _complete_control(USBHDriver *host, stm32_hc_management_t *hcm, usbh_ep_t *ep, usbh_urb_t *urb, uint32_t hctsiz) { - osalDbgCheck(ep->xfer.u.ctrl_phase != USBH_LLD_CTRLPHASE_SETUP); - - _release_channel(host, hcm); - if (ep->xfer.u.ctrl_phase == USBH_LLD_CTRLPHASE_DATA) { - if (_update_urb(ep, hctsiz, urb, TRUE)) { - udbgf("\t%s: DATA done", ep->name); - ep->xfer.u.ctrl_phase = USBH_LLD_CTRLPHASE_STATUS; - ep->in = !ep->in; - } else { - osalDbgCheck(urb->requestedLength > 0x7FFFF); - uwarnf("\t%s: DATA incomplete", ep->name); - _save_dt_mask(ep, hctsiz); - } - _move_to_pending_queue(ep); - } else { - osalDbgCheck(ep->xfer.u.ctrl_phase == USBH_LLD_CTRLPHASE_STATUS); - udbgf("\t%s: STATUS done", ep->name); - _transfer_completed(ep, urb, USBH_URBSTATUS_OK); - } - _try_commit_np(host); -} - -static void _complete_control_setup(USBHDriver *host, stm32_hc_management_t *hcm, usbh_ep_t *ep, usbh_urb_t *urb) { - _release_channel(host, hcm); - if (urb->requestedLength) { - udbgf("\t%s: SETUP done -> DATA", ep->name); - ep->xfer.u.ctrl_phase = USBH_LLD_CTRLPHASE_DATA; - ep->in = *((uint8_t *)urb->setup_buff) & 0x80 ? TRUE : FALSE; - ep->dt_mask = HCTSIZ_DPID_DATA1; - ep->xfer.error_count = 0; - } else { - udbgf("\t%s: SETUP done -> STATUS", ep->name); - ep->in = TRUE; - ep->xfer.u.ctrl_phase = USBH_LLD_CTRLPHASE_STATUS; - } - _move_to_pending_queue(ep); - _try_commit_np(host); -} - -static void _complete_iso(USBHDriver *host, stm32_hc_management_t *hcm, usbh_ep_t *ep, usbh_urb_t *urb, uint32_t hctsiz) { - udbgf("\t%s: done", hcm->ep->name); - _release_channel(host, hcm); - _update_urb(ep, hctsiz, urb, TRUE); - _transfer_completed(ep, urb, USBH_URBSTATUS_OK); - _try_commit_p(host, FALSE); -} - -static inline void _xfrc_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - usbh_ep_t *const ep = hcm->ep; - usbh_urb_t *const urb = _active_urb(ep); - osalDbgCheck(urb); - uint32_t hctsiz = hc->HCTSIZ; - - hc->HCINTMSK &= ~HCINTMSK_XFRCM; - - switch (ep->type) { - case USBH_EPTYPE_CTRL: - if (ep->xfer.u.ctrl_phase == USBH_LLD_CTRLPHASE_SETUP) { - _complete_control_setup(host, hcm, ep, urb); - } else if (ep->in) { - _halt_channel(host, hcm, USBH_LLD_HALTREASON_XFRC); - } else { - _complete_control(host, hcm, ep, urb, hctsiz); - } - break; - - case USBH_EPTYPE_BULK: - if (ep->in) { - _halt_channel(host, hcm, USBH_LLD_HALTREASON_XFRC); - } else { - _complete_bulk_int(host, hcm, ep, urb, hctsiz); - } - break; - - case USBH_EPTYPE_INT: - if (ep->in && (hctsiz & HCTSIZ_PKTCNT_MASK)) { - _halt_channel(host, hcm, USBH_LLD_HALTREASON_XFRC); - } else { - _complete_bulk_int(host, hcm, ep, urb, hctsiz); - } - break; - - case USBH_EPTYPE_ISO: - if (ep->in && (hctsiz & HCTSIZ_PKTCNT_MASK)) { - _halt_channel(host, hcm, USBH_LLD_HALTREASON_XFRC); - } else { - _complete_iso(host, hcm, ep, urb, hctsiz); - } - break; - } -} - -static inline void _chh_int(USBHDriver *host, stm32_hc_management_t *hcm, stm32_otg_host_chn_t *hc) { - - usbh_ep_t *const ep = hcm->ep; - usbh_urb_t *const urb = _active_urb(ep); - osalDbgCheck(urb); - uint32_t hctsiz = hc->HCTSIZ; - usbh_lld_halt_reason_t reason = hcm->halt_reason; - - //osalDbgCheck(reason != USBH_LLD_HALTREASON_NONE); - if (reason == USBH_LLD_HALTREASON_NONE) { - uwarnf("\tCHH: ch=%d, USBH_LLD_HALTREASON_NONE", hcm - host->channels); - return; - } - - if (reason == USBH_LLD_HALTREASON_XFRC) { - osalDbgCheck(ep->in); - switch (ep->type) { - case USBH_EPTYPE_CTRL: - _complete_control(host, hcm, ep, urb, hctsiz); - break; - case USBH_EPTYPE_BULK: - case USBH_EPTYPE_INT: - _complete_bulk_int(host, hcm, ep, urb, hctsiz); - break; - case USBH_EPTYPE_ISO: - _complete_iso(host, hcm, ep, urb, hctsiz); - break; - } - } else { - _release_channel(host, hcm); - _save_dt_mask(ep, hctsiz); - bool done = _update_urb(ep, hctsiz, urb, FALSE); - - switch (reason) { - case USBH_LLD_HALTREASON_NAK: - if ((ep->type == USBH_EPTYPE_INT) && ep->in) { - _transfer_completed(ep, urb, USBH_URBSTATUS_TIMEOUT); - } else { - ep->xfer.error_count = 0; - _move_to_pending_queue(ep); - } - break; - - case USBH_LLD_HALTREASON_STALL: - if ((ep->type == USBH_EPTYPE_CTRL) && (ep->xfer.u.ctrl_phase == USBH_LLD_CTRLPHASE_SETUP)) { - uerrf("\t%s: Faulty device: STALLed SETUP phase", ep->name); - } - _transfer_completed(ep, urb, USBH_URBSTATUS_STALL); - break; - - case USBH_LLD_HALTREASON_ERROR: - if ((ep->type == USBH_EPTYPE_ISO) || done || (ep->xfer.error_count >= 3)) { - _transfer_completed(ep, urb, USBH_URBSTATUS_ERROR); - } else { - uerrf("\t%s: err=%d, done=%d, retry", ep->name, ep->xfer.error_count, done); - _move_to_pending_queue(ep); - } - break; - - case USBH_LLD_HALTREASON_ABORT: - uwarnf("\t%s: Abort", ep->name); - _transfer_completed(ep, urb, urb->status); - break; - - default: - osalDbgCheck(0); - break; - } - - if (usbhEPIsPeriodic(ep)) { - _try_commit_p(host, FALSE); - } else { - _try_commit_np(host); - } - } -} - -static void _hcint_n_int(USBHDriver *host, uint8_t chn) { - - stm32_hc_management_t *const hcm = &host->channels[chn]; - stm32_otg_host_chn_t *const hc = hcm->hc; - - uint32_t hcint = hc->HCINT; - hcint &= hc->HCINTMSK; - hc->HCINT = hcint; - - osalDbgCheck((hcint & HCINTMSK_AHBERRM) == 0); - osalDbgCheck(hcm->ep); - - if (hcint & HCINTMSK_STALLM) - _stall_int(host, hcm, hc); - if (hcint & HCINTMSK_NAKM) - _nak_int(host, hcm, hc); - if (hcint & HCINTMSK_ACKM) - _ack_int(host, hcm, hc); - if (hcint & HCINTMSK_TRERRM) - _trerr_int(host, hcm, hc); - if (hcint & HCINTMSK_BBERRM) - _bberr_int(host, hcm, hc); - if (hcint & HCINTMSK_FRMORM) - _frmor_int(host, hcm, hc); - if (hcint & HCINTMSK_DTERRM) - _dterr_int(host, hcm, hc); - if (hcint & HCINTMSK_XFRCM) - _xfrc_int(host, hcm, hc); - if (hcint & HCINTMSK_CHHM) - _chh_int(host, hcm, hc); -} - -static inline void _hcint_int(USBHDriver *host) { - uint32_t haint; - - haint = host->otg->HAINT; - haint &= host->otg->HAINTMSK; - - if (!haint) { - uerrf("HAINT=%08x, HAINTMSK=%08x", host->otg->HAINT, host->otg->HAINTMSK); - return; - } - -#if 1 //channel lookup loop - uint8_t i; - for (i = 0; haint && (i < host->channels_number); i++) { - if (haint & (1 << i)) { - _hcint_n_int(host, i); - haint &= ~(1 << i); - } - } -#else //faster calculation, with __CLZ (count leading zeroes) - while (haint) { - uint8_t chn = (uint8_t)(31 - __CLZ(haint)); - osalDbgAssert(chn < host->channels_number, "what?"); - haint &= ~host->channels[chn].haintmsk; - _hcint_n_int(host, chn); - } -#endif -} - - -/*===========================================================================*/ -/* Host interrupts. */ -/*===========================================================================*/ -static inline void _sof_int(USBHDriver *host) { - udbg("SOF"); - _try_commit_p(host, TRUE); -} - -static inline void _rxflvl_int(USBHDriver *host) { - - stm32_otg_t *const otg = host->otg; - - otg->GINTMSK &= ~GINTMSK_RXFLVLM; - while (otg->GINTSTS & GINTSTS_RXFLVL) { - uint32_t grxstsp = otg->GRXSTSP; - osalDbgCheck((grxstsp & GRXSTSP_CHNUM_MASK) < host->channels_number); - stm32_hc_management_t *const hcm = &host->channels[grxstsp & GRXSTSP_CHNUM_MASK]; - uint32_t hctsiz = hcm->hc->HCTSIZ; - - if ((grxstsp & GRXSTSP_PKTSTS_MASK) == GRXSTSP_PKTSTS(2)) { - /* 0010: IN data packet received */ - usbh_ep_t *const ep = hcm->ep; - osalDbgCheck(ep); - - /* restart the channel ASAP */ - if (hctsiz & HCTSIZ_PKTCNT_MASK) { -#if CH_DBG_ENABLE_CHECKS - if (usbhEPIsPeriodic(ep)) { - osalDbgCheck(host->otg->HPTXSTS & HPTXSTS_PTXQSAV_MASK); - } else { - osalDbgCheck(host->otg->HNPTXSTS & HPTXSTS_PTXQSAV_MASK); - } -#endif - hcm->hc->HCCHAR |= HCCHAR_CHENA; - } - - udbgf("\t%s: RXFLVL rx=%dB, rem=%dB (%dpkts)", - ep->name, - (grxstsp & GRXSTSP_BCNT_MASK) >> 4, - (hctsiz & HCTSIZ_XFRSIZ_MASK), - (hctsiz & HCTSIZ_PKTCNT_MASK) >> 19); - - /* Read */ - uint32_t *dest = (uint32_t *)ep->xfer.buf; - volatile uint32_t *const src = hcm->fifo; - - uint32_t bcnt = (grxstsp & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF; - osalDbgCheck(bcnt + ep->xfer.partial <= ep->xfer.len); - - //TODO: optimize this - uint32_t words = bcnt / 4; - uint8_t bytes = bcnt & 3; - while (words--) { - *dest++ = *src; - } - if (bytes) { - uint32_t r = *src; - uint8_t *bsrc = (uint8_t *)&r; - uint8_t *bdest = (uint8_t *)dest; - do { - *bdest++ = *bsrc++; - } while (--bytes); - } - - ep->xfer.buf += bcnt; - ep->xfer.partial += bcnt; - -#if 0 //STM32_USBH_CHANNELS_NP > 1 - /* check bug */ - if (hctsiz & HCTSIZ_PKTCNT_MASK) { - uint32_t pkt = (hctsiz & HCTSIZ_PKTCNT_MASK) >> 19; - uint32_t siz = (hctsiz & HCTSIZ_XFRSIZ_MASK); - if (pkt * ep->wMaxPacketSize != siz) { - uerrf("\t%s: whatttt???", ep->name); - } - } -#endif - -#if USBH_DEBUG_ENABLE && USBH_LLD_DEBUG_ENABLE_ERRORS - } else { - /* 0011: IN transfer completed (triggers an interrupt) - * 0101: Data toggle error (triggers an interrupt) - * 0111: Channel halted (triggers an interrupt) - */ - switch (grxstsp & GRXSTSP_PKTSTS_MASK) { - case GRXSTSP_PKTSTS(3): - case GRXSTSP_PKTSTS(5): - case GRXSTSP_PKTSTS(7): - break; - default: - uerrf("\tRXFLVL: ch=%d, UNK=%d", grxstsp & GRXSTSP_CHNUM_MASK, (grxstsp & GRXSTSP_PKTSTS_MASK) >> 17); - break; - } -#endif - } - } - otg->GINTMSK |= GINTMSK_RXFLVLM; -} - -static inline void _nptxfe_int(USBHDriver *host) { - uint32_t rem; - stm32_otg_t *const otg = host->otg; - - rem = _write_packet(&host->ep_active_lists[USBH_EPTYPE_CTRL], - otg->HNPTXSTS & HPTXSTS_PTXFSAVL_MASK); - - rem += _write_packet(&host->ep_active_lists[USBH_EPTYPE_BULK], - otg->HNPTXSTS & HPTXSTS_PTXFSAVL_MASK); - -// if (rem) -// otg->GINTMSK |= GINTMSK_NPTXFEM; - - if (!rem) - otg->GINTMSK &= ~GINTMSK_NPTXFEM; - -} - -static inline void _ptxfe_int(USBHDriver *host) { - //TODO: implement - (void)host; - uinfo("PTXFE"); -} - -static inline void _discint_int(USBHDriver *host) { - uint32_t hprt = host->otg->HPRT; - - uwarn("\tDISCINT"); - - if (!(hprt & HPRT_PCSTS)) { - host->rootport.lld_status &= ~(USBH_PORTSTATUS_CONNECTION | USBH_PORTSTATUS_ENABLE); - host->rootport.lld_c_status |= USBH_PORTSTATUS_C_CONNECTION | USBH_PORTSTATUS_C_ENABLE; - } - _purge_active(host); - _purge_pending(host); -} - -static inline void _hprtint_int(USBHDriver *host) { - stm32_otg_t *const otg = host->otg; - uint32_t hprt = otg->HPRT; - - /* note: writing PENA = 1 actually disables the port */ - uint32_t hprt_clr = hprt & ~(HPRT_PENA | HPRT_PCDET | HPRT_PENCHNG | HPRT_POCCHNG); - - if (hprt & HPRT_PCDET) { - hprt_clr |= HPRT_PCDET; - if (hprt & HPRT_PCSTS) { - uinfo("\tHPRT: Port connection detected"); - host->rootport.lld_status |= USBH_PORTSTATUS_CONNECTION; - host->rootport.lld_c_status |= USBH_PORTSTATUS_C_CONNECTION; - } else { - uinfo("\tHPRT: Port disconnection detected"); - } - } - - if (hprt & HPRT_PENCHNG) { - hprt_clr |= HPRT_PENCHNG; - if (hprt & HPRT_PENA) { - uinfo("\tHPRT: Port enabled"); - host->rootport.lld_status |= USBH_PORTSTATUS_ENABLE; - host->rootport.lld_status &= ~(USBH_PORTSTATUS_HIGH_SPEED | USBH_PORTSTATUS_LOW_SPEED); - - /* Make sure the FIFOs are flushed. */ - otg_txfifo_flush(host, 0x10); - otg_rxfifo_flush(host); - - /* Clear all pending HC Interrupts */ - uint8_t i; - for (i = 0; i < host->channels_number; i++) { - otg->hc[i].HCINTMSK = 0; - otg->hc[i].HCINT = 0xFFFFFFFF; - } - - /* configure speed */ - if ((hprt & HPRT_PSPD_MASK) == HPRT_PSPD_LS) { - host->rootport.lld_status |= USBH_PORTSTATUS_LOW_SPEED; - otg->HFIR = 6000; - otg->HCFG = (otg->HCFG & ~HCFG_FSLSPCS_MASK) | HCFG_FSLSPCS_6; - } else { - otg->HFIR = 48000; - otg->HCFG = (otg->HCFG & ~HCFG_FSLSPCS_MASK) | HCFG_FSLSPCS_48; - } - } else { - if (hprt & HPRT_PCSTS) { - if (hprt & HPRT_POCA) { - uerr("\tHPRT: Port disabled due to overcurrent"); - } else { - uerr("\tHPRT: Port disabled due to port babble"); - } - } else { - uerr("\tHPRT: Port disabled due to disconnect"); - } - - _purge_active(host); - _purge_pending(host); - - host->rootport.lld_status &= ~USBH_PORTSTATUS_ENABLE; - } - host->rootport.lld_c_status |= USBH_PORTSTATUS_C_ENABLE; - } - - if (hprt & HPRT_POCCHNG) { - hprt_clr |= HPRT_POCCHNG; - if (hprt & HPRT_POCA) { - uerr("\tHPRT: Overcurrent"); - host->rootport.lld_status |= USBH_PORTSTATUS_OVERCURRENT; - } else { - udbg("\tHPRT: Clear overcurrent"); - host->rootport.lld_status &= ~USBH_PORTSTATUS_OVERCURRENT; - } - host->rootport.lld_c_status |= USBH_PORTSTATUS_C_OVERCURRENT; - } - - otg->HPRT = hprt_clr; -} - -static void usb_lld_serve_interrupt(USBHDriver *host) { - osalDbgCheck(host && (host->status != USBH_STATUS_STOPPED)); - - stm32_otg_t *const otg = host->otg; - uint32_t gintsts = otg->GINTSTS; - - /* check host mode */ - if (!(gintsts & GINTSTS_CMOD)) { - uerr("Device mode"); - otg->GINTSTS = gintsts; - return; - } - - /* check mismatch */ - if (gintsts & GINTSTS_MMIS) { - uerr("Mode Mismatch"); - otg->GINTSTS = gintsts; - return; - } - - gintsts &= otg->GINTMSK; - if (!gintsts) { - uwarnf("GINTSTS=%08x, GINTMSK=%08x", otg->GINTSTS, otg->GINTMSK); - return; - } -// otg->GINTMSK &= ~(GINTMSK_NPTXFEM | GINTMSK_PTXFEM); - otg->GINTSTS = gintsts; - - if (gintsts & GINTSTS_SOF) - _sof_int(host); - if (gintsts & GINTSTS_RXFLVL) - _rxflvl_int(host); - if (gintsts & GINTSTS_HPRTINT) - _hprtint_int(host); - if (gintsts & GINTSTS_DISCINT) - _discint_int(host); - if (gintsts & GINTSTS_HCINT) - _hcint_int(host); - if (gintsts & GINTSTS_NPTXFE) - _nptxfe_int(host); - if (gintsts & GINTSTS_PTXFE) - _ptxfe_int(host); - if (gintsts & GINTSTS_IPXFR) { - uerr("IPXFRM"); - } -} - - -/*===========================================================================*/ -/* Interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_USBH_USE_OTG1 -OSAL_IRQ_HANDLER(STM32_OTG1_HANDLER) { - OSAL_IRQ_PROLOGUE(); - osalSysLockFromISR(); - usb_lld_serve_interrupt(&USBHD1); - osalSysUnlockFromISR(); - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_USBH_USE_OTG2 -OSAL_IRQ_HANDLER(STM32_OTG2_HANDLER) { - OSAL_IRQ_PROLOGUE(); - osalSysLockFromISR(); - usb_lld_serve_interrupt(&USBHD2); - osalSysUnlockFromISR(); - OSAL_IRQ_EPILOGUE(); -} -#endif - - -/*===========================================================================*/ -/* Initialization functions. */ -/*===========================================================================*/ -static void otg_core_reset(USBHDriver *usbp) { - stm32_otg_t *const otgp = usbp->otg; - - /* Wait AHB idle condition.*/ - while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) - ; - - osalSysPolledDelayX(64); - - /* Core reset and delay of at least 3 PHY cycles.*/ - otgp->GRSTCTL = GRSTCTL_CSRST; - while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0) - ; - - osalSysPolledDelayX(24); - - /* Wait AHB idle condition.*/ - while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) - ; -} - -static void otg_rxfifo_flush(USBHDriver *usbp) { - stm32_otg_t *const otgp = usbp->otg; - - otgp->GRSTCTL = GRSTCTL_RXFFLSH; - while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0) - ; - /* Wait for 3 PHY Clocks.*/ - osalSysPolledDelayX(24); -} - -static void otg_txfifo_flush(USBHDriver *usbp, uint32_t fifo) { - stm32_otg_t *const otgp = usbp->otg; - - otgp->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH; - while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0) - ; - /* Wait for 3 PHY Clocks.*/ - osalSysPolledDelayX(24); -} - -static void _init(USBHDriver *host) { - int i; - - usbhObjectInit(host); - -#if STM32_USBH_USE_OTG1 -#if STM32_USBH_USE_OTG2 - if (&USBHD1 == host) { -#endif - host->otg = OTG_FS; - host->channels_number = STM32_OTG1_CHANNELS_NUMBER; -#if STM32_USBH_USE_OTG2 - } -#endif -#endif - -#if STM32_USBH_USE_OTG2 -#if STM32_USBH_USE_OTG1 - if (&USBHD2 == host) { -#endif - host->otg = OTG_HS; - host->channels_number = STM32_OTG2_CHANNELS_NUMBER; -#if STM32_USBH_USE_OTG1 - } -#endif -#endif - INIT_LIST_HEAD(&host->ch_free[0]); - INIT_LIST_HEAD(&host->ch_free[1]); - for (i = 0; i < host->channels_number; i++) { - host->channels[i].haintmsk = 1 << i; - host->channels[i].hc = &host->otg->hc[i]; - host->channels[i].fifo = host->otg->FIFO[i]; - if (i < STM32_USBH_CHANNELS_NP) { - list_add_tail(&host->channels[i].node, &host->ch_free[1]); - } else { - list_add_tail(&host->channels[i].node, &host->ch_free[0]); - } - } - for (i = 0; i < 4; i++) { - INIT_LIST_HEAD(&host->ep_active_lists[i]); - INIT_LIST_HEAD(&host->ep_pending_lists[i]); - } -} - -void usbh_lld_init(void) { -#if STM32_USBH_USE_OTG1 - _init(&USBHD1); -#endif -#if STM32_USBH_USE_OTG2 - _init(&USBHD2); -#endif -} - -static void _usbh_start(USBHDriver *usbh) { - stm32_otg_t *const otgp = usbh->otg; - - /* Clock activation.*/ -#if STM32_USBH_USE_OTG1 -#if STM32_USBH_USE_OTG2 - if (&USBHD1 == usbh) { -#endif - /* OTG FS clock enable and reset.*/ - rccEnableOTG_FS(FALSE); - rccResetOTG_FS(); - - otgp->GINTMSK = 0; - - /* Enables IRQ vector.*/ - nvicEnableVector(STM32_OTG1_NUMBER, STM32_USB_OTG1_IRQ_PRIORITY); -#if STM32_USBH_USE_OTG2 - } -#endif -#endif - -#if STM32_USBH_USE_OTG2 -#if STM32_USBH_USE_OTG1 - if (&USBHD2 == usbh) { -#endif - /* OTG HS clock enable and reset.*/ - rccEnableOTG_HS(FALSE); - rccResetOTG_HS(); - - otgp->GINTMSK = 0; - - /* Enables IRQ vector.*/ - nvicEnableVector(STM32_OTG2_NUMBER, STM32_USB_OTG2_IRQ_PRIORITY); -#if STM32_USBH_USE_OTG1 - } -#endif -#endif - - otgp->GUSBCFG = GUSBCFG_PHYSEL | GUSBCFG_TRDT(5); - - otg_core_reset(usbh); - - otgp->GCCFG = GCCFG_PWRDWN; - - /* Forced host mode. */ - otgp->GUSBCFG = GUSBCFG_FHMOD | GUSBCFG_PHYSEL | GUSBCFG_TRDT(5); - - /* PHY enabled.*/ - otgp->PCGCCTL = 0; - - /* Internal FS PHY activation.*/ -#if defined(BOARD_OTG_NOVBUSSENS) - otgp->GCCFG = GCCFG_NOVBUSSENS | GCCFG_PWRDWN; -#else - otgp->GCCFG = GCCFG_PWRDWN; -#endif - - /* 48MHz 1.1 PHY.*/ - otgp->HCFG = HCFG_FSLSS | HCFG_FSLSPCS_48; - - /* Interrupts on FIFOs half empty.*/ - otgp->GAHBCFG = 0; - - otgp->GOTGINT = 0xFFFFFFFF; - - otgp->HPRT |= HPRT_PPWR; - - /* without this delay, the FIFO sizes are set INcorrectly */ - osalThreadSleepS(MS2ST(200)); - -#define HNPTXFSIZ DIEPTXF0 -#if STM32_USBH_USE_OTG1 -#if STM32_USBH_USE_OTG2 - if (&USBHD1 == usbh) { -#endif - otgp->GRXFSIZ = GRXFSIZ_RXFD(STM32_OTG1_RXFIFO_SIZE / 4); - otgp->HNPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG1_RXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG1_NPTXFIFO_SIZE / 4); - otgp->HPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG1_RXFIFO_SIZE / 4) + (STM32_OTG1_NPTXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG1_PTXFIFO_SIZE / 4); -#if STM32_USBH_USE_OTG2 - } -#endif -#endif -#if STM32_USBH_USE_OTG2 -#if STM32_USBH_USE_OTG1 - if (&USBHD2 == usbh) { -#endif - otgp->GRXFSIZ = GRXFSIZ_RXFD(STM32_OTG2_RXFIFO_SIZE / 4); - otgp->HNPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG2_RXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG2_NPTXFIFO_SIZE / 4); - otgp->HPTXFSIZ = HPTXFSIZ_PTXSA((STM32_OTG2_RXFIFO_SIZE / 4) + (STM32_OTG2_NPTXFIFO_SIZE / 4)) | HPTXFSIZ_PTXFD(STM32_OTG2_PTXFIFO_SIZE / 4); -#if STM32_USBH_USE_OTG1 - } -#endif -#endif - - otg_txfifo_flush(usbh, 0x10); - otg_rxfifo_flush(usbh); - - otgp->GINTSTS = 0xffffffff; - otgp->GINTMSK = GINTMSK_DISCM /*| GINTMSK_PTXFEM*/ | GINTMSK_HCM | GINTMSK_HPRTM - /*| GINTMSK_IPXFRM | GINTMSK_NPTXFEM*/ | GINTMSK_RXFLVLM - /*| GINTMSK_SOFM */ | GINTMSK_MMISM; - - usbh->rootport.lld_status = USBH_PORTSTATUS_POWER; - usbh->rootport.lld_c_status = 0; - - /* Global interrupts enable.*/ - otgp->GAHBCFG |= GAHBCFG_GINTMSK; -} - -void usbh_lld_start(USBHDriver *usbh) { - if (usbh->status != USBH_STATUS_STOPPED) return; - _usbh_start(usbh); -} - -/*===========================================================================*/ -/* Root Hub request handler. */ -/*===========================================================================*/ -usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestType, uint8_t bRequest, - uint16_t wvalue, uint16_t windex, uint16_t wlength, uint8_t *buf) { - - uint16_t typereq = (bmRequestType << 8) | bRequest; - - switch (typereq) { - case ClearHubFeature: - switch (wvalue) { - case USBH_HUB_FEAT_C_HUB_LOCAL_POWER: - case USBH_HUB_FEAT_C_HUB_OVER_CURRENT: - break; - default: - osalDbgAssert(0, "invalid wvalue"); - } - break; - - case ClearPortFeature: - chDbgAssert(windex == 1, "invalid windex"); - - osalSysLock(); - switch (wvalue) { - case USBH_PORT_FEAT_ENABLE: - case USBH_PORT_FEAT_SUSPEND: - case USBH_PORT_FEAT_POWER: - chDbgAssert(0, "unimplemented"); /* TODO */ - break; - - case USBH_PORT_FEAT_INDICATOR: - chDbgAssert(0, "unsupported"); - break; - - case USBH_PORT_FEAT_C_CONNECTION: - usbh->rootport.lld_c_status &= ~USBH_PORTSTATUS_C_CONNECTION; - break; - - case USBH_PORT_FEAT_C_RESET: - usbh->rootport.lld_c_status &= ~USBH_PORTSTATUS_C_RESET; - break; - - case USBH_PORT_FEAT_C_ENABLE: - usbh->rootport.lld_c_status &= ~USBH_PORTSTATUS_C_ENABLE; - break; - - case USBH_PORT_FEAT_C_SUSPEND: - usbh->rootport.lld_c_status &= ~USBH_PORTSTATUS_C_SUSPEND; - break; - - case USBH_PORT_FEAT_C_OVERCURRENT: - usbh->rootport.lld_c_status &= USBH_PORTSTATUS_C_OVERCURRENT; - break; - - default: - osalDbgAssert(0, "invalid wvalue"); - break; - } - osalOsRescheduleS(); - osalSysUnlock(); - break; - - case GetHubDescriptor: - /*dev_dbg(hsotg->dev, "GetHubDescriptor\n"); - hub_desc = (struct usb_hub_descriptor *)buf; - hub_desc->bDescLength = 9; - hub_desc->bDescriptorType = USB_DT_HUB; - hub_desc->bNbrPorts = 1; - hub_desc->wHubCharacteristics = - cpu_to_le16(HUB_CHAR_COMMON_LPSM | - HUB_CHAR_INDV_PORT_OCPM); - hub_desc->bPwrOn2PwrGood = 1; - hub_desc->bHubContrCurrent = 0; - hub_desc->u.hs.DeviceRemovable[0] = 0; - hub_desc->u.hs.DeviceRemovable[1] = 0xff;*/ - break; - - case GetHubStatus: - osalDbgCheck(wlength >= 4); - *(uint32_t *)buf = 0; - break; - - case GetPortStatus: - chDbgAssert(windex == 1, "invalid windex"); - osalDbgCheck(wlength >= 4); - osalSysLock(); - *(uint32_t *)buf = usbh->rootport.lld_status | (usbh->rootport.lld_c_status << 16); - osalOsRescheduleS(); - osalSysUnlock(); - break; - - case SetHubFeature: - chDbgAssert(0, "unsupported"); - break; - - case SetPortFeature: - chDbgAssert(windex == 1, "invalid windex"); - - switch (wvalue) { - case USBH_PORT_FEAT_TEST: - case USBH_PORT_FEAT_SUSPEND: - case USBH_PORT_FEAT_POWER: - chDbgAssert(0, "unimplemented"); /* TODO */ - break; - - case USBH_PORT_FEAT_RESET: { - osalSysLock(); - stm32_otg_t *const otg = usbh->otg; - uint32_t hprt; - otg->PCGCCTL = 0; - hprt = otg->HPRT; - /* note: writing PENA = 1 actually disables the port */ - hprt &= ~(HPRT_PSUSP | HPRT_PENA | HPRT_PCDET | HPRT_PENCHNG | HPRT_POCCHNG ); - otg->HPRT = hprt | HPRT_PRST; - osalThreadSleepS(MS2ST(60)); - otg->HPRT = hprt; - usbh->rootport.lld_c_status |= USBH_PORTSTATUS_C_RESET; - osalOsRescheduleS(); - osalSysUnlock(); - } break; - - case USBH_PORT_FEAT_INDICATOR: - chDbgAssert(0, "unsupported"); - break; - - default: - osalDbgAssert(0, "invalid wvalue"); - break; - } - break; - - default: - osalDbgAssert(0, "invalid typereq"); - break; - } - - return USBH_URBSTATUS_OK; -} - -uint8_t usbh_lld_roothub_get_statuschange_bitmap(USBHDriver *usbh) { - osalSysLock(); - if (usbh->rootport.lld_c_status) { - osalOsRescheduleS(); - osalSysUnlock(); - return 1 << 1; - } - osalOsRescheduleS(); - osalSysUnlock(); - return 0; -} - - -#endif diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h deleted file mode 100644 index e8df749..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef USBH_LLD_H_ -#define USBH_LLD_H_ - -#include "hal.h" - -#if HAL_USE_USBH - -#include "osal.h" -#include "stm32_otg.h" - -/* TODO: - * - * - Implement ISO/INT OUT and test - * - Consider DMA mode for OTG_HS, consider external PHY for HS. - * - Implement a data pump thread, so we don't have to copy data from the ISR - * This might be a bad idea for small endpoint packet sizes (the context switch - * could be longer than the copy) - */ - -typedef enum { - USBH_LLD_CTRLPHASE_SETUP, - USBH_LLD_CTRLPHASE_DATA, - USBH_LLD_CTRLPHASE_STATUS -} usbh_lld_ctrlphase_t; - -typedef enum { - USBH_LLD_HALTREASON_NONE, - USBH_LLD_HALTREASON_XFRC, - USBH_LLD_HALTREASON_NAK, - USBH_LLD_HALTREASON_STALL, - USBH_LLD_HALTREASON_ERROR, - USBH_LLD_HALTREASON_ABORT -} usbh_lld_halt_reason_t; - - -typedef struct stm32_hc_management { - struct list_head node; - - stm32_otg_host_chn_t *hc; - volatile uint32_t *fifo; - usbh_ep_t *ep; - uint16_t haintmsk; - usbh_lld_halt_reason_t halt_reason; -} stm32_hc_management_t; - - -#define _usbhdriver_ll_data \ - stm32_otg_t *otg; \ - /* channels */ \ - uint8_t channels_number; \ - stm32_hc_management_t channels[STM32_OTG2_CHANNELS_NUMBER]; \ - struct list_head ch_free[2]; \ - /* Enpoints being processed */ \ - struct list_head ep_active_lists[4]; \ - /* Pending endpoints */ \ - struct list_head ep_pending_lists[4]; - - -#define _usbh_ep_ll_data \ - struct list_head *active_list; /* shortcut to ep list */ \ - struct list_head *pending_list; /* shortcut to ep list */ \ - struct list_head urb_list; /* list of URBs queued in this EP */ \ - struct list_head node; /* this EP */ \ - uint32_t hcintmsk; \ - uint32_t hcchar; \ - uint32_t dt_mask; /* data-toggle mask */ \ - /* current transfer */ \ - struct { \ - stm32_hc_management_t *hcm; /* assigned channel */ \ - uint32_t len; /* this transfer's total length */ \ - uint8_t *buf; /* this transfer's buffer */ \ - uint32_t partial; /* this transfer's partial length */\ - uint16_t packets; /* packets allocated */ \ - union { \ - uint32_t frame_counter; /* frame counter (for INT) */ \ - usbh_lld_ctrlphase_t ctrl_phase; /* control phase (for CTRL) */ \ - } u; \ - uint8_t error_count; /* error count */ \ - } xfer; - - - - - -#define _usbh_port_ll_data \ - uint16_t lld_c_status; \ - uint16_t lld_status; - -#define _usbh_device_ll_data - -#define _usbh_hub_ll_data - -#define _usbh_urb_ll_data \ - struct list_head node; \ - bool queued; - - -#define usbh_lld_urb_object_init(urb) \ - do { \ - osalDbgAssert(((uint32_t)urb->buff & 3) == 0, \ - "use USBH_DEFINE_BUFFER() to declare the IO buffers"); \ - urb->queued = FALSE; \ - } while (0) - - -#define usbh_lld_urb_object_reset(urb) \ - do { \ - osalDbgAssert(urb->queued == FALSE, "wrong state"); \ - osalDbgAssert(((uint32_t)urb->buff & 3) == 0, \ - "use USBH_DEFINE_BUFFER() to declare the IO buffers"); \ - } while (0) - - - -void usbh_lld_init(void); -void usbh_lld_start(USBHDriver *usbh); -void usbh_lld_ep_object_init(usbh_ep_t *ep); -void usbh_lld_ep_open(usbh_ep_t *ep); -void usbh_lld_ep_close(usbh_ep_t *ep); -void usbh_lld_urb_submit(usbh_urb_t *urb); -bool usbh_lld_urb_abort(usbh_urb_t *urb, usbh_urbstatus_t status); -usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestType, uint8_t bRequest, - uint16_t wvalue, uint16_t windex, uint16_t wlength, uint8_t *buf); -uint8_t usbh_lld_roothub_get_statuschange_bitmap(USBHDriver *usbh); - -#define usbh_lld_epreset(ep) do {(ep)->dt_mask = HCTSIZ_DPID_DATA0;} while (0); - -#ifdef __IAR_SYSTEMS_ICC__ -#define USBH_LLD_DEFINE_BUFFER(type, name) type name -#else -#define USBH_LLD_DEFINE_BUFFER(type, name) type name __attribute__((aligned(4))) -#endif - -#endif - -#endif /* USBH_LLD_H_ */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/STM32F0xx/platform.mk b/ChibiOS_16.1.5/community/os/hal/ports/STM32/STM32F0xx/platform.mk deleted file mode 100644 index 377acdf..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/STM32F0xx/platform.mk +++ /dev/null @@ -1,9 +0,0 @@ -include ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/platform.mk - -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ - -PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/STM32F1xx/platform.mk b/ChibiOS_16.1.5/community/os/hal/ports/STM32/STM32F1xx/platform.mk deleted file mode 100644 index a8f21bc..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/STM32F1xx/platform.mk +++ /dev/null @@ -1,15 +0,0 @@ -include ${CHIBIOS}/os/hal/ports/STM32/STM32F1xx/platform.mk - -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c - -PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/STM32F3xx/platform.mk b/ChibiOS_16.1.5/community/os/hal/ports/STM32/STM32F3xx/platform.mk deleted file mode 100644 index 92f033c..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/STM32F3xx/platform.mk +++ /dev/null @@ -1,10 +0,0 @@ -include ${CHIBIOS}/os/hal/ports/STM32/STM32F3xx/platform.mk - -PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ - -PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD diff --git a/ChibiOS_16.1.5/community/os/hal/ports/STM32/STM32F4xx/platform.mk b/ChibiOS_16.1.5/community/os/hal/ports/STM32/STM32F4xx/platform.mk deleted file mode 100644 index c312e72..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/STM32/STM32F4xx/platform.mk +++ /dev/null @@ -1,21 +0,0 @@ -include ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx/platform.mk
-
-PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c
-
-PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1 \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_ext_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_ext_lld.c deleted file mode 100644 index efe6421..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_ext_lld.c +++ /dev/null @@ -1,981 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Tiva/ext_lld.c - * @brief Tiva EXT subsystem low level driver source. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Generic interrupt serving code for multiple pins per interrupt - * handler. - */ -#define ext_lld_serve_port_interrupt(gpiop, start) \ - do { \ - uint32_t mis = gpiop->MIS; \ - \ - gpiop->ICR = mis; \ - \ - if (mis & (1 << 0)) { \ - EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0); \ - } \ - if (mis & (1 << 1)) { \ - EXTD1.config->channels[start + 1].cb(&EXTD1, start + 1); \ - } \ - if (mis & (1 << 2)) { \ - EXTD1.config->channels[start + 2].cb(&EXTD1, start + 2); \ - } \ - if (mis & (1 << 3)) { \ - EXTD1.config->channels[start + 3].cb(&EXTD1, start + 3); \ - } \ - if (mis & (1 << 4)) { \ - EXTD1.config->channels[start + 4].cb(&EXTD1, start + 4); \ - } \ - if (mis & (1 << 5)) { \ - EXTD1.config->channels[start + 5].cb(&EXTD1, start + 5); \ - } \ - if (mis & (1 << 6)) { \ - EXTD1.config->channels[start + 6].cb(&EXTD1, start + 6); \ - } \ - if (mis & (1 << 7)) { \ - EXTD1.config->channels[start + 7].cb(&EXTD1, start + 7); \ - } \ - } while (0); - -/** - * @brief Generic interrupt serving code for single pin per interrupt - * handler. - */ -#define ext_lld_serve_pin_interrupt(gpiop, start, pin) \ - do { \ - gpiop->ICR = (1 << pin); \ - EXTD1.config->channels[start].cb(&EXTD1, start); \ - } while (0); - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EXTD1 driver identifier. - */ -EXTDriver EXTD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -const ioportid_t gpio[] = -{ -#if TIVA_HAS_GPIOA - GPIOA, -#endif -#if TIVA_HAS_GPIOB - GPIOB, -#endif -#if TIVA_HAS_GPIOC - GPIOC, -#endif -#if TIVA_HAS_GPIOD - GPIOD, -#endif -#if TIVA_HAS_GPIOE - GPIOE, -#endif -#if TIVA_HAS_GPIOF - GPIOF, -#endif -#if TIVA_HAS_GPIOG - GPIOG, -#endif -#if TIVA_HAS_GPIOH - GPIOH, -#endif -#if TIVA_HAS_GPIOJ - GPIOJ, -#endif -#if TIVA_HAS_GPIOK - GPIOK, -#endif -#if TIVA_HAS_GPIOL - GPIOL, -#endif -#if TIVA_HAS_GPIOM - GPIOM, -#endif -#if TIVA_HAS_GPION - GPION, -#endif -#if TIVA_HAS_GPIOP - GPIOP, -#endif -#if TIVA_HAS_GPIOQ - GPIOQ, -#endif -#if TIVA_HAS_GPIOR - GPIOR, -#endif -#if TIVA_HAS_GPIOS - GPIOS, -#endif -#if TIVA_HAS_GPIOT - GPIOT, -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Enables GPIO IRQ sources. - * - * @notapi - */ -static void ext_lld_irq_enable(void) -{ -#if TIVA_HAS_GPIOA - nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_EXT_GPIOA_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOB - nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_EXT_GPIOB_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOC - nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_EXT_GPIOC_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOD - nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_EXT_GPIOD_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOE - nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_EXT_GPIOE_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOF - nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_EXT_GPIOF_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOG - nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_EXT_GPIOG_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOH - nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_EXT_GPIOH_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOJ - nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_EXT_GPIOJ_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOK - nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_EXT_GPIOK_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOL - nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_EXT_GPIOL_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOM - nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_EXT_GPIOM_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPION - nvicEnableVector(TIVA_GPION_NUMBER, TIVA_EXT_GPION_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOP - nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_EXT_GPIOP0_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_EXT_GPIOP1_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_EXT_GPIOP2_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_EXT_GPIOP3_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_EXT_GPIOP4_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_EXT_GPIOP5_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_EXT_GPIOP6_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_EXT_GPIOP7_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOQ - nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_EXT_GPIOQ0_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_EXT_GPIOQ1_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_EXT_GPIOQ2_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_EXT_GPIOQ3_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_EXT_GPIOQ4_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_EXT_GPIOQ5_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_EXT_GPIOQ6_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_EXT_GPIOQ7_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOR - nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_EXT_GPIOR_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOS - nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_EXT_GPIOS_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOT - nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_EXT_GPIOT_IRQ_PRIORITY); -#endif -} - -/** - * @brief Disables GPIO IRQ sources. - * - * @notapi - */ -static void ext_lld_irq_disable(void) -{ -#if TIVA_HAS_GPIOA - nvicDisableVector(TIVA_GPIOA_NUMBER); -#endif -#if TIVA_HAS_GPIOB - nvicDisableVector(TIVA_GPIOB_NUMBER); -#endif -#if TIVA_HAS_GPIOC - nvicDisableVector(TIVA_GPIOC_NUMBER); -#endif -#if TIVA_HAS_GPIOD - nvicDisableVector(TIVA_GPIOD_NUMBER); -#endif -#if TIVA_HAS_GPIOE - nvicDisableVector(TIVA_GPIOE_NUMBER); -#endif -#if TIVA_HAS_GPIOF - nvicDisableVector(TIVA_GPIOF_NUMBER); -#endif -#if TIVA_HAS_GPIOG - nvicDisableVector(TIVA_GPIOG_NUMBER); -#endif -#if TIVA_HAS_GPIOH - nvicDisableVector(TIVA_GPIOH_NUMBER); -#endif -#if TIVA_HAS_GPIOJ - nvicDisableVector(TIVA_GPIOJ_NUMBER); -#endif -#if TIVA_HAS_GPIOK - nvicDisableVector(TIVA_GPIOK_NUMBER); -#endif -#if TIVA_HAS_GPIOL - nvicDisableVector(TIVA_GPIOL_NUMBER); -#endif -#if TIVA_HAS_GPIOM - nvicDisableVector(TIVA_GPIOM_NUMBER); -#endif -#if TIVA_HAS_GPION - nvicDisableVector(TIVA_GPION_NUMBER); -#endif -#if TIVA_HAS_GPIOP - nvicDisableVector(TIVA_GPIOP0_NUMBER); - nvicDisableVector(TIVA_GPIOP1_NUMBER); - nvicDisableVector(TIVA_GPIOP2_NUMBER); - nvicDisableVector(TIVA_GPIOP3_NUMBER); - nvicDisableVector(TIVA_GPIOP4_NUMBER); - nvicDisableVector(TIVA_GPIOP5_NUMBER); - nvicDisableVector(TIVA_GPIOP6_NUMBER); - nvicDisableVector(TIVA_GPIOP7_NUMBER); -#endif -#if TIVA_HAS_GPIOQ - nvicDisableVector(TIVA_GPIOQ0_NUMBER); - nvicDisableVector(TIVA_GPIOQ1_NUMBER); - nvicDisableVector(TIVA_GPIOQ2_NUMBER); - nvicDisableVector(TIVA_GPIOQ3_NUMBER); - nvicDisableVector(TIVA_GPIOQ4_NUMBER); - nvicDisableVector(TIVA_GPIOQ5_NUMBER); - nvicDisableVector(TIVA_GPIOQ6_NUMBER); - nvicDisableVector(TIVA_GPIOQ7_NUMBER); -#endif -#if TIVA_HAS_GPIOR - nvicDisableVector(TIVA_GPIOR_NUMBER); -#endif -#if TIVA_HAS_GPIOS - nvicDisableVector(TIVA_GPIOS_NUMBER); -#endif -#if TIVA_HAS_GPIOT - nvicDisableVector(TIVA_GPIOT_NUMBER); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) -/** - * @brief GPIOA interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOA, 0); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) -/** - * @brief GPIOB interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOB, 8); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) -/** - * @brief GPIOC interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOC, 16); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) -/** - * @brief GPIOD interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOD, 24); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) -/** - * @brief GPIOE interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOE, 32); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) -/** - * @brief GPIOF interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOF, 40); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) -/** - * @brief GPIOG interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOG, 48); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) -/** - * @brief GPIOH interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOH, 56); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) -/** - * @brief GPIOJ interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOJ, 64); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) -/** - * @brief GPIOK interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOK, 72); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) -/** - * @brief GPIOL interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOL, 80); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) -/** - * @brief GPIOM interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOM, 88); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) -/** - * @brief GPION interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPION, 96); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) -/** - * @brief GPIOP0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 104, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 105, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 106, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 107, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 108, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 109, 5); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP6 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 110, 6); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP7 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 111, 7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) -/** - * @brief GPIOQ0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 112, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 113, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 114, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 115, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 116, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 117, 5); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ6 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 118, 6); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ7 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 119, 7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) -/** - * @brief GPIOR interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOR, 120); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) -/** - * @brief GPIOS interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOS, 128); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) -/** - * @brief GPIOT interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOT, 132); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level EXT driver initialization. - * - * @notapi - */ -void ext_lld_init(void) -{ - extObjectInit(&EXTD1); -} - -/** - * @brief Configures and activates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_start(EXTDriver *extp) -{ - uint8_t i; - - if (extp->state == EXT_STOP) { - ext_lld_irq_enable(); - } - - /* Configuration of automatic channels.*/ - for (i = 0; i < EXT_MAX_CHANNELS; i++) { - if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) { - ext_lld_channel_enable(extp, i); - } - else { - ext_lld_channel_disable(extp, i); - } - } -} - -/** - * @brief Deactivates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_stop(EXTDriver *extp) -{ - if (extp->state == EXT_ACTIVE) { - ext_lld_irq_disable(); - } - -#if TIVA_HAS_GPIOA - GPIOA->IM = 0; -#endif -#if TIVA_HAS_GPIOB - GPIOB->IM = 0; -#endif -#if TIVA_HAS_GPIOC - GPIOC->IM = 0; -#endif -#if TIVA_HAS_GPIOD - GPIOD->IM = 0; -#endif -#if TIVA_HAS_GPIOE - GPIOE->IM = 0; -#endif -#if TIVA_HAS_GPIOF - GPIOF->IM = 0; -#endif -#if TIVA_HAS_GPIOG - GPIOG->IM = 0; -#endif -#if TIVA_HAS_GPIOH - GPIOH->IM = 0; -#endif -#if TIVA_HAS_GPIOJ - GPIOJ->IM = 0; -#endif -#if TIVA_HAS_GPIOK - GPIOK->IM = 0; -#endif -#if TIVA_HAS_GPIOL - GPIOL->IM = 0; -#endif -#if TIVA_HAS_GPIOM - GPIOM->IM = 0; -#endif -#if TIVA_HAS_GPION - GPION->IM = 0; -#endif -#if TIVA_HAS_GPIOP - GPIOP->IM = 0; -#endif -#if TIVA_HAS_GPIOQ - GPIOQ->IM = 0; -#endif -#if TIVA_HAS_GPIOR - GPIOR->IM = 0; -#endif -#if TIVA_HAS_GPIOS - GPIOS->IM = 0; -#endif -#if TIVA_HAS_GPIOT - GPIOT->IM = 0; -#endif -} - -/** - * @brief Enables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be enabled - * - * @notapi - */ -void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) -{ - GPIO_TypeDef *gpiop; - uint8_t pin; - uint32_t im; - - pin = channel & 0x07; - gpiop = gpio[channel >> 3]; - - /* Disable interrupts */ - im = gpiop->IM; - gpiop->IM = 0; - - /* Configure pin to be edge-sensitive.*/ - gpiop->IS &= ~(1 << pin); - - /* Programming edge registers.*/ - if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_BOTH_EDGES) { - gpiop->IBE |= (1 << pin); - } - else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_FALLING_EDGE) { - gpiop->IBE &= ~(1 << pin); - gpiop->IEV &= ~(1 << pin); - } - else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_RISING_EDGE) { - gpiop->IBE &= ~(1 << pin); - gpiop->IEV |= (1 << pin); - } - - /* Programming interrupt and event registers.*/ - if ((extp->config->channels[channel].cb != NULL) && - ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) != - EXT_CH_MODE_DISABLED)) { - im |= (1 << pin); - } - else { - im &= ~(1 << pin); - } - - /* Restore interrupts */ - gpiop->IM = im; -} - -/** - * @brief Disables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be disabled - * - * @notapi - */ -void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) -{ - (void)extp; - GPIO_TypeDef *gpiop; - uint8_t pin; - - pin = channel & 0x07; - gpiop = gpio[channel >> 3]; - - gpiop->IM &= ~(1 << pin); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_ext_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_ext_lld.h deleted file mode 100644 index 08accb2..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_ext_lld.h +++ /dev/null @@ -1,523 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Tiva/ext_lld.h - * @brief Tiva EXT subsystem low level driver header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef HAL_EXT_LLD_H -#define HAL_EXT_LLD_H - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Number of EXT per port. - */ -#define EXT_MAX_CHANNELS TIVA_GPIO_PINS - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief GPIOA interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOA_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOB interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOB_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOC interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOC_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOD interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOD_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOE interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOE_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOF interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOF_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOG interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOG_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOH interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOH_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOJ interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOJ_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOK interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOK_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOL interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOL_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOM interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOM_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPION interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPION_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP0 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP0_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP1 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP1_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP2 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP2_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP3 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP3_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP4 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP4_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP5 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP5_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP6 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP6_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP7 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP7_IRQ_PRIORITY 3 -#endif -/** @} */ - -/** - * @brief GPIOQ0 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ0_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ1 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ1_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ2 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ2_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ3 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ3_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ4 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ4_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ5 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ5_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ6 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ6_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ7 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ7_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOR interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOR_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOS interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOS_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOT interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOT_IRQ_PRIORITY 3 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if TIVA_HAS_GPIOA && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOA" -#endif - -#if TIVA_HAS_GPIOB && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOB_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOB" -#endif - -#if TIVA_HAS_GPIOC && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOC_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOC" -#endif - -#if TIVA_HAS_GPIOD && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOD_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOD" -#endif - -#if TIVA_HAS_GPIOE && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOE_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOE" -#endif - -#if TIVA_HAS_GPIOF && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOF_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOF" -#endif - -#if TIVA_HAS_GPIOG && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOG_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOG" -#endif - -#if TIVA_HAS_GPIOH && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOH_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOH" -#endif - -#if TIVA_HAS_GPIOJ && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOJ_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOJ" -#endif - -#if TIVA_HAS_GPIOK && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOK_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOK" -#endif - -#if TIVA_HAS_GPIOL && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOL_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOL" -#endif - -#if TIVA_HAS_GPIOM && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOM_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOM" -#endif - -#if TIVA_HAS_GPION && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPION_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPION" -#endif - -#if TIVA_HAS_GPIOP0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP0" -#endif - -#if TIVA_HAS_GPIOP1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP1" -#endif - -#if TIVA_HAS_GPIOP2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP2" -#endif - -#if TIVA_HAS_GPIOP3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP3" -#endif - -#if TIVA_HAS_GPIOP4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP4" -#endif - -#if TIVA_HAS_GPIOP5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP5" -#endif - -#if TIVA_HAS_GPIOP6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP6" -#endif - -#if TIVA_HAS_GPIOP7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP7" -#endif - -#if TIVA_HAS_GPIOQ0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ0" -#endif - -#if TIVA_HAS_GPIOQ1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ1" -#endif - -#if TIVA_HAS_GPIOQ2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ2" -#endif - -#if TIVA_HAS_GPIOQ3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ3" -#endif - -#if TIVA_HAS_GPIOQ4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ4" -#endif - -#if TIVA_HAS_GPIOQ5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ5" -#endif - -#if TIVA_HAS_GPIOQ6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ6" -#endif - -#if TIVA_HAS_GPIOQ7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ7" -#endif - -#if TIVA_HAS_GPIOR && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOR_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOR" -#endif - -#if TIVA_HAS_GPIOS && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOS_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOS" -#endif - -#if TIVA_HAS_GPIOT && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOT_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOT" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief EXT channel identifier. - */ -typedef uint32_t expchannel_t; - -/** - * @brief Type of an EXT generic notification callback. - * - * @param[in] extp pointer to the @p EXPDriver object triggering the - * callback - */ -typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); - -/** - * @brief Channel configuration structure. - */ -typedef struct { - /** - * @brief Channel mode. - */ - uint32_t mode; - /** - * @brief Channel callback. - */ - extcallback_t cb; -} EXTChannelConfig; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Channel configurations. - */ - EXTChannelConfig channels[EXT_MAX_CHANNELS]; - /* End of the mandatory fields.*/ -} EXTConfig; - -/** - * @brief Structure representing an EXT driver. - */ -struct EXTDriver { - /** - * @brief Driver state. - */ - extstate_t state; - /** - * @brief Current configuration data. - */ - const EXTConfig *config; - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern EXTDriver EXTD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_init(void); - void ext_lld_start(EXTDriver *extp); - void ext_lld_stop(EXTDriver *extp); - void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); - void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* HAL_EXT_LLD_H */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_gpt_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_gpt_lld.c deleted file mode 100644 index 86f2303..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_gpt_lld.c +++ /dev/null @@ -1,708 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/gpt_lld.c - * @brief TM4C123x/TM4C129x GPT subsystem low level driver source. - * - * @addtogroup GPT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_GPT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief GPTD1 driver identifier. - */ -#if TIVA_GPT_USE_GPT0 || defined(__DOXYGEN__) -GPTDriver GPTD1; -#endif - -/** - * @brief GPTD2 driver identifier. - */ -#if TIVA_GPT_USE_GPT1 || defined(__DOXYGEN__) -GPTDriver GPTD2; -#endif - -/** - * @brief GPTD3 driver identifier. - */ -#if TIVA_GPT_USE_GPT2 || defined(__DOXYGEN__) -GPTDriver GPTD3; -#endif - -/** - * @brief GPTD4 driver identifier. - */ -#if TIVA_GPT_USE_GPT3 || defined(__DOXYGEN__) -GPTDriver GPTD4; -#endif - -/** - * @brief GPTD5 driver identifier. - */ -#if TIVA_GPT_USE_GPT4 || defined(__DOXYGEN__) -GPTDriver GPTD5; -#endif - -/** - * @brief GPTD6 driver identifier. - */ -#if TIVA_GPT_USE_GPT5 || defined(__DOXYGEN__) -GPTDriver GPTD6; -#endif - -/** - * @brief GPTD7 driver identifier. - */ -#if TIVA_GPT_USE_WGPT0 || defined(__DOXYGEN__) -GPTDriver GPTD7; -#endif - -/** - * @brief GPTD8 driver identifier. - */ -#if TIVA_GPT_USE_WGPT1 || defined(__DOXYGEN__) -GPTDriver GPTD8; -#endif - -/** - * @brief GPTD9 driver identifier. - */ -#if TIVA_GPT_USE_WGPT2 || defined(__DOXYGEN__) -GPTDriver GPTD9; -#endif - -/** - * @brief GPTD10 driver identifier. - */ -#if TIVA_GPT_USE_WGPT3 || defined(__DOXYGEN__) -GPTDriver GPTD10; -#endif - -/** - * @brief GPTD11 driver identifier. - */ -#if TIVA_GPT_USE_WGPT4 || defined(__DOXYGEN__) -GPTDriver GPTD11; -#endif - -/** - * @brief GPTD12 driver identifier. - */ -#if TIVA_GPT_USE_WGPT5 || defined(__DOXYGEN__) -GPTDriver GPTD12; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared IRQ handler. - * - * @param[in] gptp pointer to @p GPTDriver object - */ -static void gpt_lld_serve_interrupt(GPTDriver *gptp) -{ - gptp->gpt->ICR = 0xffffffff; - - if (gptp->state == GPT_ONESHOT) { - gptp->state = GPT_READY; - gpt_lld_stop_timer(gptp); - } - - gptp->config->callback(gptp); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_GPT_USE_GPT0 -#if !defined(TIVA_GPT0A_HANDLER) -#error "TIVA_GPT0A_HANDLER not defined" -#endif -/** - * @brief GPT0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPT0A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_GPT1 -#if !defined(TIVA_GPT1A_HANDLER) -#error "TIVA_GPT1A_HANDLER not defined" -#endif -/** - * @brief GPT1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPT1A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_GPT2 -#if !defined(TIVA_GPT2A_HANDLER) -#error "TIVA_GPT2A_HANDLER not defined" -#endif -/** - * @brief GPT2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPT2A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_GPT3 -#if !defined(TIVA_GPT3A_HANDLER) -#error "TIVA_GPT3A_HANDLER not defined" -#endif -/** - * @brief GPT3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPT3A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD4); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_GPT4 -#if !defined(TIVA_GPT4A_HANDLER) -#error "TIVA_GPT4A_HANDLER not defined" -#endif -/** - * @brief GPT4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPT4A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD5); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_GPT5 -#if !defined(TIVA_GPT5A_HANDLER) -#error "TIVA_GPT5A_HANDLER not defined" -#endif -/** - * @brief GPT5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPT5A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD6); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_WGPT0 -#if !defined(TIVA_WGPT0A_HANDLER) -#error "TIVA_WGPT0A_HANDLER not defined" -#endif -/** - * @brief WGPT0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WGPT0A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_WGPT1 -#if !defined(TIVA_WGPT1A_HANDLER) -#error "TIVA_WGPT1A_HANDLER not defined" -#endif -/** - * @brief WGPT1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WGPT1A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD8); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_WGPT2 -#if !defined(TIVA_WGPT2A_HANDLER) -#error "TIVA_WGPT2A_HANDLER not defined" -#endif -/** - * @brief WGPT2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WGPT2A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD9); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_WGPT3 -#if !defined(TIVA_WGPT3A_HANDLER) -#error "TIVA_WGPT3A_HANDLER not defined" -#endif -/** - * @brief WGPT3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WGPT3A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD10); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_WGPT4 -#if !defined(TIVA_WGPT4A_HANDLER) -#error "TIVA_WGPT4A_HANDLER not defined" -#endif -/** - * @brief WGPT4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WGPT4A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD11); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_WGPT5 -#if !defined(TIVA_WGPT5A_HANDLER) -#error "TIVA_WGPT5A_HANDLER not defined" -#endif -/** - * @brief WGPT5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WGPT5A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD12); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level GPT driver initialization. - * - * @notapi - */ -void gpt_lld_init(void) -{ - /* Driver initialization.*/ -#if TIVA_GPT_USE_GPT0 - GPTD1.gpt = GPT0; - gptObjectInit(&GPTD1); -#endif - -#if TIVA_GPT_USE_GPT1 - GPTD2.gpt = GPT1; - gptObjectInit(&GPTD2); -#endif - -#if TIVA_GPT_USE_GPT2 - GPTD3.gpt = GPT2; - gptObjectInit(&GPTD3); -#endif - -#if TIVA_GPT_USE_GPT3 - GPTD4.gpt = GPT3; - gptObjectInit(&GPTD4); -#endif - -#if TIVA_GPT_USE_GPT4 - GPTD5.gpt = GPT4; - gptObjectInit(&GPTD5); -#endif - -#if TIVA_GPT_USE_GPT5 - GPTD6.gpt = GPT5; - gptObjectInit(&GPTD6); -#endif - -#if TIVA_GPT_USE_WGPT0 - GPTD7.gpt = WGPT0; - gptObjectInit(&GPTD7); -#endif - -#if TIVA_GPT_USE_WGPT1 - GPTD8.gpt = WGPT1; - gptObjectInit(&GPTD8); -#endif - -#if TIVA_GPT_USE_WGPT2 - GPTD9.gpt = WGPT2; - gptObjectInit(&GPTD9); -#endif - -#if TIVA_GPT_USE_WGPT3 - GPTD10.gpt = WGPT3; - gptObjectInit(&GPTD10); -#endif - -#if TIVA_GPT_USE_WGPT4 - GPTD11.gpt = WGPT4; - gptObjectInit(&GPTD11); -#endif - -#if TIVA_GPT_USE_WGPT5 - GPTD12.gpt = WGPT5; - gptObjectInit(&GPTD12); -#endif -} - -/** - * @brief Configures and activates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_start(GPTDriver *gptp) -{ - if (gptp->state == GPT_STOP) { - /* Clock activation.*/ -#if TIVA_GPT_USE_GPT0 - if (&GPTD1 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 0); - nvicEnableVector(TIVA_GPT0A_NUMBER, TIVA_GPT_GPT0A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_GPT1 - if (&GPTD2 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 1); - nvicEnableVector(TIVA_GPT1A_NUMBER, TIVA_GPT_GPT1A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_GPT2 - if (&GPTD3 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 2); - nvicEnableVector(TIVA_GPT2A_NUMBER, TIVA_GPT_GPT2A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_GPT3 - if (&GPTD4 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 3); - nvicEnableVector(TIVA_GPT3A_NUMBER, TIVA_GPT_GPT3A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_GPT4 - if (&GPTD5 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 4); - nvicEnableVector(TIVA_GPT4A_NUMBER, TIVA_GPT_GPT4A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_GPT5 - if (&GPTD6 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 5); - nvicEnableVector(TIVA_GPT5A_NUMBER, TIVA_GPT_GPT5A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_WGPT0 - if (&GPTD7 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 0); - nvicEnableVector(TIVA_WGPT0A_NUMBER, TIVA_GPT_WGPT0A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_WGPT1 - if (&GPTD8 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 1); - nvicEnableVector(TIVA_WGPT1A_NUMBER, TIVA_GPT_WGPT1A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_WGPT2 - if (&GPTD9 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 2); - nvicEnableVector(TIVA_WGPT2A_NUMBER, TIVA_GPT_WGPT2A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_WGPT3 - if (&GPTD10 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 3); - nvicEnableVector(TIVA_WGPT3A_NUMBER, TIVA_GPT_WGPT3A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_WGPT4 - if (&GPTD11 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 4); - nvicEnableVector(TIVA_WGPT4A_NUMBER, TIVA_GPT_WGPT4A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_WGPT5 - if (&GPTD12 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 5); - nvicEnableVector(TIVA_WGPT5A_NUMBER, TIVA_GPT_WGPT5A_IRQ_PRIORITY); - } -#endif - } - - /* Timer configuration.*/ - gptp->gpt->CTL = 0; - gptp->gpt->CFG = GPTM_CFG_CFG_SPLIT; - gptp->gpt->TAPR = ((TIVA_SYSCLK / gptp->config->frequency) - 1); -} - -/** - * @brief Deactivates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_stop(GPTDriver *gptp) -{ - if (gptp->state == GPT_READY) { - gptp->gpt->IMR = 0; - gptp->gpt->TAILR = 0; - gptp->gpt->CTL = 0; - -#if TIVA_GPT_USE_GPT0 - if (&GPTD1 == gptp) { - nvicDisableVector(TIVA_GPT0A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 0); - } -#endif - -#if TIVA_GPT_USE_GPT1 - if (&GPTD2 == gptp) { - nvicDisableVector(TIVA_GPT1A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 1); - } -#endif - -#if TIVA_GPT_USE_GPT2 - if (&GPTD3 == gptp) { - nvicDisableVector(TIVA_GPT2A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 2); - } -#endif - -#if TIVA_GPT_USE_GPT3 - if (&GPTD4 == gptp) { - nvicDisableVector(TIVA_GPT3A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 3); - } -#endif - -#if TIVA_GPT_USE_GPT4 - if (&GPTD5 == gptp) { - nvicDisableVector(TIVA_GPT4A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 4); - } -#endif - -#if TIVA_GPT_USE_GPT5 - if (&GPTD6 == gptp) { - nvicDisableVector(TIVA_GPT5A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 5); - } -#endif - -#if TIVA_GPT_USE_WGPT0 - if (&GPTD7 == gptp) { - nvicDisableVector(TIVA_WGPT0A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 0); - } -#endif - -#if TIVA_GPT_USE_WGPT1 - if (&GPTD8 == gptp) { - nvicDisableVector(TIVA_WGPT1A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 1); - } -#endif - -#if TIVA_GPT_USE_WGPT2 - if (&GPTD9 == gptp) { - nvicDisableVector(TIVA_WGPT2A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 2); - } -#endif - -#if TIVA_GPT_USE_WGPT3 - if (&GPTD10 == gptp) { - nvicDisableVector(TIVA_WGPT3A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 3); - } -#endif - -#if TIVA_GPT_USE_WGPT4 - if (&GPTD11 == gptp) { - nvicDisableVector(TIVA_WGPT4A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 4); - } -#endif - -#if TIVA_GPT_USE_WGPT5 - if (&GPTD12 == gptp) { - nvicDisableVector(TIVA_WGPT5A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 5); - } -#endif - } -} - -/** - * @brief Starts the timer in continuous mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval period in ticks - * - * @notapi - */ -void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) -{ - gptp->gpt->TAILR = interval - 1; - gptp->gpt->ICR = 0xfffffff; - gptp->gpt->IMR = GPTM_IMR_TATOIM; - gptp->gpt->TAMR = GPTM_TAMR_TAMR_PERIODIC | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; - gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; -} - -/** - * @brief Stops the timer. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_stop_timer(GPTDriver *gptp) -{ - gptp->gpt->IMR = 0; - gptp->gpt->TAILR = 0; - gptp->gpt->CTL &= ~GPTM_CTL_TAEN; -} - -/** - * @brief Starts the timer in one shot mode and waits for completion. - * @details This function specifically polls the timer waiting for completion - * in order to not have extra delays caused by interrupt servicing, - * this function is only recommended for short delays. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval time interval in ticks - * - * @notapi - */ -void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) -{ - gptp->gpt->TAMR = GPTM_TAMR_TAMR_ONESHOT | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; - gptp->gpt->TAILR = interval - 1; - gptp->gpt->ICR = 0xffffffff; - gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; - while (!(gptp->gpt->RIS & GPTM_IMR_TATOIM)) - ; - gptp->gpt->ICR = 0xffffffff; -} - -#endif /* HAL_USE_GPT */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_gpt_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_gpt_lld.h deleted file mode 100644 index e518e58..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_gpt_lld.h +++ /dev/null @@ -1,501 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/gpt_lld.h - * @brief TM4C123x/TM4C129x GPT subsystem low level driver header. - * - * @addtogroup GPT - * @{ - */ - -#ifndef HAL_GPT_LLD_H -#define HAL_GPT_LLD_H - -#if HAL_USE_GPT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief GPTD1 driver enable switch. - * @details If set to @p TRUE the support for GPTD1 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_GPT0) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_GPT0 FALSE -#endif - -/** - * @brief GPTD2 driver enable switch. - * @details If set to @p TRUE the support for GPTD2 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_GPT1) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_GPT1 FALSE -#endif - -/** - * @brief GPTD3 driver enable switch. - * @details If set to @p TRUE the support for GPTD3 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_GPT2) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_GPT2 FALSE -#endif - -/** - * @brief GPTD4 driver enable switch. - * @details If set to @p TRUE the support for GPTD4 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_GPT3) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_GPT3 FALSE -#endif - -/** - * @brief GPTD5 driver enable switch. - * @details If set to @p TRUE the support for GPTD5 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_GPT4) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_GPT4 FALSE -#endif - -/** - * @brief GPTD6 driver enable switch. - * @details If set to @p TRUE the support for GPTD6 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_GPT5) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_GPT5 FALSE -#endif - -/** - * @brief GPTD7 driver enable switch. - * @details If set to @p TRUE the support for GPTD1 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_WGPT0) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_WGPT0 FALSE -#endif - -/** - * @brief GPTD8 driver enable switch. - * @details If set to @p TRUE the support for GPTD2 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_WGPT1) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_WGPT1 FALSE -#endif - -/** - * @brief GPTD9 driver enable switch. - * @details If set to @p TRUE the support for GPTD3 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_WGPT2) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_WGPT2 FALSE -#endif - -/** - * @brief GPTD10 driver enable switch. - * @details If set to @p TRUE the support for GPTD4 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_WGPT3) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_WGPT3 FALSE -#endif - -/** - * @brief GPTD11 driver enable switch. - * @details If set to @p TRUE the support for GPTD5 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_WGPT4) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_WGPT4 FALSE -#endif - -/** - * @brief GPTD12 driver enable switch. - * @details If set to @p TRUE the support for GPTD6 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_WGPT5) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_WGPT5 FALSE -#endif - -/** - * @brief GPTD1 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_GPT0A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_GPT0A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD2 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_GPT1A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_GPT1A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD3 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_GPT2A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_GPT2A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD4 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_GPT3A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_GPT3A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD5 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_GPT4A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_GPT4A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD6 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_GPT5A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_GPT5A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD7 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_WGPT0A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_WGPT0A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD8 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_WGPT1A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_WGPT1A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD9 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_WGPT2A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_WGPT2A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD10 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_WGPT3A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_WGPT3A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD11 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_WGPT4A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_WGPT4A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD12 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_WGPT5A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_WGPT5A_IRQ_PRIORITY 7 -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if TIVA_GPT_USE_GPT0 && !TIVA_HAS_GPT0 -#error "GPT0 not present in the selected device" -#endif - -#if TIVA_GPT_USE_GPT1 && !TIVA_HAS_GPT1 -#error "GPT1 not present in the selected device" -#endif - -#if TIVA_GPT_USE_GPT2 && !TIVA_HAS_GPT2 -#error "GPT2 not present in the selected device" -#endif - -#if TIVA_GPT_USE_GPT3 && !TIVA_HAS_GPT3 -#error "GPT3 not present in the selected device" -#endif - -#if TIVA_GPT_USE_GPT4 && !TIVA_HAS_GPT4 -#error "GPT4 not present in the selected device" -#endif - -#if TIVA_GPT_USE_GPT5 && !TIVA_HAS_GPT5 -#error "GPT5 not present in the selected device" -#endif - -#if TIVA_GPT_USE_WGPT0 && !TIVA_HAS_WGPT0 -#error "WGPT0 not present in the selected device" -#endif - -#if TIVA_GPT_USE_WGPT1 && !TIVA_HAS_WGPT1 -#error "WGPT1 not present in the selected device" -#endif - -#if TIVA_GPT_USE_WGPT2 && !TIVA_HAS_WGPT2 -#error "WGPT2 not present in the selected device" -#endif - -#if TIVA_GPT_USE_WGPT3 && !TIVA_HAS_WGPT3 -#error "WGPT3 not present in the selected device" -#endif - -#if TIVA_GPT_USE_WGPT4 && !TIVA_HAS_WGPT4 -#error "WGPT4 not present in the selected device" -#endif - -#if TIVA_GPT_USE_WGPT5 && !TIVA_HAS_WGPT5 -#error "WGPT5 not present in the selected device" -#endif - -#if !TIVA_GPT_USE_GPT0 && !TIVA_GPT_USE_GPT1 && !TIVA_GPT_USE_GPT2 && \ - !TIVA_GPT_USE_GPT3 && !TIVA_GPT_USE_GPT4 && !TIVA_GPT_USE_GPT5 && \ - !TIVA_GPT_USE_WGPT0 && !TIVA_GPT_USE_WGPT1 && !TIVA_GPT_USE_WGPT2 && \ - !TIVA_GPT_USE_WGPT3 && !TIVA_GPT_USE_WGPT4 && !TIVA_GPT_USE_WGPT5 -#error "GPT driver activated but no (W)GPT peripheral assigned" -#endif - -#if TIVA_GPT_USE_GPT0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT0A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPT0" -#endif - -#if TIVA_GPT_USE_GPT1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT1A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPT1" -#endif - -#if TIVA_GPT_USE_GPT2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT2A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPT2" -#endif - -#if TIVA_GPT_USE_GPT3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT3A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPT3" -#endif - -#if TIVA_GPT_USE_GPT4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT4A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPT4" -#endif - -#if TIVA_GPT_USE_GPT5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT5A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPT5" -#endif - -#if TIVA_GPT_USE_WGPT0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT0A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to WGPT0" -#endif - -#if TIVA_GPT_USE_WGPT1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT1A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to WGPT1" -#endif - -#if TIVA_GPT_USE_WGPT2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT2A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to WGPT2" -#endif - -#if TIVA_GPT_USE_WGPT3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT3A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to WGPT3" -#endif - -#if TIVA_GPT_USE_WGPT4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT4A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to WGPT4" -#endif - -#if TIVA_GPT_USE_WGPT5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT5A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to WGPT5" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief GPT frequency type. - */ -typedef uint32_t gptfreq_t; - -/** - * @brief GPT counter type. - */ -typedef uint16_t gptcnt_t; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - gptfreq_t frequency; - /** - * @brief Timer callback pointer. - * @note This callback is invoked on GPT counter events. - */ - gptcallback_t callback; - /* End of the mandatory fields.*/ -} GPTConfig; - -/** - * @brief Structure representing a GPT driver. - */ -struct GPTDriver { - /** - * @brief Driver state. - */ - gptstate_t state; - /** - * @brief Current configuration data. - */ - const GPTConfig *config; -#if defined(GPT_DRIVER_EXT_FIELDS) - GPT_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the GPT registers block. - */ - GPT_TypeDef *gpt; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the interval of GPT peripheral. - * @details This function changes the interval of a running GPT unit. - * @pre The GPT unit must have been activated using @p gptStart(). - * @pre The GPT unit must have been running in continuous mode using - * @p gptStartContinuous(). - * @post The GPT unit interval is changed to the new value. - * @note The function has effect at the next cycle start. - * - * @param[in] gptp pointer to a @p GPTDriver object - * @param[in] interval new cycle time in timer ticks - * @notapi - */ -#define gpt_lld_change_interval(gptp, interval) { \ - gptp->gpt->TAILR = interval - 1; \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if TIVA_GPT_USE_GPT0 && !defined(__DOXYGEN__) -extern GPTDriver GPTD1; -#endif - -#if TIVA_GPT_USE_GPT1 && !defined(__DOXYGEN__) -extern GPTDriver GPTD2; -#endif - -#if TIVA_GPT_USE_GPT2 && !defined(__DOXYGEN__) -extern GPTDriver GPTD3; -#endif - -#if TIVA_GPT_USE_GPT3 && !defined(__DOXYGEN__) -extern GPTDriver GPTD4; -#endif - -#if TIVA_GPT_USE_GPT4 && !defined(__DOXYGEN__) -extern GPTDriver GPTD5; -#endif - -#if TIVA_GPT_USE_GPT5 && !defined(__DOXYGEN__) -extern GPTDriver GPTD6; -#endif - -#if TIVA_GPT_USE_WGPT0 && !defined(__DOXYGEN__) -extern GPTDriver GPTD7; -#endif - -#if TIVA_GPT_USE_WGPT1 && !defined(__DOXYGEN__) -extern GPTDriver GPTD8; -#endif - -#if TIVA_GPT_USE_WGPT2 && !defined(__DOXYGEN__) -extern GPTDriver GPTD9; -#endif - -#if TIVA_GPT_USE_WGPT3 && !defined(__DOXYGEN__) -extern GPTDriver GPTD10; -#endif - -#if TIVA_GPT_USE_WGPT4 && !defined(__DOXYGEN__) -extern GPTDriver GPTD11; -#endif - -#if TIVA_GPT_USE_WGPT5 && !defined(__DOXYGEN__) -extern GPTDriver GPTD12; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void gpt_lld_init(void); - void gpt_lld_start(GPTDriver *gptp); - void gpt_lld_stop(GPTDriver *gptp); - void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); - void gpt_lld_stop_timer(GPTDriver *gptp); - void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_GPT */ - -#endif /* HAL_GPT_LLD_H */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_i2c_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_i2c_lld.c deleted file mode 100644 index 5d80633..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_i2c_lld.c +++ /dev/null @@ -1,854 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/i2c_lld.c - * @brief TM4C123x/TM4C129x I2C subsystem low level driver source. - * - * @addtogroup I2C - * @{ - */ - -#include "hal.h" - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief I2C0 driver identifier. - */ -#if TIVA_I2C_USE_I2C0 || defined(__DOXYGEN__) -I2CDriver I2CD1; -#endif - -/** - * @brief I2C1 driver identifier. - */ -#if TIVA_I2C_USE_I2C1 || defined(__DOXYGEN__) -I2CDriver I2CD2; -#endif - -/** - * @brief I2C2 driver identifier. - */ -#if TIVA_I2C_USE_I2C2 || defined(__DOXYGEN__) -I2CDriver I2CD3; -#endif - -/** - * @brief I2C3 driver identifier. - */ -#if TIVA_I2C_USE_I2C3 || defined(__DOXYGEN__) -I2CDriver I2CD4; -#endif - -/** - * @brief I2C4 driver identifier. - */ -#if TIVA_I2C_USE_I2C4 || defined(__DOXYGEN__) -I2CDriver I2CD5; -#endif - -/** - * @brief I2C5 driver identifier. - */ -#if TIVA_I2C_USE_I2C5 || defined(__DOXYGEN__) -I2CDriver I2CD6; -#endif - -/** - * @brief I2C6 driver identifier. - */ -#if TIVA_I2C_USE_I2C6 || defined(__DOXYGEN__) -I2CDriver I2CD7; -#endif - -/** - * @brief I2C7 driver identifier. - */ -#if TIVA_I2C_USE_I2C7 || defined(__DOXYGEN__) -I2CDriver I2CD8; -#endif - -/** - * @brief I2C8 driver identifier. - */ -#if TIVA_I2C_USE_I2C8 || defined(__DOXYGEN__) -I2CDriver I2CD9; -#endif - -/** - * @brief I2C9 driver identifier. - */ -#if TIVA_I2C_USE_I2C9 || defined(__DOXYGEN__) -I2CDriver I2CD10; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief I2C shared ISR code. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_serve_interrupt(I2CDriver *i2cp) -{ - I2C_TypeDef *dp = i2cp->i2c; - uint32_t status; - - // clear MIS bit in MICR by writing 1 - dp->MICR = 1; - - // read interrupt status - status = dp->MCS; - - if (status & TIVA_MCS_ERROR) { - i2cp->errors |= I2C_BUS_ERROR; - } - if (status & TIVA_MCS_ARBLST) { - i2cp->errors |= I2C_ARBITRATION_LOST; - } - - if (i2cp->errors == I2C_NO_ERROR) { - // no error detected - switch(i2cp->intstate) { - case STATE_IDLE: { - _i2c_wakeup_isr(i2cp); - break; - } - case STATE_WRITE_NEXT: { - if (i2cp->txbytes == 1) { - i2cp->intstate = STATE_WRITE_FINAL; - } - dp->MDR = *(i2cp->txbuf); - i2cp->txbuf++; - i2cp->txbytes--; - // start transmission - dp->MCS = TIVA_I2C_BURST_SEND_CONTINUE; - break; - } - case STATE_WRITE_FINAL: { - if (i2cp->rxbytes == 0) { - i2cp->intstate = STATE_IDLE; - } - else if (i2cp->rxbytes == 1) { - i2cp->intstate = STATE_READ_ONE; - } - else { - i2cp->intstate = STATE_READ_FIRST; - } - dp->MDR = *(i2cp->txbuf); - i2cp->txbuf++; - // txbytes - 1 - i2cp->txbytes--; - // start transmission - dp->MCS = TIVA_I2C_BURST_SEND_FINISH; - break; - } - case STATE_WAIT_ACK: { - break; - } - case STATE_SEND_ACK: { - break; - } - case STATE_READ_ONE: { - i2cp->intstate = STATE_READ_WAIT; - // Initializes driver fields, LSB = 1 -> read. - i2cp->addr |= 1; - - // set slave address - dp->MSA = i2cp->addr; - i2cp->rxbytes--; - //start receiving - dp->MCS = TIVA_I2C_SINGLE_RECEIVE; - - break; - } - case STATE_READ_FIRST: { - if (i2cp->rxbytes == 2) { - i2cp->intstate = STATE_READ_FINAL; - } - else { - i2cp->intstate = STATE_READ_NEXT; - } - - // Initializes driver fields, LSB = 1 -> read. - i2cp->addr |= 1; - - // set slave address - dp->MSA = i2cp->addr; - i2cp->rxbytes--; - //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_START; - - break; - } - case STATE_READ_NEXT: { - if(i2cp->rxbytes == 2) { - i2cp->intstate = STATE_READ_FINAL; - } - *(i2cp->rxbuf) = dp->MDR; - i2cp->rxbuf++; - i2cp->rxbytes--; - //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_CONTINUE; - - break; - } - case STATE_READ_FINAL: { - i2cp->intstate = STATE_READ_WAIT; - *(i2cp->rxbuf) = dp->MDR; - i2cp->rxbuf++; - i2cp->rxbytes--; - //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_FINISH; - - break; - } - case STATE_READ_WAIT: { - i2cp->intstate = STATE_IDLE; - *(i2cp->rxbuf) = dp->MDR; - i2cp->rxbuf++; - _i2c_wakeup_isr(i2cp); - break; - } - } - } - else { - // error detected - _i2c_wakeup_error_isr(i2cp); - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_I2C_USE_I2C0 || defined(__DOXYGEN__) -/** - * @brief I2C0 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C0 */ - -#if TIVA_I2C_USE_I2C1 || defined(__DOXYGEN__) -/** - * @brief I2C1 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C1 */ - -#if TIVA_I2C_USE_I2C2 || defined(__DOXYGEN__) -/** - * @brief I2C2 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD3); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C2 */ - -#if TIVA_I2C_USE_I2C3 || defined(__DOXYGEN__) -/** - * @brief I2C3 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD4); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C3 */ - -#if TIVA_I2C_USE_I2C4 || defined(__DOXYGEN__) -/** - * @brief I2C4 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD5); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C4 */ - -#if TIVA_I2C_USE_I2C5 || defined(__DOXYGEN__) -/** - * @brief I2C5 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD6); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C5 */ - -#if TIVA_I2C_USE_I2C6 || defined(__DOXYGEN__) -/** - * @brief I2C6 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C6_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD7); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C6 */ - -#if TIVA_I2C_USE_I2C7 || defined(__DOXYGEN__) -/** - * @brief I2C7 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C7_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD8); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C7 */ - -#if TIVA_I2C_USE_I2C8 || defined(__DOXYGEN__) -/** - * @brief I2C8 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C8_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD9); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C8 */ - -#if TIVA_I2C_USE_I2C9 || defined(__DOXYGEN__) -/** - * @brief I2C9 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C9_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD10); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C9 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level I2C driver initialization. - * - * @notapi - */ -void i2c_lld_init(void) { - -#if TIVA_I2C_USE_I2C0 - i2cObjectInit(&I2CD1); - I2CD1.thread = NULL; - I2CD1.i2c = I2C0; -#endif /* TIVA_I2C_USE_I2C0 */ - -#if TIVA_I2C_USE_I2C1 - i2cObjectInit(&I2CD2); - I2CD2.thread = NULL; - I2CD2.i2c = I2C1; -#endif /* TIVA_I2C_USE_I2C1 */ - -#if TIVA_I2C_USE_I2C2 - i2cObjectInit(&I2CD3); - I2CD3.thread = NULL; - I2CD3.i2c = I2C2; -#endif /* TIVA_I2C_USE_I2C2 */ - -#if TIVA_I2C_USE_I2C3 - i2cObjectInit(&I2CD4); - I2CD4.thread = NULL; - I2CD4.i2c = I2C3; -#endif /* TIVA_I2C_USE_I2C3 */ - -#if TIVA_I2C_USE_I2C4 - i2cObjectInit(&I2CD5); - I2CD5.thread = NULL; - I2CD5.i2c = I2C4; -#endif /* TIVA_I2C_USE_I2C4 */ - -#if TIVA_I2C_USE_I2C5 - i2cObjectInit(&I2CD6); - I2CD6.thread = NULL; - I2CD6.i2c = I2C5; -#endif /* TIVA_I2C_USE_I2C5 */ - -#if TIVA_I2C_USE_I2C6 - i2cObjectInit(&I2CD7); - I2CD7.thread = NULL; - I2CD7.i2c = I2C6; -#endif /* TIVA_I2C_USE_I2C6 */ - -#if TIVA_I2C_USE_I2C7 - i2cObjectInit(&I2CD8); - I2CD8.thread = NULL; - I2CD8.i2c = I2C7; -#endif /* TIVA_I2C_USE_I2C7 */ - -#if TIVA_I2C_USE_I2C8 - i2cObjectInit(&I2CD9); - I2CD9.thread = NULL; - I2CD9.i2c = I2C8; -#endif /* TIVA_I2C_USE_I2C8 */ - -#if TIVA_I2C_USE_I2C9 - i2cObjectInit(&I2CD10); - I2CD10.thread = NULL; - I2CD10.i2c = I2C9; -#endif /* TIVA_I2C_USE_I2C9 */ -} - -/** - * @brief Configures and activates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_start(I2CDriver *i2cp) -{ - I2C_TypeDef *dp = i2cp->i2c; - - /* If in stopped state then enables the I2C clocks.*/ - if (i2cp->state == I2C_STOP) { -#if TIVA_I2C_USE_I2C0 - if (&I2CD1 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 0); - nvicEnableVector(TIVA_I2C0_NUMBER, TIVA_I2C_I2C0_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C0 */ - -#if TIVA_I2C_USE_I2C1 - if (&I2CD2 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 1); - nvicEnableVector(TIVA_I2C1_NUMBER, TIVA_I2C_I2C1_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C1 */ - -#if TIVA_I2C_USE_I2C2 - if (&I2CD3 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 2); - nvicEnableVector(TIVA_I2C2_NUMBER, TIVA_I2C_I2C2_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C2 */ - -#if TIVA_I2C_USE_I2C3 - if (&I2CD4 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 3); - nvicEnableVector(TIVA_I2C3_NUMBER, TIVA_I2C_I2C3_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C3 */ - -#if TIVA_I2C_USE_I2C4 - if (&I2CD5 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 4); - nvicEnableVector(TIVA_I2C4_NUMBER, TIVA_I2C_I2C4_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C4 */ - -#if TIVA_I2C_USE_I2C5 - if (&I2CD6 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 5); - nvicEnableVector(TIVA_I2C5_NUMBER, TIVA_I2C_I2C5_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C5 */ - -#if TIVA_I2C_USE_I2C6 - if (&I2CD7 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 6); - nvicEnableVector(TIVA_I2C6_NUMBER, TIVA_I2C_I2C6_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C6 */ - -#if TIVA_I2C_USE_I2C7 - if (&I2CD8 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 7); - nvicEnableVector(TIVA_I2C7_NUMBER, TIVA_I2C_I2C7_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C7 */ - -#if TIVA_I2C_USE_I2C8 - if (&I2CD9 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 8); - nvicEnableVector(TIVA_I2C8_NUMBER, TIVA_I2C_I2C8_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C7 */ - -#if TIVA_I2C_USE_I2C9 - if (&I2CD10 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 9); - nvicEnableVector(TIVA_I2C9_NUMBER, TIVA_I2C_I2C9_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C7 */ - } - - dp->MCR = 0x10; - dp->MTPR = MTPR_VALUE; -} - -/** - * @brief Deactivates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_stop(I2CDriver *i2cp) -{ - I2C_TypeDef *dp = i2cp->i2c; - /* If not in stopped state then disables the I2C clock.*/ - if (i2cp->state != I2C_STOP) { - - /* I2C disable.*/ - // TODO: abort i2c operation - //i2c_lld_abort_operation(i2cp); - -#if TIVA_I2C_USE_I2C0 - if (&I2CD1 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 0); - nvicDisableVector(TIVA_I2C0_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C0 */ - -#if TIVA_I2C_USE_I2C1 - if (&I2CD2 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 1); - nvicDisableVector(TIVA_I2C1_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C1 */ - -#if TIVA_I2C_USE_I2C2 - if (&I2CD3 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 2); - nvicDisableVector(TIVA_I2C2_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C2 */ - -#if TIVA_I2C_USE_I2C3 - if (&I2CD4 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 3); - nvicDisableVector(TIVA_I2C3_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C3 */ - -#if TIVA_I2C_USE_I2C4 - if (&I2CD5 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 4); - nvicDisableVector(TIVA_I2C4_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C4 */ - -#if TIVA_I2C_USE_I2C5 - if (&I2CD6 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 5); - nvicDisableVector(TIVA_I2C5_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C5 */ - -#if TIVA_I2C_USE_I2C6 - if (&I2CD7 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 6); - nvicDisableVector(TIVA_I2C6_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C6 */ - -#if TIVA_I2C_USE_I2C7 - if (&I2CD8 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 7); - nvicDisableVector(TIVA_I2C7_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C7 */ - -#if TIVA_I2C_USE_I2C8 - if (&I2CD9 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 8); - nvicDisableVector(TIVA_I2C8_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C8 */ - -#if TIVA_I2C_USE_I2C9 - if (&I2CD10 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 9); - nvicDisableVector(TIVA_I2C9_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C9 */ - - dp->MCR = 0; - dp->MTPR = 0; - } -} - -/** - * @brief Receives data via the I2C bus as master. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if the function succeeded. - * @retval RDY_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval RDY_TIMEOUT if a timeout occurred before operation end. <b>After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state</b>. - * - * @notapi - */ -msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) -{ - I2C_TypeDef *dp = i2cp->i2c; - systime_t start, end; - - i2cp->rxbuf = rxbuf; - i2cp->rxbytes = rxbytes; - - /* Resetting error flags for this transfer.*/ - i2cp->errors = I2C_NO_ERROR; - - /* Initializes driver fields, LSB = 1 -> receive.*/ - i2cp->addr = (addr << 1) | 0x01; - - /* Releases the lock from high level driver.*/ - osalSysUnlock(); - - /* Calculating the time window for the timeout on the busy bus condition.*/ - start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT); - - /* Waits until BUSY flag is reset or, alternatively, for a timeout - condition.*/ - while (true) { - osalSysLock(); - - /* If the bus is not busy then the operation can continue, note, the - loop is exited in the locked state.*/ - if ((dp->MCS & TIVA_MCS_BUSY) == 0) - break; - - /* If the system time went outside the allowed window then a timeout - condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) - return MSG_TIMEOUT; - - osalSysUnlock(); - } - - /* set slave address */ - dp->MSA = addr; - - /* Starts the operation.*/ - dp->MCS = TIVA_I2C_SINGLE_RECEIVE; - - /* Waits for the operation completion or a timeout.*/ - return osalThreadSuspendTimeoutS(&i2cp->thread, timeout); -} - -/** - * @brief Transmits data via the I2C bus as master. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[in] txbuf pointer to the transmit buffer - * @param[in] txbytes number of bytes to be transmitted - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if the function succeeded. - * @retval RDY_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval RDY_TIMEOUT if a timeout occurred before operation end. <b>After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state</b>. - * - * @notapi - */ -msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) -{ - I2C_TypeDef *dp = i2cp->i2c; - systime_t start, end; - - i2cp->rxbuf = rxbuf; - i2cp->rxbytes = rxbytes; - i2cp->txbuf = txbuf; - i2cp->txbytes = txbytes; - - /* Resetting error flags for this transfer.*/ - i2cp->errors = I2C_NO_ERROR; - - /* Releases the lock from high level driver.*/ - osalSysUnlock(); - - /* Calculating the time window for the timeout on the busy bus condition.*/ - start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT); - - /* Waits until BUSY flag is reset or, alternatively, for a timeout - condition.*/ - while (true) { - osalSysLock(); - - /* If the bus is not busy then the operation can continue, note, the - loop is exited in the locked state.*/ - if ((dp->MCS & TIVA_MCS_BUSY) == 0) - break; - - /* If the system time went outside the allowed window then a timeout - condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) - return MSG_TIMEOUT; - - osalSysUnlock(); - } - - /* Initializes driver fields, LSB = 0 -> write.*/ - i2cp->addr = addr << 1 | 0; - - /* set slave address */ - dp->MSA = i2cp->addr; - - /* enable interrupts */ - dp->MIMR = TIVA_MIMR_IM; - - /* put data in register */ - dp->MDR = *(i2cp->txbuf); - - /* check if 1 or more bytes */ - if (i2cp->txbytes == 1) { - if (i2cp->rxbytes == 1) { - // one byte read - i2cp->intstate = STATE_READ_ONE; - } - else { - // multiple byte read - i2cp->intstate = STATE_READ_FIRST; - } - // single byte send - dp->MCS = TIVA_I2C_SIGNLE_SEND; - } - else { - if (i2cp->txbytes == 2) { - // 2 bytes - i2cp->intstate = STATE_WRITE_FINAL; - } - else { - // more then 2 bytes - i2cp->intstate = STATE_WRITE_NEXT; - } - // multiple bytes start send - dp->MCS = TIVA_I2C_BURST_SEND_START; - } - - i2cp->txbuf++; - i2cp->txbytes--; - - /* Waits for the operation completion or a timeout.*/ - return osalThreadSuspendTimeoutS(&i2cp->thread, timeout); -} - -#endif /* HAL_USE_I2C */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_i2c_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_i2c_lld.h deleted file mode 100644 index 460d231..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_i2c_lld.h +++ /dev/null @@ -1,527 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/i2c_lld.h - * @brief TM4C123x/TM4C129x I2C subsystem low level driver header. - * - * @addtogroup I2C - * @{ - */ - -#ifndef HAL_I2C_LLD_H -#define HAL_I2C_LLD_H - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define MTPR_VALUE ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1) - -#define TIVA_MSA_RS (1 << 0) -#define TIVA_MSA_SA (127 << 1) - -#define TIVA_MCS_BUSY (1 << 0) -#define TIVA_MCS_ERROR (1 << 1) -#define TIVA_MCS_ADRACK (1 << 2) -#define TIVA_MCS_DATACK (1 << 3) -#define TIVA_MCS_ARBLST (1 << 4) -#define TIVA_MCS_IDLE (1 << 5) -#define TIVA_MCS_BUSBSY (1 << 6) -#define TIVA_MCS_CLKTO (1 << 7) - -#define TIVA_MCS_RUN (1 << 0) -#define TIVA_MCS_START (1 << 1) -#define TIVA_MCS_STOP (1 << 2) -#define TIVA_MCS_ACK (1 << 3) -#define TIVA_MCS_HS (1 << 4) - -#define TIVA_I2C_SIGNLE_SEND (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_START (TIVA_MCS_RUN | TIVA_MCS_START) -#define TIVA_I2C_BURST_SEND_CONTINUE (TIVA_MCS_RUN) -#define TIVA_I2C_BURST_SEND_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_STOP (TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_ERROR_STOP (TIVA_MCS_STOP) - -#define TIVA_I2C_SINGLE_RECEIVE (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_RECEIVE_START (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_ACK) -#define TIVA_I2C_BURST_RECEIVE_CONTINUE (TIVA_MCS_RUN | TIVA_MCS_ACK) -#define TIVA_I2C_BURST_RECEIVE_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP (TIVA_MCS_STOP) - -#define TIVA_MDR_DATA (255 << 0) - -#define TIVA_MTPR_TPR (127 << 0) -#define TIVA_MTPR_HS (1 << 7) - -#define TIVA_MIMR_IM (1 << 0) -#define TIVA_MIMR_CLKIM (1 << 1) - -#define TIVA_MRIS_RIS (1 << 0) -#define TIVA_MRIS_CLKRIS (1 << 1) - -#define TIVA_MMIS_MIS (1 << 0) -#define TIVA_MMIS_CLKMIS (1 << 1) - -#define TIVA_MICR_IC (1 << 0) -#define TIVA_MICR_CLKIC (1 << 1) - -#define TIVA_MCR_LPBK (1 << 0) -#define TIVA_MCR_MFE (1 << 4) -#define TIVA_MCR_SFE (1 << 5) -#define TIVA_MCR_GFE (1 << 6) - -#define TIVA_MCLKOCNT_CNTL (255 << 0) - -#define TIVA_MBMON_SCL (1 << 0) -#define TIVA_MBMON_SDA (1 << 1) - -#define TIVA_MCR2_GFPW (7 << 4) - -// interrupt states -#define STATE_IDLE 0 -#define STATE_WRITE_NEXT 1 -#define STATE_WRITE_FINAL 2 -#define STATE_WAIT_ACK 3 -#define STATE_SEND_ACK 4 -#define STATE_READ_ONE 5 -#define STATE_READ_FIRST 6 -#define STATE_READ_NEXT 7 -#define STATE_READ_FINAL 8 -#define STATE_READ_WAIT 9 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief I2C0 driver enable switch. - * @details If set to @p TRUE the support for I2C0 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C0) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C0 FALSE -#endif - -/** - * @brief I2C1 driver enable switch. - * @details If set to @p TRUE the support for I2C1 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C1) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C1 FALSE -#endif - -/** - * @brief I2C2 driver enable switch. - * @details If set to @p TRUE the support for I2C2 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C2) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C2 FALSE -#endif - -/** - * @brief I2C3 driver enable switch. - * @details If set to @p TRUE the support for I2C3 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C3) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C3 FALSE -#endif - -/** - * @brief I2C4 driver enable switch. - * @details If set to @p TRUE the support for I2C4 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C4) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C4 FALSE -#endif - -/** - * @brief I2C5 driver enable switch. - * @details If set to @p TRUE the support for I2C5 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C5) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C5 FALSE -#endif - -/** - * @brief I2C6 driver enable switch. - * @details If set to @p TRUE the support for I2C6 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C6) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C6 FALSE -#endif - -/** - * @brief I2C7 driver enable switch. - * @details If set to @p TRUE the support for I2C7 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C7) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C7 FALSE -#endif - -/** - * @brief I2C8 driver enable switch. - * @details If set to @p TRUE the support for I2C8 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C8) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C8 FALSE -#endif - -/** - * @brief I2C9 driver enable switch. - * @details If set to @p TRUE the support for I2C9 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C9) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C9 FALSE -#endif - -/** - * @brief I2C timeout on busy condition in milliseconds. - */ -#if !defined(TIVA_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__) -#define TIVA_I2C_BUSY_TIMEOUT 50 -#endif - -/** - * @brief I2C0 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C0_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C1 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C1_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C2 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C2_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C3 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C3_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C4 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C4_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C5 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C5_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C6 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C6_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C7 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C7_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C8 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C8_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C9 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C9_IRQ_PRIORITY 4 -#endif - -/** - * @} - */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** - * @brief error checks - */ -#if !TIVA_I2C_USE_I2C0 && !TIVA_I2C_USE_I2C1 && !TIVA_I2C_USE_I2C2 && \ - !TIVA_I2C_USE_I2C3 && !TIVA_I2C_USE_I2C4 && !TIVA_I2C_USE_I2C5 && \ - !TIVA_I2C_USE_I2C6 && !TIVA_I2C_USE_I2C7 && !TIVA_I2C_USE_I2C8 && \ - !TIVA_I2C_USE_I2C9 -#error "I2C driver activated but no I2C peripheral assigned" -#endif - -#if TIVA_I2C_USE_I2C0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C0" -#endif - -#if TIVA_I2C_USE_I2C1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C1" -#endif - -#if TIVA_I2C_USE_I2C2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C2" -#endif - -#if TIVA_I2C_USE_I2C3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C3" -#endif - -#if TIVA_I2C_USE_I2C4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C4" -#endif - -#if TIVA_I2C_USE_I2C5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C5" -#endif - -#if TIVA_I2C_USE_I2C6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C6" -#endif - -#if TIVA_I2C_USE_I2C7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C7" -#endif - -#if TIVA_I2C_USE_I2C8 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C8" -#endif - -#if TIVA_I2C_USE_I2C9 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C9_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C9" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type representing I2C address. - */ -typedef uint16_t i2caddr_t; - -/** - * @brief I2C Driver condition flags type. - */ -typedef uint32_t i2cflags_t; - -/** - * @brief Driver configuration structure. - */ -typedef struct -{ - /** - * @brief Specifies the clock frequency. - * @note Must be set to a value lower than 3.33Mbps. - * TODO: high-speed mode: 3333 kHz. setup is 100-400-1000 kHz then switched to 3333 kHz - */ - uint32_t clock_speed; -} I2CConfig; - -/** - * @brief Type of a structure representing an I2C driver. - */ -typedef struct I2CDriver I2CDriver; - -/** - * @brief Structure representing an I2C driver. - */ -struct I2CDriver { - /** - * @brief Driver state. - */ - i2cstate_t state; - /** - * @brief Current configuration data. - */ - const I2CConfig *config; - /** - * @brief Error flags. - */ - i2cflags_t errors; -#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#endif /* I2C_USE_MUTUAL_EXCLUSION */ -#if defined(I2C_DRIVER_EXT_FIELDS) - I2C_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Thread waiting for I/O completion. - */ - thread_reference_t thread; - /** - * @brief Current slave address without R/W bit. - */ - i2caddr_t addr; - /** - * @brief Pointer to the buffer with data to send. - */ - const uint8_t *txbuf; - /** - * @brief Number of bytes of data to send. - */ - size_t txbytes; - /** - * @brief Pointer to the buffer to put received data. - */ - uint8_t *rxbuf; - /** - * @brief Number of bytes of data to receive. - */ - size_t rxbytes; - /** - * @brief State of the interrupt state machine. - * - * TODO is it possible to remove the interrupt state? - */ - uint8_t intstate; - /** - * @brief Pointer to the I2Cx registers block. - */ - I2C_TypeDef *i2c; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Get errors from I2C driver. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -#if TIVA_I2C_USE_I2C0 -extern I2CDriver I2CD1; -#endif - -#if TIVA_I2C_USE_I2C1 -extern I2CDriver I2CD2; -#endif - -#if TIVA_I2C_USE_I2C2 -extern I2CDriver I2CD3; -#endif - -#if TIVA_I2C_USE_I2C3 -extern I2CDriver I2CD4; -#endif - -#if TIVA_I2C_USE_I2C4 -extern I2CDriver I2CD5; -#endif - -#if TIVA_I2C_USE_I2C5 -extern I2CDriver I2CD6; -#endif - -#if TIVA_I2C_USE_I2C6 -extern I2CDriver I2CD7; -#endif - -#if TIVA_I2C_USE_I2C7 -extern I2CDriver I2CD8; -#endif - -#if TIVA_I2C_USE_I2C8 -extern I2CDriver I2CD9; -#endif - -#if TIVA_I2C_USE_I2C9 -extern I2CDriver I2CD10; -#endif - -#endif /* !defined(__DOXYGEN__) */ - -#ifdef __cplusplus -extern "C" { -#endif - void i2c_lld_init(void); - void i2c_lld_start(I2CDriver *i2cp); - void i2c_lld_stop(I2CDriver *i2cp); - msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); - msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2C */ - -#endif /* HAL_I2C_LLD_H */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_mac_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_mac_lld.c deleted file mode 100644 index 04177b6..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_mac_lld.c +++ /dev/null @@ -1,823 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/mac_lld.c - * @brief MAC Driver subsystem low level driver source. - * - * @addtogroup MAC - * @{ - */ - -#include <string.h> - -#include "hal.h" - -#if HAL_USE_MAC || defined(__DOXYGEN__) - -#include "hal_mii.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define BUFFER_SIZE ((((TIVA_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4) - -/* MII divider optimal value.*/ -#if (TIVA_SYSCLK >= 100000000) -#define MACMIIADDR_CR (0x01 << 2) -#elif (TIVA_SYSCLK >= 60000000) -#define MACMIIADDR_CR (0x00 << 2) -#elif (TIVA_SYSCLK >= 35000000) -#define MACMIIADDR_CR (0x03 << 2) -#elif (TIVA_SYSCLK >= 20000000) -#define MACMIIADDR_CR (0x02 << 2) -#else -#error "TIVA_SYSCLK below minimum frequency for ETH operations (20MHz)" -#endif - -#define EMAC_MIIADDR_MIIW 0x00000002 /* MII Write */ -#define EMAC_MIIADDR_MIIB 0x00000001 /* MII Busy */ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief Ethernet driver 1. - */ -MACDriver ETHD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13, - 0x37, 0x01, 0x10}; - -static tiva_eth_rx_descriptor_t rd[TIVA_MAC_RECEIVE_BUFFERS]; -static tiva_eth_tx_descriptor_t td[TIVA_MAC_TRANSMIT_BUFFERS]; - -static uint32_t rb[TIVA_MAC_RECEIVE_BUFFERS][BUFFER_SIZE]; -static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Writes a PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * @param[in] value new register value - * - * @notapi - */ -static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) -{ - ETH->MIIDATA = value; - ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB; - - while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) - ; -} - -/** - * @brief Writes an extended PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * @param[in] value new register value - * - * @notapi - */ -static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value) -{ - mii_write(macp, TIVA_REGCTL, 0x001F); - mii_write(macp, TIVA_ADDAR, reg); - - mii_write(macp, TIVA_REGCTL, 0x401F); - mii_write(macp, TIVA_ADDAR, value); -} - -/** - * @brief Reads a PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * - * @return The PHY register content. - * - * @notapi - */ -static uint32_t mii_read(MACDriver *macp, uint32_t reg) -{ - ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB; - - while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) - ; - - return ETH->MIIDATA; -} - -/** - * @brief Reads an extended PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * - * @return The extended PHY register content. - * - * @notapi - */ -static uint32_t mii_read_extended(MACDriver *macp, uint32_t reg) -{ - mii_write(macp, TIVA_REGCTL, 0x001F); - mii_write(macp, TIVA_ADDAR, reg); - - mii_write(macp, TIVA_REGCTL, 0x401F); - return mii_read(macp, TIVA_ADDAR); -} - -#if !defined(BOARD_PHY_ADDRESS) -/** - * @brief PHY address detection. - * - * @param[in] macp pointer to the @p MACDriver object - */ -static void mii_find_phy(MACDriver *macp) -{ - uint32_t i; - -#if TIVA_MAC_PHY_TIMEOUT > 0 - rtcnt_t start = chSysGetRealtimeCounterX(); - rtcnt_t timeout = start + MS2RTC(STM32_HCLK,STM32_MAC_PHY_TIMEOUT); - rtcnt_t time = start; - while (chSysIsCounterWithinX(time, start, timeout)) { -#endif - for (i = 0; i < 31; i++) { - macp->phyaddr = i << 11; - ETH->MIIDATA = (i << 6) | MACMIIADDR_CR; - if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) && - ((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) { - return; - } - } -#if TIVA_MAC_PHY_TIMEOUT > 0 - time = chSysGetRealtimeCounterX(); - } -#endif - /* Wrong or defective board.*/ - osalSysHalt("MAC failure"); -} -#endif - -/** - * @brief MAC address setup. - * - * @param[in] p pointer to a six bytes buffer containing the MAC - * address - */ -static void mac_lld_set_address(const uint8_t *p) -{ - /* MAC address configuration, only a single address comparator is used, - hash table not used.*/ - ETH->ADDR0H = ((uint32_t)p[5] << 8) | - ((uint32_t)p[4] << 0); - ETH->ADDR0L = ((uint32_t)p[3] << 24) | - ((uint32_t)p[2] << 16) | - ((uint32_t)p[1] << 8) | - ((uint32_t)p[0] << 0); - ETH->ADDR1H = 0x0000FFFF; - ETH->ADDR1L = 0xFFFFFFFF; - ETH->ADDR2H = 0x0000FFFF; - ETH->ADDR2L = 0xFFFFFFFF; - ETH->ADDR3H = 0x0000FFFF; - ETH->ADDR3L = 0xFFFFFFFF; - ETH->HASHTBLH = 0; - ETH->HASHTBLL = 0; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -CH_IRQ_HANDLER(TIVA_MAC_HANDLER) -{ - uint32_t dmaris; - - CH_IRQ_PROLOGUE(); - - dmaris = ETH->DMARIS; - ETH->DMARIS = dmaris & 0x0001FFFF; /* Clear status bits.*/ - - if (dmaris & (1 << 6)) { - /* Data Received.*/ - osalSysLockFromISR(); - osalThreadDequeueAllI(ÐD1.rdqueue, MSG_RESET); -#if MAC_USE_EVENTS - osalEventBroadcastFlagsI(ÐD1.rdevent, 0); -#endif - osalSysUnlockFromISR(); - } - - if (dmaris & (1 << 0)) { - /* Data Transmitted.*/ - osalSysLockFromISR(); - osalThreadDequeueAllI(ÐD1.tdqueue, MSG_RESET); - osalSysUnlockFromISR(); - } - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level MAC initialization. - * - * @notapi - */ -void mac_lld_init(void) -{ - uint8_t i; - - macObjectInit(ÐD1); - ETHD1.link_up = false; - - /* Descriptor tables are initialized in chained mode, note that the first - word is not initialized here but in mac_lld_start().*/ - for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) { - rd[i].rdes1 = TIVA_RDES1_RCH | TIVA_RDES1_RBS1(TIVA_MAC_BUFFERS_SIZE); - rd[i].rdes2 = (uint32_t)rb[i]; - rd[i].rdes3 = (uint32_t)&rd[(i + 1) % TIVA_MAC_RECEIVE_BUFFERS]; - } - for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) { - td[i].tdes1 = 0; - td[i].tdes2 = (uint32_t)tb[i]; - td[i].tdes3 = (uint32_t)&td[(i + 1) % TIVA_MAC_TRANSMIT_BUFFERS]; - } - - /* Enable MAC clock */ - SYSCTL->RCGCEMAC = 1; - while (SYSCTL->PREMAC != 0x01) - ; - - /* Set PHYHOLD bit */ - ETH->PC |= 1; - - /* Enable PHY clock */ - SYSCTL->RCGCEPHY = 1; - while (SYSCTL->PREPHY != 0x01) - ; - - /* Enable power to PHY */ - SYSCTL->PCEPHY |= 1; - while (SYSCTL->PREPHY != 0x01) - ; -#if BOARD_PHY_RMII - ETH->PC = EMAC_PHY_CONFIG | (0x04 << 28); -#else - ETH->PC = EMAC_PHY_CONFIG; -#endif - - /* - * Write OHY led configuration. - * 0: link ok - * 1: tx activity - * 2: link ok - * blink rate: 20Hz - */ - mii_write_extended(ÐD1, TIVA_LEDCFG, (0 << 8) | (2 << 4) | (0 << 0)); - mii_write(ÐD1, TIVA_LEDCR, (0 << 9)); - - /* Set done bit after writing EMACPC register */ - mii_write(ÐD1, TIVA_CFG1, (1 << 15) | mii_read(ÐD1, TIVA_CFG1)); - - while(ETH->DMABUSMOD & 1) - ; - - /* Reset MAC */ - ETH->DMABUSMOD |= 1; - while (ETH->DMABUSMOD & 1) - ; - - /* PHY address setup.*/ -#if defined(BOARD_PHY_ADDRESS) - ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11; -#else - mii_find_phy(ÐD1); -#endif - -#if defined(BOARD_PHY_RESET) - /* PHY board-specific reset procedure.*/ - BOARD_PHY_RESET(); -#else - /* PHY soft reset procedure.*/ - mii_write(ÐD1, MII_BMCR, BMCR_RESET); -#if defined(BOARD_PHY_RESET_DELAY) - chSysPolledDelayX(BOARD_PHY_RESET_DELAY); -#endif - while (mii_read(ÐD1, MII_BMCR) & BMCR_RESET) - ; -#endif - -#if TIVA_MAC_CHANGE_PHY_STATE - /* PHY in power down mode until the driver will be started.*/ - mii_write(ÐD1, MII_BMCR, mii_read(ÐD1, MII_BMCR) | BMCR_PDOWN); -#endif - - /* Disable MAC clock */ - SYSCTL->RCGCEMAC = 0; - - /* Disable PHY clock */ - SYSCTL->RCGCEPHY = 0; -} - -/** - * @brief Configures and activates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * - * @notapi - */ -void mac_lld_start(MACDriver *macp) -{ - uint8_t i; - - /* Resets the state of all descriptors.*/ - for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) { - rd[i].rdes0 = TIVA_RDES0_OWN; - } - macp->rxptr = (tiva_eth_rx_descriptor_t *)rd; - - for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) { - td[i].tdes0 = TIVA_TDES0_TCH; - td[i].locked = 0; - } - macp->txptr = (tiva_eth_tx_descriptor_t *)td; - - /* Enable MAC clock */ - SYSCTL->RCGCEMAC = 1; - while (SYSCTL->PREMAC != 0x01) - ; - - /* Enable PHY clock */ - SYSCTL->RCGCEPHY = 1; - while (!SYSCTL->PREPHY) - ; - - /* ISR vector enabled.*/ - nvicEnableVector(TIVA_MAC_NUMBER, TIVA_MAC_IRQ_PRIORITY); - -#if TIVA_MAC_CHANGE_PHY_STATE - /* PHY in power up mode.*/ - mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN); -#endif - - /* MAC configuration.*/ - ETH->FRAMEFLTR = 0; - ETH->FLOWCTL = 0; - ETH->VLANTG = 0; - - /* MAC address setup.*/ - if (macp->config->mac_address == NULL) - mac_lld_set_address(default_mac_address); - else - mac_lld_set_address(macp->config->mac_address); - - /* Transmitter and receiver enabled. - Note that the complete setup of the MAC is performed when the link - status is detected.*/ -#if TIVA_MAC_IP_CHECKSUM_OFFLOAD - ETH->CFG = (1 << 10) | (1 << 3) | (1 << 2); -#else - ETH->CFG = (1 << 3) | (1 << 2); -#endif - - /* DMA configuration: - Descriptor chains pointers.*/ - ETH->RXDLADDR = (uint32_t)rd; - ETH->TXDLADDR = (uint32_t)td; - - /* Enabling required interrupt sources.*/ - ETH->DMARIS &= 0xFFFF; - ETH->DMAIM = (1 << 16) | (1 << 6) | (1 << 0); - - /* DMA general settings.*/ - ETH->DMABUSMOD = (1 << 25) | (1 << 17) | (1 << 8); - - /* Transmit FIFO flush.*/ - ETH->DMAOPMODE = (1 << 20); - while (ETH->DMAOPMODE & (1 << 20)) - ; - - /* DMA final configuration and start.*/ - ETH->DMAOPMODE = (1 << 26) | (1 << 25) | (1 << 21) | - (1 << 13) | (1 << 1); -} - -/** - * @brief Deactivates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * - * @notapi - */ -void mac_lld_stop(MACDriver *macp) -{ - if (macp->state != MAC_STOP) { -#if TIVA_MAC_CHANGE_PHY_STATE - /* PHY in power down mode until the driver will be restarted.*/ - mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN); -#endif - - /* MAC and DMA stopped.*/ - ETH->CFG = 0; - ETH->DMAOPMODE = 0; - ETH->DMAIM = 0; - ETH->DMARIS &= 0xFFFF; - - /* MAC clocks stopped.*/ - SYSCTL->RCGCEMAC = 0; - - /* PHY clock stopped.*/ - SYSCTL->RCGCEPHY = 0; - - /* ISR vector disabled.*/ - nvicDisableVector(TIVA_MAC_NUMBER); - } -} - -/** - * @brief Returns a transmission descriptor. - * @details One of the available transmission descriptors is locked and - * returned. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] tdp pointer to a @p MACTransmitDescriptor structure - * @return The operation status. - * @retval RDY_OK the descriptor has been obtained. - * @retval RDY_TIMEOUT descriptor not available. - * - * @notapi - */ -msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp) -{ - tiva_eth_tx_descriptor_t *tdes; - - if (!macp->link_up) - return MSG_TIMEOUT; - - osalSysLock(); - - /* Get Current TX descriptor.*/ - tdes = macp->txptr; - - /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by - another thread.*/ - if (tdes->tdes0 & (TIVA_TDES0_OWN) || (tdes->locked)) { - osalSysUnlock(); - return MSG_TIMEOUT; - } - - /* Marks the current descriptor as locked.*/ - tdes->locked = 1; - - /* Next TX descriptor to use.*/ - macp->txptr = (tiva_eth_tx_descriptor_t *)tdes->tdes3; - - osalSysUnlock(); - - /* Set the buffer size and configuration.*/ - tdp->offset = 0; - tdp->size = TIVA_MAC_BUFFERS_SIZE; - tdp->physdesc = tdes; - - return MSG_OK; -} - -/** - * @brief Releases a transmit descriptor and starts the transmission of the - * enqueued data as a single frame. - * - * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure - * - * @notapi - */ -void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) -{ - osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN), - "attempt to release descriptor already owned by DMA"); - - osalSysLock(); - - /* Unlocks the descriptor and returns it to the DMA engine.*/ - tdp->physdesc->tdes1 = tdp->offset; - tdp->physdesc->tdes0 = TIVA_TDES0_CIC(TIVA_MAC_IP_CHECKSUM_OFFLOAD) | - TIVA_TDES0_IC | TIVA_TDES0_LS | TIVA_TDES0_FS | - TIVA_TDES0_TCH | TIVA_TDES0_OWN; - tdp->physdesc->locked = 0; - - /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->DMARIS & (0x7 << 20)) == (6 << 20)) { - ETH->DMARIS = (1 << 2); - ETH->TXPOLLD = 1; /* Any value is OK.*/ - } - - osalSysUnlock(); -} - -/** - * @brief Returns a receive descriptor. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] rdp pointer to a @p MACReceiveDescriptor structure - * @return The operation status. - * @retval RDY_OK the descriptor has been obtained. - * @retval RDY_TIMEOUT descriptor not available. - * - * @notapi - */ -msg_t mac_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp) -{ - tiva_eth_rx_descriptor_t *rdes; - - osalSysLock(); - - /* Get Current RX descriptor.*/ - rdes = macp->rxptr; - - /* Iterates through received frames until a valid one is found, invalid - frames are discarded.*/ - while (!(rdes->rdes0 & TIVA_RDES0_OWN)) { - if (!(rdes->rdes0 & (TIVA_RDES0_AFM | TIVA_RDES0_ES)) -#if TIVA_MAC_IP_CHECKSUM_OFFLOAD - && (rdes->rdes0 & TIVA_RDES0_FT) - && !(rdes->rdes0 & (TIVA_RDES0_IPHCE | TIVA_RDES0_PCE)) -#endif - && (rdes->rdes0 & TIVA_RDES0_FS) && (rdes->rdes0 & TIVA_RDES0_LS)) { - /* Found a valid one.*/ - rdp->offset = 0; - rdp->size = ((rdes->rdes0 & TIVA_RDES0_FL_MASK) >> 16) - 4; - rdp->physdesc = rdes; - macp->rxptr = (tiva_eth_rx_descriptor_t *)rdes->rdes3; - - osalSysUnlock(); - return MSG_OK; - } - /* Invalid frame found, purging.*/ - rdes->rdes0 = TIVA_RDES0_OWN; - rdes = (tiva_eth_rx_descriptor_t *)rdes->rdes3; - } - - /* Next descriptor to check.*/ - macp->rxptr = rdes; - - osalSysUnlock(); - return MSG_TIMEOUT; -} - -/** - * @brief Releases a receive descriptor. - * @details The descriptor and its buffer are made available for more incoming - * frames. - * - * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure - * - * @notapi - */ -void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) -{ - osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN), - "attempt to release descriptor already owned by DMA"); - - osalSysLock(); - - /* Give buffer back to the Ethernet DMA.*/ - rdp->physdesc->rdes0 = TIVA_RDES0_OWN; - - /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->STATUS & (0xf << 17)) == (4 << 17)) { - ETH->DMARIS = (1 << 7); - ETH->TXPOLLD = 1; /* Any value is OK.*/ - } - - osalSysUnlock(); -} - -/** - * @brief Updates and returns the link status. - * - * @param[in] macp pointer to the @p MACDriver object - * @return The link status. - * @retval TRUE if the link is active. - * @retval FALSE if the link is down. - * - * @notapi - */ -bool mac_lld_poll_link_status(MACDriver *macp) -{ - uint32_t maccfg, bmsr, bmcr; - - maccfg = ETH->CFG; - - /* PHY CR and SR registers read.*/ - (void)mii_read(macp, MII_BMSR); - bmsr = mii_read(macp, MII_BMSR); - bmcr = mii_read(macp, MII_BMCR); - - /* Check on auto-negotiation mode.*/ - if (bmcr & BMCR_ANENABLE) { - uint32_t lpa; - - /* Auto-negotiation must be finished without faults and link established.*/ - if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) != - (BMSR_LSTATUS | BMSR_ANEGCOMPLETE)) - return macp->link_up = false; - - /* Auto-negotiation enabled, checks the LPA register.*/ - lpa = mii_read(macp, MII_LPA); - - /* Check on link speed.*/ - if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4)) - maccfg |= (1 << 14); - else - maccfg &= ~(1 << 14); - - /* Check on link mode.*/ - if (lpa & (LPA_10FULL | LPA_100FULL)) - maccfg |= (1 << 11); - else - maccfg &= ~(1 << 11); - } - else { - /* Link must be established.*/ - if (!(bmsr & BMSR_LSTATUS)) - return macp->link_up = false; - - /* Check on link speed.*/ - if (bmcr & BMCR_SPEED100) - maccfg |= (1 << 14); - else - maccfg &= ~(1 << 14); - - /* Check on link mode.*/ - if (bmcr & BMCR_FULLDPLX) - maccfg |= (1 << 11); - else - maccfg &= ~(1 << 11); - } - - /* Changes the mode in the MAC.*/ - ETH->CFG = maccfg; - - /* Returns the link status.*/ - return macp->link_up = true; -} - -/** - * @brief Writes to a transmit descriptor's stream. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] buf pointer to the buffer containing the data to be - * written - * @param[in] size number of bytes to be written - * @return The number of bytes written into the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if the maximum - * frame size is reached. - * - * @notapi - */ -size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size) -{ - osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN), - "attempt to write descriptor already owned by DMA"); - - if (size > tdp->size - tdp->offset) - size = tdp->size - tdp->offset; - - if (size > 0) { - memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size); - tdp->offset += size; - } - return size; -} - -/** - * @brief Reads from a receive descriptor's stream. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] buf pointer to the buffer that will receive the read data - * @param[in] size number of bytes to be read - * @return The number of bytes read from the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if there are - * no more bytes to read. - * - * @notapi - */ -size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size) -{ - osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN), - "attempt to read descriptor already owned by DMA"); - - if (size > rdp->size - rdp->offset) - size = rdp->size - rdp->offset; - - if (size > 0) { - memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size); - rdp->offset += size; - } - return size; -} - -#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__) -/** - * @brief Returns a pointer to the next transmit buffer in the descriptor - * chain. - * @note The API guarantees that enough buffers can be requested to fill - * a whole frame. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] size size of the requested buffer. Specify the frame size - * on the first call then scale the value down subtracting - * the amount of data already copied into the previous - * buffers. - * @param[out] sizep pointer to variable receiving the buffer size, it is - * zero when the last buffer has already been returned. - * Note that a returned size lower than the amount - * requested means that more buffers must be requested - * in order to fill the frame data entirely. - * @return Pointer to the returned buffer. - * @retval NULL if the buffer chain has been entirely scanned. - * - * @notapi - */ -uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, - size_t size, - size_t *sizep) -{ - if (tdp->offset == 0) { - *sizep = tdp->size; - tdp->offset = size; - return (uint8_t *)tdp->physdesc->tdes2; - } - *sizep = 0; - return NULL; -} - -/** - * @brief Returns a pointer to the next receive buffer in the descriptor - * chain. - * @note The API guarantees that the descriptor chain contains a whole - * frame. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[out] sizep pointer to variable receiving the buffer size, it is - * zero when the last buffer has already been returned. - * @return Pointer to the returned buffer. - * @retval NULL if the buffer chain has been entirely scanned. - * - * @notapi - */ -const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, - size_t *sizep) -{ - if (rdp->size > 0) { - *sizep = rdp->size; - rdp->offset = rdp->size; - rdp->size = 0; - return (uint8_t *)rdp->physdesc->rdes2; - } - *sizep = 0; - return NULL; -} -#endif /* MAC_USE_ZERO_COPY */ - -#endif /* HAL_USE_MAC */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_mac_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_mac_lld.h deleted file mode 100644 index 98036bb..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_mac_lld.h +++ /dev/null @@ -1,438 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/mac_lld.h - * @brief MAC Driver subsystem low level driver header. - * - * @addtogroup MAC - * @{ - */ - -#ifndef HAL_MAC_LLD_H -#define HAL_MAC_LLD_H - -#if HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief This implementation supports the zero-copy mode API. - */ -#define MAC_SUPPORTS_ZERO_COPY TRUE - -/** - * @name RDES0 constants - * @{ - */ -#define TIVA_RDES0_OWN 0x80000000 -#define TIVA_RDES0_AFM 0x40000000 - -#define TIVA_RDES0_FL_MASK 0x3FFF0000 -#define TIVA_RDES0_FL(n) ((n) << 16) - -#define TIVA_RDES0_ES 0x00008000 -#define TIVA_RDES0_DESERR 0x00004000 -#define TIVA_RDES0_SAF 0x00002000 -#define TIVA_RDES0_LE 0x00001000 -#define TIVA_RDES0_OE 0x00000800 -#define TIVA_RDES0_VLAN 0x00000400 -#define TIVA_RDES0_FS 0x00000200 -#define TIVA_RDES0_LS 0x00000100 -#define TIVA_RDES0_TAGF 0x00000080 -#define TIVA_RDES0_LC 0x00000040 -#define TIVA_RDES0_FT 0x00000020 -#define TIVA_RDES0_RWT 0x00000010 -#define TIVA_RDES0_RE 0x00000008 -#define TIVA_RDES0_DE 0x00000004 -#define TIVA_RDES0_CE 0x00000002 -#define TIVA_RDES0_ESA 0x00000001 -/** @} */ - -/** - * @name RDES1 constants - * @{ - */ -#define TIVA_RDES1_DIC 0x80000000 - -#define TIVA_RDES1_RBS2_MASK 0x1FFF0000 -#define TIVA_RDES1_RBS2(n) ((n) << 16) - -#define TIVA_RDES1_RER 0x00008000 -#define TIVA_RDES1_RCH 0x00004000 - -#define TIVA_RDES1_RBS1_MASK 0x00001FFF -#define TIVA_RDES1_RBS1(n) ((n) << 0) - -/** @} */ - -/** - * @name TDES0 constants - * @{ - */ -#define TIVA_TDES0_OWN 0x80000000 -#define TIVA_TDES0_IC 0x40000000 -#define TIVA_TDES0_LS 0x20000000 -#define TIVA_TDES0_FS 0x10000000 -#define TIVA_TDES0_DC 0x08000000 -#define TIVA_TDES0_DP 0x04000000 -#define TIVA_TDES0_TTSE 0x02000000 -#define TIVA_TDES0_CRCR 0x01000000 - -#define TIVA_TDES0_CIC_MASK 0x00C00000 -#define TIVA_TDES0_CIC(n) ((n) << 22) - -#define TIVA_TDES0_TER 0x00200000 -#define TIVA_TDES0_TCH 0x00100000 -#define TIVA_TDES0_VLIC 0x000C0000 -#define TIVA_TDES0_TTSS 0x00020000 -#define TIVA_TDES0_IHE 0x00010000 -#define TIVA_TDES0_ES 0x00008000 -#define TIVA_TDES0_JT 0x00004000 -#define TIVA_TDES0_FF 0x00002000 -#define TIVA_TDES0_IPE 0x00001000 -#define TIVA_TDES0_LC 0x00000800 -#define TIVA_TDES0_NC 0x00000400 -#define TIVA_TDES0_LCO 0x00000200 -#define TIVA_TDES0_EC 0x00000100 -#define TIVA_TDES0_VF 0x00000080 - -#define TIVA_TDES0_CC_MASK 0x00000078 -#define TIVA_TDES0_CC(n) ((n) << 3) - -#define TIVA_TDES0_ED 0x00000004 -#define TIVA_TDES0_UF 0x00000002 -#define TIVA_TDES0_DB 0x00000001 -/** @} */ - -/** - * @name TDES1 constants - * @{ - */ -#define TIVA_TDES1_SAIC_MASK 0xE0000000 -#define TIVA_TDES1_SAIC(n) ((n) << 29) - -#define TIVA_TDES1_TBS2_MASK 0x1FFF0000 -#define TIVA_TDES1_TBS2(n) ((n) << 16) - -#define TIVA_TDES1_TBS1_MASK 0x00001FFF -#define TIVA_TDES1_TBS1(n) ((n) << 0) -/** @} */ - - - - -/** - * @name Ethernet PHY registers - */ -#define TIVA_BMCR 0x00000000 /* MR0 - Basic Mode Control */ -#define TIVA_BMSR 0x00000001 /* MR1 - Basic Mode Status */ -#define TIVA_ID1 0x00000002 /* MR2 - Identifier Register 1 */ -#define TIVA_ID2 0x00000003 /* MR3 - Identifier Register 2 */ -#define TIVA_ANA 0x00000004 /* MR4 - Auto-Negotiation Advertisement */ -#define TIVA_ANLPA 0x00000005 /* MR5 - Auto-Negotiation Link Partner Ability */ -#define TIVA_ANER 0x00000006 /* MR6 - Auto-Negotiation Expansion */ -#define TIVA_ANNPTR 0x00000007 /* MR7 - Auto-Negotiation Next Page TX */ -#define TIVA_ANLNPTR 0x00000008 /* MR8 - Auto-Negotiation Link Partner Ability Next Page */ -#define TIVA_CFG1 0x00000009 /* MR9 - Configuration 1 */ -#define TIVA_CFG2 0x0000000A /* MR10 - Configuration 2 */ -#define TIVA_CFG3 0x0000000B /* MR11 - Configuration 3 */ -#define TIVA_REGCTL 0x0000000D /* MR13 - Register Control */ -#define TIVA_ADDAR 0x0000000E /* MR14 - Address or Data */ -#define TIVA_STS 0x00000010 /* MR16 - Status */ -#define TIVA_SCR 0x00000011 /* MR17 - Specific Control */ -#define TIVA_MISR1 0x00000012 /* MR18 - MII Interrupt Status 1 */ -#define TIVA_MISR2 0x00000013 /* MR19 - MII Interrupt Status 2 */ -#define TIVA_FCSCR 0x00000014 /* MR20 - False Carrier Sense Counter */ -#define TIVA_RXERCNT 0x00000015 /* MR21 - Receive Error Count */ -#define TIVA_BISTCR 0x00000016 /* MR22 - BIST Control */ -#define TIVA_LEDCR 0x00000018 /* MR24 - LED Control */ -#define TIVA_CTL 0x00000019 /* MR25 - Control */ -#define TIVA_10BTSC 0x0000001A /* MR26 - 10Base-T Status/Control - MR26 */ -#define TIVA_BICSR1 0x0000001B /* MR27 - BIST Control and Status 1 */ -#define TIVA_BICSR2 0x0000001C /* MR28 - BIST Control and Status 2 */ -#define TIVA_CDCR 0x0000001E /* MR30 - Cable Diagnostic Control */ -#define TIVA_RCR 0x0000001F /* MR31 - Reset Control */ -#define TIVA_LEDCFG 0x00000025 /* MR37 - LED Configuration */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Number of available transmit buffers. - */ -#if !defined(TIVA_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) -#define TIVA_MAC_TRANSMIT_BUFFERS 2 -#endif - -/** - * @brief Number of available receive buffers. - */ -#if !defined(TIVA_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) -#define TIVA_MAC_RECEIVE_BUFFERS 4 -#endif - -/** - * @brief Maximum supported frame size. - */ -#if !defined(TIVA_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define TIVA_MAC_BUFFERS_SIZE 1522 -#endif - -/** - * @brief PHY detection timeout. - * @details Timeout, in milliseconds, for PHY address detection, if a PHY - * is not detected within the timeout then the driver halts during - * initialization. This setting applies only if the PHY address is - * not explicitly set in the board header file using - * @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a - * single search path is performed. - */ -#if !defined(TIVA_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__) -#define TIVA_MAC_PHY_TIMEOUT 0 -#endif - -/** - * @brief Change the PHY power state inside the driver. - */ -#if !defined(TIVA_MAC_CHANGE_PHY_STATE) || defined(__DOXYGEN__) -#define TIVA_MAC_CHANGE_PHY_STATE TRUE -#endif - -/** - * @brief ETHD1 interrupt priority level setting. - */ -#if !defined(TIVA_MAC_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_MAC_IRQ_PRIORITY 5 -#endif - -/** - * @brief IP checksum offload. - * @details The following modes are available: - * - 0 Function disabled. - * - 1 Only IP header checksum calculation and insertion are enabled. - * - 2 IP header checksum and payload checksum calculation and - * insertion are enabled, but pseudo-header checksum is not - * calculated in hardware. - * - 3 IP Header checksum and payload checksum calculation and - * insertion are enabled, and pseudo-header checksum is - * calculated in hardware. - * . - */ -#if !defined(TIVA_MAC_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__) -#define TIVA_MAC_IP_CHECKSUM_OFFLOAD 0 -#endif -/** @} */ - -#ifndef EMAC_PHY_CONFIG -#define EMAC_PHY_CONFIG ((0 << 31) | \ - (1 << 23) | \ - (1 << 10) | \ - (1 << 3) | \ - (3 << 1) | \ - (1 << 0)) -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (TIVA_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS -#error "TIVA_MAC_PHY_TIMEOUT requires the realtime counter service" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_MAC_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to MAC" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of an Tiva Ethernet receive descriptor. - */ -typedef struct -{ - volatile uint32_t rdes0; - volatile uint32_t rdes1; - volatile uint32_t rdes2; - volatile uint32_t rdes3; -} tiva_eth_rx_descriptor_t; - -/** - * @brief Type of an Tiva Ethernet transmit descriptor. - */ -typedef struct -{ - volatile uint32_t tdes0; - volatile uint32_t tdes1; - volatile uint32_t tdes2; - volatile uint32_t tdes3; - volatile uint32_t locked; -} tiva_eth_tx_descriptor_t; - -/** - * @brief Driver configuration structure. - */ -typedef struct -{ - /** - * @brief MAC address. - */ - uint8_t *mac_address; - /* End of the mandatory fields.*/ -} MACConfig; - -/** - * @brief Structure representing a MAC driver. - */ -struct MACDriver -{ - /** - * @brief Driver state. - */ - macstate_t state; - /** - * @brief Current configuration data. - */ - const MACConfig *config; - /** - * @brief Transmit semaphore. - */ - threads_queue_t tdqueue; - /** - * @brief Receive semaphore. - */ - threads_queue_t rdqueue; -#if MAC_USE_EVENTS || defined(__DOXYGEN__) - /** - * @brief Receive event. - */ - event_source_t rdevent; -#endif - /* End of the mandatory fields.*/ - /** - * @brief Link status flag. - */ - bool link_up; - /** - * @brief PHY address (pre shifted). - */ - uint32_t phyaddr; - /** - * @brief Receive next frame pointer. - */ - tiva_eth_rx_descriptor_t *rxptr; - /** - * @brief Transmit next frame pointer. - */ - tiva_eth_tx_descriptor_t *txptr; -}; - -/** - * @brief Structure representing a transmit descriptor. - */ -typedef struct -{ - /** - * @brief Current write offset. - */ - size_t offset; - /** - * @brief Available space size. - */ - size_t size; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the physical descriptor. - */ - tiva_eth_tx_descriptor_t *physdesc; -} MACTransmitDescriptor; - -/** - * @brief Structure representing a receive descriptor. - */ -typedef struct -{ - /** - * @brief Current read offset. - */ - size_t offset; - /** - * @brief Available data size. - */ - size_t size; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the physical descriptor. - */ - tiva_eth_rx_descriptor_t *physdesc; -} MACReceiveDescriptor; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern MACDriver ETHD1; - -#ifdef __cplusplus -extern "C" { -#endif - void mac_lld_init(void); - void mac_lld_start(MACDriver *macp); - void mac_lld_stop(MACDriver *macp); - msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp); - void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); - msg_t mac_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp); - void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); - bool mac_lld_poll_link_status(MACDriver *macp); - size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size); - size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size); -#if MAC_USE_ZERO_COPY - uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, - size_t size, - size_t *sizep); - const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, - size_t *sizep); -#endif /* MAC_USE_ZERO_COPY */ -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_MAC */ - -#endif /* HAL_MAC_LLD_H */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_pal_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_pal_lld.c deleted file mode 100644 index 5460fd4..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_pal_lld.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/pal_lld.c - * @brief TM4C123x/TM4C129x PAL subsystem low level driver. - * - * @addtogroup PAL - * @{ - */ - -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) -#define GPIOA_BIT (1 << 0) -#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x) -#define GPIOA_AHB_BIT (1 << 0) -#else -#define GPIOA_AHB_BIT 0 -#endif -#else -#define GPIOA_BIT 0 -#define GPIOA_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) -#define GPIOB_BIT (1 << 1) -#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x) -#define GPIOB_AHB_BIT (1 << 1) -#else -#define GPIOB_AHB_BIT 0 -#endif -#else -#define GPIOB_BIT 0 -#define GPIOB_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) -#define GPIOC_BIT (1 << 2) -#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x) -#define GPIOC_AHB_BIT (1 << 2) -#else -#define GPIOC_AHB_BIT 0 -#endif -#else -#define GPIOC_BIT 0 -#define GPIOC_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) -#define GPIOD_BIT (1 << 3) -#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x) -#define GPIOD_AHB_BIT (1 << 3) -#else -#define GPIOD_AHB_BIT 0 -#endif -#else -#define GPIOD_BIT 0 -#define GPIOD_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) -#define GPIOE_BIT (1 << 4) -#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x) -#define GPIOE_AHB_BIT (1 << 4) -#else -#define GPIOE_AHB_BIT 0 -#endif -#else -#define GPIOE_BIT 0 -#define GPIOE_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) -#define GPIOF_BIT (1 << 5) -#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x) -#define GPIOF_AHB_BIT (1 << 5) -#else -#define GPIOF_AHB_BIT 0 -#endif -#else -#define GPIOF_BIT 0 -#define GPIOF_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) -#define GPIOG_BIT (1 << 6) -#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x) -#define GPIOG_AHB_BIT (1 << 6) -#else -#define GPIOG_AHB_BIT 0 -#endif -#else -#define GPIOG_BIT 0 -#define GPIOG_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) -#define GPIOH_BIT (1 << 7) -#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x) -#define GPIOH_AHB_BIT (1 << 7) -#else -#define GPIOH_AHB_BIT 0 -#endif -#else -#define GPIOH_BIT 0 -#define GPIOH_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) -#define GPIOJ_BIT (1 << 8) -#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x) -#define GPIOJ_AHB_BIT (1 << 8) -#else -#define GPIOJ_AHB_BIT 0 -#endif -#else -#define GPIOJ_BIT 0 -#define GPIOJ_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) -#define GPIOK_BIT (1 << 9) -#define GPIOK_AHB_BIT (1 << 9) -#else -#define GPIOK_BIT 0 -#define GPIOK_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) -#define GPIOL_BIT (1 << 10) -#define GPIOL_AHB_BIT (1 << 10) -#else -#define GPIOL_BIT 0 -#define GPIOL_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) -#define GPIOM_BIT (1 << 11) -#define GPIOM_AHB_BIT (1 << 11) -#else -#define GPIOM_BIT 0 -#define GPIOM_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) -#define GPION_BIT (1 << 12) -#define GPION_AHB_BIT (1 << 12) -#else -#define GPION_BIT 0 -#define GPION_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) -#define GPIOP_BIT (1 << 13) -#define GPIOP_AHB_BIT (1 << 13) -#else -#define GPIOP_BIT 0 -#define GPIOP_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) -#define GPIOQ_BIT (1 << 14) -#define GPIOQ_AHB_BIT (1 << 14) -#else -#define GPIOQ_BIT 0 -#define GPIOQ_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) -#define GPIOR_BIT (1 << 15) -#define GPIOR_AHB_BIT (1 << 15) -#else -#define GPIOR_BIT 0 -#define GPIOR_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) -#define GPIOS_BIT (1 << 16) -#define GPIOS_AHB_BIT (1 << 16) -#else -#define GPIOS_BIT 0 -#define GPIOS_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) -#define GPIOT_BIT (1 << 17) -#define GPIOT_AHB_BIT (1 << 17) -#else -#define GPIOT_BIT 0 -#define GPIOT_AHB_BIT 0 -#endif - -#define RCGCGPIO_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \ - GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \ - GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT | \ - GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT | \ - GPIOS_BIT | GPIOR_BIT) - -#define GPIOHBCTL_MASK (GPIOA_AHB_BIT | GPIOB_AHB_BIT | GPIOC_AHB_BIT | \ - GPIOD_AHB_BIT | GPIOE_AHB_BIT | GPIOF_AHB_BIT | \ - GPIOG_AHB_BIT | GPIOH_AHB_BIT | GPIOJ_AHB_BIT | \ - GPIOK_AHB_BIT | GPIOL_AHB_BIT | GPIOM_AHB_BIT | \ - GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT | \ - GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT) - -/* GPIO lock password.*/ -#define TIVA_GPIO_LOCK_PWD 0x4C4F434B - -#define GPIOC_JTAG_MASK (0x0F) -#define GPIOD_NMI_MASK (0x80) -#define GPIOF_NMI_MASK (0x01) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the port with the port configuration. - * - * @param[in] port the port identifier - * @param[in] config the port configuration - */ -static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config) -{ - port->DATA = config->data; - port->DIR = config->dir; - port->AFSEL = config->afsel; - port->DR2R = config->dr2r; - port->DR4R = config->dr4r; - port->DR8R = config->dr8r; - port->ODR = config->odr; - port->PUR = config->pur; - port->PDR = config->pdr; - port->SLR = config->slr; - port->DEN = config->den; - port->AMSEL = config->amsel; - port->PCTL = config->pctl; -} - -/** - * @brief Unlocks the masked pins of the GPIO peripheral. - * @note This function is only useful for PORTC0-3, PORTD7 and PORTF0. - * - * @param[in] port the port identifier - * @param[in] mask the pin mask - */ -static void gpio_unlock(ioportid_t port, ioportmask_t mask) -{ - port->LOCK = TIVA_GPIO_LOCK_PWD; - port->CR = mask; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Tiva I/O ports configuration. - * @details Ports A-F (G, H, J, K, L, M, N, P, Q, R, S, T) clocks enabled. - * - * @param[in] config the Tiva ports configuration - * - * @notapi - */ -void _pal_lld_init(const PALConfig *config) -{ - /* - * Enables all GPIO clocks. - */ - SYSCTL->RCGCGPIO = RCGCGPIO_MASK; -#if defined(TM4C123x) - SYSCTL->GPIOHBCTL = GPIOHBCTL_MASK; -#endif - - /* Wait until all GPIO modules are ready */ - while (!((SYSCTL->PRGPIO & RCGCGPIO_MASK) == RCGCGPIO_MASK)) - ; - -#if TIVA_HAS_GPIOA - gpio_init(GPIOA, &config->PAData); -#endif -#if TIVA_HAS_GPIOB - gpio_init(GPIOB, &config->PBData); -#endif -#if TIVA_HAS_GPIOC - /* Unlock JTAG pins.*/ - gpio_unlock(GPIOC, GPIOC_JTAG_MASK); - gpio_init(GPIOC, &config->PCData); -#endif -#if TIVA_HAS_GPIOD - /* Unlock NMI pin.*/ - gpio_unlock(GPIOD, GPIOD_NMI_MASK); - gpio_init(GPIOD, &config->PDData); -#endif -#if TIVA_HAS_GPIOE - gpio_init(GPIOE, &config->PEData); -#endif -#if TIVA_HAS_GPIOF - /* Unlock NMI pin.*/ - gpio_unlock(GPIOF, GPIOF_NMI_MASK); - gpio_init(GPIOF, &config->PFData); -#endif -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) - gpio_init(GPIOG, &config->PGData); -#endif -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) - gpio_init(GPIOH, &config->PHData); -#endif -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_init(GPIOJ, &config->PJData); -#endif -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) - gpio_init(GPIOK, &config->PKData); -#endif -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) - gpio_init(GPIOL, &config->PLData); -#endif -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) - gpio_init(GPIOM, &config->PMData); -#endif -#if TIVA_HAS_GPION || defined(__DOXYGEN__) - gpio_init(GPION, &config->PNData); -#endif -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) - gpio_init(GPIOP, &config->PPData); -#endif -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) - gpio_init(GPIOQ, &config->PQData); -#endif -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) - gpio_init(GPIOR, &config->PRData); -#endif -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) - gpio_init(GPIOS, &config->PSData); -#endif -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) - gpio_init(GPIOT, &config->PTData); -#endif -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @notapi - */ -void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) -{ - uint32_t dir = (mode & PAL_TIVA_DIR_MASK) >> 0; - uint32_t afsel = (mode & PAL_TIVA_AFSEL_MASK) >> 1; - uint32_t dr2r = (mode & PAL_TIVA_DR2R_MASK) >> 2; - uint32_t dr4r = (mode & PAL_TIVA_DR4R_MASK) >> 3; - uint32_t dr8r = (mode & PAL_TIVA_DR8R_MASK) >> 4; - uint32_t odr = (mode & PAL_TIVA_ODR_MASK) >> 5; - uint32_t pur = (mode & PAL_TIVA_PUR_MASK) >> 6; - uint32_t pdr = (mode & PAL_TIVA_PDR_MASK) >> 7; - uint32_t slr = (mode & PAL_TIVA_SLR_MASK) >> 8; - uint32_t den = (mode & PAL_TIVA_DEN_MASK) >> 9; - uint32_t amsel = (mode & PAL_TIVA_AMSEL_MASK) >> 10; - uint32_t pctl = (mode & PAL_TIVA_PCTL_MASK) >> 11; - uint32_t bit = 0; - - while(TRUE) { - uint32_t pctl_mask = (7 << (4 * bit)); - uint32_t bit_mask = (1 << bit); - - if ((mask & 1) != 0) { - port->DIR = (port->DIR & ~bit_mask) | dir; - port->AFSEL = (port->AFSEL & ~bit_mask) | afsel; - port->DR2R = (port->DR2R & ~bit_mask) | dr2r; - port->DR4R = (port->DR4R & ~bit_mask) | dr4r; - port->DR8R = (port->DR8R & ~bit_mask) | dr8r; - port->ODR = (port->ODR & ~bit_mask) | odr; - port->PUR = (port->PUR & ~bit_mask) | pur; - port->PDR = (port->PDR & ~bit_mask) | pdr; - port->SLR = (port->SLR & ~bit_mask) | slr; - port->DEN = (port->DEN & ~bit_mask) | den; - port->AMSEL = (port->AMSEL & ~bit_mask) | amsel; - port->PCTL = (port->PCTL & ~pctl_mask) | pctl; - } - - mask >>= 1; - if (!mask) { - return; - } - - dir <<= 1; - afsel <<= 1; - dr2r <<= 1; - dr4r <<= 1; - dr8r <<= 1; - odr <<= 1; - pur <<= 1; - pdr <<= 1; - slr <<= 1; - den <<= 1; - amsel <<= 1; - pctl <<= 4; - - bit++; - } -} - -#endif /* HAL_USE_PAL */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_pal_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_pal_lld.h deleted file mode 100644 index c0cd82b..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_pal_lld.h +++ /dev/null @@ -1,762 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/pal_lld.h - * @brief TM4C123x/TM4C129x PAL subsystem low level driver header. - * - * @addtogroup PAL - * @{ - */ - -#ifndef HAL_PAL_LLD_H -#define HAL_PAL_LLD_H - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#undef PAL_MODE_RESET -#undef PAL_MODE_UNCONNECTED -#undef PAL_MODE_INPUT -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_INPUT_ANALOG -#undef PAL_MODE_OUTPUT_PUSHPULL -#undef PAL_MODE_OUTPUT_OPENDRAIN - -/** - * @name TIVA-specific I/O mode flags - * @{ - */ -#define PAL_TIVA_DIR_MASK (1 << 0) -#define PAL_TIVA_DIR_INPUT (0 << 0) -#define PAL_TIVA_DIR_OUTPUT (1 << 0) - -#define PAL_TIVA_AFSEL_MASK (1 << 1) -#define PAL_TIVA_AFSEL_GPIO (0 << 1) -#define PAL_TIVA_AFSEL_ALTERNATE (1 << 1) - -#define PAL_TIVA_DR2R_MASK (1 << 2) -#define PAL_TIVA_DR2R_DISABLE (0 << 2) -#define PAL_TIVA_DR2R_ENABLE (1 << 2) - -#define PAL_TIVA_DR4R_MASK (1 << 3) -#define PAL_TIVA_DR4R_DISABLE (0 << 3) -#define PAL_TIVA_DR4R_ENABLE (1 << 3) - -#define PAL_TIVA_DR8R_MASK (1 << 4) -#define PAL_TIVA_DR8R_DISABLE (0 << 4) -#define PAL_TIVA_DR8R_ENABLE (1 << 4) - -#define PAL_TIVA_ODR_MASK (1 << 5) -#define PAL_TIVA_ODR_PUSHPULL (0 << 5) -#define PAL_TIVA_ODR_OPENDRAIN (1 << 5) - -#define PAL_TIVA_PUR_MASK (1 << 6) -#define PAL_TIVA_PUR_DISABLE (0 << 6) -#define PAL_TIVA_PUR_ENABLE (1 << 6) - -#define PAL_TIVA_PDR_MASK (1 << 7) -#define PAL_TIVA_PDR_DISABLE (0 << 7) -#define PAL_TIVA_PDR_ENABLE (1 << 7) - -#define PAL_TIVA_SLR_MASK (1 << 8) -#define PAL_TIVA_SLR_DISABLE (0 << 8) -#define PAL_TIVA_SLR_ENABLE (1 << 8) - -#define PAL_TIVA_DEN_MASK (1 << 9) -#define PAL_TIVA_DEN_DISABLE (0 << 9) -#define PAL_TIVA_DEN_ENABLE (1 << 9) - -#define PAL_TIVA_AMSEL_MASK (1 << 10) -#define PAL_TIVA_AMSEL_DISABLE (0 << 10) -#define PAL_TIVA_AMSEL_ENABLE (1 << 10) - -#define PAL_TIVA_PCTL_MASK (7 << 11) -#define PAL_TIVA_PCTL(n) ((n) << 11) - -/** - * @brief Alternate function. - * - * @param[in] n alternate function selector - */ -#define PAL_MODE_ALTERNATE(n) (PAL_TIVA_AFSEL_ALTERNATE | \ - PAL_TIVA_PCTL(n)) -/** - * @} - */ - -/** - * @name Standard I/O mode flags - * @{ - */ -/** - * @brief This mode is implemented as input. - */ -#define PAL_MODE_RESET PAL_MODE_INPUT - -/** - * @brief This mode is implemented as input with pull-up. - */ -#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP - -/** - * @brief Regular input high-Z pad. - */ -#define PAL_MODE_INPUT (PAL_TIVA_DEN_ENABLE | \ - PAL_TIVA_DIR_INPUT) - -/** - * @brief Input pad with weak pull up resistor. - */ -#define PAL_MODE_INPUT_PULLUP (PAL_TIVA_DIR_INPUT | \ - PAL_TIVA_PUR_ENABLE | \ - PAL_TIVA_DEN_ENABLE) - -/** - * @brief Input pad with weak pull down resistor. - */ -#define PAL_MODE_INPUT_PULLDOWN (PAL_TIVA_DIR_INPUT | \ - PAL_TIVA_PDR_ENABLE | \ - PAL_TIVA_DEN_ENABLE) - -/** - * @brief Analog input mode. - */ -#define PAL_MODE_INPUT_ANALOG (PAL_TIVA_DEN_DISABLE | \ - PAL_TIVA_AMSEL_ENABLE) - -/** - * @brief Push-pull output pad. - */ -#define PAL_MODE_OUTPUT_PUSHPULL (PAL_TIVA_DIR_OUTPUT | \ - PAL_TIVA_DR2R_ENABLE | \ - PAL_TIVA_ODR_PUSHPULL | \ - PAL_TIVA_DEN_ENABLE) - -/** - * @brief Open-drain output pad. - */ -#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_TIVA_DIR_OUTPUT | \ - PAL_TIVA_DR2R_ENABLE | \ - PAL_TIVA_ODR_OPENDRAIN | \ - PAL_TIVA_DEN_ENABLE) -/** - * @} - */ - -/** @brief GPIOA port identifier.*/ -#define IOPORT1 GPIOA - -/** @brief GPIOB port identifier.*/ -#define IOPORT2 GPIOB - -/** @brief GPIOC port identifier.*/ -#define IOPORT3 GPIOC - -/** @brief GPIOD port identifier.*/ -#define IOPORT4 GPIOD - -/** @brief GPIOE port identifier.*/ -#define IOPORT5 GPIOE - -/** @brief GPIOF port identifier.*/ -#define IOPORT6 GPIOF - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) -/** @brief Port G setup data.*/ -#define IOPORT7 GPIOG -#endif /* TIVA_HAS_GPIOG.*/ - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) -/** @brief Port H setup data.*/ -#define IOPORT8 GPIOH -#endif /* TIVA_HAS_GPIOH.*/ - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) -/** @brief Port J setup data.*/ -#define IOPORT9 GPIOJ -#endif /* TIVA_HAS_GPIOJ.*/ - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) -/** @brief Port K setup data.*/ -#define IOPORT10 GPIOK -#endif /* TIVA_HAS_GPIOK.*/ - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) -/** @brief Port L setup data.*/ -#define IOPORT11 GPIOL -#endif /* TIVA_HAS_GPIOL.*/ - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) -/** @brief Port M setup data.*/ -#define IOPORT12 GPIOM -#endif /* TIVA_HAS_GPIOM.*/ - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) -/** @brief Port N setup data.*/ -#define IOPORT13 GPION -#endif /* TIVA_HAS_GPION.*/ - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) -/** @brief Port P setup data.*/ -#define IOPORT14 GPIOP -#endif /* TIVA_HAS_GPIOP.*/ - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) -/** @brief Port Q setup data.*/ -#define IOPORT15 GPIOQ -#endif /* TIVA_HAS_GPIOQ.*/ - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) -/** @brief Port R setup data.*/ -#define IOPORT16 GPIOR -#endif /* TIVA_HAS_GPIOR.*/ - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) -/** @brief Port S setup data.*/ -#define IOPORT17 GPIOS -#endif /* TIVA_HAS_GPIOS.*/ - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) -/** @brief Port T setup data.*/ -#define IOPORT18 GPIOT -#endif /* TIVA_HAS_GPIOT.*/ - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 8 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -#if defined(TM4C123x) - -/** - * @brief GPIOA AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOA. When set - * to @p FALSE the APB bus is used to access GPIOA. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOA_USE_AHB TRUE -#endif - -/** - * @brief GPIOB AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOB. When set - * to @p FALSE the APB bus is used to access GPIOB. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOB_USE_AHB TRUE -#endif - -/** - * @brief GPIOC AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOC. When set - * to @p FALSE the APB bus is used to access GPIOC. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOC_USE_AHB TRUE -#endif - -/** - * @brief GPIOD AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOD. When set - * to @p FALSE the APB bus is used to access GPIOD. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOD_USE_AHB TRUE -#endif - -/** - * @brief GPIOE AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOE. When set - * to @p FALSE the APB bus is used to access GPIOE. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOE_USE_AHB TRUE -#endif - -/** - * @brief GPIOF AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOF. When set - * to @p FALSE the APB bus is used to access GPIOF. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOF_USE_AHB TRUE -#endif - -/** - * @brief GPIOG AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOG. When set - * to @p FALSE the APB bus is used to access GPIOG. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOG_USE_AHB TRUE -#endif - -/** - * @brief GPIOH AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOH. When set - * to @p FALSE the APB bus is used to access GPIOH. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOH_USE_AHB TRUE -#endif - -/** - * @brief GPIOJ AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set - * to @p FALSE the APB bus is used to access GPIOJ. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOJ_USE_AHB TRUE -#endif - -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if defined(TM4C123x) - -#if TIVA_GPIO_GPIOA_USE_AHB -#define GPIOA GPIOA_AHB -#else -#define GPIOA GPIOA_APB -#endif - -#if TIVA_GPIO_GPIOB_USE_AHB -#define GPIOB GPIOB_AHB -#else -#define GPIOB GPIOB_APB -#endif - -#if TIVA_GPIO_GPIOC_USE_AHB -#define GPIOC GPIOC_AHB -#else -#define GPIOC GPIOC_APB -#endif - -#if TIVA_GPIO_GPIOD_USE_AHB -#define GPIOD GPIOD_AHB -#else -#define GPIOD GPIOD_APB -#endif - -#if TIVA_GPIO_GPIOE_USE_AHB -#define GPIOE GPIOE_AHB -#else -#define GPIOE GPIOE_APB -#endif - -#if TIVA_GPIO_GPIOF_USE_AHB -#define GPIOF GPIOF_AHB -#else -#define GPIOF GPIOF_APB -#endif - -#if TIVA_GPIO_GPIOG_USE_AHB -#define GPIOG GPIOG_AHB -#else -#define GPIOG GPIOG_APB -#endif - -#if TIVA_GPIO_GPIOH_USE_AHB -#define GPIOH GPIOH_AHB -#else -#define GPIOH GPIOH_APB -#endif - -#if TIVA_GPIO_GPIOJ_USE_AHB -#define GPIOJ GPIOJ_AHB -#else -#define GPIOJ GPIOJ_APB -#endif - -#define GPIOK GPIOK_AHB -#define GPIOL GPIOL_AHB -#define GPIOM GPIOM_AHB -#define GPION GPION_AHB -#define GPIOP GPIOP_AHB -#define GPIOQ GPIOQ_AHB - -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief GPIO port setup info. - */ -typedef struct -{ - /** @brief Initial value for DATA register.*/ - uint32_t data; - /** @brief Initial value for DIR register.*/ - uint32_t dir; - /** @brief Initial value for AFSEL register.*/ - uint32_t afsel; - /** @brief Initial value for DR2R register.*/ - uint32_t dr2r; - /** @brief Initial value for DR4R register.*/ - uint32_t dr4r; - /** @brief Initial value for DR8R register.*/ - uint32_t dr8r; - /** @brief Initial value for ODR register.*/ - uint32_t odr; - /** @brief Initial value for PUR register.*/ - uint32_t pur; - /** @brief Initial value for PDR register.*/ - uint32_t pdr; - /** @brief Initial value for SLR register.*/ - uint32_t slr; - /** @brief Initial value for DEN register.*/ - uint32_t den; - /** @brief Initial value for AMSEL register.*/ - uint32_t amsel; - /** @brief Initial value for PCTL register.*/ - uint32_t pctl; -} tiva_gpio_setup_t; - -/** - * @brief Tiva GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct -{ - /** @brief Port A setup data.*/ - tiva_gpio_setup_t PAData; - /** @brief Port B setup data.*/ - tiva_gpio_setup_t PBData; - /** @brief Port C setup data.*/ - tiva_gpio_setup_t PCData; - /** @brief Port D setup data.*/ - tiva_gpio_setup_t PDData; - /** @brief Port E setup data.*/ - tiva_gpio_setup_t PEData; - /** @brief Port F setup data.*/ - tiva_gpio_setup_t PFData; - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) - /** @brief Port G setup data.*/ - tiva_gpio_setup_t PGData; -#endif /* TIVA_HAS_GPIOG.*/ - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) - /** @brief Port H setup data.*/ - tiva_gpio_setup_t PHData; -#endif /* TIVA_HAS_GPIOH.*/ - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) - /** @brief Port J setup data.*/ - tiva_gpio_setup_t PJData; -#endif /* TIVA_HAS_GPIOJ.*/ - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) - /** @brief Port K setup data.*/ - tiva_gpio_setup_t PKData; -#endif /* TIVA_HAS_GPIOK.*/ - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) - /** @brief Port L setup data.*/ - tiva_gpio_setup_t PLData; -#endif /* TIVA_HAS_GPIOL.*/ - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) - /** @brief Port M setup data.*/ - tiva_gpio_setup_t PMData; -#endif /* TIVA_HAS_GPIOM.*/ - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) - /** @brief Port N setup data.*/ - tiva_gpio_setup_t PNData; -#endif /* TIVA_HAS_GPION.*/ - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) - /** @brief Port P setup data.*/ - tiva_gpio_setup_t PPData; -#endif /* TIVA_HAS_GPIOP.*/ - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) - /** @brief Port Q setup data.*/ - tiva_gpio_setup_t PQData; -#endif /* TIVA_HAS_GPIOQ.*/ - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) - /** @brief Port R setup data.*/ - tiva_gpio_setup_t PRData; -#endif /* TIVA_HAS_GPIOR.*/ - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) - /** @brief Port S setup data.*/ - tiva_gpio_setup_t PSData; -#endif /* TIVA_HAS_GPIOS.*/ - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) - /** @brief Port T setup data.*/ - tiva_gpio_setup_t PTData; -#endif /* TIVA_HAS_GPIOT.*/ -} PALConfig; - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Port Identifier. - */ -typedef GPIO_TypeDef *ioportid_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - * - * @notapi - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->DATA) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) ((port)->DATA) - -/** - * @brief Writes a bits mask on a I/O port. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->DATA = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @notapi - */ -#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFF) - -/** - * @brief Clears a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @notapi - */ -#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0) - -/** - * @brief Reads a group of bits. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @return The group logical states. - * - * @notapi - */ -#define pal_lld_readgroup(port, mask, offset) \ - ((port)->MASKED_ACCESS[(mask) << (offset)]) - -/** - * @brief Writes a group of bits. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group width - * are masked. - * - * @notapi - */ -#define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits)) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -/** - * @brief Reads a logical state from an I/O pad. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @return The logical state. - * @retval PAL_LOW low logical state. - * @retval PAL_HIGH high logical state. - * - * @notapi - */ -#define pal_lld_readpad(port, pad) ((port)->MASKED_ACCESS[1 << (pad)]) - -/** - * @brief Writes a logical state on an output pad. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @notapi - */ -#define pal_lld_writepad(port, pad, bit) \ - ((port)->MASKED_ACCESS[1 << (pad)] = (bit)) - -/** - * @brief Sets a pad logical state to @p PAL_HIGH. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_setpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad)) - -/** - * @brief Clears a pad logical state to @p PAL_LOW. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_clearpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 0) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern const PALConfig pal_default_config; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* HAL_PAL_LLD_H */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_pwm_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_pwm_lld.c deleted file mode 100644 index b223a9c..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_pwm_lld.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/pwm_lld.c - * @brief TM4C123x/TM4C129x PWM subsystem low level driver. - * - * @addtogroup PWM - * @{ - */ - -#include "hal.h" - -#if HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define PWM_INT_CMPBD (1 << 5) -#define PWM_INT_CMPBU (1 << 4) -#define PWM_INT_CMPAD (1 << 3) -#define PWM_INT_CMPAU (1 << 2) -#define PWM_INT_CNTLOAD (1 << 1) -#define PWM_INT_CNTZERO (1 << 0) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief PWMD1 driver identifier. - */ -#if TIVA_PWM_USE_PWM0 || defined(__DOXYGEN__) -PWMDriver PWMD1; -#endif - -/** - * @brief PWMD2 driver identifier. - */ -#if TIVA_PWM_USE_PWM1 || defined(__DOXYGEN__) -PWMDriver PWMD2; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Common PWM Generator IRQ handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] i pwm generator number - */ -static void pwm_lld_serve_generator_interrupt (PWMDriver *pwmp, uint8_t i) -{ - uint32_t isc; - - isc = pwmp->pwm->PWM[i].ISC; - pwmp->pwm->PWM[i].ISC = isc; - - if (((isc & PWM_INT_CMPAD) != 0) && - (pwmp->config->channels[i * 2 + 0].callback != NULL)) { - pwmp->config->channels[i * 2 + 0].callback(pwmp); - } - - if (((isc & PWM_INT_CMPAU) != 0) && - (pwmp->config->channels[i * 2 + 0].callback != NULL)) { - pwmp->config->channels[i * 2 + 0].callback(pwmp); - } - - if (((isc & PWM_INT_CMPBD) != 0) && - (pwmp->config->channels[i * 2 + 1].callback != NULL)) { - pwmp->config->channels[i * 2 + 1].callback(pwmp); - } - - if (((isc & PWM_INT_CMPBU) != 0) && - (pwmp->config->channels[i * 2 + 1].callback != NULL)) { - pwmp->config->channels[i * 2 + 1].callback(pwmp); - } - - if (((isc & PWM_INT_CNTLOAD) != 0) && (pwmp->config->callback != NULL)) { - pwmp->config->callback(pwmp); - } - - if (((isc & PWM_INT_CNTZERO) != 0) && (pwmp->config->callback != NULL)) { - pwmp->config->callback(pwmp); - } -} - -/** - * @brief Common PWM fault IRQ handler. - * - * @param[in] pwmp pointer to a @p PWMDriver object - */ -static void pwm_lld_serve_fault_interrupt (PWMDriver *pwmp) -{ - (void) pwmp; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_PWM_USE_PWM0 -#if !defined(TIVA_PWM0FAULT_HANDLER) -#error "TIVA_PWM0FAULT_HANDLER not defined" -#endif -/* - * @brief PWM0 Fault handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM0FAULT_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_fault_interrupt(&PWMD1); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM0GEN0_HANDLER) -#error "TIVA_PWM0GEN0_HANDLER not defined" -#endif -/* - * @brief PWM0 Generator 0 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM0GEN0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD1, 0); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM0GEN1_HANDLER) -#error "TIVA_PWM0GEN1_HANDLER not defined" -#endif -/* - * @brief PWM0 Generator 1 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM0GEN1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD1, 1); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM0GEN2_HANDLER) -#error "TIVA_PWM0GEN2_HANDLER not defined" -#endif -/* - * @brief PWM0 Generator 2 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM0GEN2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD1, 2); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM0GEN3_HANDLER) -#error "TIVA_PWM0GEN3_HANDLER not defined" -#endif -/* - * @brief PWM0 Generator 3 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM0GEN3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD1, 3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_PWM_USE_PWM1 -#if !defined(TIVA_PWM1FAULT_HANDLER) -#error "TIVA_PWM1FAULT_HANDLER not defined" -#endif -/* - * @brief PWM1 Fault handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM1FAULT_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_fault_interrupt(&PWMD2); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM1GEN0_HANDLER) -#error "TIVA_PWM1GEN0_HANDLER not defined" -#endif -/* - * @brief PWM1 Generator 0 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM1GEN0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD2, 0); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM1GEN1_HANDLER) -#error "TIVA_PWM1GEN1_HANDLER not defined" -#endif -/* - * @brief PWM1 Generator 1 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM1GEN1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD2, 1); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM1GEN2_HANDLER) -#error "TIVA_PWM1GEN2_HANDLER not defined" -#endif -/* - * @brief PWM1 Generator 2 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM1GEN2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD2, 2); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM1GEN3_HANDLER) -#error "TIVA_PWM1GEN3_HANDLER not defined" -#endif -/* - * @brief PWM1 Generator 3 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM1GEN3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD2, 3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level PWM driver initialization. - * - * @notapi - */ -void pwm_lld_init(void) -{ - /* Driver initialization.*/ -#if TIVA_PWM_USE_PWM0 - pwmObjectInit(&PWMD1); - PWMD1.channels = PWM_CHANNELS; - PWMD1.pwm = PWM0; -#endif - -#if TIVA_PWM_USE_PWM1 - pwmObjectInit(&PWMD2); - PWMD2.channels = PWM_CHANNELS; - PWMD2.pwm = PWM1; -#endif -} - -/** - * @brief Configures and activates the PWM peripheral. - * @note Starting a driver that is already in the @p PWM_READY state - * disables all the active channels. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_start(PWMDriver *pwmp) -{ - uint8_t i; - uint32_t invert = 0; - uint32_t enable = 0; - - if (pwmp->state == PWM_STOP) { - /* Clock activation.*/ -#if TIVA_PWM_USE_PWM0 - if (&PWMD1 == pwmp) { - SYSCTL->RCGCPWM |= (1 << 0); - nvicEnableVector(TIVA_PWM0FAULT_NUMBER, - TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM0GEN0_NUMBER, TIVA_PWM_PWM0_0_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM0GEN1_NUMBER, TIVA_PWM_PWM0_1_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM0GEN2_NUMBER, TIVA_PWM_PWM0_2_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM0GEN3_NUMBER, TIVA_PWM_PWM0_3_IRQ_PRIORITY); - } -#endif - -#if TIVA_PWM_USE_PWM1 - if (&PWMD2 == pwmp) { - SYSCTL->RCGCPWM |= (1 << 1); - nvicEnableVector(TIVA_PWM1FAULT_NUMBER, - TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM1GEN0_NUMBER, TIVA_PWM_PWM1_0_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM1GEN1_NUMBER, TIVA_PWM_PWM1_1_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM1GEN2_NUMBER, TIVA_PWM_PWM1_2_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM1GEN3_NUMBER, TIVA_PWM_PWM1_3_IRQ_PRIORITY); - } -#endif - } - else { - /* Driver re-configuration scenario, it must be stopped first.*/ - pwmp->pwm->PWM[0].CTL = 0; - pwmp->pwm->PWM[1].CTL = 0; - pwmp->pwm->PWM[2].CTL = 0; - pwmp->pwm->PWM[3].CTL = 0; - } - - /* Timer configuration.*/ - for (i = 0; i < (PWM_CHANNELS >> 1); i++) { - pwmp->pwm->PWM[i].CTL = 0; - pwmp->pwm->PWM[i].GEN[0] = 0x08C; - pwmp->pwm->PWM[i].GEN[1] = 0x80C; - pwmp->pwm->PWM[i].LOAD = (uint16_t)(pwmp->config->frequency - 1); - pwmp->pwm->PWM[i].CMP[0] = (uint16_t)(pwmp->period - 1); - pwmp->pwm->PWM[i].CMP[1] = (uint16_t)(pwmp->period - 1); - } - - /* Output enables and polarities setup.*/ - for (i = 0; i < PWM_CHANNELS; i++) { - switch (pwmp->config->channels[i].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_DISABLED: - enable &= ~(1 << i); - break; - case PWM_OUTPUT_ACTIVE_LOW: - invert |= (1 << i); - enable |= (1 << i); - break; - case PWM_OUTPUT_ACTIVE_HIGH: - invert &= ~(1 << i); - enable |= (1 << i); - break; - default: - ; - } - } - - pwmp->pwm->INVERT = invert; - pwmp->pwm->ENABLE = enable; - pwmp->pwm->ISC = 0xFFFFFFFF; -} - -/** - * @brief Deactivates the PWM peripheral. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_stop(PWMDriver *pwmp) -{ - /* If in ready state then disables the PWM clock.*/ - if (pwmp->state == PWM_READY) { - pwmp->pwm->PWM[0].CTL = 0; - pwmp->pwm->PWM[1].CTL = 0; - pwmp->pwm->PWM[2].CTL = 0; - pwmp->pwm->PWM[3].CTL = 0; - -#if TIVA_PWM_USE_PWM0 - if (&PWMD1 == pwmp) { - nvicDisableVector(TIVA_PWM0FAULT_NUMBER); - nvicDisableVector(TIVA_PWM0GEN0_NUMBER); - nvicDisableVector(TIVA_PWM0GEN1_NUMBER); - nvicDisableVector(TIVA_PWM0GEN2_NUMBER); - nvicDisableVector(TIVA_PWM0GEN3_NUMBER); - SYSCTL->RCGCPWM &= ~(1 << 0); - } -#endif - -#if TIVA_PWM_USE_PWM1 - if (&PWMD2 == pwmp) { - nvicDisableVector(TIVA_PWM1FAULT_NUMBER); - nvicDisableVector(TIVA_PWM1GEN0_NUMBER); - nvicDisableVector(TIVA_PWM1GEN1_NUMBER); - nvicDisableVector(TIVA_PWM1GEN2_NUMBER); - nvicDisableVector(TIVA_PWM1GEN3_NUMBER); - SYSCTL->RCGCPWM &= ~(1 << 1); - } -#endif - } -} - -/** - * @brief Enables a PWM channel. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is active using the specified configuration. - * @note The function has effect at the next cycle start. - * @note Channel notification is not enabled. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * @param[in] width PWM pulse width as clock pulses number - * - * @notapi - */ -void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width) -{ - /* Changing channel duty cycle on the fly.*/ - pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = width; - pwmp->pwm->PWM[channel >> 1].CTL |= (1 << 0); -} - -/** - * @brief Disables a PWM channel and its notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is disabled and its output line returned to the - * idle state. - * @note The function has effect at the next cycle start. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @notapi - */ -void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) -{ - pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = 0; - pwmp->pwm->PWM[channel >> 1].CTL &= ~(1 << 0); -} - -/** - * @brief Enables the periodic activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) -{ - uint32_t inten; - uint8_t i; - - /* If the IRQ is not already enabled care must be taken to clear it, - it is probably already pending because the timer is running.*/ - for(i = 0; i < (PWM_CHANNELS >> 1); i++) { - inten = pwmp->pwm->PWM[i].INTEN; - if ((inten & 0x03) == 0) { - pwmp->pwm->PWM[i].INTEN |= 0x03; - pwmp->pwm->PWM[i].ISC = 0x03; - } - } - - pwmp->pwm->INTEN = 0x3f; -} - -/** - * @brief Disables the periodic activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) -{ - pwmp->pwm->PWM[0].INTEN &= ~(0x03); - pwmp->pwm->PWM[1].INTEN &= ~(0x03); - pwmp->pwm->PWM[2].INTEN &= ~(0x03); - pwmp->pwm->PWM[3].INTEN &= ~(0x03); - pwmp->pwm->INTEN &= ~(0x3F); -} - -/** - * @brief Enables a channel de-activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @pre The channel must have been activated using @p pwmEnableChannel(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @notapi - */ -void pwm_lld_enable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel) -{ - uint32_t inten = pwmp->pwm->PWM[channel >> 1].INTEN; - - /* If the IRQ is not already enabled care must be taken to clear it, - it is probably already pending because the timer is running.*/ - if ((inten & (0x03 << (((channel & 1) * 2) + 2))) == 0) { - pwmp->pwm->PWM[channel >> 1].INTEN |= (0x03 << (((channel & 1) * 2) + 2)); - pwmp->pwm->PWM[channel >> 1].ISC = (0x03 << (((channel & 1) * 2) + 2)); - } -} - -/** - * @brief Disables a channel de-activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @pre The channel must have been activated using @p pwmEnableChannel(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @notapi - */ -void pwm_lld_disable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel) -{ - pwmp->pwm->PWM[channel >> 1].INTEN &= ~(0x03 << (((channel & 1) * 2) + 2)); -} - -#endif /* HAL_USE_PWM */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_pwm_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_pwm_lld.h deleted file mode 100644 index ac64fe1..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_pwm_lld.h +++ /dev/null @@ -1,372 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/pwm_lld.c - * @brief TM4C123x/TM4C129x PWM subsystem low level driver header. - * - * @addtogroup PWM - * @{ - */ - -#ifndef HAL_PWM_LLD_H -#define HAL_PWM_LLD_H - -#if HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Number of PWM channels per PWM driver. - */ -#define PWM_CHANNELS 8 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief PWMD1 driver enable switch. - * @details If set to @p TRUE the support for PWMD1 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_PWM_USE_PWM0) || defined(__DOXYGEN__) -#define TIVA_PWM_USE_PWM0 FALSE -#endif - -/** - * @brief PWMD2 driver enable switch. - * @details If set to @p TRUE the support for PWMD2 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_PWM_USE_PWM1) || defined(__DOXYGEN__) -#define TIVA_PWM_USE_PWM1 FALSE -#endif - -/** - * @brief PWMD1 fault interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY) || defined (__DOXYGEN__) -#define TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY -#endif - -/** - * @brief PWMD1 channel 0 & 1 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM0_0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM0_0_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD1 channel 2 & 3 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM0_1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM0_1_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD1 channel 4 & 5 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM0_2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM0_2_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD1 channel 6 & 7 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM0_3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM0_3_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD2 fault interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY) || defined (__DOXYGEN__) -#define TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY -#endif - -/** - * @brief PWMD2 channel 0 & 1 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM1_0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM1_0_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD2 channel 2 & 3 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM1_1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM1_1_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD2 channel 4 & 5 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM1_2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM1_2_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD2 channel 6 & 7 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM1_3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM1_3_IRQ_PRIORITY 4 -#endif - -/** - * @} - */ - -/*===========================================================================*/ -/* Configuration checks. */ -/*===========================================================================*/ - -#if TIVA_PWM_USE_PWM0 && !TIVA_HAS_PWM0 -#error "PWM0 not present in the selected device" -#endif - -#if TIVA_PWM_USE_PWM1 && !TIVA_HAS_PWM1 -#error "PWM1 not present in the selected device" -#endif - -#if !TIVA_PWM_USE_PWM0 && !TIVA_PWM_USE_PWM1 -#error "PWM driver activated but no PWM peripheral assigned" -#endif - -#if TIVA_PWM_USE_PWM0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM0 FAULT" -#endif - -#if TIVA_PWM_USE_PWM0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM0 GEN0" -#endif - -#if TIVA_PWM_USE_PWM0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM0 GEN1" -#endif - -#if TIVA_PWM_USE_PWM0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM0 GEN2" -#endif - -#if TIVA_PWM_USE_PWM0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM0 GEN3" -#endif - -#if TIVA_PWM_USE_PWM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM1 FAULT" -#endif - -#if TIVA_PWM_USE_PWM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM1 GEN0" -#endif - -#if TIVA_PWM_USE_PWM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM1 GEN1" -#endif - -#if TIVA_PWM_USE_PWM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM1 GEN2" -#endif - -#if TIVA_PWM_USE_PWM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM1 GEN3" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a PWM mode. - */ -typedef uint32_t pwmmode_t; - -/** - * @brief Type of a PWM channel. - */ -typedef uint8_t pwmchannel_t; - -/** - * @brief Type of a channels mask. - */ -typedef uint32_t pwmchnmsk_t; - -/** - * @brief Type of a PWM counter. - */ -typedef uint16_t pwmcnt_t; - -/** - * @brief Type of a PWM driver channel configuration structure. - */ -typedef struct { - /** - * @brief Channel active logic level. - */ - pwmmode_t mode; - /** - * @brief Channel callback pointer. - * @note This callback is invoked on the channel compare event. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t callback; - /* End of the mandatory fields.*/ -} PWMChannelConfig; - -/** - * @brief Type of a PWM driver configuration structure. - */ -typedef struct { - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - uint32_t frequency; - /** - * @brief PWM period in ticks. - * @note The low level can use assertions in order to catch invalid - * period specifications. - */ - pwmcnt_t period; - /** - * @brief Periodic callback pointer. - * @note This callback is invoked on PWM counter reset. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t callback; - /** - * @brief Channels configurations. - */ - PWMChannelConfig channels[PWM_CHANNELS]; - /* End of the mandatory fields.*/ -} PWMConfig; - -/** - * @brief Structure representing a PWM driver. - */ -struct PWMDriver { - /** - * @brief Driver state. - */ - pwmstate_t state; - /** - * @brief Current driver configuration data. - */ - const PWMConfig *config; - /** - * @brief Current PWM period in ticks. - */ - pwmcnt_t period; - /** - * @brief Mask of the enabled channels. - */ - pwmchnmsk_t enabled; - /** - * @brief Number of channels in this instance. - */ - pwmchannel_t channels; -#if defined(PWM_DRIVER_EXT_FIELDS) - PWM_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the PWMx registers block. - */ - PWM_TypeDef *pwm; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the period the PWM peripheral. - * @details This function changes the period of a PWM unit that has already - * been activated using @p pwmStart(). - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The PWM unit period is changed to the new value. - * @note The function has effect at the next cycle start. - * @note If a period is specified that is shorter than the pulse width - * programmed in one of the channels then the behavior is not - * guaranteed. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] period new cycle time in ticks - * - * @notapi - */ -#define pwm_lld_change_period(pwmp, period) \ - ((pwmp)->pwm->PWM[0].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[1].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[2].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[3].LOAD = (uint16_t)((period) - 1)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if TIVA_PWM_USE_PWM0 && !defined(__DOXYGEN__) -extern PWMDriver PWMD1; -#endif - -#if TIVA_PWM_USE_PWM1 && !defined(__DOXYGEN__) -extern PWMDriver PWMD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void pwm_lld_init(void); - void pwm_lld_start(PWMDriver *pwmp); - void pwm_lld_stop(PWMDriver *pwmp); - void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width); - void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); - void pwm_lld_enable_periodic_notification(PWMDriver *pwmp); - void pwm_lld_disable_periodic_notification(PWMDriver *pwmp); - void pwm_lld_enable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel); - void pwm_lld_disable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PWM */ - -#endif /* HAL_PWM_LLD_H */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_serial_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_serial_lld.c deleted file mode 100644 index bd1b81e..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_serial_lld.c +++ /dev/null @@ -1,632 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/serial_lld.c - * @brief Tiva low level serial driver code. - * - * @addtogroup SERIAL - * @{ - */ - -#include "hal.h" - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief UART0 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif - -/** - * @brief UART1 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/** - * @brief UART2 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) -SerialDriver SD3; -#endif - -/** - * @brief UART3 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) -SerialDriver SD4; -#endif - -/** - * @brief UART4 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) -SerialDriver SD5; -#endif - -/** - * @brief UART5 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) -SerialDriver SD6; -#endif - -/** - * @brief UART6 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) -SerialDriver SD7; -#endif - -/** - * @brief UART7 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) -SerialDriver SD8; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** - * @brief Driver default configuration. - */ -static const SerialConfig sd_default_config = -{ - SERIAL_DEFAULT_BITRATE, - TIVA_LCRH_FEN | TIVA_LCRH_WLEN_8, - TIVA_IFLS_TXIFLSEL_1_8_F | TIVA_IFLS_RXIFLSEL_1_8_E -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief UART initialization. - * - * @param[in] sdp communication channel associated to the UART - * @param[in] config the architecture-dependent serial driver configuration - */ -static void uart_init(SerialDriver *sdp, const SerialConfig *config) -{ - UART_TypeDef *u = sdp->uart; - uint32_t div; /* baud rate divisor */ - - /* disable the UART before any of the control registers are reprogrammed */ - u->CTL &= ~TIVA_CTL_UARTEN; - div = (((TIVA_SYSCLK * 8) / config->sc_speed) + 1) / 2; - u->IBRD = div / 64; /* integer portion of the baud rate divisor */ - u->FBRD = div % 64; /* fractional portion of the baud rate divisor */ - u->LCRH = config->sc_lcrh; /* set data format */ - u->IFLS = config->sc_ifls; - u->CTL |= TIVA_CTL_TXE | TIVA_CTL_RXE | TIVA_CTL_UARTEN; - u->IM |= TIVA_IM_RXIM | TIVA_IM_TXIM | TIVA_IM_RTIM; /* interrupts enable */ -} - -/** - * @brief UART de-initialization. - * - * @param[in] u pointer to an UART I/O block - */ -static void uart_deinit(UART_TypeDef *u) -{ - u->CTL &= ~TIVA_CTL_UARTEN; -} - -/** - * @brief Error handling routine. - * - * @param[in] sdp communication channel associated to the UART - * @param[in] err UART LSR register value - */ -static void set_error(SerialDriver *sdp, uint16_t err) -{ - eventflags_t sts = 0; - - if (err & TIVA_MIS_FEMIS) - sts |= SD_FRAMING_ERROR; - if (err & TIVA_MIS_PEMIS) - sts |= SD_PARITY_ERROR; - if (err & TIVA_MIS_BEMIS) - sts |= SD_BREAK_DETECTED; - if (err & TIVA_MIS_OEMIS) - sts |= SD_OVERRUN_ERROR; - osalSysLockFromISR(); - chnAddFlagsI(sdp, sts); - osalSysUnlockFromISR(); -} - -/** - * @brief Common IRQ handler. - * @note Tries hard to clear all the pending interrupt sources, we don't - * want to go through the whole ISR and have another interrupt soon - * after. - * - * @param[in] u pointer to an UART I/O block - * @param[in] sdp communication channel associated to the UART - */ -static void serial_serve_interrupt(SerialDriver *sdp) -{ - UART_TypeDef *u = sdp->uart; - uint16_t mis = u->MIS; - - u->ICR = mis; /* clear interrupts */ - - if (mis & (TIVA_MIS_FEMIS | TIVA_MIS_PEMIS | TIVA_MIS_BEMIS | TIVA_MIS_OEMIS)) { - set_error(sdp, mis); - } - - if ((mis & TIVA_MIS_RXMIS) || (mis & TIVA_MIS_RTMIS)) { - osalSysLockFromISR(); - if (iqIsEmptyI(&sdp->iqueue)) { - chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); - } - osalSysUnlockFromISR(); - while ((u->FR & TIVA_FR_RXFE) == 0) { - osalSysLockFromISR(); - if (iqPutI(&sdp->iqueue, u->DR) < Q_OK) { - chnAddFlagsI(sdp, SD_OVERRUN_ERROR); - } - osalSysUnlockFromISR(); - } - } - - if (mis & TIVA_MIS_TXMIS) { - while ((u->FR & TIVA_FR_TXFF) == 0) { - msg_t b; - osalSysLockFromISR(); - b = oqGetI(&sdp->oqueue); - osalSysUnlockFromISR(); - if (b < Q_OK) { - u->IM &= ~TIVA_IM_TXIM; - osalSysLockFromISR(); - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - osalSysUnlockFromISR(); - break; - } - u->DR = b; - } - } -} - -/** - * @brief - */ -static void fifo_load(SerialDriver *sdp) -{ - UART_TypeDef *u = sdp->uart; - - while ((u->FR & TIVA_FR_TXFF) == 0) { - msg_t b = oqGetI(&sdp->oqueue); - if (b < Q_OK) { - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - return; - } - u->DR = b; - } - u->IM |= TIVA_IM_TXIM; /* transmit interrupt enable */ -} - -/** - * @brief Driver SD1 output notification. - */ -#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) -static void notify1(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD1); -} -#endif - -/** - * @brief Driver SD2 output notification. - */ -#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) -static void notify2(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD2); -} -#endif - -/** - * @brief Driver SD3 output notification. - */ -#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) -static void notify3(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD3); -} -#endif - -/** - * @brief Driver SD4 output notification. - */ -#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) -static void notify4(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD4); -} -#endif - -/** - * @brief Driver SD5 output notification. - */ -#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) -static void notify5(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD5); -} -#endif - -/** - * @brief Driver SD6 output notification. - */ -#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) -static void notify6(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD6); -} -#endif - -/** - * @brief Driver SD7 output notification. - */ -#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) -static void notify7(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD7); -} -#endif - -/** - * @brief Driver SD8 output notification. - */ -#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) -static void notify8(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD8); -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief UART0 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) -#if !defined(TIVA_UART0_HANDLER) -#error "TIVA_UART0_HANDLER not defined" -#endif -CH_IRQ_HANDLER(TIVA_UART0_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD1); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART1 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART1_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD2); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART2 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART2_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD3); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART3 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART3_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD4); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART4 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART4_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD5); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART5 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART5_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD6); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART6 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART6_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD7); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART7 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART7_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD8); - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) -{ -#if TIVA_SERIAL_USE_UART0 - sdObjectInit(&SD1, NULL, notify1); - SD1.uart = UART0; -#endif - -#if TIVA_SERIAL_USE_UART1 - sdObjectInit(&SD2, NULL, notify2); - SD2.uart = UART1; -#endif - -#if TIVA_SERIAL_USE_UART2 - sdObjectInit(&SD3, NULL, notify3); - SD3.uart = UART2; -#endif - -#if TIVA_SERIAL_USE_UART3 - sdObjectInit(&SD4, NULL, notify4); - SD4.uart = UART3; -#endif - -#if TIVA_SERIAL_USE_UART4 - sdObjectInit(&SD5, NULL, notify5); - SD5.uart = UART4; -#endif - -#if TIVA_SERIAL_USE_UART5 - sdObjectInit(&SD6, NULL, notify6); - SD6.uart = UART5; -#endif - -#if TIVA_SERIAL_USE_UART6 - sdObjectInit(&SD7, NULL, notify7); - SD7.uart = UART6; -#endif - -#if TIVA_SERIAL_USE_UART7 - sdObjectInit(&SD8, NULL, notify8); - SD8.uart = UART7; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) -{ - if (config == NULL) - config = &sd_default_config; - - if (sdp->state == SD_STOP) { -#if TIVA_SERIAL_USE_UART0 - if (&SD1 == sdp) { - SYSCTL->RCGCUART |= (1 << 0); - nvicEnableVector(TIVA_UART0_NUMBER, TIVA_SERIAL_UART0_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART1 - if (&SD2 == sdp) { - SYSCTL->RCGC.UART |= (1 << 1); - nvicEnableVector(TIVA_UART1_NUMBER, TIVA_SERIAL_UART1_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART2 - if (&SD3 == sdp) { - SYSCTL->RCGC.UART |= (1 << 2); /* enable UART2 module */ - nvicEnableVector(TIVA_UART2_NUMBER, TIVA_SERIAL_UART2_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART3 - if (&SD4 == sdp) { - SYSCTL->RCGC.UART |= (1 << 3); /* enable UART3 module */ - nvicEnableVector(TIVA_UART3_NUMBER, TIVA_SERIAL_UART3_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART4 - if (&SD5 == sdp) { - SYSCTL->RCGC.UART |= (1 << 4); /* enable UART4 module */ - nvicEnableVector(TIVA_UART4_NUMBER, TIVA_SERIAL_UART4_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART5 - if (&SD6 == sdp) { - SYSCTL->RCGC.UART |= (1 << 5); /* enable UART5 module */ - nvicEnableVector(TIVA_UART5_NUMBER, TIVA_SERIAL_UART5_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART6 - if (&SD7 == sdp) { - SYSCTL->RCGC.UART |= (1 << 6); /* enable UART6 module */ - nvicEnableVector(TIVA_UART6_NUMBER, TIVA_SERIAL_UART6_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART7 - if (&SD8 == sdp) { - SYSCTL->RCGC.UART |= (1 << 7); /* enable UART7 module */ - nvicEnableVector(TIVA_UART7_NUMBER, TIVA_SERIAL_UART7_PRIORITY); - } -#endif - } - uart_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the UART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) -{ - if (sdp->state == SD_READY) { - uart_deinit(sdp->uart); -#if TIVA_SERIAL_USE_UART0 - if (&SD1 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 0); /* disable UART0 module */ - nvicDisableVector(TIVA_UART0_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART1 - if (&SD2 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 1); /* disable UART1 module */ - nvicDisableVector(TIVA_UART1_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART2 - if (&SD3 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 2); /* disable UART2 module */ - nvicDisableVector(TIVA_UART2_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART3 - if (&SD4 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 3); /* disable UART3 module */ - nvicDisableVector(TIVA_UART3_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART4 - if (&SD5 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 4); /* disable UART4 module */ - nvicDisableVector(TIVA_UART4_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART5 - if (&SD6 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 5); /* disable UART5 module */ - nvicDisableVector(TIVA_UART5_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART6 - if (&SD7 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 6); /* disable UART6 module */ - nvicDisableVector(TIVA_UART6_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART7 - if (&SD8 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 7); /* disable UART7 module */ - nvicDisableVector(TIVA_UART7_NUMBER); - return; - } -#endif - } -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_serial_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_serial_lld.h deleted file mode 100644 index 203ef6a..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_serial_lld.h +++ /dev/null @@ -1,482 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/serial_lld.h - * @brief Tiva low level serial driver header. - * - * @addtogroup SERIAL - * @{ - */ - -#ifndef HAL_SERIAL_LLD_H -#define HAL_SERIAL_LLD_H - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name FR register bits definitions - * @{ - */ - -#define TIVA_FR_CTS (1 << 0) - -#define TIVA_FR_BUSY (1 << 3) - -#define TIVA_FR_RXFE (1 << 4) - -#define TIVA_FR_TXFF (1 << 5) - -#define TIVA_FR_RXFF (1 << 6) - -#define TIVA_FR_TXFE (1 << 7) - -/** - * @} - */ - -/** - * @name LCRH register bits definitions - * @{ - */ - -#define TIVA_LCRH_BRK (1 << 0) - -#define TIVA_LCRH_PEN (1 << 1) - -#define TIVA_LCRH_EPS (1 << 2) - -#define TIVA_LCRH_STP2 (1 << 3) - -#define TIVA_LCRH_FEN (1 << 4) - -#define TIVA_LCRH_WLEN_MASK (3 << 5) -#define TIVA_LCRH_WLEN_5 (0 << 5) -#define TIVA_LCRH_WLEN_6 (1 << 5) -#define TIVA_LCRH_WLEN_7 (2 << 5) -#define TIVA_LCRH_WLEN_8 (3 << 5) - -#define TIVA_LCRH_SPS (1 << 7) - -/** - * @} - */ - -/** - * @name CTL register bits definitions - * @{ - */ - -#define TIVA_CTL_UARTEN (1 << 0) - -#define TIVA_CTL_SIREN (1 << 1) - -#define TIVA_CTL_SIRLP (1 << 2) - -#define TIVA_CTL_SMART (1 << 3) - -#define TIVA_CTL_EOT (1 << 4) - -#define TIVA_CTL_HSE (1 << 5) - -#define TIVA_CTL_LBE (1 << 7) - -#define TIVA_CTL_TXE (1 << 8) - -#define TIVA_CTL_RXE (1 << 9) - -#define TIVA_CTL_RTS (1 << 11) - -#define TIVA_CTL_RTSEN (1 << 14) - -#define TIVA_CTL_CTSEN (1 << 15) - -/** - * @} - */ - -/** - * @name IFLS register bits definitions - * @{ - */ - -#define TIVA_IFLS_TXIFLSEL_MASK (7 << 0) -#define TIVA_IFLS_TXIFLSEL_1_8_F (0 << 0) -#define TIVA_IFLS_TXIFLSEL_1_4_F (1 << 0) -#define TIVA_IFLS_TXIFLSEL_1_2_F (2 << 0) -#define TIVA_IFLS_TXIFLSEL_3_4_F (3 << 0) -#define TIVA_IFLS_TXIFLSEL_7_8_F (4 << 0) - -#define TIVA_IFLS_RXIFLSEL_MASK (7 << 3) -#define TIVA_IFLS_RXIFLSEL_7_8_E (0 << 3) -#define TIVA_IFLS_RXIFLSEL_3_4_E (1 << 3) -#define TIVA_IFLS_RXIFLSEL_1_2_E (2 << 3) -#define TIVA_IFLS_RXIFLSEL_1_4_E (3 << 3) -#define TIVA_IFLS_RXIFLSEL_1_8_E (4 << 3) - -/** - * @} - */ - -/** - * @name MIS register bits definitions - * @{ - */ - -#define TIVA_MIS_CTSMIS (1 << 1) - -#define TIVA_MIS_RXMIS (1 << 4) - -#define TIVA_MIS_TXMIS (1 << 5) - -#define TIVA_MIS_RTMIS (1 << 6) - -#define TIVA_MIS_FEMIS (1 << 7) - -#define TIVA_MIS_PEMIS (1 << 8) - -#define TIVA_MIS_BEMIS (1 << 9) - -#define TIVA_MIS_OEMIS (1 << 10) - -#define TIVA_MIS_9BITMIS (1 << 12) - -/** - * @} - */ - -/** - * @name IM register bits definitions - * @{ - */ - -#define TIVA_IM_CTSIM (1 << 1) - -#define TIVA_IM_RXIM (1 << 4) - -#define TIVA_IM_TXIM (1 << 5) - -#define TIVA_IM_RTIM (1 << 6) - -#define TIVA_IM_FEIM (1 << 7) - -#define TIVA_IM_PEIM (1 << 8) - -#define TIVA_IM_BEIM (1 << 9) - -#define TIVA_IM_OEIM (1 << 10) - -#define TIVA_IM_9BITIM (1 << 12) - -/** - * @} - */ -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief UART0 driver enable switch. - * @details If set to @p TRUE the support for UART0 is included. - * @note The default is @p TRUE. - */ -#if !defined(TIVA_SERIAL_USE_UART0) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART0 FALSE -#endif - -/** - * @brief UART1 driver enable switch. - * @details If set to @p TRUE the support for UART1 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART1) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART1 FALSE -#endif - -/** - * @brief UART2 driver enable switch. - * @details If set to @p TRUE the support for UART2 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART2) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART2 FALSE -#endif - -/** - * @brief UART3 driver enable switch. - * @details If set to @p TRUE the support for UART3 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART3) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART3 FALSE -#endif - -/** - * @brief UART4 driver enable switch. - * @details If set to @p TRUE the support for UART4 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART4) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART4 FALSE -#endif - -/** - * @brief UART5 driver enable switch. - * @details If set to @p TRUE the support for UART5 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART5) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART5 FALSE -#endif - -/** - * @brief UART6 driver enable switch. - * @details If set to @p TRUE the support for UART6 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART6) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART6 FALSE -#endif - -/** - * @brief UART7 driver enable switch. - * @details If set to @p TRUE the support for UART7 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART7) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART7 FALSE -#endif - -/** - * @brief UART0 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART0_PRIORITY 5 -#endif - -/** - * @brief UART1 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART1_PRIORITY 5 -#endif - -/** - * @brief UART2 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART2_PRIORITY 5 -#endif - -/** - * @brief UART3 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART3_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART3_PRIORITY 5 -#endif - -/** - * @brief UART4 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART4_PRIORITY 5 -#endif - -/** - * @brief UART5 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART5_PRIORITY 5 -#endif - -/** - * @brief UART6 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART6_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART6_PRIORITY 5 -#endif - -/** - * @brief UART7 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART7_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART7_PRIORITY 5 -#endif - -/** - * @} - */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !TIVA_SERIAL_USE_UART0 && !TIVA_SERIAL_USE_UART1 && \ - !TIVA_SERIAL_USE_UART2 && !TIVA_SERIAL_USE_UART3 && \ - !TIVA_SERIAL_USE_UART4 && !TIVA_SERIAL_USE_UART5 && \ - !TIVA_SERIAL_USE_UART6 && !TIVA_SERIAL_USE_UART7 -#error "SERIAL driver activated but no UART peripheral assigned" -#endif - -#if TIVA_SERIAL_USE_UART0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART0_PRIORITY) -#error "Invalid IRQ priority assigned to UART0" -#endif - -#if TIVA_SERIAL_USE_UART1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART1_PRIORITY) -#error "Invalid IRQ priority assigned to UART1" -#endif - -#if TIVA_SERIAL_USE_UART2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART2_PRIORITY) -#error "Invalid IRQ priority assigned to UART2" -#endif - -#if TIVA_SERIAL_USE_UART3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART3_PRIORITY) -#error "Invalid IRQ priority assigned to UART3" -#endif - -#if TIVA_SERIAL_USE_UART4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART4_PRIORITY) -#error "Invalid IRQ priority assigned to UART4" -#endif - -#if TIVA_SERIAL_USE_UART5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART5_PRIORITY) -#error "Invalid IRQ priority assigned to UART5" -#endif - -#if TIVA_SERIAL_USE_UART6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART6_PRIORITY) -#error "Invalid IRQ priority assigned to UART6" -#endif - -#if TIVA_SERIAL_USE_UART7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART7_PRIORITY) -#error "Invalid IRQ priority assigned to UART7" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Tiva Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t sc_speed; - /* End of the mandatory fields. */ - /** - * @brief Initialization value for the LCRH (Line Control) register. - */ - uint32_t sc_lcrh; - /** - * @brief Initialization value for the IFLS (Interrupt FIFO Level Select) - * register. - */ - uint32_t sc_ifls; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - input_queue_t iqueue; \ - /* Output queue.*/ \ - output_queue_t oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the USART registers block.*/ \ - UART_TypeDef *uart; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if TIVA_SERIAL_USE_UART0 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif - -#if TIVA_SERIAL_USE_UART1 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif - -#if TIVA_SERIAL_USE_UART2 && !defined(__DOXYGEN__) -extern SerialDriver SD3; -#endif - -#if TIVA_SERIAL_USE_UART3 && !defined(__DOXYGEN__) -extern SerialDriver SD4; -#endif - -#if TIVA_SERIAL_USE_UART4 && !defined(__DOXYGEN__) -extern SerialDriver SD5; -#endif - -#if TIVA_SERIAL_USE_UART5 && !defined(__DOXYGEN__) -extern SerialDriver SD6; -#endif - -#if TIVA_SERIAL_USE_UART6 && !defined(__DOXYGEN__) -extern SerialDriver SD7; -#endif - -#if TIVA_SERIAL_USE_UART7 && !defined(__DOXYGEN__) -extern SerialDriver SD8; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL */ - -#endif /* HAL_SERIAL_LLD_H */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_spi_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_spi_lld.c deleted file mode 100644 index ded2b99..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_spi_lld.c +++ /dev/null @@ -1,685 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/spi_lld.c - * @brief TM4C123x/TM4C129x SPI subsystem low level driver. - * - * @addtogroup SPI - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief SPI1 driver identifier. - */ -#if TIVA_SPI_USE_SSI0 || defined(__DOXYGEN__) -SPIDriver SPID1; -#endif - -/** - * @brief SPI2 driver identifier. - */ -#if TIVA_SPI_USE_SSI1 || defined(__DOXYGEN__) -SPIDriver SPID2; -#endif - -/** - * @brief SPI3 driver identifier. - */ -#if TIVA_SPI_USE_SSI2 || defined(__DOXYGEN__) -SPIDriver SPID3; -#endif - -/** - * @brief SPI4 driver identifier. - */ -#if TIVA_SPI_USE_SSI3 || defined(__DOXYGEN__) -SPIDriver SPID4; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -static uint16_t dummytx; -static uint16_t dummyrx; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Common IRQ handler. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -static void spi_serve_interrupt(SPIDriver *spip) -{ - SSI_TypeDef *ssi = spip->ssi; - uint32_t mis = ssi->MIS; - uint32_t dmachis = UDMA->CHIS; - - /* SPI error handling.*/ - if ((mis & (TIVA_MIS_RORMIS | TIVA_MIS_RTMIS)) != 0) { - TIVA_SPI_SSI_ERROR_HOOK(spip); - } - - if ( (dmachis & ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) == - ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) { - /* Clear DMA Channel interrupts.*/ - UDMA->CHIS = (1 << spip->dmarxnr) | (1 << spip->dmatxnr); - - /* Portable SPI ISR code defined in the high level driver, note, it is a - macro.*/ - _spi_isr_code(spip); - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_SPI_USE_SSI0 || defined(__DOXYGEN__) -/** - * @brief SSI0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_SSI0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - spi_serve_interrupt(&SPID1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_SPI_USE_SSI1 || defined(__DOXYGEN__) -/** - * @brief SSI1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_SSI1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - spi_serve_interrupt(&SPID2); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_SPI_USE_SSI2 || defined(__DOXYGEN__) -/** - * @brief SSI2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_SSI2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - spi_serve_interrupt(&SPID3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_SPI_USE_SSI3 || defined(__DOXYGEN__) -/** - * @brief SSI3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_SSI3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - spi_serve_interrupt(&SPID4); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - * - * @notapi - */ -void spi_lld_init(void) -{ - dummytx = 0xFFFF; - -#if TIVA_SPI_USE_SSI0 - spiObjectInit(&SPID1); - SPID1.ssi = SSI0; - SPID1.dmarxnr = TIVA_SPI_SSI0_RX_UDMA_CHANNEL; - SPID1.dmatxnr = TIVA_SPI_SSI0_TX_UDMA_CHANNEL; - SPID1.rxchnmap = TIVA_SPI_SSI0_RX_UDMA_MAPPING; - SPID1.txchnmap = TIVA_SPI_SSI0_TX_UDMA_MAPPING; -#endif - -#if TIVA_SPI_USE_SSI1 - spiObjectInit(&SPID2); - SPID2.ssi = SSI1; - SPID2.dmarxnr = TIVA_SPI_SSI1_RX_UDMA_CHANNEL; - SPID2.dmatxnr = TIVA_SPI_SSI1_TX_UDMA_CHANNEL; - SPID2.rxchnmap = TIVA_SPI_SSI1_RX_UDMA_MAPPING; - SPID2.txchnmap = TIVA_SPI_SSI1_TX_UDMA_MAPPING; -#endif - -#if TIVA_SPI_USE_SSI2 - spiObjectInit(&SPID3); - SPID3.ssi = SSI2; - SPID3.dmarxnr = TIVA_SPI_SSI2_RX_UDMA_CHANNEL; - SPID3.dmatxnr = TIVA_SPI_SSI2_TX_UDMA_CHANNEL; - SPID3.rxchnmap = TIVA_SPI_SSI2_RX_UDMA_MAPPING; - SPID3.txchnmap = TIVA_SPI_SSI2_TX_UDMA_MAPPING; -#endif - -#if TIVA_SPI_USE_SSI3 - spiObjectInit(&SPID4); - SPID4.ssi = SSI3; - SPID4.dmarxnr = TIVA_SPI_SSI3_RX_UDMA_CHANNEL; - SPID4.dmatxnr = TIVA_SPI_SSI3_TX_UDMA_CHANNEL; - SPID4.rxchnmap = TIVA_SPI_SSI3_RX_UDMA_MAPPING; - SPID4.txchnmap = TIVA_SPI_SSI3_TX_UDMA_MAPPING; -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_start(SPIDriver *spip) -{ - if (spip->state == SPI_STOP) { - /* Clock activation.*/ -#if TIVA_SPI_USE_SSI0 - if (&SPID1 == spip) { - bool b; - b = udmaChannelAllocate(spip->dmarxnr); - osalDbgAssert(!b, "channel already allocated"); - b = udmaChannelAllocate(spip->dmatxnr); - osalDbgAssert(!b, "channel already allocated"); - - /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 0); - while (!(SYSCTL->PRSSI & (1 << 0))) - ; - - nvicEnableVector(TIVA_SSI0_NUMBER, TIVA_SPI_SSI0_IRQ_PRIORITY); - } -#endif -#if TIVA_SPI_USE_SSI1 - if (&SPID2 == spip) { - bool b; - b = udmaChannelAllocate(spip->dmarxnr); - osalDbgAssert(!b, "channel already allocated"); - b = udmaChannelAllocate(spip->dmatxnr); - osalDbgAssert(!b, "channel already allocated"); - - /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 1); - while (!(SYSCTL->PRSSI & (1 << 1))) - ; - - nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY); - } -#endif -#if TIVASPI_USE_SSI2 - if (&SPID2 == spip) { - bool b; - b = udmaChannelAllocate(spip->dmarxnr); - osalDbgAssert(!b, "channel already allocated"); - b = udmaChannelAllocate(spip->dmatxnr); - osalDbgAssert(!b, "channel already allocated"); - - /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 2); - while (!(SYSCTL->PRSSI & (1 << 2))) - ; - - nvicEnableVector(TIVA_SSI2_NUMBER, TIVA_SPI_SSI2_IRQ_PRIORITY); - } -#endif -#if TIVA_SPI_USE_SSI3 - if (&SPID2 == spip) { - bool b; - b = udmaChannelAllocate(spip->dmarxnr); - osalDbgAssert(!b, "channel already allocated"); - b = udmaChannelAllocate(spip->dmatxnr); - osalDbgAssert(!b, "channel already allocated"); - - /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 3); - while (!(SYSCTL->PRSSI & (1 << 3))) - ; - - nvicEnableVector(TIVA_SSI3_NUMBER, TIVA_SPI_SSI3_IRQ_PRIORITY); - } -#endif - - UDMA->CHMAP[spip->dmarxnr / 8] |= (spip->rxchnmap << (spip->dmarxnr % 8)); - UDMA->CHMAP[spip->dmatxnr / 8] |= (spip->txchnmap << (spip->dmatxnr % 8)); - } - /* Set master operation mode.*/ - spip->ssi->CR1 = 0; - - /* Clock configuration - System Clock.*/ - spip->ssi->CC = 0; - - /* Clear pending interrupts.*/ - spip->ssi->ICR = TIVA_ICR_RTIC | TIVA_ICR_RORIC; - - /* Enable Receive Time-Out and Receive Overrun Interrupts.*/ - spip->ssi->IM = TIVA_IM_RTIM | TIVA_IM_RORIM; - - /* Configure the clock prescale divisor.*/ - spip->ssi->CPSR = spip->config->cpsr; - - /* Serial clock rate, phase/polarity, data size, fixed SPI frame format.*/ - spip->ssi->CR0 = (spip->config->cr0 & ~TIVA_CR0_FRF_MASK) | TIVA_CR0_FRF(0); - - /* Enable SSI.*/ - spip->ssi->CR1 |= TIVA_CR1_SSE; - - /* Enable RX and TX DMA channels.*/ - spip->ssi->DMACTL = (TIVA_DMACTL_TXDMAE | TIVA_DMACTL_RXDMAE); -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_stop(SPIDriver *spip) -{ - if (spip->state != SPI_STOP) { - spip->ssi->CR1 = 0; - spip->ssi->CR0 = 0; - spip->ssi->CPSR = 0; - - udmaChannelRelease(spip->dmarxnr); - udmaChannelRelease(spip->dmatxnr); - -#if TIVA_SPI_USE_SSI0 - if (&SPID1 == spip) { - nvicDisableVector(TIVA_SSI0_NUMBER); - } -#endif -#if TIVA_SPI_USE_SSI1 - if (&SPID2 == spip) { - nvicDisableVector(TIVA_SSI1_NUMBER); - } -#endif -#if TIVA_SPI_USE_SSI2 - if (&SPID3 == spip) { - nvicDisableVector(TIVA_SSI2_NUMBER); - } -#endif -#if TIVA_SPI_USE_SSI3 - if (&SPID4 == spip) { - nvicDisableVector(TIVA_SSI3_NUMBER); - } -#endif - } -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_select(SPIDriver *spip) -{ - palClearPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_unselect(SPIDriver *spip) -{ - palSetPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This function transmits a series of idle words on the SPI bus and - * ignores the received data. This function can be invoked even - * when a slave select signal has not been yet asserted. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @notapi - */ -void spi_lld_ignore(SPIDriver *spip, size_t n) -{ - tiva_udma_table_entry_t *primary = udmaControlTable.primary; - - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { - /* Configure for 8-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; - primary[spip->dmarxnr].dstendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - else { - /* Configure for 16-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; - primary[spip->dmarxnr].dstendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - - dmaChannelSingleBurst(spip->dmatxnr); - dmaChannelPrimary(spip->dmatxnr); - dmaChannelPriorityDefault(spip->dmatxnr); - dmaChannelEnableRequest(spip->dmatxnr); - - dmaChannelSingleBurst(spip->dmarxnr); - dmaChannelPrimary(spip->dmarxnr); - dmaChannelPriorityDefault(spip->dmarxnr); - dmaChannelEnableRequest(spip->dmarxnr); - - /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/ - dmaChannelEnable(spip->dmarxnr); - dmaChannelEnable(spip->dmatxnr); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) -{ - tiva_udma_table_entry_t *primary = udmaControlTable.primary; - - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { - /* Configure for 8-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; - primary[spip->dmarxnr].dstendp = rxbuf+n-1; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - else { - /* Configure for 16-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; - primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - - dmaChannelSingleBurst(spip->dmatxnr); - dmaChannelPrimary(spip->dmatxnr); - dmaChannelPriorityDefault(spip->dmatxnr); - dmaChannelEnableRequest(spip->dmatxnr); - - dmaChannelSingleBurst(spip->dmarxnr); - dmaChannelPrimary(spip->dmarxnr); - dmaChannelPriorityDefault(spip->dmarxnr); - dmaChannelEnableRequest(spip->dmarxnr); - - /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/ - dmaChannelEnable(spip->dmarxnr); - dmaChannelEnable(spip->dmatxnr); -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) -{ - tiva_udma_table_entry_t *primary = udmaControlTable.primary; - - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { - /* Configure for 8-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].dstendp = &spip->ssi->DR; - primary[spip->dmarxnr].srcendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - else { - /* Configure for 16-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].dstendp = &spip->ssi->DR; - primary[spip->dmarxnr].srcendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - - dmaChannelSingleBurst(spip->dmatxnr); - dmaChannelPrimary(spip->dmatxnr); - dmaChannelPriorityDefault(spip->dmatxnr); - dmaChannelEnableRequest(spip->dmatxnr); - - dmaChannelSingleBurst(spip->dmarxnr); - dmaChannelPrimary(spip->dmarxnr); - dmaChannelPriorityDefault(spip->dmarxnr); - dmaChannelEnableRequest(spip->dmarxnr); - - /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/ - dmaChannelEnable(spip->dmarxnr); - dmaChannelEnable(spip->dmatxnr); -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) -{ - tiva_udma_table_entry_t *primary = udmaControlTable.primary; - - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { - /* Configure for 8-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; - primary[spip->dmarxnr].dstendp = rxbuf+n-1; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - else { - /* Configure for 16-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; - primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - - dmaChannelSingleBurst(spip->dmatxnr); - dmaChannelPrimary(spip->dmatxnr); - dmaChannelPriorityDefault(spip->dmatxnr); - dmaChannelEnableRequest(spip->dmatxnr); - - dmaChannelSingleBurst(spip->dmarxnr); - dmaChannelPrimary(spip->dmarxnr); - dmaChannelPriorityDefault(spip->dmarxnr); - dmaChannelEnableRequest(spip->dmarxnr); - - /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/ - dmaChannelEnable(spip->dmarxnr); - dmaChannelEnable(spip->dmatxnr); -} - -/** - * @brief Exchanges one frame using a polled wait. - * @details This synchronous function exchanges one frame using a polled - * synchronization method. This function is useful when exchanging - * small amount of data on high speed channels, usually in this - * situation is much more efficient just wait for completion using - * polling than suspending the thread waiting for an interrupt. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] frame the data frame to send over the SPI bus - * @return The received data frame from the SPI bus. - */ -uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) -{ - spip->ssi->DR = (uint32_t)frame; - while ((spip->ssi->SR & TIVA_SR_RNE) == 0) - ; - return (uint16_t)spip->ssi->DR; -} - -#endif /* HAL_USE_SPI */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_spi_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_spi_lld.h deleted file mode 100644 index 2adc9ed..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_spi_lld.h +++ /dev/null @@ -1,388 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/spi_lld.h - * @brief TM4C123x/TM4C129x SPI subsystem low level driver. - * - * @addtogroup SPI - * @{ - */ - -#ifndef HAL_SPI_LLD_H -#define HAL_SPI_LLD_H - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Control 0 - * @{ - */ -#define TIVA_CR0_DSS_MASK 0x0F -#define TIVA_CR0_DSS(n) ((n-1) << 0) - -#define TIVA_CR0_FRF_MASK (3 << 4) -#define TIVA_CR0_FRF(n) ((n) << 4) - -#define TIVA_CR0_SPO (1 << 6) -#define TIVA_CR0_SPH (1 << 7) - -#define TIVA_CR0_SRC_MASK (0xFF << 8) -#define TIVA_CR0_SRC(n) ((n) << 8) -/** @} */ - -/** - * @name Control 1 - * @{ - */ -#define TIVA_CR1_LBM (1 << 0) -#define TIVA_CR1_SSE (1 << 1) -#define TIVA_CR1_MS (1 << 2) -#define TIVA_CR1_SOD (1 << 3) -#define TIVA_CR1_EOT (1 << 4) -/** @} */ - -/** - * @name Status - * @{ - */ -#define TIVA_SR_TFE (1 << 0) -#define TIVA_SR_TNF (1 << 1) -#define TIVA_SR_RNE (1 << 2) -#define TIVA_SR_RFF (1 << 3) -#define TIVA_SR_BSY (1 << 4) -/** @} */ - -/** - * @name Interrupt Mask - * @{ - */ -#define TIVA_IM_RORIM (1 << 0) -#define TIVA_IM_RTIM (1 << 1) -#define TIVA_IM_RXIM (1 << 2) -#define TIVA_IM_TXIM (1 << 3) -/** @} */ - -/** - * @name Interrupt Status - * @{ - */ -#define TIVA_IS_RORIS (1 << 0) -#define TIVA_IS_RTIS (1 << 1) -#define TIVA_IS_RXIS (1 << 2) -#define TIVA_IS_TXIS (1 << 3) -/** @} */ - -/** - * @name Masked Interrupt Status - * @{ - */ -#define TIVA_MIS_RORMIS (1 << 0) -#define TIVA_MIS_RTMIS (1 << 1) -#define TIVA_MIS_RXMIS (1 << 2) -#define TIVA_MIS_TXMIS (1 << 3) -/** @} */ - -/** - * @name Interrupt Clear - * @{ - */ -#define TIVA_ICR_RORIC (1 << 0) -#define TIVA_ICR_RTIC (1 << 1) -/** @} */ - -/** - * @name DMA Control - * @{ - */ -#define TIVA_DMACTL_RXDMAE (1 << 0) -#define TIVA_DMACTL_TXDMAE (1 << 1) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SSI0 driver enable switch. - * @details If set to @p TRUE the support for SSI0 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_SPI_USE_SSI0) || defined(__DOXYGEN__) -#define TIVA_SPI_USE_SSI0 FALSE -#endif - -/** - * @brief SSI1 driver enable switch. - * @details If set to @p TRUE the support for SSI1 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_SPI_USE_SSI1) || defined(__DOXYGEN__) -#define TIVA_SPI_USE_SSI1 FALSE -#endif - -/** - * @brief SSI2 driver enable switch. - * @details If set to @p TRUE the support for SSI2 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_SPI_USE_SSI2) || defined(__DOXYGEN__) -#define TIVA_SPI_USE_SSI2 FALSE -#endif - -/** - * @brief SSI3 driver enable switch. - * @details If set to @p TRUE the support for SSI3 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_SPI_USE_SSI3) || defined(__DOXYGEN__) -#define TIVA_SPI_USE_SSI3 FALSE -#endif - -/** - * @brief SPID1 interrupt priority level setting. - */ -#if !defined(TIVA_SPI_SSI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SPI_SSI0_IRQ_PRIORITY 5 -#endif - -/** - * @brief SPID2 interrupt priority level setting. - */ -#if !defined(TIVA_SPI_SSI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SPI_SSI1_IRQ_PRIORITY 5 -#endif - -/** - * @brief SPID3 interrupt priority level setting. - */ -#if !defined(TIVA_SPI_SSI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SPI_SSI2_IRQ_PRIORITY 5 -#endif - -/** - * @brief SPID4 interrupt priority level setting. - */ -#if !defined(TIVA_SPI_SSI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SPI_SSI3_IRQ_PRIORITY 5 -#endif - -/** - * @brief SPI error hook. - */ -#if !defined(TIVA_SPI_SSI_ERROR_HOOK) || defined(__DOXYGEN__) -#define TIVA_SPI_SSI_ERROR_HOOK(spip) osalSysHalt("SSI failure") -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if TIVA_SPI_USE_SSI0 && !TIVA_HAS_SSI0 -#error "SSI0 not present in the selected device" -#endif - -#if TIVA_SPI_USE_SSI1 && !TIVA_HAS_SSI1 -#error "SSI1 not present in the selected device" -#endif - -#if TIVA_SPI_USE_SSI2 && !TIVA_HAS_SSI2 -#error "SSI2 not present in the selected device" -#endif - -#if TIVA_SPI_USE_SSI3 && !TIVA_HAS_SSI03 -#error "SSI3 not present in the selected device" -#endif - -#if !TIVA_SPI_USE_SSI0 && !TIVA_SPI_USE_SSI1 && !TIVA_SPI_USE_SSI2 && \ - !TIVA_SPI_USE_SSI3 -#error "SPI driver activated but no SSI peripheral assigned" -#endif - -#if TIVA_SPI_USE_SSI0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SSI0" -#endif - -#if TIVA_SPI_USE_SSI1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SSI1" -#endif - -#if TIVA_SPI_USE_SSI2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SSI2" -#endif - -#if TM4C123x_SPI_USE_SSI3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SSI3" -#endif - -#if !defined(TIVA_UDMA_REQUIRED) -#define TIVA_UDMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an SPI driver. - */ -typedef struct SPIDriver SPIDriver; - -/** - * @brief SPI notification callback type. - * - * @param[in] spip pointer to the @p SPIDriver object triggering the - * callback - */ -typedef void (*spicallback_t)(SPIDriver *spip); - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief Operation complete callback or @p NULL. - */ - spicallback_t end_cb; - /* End of the mandatory fields.*/ - /** - * @brief The chip select line port. - */ - ioportid_t ssport; - /** - * @brief The chip select line pad number. - */ - uint16_t sspad; - /** - * @brief SSI CR0 initialization data. - */ - uint16_t cr0; - /** - * @brief SSI CPSR initialization data. - */ - uint32_t cpsr; -} SPIConfig; - -/** - * @brief Structure representing a SPI driver. - */ -struct SPIDriver { - /** - * @brief Driver state. - */ - spistate_t state; - /** - * @brief Current configuration data. - */ - const SPIConfig *config; -#if SPI_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif /* SPI_USE_WAIT */ -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#endif /* SPI_USE_MUTUAL_EXCLUSION */ -#if defined(SPI_DRIVER_EXT_FIELDS) - SPI_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the SSI registers block. - */ - SSI_TypeDef *ssi; - /** - * @brief Receive DMA channel number. - */ - uint8_t dmarxnr; - /** - * @brief Transmit DMA channel number. - */ - uint8_t dmatxnr; - /** - * @brief Receive DMA channel map. - */ - uint8_t rxchnmap; - /** - * @brief Transmit DMA channel map. - */ - uint8_t txchnmap; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if TIVA_SPI_USE_SSI0 && !defined(__DOXYGEN__) -extern SPIDriver SPID1; -#endif - -#if TIVA_SPI_USE_SSI1 && !defined(__DOXYGEN__) -extern SPIDriver SPID2; -#endif - -#if TIVA_SPI_USE_SSI2 && !defined(__DOXYGEN__) -extern SPIDriver SPID3; -#endif - -#if TIVA_SPI_USE_SSI3 && !defined(__DOXYGEN__) -extern SPIDriver SPID4; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void spi_lld_init(void); - void spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); - void spi_lld_ignore(SPIDriver *spip, size_t n); - void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); - uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SPI */ - -#endif /* HAL_SPI_LLD_H */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_st_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_st_lld.c deleted file mode 100644 index 30fdb8a..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_st_lld.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Tiva/LLD/st_lld.c - * @brief ST Driver subsystem low level driver code. - * - * @addtogroup ST - * @{ - */ - -#include "hal.h" - -#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING - -#if (TIVA_ST_USE_WIDE_TIMER == TRUE) - -#if TIVA_ST_TIMER_NUMBER == 0 -#define ST_HANDLER TIVA_WGPT0A_HANDLER -#define ST_NUMBER TIVA_WGPT0A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 0)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 0))) - -#elif TIVA_ST_TIMER_NUMBER == 1 -#define ST_HANDLER TIVA_WGPT1A_HANDLER -#define ST_NUMBER TIVA_WGPT1A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 1)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 1))) - -#elif TIVA_ST_TIMER_NUMBER == 2 -#define ST_HANDLER TIVA_WGPT2A_HANDLER -#define ST_NUMBER TIVA_WGPT2A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 2)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 2))) - -#elif TIVA_ST_TIMER_NUMBER == 3 -#define ST_HANDLER TIVA_WGPT3A_HANDLER -#define ST_NUMBER TIVA_WGPT3A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 3)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 3))) - -#elif TIVA_ST_TIMER_NUMBER == 4 -#define ST_HANDLER TIVA_WGPT4A_HANDLER -#define ST_NUMBER TIVA_WGPT4A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 4)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 4))) - -#elif TIVA_ST_TIMER_NUMBER == 5 -#define ST_HANDLER TIVA_WGPT5A_HANDLER -#define ST_NUMBER TIVA_WGPT5A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 5)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 5))) - -#else -#error "TIVA_ST_USE_TIMER specifies an unsupported timer" -#endif - -#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF -#error "the selected ST frequency is not obtainable because TIM timer prescaler limits" -#endif - -#elif (TIVA_ST_USE_WIDE_TIMER == FALSE) - -#if TIVA_ST_TIMER_NUMBER == 0 -#define ST_HANDLER TIVA_GPT0A_HANDLER -#define ST_NUMBER TIVA_GPT0A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 0)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 0))) - -#elif TIVA_ST_TIMER_NUMBER == 1 -#define ST_HANDLER TIVA_GPT1A_HANDLER -#define ST_NUMBER TIVA_GPT1A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 1)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 1))) - -#elif TIVA_ST_TIMER_NUMBER == 2 -#define ST_HANDLER TIVA_GPT2A_HANDLER -#define ST_NUMBER TIVA_GPT2A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 2)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 2))) - -#elif TIVA_ST_TIMER_NUMBER == 3 -#define ST_HANDLER TIVA_GPT3A_HANDLER -#define ST_NUMBER TIVA_GPT3A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 3)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 3))) - -#elif TIVA_ST_TIMER_NUMBER == 4 -#define ST_HANDLER TIVA_GPT4A_HANDLER -#define ST_NUMBER TIVA_GPT4A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 4)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 4))) - -#elif TIVA_ST_TIMER_NUMBER == 5 -#define ST_HANDLER TIVA_GPT5A_HANDLER -#define ST_NUMBER TIVA_GPT5A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 5)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 5))) - -#else -#error "TIVA_ST_USE_TIMER specifies an unsupported timer" -#endif - -#if (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1 > 0xFF -#error "the selected ST frequency is not obtainable because TIM timer prescaler limits" -#endif - -#endif - -#if TIVA_SYSCLK % OSAL_ST_FREQUENCY != 0 -#error "the selected ST frequency is not obtainable because integer rounding" -#endif - -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__) -/** - * @brief System Timer vector. - * @details This interrupt is used for system tick in periodic mode. - * - * @isr - */ -OSAL_IRQ_HANDLER(SysTick_Handler) -{ - OSAL_IRQ_PROLOGUE(); - - osalSysLockFromISR(); - osalOsTimerHandlerI(); - osalSysUnlockFromISR(); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ - -#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__) -/** - * @brief GPT interrupt handler. - * @details This interrupt is used for system tick in free running mode. - * - * @isr - */ -OSAL_IRQ_HANDLER(ST_HANDLER) -{ - uint32_t mis; - - OSAL_IRQ_PROLOGUE(); - - mis = TIVA_ST_TIM->MIS; - TIVA_ST_TIM->ICR = mis; - - if (mis & GPTM_IMR_TAMIM) { - osalSysLockFromISR(); - osalOsTimerHandlerI(); - osalSysUnlockFromISR(); - } - - OSAL_IRQ_EPILOGUE(); -} -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ST driver initialization. - * - * @notapi - */ -void st_lld_init(void) -{ -#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING - /* Free running counter mode.*/ - - /* Enabling timer clock.*/ - ST_ENABLE_CLOCK(); - - /* Wait until timer peripheral is ready */ - ST_WAIT_CLOCK(); - - /* Initializing the counter in free running down mode.*/ - TIVA_ST_TIM->CTL = 0; - TIVA_ST_TIM->CFG = GPTM_CFG_CFG_SPLIT; /* Timer split mode */ - TIVA_ST_TIM->TAMR = (GPTM_TAMR_TAMR_PERIODIC |/* Periodic mode */ - GPTM_TAMR_TAMIE | /* Match interrupt enable */ - GPTM_TAMR_TASNAPS); /* Snapshot mode */ - - TIVA_ST_TIM->TAPR = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1; - TIVA_ST_TIM->CTL = (GPTM_CTL_TAEN | /* Timer A enable */ - GPTM_CTL_TASTALL); /* Timer A stall when paused */ - - /* IRQ enabled.*/ - nvicEnableVector(ST_NUMBER, TIVA_ST_IRQ_PRIORITY); -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ - -#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC - /* Periodic systick mode, the Cortex-Mx internal systick timer is used - in this mode.*/ - SysTick->LOAD = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; - - /* IRQ enabled.*/ - nvicSetSystemHandlerPriority(HANDLER_SYSTICK, TIVA_ST_IRQ_PRIORITY); -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ -} - -#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_st_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_st_lld.h deleted file mode 100644 index 35bf008..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_st_lld.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Tiva/LLD/st_lld.h - * @brief ST Driver subsystem low level driver header. - * @details This header is designed to be include-able without having to - * include other files from the HAL. - * - * @addtogroup ST - * @{ - */ - -#ifndef HAL_ST_LLD_H -#define HAL_ST_LLD_H - -#include "mcuconf.h" -#include "tiva_registry.h" -#include "tiva_gpt.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SysTick timer IRQ priority. - */ -#if !defined(TIVA_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_ST_IRQ_PRIORITY 2 -#endif - -/** - * @brief GPTx unit (by number) to be used for free running operations. - * @note You must select a 32 bits timer if a 32 bits @p systick_t type - * is required. - */ -#if !defined(TIVA_ST_TIMER_NUMBER) || defined(__DOXYGEN__) -#define TIVA_ST_TIMER_NUMBER 0 -#endif - -/** - * @brief When set to @p TRUE a wide timer is used. When set to @p FALSE a - * normal timer is used. - */ -#if !defined(TIVA_ST_USE_WIDE_TIMER) || defined(__DOXYGEN__) -#define TIVA_ST_USE_WIDE_TIMER TRUE -#endif - -/** - * @} - */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (TIVA_ST_USE_WIDE_TIMER == TRUE) - -#if TIVA_ST_TIMER_NUMBER == 0 -#if !TIVA_HAS_WGPT0 -#error "WGPT0 not present" -#endif -#define TIVA_ST_TIM WGPT0 - -#elif TIVA_ST_TIMER_NUMBER == 1 -#if !TIVA_HAS_WGPT1 -#error "WGPT1 not present" -#endif -#define TIVA_ST_TIM WGPT1 - -#elif TIVA_ST_TIMER_NUMBER == 2 -#if !TIVA_HAS_WGPT2 -#error "WGPT2 not present" -#endif -#define TIVA_ST_TIM WGPT2 - -#elif TIVA_ST_TIMER_NUMBER == 3 -#if !TIVA_HAS_WGPT3 -#error "WGPT3 not present" -#endif -#define TIVA_ST_TIM WGPT3 - -#elif TIVA_ST_TIMER_NUMBER == 4 -#if !TIVA_HAS_WGPT4 -#error "WGPT4 not present" -#endif -#define TIVA_ST_TIM WGPT4 - -#elif TIVA_ST_TIMER_NUMBER == 5 -#if !TIVA_HAS_WGPT5 -#error "WGPT5 not present" -#endif -#define TIVA_ST_TIM WGPT5 - -#else -#error "TIVA_ST_USE_TIMER specifies an unsupported timer" -#endif - -#elif (TIVA_ST_USE_WIDE_TIMER == FALSE) - -#if TIVA_ST_TIMER_NUMBER == 0 -#if !TIVA_HAS_GPT0 -#error "GPT0 not present" -#endif -#define TIVA_ST_TIM GPT0 - -#elif TIVA_ST_TIMER_NUMBER == 1 -#if !TIVA_HAS_GPT1 -#error "GPT1 not present" -#endif -#define TIVA_ST_TIM GPT1 - -#elif TIVA_ST_TIMER_NUMBER == 2 -#if !TIVA_HAS_GPT2 -#error "GPT2 not present" -#endif -#define TIVA_ST_TIM GPT2 - -#elif TIVA_ST_TIMER_NUMBER == 3 -#if !TIVA_HAS_GPT3 -#error "GPT3 not present" -#endif -#define TIVA_ST_TIM GPT3 - -#elif TIVA_ST_TIMER_NUMBER == 4 -#if !TIVA_HAS_GPT4 -#error "GPT4 not present" -#endif -#define TIVA_ST_TIM GPT4 - -#elif TIVA_ST_TIMER_NUMBER == 5 -#if !TIVA_HAS_GPT5 -#error "GPT5 not present" -#endif -#define TIVA_ST_TIM GPT5 - -#else -#error "TIVA_ST_TIMER_NUMBER specifies an unsupported timer" -#endif - -#else -#error "wrong value defined for TIVA_ST_USE_WIDE_TIMER" -#endif - -#if OSAL_ST_MODE != OSAL_ST_MODE_NONE && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ST" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void st_lld_init(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Driver inline functions. */ -/*===========================================================================*/ - -/** - * @brief Returns the time counter value. - * - * @return The counter value. - * - * @notapi - */ -static inline systime_t st_lld_get_counter(void) -{ - return (systime_t) (((systime_t) 0xffffffff) - TIVA_ST_TIM->TAR); -} - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * - * @param[in] time the time to be set for the first alarm - * - * @notapi - */ -static inline void st_lld_start_alarm(systime_t time) -{ - TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time); - TIVA_ST_TIM->ICR = TIVA_ST_TIM->MIS; - TIVA_ST_TIM->IMR = GPTM_IMR_TAMIM; -} - -/** - * @brief Stops the alarm interrupt. - * - * @notapi - */ -static inline void st_lld_stop_alarm(void) -{ - TIVA_ST_TIM->IMR = 0; -} - -/** - * @brief Sets the alarm time. - * - * @param[in] time the time to be set for the next alarm - * - * @notapi - */ -static inline void st_lld_set_alarm(systime_t time) -{ - TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time); -} - -/** - * @brief Returns the current alarm time. - * - * @return The currently set alarm time. - * - * @notapi - */ -static inline systime_t st_lld_get_alarm(void) -{ - return (systime_t) (((systime_t)0xffffffff) - TIVA_ST_TIM->TAMATCHR); -} - -/** - * @brief Determines if the alarm is active. - * - * @return The alarm status. - * @retval false if the alarm is not active. - * @retval true is the alarm is active - * - * @notapi - */ -static inline bool st_lld_is_alarm_active(void) -{ - return (bool) ((TIVA_ST_TIM->IMR & GPTM_IMR_TAMIM) !=0); -} - -#endif /* HAL_ST_LLD_H */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_wdg_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_wdg_lld.c deleted file mode 100644 index 38dcef0..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_wdg_lld.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - - -/** - * @file TIVA/wdg_lld.c - * @brief WDG Driver subsystem low level driver source. - * - * @addtogroup WDG - * @{ - */ - -#include "hal.h" - -#if HAL_USE_WDG || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -#if TIVA_WDG_USE_WDT0 || defined(__DOXYGEN__) -WDGDriver WDGD1; -#endif /* TIVA_WDG_USE_WDT0 */ - -#if TIVA_WDG_USE_WDT1 || defined(__DOXYGEN__) -WDGDriver WDGD2; -#endif /* TIVA_WDG_USE_WDT1 */ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared IRQ handler. - * - * @param[in] wdgp pointer to @p WDGDriver object. - */ -static void serve_interrupt(WDGDriver *wdgp) -{ - uint32_t mis; - - mis = wdgp->wdt->MIS; - - if (mis & MIS_WDTMIS) { - /* Invoke callback, if any */ - if (wdgp->config->callback) { - if (wdgp->config->callback(wdgp)) { - /* Clear interrupt */ - wdgp->wdt->ICR = 0; - wdgTivaSyncWrite(wdgp); - } - } - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_WDG_USE_WDT0 || TIVA_WDG_USE_WDT1 -/** - * @brief WDT0/WDT1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WDT_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - -#if TIVA_WDG_USE_WDT0 - serve_interrupt(&WDGD1); -#endif - -#if TIVA_WDG_USE_WDT1 - serve_interrupt(&WDGD2); -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_WDG_USE_WDT0 || TIVA_WDG_USE_WDT1 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level WDG driver initialization. - * - * @notapi - */ -void wdg_lld_init(void) -{ -#if TIVA_WDG_USE_WDT0 - WDGD1.state = WDG_STOP; - WDGD1.wdt = WDT0; -#endif /* TIVA_WDG_USE_WDT0 */ - -#if TIVA_WDG_USE_WDT1 - WDGD2.state = WDG_STOP; - WDGD2.wdt = WDT1; -#endif /* TIVA_WDG_USE_WDT1 */ - - /* The shared vector is initialized on driver initialization and never - disabled because it is shared between the Watchdog Timers.*/ - nvicEnableVector(TIVA_WDT_NUMBER, TIVA_WDG_WDT_IRQ_PRIORITY); -} - -/** - * @brief Configures and activates the WDG peripheral. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @notapi - */ -void wdg_lld_start(WDGDriver *wdgp) -{ -#if TIVA_WDG_USE_WDT0 - if (&WDGD1 == wdgp) { - SYSCTL->RCGCWD |= (1 << 0); - - while (!(SYSCTL->PRWD & (1 << 0))) - ; - } -#endif /* TIVA_WDG_USE_WDT0 */ - -#if TIVA_WDG_USE_WDT1 - if (&WDGD2 == wdgp) { - SYSCTL->RCGCWD |= (1 << 1); - - while (!(SYSCTL->PRWD & (1 << 1))) - ; - } -#endif /* TIVA_WDG_USE_WDT1 */ - - wdgp->wdt->LOAD = wdgp->config->load; - wdgTivaSyncWrite(wdgp); - - wdgp->wdt->TEST = wdgp->config->test; - wdgTivaSyncWrite(wdgp); - - wdgp->wdt->CTL |= CTL_RESEN; - wdgTivaSyncWrite(wdgp); - - wdgp->wdt->CTL |= CTL_INTEN; - wdgTivaSyncWrite(wdgp); -} - -/** - * @brief Deactivates the WDG peripheral. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @api - */ -void wdg_lld_stop(WDGDriver *wdgp) -{ -#if TIVA_WDG_USE_WDT0 - if (&WDGD1 == wdgp) { - SYSCTL->SRWD |= (1 << 0); - SYSCTL->SRWD &= ~(1 << 0); - } -#endif /* TIVA_WDG_USE_WDT0 */ - -#if TIVA_WDG_USE_WDT1 - if (&WDGD2 == wdgp) { - SYSCTL->SRWD |= (1 << 1); - SYSCTL->SRWD &= ~(1 << 1); - } -#endif /* TIVA_WDG_USE_WDT1 */ -} - -/** - * @brief Reloads WDG's counter. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @notapi - */ -void wdg_lld_reset(WDGDriver *wdgp) -{ -#if defined(TM4C123_USE_REVISION_6_FIX) || defined(TM4C123_USE_REVISION_7_FIX) - -#if TIVA_WDG_USE_WDT1 - if (&WDGD2 == wdgp) { - /* Number: WDT#02 - * Description: Periodically reloading the count value into the Watchdog - * Timer Load (WDTLOAD) register of the Watchdog Timer 1 - * module will not restart the count, as specified in the data - * sheet. - * Workaround: Disable the Watchdog Timer 1 module by setting the - * appropriate bit in the Watchdog Timer Software Reset (SRWD) - * register before reprogramming the counter.*/ - wdg_lld_stop(wdgp); - wdg_lld_start(wdgp); - return; - } -#endif /* TIVA_WDG_USE_WDT1 */ - -#endif /* defined(TM4C123_USE_REVISION_6_FIX) || - defined(TM4C123_USE_REVISION_7_FIX) */ - wdgp->wdt->LOAD = wdgp->config->load; - wdgTivaSyncWrite(wdgp); -} - -#endif /* HAL_USE_WDG */ - -#if TIVA_WDG_USE_WDT1 -/** - * @brief synchronize after a write to a watchdog register. - * - * @param[in] wdgp pointer to the @p WDGDriver object. - */ -void wdgTivaSyncWrite(WDGDriver *wdgp) -{ - if (&WDGD2 == wdgp) { - while (!(wdgp->wdt->CTL & CTL_WRC)) { - ; - } - } -} -#endif /* TIVA_WDG_USE_WDT1 */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_wdg_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_wdg_lld.h deleted file mode 100644 index f88fa26..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/hal_wdg_lld.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - - -/** - * @file TIVA/wdg_lld.h - * @brief WDG Driver subsystem low level driver header. - * - * @addtogroup WDG - * @{ - */ - -#ifndef _WDG_LLD_H_ -#define _WDG_LLD_H_ - -#if HAL_USE_WDG || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define LOCK_UNLOCK 0x1ACCE551U -#define LOCK_LOCK 0x00000000U - -#define LOCK_IS_UNLOCKED 0U -#define LOCK_IS_LOCKED 1U - -#define TEST_STALL (1 << 8) - -#define MIS_WDTMIS (1 << 0) -#define RIS_WDTRIS (1 << 0) -#define ICR_WDTICR (1 << 0) - -#define CTL_INTEN (1 << 0) -#define CTL_RESEN (1 << 1) -#define CTL_INTTYPE (1 << 2) -#define CTL_WRC (1 << 31) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief WDT driver enable switch. - * @details If set to @p TRUE the support for WDT is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_WDG_USE_WDT) || defined(__DOXYGEN__) -#define TIVA_WDG_USE_WDT FALSE -#endif - -/** - * @brief WDT interrupt priority level setting. - */ -#if !defined(TIVA_WDG_WDT_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_WDG_WDT_IRQ_PRIORITY 5 -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if TIVA_WDG_USE_WDT0 && !TIVA_HAS_WDT0 -#error "WDT0 not present in the selected device" -#endif - -#if TIVA_WDG_USE_WDT1 && !TIVA_HAS_WDT1 -#error "WDT1 not present in the selected device" -#endif - -#if !TIVA_WDG_USE_WDT0 && !TIVA_WDG_USE_WDT1 -#error "WDG driver activated but no WDT peripheral assigned" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an WDG driver. - */ -typedef struct WDGDriver WDGDriver; - -/** - * @brief WDG timeout callback type. - * - * @param[in] wdgp pointer to the @p WDGDriver object triggering the callback. - */ -typedef bool (*wdgcallback_t)(WDGDriver *wdgp); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct -{ - /** - * @brief Interval value used by the WDT. - */ - uint32_t load; - /** - * @brief Timeout callback pointer. - * @note This callback is invoked on the first WDT timeout. If set to - * @p NULL then the callback is disabled. - */ - wdgcallback_t callback; - /** - * @brief Test register configuration value. - */ - uint16_t test; -} WDGConfig; - -/** - * @brief Structure representing an WDG driver. - */ -struct WDGDriver -{ - /** - * @brief Driver state. - */ - wdgstate_t state; - /** - * @brief Current configuration data. - */ - const WDGConfig *config; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the WDT registers block. - */ - WDT_TypeDef *wdt; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -#if !TIVA_WDG_USE_WDT1 -#define wdgTivaSyncWrite(wdt) -#endif - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if TIVA_WDG_USE_WDT0 && !defined(__DOXYGEN__) -extern WDGDriver WDGD1; -#endif - -#if TIVA_WDG_USE_WDT1 && !defined(__DOXYGEN__) -extern WDGDriver WDGD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void wdg_lld_init(void); - void wdg_lld_start(WDGDriver *wdgp); - void wdg_lld_stop(WDGDriver *wdgp); - void wdg_lld_reset(WDGDriver *wdgp); -#if TIVA_WDG_USE_WDT1 - void wdgTivaSyncWrite(WDGDriver *wdgp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_WDG */ - -#endif /* _WDG_LLD_H_ */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/tiva_gpt.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/tiva_gpt.h deleted file mode 100644 index 114831b..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/tiva_gpt.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file tiva_gpt.h - * @brief TIVA GPT registers layout header. - * - * @addtogroup TIVA_GPT - * @{ - */ - -#ifndef TIVA_GPT_H_ -#define TIVA_GPT_H_ - -// cfg -#define GPTM_CFG_CFG_MASK (7 << 0) -#define GPTM_CFG_CFG_WHOLE (0 << 0) -#define GPTM_CFG_CFG_RTC (1 << 0) -#define GPTM_CFG_CFG_SPLIT (4 << 0) - -// tamr -#define GPTM_TAMR_TAMR_MASK (3 << 0) -#define GPTM_TAMR_TAMR_ONESHOT (1 << 0) -#define GPTM_TAMR_TAMR_PERIODIC (2 << 0) -#define GPTM_TAMR_TAMR_CAPTURE (3 << 0) - -#define GPTM_TAMR_TACMR (1 << 2) - -#define GPTM_TAMR_TAAMS (1 << 3) - -#define GPTM_TAMR_TACDIR (1 << 4) - -#define GPTM_TAMR_TAMIE (1 << 5) - -#define GPTM_TAMR_TAWOT (1 << 6) - -#define GPTM_TAMR_TASNAPS (1 << 7) - -#define GPTM_TAMR_TAILD (1 << 8) - -#define GPTM_TAMR_TAPWMIE (1 << 9) - -#define GPTM_TAMR_TAMRSU (1 << 10) - -#define GPTM_TAMR_TAPLO (1 << 11) - -// ctl -#define GPTM_CTL_TAEN (1 << 0) - -#define GPTM_CTL_TASTALL (1 << 1) - -#define GPTM_CTL_TAEVENT_MASK (3 << 2) -#define GPTM_CTL_TAEVENT_POS (0 << 2) -#define GPTM_CTL_TAEVENT_NEG (1 << 2) -#define GPTM_CTL_TAEVENT_BOTH (3 << 2) - -#define GPTM_CTL_RTCEN (1 << 4) - -#define GPTM_CTL_TAOTE (1 << 5) - -#define GPTM_CTL_TAPWML (1 << 6) - -#define GPTM_CTL_TBEN (1 << 8) - -#define GPTM_CTL_TBSTALL (1 << 9) - -#define GPTM_CTL_TBEVENT_MASK (3 << 10) -#define GPTM_CTL_TBEVENT_POS (0 << 10) -#define GPTM_CTL_TBEVENT_NEG (1 << 10) -#define GPTM_CTL_TBEVENT_BOTH (3 << 10) - -#define GPTM_CTL_TBOTE (1 << 13) - -#define GPTM_CTL_TBPWML (1 << 14) - -// imr -#define GPTM_IMR_TATOIM (1 << 0) - -#define GPTM_IMR_CAMIM (1 << 1) - -#define GPTM_IMR_CAEIM (1 << 2) - -#define GPTM_IMR_RTCIM (1 << 3) - -#define GPTM_IMR_TAMIM (1 << 4) - -#define GPTM_IMR_TBTOIM (1 << 8) - -#define GPTM_IMR_CBMIM (1 << 9) - -#define GPTM_IMR_CBEIM (1 << 10) - -#define GPTM_IMR_TBMIM (1 << 11) - -#define GPTM_IMR_WUEIM (1 << 16) - -// icr -#define GPTM_ICR_TATOCINT (1 << 0) - -#define GPTM_ICR_CAMCINT (1 << 1) - -#define GPTM_ICR_CAECINT (1 << 2) - -#define GPTM_ICR_RTCCINT (1 << 3) - -#define GPTM_ICR_TAMCINT (1 << 4) - -#define GPTM_ICR_TBTOCINT (1 << 8) - -#define GPTM_ICR_CBMCINT (1 << 9) - -#define GPTM_ICR_CBECINT (1 << 10) - -#define GPTM_ICR_TBMCINT (1 << 11) - -#define GPTM_ICR_WUECINT (1 << 16) - -#endif /* TIVA_GPT_H_ */ - -/* - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/tiva_udma.c b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/tiva_udma.c deleted file mode 100644 index 9f122b2..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/tiva_udma.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -/* The following macro is only defined if some driver requiring DMA services - has been enabled.*/ -#if defined(TIVA_UDMA_REQUIRED) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -udmaControlTable_t udmaControlTable; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static uint32_t udma_channel_mask; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if !defined(TIVA_UDMA_SW_HANDLER) -#error "TIVA_UDMA_SW_HANDLER not defined" -#endif -/** - * @brief UDMA software interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_UDMA_SW_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - /* TODO Process software transfer interrupts.*/ - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_UDMA_ERR_HANDLER) -#error "TIVA_UDMA_ERR_HANDLER not defined" -#endif -/** - * @brief UDMA error interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_UDMA_ERR_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - /* TODO Do we need to halt the system on a DMA error?*/ - - if (UDMA->ERRCLR) { - UDMA->ERRCLR = 1; - } - - OSAL_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initialize UDMA. - * - * @init - */ -void udmaInit(void) -{ - udma_channel_mask = 0; - - /* Enable UDMA module.*/ - SYSCTL->RCGCDMA = 1; - while (!(SYSCTL->PRDMA & (1 << 0))) - ; - - nvicEnableVector(TIVA_UDMA_ERR_NUMBER, TIVA_UDMA_ERR_IRQ_PRIORITY); - nvicEnableVector(TIVA_UDMA_SW_NUMBER, TIVA_UDMA_SW_IRQ_PRIORITY); - - /* Enable UDMA controller.*/ - UDMA->CFG = 1; - - /* Set address of control table.*/ - UDMA->CTLBASE = (uint32_t)udmaControlTable.primary; -} - -/** - * @brief Allocates a DMA channel. - * - * @special - */ -bool udmaChannelAllocate(uint8_t dmach) -{ - /* Checks if the channel is already taken.*/ - if ((udma_channel_mask & (1 << dmach)) != 0) - return TRUE; - - /* Mark channel as used */ - udma_channel_mask |= (1 << dmach); - - return FALSE; -} - -/** - * @brief Releases a DMA channel. - * - * @special - */ -void udmaChannelRelease(uint8_t dmach) -{ - /* Marks the channel as not used.*/ - udma_channel_mask &= ~(1 << dmach); -} - -#endif diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/tiva_udma.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/tiva_udma.h deleted file mode 100644 index 6479b08..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/LLD/tiva_udma.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef TIVA_UDMA_H_ -#define TIVA_UDMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name CHCTL register defines. - * @{ - */ -#define UDMA_CHCTL_DSTINC_MASK 0xC0000000 -#define UDMA_CHCTL_DSTINC_0 0xC0000000 -#define UDMA_CHCTL_DSTINC_8 0x00000000 -#define UDMA_CHCTL_DSTINC_16 0x40000000 -#define UDMA_CHCTL_DSTINC_32 0x80000000 -#define UDMA_CHCTL_DSTSIZE_MASK 0x30000000 -#define UDMA_CHCTL_DSTSIZE_8 0x00000000 -#define UDMA_CHCTL_DSTSIZE_16 0x10000000 -#define UDMA_CHCTL_DSTSIZE_32 0x20000000 -#define UDMA_CHCTL_SRCINC_MASK 0x0C000000 -#define UDMA_CHCTL_SRCINC_0 0x0C000000 -#define UDMA_CHCTL_SRCINC_8 0x00000000 -#define UDMA_CHCTL_SRCINC_16 0x04000000 -#define UDMA_CHCTL_SRCINC_32 0x08000000 -#define UDMA_CHCTL_SRCSIZE_MASK 0x03000000 -#define UDMA_CHCTL_SRCSIZE_8 0x00000000 -#define UDMA_CHCTL_SRCSIZE_16 0x01000000 -#define UDMA_CHCTL_SRCSIZE_32 0x02000000 -#define UDMA_CHCTL_ARBSIZE_MASK 0x0003C000 -#define UDMA_CHCTL_ARBSIZE_1 0x00000000 -#define UDMA_CHCTL_ARBSIZE_2 0x00004000 -#define UDMA_CHCTL_ARBSIZE_4 0x00008000 -#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 -#define UDMA_CHCTL_ARBSIZE_16 0x00010000 -#define UDMA_CHCTL_ARBSIZE_32 0x00014000 -#define UDMA_CHCTL_ARBSIZE_64 0x00018000 -#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 -#define UDMA_CHCTL_ARBSIZE_256 0x00020000 -#define UDMA_CHCTL_ARBSIZE_512 0x00024000 -#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 -#define UDMA_CHCTL_XFERSIZE_MASK 0x00003FF0 -#define UDMA_CHCTL_XFERSIZE(n) ((n-1) << 4) -#define UDMA_CHCTL_NXTUSEBURST 0x00000008 -#define UDMA_CHCTL_XFERMODE_MASK 0x00000007 -#define UDMA_CHCTL_XFERMODE_STOP 0x00000000 -#define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 -#define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 -#define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 -#define UDMA_CHCTL_XFERMODE_MSG 0x00000004 -#define UDMA_CHCTL_XFERMODE_AMSG 0x00000005 -#define UDMA_CHCTL_XFERMODE_PSG 0x00000006 -#define UDMA_CHCTL_XFERMODE_APSG 0x00000007 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief UDMA software interrupt priority level setting. - */ -#if !defined(TIVA_UDMA_SW_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_UDMA_SW_IRQ_PRIORITY 5 -#endif - -/** - * @brief UDMA error interrupt priority level setting. - */ -#if !defined(TIVA_UDMA_ERR_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_UDMA_ERR_IRQ_PRIORITY 5 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief A structure that defines an entry in the channel control table. - * @note These fields are used by the uDMA controller and normally it is not - * necessary for software to directly read or write fields in the - * table. - */ -typedef struct __attribute__((packed)) -{ - /** - * @brief The ending source address of the data transfer. - */ - volatile void *srcendp; - /** - * @brief The ending destination address of the data transfer. - */ - volatile void *dstendp; - /** - * @brief The channel control mode. - */ - volatile uint32_t chctl; - /** - * @brief An unused location. - */ - volatile uint32_t unused; -} tiva_udma_table_entry_t; - -typedef struct __attribute__((packed, aligned(1024))) -{ - union { - struct { - tiva_udma_table_entry_t primary[32]; - tiva_udma_table_entry_t alternate[32]; - }; - uint8_t raw[1024]; - }; -} udmaControlTable_t ; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -#define dmaChannelEnable(dmach) {\ - UDMA->ENASET = (1 << dmach);\ -} - -#define dmaChannelDisable(dmach) { \ - UDMA->ENACLR = (1 << dmach); \ -} - -#define dmaChannelPrimary(dmach) {\ - UDMA->ALTCLR = (1 << dmach); \ -} - -#define dmaChannelAlternate(dmach) { \ - UDMA->ALTSET = (1 << dmach); \ -} - -#define dmaChannelSingleBurst(dmach) { \ - UDMA->USEBURSTCLR = (1 << dmach); \ -} - -#define dmaChannelBurstOnly(dmach) { \ - UDMA->USEBURSTSET = (1 << dmach); \ -} - -#define dmaChannelPriorityHigh(dmach) { \ - UDMA->PRIOSET = (1 << dmach); \ -} - -#define dmaChannelPriorityDefault(dmach) { \ - UDMA->PRIOCLR = (1 << dmach); \ -} - -#define dmaChannelEnableRequest(dmach) {\ - UDMA->REQMASKCLR = (1 << dmach); \ -} - -#define dmaChannelDisableRequest(dmach) {\ - UDMA->REQMASKSET = (1 << dmach); \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern udmaControlTable_t udmaControlTable; - -#ifdef __cplusplus -extern "C" { -#endif - void udmaInit(void); - bool udmaChannelAllocate(uint8_t dmach); - void udmaChannelRelease(uint8_t dmach); -#ifdef __cplusplus -} -#endif - -#endif /* TIVA_UDMA_H_ */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/hal_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/hal_lld.c deleted file mode 100644 index ddcddb3..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/hal_lld.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/TM4C123x/hal_lld.c - * @brief TM4C123x HAL Driver subsystem low level driver source. - * - * @addtogroup HAL - * @{ - */ - -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - * - * @notapi - */ -void hal_lld_init(void) -{ -} - -/** - * @brief TM4C123x clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h and - * @p mcuconf.h. - * @note This function should be invoked just after the system reset. - * - * @special - */ -void tiva_clock_init(void) -{ - uint32_t rcc, rcc2, i; - - /* 1. Bypass the PLL and system clock divider by setting the BYPASS bit and - * clearing the USESYSDIV bit in the RCC register, thereby configuring the - * microcontroller to run off a "raw" clock source and allowing for the new - * PLL configuration to be validated before switching the system clock to the - * PLL. */ - /* read */ - - rcc = SYSCTL->RCC; - rcc2 = SYSCTL->RCC2; - - /* modify */ - rcc |= TIVA_RCC_BYPASS; - rcc &= ~TIVA_RCC_USESYSDIV; - rcc2 |= TIVA_RCC2_BYPASS2 | TIVA_RCC2_USERCC2; - - /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; - - /* 2 Select the crystal value (XTAL) and oscillator source (OSCSRC), and - * clear the PWRDN bit in RCC and RCC2. Setting the XTAL field automatically - * pulls valid PLL configuration data for the appropriate crystal, and - * clearing the PWRDN bit powers and enables the PLL and its output. */ - /* modify */ - rcc &= ~(TIVA_RCC_OSCSRC_MASK | TIVA_RCC_XTAL_MASK | TIVA_RCC_PWRDN | TIVA_RCC_MOSCDIS); - rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (TIVA_RCC_XTAL_MASK | TIVA_RCC_OSCSRC_MASK | TIVA_RCC_MOSCDIS)); - rcc2 &= ~(TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_PWRDN2); - rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_DIV400)); - - /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; - for(i = 100000; i; i--); - - /* 3. Select the desired system divider (SYSDIV) in RCC and RCC2 and set the - * USESYSDIV bit in RCC. The SYSDIV field determines the system frequency for - * the microcontroller. */ - /* modify */ - rcc &= ~TIVA_RCC_SYSDIV_MASK; - rcc |= (TIVA_SYSDIV & TIVA_RCC_SYSDIV_MASK) | TIVA_USESYSDIV; - rcc2 &= ~(TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB); - rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB)); - - /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; - - /* 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw - * Interrupt Status (RIS) register. */ - while ((SYSCTL->RIS & SYSCTL_RIS_PLLLRIS) == 0); - - /* 5. Enable use of the PLL by clearing the BYPASS bit in RCC and RCC2. */ - rcc &= ~TIVA_RCC_BYPASS; - rcc2 &= ~TIVA_RCC2_BYPASS2; - rcc |= (TIVA_BYPASS_VALUE << 11); - rcc2 |= (TIVA_BYPASS_VALUE << 11); - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; - -#if HAL_USE_PWM - SYSCTL->RCC |= TIVA_PWM_FIELDS; -#endif - -#if defined(TIVA_UDMA_REQUIRED) - udmaInit(); -#endif -} - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/hal_lld.h deleted file mode 100644 index ec81806..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/hal_lld.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Tiva/TM4C123x/hal_lld.h - * @brief TM4C123x HAL subsystem low level driver header. - * @pre This module requires the following macros to be defined in the - * @p board.h file: - * - TODO: add required macros - * - * @addtogroup HAL - * @{ - */ - -#ifndef HAL_LLD_H -#define HAL_LLD_H - -#include "tiva_registry.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Platform identification - * @{ - */ - -#define PLATFORM_NAME "Tiva C Series TM4C123x" - -/** - * @} - */ - -/** - * @name RCC register bits definitions - * @{ - */ - -#define TIVA_RCC_MOSCDIS (0x01 << 0) - -#define TIVA_RCC_OSCSRC_MASK (0x03 << 4) -#define TIVA_RCC_OSCSRC_MOSC (0x00 << 4) -#define TIVA_RCC_OSCSRC_PIOSC (0x01 << 4) -#define TIVA_RCC_OSCSRC_PIOSC_4 (0x02 << 4) -#define TIVA_RCC_OSCSRC_LFIOSC (0x03 << 4) - -#define TIVA_RCC_XTAL_MASK (0x1f << 6) -#define TIVA_RCC_XTAL_4000000 (0x06 << 6) -#define TIVA_RCC_XTAL_4096000 (0x07 << 6) -#define TIVA_RCC_XTAL_4915200 (0x08 << 6) -#define TIVA_RCC_XTAL_5000000 (0x09 << 6) -#define TIVA_RCC_XTAL_5120000 (0x0a << 6) -#define TIVA_RCC_XTAL_6000000 (0x0b << 6) -#define TIVA_RCC_XTAL_6144000 (0x0c << 6) -#define TIVA_RCC_XTAL_7372800 (0x0d << 6) -#define TIVA_RCC_XTAL_8000000 (0x0e << 6) -#define TIVA_RCC_XTAL_8192000 (0x0f << 6) -#define TIVA_RCC_XTAL_10000000 (0x10 << 6) -#define TIVA_RCC_XTAL_12000000 (0x11 << 6) -#define TIVA_RCC_XTAL_12288000 (0x12 << 6) -#define TIVA_RCC_XTAL_13560000 (0x13 << 6) -#define TIVA_RCC_XTAL_14318180 (0x14 << 6) -#define TIVA_RCC_XTAL_16000000 (0x15 << 6) -#define TIVA_RCC_XTAL_16384000 (0x16 << 6) -#define TIVA_RCC_XTAL_18000000 (0x17 << 6) -#define TIVA_RCC_XTAL_20000000 (0x18 << 6) -#define TIVA_RCC_XTAL_24000000 (0x19 << 6) -#define TIVA_RCC_XTAL_25000000 (0x1a << 6) - -#define TIVA_RCC_BYPASS (1 << 11) - -#define TIVA_RCC_PWRDN (1 << 13) - -#define TIVA_RCC_PWMDIV_MASK (0x07 << 17) -#define TIVA_RCC_PWMDIV_2 (0x00 << 17) -#define TIVA_RCC_PWMDIV_4 (0x01 << 17) -#define TIVA_RCC_PWMDIV_8 (0x02 << 17) -#define TIVA_RCC_PWMDIV_16 (0x03 << 17) -#define TIVA_RCC_PWMDIV_32 (0x04 << 17) -#define TIVA_RCC_PWMDIV_64 (0x07 << 17) - -#define TIVA_RCC_USEPWMDIV (1 << 20) - -#define TIVA_RCC_USESYSDIV (1 << 22) - -#define TIVA_RCC_SYSDIV_MASK (0x0f << 23) -#define TIVA_RCC_SYSDIV_1 (0x00 << 23) -#define TIVA_RCC_SYSDIV_2 (0x01 << 23) -#define TIVA_RCC_SYSDIV_3 (0x02 << 23) -#define TIVA_RCC_SYSDIV_4 (0x03 << 23) -#define TIVA_RCC_SYSDIV_5 (0x04 << 23) -#define TIVA_RCC_SYSDIV_6 (0x05 << 23) -#define TIVA_RCC_SYSDIV_7 (0x06 << 23) -#define TIVA_RCC_SYSDIV_8 (0x07 << 23) -#define TIVA_RCC_SYSDIV_9 (0x08 << 23) -#define TIVA_RCC_SYSDIV_10 (0x09 << 23) -#define TIVA_RCC_SYSDIV_11 (0x0a << 23) -#define TIVA_RCC_SYSDIV_12 (0x0b << 23) -#define TIVA_RCC_SYSDIV_13 (0x0c << 23) -#define TIVA_RCC_SYSDIV_14 (0x0d << 23) -#define TIVA_RCC_SYSDIV_15 (0x0e << 23) -#define TIVA_RCC_SYSDIV_16 (0x0f << 23) - -#define TIVA_RCC_ACG (1 << 27) - -/** - * @} - */ - -/** - * @name RCC2 register bits definitions - * @{ - */ - -#define TIVA_RCC2_OSCSRC2_MASK (0x07 << 4) -#define TIVA_RCC2_OSCSRC2_MOSC (0x00 << 4) -#define TIVA_RCC2_OSCSRC2_PIOSC (0x01 << 4) -#define TIVA_RCC2_OSCSRC2_PIOSC_4 (0x02 << 4) -#define TIVA_RCC2_OSCSRC2_LFIOSC (0x03 << 4) -#define TIVA_RCC2_OSCSRC2_32768 (0x07 << 4) - -#define TIVA_RCC2_BYPASS2 (1 << 11) - -#define TIVA_RCC2_PWRDN2 (1 << 13) - -#define TIVA_RCC2_USBPWRDN (1 << 14) - -#define TIVA_RCC2_SYSDIV2LSB (1 << 22) - -#define TIVA_RCC2_SYSDIV2_MASK (0x3f << 23) - -#define TIVA_RCC2_DIV400 (1 << 30) - -#define TIVA_RCC2_USERCC2 (1 << 31) - -/** - * @} - */ - -/** - * @name RIS register bits definitions - * @{ - */ - -#define SYSCTL_RIS_PLLLRIS (1 << 6) - -/** - * @} - */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -#if !defined(TIVA_OSCSRC) -#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC -#endif - -#if !defined(TIVA_MOSC_ENABLE) -#define TIVA_MOSC_ENABLE TRUE -#endif - -#if !defined(TIVA_DIV400_VALUE) -#define TIVA_DIV400_VALUE 1 -#endif - -#if !defined(TIVA_SYSDIV_VALUE) -#define TIVA_SYSDIV_VALUE 2 -#endif - -#if !defined(TIVA_USESYSDIV_ENABLE) -#define TIVA_USESYSDIV_ENABLE FALSE -#endif - -#if !defined(TIVA_SYSDIV2LSB_ENABLE) -#define TIVA_SYSDIV2LSB_ENABLE FALSE -#endif - -#if !defined(TIVA_BYPASS_VALUE) -#define TIVA_BYPASS_VALUE 0 -#endif - -/** - * @} - */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* - * Configuration-related checks. - */ -#if !defined(TM4C123x_MCUCONF) -#error "Using a wrong mcuconf.h file, TM4C123x_MCUCONF not defined" -#endif - -/* - * Oscillator-related checks. - */ -#if !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_MOSC) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_PIOSC) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_PIOSC_4) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_LFIOSC) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_32768) -#error "Invalid value for TIVA_OSCSRC defined" -#endif - -#if TIVA_XTAL_VALUE == 4000000 -#define TIVA_XTAL_ (0x06 << 6) -#elif TIVA_XTAL_VALUE == 4096000 -#define TIVA_XTAL_ (0x07 << 6) -#elif TIVA_XTAL_VALUE == 4915200 -#define TIVA_XTAL_ (0x08 << 6) -#elif TIVA_XTAL_VALUE == 5000000 -#define TIVA_XTAL_ (0x09 << 6) -#elif TIVA_XTAL_VALUE == 5120000 -#define TIVA_XTAL_ (0x0a << 6) -#elif TIVA_XTAL_VALUE == 6000000 -#define TIVA_XTAL_ (0x0b << 6) -#elif TIVA_XTAL_VALUE == 6144000 -#define TIVA_XTAL_ (0x0c << 6) -#elif TIVA_XTAL_VALUE == 7372800 -#define TIVA_XTAL_ (0x0d << 6) -#elif TIVA_XTAL_VALUE == 8000000 -#define TIVA_XTAL_ (0x0e << 6) -#elif TIVA_XTAL_VALUE == 8192000 -#define TIVA_XTAL_ (0x0f << 6) -#elif TIVA_XTAL_VALUE == 10000000 -#define TIVA_XTAL_ (0x10 << 6) -#elif TIVA_XTAL_VALUE == 12000000 -#define TIVA_XTAL_ (0x11 << 6) -#elif TIVA_XTAL_VALUE == 12288000 -#define TIVA_XTAL_ (0x12 << 6) -#elif TIVA_XTAL_VALUE == 13560000 -#define TIVA_XTAL_ (0x13 << 6) -#elif TIVA_XTAL_VALUE == 14318180 -#define TIVA_XTAL_ (0x14 << 6) -#elif TIVA_XTAL_VALUE == 16000000 -#define TIVA_XTAL_ (0x15 << 6) -#elif TIVA_XTAL_VALUE == 16384000 -#define TIVA_XTAL_ (0x16 << 6) -#elif TIVA_XTAL_VALUE == 18000000 -#define TIVA_XTAL_ (0x17 << 6) -#elif TIVA_XTAL_VALUE == 20000000 -#define TIVA_XTAL_ (0x18 << 6) -#elif TIVA_XTAL_VALUE == 24000000 -#define TIVA_XTAL_ (0x19 << 6) -#elif TIVA_XTAL_VALUE == 25000000 -#define TIVA_XTAL_ (0x1a << 6) -#else -#error "Invalid value for TIVA_XTAL_VALUE defined" -#endif - -#if TIVA_MOSC_ENABLE == TRUE -#define TIVA_MOSCDIS (0 << 0) -#define TIVA_XTAL TIVA_XTAL_ -#elif TIVA_MOSC_ENABLE == FALSE -#define TIVA_MOSCDIS (1 << 0) -#define TIVA_XTAL 0 -#else -#error "Invalid value for TIVA_MOSC_ENABLE defined" -#endif - -#if TIVA_DIV400_VALUE == 1 -#define TIVA_DIV400 (1 << 30) -#elif TIVA_DIV400_VALUE == 0 -#define TIVA_DIV400 (0 << 30) -#else -#error "Invalid value for TIVA_DIV400_VALUE defined" -#endif - -#if (TIVA_SYSDIV_VALUE >= 0x02) && (TIVA_SYSDIV_VALUE <= 0x3f) -#define TIVA_SYSDIV (TIVA_SYSDIV_VALUE << 23) -#define TIVA_SYSDIV2 (TIVA_SYSDIV_VALUE << 23) -#else -#error "Invalid value for TIVA_SYSDIV_VALUE defined" -#endif - -#if TIVA_USESYSDIV_ENABLE == TRUE -#define TIVA_USESYSDIV (1 << 22) -#elif TIVA_USESYSDIV_ENABLE == FALSE -#define TIVA_USESYSDIV (0 << 22) -#else -#error "Invalid value for TIVA_USESYSDIV_ENABLE defined" -#endif - -#if TIVA_SYSDIV2LSB_ENABLE == TRUE -#define TIVA_SYSDIV2LSB (1 << 22) -#elif TIVA_SYSDIV2LSB_ENABLE == FALSE -#define TIVA_SYSDIV2LSB (0 << 22) -#else -#error "Invalid value for TIVA_SYSDIV2LSB_ENABLE defined" -#endif - -#if TIVA_BYPASS_VALUE == 1 -#define TIVA_SRC 16000000 -#elif TIVA_BYPASS_VALUE == 0 -#define TIVA_SRC (200000000 + (TIVA_DIV400_VALUE * 200000000)) -#else -#error "Invalid value for TIVA_BYPASS_VALUE defined" -#endif - -#if (TIVA_OSCSRC == TIVA_RCC_OSCSRC_MOSC) && (TIVA_MOSC_ENABLE == FALSE) -#error "Main Oscillator selected but not enabled" -#endif - -/* - * System Clock calculation - */ -#define TIVA_SYSCLK (TIVA_SRC / (((TIVA_SYSDIV_VALUE << TIVA_DIV400_VALUE /*& TIVA_BYPASS_VALUE*/) | (TIVA_SYSDIV2LSB >> 22)) + 1)) - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* Various helpers.*/ -#include "nvic.h" -#include "tiva_isr.h" -#include "tiva_udma.h" - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void tiva_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_LLD_H */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/platform.mk b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/platform.mk deleted file mode 100644 index 0abafcc..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/platform.mk +++ /dev/null @@ -1,18 +0,0 @@ -# List of all the TM4C123x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_st_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_serial_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_i2c_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_gpt_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pwm_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_spi_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/tiva_udma.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_ext_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_wdg_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/tiva_isr.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/tiva_isr.h deleted file mode 100644 index b380e46..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/tiva_isr.h +++ /dev/null @@ -1,650 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TM4C123x/tiva_isr.h - * @brief TM4C123x ISR remapper driver header. - * - * @addtogroup TM4C123x_ISR - * @{ - */ - -#ifndef _TIVA_ISR_H_ -#define _TIVA_ISR_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name ISR names and numbers remapping - * @{ - */ - -/* UDMA units.*/ -#define TIVA_UDMA_SW_HANDLER VectorF8 -#define TIVA_UDMA_ERR_HANDLER VectorFC - -#define TIVA_UDMA_SW_NUMBER 46 -#define TIVA_UDMA_ERR_NUMBER 47 - -/* GPIO units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) \ - || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) || defined(TM4C1236D5PM) \ - || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) -#define TIVA_GPIOA_HANDLER Vector40 -#define TIVA_GPIOB_HANDLER Vector44 -#define TIVA_GPIOC_HANDLER Vector48 -#define TIVA_GPIOD_HANDLER Vector4C -#define TIVA_GPIOE_HANDLER Vector50 -#define TIVA_GPIOF_HANDLER VectorB8 -#define TIVA_GPIOG_HANDLER VectorBC - -#define TIVA_GPIOA_NUMBER 0 -#define TIVA_GPIOB_NUMBER 1 -#define TIVA_GPIOC_NUMBER 2 -#define TIVA_GPIOD_NUMBER 3 -#define TIVA_GPIOE_NUMBER 4 -#define TIVA_GPIOF_NUMBER 30 -#define TIVA_GPIOG_NUMBER 31 -#endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) -#define TIVA_GPIOA_HANDLER Vector40 -#define TIVA_GPIOB_HANDLER Vector44 -#define TIVA_GPIOC_HANDLER Vector48 -#define TIVA_GPIOD_HANDLER Vector4C -#define TIVA_GPIOE_HANDLER Vector50 -#define TIVA_GPIOF_HANDLER VectorB8 - -#define TIVA_GPIOA_NUMBER 0 -#define TIVA_GPIOB_NUMBER 1 -#define TIVA_GPIOC_NUMBER 2 -#define TIVA_GPIOD_NUMBER 3 -#define TIVA_GPIOE_NUMBER 4 -#define TIVA_GPIOF_NUMBER 30 -#endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ) \ - || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PZ) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PZ) -#define TIVA_GPIOA_HANDLER Vector40 -#define TIVA_GPIOB_HANDLER Vector44 -#define TIVA_GPIOC_HANDLER Vector48 -#define TIVA_GPIOD_HANDLER Vector4C -#define TIVA_GPIOE_HANDLER Vector50 -#define TIVA_GPIOF_HANDLER VectorB8 -#define TIVA_GPIOG_HANDLER VectorBC -#define TIVA_GPIOH_HANDLER VectorC0 -#define TIVA_GPIOJ_HANDLER Vector118 -#define TIVA_GPIOK_HANDLER Vector11C -#define TIVA_GPIOL_HANDLER Vector120 - -#define TIVA_GPIOA_NUMBER 0 -#define TIVA_GPIOB_NUMBER 1 -#define TIVA_GPIOC_NUMBER 2 -#define TIVA_GPIOD_NUMBER 3 -#define TIVA_GPIOE_NUMBER 4 -#define TIVA_GPIOF_NUMBER 30 -#define TIVA_GPIOG_NUMBER 31 -#define TIVA_GPIOH_NUMBER 32 -#define TIVA_GPIOJ_NUMBER 54 -#define TIVA_GPIOK_NUMBER 55 -#define TIVA_GPIOL_NUMBER 56 -#endif -#if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\ - || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE) -#define TIVA_GPIOA_HANDLER Vector40 -#define TIVA_GPIOB_HANDLER Vector44 -#define TIVA_GPIOC_HANDLER Vector48 -#define TIVA_GPIOD_HANDLER Vector4C -#define TIVA_GPIOE_HANDLER Vector50 -#define TIVA_GPIOF_HANDLER VectorB8 -#define TIVA_GPIOG_HANDLER VectorBC -#define TIVA_GPIOH_HANDLER VectorC0 -#define TIVA_GPIOJ_HANDLER Vector118 -#define TIVA_GPIOK_HANDLER Vector11C -#define TIVA_GPIOL_HANDLER Vector120 -#define TIVA_GPIOM_HANDLER Vector1FC -#define TIVA_GPION_HANDLER Vector200 -#define TIVA_GPIOP0_HANDLER Vector210 -#define TIVA_GPIOP1_HANDLER Vector214 -#define TIVA_GPIOP2_HANDLER Vector218 -#define TIVA_GPIOP3_HANDLER Vector21C -#define TIVA_GPIOP4_HANDLER Vector220 -#define TIVA_GPIOP5_HANDLER Vector224 -#define TIVA_GPIOP6_HANDLER Vector228 -#define TIVA_GPIOP7_HANDLER Vector22C - -#define TIVA_GPIOA_NUMBER 0 -#define TIVA_GPIOB_NUMBER 1 -#define TIVA_GPIOC_NUMBER 2 -#define TIVA_GPIOD_NUMBER 3 -#define TIVA_GPIOE_NUMBER 4 -#define TIVA_GPIOF_NUMBER 30 -#define TIVA_GPIOG_NUMBER 31 -#define TIVA_GPIOH_NUMBER 32 -#define TIVA_GPIOJ_NUMBER 54 -#define TIVA_GPIOK_NUMBER 55 -#define TIVA_GPIOL_NUMBER 56 -#define TIVA_GPIOM_NUMBER 111 -#define TIVA_GPION_NUMBER 112 -#define TIVA_GPIOP0_NUMBER 116 -#define TIVA_GPIOP1_NUMBER 117 -#define TIVA_GPIOP2_NUMBER 118 -#define TIVA_GPIOP3_NUMBER 119 -#define TIVA_GPIOP4_NUMBER 120 -#define TIVA_GPIOP5_NUMBER 121 -#define TIVA_GPIOP6_NUMBER 122 -#define TIVA_GPIOP7_NUMBER 123 -#endif -#if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_GPIOA_HANDLER Vector40 -#define TIVA_GPIOB_HANDLER Vector44 -#define TIVA_GPIOC_HANDLER Vector48 -#define TIVA_GPIOD_HANDLER Vector4C -#define TIVA_GPIOE_HANDLER Vector50 -#define TIVA_GPIOF_HANDLER VectorB8 -#define TIVA_GPIOG_HANDLER VectorBC -#define TIVA_GPIOH_HANDLER VectorC0 -#define TIVA_GPIOJ_HANDLER Vector118 -#define TIVA_GPIOK_HANDLER Vector11C -#define TIVA_GPIOL_HANDLER Vector120 -#define TIVA_GPIOM_HANDLER Vector1FC -#define TIVA_GPION_HANDLER Vector200 -#define TIVA_GPIOP0_HANDLER Vector210 -#define TIVA_GPIOP1_HANDLER Vector214 -#define TIVA_GPIOP2_HANDLER Vector218 -#define TIVA_GPIOP3_HANDLER Vector21C -#define TIVA_GPIOP4_HANDLER Vector220 -#define TIVA_GPIOP5_HANDLER Vector224 -#define TIVA_GPIOP6_HANDLER Vector228 -#define TIVA_GPIOP7_HANDLER Vector22C -#define TIVA_GPIOQ0_HANDLER Vector230 -#define TIVA_GPIOQ1_HANDLER Vector234 -#define TIVA_GPIOQ2_HANDLER Vector238 -#define TIVA_GPIOQ3_HANDLER Vector23C -#define TIVA_GPIOQ4_HANDLER Vector240 -#define TIVA_GPIOQ5_HANDLER Vector244 -#define TIVA_GPIOQ6_HANDLER Vector248 -#define TIVA_GPIOQ7_HANDLER Vector24C - -#define TIVA_GPIOA_NUMBER 0 -#define TIVA_GPIOB_NUMBER 1 -#define TIVA_GPIOC_NUMBER 2 -#define TIVA_GPIOD_NUMBER 3 -#define TIVA_GPIOE_NUMBER 4 -#define TIVA_GPIOF_NUMBER 30 -#define TIVA_GPIOG_NUMBER 31 -#define TIVA_GPIOH_NUMBER 32 -#define TIVA_GPIOJ_NUMBER 54 -#define TIVA_GPIOK_NUMBER 55 -#define TIVA_GPIOL_NUMBER 56 -#define TIVA_GPIOM_NUMBER 111 -#define TIVA_GPION_NUMBER 112 -#define TIVA_GPIOP0_NUMBER 116 -#define TIVA_GPIOP1_NUMBER 117 -#define TIVA_GPIOP2_NUMBER 118 -#define TIVA_GPIOP3_NUMBER 119 -#define TIVA_GPIOP4_NUMBER 120 -#define TIVA_GPIOP5_NUMBER 121 -#define TIVA_GPIOP6_NUMBER 122 -#define TIVA_GPIOP7_NUMBER 123 -#define TIVA_GPIOQ0_NUMBER 124 -#define TIVA_GPIOQ1_NUMBER 125 -#define TIVA_GPIOQ2_NUMBER 126 -#define TIVA_GPIOQ3_NUMBER 127 -#define TIVA_GPIOQ4_NUMBER 128 -#define TIVA_GPIOQ5_NUMBER 129 -#define TIVA_GPIOQ6_NUMBER 130 -#define TIVA_GPIOQ7_NUMBER 131 -#endif - -/* GPTM units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_GPT0A_HANDLER Vector8C -#define TIVA_GPT0B_HANDLER Vector90 -#define TIVA_GPT1A_HANDLER Vector94 -#define TIVA_GPT1B_HANDLER Vector98 -#define TIVA_GPT2A_HANDLER Vector9C -#define TIVA_GPT2B_HANDLER VectorA0 -#define TIVA_GPT3A_HANDLER VectorCC -#define TIVA_GPT3B_HANDLER VectorD0 -#define TIVA_GPT4A_HANDLER Vector158 -#define TIVA_GPT4B_HANDLER Vector15C -#define TIVA_GPT5A_HANDLER Vector1B0 -#define TIVA_GPT5B_HANDLER Vector1B4 - -#define TIVA_GPT0A_NUMBER 19 -#define TIVA_GPT0B_NUMBER 20 -#define TIVA_GPT1A_NUMBER 21 -#define TIVA_GPT1B_NUMBER 22 -#define TIVA_GPT2A_NUMBER 23 -#define TIVA_GPT2B_NUMBER 24 -#define TIVA_GPT3A_NUMBER 35 -#define TIVA_GPT3B_NUMBER 36 -#define TIVA_GPT4A_NUMBER 70 -#define TIVA_GPT4B_NUMBER 71 -#define TIVA_GPT5A_NUMBER 92 -#define TIVA_GPT5B_NUMBER 93 - -#define TIVA_WGPT0A_HANDLER Vector1B8 -#define TIVA_WGPT0B_HANDLER Vector1BC -#define TIVA_WGPT1A_HANDLER Vector1C0 -#define TIVA_WGPT1B_HANDLER Vector1C4 -#define TIVA_WGPT2A_HANDLER Vector1C8 -#define TIVA_WGPT2B_HANDLER Vector1CC -#define TIVA_WGPT3A_HANDLER Vector1D0 -#define TIVA_WGPT3B_HANDLER Vector1D4 -#define TIVA_WGPT4A_HANDLER Vector1D8 -#define TIVA_WGPT4B_HANDLER Vector1DC -#define TIVA_WGPT5A_HANDLER Vector1E0 -#define TIVA_WGPT5B_HANDLER Vector1E4 - -#define TIVA_WGPT0A_NUMBER 94 -#define TIVA_WGPT0B_NUMBER 95 -#define TIVA_WGPT1A_NUMBER 96 -#define TIVA_WGPT1B_NUMBER 97 -#define TIVA_WGPT2A_NUMBER 98 -#define TIVA_WGPT2B_NUMBER 99 -#define TIVA_WGPT3A_NUMBER 100 -#define TIVA_WGPT3B_NUMBER 101 -#define TIVA_WGPT4A_NUMBER 102 -#define TIVA_WGPT4B_NUMBER 103 -#define TIVA_WGPT5A_NUMBER 104 -#define TIVA_WGPT5B_NUMBER 105 -#endif - -/* WDT units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_WDT_HANDLER Vector88 - -#define TIVA_WDT_NUMBER 18 -#endif - -/* ADC units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_ADC0_SEQ0_HANDLER Vector78 -#define TIVA_ADC0_SEQ1_HANDLER Vector7C -#define TIVA_ADC0_SEQ2_HANDLER Vector80 -#define TIVA_ADC0_SEQ3_HANDLER Vector84 -#define TIVA_ADC1_SEQ0_HANDLER Vector100 -#define TIVA_ADC1_SEQ1_HANDLER Vector104 -#define TIVA_ADC1_SEQ2_HANDLER Vector108 -#define TIVA_ADC1_SEQ3_HANDLER Vector10C - -#define TIVA_ADC0_SEQ0_NUMBER 14 -#define TIVA_ADC0_SEQ1_NUMBER 15 -#define TIVA_ADC0_SEQ2_NUMBER 16 -#define TIVA_ADC0_SEQ3_NUMBER 17 -#define TIVA_ADC1_SEQ0_NUMBER 48 -#define TIVA_ADC1_SEQ1_NUMBER 49 -#define TIVA_ADC1_SEQ2_NUMBER 50 -#define TIVA_ADC1_SEQ3_NUMBER 51 -#endif - -/* UART units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_UART0_HANDLER Vector54 -#define TIVA_UART1_HANDLER Vector58 -#define TIVA_UART2_HANDLER VectorC4 -#define TIVA_UART3_HANDLER Vector12C -#define TIVA_UART4_HANDLER Vector130 -#define TIVA_UART5_HANDLER Vector134 -#define TIVA_UART6_HANDLER Vector138 -#define TIVA_UART7_HANDLER Vector13C - -#define TIVA_UART0_NUMBER 5 -#define TIVA_UART1_NUMBER 6 -#define TIVA_UART2_NUMBER 33 -#define TIVA_UART3_NUMBER 59 -#define TIVA_UART4_NUMBER 60 -#define TIVA_UART5_NUMBER 61 -#define TIVA_UART6_NUMBER 62 -#define TIVA_UART7_NUMBER 63 -#endif - -/* SPI units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_SSI0_HANDLER Vector5C -#define TIVA_SSI1_HANDLER VectorC8 -#define TIVA_SSI2_HANDLER Vector124 -#define TIVA_SSI3_HANDLER Vector128 - -#define TIVA_SSI0_NUMBER 7 -#define TIVA_SSI1_NUMBER 34 -#define TIVA_SSI2_NUMBER 57 -#define TIVA_SSI3_NUMBER 58 -#endif - -/* I2C units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PZ) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PGE) \ - || defined(TM4C1233H6PZ) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) \ - || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_I2C0_HANDLER Vector60 -#define TIVA_I2C1_HANDLER VectorD4 -#define TIVA_I2C2_HANDLER Vector150 -#define TIVA_I2C3_HANDLER Vector154 -#define TIVA_I2C4_HANDLER Vector1F4 -#define TIVA_I2C5_HANDLER Vector1F8 - -#define TIVA_I2C0_NUMBER 8 -#define TIVA_I2C1_NUMBER 37 -#define TIVA_I2C2_NUMBER 68 -#define TIVA_I2C3_NUMBER 69 -#define TIVA_I2C4_NUMBER 109 -#define TIVA_I2C5_NUMBER 110 -#endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) -#define TIVA_I2C0_HANDLER Vector60 -#define TIVA_I2C1_HANDLER VectorD4 -#define TIVA_I2C2_HANDLER Vector150 -#define TIVA_I2C3_HANDLER Vector154 - -#define TIVA_I2C0_NUMBER 8 -#define TIVA_I2C1_NUMBER 37 -#define TIVA_I2C2_NUMBER 68 -#define TIVA_I2C3_NUMBER 69 -#endif - -/* CAN units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) -#define TIVA_CAN0_HANDLER VectorDC - -#define TIVA_CAN0_NUMBER 39 -#endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_CAN0_HANDLER VectorDC -#define TIVA_CAN1_HANDLER VectorE0 - -#define TIVA_CAN0_NUMBER 39 -#define TIVA_CAN1_NUMBER 40 -#endif - -/* USB units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) -/* No interrupt handler and number.*/ -#endif -#if defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) \ - || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) \ - || defined(TM4C123GH5ZXR) -#define TIVA_USB0_HANDLER VectorF0 - -#define TIVA_USB0_NUMBER 44 -#endif - -/* AC units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231E6PM) || defined(TM4C1231H6PM) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) || defined(TM4C1233E6PM) \ - || defined(TM4C1233H6PM) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PM) || defined(TM4C1237E6PM) \ - || defined(TM4C1237H6PM) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BH6PM) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) -#define TIVA_AC0_HANDLER VectorA4 -#define TIVA_AC1_HANDLER VectorA8 - -#define TIVA_AC0_NUMBER 25 -#define TIVA_AC1_NUMBER 26 -#endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PGE) \ - || defined(TM4C1231H6PZ) || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PZ) || defined(TM4C1237D5PZ) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PZ) \ - || defined(TM4C123BH6ZRB) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE)\ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_AC0_HANDLER VectorA4 -#define TIVA_AC1_HANDLER VectorA8 -#define TIVA_AC2_HANDLER VectorAC - -#define TIVA_AC0_NUMBER 25 -#define TIVA_AC1_NUMBER 26 -#define TIVA_AC2_NUMBER 27 -#endif - -/* PWM units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) -/* No interrupt handler and number.*/ -#endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_PWM0FAULT_HANDLER Vector64 -#define TIVA_PWM0GEN0_HANDLER Vector68 -#define TIVA_PWM0GEN1_HANDLER Vector6C -#define TIVA_PWM0GEN2_HANDLER Vector70 -#define TIVA_PWM0GEN3_HANDLER VectorF4 -#define TIVA_PWM1FAULT_HANDLER Vector268 -#define TIVA_PWM1GEN0_HANDLER Vector258 -#define TIVA_PWM1GEN1_HANDLER Vector25C -#define TIVA_PWM1GEN2_HANDLER Vector260 -#define TIVA_PWM1GEN3_HANDLER Vector264 - -#define TIVA_PWM0FAULT_NUMBER 9 -#define TIVA_PWM0GEN0_NUMBER 10 -#define TIVA_PWM0GEN1_NUMBER 11 -#define TIVA_PWM0GEN2_NUMBER 12 -#define TIVA_PWM0GEN3_NUMBER 45 -#define TIVA_PWM1FAULT_NUMBER 138 -#define TIVA_PWM1GEN0_NUMBER 134 -#define TIVA_PWM1GEN1_NUMBER 135 -#define TIVA_PWM1GEN2_NUMBER 136 -#define TIVA_PWM1GEN3_NUMBER 137 -#endif - -/* QEI units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) -/* No interrupt handler and number.*/ -#endif -#if defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_QEI0_HANLDER Vector74 -#define TIVA_QEI1_HANLDER VectorD8 - -#define TIVA_QEI0_NUMBER 13 -#define TIVA_QEI1_NUMBER 38 -#endif - -/** - * @} - */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#endif /* _TIVA_ISR_H_ */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/tiva_registry.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/tiva_registry.h deleted file mode 100644 index ac7a1d2..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/tiva_registry.h +++ /dev/null @@ -1,504 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TM4C123x/tiva_registry.h - * @brief TM4C123x capabilities registry. - * - * @addtogroup HAL - * @{ - */ - -#ifndef _TIVA_REGISTRY_H_ -#define _TIVA_REGISTRY_H_ - -/*===========================================================================*/ -/* Defined device check. */ -/*===========================================================================*/ - -#if !defined(TM4C1230C3PM) && !defined(TM4C1230D5PM) && \ - !defined(TM4C1230E6PM) && !defined(TM4C1230H6PM) && \ - !defined(TM4C1231C3PM) && !defined(TM4C1231D5PM) && \ - !defined(TM4C1231D5PZ) && !defined(TM4C1231E6PM) && \ - !defined(TM4C1231E6PZ) && !defined(TM4C1231H6PGE) && \ - !defined(TM4C1231H6PM) && !defined(TM4C1231H6PZ) && \ - !defined(TM4C1232C3PM) && !defined(TM4C1232D5PM) && \ - !defined(TM4C1232E6PM) && !defined(TM4C1232H6PM) && \ - !defined(TM4C1233C3PM) && !defined(TM4C1233D5PM) && \ - !defined(TM4C1233D5PZ) && !defined(TM4C1233E6PM) && \ - !defined(TM4C1233E6PZ) && !defined(TM4C1233H6PGE) && \ - !defined(TM4C1233H6PM) && !defined(TM4C1233H6PZ) && \ - !defined(TM4C1236D5PM) && !defined(TM4C1236E6PM) && \ - !defined(TM4C1236H6PM) && !defined(TM4C1237D5PM) && \ - !defined(TM4C1237D5PZ) && !defined(TM4C1237E6PM) && \ - !defined(TM4C1237E6PZ) && !defined(TM4C1237H6PGE) && \ - !defined(TM4C1237H6PM) && !defined(TM4C1237H6PZ) && \ - !defined(TM4C123AE6PM) && !defined(TM4C123AH6PM) && \ - !defined(TM4C123BE6PM) && !defined(TM4C123BE6PZ) && \ - !defined(TM4C123BH6PGE) && !defined(TM4C123BH6PM) && \ - !defined(TM4C123BH6PZ) && !defined(TM4C123BH6ZRB) && \ - !defined(TM4C123FE6PM) && !defined(TM4C123FH6PM) && \ - !defined(TM4C123GE6PM) && !defined(TM4C123GE6PZ) && \ - !defined(TM4C123GH6PGE) && !defined(TM4C123GH6PM) && \ - !defined(TM4C123GH6PZ) && !defined(TM4C123GH6ZRB) && \ - !defined(TM4C123GH5ZXR) -#error "No valid device defined." -#endif - -/** - * @brief Sub-family identifier. - */ -#if !defined(TM4C123x) || defined(__DOXYGEN__) -#define TM4C123x -#endif - -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -/** - * @name TM4C123x capabilities - * @{ - */ - -/* GPIO attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) \ - || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) || defined(TM4C1236D5PM) \ - || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) -#define TIVA_HAS_GPIOA TRUE -#define TIVA_HAS_GPIOB TRUE -#define TIVA_HAS_GPIOC TRUE -#define TIVA_HAS_GPIOD TRUE -#define TIVA_HAS_GPIOE TRUE -#define TIVA_HAS_GPIOF TRUE -#define TIVA_HAS_GPIOG TRUE -#define TIVA_HAS_GPIOH FALSE -#define TIVA_HAS_GPIOJ FALSE -#define TIVA_HAS_GPIOK FALSE -#define TIVA_HAS_GPIOL FALSE -#define TIVA_HAS_GPIOM FALSE -#define TIVA_HAS_GPION FALSE -#define TIVA_HAS_GPIOP FALSE -#define TIVA_HAS_GPIOQ FALSE -#define TIVA_HAS_GPIOR FALSE -#define TIVA_HAS_GPIOS FALSE -#define TIVA_HAS_GPIOT FALSE -#define TIVA_GPIO_PINS 56 -#endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) -#define TIVA_HAS_GPIOA TRUE -#define TIVA_HAS_GPIOB TRUE -#define TIVA_HAS_GPIOC TRUE -#define TIVA_HAS_GPIOD TRUE -#define TIVA_HAS_GPIOE TRUE -#define TIVA_HAS_GPIOF TRUE -#define TIVA_HAS_GPIOG FALSE -#define TIVA_HAS_GPIOH FALSE -#define TIVA_HAS_GPIOJ FALSE -#define TIVA_HAS_GPIOK FALSE -#define TIVA_HAS_GPIOL FALSE -#define TIVA_HAS_GPIOM FALSE -#define TIVA_HAS_GPION FALSE -#define TIVA_HAS_GPIOP FALSE -#define TIVA_HAS_GPIOQ FALSE -#define TIVA_HAS_GPIOR FALSE -#define TIVA_HAS_GPIOS FALSE -#define TIVA_HAS_GPIOT FALSE -#define TIVA_GPIO_PINS 48 -#endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ) \ - || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PZ) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PZ) -#define TIVA_HAS_GPIOA TRUE -#define TIVA_HAS_GPIOB TRUE -#define TIVA_HAS_GPIOC TRUE -#define TIVA_HAS_GPIOD TRUE -#define TIVA_HAS_GPIOE TRUE -#define TIVA_HAS_GPIOF TRUE -#define TIVA_HAS_GPIOG TRUE -#define TIVA_HAS_GPIOH TRUE -#define TIVA_HAS_GPIOJ TRUE -#define TIVA_HAS_GPIOK TRUE -#define TIVA_HAS_GPIOL TRUE -#define TIVA_HAS_GPIOM FALSE -#define TIVA_HAS_GPION FALSE -#define TIVA_HAS_GPIOP FALSE -#define TIVA_HAS_GPIOQ FALSE -#define TIVA_HAS_GPIOR FALSE -#define TIVA_HAS_GPIOS FALSE -#define TIVA_HAS_GPIOT FALSE -#define TIVA_GPIO_PINS 88 -#endif -#if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\ - || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE) -#define TIVA_HAS_GPIOA TRUE -#define TIVA_HAS_GPIOB TRUE -#define TIVA_HAS_GPIOC TRUE -#define TIVA_HAS_GPIOD TRUE -#define TIVA_HAS_GPIOE TRUE -#define TIVA_HAS_GPIOF TRUE -#define TIVA_HAS_GPIOG TRUE -#define TIVA_HAS_GPIOH TRUE -#define TIVA_HAS_GPIOJ TRUE -#define TIVA_HAS_GPIOK TRUE -#define TIVA_HAS_GPIOL TRUE -#define TIVA_HAS_GPIOM TRUE -#define TIVA_HAS_GPION TRUE -#define TIVA_HAS_GPIOP TRUE -#define TIVA_HAS_GPIOQ FALSE -#define TIVA_HAS_GPIOR FALSE -#define TIVA_HAS_GPIOS FALSE -#define TIVA_HAS_GPIOT FALSE -#define TIVA_GPIO_PINS 112 -#endif -#if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_HAS_GPIOA TRUE -#define TIVA_HAS_GPIOB TRUE -#define TIVA_HAS_GPIOC TRUE -#define TIVA_HAS_GPIOD TRUE -#define TIVA_HAS_GPIOE TRUE -#define TIVA_HAS_GPIOF TRUE -#define TIVA_HAS_GPIOG TRUE -#define TIVA_HAS_GPIOH TRUE -#define TIVA_HAS_GPIOJ TRUE -#define TIVA_HAS_GPIOK TRUE -#define TIVA_HAS_GPIOL TRUE -#define TIVA_HAS_GPIOM TRUE -#define TIVA_HAS_GPION TRUE -#define TIVA_HAS_GPIOP TRUE -#define TIVA_HAS_GPIOQ TRUE -#define TIVA_HAS_GPIOR FALSE -#define TIVA_HAS_GPIOS FALSE -#define TIVA_HAS_GPIOT FALSE -#define TIVA_GPIO_PINS 120 -#endif - -/* GPTM attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_HAS_GPT0 TRUE -#define TIVA_HAS_GPT1 TRUE -#define TIVA_HAS_GPT2 TRUE -#define TIVA_HAS_GPT3 TRUE -#define TIVA_HAS_GPT4 TRUE -#define TIVA_HAS_GPT5 TRUE -#define TIVA_HAS_GPT6 FALSE -#define TIVA_HAS_GPT7 FALSE -#define TIVA_HAS_WGPT0 TRUE -#define TIVA_HAS_WGPT1 TRUE -#define TIVA_HAS_WGPT2 TRUE -#define TIVA_HAS_WGPT3 TRUE -#define TIVA_HAS_WGPT4 TRUE -#define TIVA_HAS_WGPT5 TRUE -#endif - -/* WDT attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_HAS_WDT0 TRUE -#define TIVA_HAS_WDT1 TRUE -#endif - -/* ADC attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_HAS_ADC0 TRUE -#define TIVA_HAS_ADC1 TRUE -#endif - -/* UART attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_HAS_UART0 TRUE -#define TIVA_HAS_UART1 TRUE -#define TIVA_HAS_UART2 TRUE -#define TIVA_HAS_UART3 TRUE -#define TIVA_HAS_UART4 TRUE -#define TIVA_HAS_UART5 TRUE -#define TIVA_HAS_UART6 TRUE -#define TIVA_HAS_UART7 TRUE -#endif - -/* SPI attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_HAS_SSI0 TRUE -#define TIVA_HAS_SSI1 TRUE -#define TIVA_HAS_SSI2 TRUE -#define TIVA_HAS_SSI3 TRUE -#endif - -/* I2C attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PZ) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PGE) \ - || defined(TM4C1233H6PZ) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) \ - || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_HAS_I2C0 TRUE -#define TIVA_HAS_I2C1 TRUE -#define TIVA_HAS_I2C2 TRUE -#define TIVA_HAS_I2C3 TRUE -#define TIVA_HAS_I2C4 TRUE -#define TIVA_HAS_I2C5 TRUE -#define TIVA_HAS_I2C6 FALSE -#define TIVA_HAS_I2C7 FALSE -#define TIVA_HAS_I2C8 FALSE -#define TIVA_HAS_I2C9 FALSE -#endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) -#define TIVA_HAS_I2C0 TRUE -#define TIVA_HAS_I2C1 TRUE -#define TIVA_HAS_I2C2 TRUE -#define TIVA_HAS_I2C3 TRUE -#define TIVA_HAS_I2C4 FALSE -#define TIVA_HAS_I2C5 FALSE -#define TIVA_HAS_I2C6 FALSE -#define TIVA_HAS_I2C7 FALSE -#define TIVA_HAS_I2C8 FALSE -#define TIVA_HAS_I2C9 FALSE -#endif - -/* CAN attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) -#define TIVA_HAS_CAN0 TRUE -#define TIVA_HAS_CAN1 FALSE -#endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_HAS_CAN0 TRUE -#define TIVA_HAS_CAN1 TRUE -#endif - -/* USB attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) -#define TIVA_HAS_USB0 FALSE -#endif -#if defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) \ - || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) \ - || defined(TM4C123GH5ZXR) -#define TIVA_HAS_USB0 TRUE -#endif - -/* AC attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231E6PM) || defined(TM4C1231H6PM) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) || defined(TM4C1233E6PM) \ - || defined(TM4C1233H6PM) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PM) || defined(TM4C1237E6PM) \ - || defined(TM4C1237H6PM) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BH6PM) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) -#define TIVA_HAS_AC0 TRUE -#define TIVA_HAS_AC1 TRUE -#define TIVA_HAS_AC2 FALSE -#endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PGE) \ - || defined(TM4C1231H6PZ) || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PZ) || defined(TM4C1237D5PZ) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PZ) \ - || defined(TM4C123BH6ZRB) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE)\ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_HAS_AC0 TRUE -#define TIVA_HAS_AC1 TRUE -#define TIVA_HAS_AC2 TRUE -#endif - -/* PWM attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) -#define TIVA_HAS_PWM0 FALSE -#define TIVA_HAS_PWM1 FALSE -#endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_HAS_PWM0 TRUE -#define TIVA_HAS_PWM1 TRUE -#endif - -/* QEI attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) -#define TIVA_HAS_QEI0 FALSE -#define TIVA_HAS_QEI1 FALSE -#endif -#if defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) -#define TIVA_HAS_QEI0 TRUE -#define TIVA_HAS_QEI1 TRUE -#endif - -/** - * @} - */ - -#endif /* _TIVA_REGISTRY_H_ */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/tm4c123x.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/tm4c123x.h deleted file mode 100644 index d64afa8..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C123x/tm4c123x.h +++ /dev/null @@ -1,958 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @addtogroup CMSIS - * @{ - */ - -/** - * @addtogroup TM4C123x - * @{ - */ - -#ifndef __TM4C123x_H -#define __TM4C123x_H - -/** - * @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /**< MPU present */ -#define __NVIC_PRIO_BITS 3 /**< Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Use different SysTick Config */ -#define __FPU_PRESENT 1 /**< FPU present */ - -/** - * @brief TM4C123x Interrupt Number Definitions - */ -typedef enum IRQn -{ - /***** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< Cortex-M4 Non-Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -3, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - /***** TM4C123x Specific Interrupt Numbers *********************************/ - GPIOA_IRQn = 0, /**< GPIO Port A */ - GPIOB_IRQn = 1, /**< GPIO Port B */ - GPIOC_IRQn = 2, /**< GPIO Port C */ - GPIOD_IRQn = 3, /**< GPIO Port D */ - GPIOE_IRQn = 4, /**< GPIO Port E */ - UART0_IRQn = 5, /**< UART0 */ - UART1_IRQn = 6, /**< UART1 */ - SSI0_IRQn = 7, /**< SSI0 */ - I2C0_IRQn = 8, /**< I2C0 */ - PWM0FAULT_IRQn = 9, /**< PWM0 Fault */ - PWM0GEN0_IRQn = 10, /**< PWM0 Generator 0 */ - PWM0GEN1_IRQn = 11, /**< PWM0 Generator 1 */ - PWM0GEN2_IRQn = 12, /**< PWM0 Generator 2 */ - QEI0_IRQn = 13, /**< QEI0 */ - ADC0SEQ0_IRQn = 14, /**< ADC0 Sequence 0 */ - ADC0SEQ1_IRQn = 15, /**< ADC0 Sequence 1 */ - ADC0SEQ2_IRQn = 16, /**< ADC0 Sequence 2 */ - ADC0SEQ3_IRQn = 17, /**< ADC0 Sequence 3 */ - WATCHDOG_IRQn = 18, /**< Watchdog Timers 0 and 1 */ - TIMER0A_IRQn = 19, /**< 16/32-Bit Timer 0A */ - TIMER0B_IRQn = 20, /**< 16/32-Bit Timer 0B */ - TIMER1A_IRQn = 21, /**< 16/32-Bit Timer 1A */ - TIMER1B_IRQn = 22, /**< 16/32-Bit Timer 1B */ - TIMER2A_IRQn = 23, /**< 16/32-Bit Timer 2A */ - TIMER2B_IRQn = 24, /**< 16/32-Bit Timer 2B */ - ACOMP0_IRQn = 25, /**< Analog Comparator 0 */ - ACOMP1_IRQn = 26, /**< Analog Comparator 1 */ - SYSCON_IRQn = 28, /**< System Control */ - FMCEECON_IRQn = 29, /**< Flash Memory Control and EEPROM Control */ - GPIOF_IRQn = 30, /**< GPIO Port F */ - UART2_IRQn = 33, /**< UART2 */ - SSI1_IRQn = 34, /**< SSI1 */ - TIMER3A_IRQn = 35, /**< 16/32-Bit Timer 3A */ - TIMER3B_IRQn = 36, /**< 16/32-Bit Timer 3B */ - I2C1_IRQn = 37, /**< I2C1 */ - QEI1_IRQn = 38, /**< QEI1 */ - CAN0_IRQn = 39, /**< CAN0 */ - CAN1_IRQn = 40, /**< CAN1 */ - HIBMODULE_IRQn = 43, /**< Hibernation Module */ - USB_IRQn = 44, /**< USB */ - PWM0GEN3_IRQn = 45, /**< PWM0 Generator 3 */ - UDMASFW_IRQn = 46, /**< UDMA Software */ - UDMAERR_IRQn = 47, /**< UDMA Error */ - ADC1SEQ0_IRQn = 48, /**< ADC1 Sequence 0 */ - ADC1SEQ1_IRQn = 49, /**< ADC1 Sequence 1 */ - ADC1SEQ2_IRQn = 50, /**< ADC1 Sequence 2 */ - ADC1SEQ3_IRQn = 51, /**< ADC1 Sequence 3 */ - SSI2_IRQn = 57, /**< SSI2 */ - SSI3_IRQn = 58, /**< SSI3 */ - UART3_IRQn = 59, /**< UART3 */ - UART4_IRQn = 60, /**< UART4 */ - UART5_IRQn = 61, /**< UART5 */ - UART6_IRQn = 62, /**< UART6 */ - UART7_IRQn = 63, /**< UART7 */ - I2C2_IRQn = 68, /**< I2C2 */ - I2C3_IRQn = 69, /**< I2C3 */ - TIMER4A_IRQn = 70, /**< 16/32-Bit Timer 4A */ - TIMER4B_IRQn = 71, /**< 16/32-Bit Timer 4B */ - TIMER5A_IRQn = 92, /**< 16/32-Bit Timer 5A */ - TIMER5B_IRQn = 93, /**< 16/32-Bit Timer 5B */ - WTIMER0A_IRQn = 94, /**< 32/64-Bit Timer 0A */ - WTIMER0B_IRQn = 95, /**< 32/64-Bit Timer 0B */ - WTIMER1A_IRQn = 96, /**< 32/64-Bit Timer 1A */ - WTIMER1B_IRQn = 97, /**< 32/64-Bit Timer 1B */ - WTIMER2A_IRQn = 98, /**< 32/64-Bit Timer 2A */ - WTIMER2B_IRQn = 99, /**< 32/64-Bit Timer 2B */ - WTIMER3A_IRQn = 100, /**< 32/64-Bit Timer 3A */ - WTIMER3B_IRQn = 101, /**< 32/64-Bit Timer 3B */ - WTIMER4A_IRQn = 102, /**< 32/64-Bit Timer 4A */ - WTIMER4B_IRQn = 103, /**< 32/64-Bit Timer 4B */ - WTIMER5A_IRQn = 104, /**< 32/64-Bit Timer 5A */ - WTIMER5B_IRQn = 105, /**< 32/64-Bit Timer 5B */ - SYSEXCEPT_IRQn = 106, /**< System Exception (imprecise) */ - PWM1GEN0_IRQn = 134, /**< PWM1 Generator 0 */ - PWM1GEN1_IRQn = 135, /**< PWM1 Generator 1 */ - PWM1GEN2_IRQn = 136, /**< PWM1 Generator 2 */ - PWM1GEN3_IRQn = 137, /**< PWM1 Generator 3 */ - PWM1FAULT_IRQn = 138 /**< PWM1 Fault */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals.*/ -#include <stdint.h> - -/** - * @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog Comparator - */ -typedef struct -{ - __IO uint32_t MIS; /**< Masked Interrupt Status */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t INTEN; /**< Interrupt Enable */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t REFCTL; /**< Reference Voltage Control */ - __I uint32_t _RESERVED1[3]; /**< Reserved */ - __I uint32_t STAT0; /**< Status 0 */ - __IO uint32_t CTL0; /**< Control 0 */ - __I uint32_t _RESERVED2[6]; /**< Reserved */ - __I uint32_t STAT1; /**< Status 1 */ - __IO uint32_t CTL1; /**< Control 1 */ - __I uint32_t _RESERVED3[990];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ -} ACMP_TypeDef; - -/** - * @brief Analog-to-Digital Converter - */ -typedef struct -{ - __IO uint32_t MUX; /**< Sample Sequence Input Multiplexer - Select */ - __IO uint32_t CTL; /**< Sample Sequence Control */ - __I uint32_t FIFO; /**< Sample Sequence Result FIFO */ - __I uint32_t FSTAT; /**< Sample Sequence FIFO Status */ - __IO uint32_t OP; /**< Sample Sequence Operation */ - __IO uint32_t DC; /**< Sample Sequence Digital Comparator - Select */ - __I uint32_t _RESERVED0[2]; /**< Reserved */ -} ADC_SS_t; - -typedef struct -{ - __IO uint32_t ACTSS; /**< Active Sample Sequencer */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t IM; /**< Interrupt Mask */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ - __IO uint32_t OSTAT; /**< Overflow Status */ - __IO uint32_t EMUX; /**< Event Multiplexer Select */ - __IO uint32_t USTAT; /**< Underflow Status */ - __IO uint32_t TSSEL; /**< Trigger Source Select */ - __IO uint32_t SSPRI; /**< Sample Sequencer Priority */ - __IO uint32_t SPC; /**< Sample Phase Control */ - __IO uint32_t PSSI; /**< Processor Sample Sequence Initiate */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t SAC; /**< Sample Averaging Control */ - __IO uint32_t DCISC; /**< Digital Comparator Interrupt Status and - Clear */ - __IO uint32_t CTL; /**< Control */ - __I uint32_t _RESERVED1[1]; /**< Reserved */ - ADC_SS_t SS[4]; /**< Sample Sequence 0, 1, 2 and 3 */ - __I uint32_t _RESERVED2[784];/**< Reserved */ - __O uint32_t DCRIC; /**< Digital Comparator Reset Initial - Conditions */ - __I uint32_t _RESERVED3[63]; /**< Reserved */ - __IO uint32_t DCCTL[8]; /**< Digital Comparator Control 0 - 7 */ - __I uint32_t _RESERVED4[8]; /**< Reserved */ - __IO uint32_t DCCMP[8]; /**< Digital Comparator Range 0 - 7 */ - __I uint32_t _RESERVED5[88]; /**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ - __IO uint32_t PC; /**< Peripheral Configuration */ - __IO uint32_t CC; /**< Clock Configuration */ -} ADC_TypeDef; - -/** - * @brief Controller Area Network - */ -typedef struct -{ - __IO uint32_t CRQ; /**< Command Request */ - __IO uint32_t CMSK; /**< Command Mask */ - __IO uint32_t MSK[2]; /**< Mask 1 and 2 */ - __IO uint32_t ARB[2]; /**< Arbitration 1 and 2 */ - __IO uint32_t MCTL; /**< Message Control */ - __IO uint32_t DA[2]; /**< Data A1 and A2 */ - __IO uint32_t DB[2]; /**< Data B1 and B2 */ - __I uint32_t _RESERVED0[13]; /**< Reserved */ -} CAN_INTERFACE_t; - -typedef struct -{ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t STS; /**< Status */ - __I uint32_t ERR; /**< Error Counter */ - __IO uint32_t BIT; /**< Bit Timing */ - __I uint32_t INT; /**< Interrupt */ - __IO uint32_t TST; /**< Test */ - __IO uint32_t BRPE; /**< Baud Rate Prescaler Extension */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - CAN_INTERFACE_t IF[2]; /**< IF1 and IF2 */ - __I uint32_t _RESERVED1[8]; /**< Reserved */ - __I uint32_t TXRQ[2]; /**< Transmission Request 1 and 2 */ - __I uint32_t _RESERVED2[6]; /**< Reserved */ - __I uint32_t NWDA[2]; /**< New Data 1 and 2 */ - __I uint32_t _RESERVED3[6]; /**< Reserved */ - __I uint32_t MSGINT[2]; /**< Message 1 and 2 Interrupt Pending */ - __I uint32_t _RESERVED4[6]; /**< Reserved */ - __I uint32_t MSGVAL[2]; /**< Message 1 and 2 Valid */ -} CAN_TypeDef; - -/** - * @brief EEPROM Memory - */ -typedef struct -{ - __IO uint32_t EESIZE; /**< Size Information */ - __IO uint32_t EEBLOCK; /**< Current Block */ - __IO uint32_t EEOFFSET; /**< Current Offset */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t EERDWR; /**< Read-Write */ - __IO uint32_t EERDWRINC; /**< Read-Write with Increment */ - __IO uint32_t EEDONE; /**< Done Status */ - __IO uint32_t EESUPP; /**< Support Control and Status */ - __IO uint32_t EEUNLOCK; /**< Unlock */ - __I uint32_t _RESERVED1[3]; /**< Reserved */ - __IO uint32_t EEPROT; /**< Protection */ - __IO uint32_t EEPASS[3]; /**< Password */ - __IO uint32_t EEINT; /**< Interrupt */ - __I uint32_t _RESERVED2[3]; /**< Reserved */ - __IO uint32_t EEHIDE; /**< Block Hide */ - __I uint32_t _RESERVED3[11]; /**< Reserved */ - __IO uint32_t EEDBGME; /**< Debug Mass Erase */ - __I uint32_t _RESERVED4[975];/**< Reserved */ - __IO uint32_t EEPROMPP; /**< Peripheral Properties */ -} EEPROM_TypeDef; - -/** - * @brief Flash Memory - */ -typedef struct -{ - __IO uint32_t FMA; /**< Flash Memory Address */ - __IO uint32_t FMD; /**< Flash Memory Data */ - __IO uint32_t FMC; /**< Flash Memory Control */ - __I uint32_t FCRIS; /**< Flash Controller Raw Interrupt Status */ - __IO uint32_t FCIM; /**< Flash Controller Interrupt Mask */ - __IO uint32_t FCMISC; /**< Masked Interrupt Status and Clear */ - __I uint32_t _RESERVED0[2]; /**< Reserved */ - __IO uint32_t FMC2; /**< Flash Memory Control 2 */ - __I uint32_t _RESERVED1[3]; /**< Reserved */ - __IO uint32_t FWBVAL; /**< Flash Write Buffer Valid */ - __I uint32_t _RESERVED2[51]; /**< Reserved */ - __IO uint32_t FWBN; /**< Flash Write Buffer n */ - __I uint32_t _RESERVED3[943];/**< Reserved */ - __I uint32_t FSIZE; /**< Flash Size */ - __I uint32_t SSIZE; /**< SRAM Size */ - __I uint32_t _RESERVED4[1]; /**< Reserved */ - __IO uint32_t ROMSWMAP; /**< ROM Software Map */ -} FLASH_TypeDef; - -/** - * @brief General Purpose Input/Outputs - */ -typedef struct -{ - union { - __IO uint32_t MASKED_ACCESS[256]; /**< Masked access of Data Register */ - struct { - __I uint32_t _RESERVED0[255]; /**< Reserved */ - __IO uint32_t DATA; /**< Data */ - }; - }; - __IO uint32_t DIR; /**< Direction */ - __IO uint32_t IS; /**< Interrupt Sense */ - __IO uint32_t IBE; /**< Interrupt Both Edges */ - __IO uint32_t IEV; /**< Interrupt Event */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t AFSEL; /**< Alternate Function Select */ - __I uint32_t _RESERVED1[55]; /**< Reserved */ - __IO uint32_t DR2R; /**< 2-mA Drive Select */ - __IO uint32_t DR4R; /**< 4-mA Drive Select */ - __IO uint32_t DR8R; /**< 8-mA Drive Select */ - __IO uint32_t ODR; /**< Open Drain Select */ - __IO uint32_t PUR; /**< Pull-Up Select */ - __IO uint32_t PDR; /**< Pull-Down Select */ - __IO uint32_t SLR; /**< Slew Rate Control Select */ - __IO uint32_t DEN; /**< Digital Enable */ - __IO uint32_t LOCK; /**< Lock */ - __IO uint32_t CR; /**< Commit */ - __IO uint32_t AMSEL; /**< Analog Mode Select */ - __IO uint32_t PCTL; /**< Port Control */ - __IO uint32_t ADCCTL; /**< ADC Control */ - __IO uint32_t DMACTL; /**< DMA Control */ -} GPIO_TypeDef; - -/** - * @brief General Purpose Timer - */ -typedef struct -{ - __IO uint32_t CFG; /**< Configuration */ - __IO uint32_t TAMR; /**< Timer A Mode */ - __IO uint32_t TBMR; /**< Timer B Mode */ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t SYNC; /**< Synchronize */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t IMR; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t TAILR; /**< Timer A Interval Load */ - __IO uint32_t TBILR; /**< Timer B Interval Load */ - __IO uint32_t TAMATCHR; /**< Timer A Match */ - __IO uint32_t TBMATCHR; /**< Timer B Match */ - __IO uint32_t TAPR; /**< Timer A Prescale */ - __IO uint32_t TBPR; /**< Timer B Prescale */ - __IO uint32_t TAPMR; /**< Timer A Prescale Match */ - __IO uint32_t TBPMR; /**< Timer B Prescale Match */ - __I uint32_t TAR; /**< Timer A */ - __I uint32_t TBR; /**< Timer B */ - __IO uint32_t TAV; /**< Timer A Value */ - __IO uint32_t TBV; /**< Timer B Value */ - __I uint32_t RTCPD; /**< RTC Predivide */ - __I uint32_t TAPS; /**< Timer A Prescale Snapshot */ - __I uint32_t TBPS; /**< Timer B Prescale Snapshot */ - __I uint32_t TAPV; /**< Timer A Prescale Value */ - __I uint32_t TBPV; /**< Timer B Prescale Value */ - __I uint32_t _RESERVED1[981];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ -} GPT_TypeDef; - -/** - * @brief Hibernation Module - */ -typedef struct -{ - __I uint32_t RTCC; /**< RTC Counter */ - __IO uint32_t RTCM0; /**< RTC Match 0 */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t RTCLD; /**< RTC Load */ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __IO uint32_t IC; /**< Interrupt Clear */ - __IO uint32_t RTCT; /**< RTC Trim */ - __IO uint32_t RTCSS; /**< RTC Sub Seconds */ - __I uint32_t _RESERVED1[1]; /**< Reserved */ - __IO uint32_t DATA; /**< Data */ -} HIB_TypeDef; - -/** - * @brief Inter-Integrated Circuit - */ -typedef struct -{ - __IO uint32_t MSA; /**< Master Slave Address */ - __IO uint32_t MCS; /**< Master Control/Status */ - __IO uint32_t MDR; /**< Master Data */ - __IO uint32_t MTPR; /**< Master Timer Period */ - __IO uint32_t MIMR; /**< Master Interrupt Mask */ - __I uint32_t MRIS; /**< Master Raw Interrupt Status */ - __IO uint32_t MMIS; /**< Master Masked Interrupt Status */ - __O uint32_t MICR; /**< Master Interrupt Clear */ - __IO uint32_t MCR; /**< Master Configuration */ - __IO uint32_t MCLKOCNT; /**< Master Clock Low Timeout Count */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __I uint32_t MBMON; /**< Master Bus Monitor */ - __IO uint32_t MCR2; /**< Master Configuration 2 */ - __I uint32_t _RESERVED1[497];/**< Reserved */ - __IO uint32_t SOAR; /**< Slave Own Address */ - __IO uint32_t SCSR; /**< Slave Control/Status */ - __IO uint32_t SDR; /**< Slave Data */ - __IO uint32_t SIMR; /**< Slave Interrupt Mask */ - __I uint32_t SRIS; /**< Slave Raw Interrupt Status */ - __I uint32_t SMIS; /**< Slave Masked Interrupt Status */ - __O uint32_t SICR; /**< Slave Interrupt Clear */ - __IO uint32_t SOAR2; /**< Slave Own Address 2 */ - __IO uint32_t SACKCTL; /**< Slave ACK Control */ - __I uint32_t _RESERVED2[487];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ - __I uint32_t PC; /**< Peripheral Configuration */ -} I2C_TypeDef; - -/* - * @brief Pulse Width Modulator - */ -typedef struct -{ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t INTEN; /**< Interrupt and Trigger Enable */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ - __IO uint32_t LOAD; /**< Load */ - __I uint32_t COUNT; /**< Counter */ - __IO uint32_t CMP[2]; /**< Compare A, B */ - __IO uint32_t GEN[2]; /**< Generator A, B Control */ - __IO uint32_t DBCTL; /**< Dead-Band Control */ - __IO uint32_t DBRISE; /**< Dead-Band Rising-Edge Delay */ - __IO uint32_t DBFALL; /**< Dead-Band Falling-Edge Delay */ - __IO uint32_t FLTSRC[2]; /**< Fault Source 0, 1 */ - __IO uint32_t MINFLTPER; /**< Minimum Fault Period */ -} PWM_GENERATOR_T; - -typedef struct -{ - union { - __IO uint32_t SEN; /**< Fault Pin Logic Sense, for GEN 0 and 1 */ - __I uint32_t _RESERVED0[1];/**< Reserved, for GEN 2 and 3 */ - }; - __IO uint32_t STAT[2]; /**< Fault Status */ - __I uint32_t _RESERVED1[29]; /**< Reserved */ -} PWM_FLT_t; - -typedef struct -{ - __IO uint32_t CTL; /**< Master Control */ - __IO uint32_t SYNC; /**< Time Base Sync */ - __IO uint32_t ENABLE; /**< Output Enable */ - __IO uint32_t INVERT; /**< Output Inversion */ - __IO uint32_t FAULT; /**< Output Fault */ - __IO uint32_t INTEN; /**< Interrupt Enable */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ - __I uint32_t STATUS; /**< Status */ - __IO uint32_t FAULTVAL; /**< Fault Condition Value */ - __IO uint32_t ENUPD; /**< Enable Update */ - __I uint32_t _RESERVED0[5]; /**< Reserved */ - __IO PWM_GENERATOR_T PWM[4]; /**< PWM Generator 0, 1, 2 and 3 */ - __I uint32_t _RESERVED1[432];/**< Reserved */ - PWM_FLT_t FLT[4]; /**< Fault registers 0, 1, 2 and 3 */ - __I uint32_t _RESERVED2[368];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ -} PWM_TypeDef; - -/** - * @brief Quadrature Encoder Interface - */ -typedef struct -{ - __IO uint32_t CTL; /**< Control */ - __I uint32_t STAT; /**< Status */ - __IO uint32_t POS; /**< Position */ - __IO uint32_t MAXPOS; /**< Maximum Position */ - __IO uint32_t LOAD; /**< Timer Load */ - __I uint32_t TIME; /**< Timer */ - __I uint32_t COUNT; /**< Velocity Counter */ - __I uint32_t SPEED; /**< Velocity */ - __IO uint32_t INTEN; /**< Interrupt Enable */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ -} QEI_TypeDef; - -/** - * @brief Synchronous Serial Interface - */ -typedef struct -{ - __IO uint32_t CR0; /**< Control 0 */ - __IO uint32_t CR1; /**< Control 1 */ - __IO uint32_t DR; /**< Data */ - __I uint32_t SR; /**< Status */ - __IO uint32_t CPSR; /**< Clock Prescale */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t DMACTL; /**< DMA Control */ - __I uint32_t _RESERVED0[1000];/**< Reserved */ - __IO uint32_t CC; /**< Clock Configuration */ -} SSI_TypeDef; - -/** - * @brief System Control - */ -typedef struct -{ - __I uint32_t DID0; /**< Device Identification 0 */ - __I uint32_t DID1; /**< Device Identification 1 */ - __I uint32_t RESERVED0[10]; /**< Reserved */ - __IO uint32_t PBORCTL; /**< Brown-Out Reset Control */ - __I uint32_t RESERVED1[7]; /**< Reserved */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t IMC; /**< Interrupt Mask Control */ - __IO uint32_t MISC; /**< Interrupt Status and Clear */ - __IO uint32_t RESC; /**< Reset Cause */ - __IO uint32_t RCC; /**< Run-Mode Clock Configuration */ - __I uint32_t RESERVED2[2]; /**< Reserved */ - __IO uint32_t GPIOHBCTL; /**< GPIO High-Performance Bus Control */ - __IO uint32_t RCC2; /**< Run-Mode Clock Configuration 2 */ - __I uint32_t RESERVED3[2]; /**< Reserved */ - __IO uint32_t MOSCCTL; /**< Main Oscillator Control */ - __I uint32_t RESERVED4[49]; /**< Reserved */ - __IO uint32_t DSLPCLKCFG; /**< Deep Sleep Clock Configuration */ - __I uint32_t RESERVED5[1]; /**< Reserved */ - __I uint32_t SYSPROP; /**< System Properties */ - __IO uint32_t PIOSCCAL; /**< PIOSC Calibration */ - __I uint32_t PIOSCSTAT; /**< PIOSC Statistics */ - __I uint32_t RESERVED6[2]; /**< Reserved */ - __I uint32_t PLLFREQ0; /**< PLL Frequency 0 */ - __I uint32_t PLLFREQ1; /**< PLL Frequency 1 */ - __I uint32_t PLLSTAT; /**< PLL Frequency Status */ - __I uint32_t RESERVED7[7]; /**< Reserved */ - __IO uint32_t SLPPWRCFG; /**< Sleep Power Configuration */ - __IO uint32_t DSLPPWRCFG; /**< Deep-Sleep Power Configuration */ - __I uint32_t RESERVED8[9]; /**< Reserved */ - __IO uint32_t LDOSPCTL; /**< LDO Sleep Power Control */ - __I uint32_t LDOSPCAL; /**< LDO Sleep Power Calibration */ - __IO uint32_t LDODPCTL; /**< LDO Deep-Sleep Power Control */ - __I uint32_t LDODPCAL; /**< LDO Deep-Sleep Power Calibration */ - __I uint32_t RESERVED9[2]; /**< Reserved */ - __I uint32_t SDPMST; /**< Sleep/Deep-Sleep Power Mode Status */ - __I uint32_t RESERVED10[76]; /**< Reserved */ - __I uint32_t PPWD; /**< WDT Peripheral Present */ - __I uint32_t PPTIMER; /**< GPT Peripheral Present */ - __I uint32_t PPGPIO; /**< GPIO Peripheral Present */ - __I uint32_t PPDMA; /**< UDMA Peripheral Present */ - __I uint32_t RESERVED11[1]; /**< Reserved */ - __I uint32_t PPHIB; /**< HIB Peripheral Present */ - __I uint32_t PPUART; /**< UART Peripheral Present */ - __I uint32_t PPSSI; /**< SSI Peripheral Present */ - __I uint32_t PPI2C; /**< I2C Peripheral Present */ - __I uint32_t RESERVED12[1]; /**< Reserved */ - __I uint32_t PPUSB; /**< USB Peripheral Present */ - __I uint32_t RESERVED13[2]; /**< Reserved */ - __I uint32_t PPCAN; /**< CAN Peripheral Present */ - __I uint32_t PPADC; /**< ADC Peripheral Present */ - __I uint32_t PPACMP; /**< ACMP Peripheral Present */ - __I uint32_t PPPWM; /**< PWM Peripheral Present */ - __I uint32_t PPQEI; /**< QEI Peripheral Present */ - __I uint32_t RESERVED14[4]; /**< Reserved */ - __I uint32_t PPEEPROM; /**< EEPROM Peripheral Present */ - __I uint32_t PPWTIMER; /**< Wide GPT Peripheral Present */ - __I uint32_t RESERVED15[104];/**< Reserved */ - __IO uint32_t SRWD; /**< WDT Software Reset */ - __IO uint32_t SRTIMER; /**< GPT Software Reset */ - __IO uint32_t SRGPIO; /**< GPIO Software Reset */ - __IO uint32_t SRDMA; /**< UDMA Software Reset */ - __I uint32_t RESERVED16[1]; /**< Reserved */ - __IO uint32_t SRHIB; /**< HIB Software Reset */ - __IO uint32_t SRUART; /**< UART Software Reset */ - __IO uint32_t SRSSI; /**< SSI Software Reset */ - __IO uint32_t SRI2C; /**< I2C Software Reset */ - __I uint32_t RESERVED17[1]; /**< Reserved */ - __IO uint32_t SRUSB; /**< USB Software Reset */ - __I uint32_t RESERVED18[2]; /**< Reserved */ - __IO uint32_t SRCAN; /**< CAN Software Reset */ - __IO uint32_t SRADC; /**< ADC Software Reset */ - __IO uint32_t SRACMP; /**< ACMP Software Reset */ - __IO uint32_t SRPWM; /**< PWM Software Reset */ - __IO uint32_t SRQEI; /**< QEI Software Reset */ - __I uint32_t RESERVED19[4]; /**< Reserved */ - __IO uint32_t SREEPROM; /**< EEPROM Software Reset */ - __IO uint32_t SRWTIMER; /**< Wide GPT Software Reset */ - __I uint32_t RESERVED20[40]; /**< Reserved */ - __IO uint32_t RCGCWD; /**< WDT Run Mode Clock Gating Control */ - __IO uint32_t RCGCTIMER; /**< GPT Run Mode Clock Gating Control */ - __IO uint32_t RCGCGPIO; /**< GPIO Run Mode Clock Gating Control */ - __IO uint32_t RCGCDMA; /**< UDMA Run Mode Clock Gating Control */ - __I uint32_t RESERVED21[1]; /**< Reserved */ - __IO uint32_t RCGCHIB; /**< HIB Run Mode Clock Gating Control */ - __IO uint32_t RCGCUART; /**< UART Run Mode Control */ - __IO uint32_t RCGCSSI; /**< SSI Run Mode Clock Gating Control */ - __IO uint32_t RCGCI2C; /**< I2C Run Mode Clock Gating Control */ - __I uint32_t RESERVED22[1]; /**< Reserved */ - __IO uint32_t RCGCUSB; /**< USB Run Mode Clock Gating Control */ - __I uint32_t RESERVED23[2]; /**< Reserved */ - __IO uint32_t RCGCCAN; /**< CAN Run Mode Clock Gating Control */ - __IO uint32_t RCGCADC; /**< ADC Run Mode Clock Gating Control */ - __IO uint32_t RCGCACMP; /**< ACMP Run Mode Clock Gating Control */ - __IO uint32_t RCGCPWM; /**< PWM Run Mode Clock Gating Control */ - __IO uint32_t RCGCQEI; /**< QEI Run Mode Clock Gating Control */ - __I uint32_t RESERVED24[4]; /**< Reserved */ - __IO uint32_t RCGCEEPROM; /**< EEPROM Run Mode Clock Gating Control */ - __IO uint32_t RCGCWTIMER; /**< Wide GPT Run Mode Clock Gating Control */ - __I uint32_t RESERVED25[40]; /**< Reserved */ - __IO uint32_t SCGCWD; /**< WDT Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCTIMER; /**< GPT Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCGPIO; /**< GPIO Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCDMA; /**< UDMA Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED26[1]; /**< Reserved */ - __IO uint32_t SCGCHIB; /**< HIB Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCUART; /**< UART Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCSSI; /**< SSI Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCI2C; /**< I2C Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED27[1]; /**< Reserved */ - __IO uint32_t SCGCUSB; /**< USB Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED28[2]; /**< Reserved */ - __IO uint32_t SCGCCAN; /**< CAN Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCADC; /**< ADC Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCACMP; /**< ACMP Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCPWM; /**< PWM Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCQEI; /**< QEI Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED29[4]; /**< Reserved */ - __IO uint32_t SCGCEEPROM; /**< EEPROM Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCWTIMER; /**< Wide GPT Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED30[40]; /**< Reserved */ - __IO uint32_t DCGCWD; /**< WDT Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCTIMER; /**< GPT Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCGPIO; /**< GPIO Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCDMA; /**< UDMA Deep-Sleep Mode Clock Gating - Control */ - __I uint32_t RESERVED31[1]; /**< Reserved */ - __IO uint32_t DCGCHIB; /**< HIB Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCUART; /**< UART Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCSSI; /**< SSI Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCI2C; /**< I2C Deep-Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED32[1]; /**< Reserved */ - __IO uint32_t DCGCUSB; /**< USB Deep-Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED33[2]; /**< Reserved */ - __IO uint32_t DCGCCAN; /**< CAN Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCADC; /**< ADC Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCACMP; /**< ACMP Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCPWM; /**< PWM Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCQEI; /**< QEI Deep-Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED34[4]; /**< Reserved */ - __IO uint32_t DCGCEEPROM; /**< EEPROM Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCWTIMER; /**< Wide GPT Deep-Sleep Mode Clock Gating - Control */ - __I uint32_t RESERVED35[104];/**< Reserved */ - __IO uint32_t PRWD; /**< WDT Peripheral Ready */ - __IO uint32_t PRTIMER; /**< GPT Peripheral Ready */ - __IO uint32_t PRGPIO; /**< GPIO Peripheral Ready */ - __IO uint32_t PRDMA; /**< UDMA Peripheral Ready */ - __I uint32_t RESERVED36[1]; /**< Reserved */ - __IO uint32_t PRHIB; /**< HIB Peripheral Ready */ - __IO uint32_t PRUART; /**< UART Peripheral Ready */ - __IO uint32_t PRSSI; /**< SSI Peripheral Ready */ - __IO uint32_t PRI2C; /**< I2C Peripheral Ready */ - __I uint32_t RESERVED37[1]; /**< Reserved */ - __IO uint32_t PRUSB; /**< USB Peripheral Ready */ - __I uint32_t RESERVED38[2]; /**< Reserved */ - __IO uint32_t PRCAN; /**< CAN Peripheral Ready */ - __IO uint32_t PRADC; /**< ADC Peripheral Ready */ - __IO uint32_t PRACMP; /**< ACMP Peripheral Ready */ - __IO uint32_t PRPWM; /**< PWM Peripheral Ready */ - __IO uint32_t PRQEI; /**< QEI Peripheral Ready */ - __I uint32_t RESERVED39[4]; /**< Reserved */ - __IO uint32_t PREEPROM; /**< EEPROM Peripheral Ready */ - __IO uint32_t PRWTIMER; /**< Wide GPT Peripheral Ready */ -} SYSCTL_TypeDef; - -/** - * @brief Universal Asynchronous Receiver/Transmitter - */ -typedef struct -{ - __IO uint32_t DR; /**< Data */ - union { - __I uint32_t RSR; /**< Receive Status */ - __O uint32_t ECR; /**< Error Clear */ - }; - __I uint32_t _RESERVED0[4]; /**< Reserved */ - __I uint32_t FR; /**< Flag */ - __I uint32_t _RESERVED1[1]; /**< Reserved */ - __IO uint32_t ILPR; /**< IrDA Low-Power Register */ - __IO uint32_t IBRD; /**< Integer Baud-Rate Divisor */ - __IO uint32_t FBRD; /**< Fractional Baud-Rate Divisor */ - __IO uint32_t LCRH; /**< Line Control */ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t IFLS; /**< Interrupt FIFO Level Select */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t DMACTL; /**< DMA Control */ - __I uint32_t _RESERVED2[22]; /**< Reserved */ - __IO uint32_t BIT9ADDR; /**< 9-Bit Self Address */ - __IO uint32_t BIT9AMASK; /**< 9-Bit Self Address Mask */ - __I uint32_t _RESERVED3[965];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ - __I uint32_t _RESERVED4[1]; /**< Reserved */ - __IO uint32_t CC; /**< Clock Configuration */ -} UART_TypeDef; - -/** - * @brief Micro Direct Memory Access - */ -typedef struct -{ - __IO uint32_t SET; /**< Set */ - __O uint32_t CLR; /**< Clear */ -} UDMA_SC_t; - -typedef struct -{ - __IO uint32_t STAT; /**< Status */ - __O uint32_t CFG; /**< Configuration */ - __IO uint32_t CTLBASE; /**< Channel Control Base Pointer */ - __IO uint32_t ALTBASE; /**< Alternate Channel Control Base Pointer */ - __IO uint32_t WAITSTAT; /**< Channel Wait-on-Request Status */ - __O uint32_t SWREQ; /**< Channel Software Request */ - __IO uint32_t USEBURSTSET; /**< Channel Useburst Set */ - __O uint32_t USEBURSTCLR; /**< Channel Useburst Clear */ - __IO uint32_t REQMASKSET; /**< Channel Request Mask Set */ - __O uint32_t REQMASKCLR; /**< Channel Request Mask Clear */ - __IO uint32_t ENASET; /**< Channel Enable Set */ - __O uint32_t ENACLR; /**< Channel Enable Clear */ - __IO uint32_t ALTSET; /**< Channel Primary Alternate Set */ - __O uint32_t ALTCLR; /**< Channel Primary Alternate Clear */ - __IO uint32_t PRIOSET; /**< Channel Priority Set */ - __O uint32_t PRIOCLR; /**< Channel Priority Clear */ - __I uint32_t _RESERVED0[3]; /**< Reserved */ - __IO uint32_t ERRCLR; /**< Bus Error Clear */ - __I uint32_t _RESERVED1[300];/**< Reserved */ - __IO uint32_t CHASGN; /**< Channel Assignment */ - __IO uint32_t CHIS; /**< Channel Interrupt Status */ - __I uint32_t _RESERVED2[2]; /**< Reserved */ - __IO uint32_t CHMAP[4]; /**< Channel Map Select 0, 1, 2 and 3 */ -} UDMA_TypeDef; - -// USB - -/** - * @brief Watchdog Timer - */ -typedef struct -{ - __IO uint32_t LOAD; /**< Load */ - __I uint32_t VALUE; /**< Value */ - __IO uint32_t CTL; /**< Control */ - __O uint32_t ICR; /**< Interrupt Clear */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __I uint32_t _RESERVED0[256];/**< Reserved */ - __IO uint32_t TEST; /**< Test */ - __I uint32_t _RESERVED1[505];/**< Reserved */ - __IO uint32_t LOCK; /**< Lock */ -} WDT_TypeDef; - -/** - * @} - */ - -/** - * @addtogroup Peripheral_memorymap - * @{ - */ - -#define SYSCTL_BASE 0x400FE000 -#define HIB_BASE 0x400FC000 -#define FLASH_BASE 0x400FD000 -#define EEPROM_BASE 0x400AF000 -#define UDMA_BASE 0x400FF000 -#define GPIOA_APB_BASE 0x40004000 -#define GPIOA_AHB_BASE 0x40058000 -#define GPIOB_APB_BASE 0x40005000 -#define GPIOB_AHB_BASE 0x40059000 -#define GPIOC_APB_BASE 0x40006000 -#define GPIOC_AHB_BASE 0x4005A000 -#define GPIOD_APB_BASE 0x40007000 -#define GPIOD_AHB_BASE 0x4005B000 -#define GPIOE_APB_BASE 0x40024000 -#define GPIOE_AHB_BASE 0x4005C000 -#define GPIOF_APB_BASE 0x40025000 -#define GPIOF_AHB_BASE 0x4005D000 -#define GPIOG_APB_BASE 0x40026000 -#define GPIOG_AHB_BASE 0x4005E000 -#define GPIOH_APB_BASE 0x40027000 -#define GPIOH_AHB_BASE 0x4005F000 -#define GPIOJ_APB_BASE 0x4003D000 -#define GPIOJ_AHB_BASE 0x40060000 -#define GPIOK_AHB_BASE 0x40061000 -#define GPIOL_AHB_BASE 0x40062000 -#define GPIOM_AHB_BASE 0x40063000 -#define GPION_AHB_BASE 0x40064000 -#define GPIOP_AHB_BASE 0x40065000 -#define GPIOQ_AHB_BASE 0x40066000 -#define GPT0_BASE 0x40030000 -#define GPT1_BASE 0x40031000 -#define GPT2_BASE 0x40032000 -#define GPT3_BASE 0x40033000 -#define GPT4_BASE 0x40034000 -#define GPT5_BASE 0x40035000 -#define WGPT0_BASE 0x40036000 -#define WGPT1_BASE 0x40037000 -#define WGPT2_BASE 0x4004C000 -#define WGPT3_BASE 0x4004D000 -#define WGPT4_BASE 0x4004E000 -#define WGPT5_BASE 0x4004F000 -#define WDT0_BASE 0x40000000 -#define WDT1_BASE 0x40001000 -#define ADC0_BASE 0x40038000 -#define ADC1_BASE 0x40039000 -#define UART0_BASE 0x4000C000 -#define UART1_BASE 0x4000D000 -#define UART2_BASE 0x4000E000 -#define UART3_BASE 0x4000F000 -#define UART4_BASE 0x40010000 -#define UART5_BASE 0x40011000 -#define UART6_BASE 0x40012000 -#define UART7_BASE 0x40013000 -#define SSI0_BASE 0x40008000 -#define SSI1_BASE 0x40009000 -#define SSI2_BASE 0x4000A000 -#define SSI3_BASE 0x4000B000 -#define I2C0_BASE 0x40020000 -#define I2C1_BASE 0x40021000 -#define I2C2_BASE 0x40022000 -#define I2C3_BASE 0x40023000 -#define I2C4_BASE 0x40023000 -#define I2C5_BASE 0x40023000 -#define CAN0_BASE 0x40040000 -#define CAN1_BASE 0x40041000 -// usb -#define ACMP_BASE 0x4003C000 -#define PWM0_BASE 0x40028000 -#define PWM1_BASE 0x40029000 -#define QEI0_BASE 0x4002C000 -#define QEI1_BASE 0x4002D000 - -/** - * @} - */ - -/** - * @addtogroup Peripheral_declaration - * @{ - */ - -#define SYSCTL ((SYSCTL_TypeDef *) SYSCTL_BASE) -#define HIB ((HIB_TypeDef *) HIB_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_BASE) -#define EEPROM ((EEPROM_TypeDef *) EEPROM_BASE) -#define UDMA ((UDMA_TypeDef *) UDMA_BASE) -#define GPIOA_APB ((GPIO_TypeDef *) GPIOA_APB_BASE) -#define GPIOA_AHB ((GPIO_TypeDef *) GPIOA_AHB_BASE) -#define GPIOB_APB ((GPIO_TypeDef *) GPIOB_APB_BASE) -#define GPIOB_AHB ((GPIO_TypeDef *) GPIOB_AHB_BASE) -#define GPIOC_APB ((GPIO_TypeDef *) GPIOC_APB_BASE) -#define GPIOC_AHB ((GPIO_TypeDef *) GPIOC_AHB_BASE) -#define GPIOD_APB ((GPIO_TypeDef *) GPIOD_APB_BASE) -#define GPIOD_AHB ((GPIO_TypeDef *) GPIOD_AHB_BASE) -#define GPIOE_APB ((GPIO_TypeDef *) GPIOE_APB_BASE) -#define GPIOE_AHB ((GPIO_TypeDef *) GPIOE_AHB_BASE) -#define GPIOF_APB ((GPIO_TypeDef *) GPIOF_APB_BASE) -#define GPIOF_AHB ((GPIO_TypeDef *) GPIOF_AHB_BASE) -#define GPIOG_APB ((GPIO_TypeDef *) GPIOG_APB_BASE) -#define GPIOG_AHB ((GPIO_TypeDef *) GPIOG_AHB_BASE) -#define GPIOH_APB ((GPIO_TypeDef *) GPIOH_APB_BASE) -#define GPIOH_AHB ((GPIO_TypeDef *) GPIOH_AHB_BASE) -#define GPIOJ_APB ((GPIO_TypeDef *) GPIOJ_APB_BASE) -#define GPIOJ_AHB ((GPIO_TypeDef *) GPIOJ_AHB_BASE) -#define GPIOK_AHB ((GPIO_TypeDef *) GPIOK_AHB_BASE) -#define GPIOL_AHB ((GPIO_TypeDef *) GPIOL_AHB_BASE) -#define GPIOM_AHB ((GPIO_TypeDef *) GPIOM_AHB_BASE) -#define GPION_AHB ((GPIO_TypeDef *) GPION_AHB_BASE) -#define GPIOP_AHB ((GPIO_TypeDef *) GPIOP_AHB_BASE) -#define GPIOQ_AHB ((GPIO_TypeDef *) GPIOQ_AHB_BASE) -#define GPT0 ((GPT_TypeDef *) GPT0_BASE) -#define GPT1 ((GPT_TypeDef *) GPT1_BASE) -#define GPT2 ((GPT_TypeDef *) GPT2_BASE) -#define GPT3 ((GPT_TypeDef *) GPT3_BASE) -#define GPT4 ((GPT_TypeDef *) GPT4_BASE) -#define GPT5 ((GPT_TypeDef *) GPT5_BASE) -#define WGPT0 ((GPT_TypeDef *) WGPT0_BASE) -#define WGPT1 ((GPT_TypeDef *) WGPT1_BASE) -#define WGPT2 ((GPT_TypeDef *) WGPT2_BASE) -#define WGPT3 ((GPT_TypeDef *) WGPT3_BASE) -#define WGPT4 ((GPT_TypeDef *) WGPT4_BASE) -#define WGPT5 ((GPT_TypeDef *) WGPT5_BASE) -#define WDT0 ((WDT_TypeDef *) WDT0_BASE) -#define WDT1 ((WDT_TypeDef *) WDT1_BASE) -#define ADC0 ((ADC_TypeDef*) ADC0_BASE) -#define ADC1 ((ADC_TypeDef*) ADC1_BASE) -#define UART0 ((UART_TypeDef *) UART0_BASE) -#define UART1 ((UART_TypeDef *) UART1_BASE) -#define UART2 ((UART_TypeDef *) UART2_BASE) -#define UART3 ((UART_TypeDef *) UART3_BASE) -#define UART4 ((UART_TypeDef *) UART4_BASE) -#define UART5 ((UART_TypeDef *) UART5_BASE) -#define UART6 ((UART_TypeDef *) UART6_BASE) -#define UART7 ((UART_TypeDef *) UART7_BASE) -#define SSI0 ((SSI_TypeDef *) SSI0_BASE) -#define SSI1 ((SSI_TypeDef *) SSI1_BASE) -#define SSI2 ((SSI_TypeDef *) SSI2_BASE) -#define SSI3 ((SSI_TypeDef *) SSI3_BASE) -#define I2C0 ((I2C_TypeDef *) I2C0_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define I2C4 ((I2C_TypeDef *) I2C4_BASE) -#define I2C5 ((I2C_TypeDef *) I2C5_BASE) -#define CAN0 ((CAN_TypeDef *) CAN0_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -// usb -#define ACMP ((ACMP_TypeDef *) ACMP_BASE) -#define PWM0 ((PWM_TypeDef *) PWM0_BASE) -#define PWM1 ((PWM_TypeDef *) PWM1_BASE) -#define QEI0 ((QEI_TypeDef *) QEI0_BASE) -#define QEI1 ((QEI_TypeDef *) QEI1_BASE) - -/** - * @} - */ - -#endif /* __TM4C123x_H */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/hal_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/hal_lld.c deleted file mode 100644 index 60d6763..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/hal_lld.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/TM4C129x/hal_lld.c - * @brief TM4C129x HAL Driver subsystem low level driver source. - * - * @addtogroup HAL - * @{ - */ - -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - * - * @notapi - */ -void hal_lld_init(void) -{ -} - -/** - * @brief TM4C129x clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h and - * @p mcuconf.h. - * @note This function should be invoked just after the system reset. - * - * @special - */ -void tiva_clock_init(void) -{ - uint32_t moscctl, rsclkcfg; - - /* - * 1. Once POR has completed, the PIOSC is acting as the system clock. - */ - - /* - * 2. Power up the MOSC by clearing the NOXTAL bit in the MOSCCTL register. - */ - moscctl = SYSCTL->MOSCCTL; - moscctl &= ~MOSCCTL_NOXTAL; - - /* - * 3. If single-ended MOSC mode is required, the MOSC is ready to use. If crystal mode is required, - * clear the PWRDN bit and wait for the MOSCPUPRIS bit to be set in the Raw Interrupt Status - * (RIS), indicating MOSC crystal mode is ready. - */ -#if TIVA_MOSC_SINGLE_ENDED - SYSCTL->MOSCCTL = moscctl; -#else - moscctl &= ~MOSCCTL_PWRDN; - SYSCTL->MOSCCTL = moscctl; - - while (!(SYSCTL->RIS & SYSCTL_RIS_MOSCPUPRIS)); -#endif - - /* - * 4. Set the OSCSRC field to 0x3 in the RSCLKCFG register at offset 0x0B0. - */ - rsclkcfg = SYSCTL->RSCLKCFG; - - rsclkcfg |= TIVA_RSCLKCFG_OSCSRC; - - /* - * 5. If the application also requires the MOSC to be the deep-sleep clock source, then program the - * DSOSCSRC field in the DSCLKCFG register to 0x3. - */ - - /* - * 6. Write the PLLFREQ0 and PLLFREQ1 registers with the values of Q, N, MINT, and MFRAC to - * the configure the desired VCO frequency setting. - */ - SYSCTL->PLLFREQ1 = (0x04 << 0); // 5 - 1 - SYSCTL->PLLFREQ0 = (0x60 << 0) | PLLFREQ0_PLLPWR; - - /* - * 7. Write the MEMTIM0 register to correspond to the new system clock setting. - */ - SYSCTL->MEMTIM0 = (MEMTIM0_FBCHT_3_5 | MEMTIM0_FWS_5 | MEMTIM0_EBCHT_3_5 | MEMTIM0_EWS_5 | MEMTIM0_MB1); - - /* - * Wait for the PLLSTAT register to indicate the PLL has reached lock at the new operating point - * (or that a timeout period has passed and lock has failed, in which case an error condition exists - * and this sequence is abandoned and error processing is initiated). - */ - while (!SYSCTL->PLLSTAT & PLLSTAT_LOCK); - - /* - * 9. Write the RSCLKCFG register's PSYSDIV value, set the USEPLL bit to enabled, and MEMTIMU - * bit. - */ - - rsclkcfg = SYSCTL->RSCLKCFG; - - rsclkcfg |= (RSCLKCFG_USEPLL | (0x03 << 0) | (0x03 << 20) | (0x03 << 24)); - - //rsclkcfg |= ((0x03 << 0) | (1 << 28) | (0x03 << 20)); - - rsclkcfg |= RSCLKCFG_MEMTIMU; - - // set new configuration - SYSCTL->RSCLKCFG = rsclkcfg; - -#if HAL_USE_PWM -#if TIVA_PWM_USE_PWM0 - PWM0->CC = TIVA_PWM_FIELDS; -#endif -#endif -} - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/hal_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/hal_lld.h deleted file mode 100644 index e5c667d..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/hal_lld.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/TM4C129x/hal_lld.h - * @brief TM4C129x HAL subsystem low level driver header. - * @pre This module requires the following macros to be defined in the - * @p board.h file: - * - TODO: add required macros - * - * @addtogroup HAL - * @{ - */ - -#ifndef HAL_LLD_H -#define HAL_LLD_H - -#include "tiva_registry.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Platform identification - * @{ - */ - -#define PLATFORM_NAME "Tiva C Series TM4C129x" - -/** - * @} - */ - -/** - * @name RIS register bits definitions - * @{ - */ - -#define SYSCTL_RIS_PLLLRIS (1 << 6) -#define SYSCTL_RIS_MOSCPUPRIS (1 << 8) - -/** - * @} - */ - -/** - * @name MOSCCTL register bits definitions - * @{ - */ - -#define MOSCCTL_CVAL (1 << 0) -#define MOSCCTL_MOSCIM (1 << 1) -#define MOSCCTL_NOXTAL (1 << 2) -#define MOSCCTL_PWRDN (1 << 3) -#define MOSCCTL_OSCRNG (1 << 4) - -/** - * @} - */ - -/** - * @name RSCLKCFG register bits definitions - * @{ - */ - -#define RSCLKCFG_PSYSDIV_bm (0xfffff << 0) -#define RSCLKCFG_OSYSDIV_bm (0xfffff << 10 - -#define RSCLKCFG_OSCSRC_bm (0xff << 20) -#define RSCLKCFG_OSCSRC_PIOSC (0 << 20) -#define RSCLKCFG_OSCSRC_LFIOSC (0x02 << 20) -#define RSCLKCFG_OSCSRC_MOSC (0x03 << 20) -#define RSCLKCFG_OSCSRC_RTCOSC (0x04 << 20) - -#define RSCLKCFG_PLLSRC_bm (0xff << 24) -#define RSCLKCFG_PLLSRC_PIOSC (0 << 24) -#define RSCLKCFG_PLLSRC_MOSC (0x03 << 24) - -#define RSCLKCFG_USEPLL (1 << 28) - -#define RSCLKCFG_ACG (1 << 29) - -#define RSCLKCFG_NEWFREQ (1 << 30) - -#define RSCLKCFG_MEMTIMU (1 << 31) - -/** - * @} - */ - -/** - * @name PLLFREQ0 register bits definitions - * The PLL frequency can be calculated using the following equation: - * fVCO = (fIN * MDIV) - * where - * fIN = fXTAL/(Q+1)(N+1) or fPIOSC/(Q+1)(N+1) - * MDIV = MINT + (MFRAC / 1024) - * The Q and N values are programmed in the PLLFREQ1 register. Note that to reduce jitter, MFRAC - * should be programmed to 0x0. - * @{ - */ - -#define PLLFREQ0_MINT_bm (0xfffff << 0) -#define PLLFREQ0_MFRAC_bm (0xfffff << 10) -#define PLLFREQ0_PLLPWR (1 << 23) - -/** - * @} - */ - -/** - * @name PLLFREQ1 register bits definitions - * @{ - */ - -#define PLLFREQ1_N_bm (0x7ff << 0) -#define PLLFREQ1_Q_bm (0x7ff << 8) - -/** - * @} - */ - -/** - * @name MEMTIM0 register bits definitions - * @{ - */ - -#define MEMTIM0_FWS_bm (0xff << 0) -#define MEMTIM0_FWS_0 (0x00 << 0) -#define MEMTIM0_FWS_1 (0x01 << 0) -#define MEMTIM0_FWS_2 (0x02 << 0) -#define MEMTIM0_FWS_3 (0x03 << 0) -#define MEMTIM0_FWS_4 (0x04 << 0) -#define MEMTIM0_FWS_5 (0x05 << 0) -#define MEMTIM0_FWS_6 (0x06 << 0) -#define MEMTIM0_FWS_7 (0x07 << 0) - -#define MEMTIM0_FBCE (1 << 5) - -#define MEMTIM0_FBCHT_bm (0xff << 6) -#define MEMTIM0_FBCHT_0_5 (0x00 << 6) -#define MEMTIM0_FBCHT_1 (0x01 << 6) -#define MEMTIM0_FBCHT_1_5 (0x02 << 6) -#define MEMTIM0_FBCHT_2 (0x03 << 6) -#define MEMTIM0_FBCHT_2_5 (0x04 << 6) -#define MEMTIM0_FBCHT_3 (0x05 << 6) -#define MEMTIM0_FBCHT_3_5 (0x06 << 6) -#define MEMTIM0_FBCHT_4 (0x07 << 6) -#define MEMTIM0_FBCHT_4_5 (0x08 << 6) - -#define MEMTIM0_EWS_bm (0xff << 16) -#define MEMTIM0_EWS_0 (0x00 << 16) -#define MEMTIM0_EWS_1 (0x01 << 16) -#define MEMTIM0_EWS_2 (0x02 << 16) -#define MEMTIM0_EWS_3 (0x03 << 16) -#define MEMTIM0_EWS_4 (0x04 << 16) -#define MEMTIM0_EWS_5 (0x05 << 16) -#define MEMTIM0_EWS_6 (0x06 << 16) -#define MEMTIM0_EWS_7 (0x07 << 16) - -#define MEMTIM0_EBCE (1 << 21) - -#define MEMTIM0_EBCHT_bm (0xff << 22) -#define MEMTIM0_EBCHT_0_5 (0x00 << 22) -#define MEMTIM0_EBCHT_1 (0x01 << 22) -#define MEMTIM0_EBCHT_1_5 (0x02 << 22) -#define MEMTIM0_EBCHT_2 (0x03 << 22) -#define MEMTIM0_EBCHT_2_5 (0x04 << 22) -#define MEMTIM0_EBCHT_3 (0x05 << 22) -#define MEMTIM0_EBCHT_3_5 (0x06 << 22) -#define MEMTIM0_EBCHT_4 (0x07 << 22) -#define MEMTIM0_EBCHT_4_5 (0x08 << 22) - -// XXX: what is this? -#define MEMTIM0_MB1 0x00100010 // MB1 = Must be one - -/** - * @} - */ - -/** - * @name PLLSTAT register bits definitions - * @{ - */ - -#define PLLSTAT_LOCK (1 << 0) - -/** - * @} - */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -#if !defined(TIVA_MOSC_SINGLE_ENDED) -#define TIVA_MOSC_SINGLE_ENDED FALSE -#endif - -#if !defined(TIVA_RSCLKCFG_OSCSRC) -#define TIVA_RSCLKCFG_OSCSRC RSCLKCFG_OSCSRC_MOSC -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* - * Configuration-related checks. - */ -#if !defined(TM4C129x_MCUCONF) -#error "Using a wrong mcuconf.h file, TM4C129x_MCUCONF not defined" -#endif - -/* - * Oscillator-related checks. - */ -#if !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_PIOSC) && \ - !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_LFIOSC) && \ - !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_MOSC) && \ - !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_RTCOSC) -#error "Invalid value for TIVA_RSCLKCFG_OSCSRC defined" -#endif - -#if TIVA_XTAL_VALUE == 4000000 -#define TIVA_XTAL_ (0x06 << 6) -#elif TIVA_XTAL_VALUE == 4096000 -#define TIVA_XTAL_ (0x07 << 6) -#elif TIVA_XTAL_VALUE == 4915200 -#define TIVA_XTAL_ (0x08 << 6) -#elif TIVA_XTAL_VALUE == 5000000 -#define TIVA_XTAL_ (0x09 << 6) -#elif TIVA_XTAL_VALUE == 5120000 -#define TIVA_XTAL_ (0x0a << 6) -#elif TIVA_XTAL_VALUE == 6000000 -#define TIVA_XTAL_ (0x0b << 6) -#elif TIVA_XTAL_VALUE == 6144000 -#define TIVA_XTAL_ (0x0c << 6) -#elif TIVA_XTAL_VALUE == 7372800 -#define TIVA_XTAL_ (0x0d << 6) -#elif TIVA_XTAL_VALUE == 8000000 -#define TIVA_XTAL_ (0x0e << 6) -#elif TIVA_XTAL_VALUE == 8192000 -#define TIVA_XTAL_ (0x0f << 6) -#elif TIVA_XTAL_VALUE == 10000000 -#define TIVA_XTAL_ (0x10 << 6) -#elif TIVA_XTAL_VALUE == 12000000 -#define TIVA_XTAL_ (0x11 << 6) -#elif TIVA_XTAL_VALUE == 12288000 -#define TIVA_XTAL_ (0x12 << 6) -#elif TIVA_XTAL_VALUE == 13560000 -#define TIVA_XTAL_ (0x13 << 6) -#elif TIVA_XTAL_VALUE == 14318180 -#define TIVA_XTAL_ (0x14 << 6) -#elif TIVA_XTAL_VALUE == 16000000 -#define TIVA_XTAL_ (0x15 << 6) -#elif TIVA_XTAL_VALUE == 16384000 -#define TIVA_XTAL_ (0x16 << 6) -#elif TIVA_XTAL_VALUE == 18000000 -#define TIVA_XTAL_ (0x17 << 6) -#elif TIVA_XTAL_VALUE == 20000000 -#define TIVA_XTAL_ (0x18 << 6) -#elif TIVA_XTAL_VALUE == 24000000 -#define TIVA_XTAL_ (0x19 << 6) -#elif TIVA_XTAL_VALUE == 25000000 -#define TIVA_XTAL_ (0x1a << 6) -#else -#error "Invalid value for TIVA_XTAL_VALUE defined" -#endif - -/* -#if TIVA_MOSC_ENABLE == TRUE -#define TIVA_MOSCDIS (0 << 0) -#define TIVA_XTAL TIVA_XTAL_ -#elif TIVA_MOSC_ENABLE == FALSE -#define TIVA_MOSCDIS (1 << 0) -#define TIVA_XTAL 0 -#else -#error "Invalid value for TIVA_MOSC_ENABLE defined" -#endif - -#if TIVA_DIV400_ENABLE == TRUE -#define TIVA_DIV400 (1 << 30) -#elif TIVA_DIV400_ENABLE == FALSE -#define TIVA_DIV400 (0 << 30) -#else -#error "Invalid value for TIVA_DIV400_ENABLE defined" -#endif - -#if (TIVA_SYSDIV_VALUE >= 0x02) && (TIVA_SYSDIV_VALUE <= 0x3f) -#define TIVA_SYSDIV (TIVA_SYSDIV_VALUE << 23) -#define TIVA_SYSDIV2 (TIVA_SYSDIV_VALUE << 23) -#else -#error "Invalid value for TIVA_SYSDIV_VALUE defined" -#endif - -#if TIVA_USESYSDIV_ENABLE == TRUE -#define TIVA_USESYSDIV (1 << 22) -#elif TIVA_USESYSDIV_ENABLE == FALSE -#define TIVA_USESYSDIV (0 << 22) -#else -#error "Invalid value for TIVA_USESYSDIV_ENABLE defined" -#endif - -#if TIVA_SYSDIV2LSB_ENABLE == TRUE -#define TIVA_SYSDIV2LSB (1 << 22) -#elif TIVA_SYSDIV2LSB_ENABLE == FALSE -#define TIVA_SYSDIV2LSB (0 << 22) -#else -#error "Invalid value for TIVA_SYSDIV2LSB_ENABLE defined" -#endif - -#if TIVA_BYPASS_ENABLE == TRUE -#define TIVA_SRC 16000000 -#define TIVA_BYPASS (1 << 11) -#elif TIVA_BYPASS_ENABLE == FALSE -#define TIVA_SRC (200000000 + ((TIVA_DIV400 >> 30) * 200000000)) -#define TIVA_BYPASS (0 << 11) -#else -#error "Invalid value for TIVA_BYPASS_ENABLE defined" -#endif - -#if (TIVA_OSCSRC == TIVA_RCC_OSCSRC_MOSC) && (TIVA_MOSC_ENABLE == FALSE) -#error "Main Oscillator selected but not enabled" -#endif -*/ -/* - * System Clock calculation - * TODO: dynamic TIVA_SYSCLK value - */ -#define TIVA_SYSCLK 120000000 - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/* Various helpers.*/ -#include "nvic.h" -#include "tiva_isr.h" - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void tiva_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_LLD_H */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/platform.mk b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/platform.mk deleted file mode 100644 index b8363f3..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/platform.mk +++ /dev/null @@ -1,14 +0,0 @@ -# List of all the TM4C129x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_st_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_serial_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_mac_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_ext_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_wdg_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/tiva_isr.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/tiva_isr.h deleted file mode 100644 index 255bfd6..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/tiva_isr.h +++ /dev/null @@ -1,569 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TM4C129x/tiva_isr.h - * @brief TM4C129x ISR remapper driver header. - * - * @addtogroup TM4C129x_ISR - * @{ - */ - -#ifndef _TIVA_ISR_H_ -#define _TIVA_ISR_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name ISR names and numbers remapping - * @{ - */ - -/* GPIO units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) -#define TIVA_GPIOA_HANDLER Vector40 -#define TIVA_GPIOB_HANDLER Vector44 -#define TIVA_GPIOC_HANDLER Vector48 -#define TIVA_GPIOD_HANDLER Vector4C -#define TIVA_GPIOE_HANDLER Vector50 -#define TIVA_GPIOF_HANDLER VectorB8 -#define TIVA_GPIOG_HANDLER VectorBC -#define TIVA_GPIOH_HANDLER VectorC0 -#define TIVA_GPIOJ_HANDLER Vector10C -#define TIVA_GPIOK_HANDLER Vector110 -#define TIVA_GPIOL_HANDLER Vector114 -#define TIVA_GPIOM_HANDLER Vector160 -#define TIVA_GPION_HANDLER Vector164 -#define TIVA_GPIOP0_HANDLER Vector170 -#define TIVA_GPIOP1_HANDLER Vector174 -#define TIVA_GPIOP2_HANDLER Vector178 -#define TIVA_GPIOP3_HANDLER Vector17C -#define TIVA_GPIOP4_HANDLER Vector180 -#define TIVA_GPIOP5_HANDLER Vector184 -#define TIVA_GPIOP6_HANDLER Vector188 -#define TIVA_GPIOP7_HANDLER Vector18C -#define TIVA_GPIOQ0_HANDLER Vector190 -#define TIVA_GPIOQ1_HANDLER Vector194 -#define TIVA_GPIOQ2_HANDLER Vector198 -#define TIVA_GPIOQ3_HANDLER Vector19C -#define TIVA_GPIOQ4_HANDLER Vector1A0 -#define TIVA_GPIOQ5_HANDLER Vector1A4 -#define TIVA_GPIOQ6_HANDLER Vector1A8 -#define TIVA_GPIOQ7_HANDLER Vector1AC - -#define TIVA_GPIOA_NUMBER 0 -#define TIVA_GPIOB_NUMBER 1 -#define TIVA_GPIOC_NUMBER 2 -#define TIVA_GPIOD_NUMBER 3 -#define TIVA_GPIOE_NUMBER 4 -#define TIVA_GPIOF_NUMBER 30 -#define TIVA_GPIOG_NUMBER 31 -#define TIVA_GPIOH_NUMBER 32 -#define TIVA_GPIOJ_NUMBER 51 -#define TIVA_GPIOK_NUMBER 52 -#define TIVA_GPIOL_NUMBER 53 -#define TIVA_GPIOM_NUMBER 72 -#define TIVA_GPION_NUMBER 73 -#define TIVA_GPIOP0_NUMBER 76 -#define TIVA_GPIOP1_NUMBER 77 -#define TIVA_GPIOP2_NUMBER 78 -#define TIVA_GPIOP3_NUMBER 79 -#define TIVA_GPIOP4_NUMBER 80 -#define TIVA_GPIOP5_NUMBER 81 -#define TIVA_GPIOP6_NUMBER 82 -#define TIVA_GPIOP7_NUMBER 83 -#define TIVA_GPIOQ0_NUMBER 84 -#define TIVA_GPIOQ1_NUMBER 85 -#define TIVA_GPIOQ2_NUMBER 86 -#define TIVA_GPIOQ3_NUMBER 87 -#define TIVA_GPIOQ4_NUMBER 88 -#define TIVA_GPIOQ5_NUMBER 89 -#define TIVA_GPIOQ6_NUMBER 90 -#define TIVA_GPIOQ7_NUMBER 91 -#endif -#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\ - || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_GPIOA_HANDLER Vector40 -#define TIVA_GPIOB_HANDLER Vector44 -#define TIVA_GPIOC_HANDLER Vector48 -#define TIVA_GPIOD_HANDLER Vector4C -#define TIVA_GPIOE_HANDLER Vector50 -#define TIVA_GPIOF_HANDLER VectorB8 -#define TIVA_GPIOG_HANDLER VectorBC -#define TIVA_GPIOH_HANDLER VectorC0 -#define TIVA_GPIOJ_HANDLER Vector10C -#define TIVA_GPIOK_HANDLER Vector110 -#define TIVA_GPIOL_HANDLER Vector114 -#define TIVA_GPIOM_HANDLER Vector160 -#define TIVA_GPION_HANDLER Vector164 -#define TIVA_GPIOP0_HANDLER Vector170 -#define TIVA_GPIOP1_HANDLER Vector174 -#define TIVA_GPIOP2_HANDLER Vector178 -#define TIVA_GPIOP3_HANDLER Vector17C -#define TIVA_GPIOP4_HANDLER Vector180 -#define TIVA_GPIOP5_HANDLER Vector184 -#define TIVA_GPIOP6_HANDLER Vector188 -#define TIVA_GPIOP7_HANDLER Vector18C -#define TIVA_GPIOQ0_HANDLER Vector190 -#define TIVA_GPIOQ1_HANDLER Vector194 -#define TIVA_GPIOQ2_HANDLER Vector198 -#define TIVA_GPIOQ3_HANDLER Vector19C -#define TIVA_GPIOQ4_HANDLER Vector1A0 -#define TIVA_GPIOQ5_HANDLER Vector1A4 -#define TIVA_GPIOQ6_HANDLER Vector1A8 -#define TIVA_GPIOQ7_HANDLER Vector1AC -#define TIVA_GPIOR_HANDLER Vector1B0 -#define TIVA_GPIOS_HANDLER Vector1B4 -#define TIVA_GPIOT_HANDLER Vector1FC - -#define TIVA_GPIOA_NUMBER 0 -#define TIVA_GPIOB_NUMBER 1 -#define TIVA_GPIOC_NUMBER 2 -#define TIVA_GPIOD_NUMBER 3 -#define TIVA_GPIOE_NUMBER 4 -#define TIVA_GPIOF_NUMBER 30 -#define TIVA_GPIOG_NUMBER 31 -#define TIVA_GPIOH_NUMBER 32 -#define TIVA_GPIOJ_NUMBER 51 -#define TIVA_GPIOK_NUMBER 52 -#define TIVA_GPIOL_NUMBER 53 -#define TIVA_GPIOM_NUMBER 72 -#define TIVA_GPION_NUMBER 73 -#define TIVA_GPIOP0_NUMBER 76 -#define TIVA_GPIOP1_NUMBER 77 -#define TIVA_GPIOP2_NUMBER 78 -#define TIVA_GPIOP3_NUMBER 79 -#define TIVA_GPIOP4_NUMBER 80 -#define TIVA_GPIOP5_NUMBER 81 -#define TIVA_GPIOP6_NUMBER 82 -#define TIVA_GPIOP7_NUMBER 83 -#define TIVA_GPIOQ0_NUMBER 84 -#define TIVA_GPIOQ1_NUMBER 85 -#define TIVA_GPIOQ2_NUMBER 86 -#define TIVA_GPIOQ3_NUMBER 87 -#define TIVA_GPIOQ4_NUMBER 88 -#define TIVA_GPIOQ5_NUMBER 89 -#define TIVA_GPIOQ6_NUMBER 90 -#define TIVA_GPIOQ7_NUMBER 91 -#define TIVA_GPIOR_NUMBER 92 -#define TIVA_GPIOS_NUMBER 93 -#define TIVA_GPIOT_NUMBER 111 -#endif - -/* EPI units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_EPI0_HANDLER Vector108 - -#define TIVA_EPI0_NUMBER 50 -#endif - -/* CRC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -/* CRC has no interrupts.*/ -#endif - -/* AES Accelerator units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) -/* no interrupts.*/ -#endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) -#define TIVA_AES_HANDLER Vector1BC - -#define TIVA_AES_NUMBER 95 -#endif - -/* DES Accelerator units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) -/* no interrupts.*/ -#endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) -#define TIVA_DES_HANDLER Vector1C0 - -#define TIVA_DES_NUMBER 51 -#endif - -/* SHA/MD5 Accelerator units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) -/* no interrupts.*/ -#endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) -#define TIVA_SHA_MD5_HANDLER Vector1B8 - -#define TIVA_SHA_MD5_NUMBER 94 -#endif - -/* GPT units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_GPT0A_HANDLER Vector8C -#define TIVA_GPT0B_HANDLER Vector90 -#define TIVA_GPT1A_HANDLER Vector94 -#define TIVA_GPT1B_HANDLER Vector98 -#define TIVA_GPT2A_HANDLER Vector9C -#define TIVA_GPT2B_HANDLER VectorA0 -#define TIVA_GPT3A_HANDLER VectorCC -#define TIVA_GPT3B_HANDLER VectorD0 -#define TIVA_GPT4A_HANDLER Vector13C -#define TIVA_GPT4B_HANDLER Vector140 -#define TIVA_GPT5A_HANDLER Vector144 -#define TIVA_GPT5B_HANDLER Vector148 -#define TIVA_GPT6A_HANDLER Vector1C8 -#define TIVA_GPT6B_HANDLER Vector1CC -#define TIVA_GPT7A_HANDLER Vector1D0 -#define TIVA_GPT7B_HANDLER Vector1D4 - -#define TIVA_GPT0A_NUMBER 19 -#define TIVA_GPT0B_NUMBER 20 -#define TIVA_GPT1A_NUMBER 21 -#define TIVA_GPT1B_NUMBER 22 -#define TIVA_GPT2A_NUMBER 23 -#define TIVA_GPT2B_NUMBER 24 -#define TIVA_GPT3A_NUMBER 35 -#define TIVA_GPT3B_NUMBER 36 -#define TIVA_GPT4A_NUMBER 63 -#define TIVA_GPT4B_NUMBER 64 -#define TIVA_GPT5A_NUMBER 65 -#define TIVA_GPT5B_NUMBER 66 -#define TIVA_GPT6A_NUMBER 98 -#define TIVA_GPT6B_NUMBER 99 -#define TIVA_GPT7A_NUMBER 100 -#define TIVA_GPT7B_NUMBER 101 -#endif - -/* WDT units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_WDT_HANDLER Vector88 - -#define TIVA_WDT_NUMBER 18 -#endif - -/* ADC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_ADC0_SEQ0_HANDLER Vector78 -#define TIVA_ADC0_SEQ1_HANDLER Vector7C -#define TIVA_ADC0_SEQ2_HANDLER Vector80 -#define TIVA_ADC0_SEQ3_HANDLER Vector84 -#define TIVA_ADC1_SEQ0_HANDLER VectorF8 -#define TIVA_ADC1_SEQ1_HANDLER VectorFC -#define TIVA_ADC1_SEQ2_HANDLER Vector100 -#define TIVA_ADC1_SEQ3_HANDLER Vector104 - -#define TIVA_ADC0_SEQ0_NUMBER 14 -#define TIVA_ADC0_SEQ1_NUMBER 15 -#define TIVA_ADC0_SEQ2_NUMBER 16 -#define TIVA_ADC0_SEQ3_NUMBER 17 -#define TIVA_ADC1_SEQ0_NUMBER 46 -#define TIVA_ADC1_SEQ1_NUMBER 47 -#define TIVA_ADC1_SEQ2_NUMBER 48 -#define TIVA_ADC1_SEQ3_NUMBER 49 -#endif - -/* UART units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_UART0_HANDLER Vector54 -#define TIVA_UART1_HANDLER Vector58 -#define TIVA_UART2_HANDLER VectorC4 -#define TIVA_UART3_HANDLER Vector120 -#define TIVA_UART4_HANDLER Vector124 -#define TIVA_UART5_HANDLER Vector128 -#define TIVA_UART6_HANDLER Vector12C -#define TIVA_UART7_HANDLER Vector130 - -#define TIVA_UART0_NUMBER 5 -#define TIVA_UART1_NUMBER 6 -#define TIVA_UART2_NUMBER 33 -#define TIVA_UART3_NUMBER 56 -#define TIVA_UART4_NUMBER 57 -#define TIVA_UART5_NUMBER 58 -#define TIVA_UART6_NUMBER 59 -#define TIVA_UART7_NUMBER 60 -#endif - -/* QSSI units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_QSSI0_HANDLER Vector5C -#define TIVA_QSSI1_HANDLER VectorC8 -#define TIVA_QSSI2_HANDLER Vector118 -#define TIVA_QSSI3_HANDLER Vector11C - -#define TIVA_QSSI0_NUMBER 7 -#define TIVA_QSSI1_NUMBER 34 -#define TIVA_QSSI2_NUMBER 54 -#define TIVA_QSSI3_NUMBER 55 -#endif - -/* I2C units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_I2C0_HANDLER Vector60 -#define TIVA_I2C1_HANDLER VectorD4 -#define TIVA_I2C2_HANDLER Vector134 -#define TIVA_I2C3_HANDLER Vector138 -#define TIVA_I2C4_HANDLER Vector158 -#define TIVA_I2C5_HANDLER Vector15C -#define TIVA_I2C6_HANDLER Vector1D8 -#define TIVA_I2C7_HANDLER Vector1DC -#define TIVA_I2C8_HANDLER Vector1F4 -#define TIVA_I2C9_HANDLER Vector1F8 - -#define TIVA_I2C0_NUMBER 8 -#define TIVA_I2C1_NUMBER 37 -#define TIVA_I2C2_NUMBER 61 -#define TIVA_I2C3_NUMBER 62 -#define TIVA_I2C4_NUMBER 70 -#define TIVA_I2C5_NUMBER 71 -#define TIVA_I2C6_NUMBER 102 -#define TIVA_I2C7_NUMBER 103 -#define TIVA_I2C8_NUMBER 109 -#define TIVA_I2C9_NUMBER 110 -#endif - -/* 1-Wire Master units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) -#define TIVA_HAS_1WIRE FALSE -#endif -#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_1WIRE_HANDLER Vector1E4 - -#define TIVA_1WIRE_NUMBER 105 -#endif - -/* CAN units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_CAN0_HANDLER VectorD8 -#define TIVA_CAN1_HANDLER VectorDC - -#define TIVA_CAN0_NUMBER 38 -#define TIVA_CAN1_NUMBER 39 -#endif - -/* Ethernet MAC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\ - || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) -/* no interrupts.*/ -#endif -#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_MAC_HANDLER VectorE0 - -#define TIVA_MAC_NUMBER 40 -#endif - -/* Ethernet PHY units.*/ -#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \ - || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) -/* no interrupts.*/ -#endif -#if defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\ - || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -/* no interrupts.*/ -#endif - -/* USB units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_USB0_HANDLER VectorE8 - -#define TIVA_USB0_NUMBER 42 -#endif - -/* LCD units.*/ -#if defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_LCD_HANDLER Vector1C4 - -#define TIVA_LCD_NUMBER 97 -#endif -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) -/* no interrupts.*/ -#endif - -/* AC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_AC0_HANDLER VectorA4 -#define TIVA_AC1_HANDLER VectorA8 -#define TIVA_AC2_HANDLER VectorAC - -#define TIVA_AC0_NUMBER 25 -#define TIVA_AC1_NUMBER 26 -#define TIVA_AC2_NUMBER 27 -#endif - -/* PWM units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_PWM0FAULT_HANDLER Vector64 -#define TIVA_PWM0GEN0_HANDLER Vector68 -#define TIVA_PWM0GEN1_HANDLER Vector6C -#define TIVA_PWM0GEN2_HANDLER Vector70 -#define TIVA_PWM0GEN3_HANDLER VectorEC - -#define TIVA_PWM0FAULT_NUMBER 9 -#define TIVA_PWM0GEN0_NUMBER 10 -#define TIVA_PWM0GEN1_NUMBER 11 -#define TIVA_PWM0GEN2_NUMBER 12 -#define TIVA_PWM0GEN3_NUMBER 43 -#endif - -/* QEI units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_QEI0_HANLDER Vector74 - -#define TIVA_QEI0_NUMBER 13 -#endif - -/** - * @} - */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#endif /* _TIVA_ISR_H_ */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/tiva_registry.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/tiva_registry.h deleted file mode 100644 index 5815351..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/tiva_registry.h +++ /dev/null @@ -1,368 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TM4C129x/tiva_registry.h - * @brief TM4C123x capabilities registry. - * - * @addtogroup HAL - * @{ - */ - -#ifndef _TIVA_REGISTRY_H_ -#define _TIVA_REGISTRY_H_ - -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -/** - * @name TM4C129x capabilities - * @{ - */ - -/* GPIO attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) -#define TIVA_HAS_GPIOA TRUE -#define TIVA_HAS_GPIOB TRUE -#define TIVA_HAS_GPIOC TRUE -#define TIVA_HAS_GPIOD TRUE -#define TIVA_HAS_GPIOE TRUE -#define TIVA_HAS_GPIOF TRUE -#define TIVA_HAS_GPIOG TRUE -#define TIVA_HAS_GPIOH TRUE -#define TIVA_HAS_GPIOJ TRUE -#define TIVA_HAS_GPIOK TRUE -#define TIVA_HAS_GPIOL TRUE -#define TIVA_HAS_GPIOM TRUE -#define TIVA_HAS_GPION TRUE -#define TIVA_HAS_GPIOP TRUE -#define TIVA_HAS_GPIOQ TRUE -#define TIVA_HAS_GPIOR FALSE -#define TIVA_HAS_GPIOS FALSE -#define TIVA_HAS_GPIOT FALSE -#endif -#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\ - || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_GPIOA TRUE -#define TIVA_HAS_GPIOB TRUE -#define TIVA_HAS_GPIOC TRUE -#define TIVA_HAS_GPIOD TRUE -#define TIVA_HAS_GPIOE TRUE -#define TIVA_HAS_GPIOF TRUE -#define TIVA_HAS_GPIOG TRUE -#define TIVA_HAS_GPIOH TRUE -#define TIVA_HAS_GPIOJ TRUE -#define TIVA_HAS_GPIOK TRUE -#define TIVA_HAS_GPIOL TRUE -#define TIVA_HAS_GPIOM TRUE -#define TIVA_HAS_GPION TRUE -#define TIVA_HAS_GPIOP TRUE -#define TIVA_HAS_GPIOQ TRUE -#define TIVA_HAS_GPIOR TRUE -#define TIVA_HAS_GPIOS TRUE -#define TIVA_HAS_GPIOT TRUE -#endif - -/* EPI attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_EPI0 TRUE -#endif - -/* CRC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_CRC0 TRUE -#endif - -/* AES Accelerator attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) -#define TIVA_HAS_AES FALSE -#endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) -#define TIVA_HAS_AES TRUE -#endif - -/* DES Accelerator attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) -#define TIVA_HAS_DES FALSE -#endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) -#define TIVA_HAS_DES TRUE -#endif - -/* SHA/MD5 Accelerator attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) -#define TIVA_HAS_SHA_MD5 FALSE -#endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) -#define TIVA_HAS_SHA_MD5 TRUE -#endif - -/* GPT attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_GPT0 TRUE -#define TIVA_HAS_GPT1 TRUE -#define TIVA_HAS_GPT2 TRUE -#define TIVA_HAS_GPT3 TRUE -#define TIVA_HAS_GPT4 TRUE -#define TIVA_HAS_GPT5 TRUE -#define TIVA_HAS_GPT6 TRUE -#define TIVA_HAS_GPT7 TRUE -#define TIVA_HAS_WGPT0 FALSE -#define TIVA_HAS_WGPT1 FALSE -#define TIVA_HAS_WGPT2 FALSE -#define TIVA_HAS_WGPT3 FALSE -#define TIVA_HAS_WGPT4 FALSE -#define TIVA_HAS_WGPT5 FALSE -#endif - -/* WDT attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_WDT0 TRUE -#define TIVA_HAS_WDT1 TRUE -#endif - -/* ADC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_ADC0 TRUE -#define TIVA_HAS_ADC1 TRUE -#endif - -/* UART attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_UART0 TRUE -#define TIVA_HAS_UART1 TRUE -#define TIVA_HAS_UART2 TRUE -#define TIVA_HAS_UART3 TRUE -#define TIVA_HAS_UART4 TRUE -#define TIVA_HAS_UART5 TRUE -#define TIVA_HAS_UART6 TRUE -#define TIVA_HAS_UART7 TRUE -#endif - -/* QSSI attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_QSSI0 TRUE -#define TIVA_HAS_QSSI1 TRUE -#define TIVA_HAS_QSSI2 TRUE -#define TIVA_HAS_QSSI3 TRUE -#endif - -/* I2C attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_I2C0 TRUE -#define TIVA_HAS_I2C1 TRUE -#define TIVA_HAS_I2C2 TRUE -#define TIVA_HAS_I2C3 TRUE -#define TIVA_HAS_I2C4 TRUE -#define TIVA_HAS_I2C5 TRUE -#define TIVA_HAS_I2C6 TRUE -#define TIVA_HAS_I2C7 TRUE -#define TIVA_HAS_I2C8 TRUE -#define TIVA_HAS_I2C9 TRUE -#endif - -/* 1-Wire Master attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) -#define TIVA_HAS_1WIRE FALSE -#endif -#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_1WIRE TRUE -#endif - -/* CAN attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_CAN0 TRUE -#define TIVA_HAS_CAN1 TRUE -#endif - -/* Ethernet MAC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\ - || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) -#define TIVA_HAS_ETHERNET_MAC FALSE -#endif -#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_ETHERNET_MAC TRUE -#endif - -/* Ethernet PHY attributes.*/ -#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \ - || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) -#define TIVA_HAS_ETHERNET_PHY FALSE -#endif -#if defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\ - || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_ETHERNET_PHY TRUE -#endif - -/* USB attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_USB0 TRUE -#endif - -/* LCD attributes.*/ -#if defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_LCD TRUE -#endif -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) -#define TIVA_HAS_LCD FALSE -#endif - -/* AC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_AC0 TRUE -#define TIVA_HAS_AC1 TRUE -#define TIVA_HAS_AC2 TRUE -#endif - -/* PWM attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_PWM0 TRUE -#define TIVA_HAS_PWM1 FALSE -#endif - -/* QEI attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) -#define TIVA_HAS_QEI0 TRUE -#define TIVA_HAS_QEI1 FALSE -#endif - -/** - * @} - */ - -#endif /* _TIVA_REGISTRY_H_ */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/tm4c129x.h b/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/tm4c129x.h deleted file mode 100644 index 5a5f4f2..0000000 --- a/ChibiOS_16.1.5/community/os/hal/ports/TIVA/TM4C129x/tm4c129x.h +++ /dev/null @@ -1,1131 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @addtogroup CMSIS - * @{ - */ - -/** - * @addtogroup TM4C129x - * @{ - */ - -#ifndef __TM4C129x_H -#define __TM4C129x_H - -/** - * @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /**< MPU present */ -#define __NVIC_PRIO_BITS 3 /**< Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Use different SysTick Config */ -#define __FPU_PRESENT 1 /**< FPU present */ - -/** - * @brief TM4C129x Interrupt Number Definitions - */ -typedef enum IRQn -{ - /* TODO: check interrupt numbers with tm4c129 device */ - /***** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< Cortex-M4 Non-Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -3, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - /***** TM4C129x Specific Interrupt Numbers *********************************/ - GPIOA_IRQn = 0, /**< GPIO Port A */ - GPIOB_IRQn = 1, /**< GPIO Port B */ - GPIOC_IRQn = 2, /**< GPIO Port C */ - GPIOD_IRQn = 3, /**< GPIO Port D */ - GPIOE_IRQn = 4, /**< GPIO Port E */ - UART0_IRQn = 5, /**< UART0 */ - UART1_IRQn = 6, /**< UART1 */ - SSI0_IRQn = 7, /**< SSI0 */ - I2C0_IRQn = 8, /**< I2C0 */ - PWM0FAULT_IRQn = 9, /**< PWM0 Fault */ - PWM0GEN0_IRQn = 10, /**< PWM0 Generator 0 */ - PWM0GEN1_IRQn = 11, /**< PWM0 Generator 1 */ - PWM0GEN2_IRQn = 12, /**< PWM0 Generator 2 */ - QEI0_IRQn = 13, /**< QEI0 */ - ADC0SEQ0_IRQn = 14, /**< ADC0 Sequence 0 */ - ADC0SEQ1_IRQn = 15, /**< ADC0 Sequence 1 */ - ADC0SEQ2_IRQn = 16, /**< ADC0 Sequence 2 */ - ADC0SEQ3_IRQn = 17, /**< ADC0 Sequence 3 */ - WATCHDOG_IRQn = 18, /**< Watchdog Timers 0 and 1 */ - TIMER0A_IRQn = 19, /**< 16/32-Bit Timer 0A */ - TIMER0B_IRQn = 20, /**< 16/32-Bit Timer 0B */ - TIMER1A_IRQn = 21, /**< 16/32-Bit Timer 1A */ - TIMER1B_IRQn = 22, /**< 16/32-Bit Timer 1B */ - TIMER2A_IRQn = 23, /**< 16/32-Bit Timer 2A */ - TIMER2B_IRQn = 24, /**< 16/32-Bit Timer 2B */ - ACOMP0_IRQn = 25, /**< Analog Comparator 0 */ - ACOMP1_IRQn = 26, /**< Analog Comparator 1 */ - SYSCON_IRQn = 28, /**< System Control */ - FMCEECON_IRQn = 29, /**< Flash Memory Control and EEPROM Control */ - GPIOF_IRQn = 30, /**< GPIO Port F */ - UART2_IRQn = 33, /**< UART2 */ - SSI1_IRQn = 34, /**< SSI1 */ - TIMER3A_IRQn = 35, /**< 16/32-Bit Timer 3A */ - TIMER3B_IRQn = 36, /**< 16/32-Bit Timer 3B */ - I2C1_IRQn = 37, /**< I2C1 */ - QEI1_IRQn = 38, /**< QEI1 */ - CAN0_IRQn = 39, /**< CAN0 */ - CAN1_IRQn = 40, /**< CAN1 */ - HIBMODULE_IRQn = 43, /**< Hibernation Module */ - USB_IRQn = 44, /**< USB */ - PWM0GEN3_IRQn = 45, /**< PWM0 Generator 3 */ - UDMASFW_IRQn = 46, /**< UDMA Software */ - UDMAERR_IRQn = 47, /**< UDMA Error */ - ADC1SEQ0_IRQn = 48, /**< ADC1 Sequence 0 */ - ADC1SEQ1_IRQn = 49, /**< ADC1 Sequence 1 */ - ADC1SEQ2_IRQn = 50, /**< ADC1 Sequence 2 */ - ADC1SEQ3_IRQn = 51, /**< ADC1 Sequence 3 */ - SSI2_IRQn = 57, /**< SSI2 */ - SSI3_IRQn = 58, /**< SSI3 */ - UART3_IRQn = 59, /**< UART3 */ - UART4_IRQn = 60, /**< UART4 */ - UART5_IRQn = 61, /**< UART5 */ - UART6_IRQn = 62, /**< UART6 */ - UART7_IRQn = 63, /**< UART7 */ - I2C2_IRQn = 68, /**< I2C2 */ - I2C3_IRQn = 69, /**< I2C3 */ - TIMER4A_IRQn = 70, /**< 16/32-Bit Timer 4A */ - TIMER4B_IRQn = 71, /**< 16/32-Bit Timer 4B */ - TIMER5A_IRQn = 92, /**< 16/32-Bit Timer 5A */ - TIMER5B_IRQn = 93, /**< 16/32-Bit Timer 5B */ - WTIMER0A_IRQn = 94, /**< 32/64-Bit Timer 0A */ - WTIMER0B_IRQn = 95, /**< 32/64-Bit Timer 0B */ - WTIMER1A_IRQn = 96, /**< 32/64-Bit Timer 1A */ - WTIMER1B_IRQn = 97, /**< 32/64-Bit Timer 1B */ - WTIMER2A_IRQn = 98, /**< 32/64-Bit Timer 2A */ - WTIMER2B_IRQn = 99, /**< 32/64-Bit Timer 2B */ - WTIMER3A_IRQn = 100, /**< 32/64-Bit Timer 3A */ - WTIMER3B_IRQn = 101, /**< 32/64-Bit Timer 3B */ - WTIMER4A_IRQn = 102, /**< 32/64-Bit Timer 4A */ - WTIMER4B_IRQn = 103, /**< 32/64-Bit Timer 4B */ - WTIMER5A_IRQn = 104, /**< 32/64-Bit Timer 5A */ - WTIMER5B_IRQn = 105, /**< 32/64-Bit Timer 5B */ - SYSEXCEPT_IRQn = 106, /**< System Exception (imprecise) */ - PWM1GEN0_IRQn = 134, /**< PWM1 Generator 0 */ - PWM1GEN1_IRQn = 135, /**< PWM1 Generator 1 */ - PWM1GEN2_IRQn = 136, /**< PWM1 Generator 2 */ - PWM1GEN3_IRQn = 137, /**< PWM1 Generator 3 */ - PWM1FAULT_IRQn = 138 /**< PWM1 Fault */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals.*/ -#include <stdint.h> - -/** - * @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog Comparator - */ -typedef struct -{ - __IO uint32_t MIS; /**< Masked Interrupt Status */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t INTEN; /**< Interrupt Enable */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t REFCTL; /**< Reference Voltage Control */ - __I uint32_t _RESERVED1[3]; /**< Reserved */ - __I uint32_t STAT0; /**< Status 0 */ - __IO uint32_t CTL0; /**< Control 0 */ - __I uint32_t _RESERVED2[6]; /**< Reserved */ - __I uint32_t STAT1; /**< Status 1 */ - __IO uint32_t CTL1; /**< Control 1 */ - __I uint32_t _RESERVED3[990];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ -} ACMP_TypeDef; - -/** - * @brief Analog-to-Digital Converter - */ -typedef struct -{ - __IO uint32_t MUX; /**< Sample Sequence Input Multiplexer - Select */ - __IO uint32_t CTL; /**< Sample Sequence Control */ - __I uint32_t FIFO; /**< Sample Sequence Result FIFO */ - __I uint32_t FSTAT; /**< Sample Sequence FIFO Status */ - __IO uint32_t OP; /**< Sample Sequence Operation */ - __IO uint32_t DC; /**< Sample Sequence Digital Comparator - Select */ - __I uint32_t _RESERVED0[2]; /**< Reserved */ -} ADC_SS_t; - -typedef struct -{ - __IO uint32_t ACTSS; /**< Active Sample Sequencer */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t IM; /**< Interrupt Mask */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ - __IO uint32_t OSTAT; /**< Overflow Status */ - __IO uint32_t EMUX; /**< Event Multiplexer Select */ - __IO uint32_t USTAT; /**< Underflow Status */ - __IO uint32_t TSSEL; /**< Trigger Source Select */ - __IO uint32_t SSPRI; /**< Sample Sequencer Priority */ - __IO uint32_t SPC; /**< Sample Phase Control */ - __IO uint32_t PSSI; /**< Processor Sample Sequence Initiate */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t SAC; /**< Sample Averaging Control */ - __IO uint32_t DCISC; /**< Digital Comparator Interrupt Status and - Clear */ - __IO uint32_t CTL; /**< Control */ - __I uint32_t _RESERVED1[1]; /**< Reserved */ - ADC_SS_t SS[4]; /**< Sample Sequence 0, 1, 2 and 3 */ - __I uint32_t _RESERVED2[784];/**< Reserved */ - __O uint32_t DCRIC; /**< Digital Comparator Reset Initial - Conditions */ - __I uint32_t _RESERVED3[63]; /**< Reserved */ - __IO uint32_t DCCTL[8]; /**< Digital Comparator Control 0 - 7 */ - __I uint32_t _RESERVED4[8]; /**< Reserved */ - __IO uint32_t DCCMP[8]; /**< Digital Comparator Range 0 - 7 */ - __I uint32_t _RESERVED5[88]; /**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ - __IO uint32_t PC; /**< Peripheral Configuration */ - __IO uint32_t CC; /**< Clock Configuration */ -} ADC_TypeDef; - -/** - * @brief Controller Area Network - */ -typedef struct -{ - __IO uint32_t CRQ; /**< Command Request */ - __IO uint32_t CMSK; /**< Command Mask */ - __IO uint32_t MSK[2]; /**< Mask 1 and 2 */ - __IO uint32_t ARB[2]; /**< Arbitration 1 and 2 */ - __IO uint32_t MCTL; /**< Message Control */ - __IO uint32_t DA[2]; /**< Data A1 and A2 */ - __IO uint32_t DB[2]; /**< Data B1 and B2 */ - __I uint32_t _RESERVED0[13]; /**< Reserved */ -} CAN_INTERFACE_t; - -typedef struct -{ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t STS; /**< Status */ - __I uint32_t ERR; /**< Error Counter */ - __IO uint32_t BIT; /**< Bit Timing */ - __I uint32_t INT; /**< Interrupt */ - __IO uint32_t TST; /**< Test */ - __IO uint32_t BRPE; /**< Baud Rate Prescaler Extension */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - CAN_INTERFACE_t IF[2]; /**< IF1 and IF2 */ - __I uint32_t _RESERVED1[8]; /**< Reserved */ - __I uint32_t TXRQ[2]; /**< Transmission Request 1 and 2 */ - __I uint32_t _RESERVED2[6]; /**< Reserved */ - __I uint32_t NWDA[2]; /**< New Data 1 and 2 */ - __I uint32_t _RESERVED3[6]; /**< Reserved */ - __I uint32_t MSGINT[2]; /**< Message 1 and 2 Interrupt Pending */ - __I uint32_t _RESERVED4[6]; /**< Reserved */ - __I uint32_t MSGVAL[2]; /**< Message 1 and 2 Valid */ -} CAN_TypeDef; - -/** - * @brief EEPROM Memory - */ -typedef struct -{ - __IO uint32_t EESIZE; /**< Size Information */ - __IO uint32_t EEBLOCK; /**< Current Block */ - __IO uint32_t EEOFFSET; /**< Current Offset */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t EERDWR; /**< Read-Write */ - __IO uint32_t EERDWRINC; /**< Read-Write with Increment */ - __IO uint32_t EEDONE; /**< Done Status */ - __IO uint32_t EESUPP; /**< Support Control and Status */ - __IO uint32_t EEUNLOCK; /**< Unlock */ - __I uint32_t _RESERVED1[3]; /**< Reserved */ - __IO uint32_t EEPROT; /**< Protection */ - __IO uint32_t EEPASS[3]; /**< Password */ - __IO uint32_t EEINT; /**< Interrupt */ - __I uint32_t _RESERVED2[3]; /**< Reserved */ - __IO uint32_t EEHIDE; /**< Block Hide */ - __I uint32_t _RESERVED3[11]; /**< Reserved */ - __IO uint32_t EEDBGME; /**< Debug Mass Erase */ - __I uint32_t _RESERVED4[975];/**< Reserved */ - __IO uint32_t EEPROMPP; /**< Peripheral Properties */ -} EEPROM_TypeDef; - -/** - * @brief Flash Memory - */ -typedef struct -{ - __IO uint32_t FMA; /**< Flash Memory Address */ - __IO uint32_t FMD; /**< Flash Memory Data */ - __IO uint32_t FMC; /**< Flash Memory Control */ - __I uint32_t FCRIS; /**< Flash Controller Raw Interrupt Status */ - __IO uint32_t FCIM; /**< Flash Controller Interrupt Mask */ - __IO uint32_t FCMISC; /**< Masked Interrupt Status and Clear */ - __I uint32_t _RESERVED0[2]; /**< Reserved */ - __IO uint32_t FMC2; /**< Flash Memory Control 2 */ - __I uint32_t _RESERVED1[3]; /**< Reserved */ - __IO uint32_t FWBVAL; /**< Flash Write Buffer Valid */ - __I uint32_t _RESERVED2[51]; /**< Reserved */ - __IO uint32_t FWBN; /**< Flash Write Buffer n */ - __I uint32_t _RESERVED3[943];/**< Reserved */ - __I uint32_t FSIZE; /**< Flash Size */ - __I uint32_t SSIZE; /**< SRAM Size */ - __I uint32_t _RESERVED4[1]; /**< Reserved */ - __IO uint32_t ROMSWMAP; /**< ROM Software Map */ -} FLASH_TypeDef; - - - -/** - * @brief General Purpose Input/Outputs - */ -typedef struct -{ - union { - __IO uint32_t MASKED_ACCESS[256]; /**< Masked access of Data Register */ - struct { - __I uint32_t _RESERVED0[255]; /**< Reserved */ - __IO uint32_t DATA; /**< Data */ - }; - }; - __IO uint32_t DIR; /**< Direction */ - __IO uint32_t IS; /**< Interrupt Sense */ - __IO uint32_t IBE; /**< Interrupt Both Edges */ - __IO uint32_t IEV; /**< Interrupt Event */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t AFSEL; /**< Alternate Function Select */ - __I uint32_t _RESERVED1[55]; /**< Reserved */ - __IO uint32_t DR2R; /**< 2-mA Drive Select */ - __IO uint32_t DR4R; /**< 4-mA Drive Select */ - __IO uint32_t DR8R; /**< 8-mA Drive Select */ - __IO uint32_t ODR; /**< Open Drain Select */ - __IO uint32_t PUR; /**< Pull-Up Select */ - __IO uint32_t PDR; /**< Pull-Down Select */ - __IO uint32_t SLR; /**< Slew Rate Control Select */ - __IO uint32_t DEN; /**< Digital Enable */ - __IO uint32_t LOCK; /**< Lock */ - __IO uint32_t CR; /**< Commit */ - __IO uint32_t AMSEL; /**< Analog Mode Select */ - __IO uint32_t PCTL; /**< Port Control */ - __IO uint32_t ADCCTL; /**< ADC Control */ - __IO uint32_t DMACTL; /**< DMA Control */ - __IO uint32_t SI; /**< */ - __IO uint32_t DR12R; /**< */ - __IO uint32_t WAKEPEN; /**< */ - __IO uint32_t WAKELVL; /**< */ - __IO uint32_t WAKESTAT; /**< */ - __I uint32_t _RESERVED2[669];/**< */ - __I uint32_t PP; /**< */ - __IO uint32_t PC; /**< */ -} GPIO_TypeDef; - -/** - * @brief General Purpose Timer - */ -typedef struct -{ - __IO uint32_t CFG; /**< Configuration */ - __IO uint32_t TAMR; /**< Timer A Mode */ - __IO uint32_t TBMR; /**< Timer B Mode */ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t SYNC; /**< Synchronize */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t IMR; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t TAILR; /**< Timer A Interval Load */ - __IO uint32_t TBILR; /**< Timer B Interval Load */ - __IO uint32_t TAMATCHR; /**< Timer A Match */ - __IO uint32_t TBMATCHR; /**< Timer B Match */ - __IO uint32_t TAPR; /**< Timer A Prescale */ - __IO uint32_t TBPR; /**< Timer B Prescale */ - __IO uint32_t TAPMR; /**< Timer A Prescale Match */ - __IO uint32_t TBPMR; /**< Timer B Prescale Match */ - __I uint32_t TAR; /**< Timer A */ - __I uint32_t TBR; /**< Timer B */ - __IO uint32_t TAV; /**< Timer A Value */ - __IO uint32_t TBV; /**< Timer B Value */ - __I uint32_t RTCPD; /**< RTC Predivide */ - __I uint32_t TAPS; /**< Timer A Prescale Snapshot */ - __I uint32_t TBPS; /**< Timer B Prescale Snapshot */ - __I uint32_t TAPV; /**< Timer A Prescale Value */ - __I uint32_t TBPV; /**< Timer B Prescale Value */ - __I uint32_t _RESERVED1[981];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ -} GPT_TypeDef; - -/** - * @brief Hibernation Module - */ -typedef struct -{ - __I uint32_t RTCC; /**< RTC Counter */ - __IO uint32_t RTCM0; /**< RTC Match 0 */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t RTCLD; /**< RTC Load */ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __IO uint32_t IC; /**< Interrupt Clear */ - __IO uint32_t RTCT; /**< RTC Trim */ - __IO uint32_t RTCSS; /**< RTC Sub Seconds */ - __I uint32_t _RESERVED1[1]; /**< Reserved */ - __IO uint32_t DATA; /**< Data */ -} HIB_TypeDef; - -/** - * @brief Inter-Integrated Circuit - */ -typedef struct -{ - __IO uint32_t MSA; /**< Master Slave Address */ - __IO uint32_t MCS; /**< Master Control/Status */ - __IO uint32_t MDR; /**< Master Data */ - __IO uint32_t MTPR; /**< Master Timer Period */ - __IO uint32_t MIMR; /**< Master Interrupt Mask */ - __I uint32_t MRIS; /**< Master Raw Interrupt Status */ - __IO uint32_t MMIS; /**< Master Masked Interrupt Status */ - __O uint32_t MICR; /**< Master Interrupt Clear */ - __IO uint32_t MCR; /**< Master Configuration */ - __IO uint32_t MCLKOCNT; /**< Master Clock Low Timeout Count */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __I uint32_t MBMON; /**< Master Bus Monitor */ - __IO uint32_t MCR2; /**< Master Configuration 2 */ - __I uint32_t _RESERVED1[497];/**< Reserved */ - __IO uint32_t SOAR; /**< Slave Own Address */ - __IO uint32_t SCSR; /**< Slave Control/Status */ - __IO uint32_t SDR; /**< Slave Data */ - __IO uint32_t SIMR; /**< Slave Interrupt Mask */ - __I uint32_t SRIS; /**< Slave Raw Interrupt Status */ - __I uint32_t SMIS; /**< Slave Masked Interrupt Status */ - __O uint32_t SICR; /**< Slave Interrupt Clear */ - __IO uint32_t SOAR2; /**< Slave Own Address 2 */ - __IO uint32_t SACKCTL; /**< Slave ACK Control */ - __I uint32_t _RESERVED2[487];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ - __I uint32_t PC; /**< Peripheral Configuration */ -} I2C_TypeDef; - -/* - * @brief Pulse Width Modulator - */ -typedef struct -{ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t INTEN; /**< Interrupt and Trigger Enable */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ - __IO uint32_t LOAD; /**< Load */ - __I uint32_t COUNT; /**< Counter */ - __IO uint32_t CMP[2]; /**< Compare A, B */ - __IO uint32_t GEN[2]; /**< Generator A, B Control */ - __IO uint32_t DBCTL; /**< Dead-Band Control */ - __IO uint32_t DBRISE; /**< Dead-Band Rising-Edge Delay */ - __IO uint32_t DBFALL; /**< Dead-Band Falling-Edge Delay */ - __IO uint32_t FLTSRC[2]; /**< Fault Source 0, 1 */ - __IO uint32_t MINFLTPER; /**< Minimum Fault Period */ -} PWM_GENERATOR_T; - -typedef struct -{ - union { - __IO uint32_t SEN; /**< Fault Pin Logic Sense, for GEN 0 and 1 */ - __I uint32_t _RESERVED0[1];/**< Reserved, for GEN 2 and 3 */ - }; - __IO uint32_t STAT[2]; /**< Fault Status */ - __I uint32_t _RESERVED1[29]; /**< Reserved */ -} PWM_FLT_t; - -typedef struct -{ - __IO uint32_t CTL; /**< Master Control */ - __IO uint32_t SYNC; /**< Time Base Sync */ - __IO uint32_t ENABLE; /**< Output Enable */ - __IO uint32_t INVERT; /**< Output Inversion */ - __IO uint32_t FAULT; /**< Output Fault */ - __IO uint32_t INTEN; /**< Interrupt Enable */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ - __I uint32_t STATUS; /**< Status */ - __IO uint32_t FAULTVAL; /**< Fault Condition Value */ - __IO uint32_t ENUPD; /**< Enable Update */ - __I uint32_t _RESERVED0[5]; /**< Reserved */ - __IO PWM_GENERATOR_T PWM[4]; /**< PWM Generator 0, 1, 2 and 3 */ - __I uint32_t _RESERVED1[432];/**< Reserved */ - PWM_FLT_t FLT[4]; /**< Fault registers 0, 1, 2 and 3 */ - __I uint32_t _RESERVED2[368];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ -} PWM_TypeDef; - -/** - * @brief Quadrature Encoder Interface - */ -typedef struct -{ - __IO uint32_t CTL; /**< Control */ - __I uint32_t STAT; /**< Status */ - __IO uint32_t POS; /**< Position */ - __IO uint32_t MAXPOS; /**< Maximum Position */ - __IO uint32_t LOAD; /**< Timer Load */ - __I uint32_t TIME; /**< Timer */ - __I uint32_t COUNT; /**< Velocity Counter */ - __I uint32_t SPEED; /**< Velocity */ - __IO uint32_t INTEN; /**< Interrupt Enable */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ -} QEI_TypeDef; - -/** - * @brief Synchronous Serial Interface - */ -typedef struct -{ - __IO uint32_t CR[2]; /**< Control 0, 1 */ - __IO uint32_t DR; /**< Data */ - __I uint32_t SR; /**< Status */ - __IO uint32_t CPSR; /**< Clock Prescale */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t DMACTL; /**< DMA Control */ - __I uint32_t _RESERVED0[1000];/**< Reserved */ - __IO uint32_t CC; /**< Clock Configuration */ -} SSI_TypeDef; - -/** - * @brief System Control - */ -typedef struct -{ - __I uint32_t DID0; /**< Device Identification 0 */ - __I uint32_t DID1; /**< Device Identification 1 */ - __I uint32_t RESERVED0[12]; /**< Reserved */ - __IO uint32_t PBORCTL; /**< Power-Temp Brown Out Control */ - __I uint32_t RESERVED1[5]; /**< Reserved */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t IMC; /**< Interrupt Mask Control */ - __IO uint32_t MISC; /**< Interrupt Status and Clear */ - __IO uint32_t RESC; /**< Reset Cause */ - __IO uint32_t PWRTC; /**< Power-Temperature Cause */ - __IO uint32_t NMIC; /**< NMI Cause Register */ - __I uint32_t RESERVED2[5]; /**< Reserved */ - __IO uint32_t MOSCCTL; /**< Main Oscillator Control */ - __I uint32_t RESERVED3[12]; /**< Reserved */ - __IO uint32_t RSCLKCFG; /**< Run and Sleep Mode Configuration Register */ - __I uint32_t RESERVEDx[3]; - __IO uint32_t MEMTIM0; /**< Memory Timing Parameter Register 0 for Main Flash and EEPROM */ - __I uint32_t RESERVED4[29]; /**< Reserved */ - __IO uint32_t ALTCLKCFG; /**< Alternate Clock Configuration */ - __I uint32_t RESERVED5[2]; /**< Reserved */ - __IO uint32_t DSLPCLKCFG; /**< Deep Sleep Clock Configuration */ - __IO uint32_t DIVSCLK; /**< Divisor and Source Clock Configuration */ - __I uint32_t SYSPROP; /**< System Properties */ - __IO uint32_t PIOSCCAL; /**< PIOSC Calibration */ - __I uint32_t PIOSCSTAT; /**< PIOSC Statistics */ - __I uint32_t RESERVED6[2]; /**< Reserved */ - __IO uint32_t PLLFREQ0; /**< PLL Frequency 0 */ - __IO uint32_t PLLFREQ1; /**< PLL Frequency 1 */ - __I uint32_t PLLSTAT; /**< PLL Frequency Status */ - __I uint32_t RESERVED7[7]; /**< Reserved */ - __IO uint32_t SLPPWRCFG; /**< Sleep Power Configuration */ - __IO uint32_t DSLPPWRCFG; /**< Deep-Sleep Power Configuration */ - __I uint32_t RESERVED8[4]; /**< Reserved */ - __I uint32_t NVMSTAT; /**< Non-Volatile Memory Information */ - __I uint32_t RESERVED9[4]; /**< Reserved */ - __IO uint32_t LDOSPCTL; /**< LDO Sleep Power Control */ - __I uint32_t LDOSPCAL; /**< LDO Sleep Power Calibration */ - __IO uint32_t LDODPCTL; /**< LDO Deep-Sleep Power Control */ - __I uint32_t LDODPCAL; /**< LDO Deep-Sleep Power Calibration */ - __I uint32_t RESERVED10[2]; /**< Reserved */ - __I uint32_t SDPMST; /**< Sleep/Deep-Sleep Power Mode Status */ - __I uint32_t RESERVED11[2]; /**< Reserved */ - __IO uint32_t RESBEHAVCTL; /**< Reset Behavior Control Register */ - __I uint32_t RESERVED12[6]; /**< Reserved */ - __IO uint32_t HSSR; /**< Hardware System Service Request */ - __I uint32_t RESERVED[34]; /**< Reserved */ - __I uint32_t USBPDS; /**< USB Power Domain Status */ - __IO uint32_t USBMPC; /**< USB Memory Power Control */ - __I uint32_t EMACPDS; /**< Ethernet MAC Power Domain Status */ - __IO uint32_t EMACMPC; /**< Ethernet MAC Memory Power Control */ - __I uint32_t RESERVED13[2]; /**< Reserved */ - __I uint32_t CAN0PDS; /**< CAN 0 Power Domain Status */ - __IO uint32_t CAN0MPC; /**< CAN 0 Memory Power Control */ - __I uint32_t CAN1PDS; /**< CAN 1 Power Domain Status */ - __IO uint32_t CAN1MPC; /**< CAN 1 Memory Power Control */ - __I uint32_t RESERVED14[22]; /**< Reserved */ - __I uint32_t PPWD; /**< WDT Peripheral Present */ - __I uint32_t PPTIMER; /**< GPT Peripheral Present */ - __I uint32_t PPGPIO; /**< GPIO Peripheral Present */ - __I uint32_t PPDMA; /**< UDMA Peripheral Present */ - __I uint32_t PPEPI; /**< EPI Peripheral Present */ - __I uint32_t PPHIB; /**< HIB Peripheral Present */ - __I uint32_t PPUART; /**< UART Peripheral Present */ - __I uint32_t PPSSI; /**< SSI Peripheral Present */ - __I uint32_t PPI2C; /**< I2C Peripheral Present */ - __I uint32_t RESERVED15[1]; /**< Reserved */ - __I uint32_t PPUSB; /**< USB Peripheral Present */ - __I uint32_t RESERVED16[1]; /**< Reserved */ - __I uint32_t PPEPHY; /**< Ethernet PHY Peripheral Present */ - __I uint32_t PPCAN; /**< CAN Peripheral Present */ - __I uint32_t PPADC; /**< ADC Peripheral Present */ - __I uint32_t PPACMP; /**< ACMP Peripheral Present */ - __I uint32_t PPPWM; /**< PWM Peripheral Present */ - __I uint32_t PPQEI; /**< QEI Peripheral Present */ - __I uint32_t PPLPC; /**< Low Pin Count Interface Peripheral Present */ - __I uint32_t RESERVED17[1]; /**< Reserved */ - __I uint32_t PPPECI; /**< Platform Environment Control Interface Peripheral Present */ - __I uint32_t PPFAN; /**< Fan Control Peripheral Present */ - __I uint32_t PPEEPROM; /**< EEPROM Peripheral Present */ - __I uint32_t PPWTIMER; /**< Wide GPT Peripheral Present */ - __I uint32_t RESERVED18[4]; /**< Reserved */ - __I uint32_t PPRTS; /**< Remote Temperature Sensor Peripheral Present */ - __I uint32_t PPCCM; /**< CRC Module Peripheral Present */ - __I uint32_t RESERVED19[6]; /**< Reserved */ - __I uint32_t PPLCD; /**< LCD Peripheral Present */ - __I uint32_t RESERVED20[1]; /**< Reserved */ - __I uint32_t PPOWIRE; /**< 1-Wire Peripheral Present */ - __I uint32_t PPEMAC; /**< Ethernet MAC Peripheral Present */ - __I uint32_t PPPRB; /**< Power Regulator Bus Peripheral Present */ - __I uint32_t PPHIM; /**< Human Interface Master Peripheral Present */ - __I uint32_t RESERVED21[86]; /**< Reserved */ - __IO uint32_t SRWD; /**< WDT Software Reset */ - __IO uint32_t SRTIMER; /**< GPT Software Reset */ - __IO uint32_t SRGPIO; /**< GPIO Software Reset */ - __IO uint32_t SRDMA; /**< UDMA Software Reset */ - __IO uint32_t SREPI; /**< EPI Software Reset */ - __IO uint32_t SRHIB; /**< HIB Software Reset */ - __IO uint32_t SRUART; /**< UART Software Reset */ - __IO uint32_t SRSSI; /**< SSI Software Reset */ - __IO uint32_t SRI2C; /**< I2C Software Reset */ - __I uint32_t RESERVED22[1]; /**< Reserved */ - __IO uint32_t SRUSB; /**< USB Software Reset */ - __I uint32_t RESERVED23[1]; /**< Reserved */ - __IO uint32_t SREPHY; /**< Ethernet PHY Software Reset */ - __IO uint32_t SRCAN; /**< CAN Software Reset */ - __IO uint32_t SRADC; /**< ADC Software Reset */ - __IO uint32_t SRACMP; /**< ACMP Software Reset */ - __IO uint32_t SRPWM; /**< PWM Software Reset */ - __IO uint32_t SRQEI; /**< QEI Software Reset */ - __I uint32_t RESERVED24[4]; /**< Reserved */ - __IO uint32_t SREEPROM; /**< EEPROM Software Reset */ - __I uint32_t RESERVED25[6]; /**< Reserved */ - __IO uint32_t SRCCM; /**< CRC Module Software Reset */ - __I uint32_t RESERVED26[9]; /**< Reserved */ - __IO uint32_t SREMAC; /**< Ethernet MAC Software Reset */ - __I uint32_t RESERVED27[24]; /**< Reserved */ - __IO uint32_t RCGCWD; /**< WDT Run Mode Clock Gating Control */ - __IO uint32_t RCGCTIMER; /**< GPT Run Mode Clock Gating Control */ - __IO uint32_t RCGCGPIO; /**< GPIO Run Mode Clock Gating Control */ - __IO uint32_t RCGCDMA; /**< UDMA Run Mode Clock Gating Control */ - __IO uint32_t RCGCEPI; /**< EPI Run Mode Clock Gating Control */ - __IO uint32_t RCGCHIB; /**< HIB Run Mode Clock Gating Control */ - __IO uint32_t RCGCUART; /**< UART Run Mode Control */ - __IO uint32_t RCGCSSI; /**< SSI Run Mode Clock Gating Control */ - __IO uint32_t RCGCI2C; /**< I2C Run Mode Clock Gating Control */ - __I uint32_t RESERVED28[1]; /**< Reserved */ - __IO uint32_t RCGCUSB; /**< USB Run Mode Clock Gating Control */ - __I uint32_t RESERVED29[1]; /**< Reserved */ - __IO uint32_t RCGCEPHY; /**< Ethernet PHY Run Mode Clock Gating Control */ - __IO uint32_t RCGCCAN; /**< CAN Run Mode Clock Gating Control */ - __IO uint32_t RCGCADC; /**< ADC Run Mode Clock Gating Control */ - __IO uint32_t RCGCACMP; /**< ACMP Run Mode Clock Gating Control */ - __IO uint32_t RCGCPWM; /**< PWM Run Mode Clock Gating Control */ - __IO uint32_t RCGCQEI; /**< QEI Run Mode Clock Gating Control */ - __I uint32_t RESERVED30[4]; /**< Reserved */ - __IO uint32_t RCGCEEPROM; /**< EEPROM Run Mode Clock Gating Control */ - __I uint32_t RESERVED31[6]; /**< Reserved */ - __IO uint32_t RCGCCCM; /**< CRC Module Run Mode Clock Gating Control */ - __I uint32_t RESERVED32[9]; /**< Reserved */ - __IO uint32_t RCGCEMAC; /**< Ethernet MAC Run Mode Clock Gating Control */ - __I uint32_t RESERVED33[24]; /**< Reserved */ - __IO uint32_t SCGCWD; /**< WDT Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCTIMER; /**< GPT Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCGPIO; /**< GPIO Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCDMA; /**< UDMA Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCEPI; /**< EPI Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCHIB; /**< HIB Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCUART; /**< UART Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCSSI; /**< SSI Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCI2C; /**< I2C Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED34[1]; /**< Reserved */ - __IO uint32_t SCGCUSB; /**< USB Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED35[1]; /**< Reserved */ - __IO uint32_t SCGCEPHY; /**< Ethernet PHY Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCCAN; /**< CAN Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCADC; /**< ADC Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCACMP; /**< ACMP Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCPWM; /**< PWM Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCQEI; /**< QEI Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED36[4]; /**< Reserved */ - __IO uint32_t SCGCEEPROM; /**< EEPROM Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED37[6]; /**< Reserved */ - __IO uint32_t SCGCCCM; /**< CRC Module Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED38[9]; /**< Reserved */ - __IO uint32_t SCGCEMAC; /**< Ethernet MAC Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED39[24]; /**< Reserved */ - __IO uint32_t DCGCWD; /**< WDT Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCTIMER; /**< GPT Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCGPIO; /**< GPIO Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCDMA; /**< UDMA Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCEPI; /**< EPI Deep-Sleep Mode Clock Gating Control */ - __IO uint32_t DCGCHIB; /**< HIB Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCUART; /**< UART Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCSSI; /**< SSI Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCI2C; /**< I2C Deep-Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED40[1]; /**< Reserved */ - __IO uint32_t DCGCUSB; /**< USB Deep-Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED41[1]; /**< Reserved */ - __IO uint32_t DCGCEPHY; /**< Ethernet PHY Deep-Sleep Mode Clock Gating Control */ - __IO uint32_t DCGCCAN; /**< CAN Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCADC; /**< ADC Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCACMP; /**< ACMP Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCPWM; /**< PWM Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCQEI; /**< QEI Deep-Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED42[4]; /**< Reserved */ - __IO uint32_t DCGCEEPROM; /**< EEPROM Deep-Sleep Mode Clock Gating - Control */ - __I uint32_t RESERVED43[6]; /**< Reserved */ - __IO uint32_t DCGCCCM; /**< CRC Module Deep-Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED44[9]; /**< Reserved */ - __IO uint32_t DCGCEMAC; /**< Ethernet MAC Deep-Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED45[24]; /**< Reserved */ - __IO uint32_t PCWD; /**< Watchdog Timer Power Control */ - __IO uint32_t PCTIMER; /**< 16/32-Bit General-Purpose Timer Power Control */ - __IO uint32_t PCGPIO; /**< General-Purpose Input/Output Power Control */ - __IO uint32_t PCDMA; /**< Micro Direct Memory Access Power Control */ - __IO uint32_t PCEPI; /**< External Peripheral Interface Power Control */ - __IO uint32_t PCHIB; /**< Hibernation Power Control */ - __IO uint32_t PCUART; /**< Universal Asynchronous Receiver/Transmitter Power Control */ - __IO uint32_t PCSSI; /**< Synchronous Serial Interface Power Control */ - __IO uint32_t PCI2C; /**< Inter-Integrated Circuit Power Control */ - __I uint32_t RESERVED46[1]; /**< Reserved */ - __IO uint32_t PCUSB; /**< Universal Serial Bus Power Control */ - __I uint32_t RESERVED47[1]; /**< Reserved */ - __IO uint32_t PCEPHY; /**< Ethernet PHY Power Control */ - __IO uint32_t PCCAN; /**< Controller Area Network Power Control */ - __IO uint32_t PCADC; /**< Analog-to-Digital Converter Power Control */ - __IO uint32_t PCACMP; /**< Analog Comparator Power Control */ - __IO uint32_t PCPWM; /**< Pulse Width Modulator Power Control */ - __IO uint32_t PCQEI; /**< Quadrature Encoder Interface Power Control */ - __I uint32_t RESERVED48[4]; /**< Reserved */ - __IO uint32_t PCEEPROM; /**< EEPROM Power Control */ - __I uint32_t RESERVED49[6]; /**< Reserved */ - __IO uint32_t PCCCM; /**< CRC Module Power Control */ - __I uint32_t RESERVED50[9]; /**< Reserved */ - __IO uint32_t PCEMAC; /**< Ethernet MAC Power Control */ - __I uint32_t RESERVED51[24]; /**< Reserved */ - __IO uint32_t PRWD; /**< WDT Peripheral Ready */ - __IO uint32_t PRTIMER; /**< GPT Peripheral Ready */ - __IO uint32_t PRGPIO; /**< GPIO Peripheral Ready */ - __IO uint32_t PRDMA; /**< UDMA Peripheral Ready */ - __IO uint32_t PREPI; /**< EPI Peripheral Ready */ - __IO uint32_t PRHIB; /**< HIB Peripheral Ready */ - __IO uint32_t PRUART; /**< UART Peripheral Ready */ - __IO uint32_t PRSSI; /**< SSI Peripheral Ready */ - __IO uint32_t PRI2C; /**< I2C Peripheral Ready */ - __I uint32_t RESERVED52[1]; /**< Reserved */ - __IO uint32_t PRUSB; /**< USB Peripheral Ready */ - __I uint32_t RESERVED53[1]; /**< Reserved */ - __IO uint32_t PREPHY; /**< Ethernet PHY Peripheral Ready */ - __IO uint32_t PRCAN; /**< CAN Peripheral Ready */ - __IO uint32_t PRADC; /**< ADC Peripheral Ready */ - __IO uint32_t PRACMP; /**< ACMP Peripheral Ready */ - __IO uint32_t PRPWM; /**< PWM Peripheral Ready */ - __IO uint32_t PRQEI; /**< QEI Peripheral Ready */ - __I uint32_t RESERVED54[4]; /**< Reserved */ - __IO uint32_t PREEPROM; /**< EEPROM Peripheral Ready */ - __I uint32_t RESERVED55[6]; /**< Reserved */ - __IO uint32_t PRCCM; /**< CRC Module Peripheral Ready */ - __I uint32_t RESERVED56[9]; /**< Reserved */ - __IO uint32_t PREMAC; /**< Ethernet MAC Peripheral Ready */ -} SYSCTL_TypeDef; - -/** - * @brief Universal Asynchronous Receiver/Transmitter - */ -typedef struct -{ - __IO uint32_t DR; /**< Data */ - union { - __I uint32_t RSR; /**< Receive Status */ - __O uint32_t ECR; /**< Error Clear */ - }; - __I uint32_t _RESERVED0[4]; /**< Reserved */ - __I uint32_t FR; /**< Flag */ - __I uint32_t _RESERVED1[1]; /**< Reserved */ - __IO uint32_t ILPR; /**< IrDA Low-Power Register */ - __IO uint32_t IBRD; /**< Integer Baud-Rate Divisor */ - __IO uint32_t FBRD; /**< Fractional Baud-Rate Divisor */ - __IO uint32_t LCRH; /**< Line Control */ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t IFLS; /**< Interrupt FIFO Level Select */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t DMACTL; /**< DMA Control */ - __I uint32_t _RESERVED2[22]; /**< Reserved */ - __IO uint32_t BIT9ADDR; /**< 9-Bit Self Address */ - __IO uint32_t BIT9AMASK; /**< 9-Bit Self Address Mask */ - __I uint32_t _RESERVED3[965];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ - __I uint32_t _RESERVED4[1]; /**< Reserved */ - __IO uint32_t CC; /**< Clock Configuration */ -} UART_TypeDef; - -/** - * @brief Micro Direct Memory Access - */ -typedef struct -{ - __IO uint32_t SET; /**< Set */ - __O uint32_t CLR; /**< Clear */ -} UDMA_SC_t; - -typedef struct -{ - __IO uint32_t STAT; /**< Status */ - __O uint32_t CFG; /**< Configuration */ - __IO uint32_t CTLBASE; /**< Channel Control Base Pointer */ - __IO uint32_t ALTBASE; /**< Alternate Channel Control Base Pointer */ - __IO uint32_t WAITSTAT; /**< Channel Wait-on-Request Status */ - __O uint32_t SWREQ; /**< Channel Software Request */ - UDMA_SC_t USEBURST; /**< Channel Useburst registers */ - UDMA_SC_t REQMASK; /**< Channel Request Mask registers */ - UDMA_SC_t ENA; /**< Channel Enable registers */ - UDMA_SC_t ALT; /**< Channel Primary Alternate registers */ - UDMA_SC_t PRIO; /**< Channel Priority registers */ - __I uint32_t _RESERVED0[3]; /**< Reserved */ - __IO uint32_t ERRCLR; /**< Bus Error Clear */ - __I uint32_t _RESERVED1[300];/**< Reserved */ - __IO uint32_t CHASGN; /**< Channel Assignment */ - __IO uint32_t CHIS; /**< Channel Interrupt Status */ - __I uint32_t _RESERVED2[2]; /**< Reserved */ - __IO uint32_t CHMAP[4]; /**< Channel Map Select 0, 1, 2 and 3 */ -} UDMA_TypeDef; - -// USB - -/** - * @brief Watchdog Timer - */ -typedef struct -{ - __IO uint32_t LOAD; /**< Load */ - __I uint32_t VALUE; /**< Value */ - __IO uint32_t CTL; /**< Control */ - __O uint32_t ICR; /**< Interrupt Clear */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __I uint32_t _RESERVED0[256];/**< Reserved */ - __IO uint32_t TEST; /**< Test */ - __I uint32_t _RESERVED1[505];/**< Reserved */ - __IO uint32_t LOCK; /**< Lock */ -} WDG_TypeDef; - -/** - * @brief Ethernet peripheral - */ -typedef struct { - __IO uint32_t CFG; /**< Configuration */ - __IO uint32_t FRAMEFLTR; /**< Frame Filter */ - __IO uint32_t HASHTBLH; /**< Hash Table High */ - __IO uint32_t HASHTBLL; /**< Hash Table Low */ - __IO uint32_t MIIADDR; /**< MII Address */ - __IO uint32_t MIIDATA; /**< MII Data Register */ - __IO uint32_t FLOWCTL; /**< Flow Control */ - __IO uint32_t VLANTG; /**< VLAN Tag */ - __I uint32_t RESERVED0[1]; /**< Reserved */ - __IO uint32_t STATUS; /**< Status */ - __IO uint32_t RWUFF; /**< Remote Wake-Up Frame Filter */ - __IO uint32_t PMTCTLSTAT; /**< PMT Control and Status Register */ - __I uint32_t RESERVED1[2]; /**< Reserved */ - __IO uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t IM; /**< Interrupt Mask */ - __IO uint32_t ADDR0H; /**< Address 0 High */ - __IO uint32_t ADDR0L; /**< Address 0 Low Register */ - __IO uint32_t ADDR1H; /**< Address 1 High */ - __IO uint32_t ADDR1L; /**< Address 1 Low */ - __IO uint32_t ADDR2H; /**< Address 2 High */ - __IO uint32_t ADDR2L; /**< Address 2 Low */ - __IO uint32_t ADDR3H; /**< Address 3 High */ - __IO uint32_t ADDR3L; /**< Address 3 Low */ - __I uint32_t RESERVED2[31]; /**< Reserved */ - __IO uint32_t WDOGTO; /**< Watchdog Timeout */ - __I uint32_t RESERVED3[8]; /**< Reserved */ - __IO uint32_t MMCCTRL; /**< MMC Control */ - __IO uint32_t MMCRXRIS; /**< MMC Receive Raw Interrupt Status */ - __IO uint32_t MMCTXRIS; /**< MMC Transmit Raw Interrupt Status */ - __IO uint32_t MMCRXIM; /**< MMC Receive Interrupt Mask */ - __IO uint32_t MMCTXIM; /**< MMC Transmit Interrupt Mask */ - __I uint32_t RESERVED4[1]; /**< Reserved */ - __IO uint32_t TXCNTGB; /**< Transmit Frame Count for Good and Bad - Frames */ - __I uint32_t RESERVED5[12]; /**< Reserved */ - __IO uint32_t TXCNTSCOL; /**< Transmit Frame Count for Frames - Transmitted after Single Collision */ - __IO uint32_t TXCNTMCOL; /**< Transmit Frame Count for Frames - Transmitted after Multiple Collisions */ - __I uint32_t RESERVED6[4]; /**< Reserved */ - __IO uint32_t TXOCTCNTG; /**< Transmit Octet Count Good */ - __I uint32_t RESERVED7[6]; /**< Reserved */ - __IO uint32_t RXCNTGB; /**< Receive Frame Count for Good and Bad - Frames */ - __I uint32_t RESERVED8[4]; /**< Reserved */ - __IO uint32_t RXCNTCRCERR; /**< Receive Frame Count for CRC Error Frames*/ - __IO uint32_t RXCNTALGNERR; /**< Receive Frame Count for Alignment Error - Frames */ - __I uint32_t RESERVED9[10]; /**< Reserved */ - __IO uint32_t RXCNTGUNI; /**< Receive Frame Count for Good Unicast - Frames */ - __I uint32_t RESERVED10[239];/**< Reserved */ - __IO uint32_t VLNINCREP; /**< VLAN Tag Inclusion or Replacement */ - __IO uint32_t VLANHASH; /**< VLAN Hash Table */ - __I uint32_t RESERVED11[93]; /**< Reserved */ - __IO uint32_t TIMSTCTRL; /**< Timestamp Control */ - __IO uint32_t SUBSECINC; /**< Sub-Second Increment */ - __IO uint32_t TIMSEC; /**< System Time - Seconds */ - __IO uint32_t TIMNANO; /**< System Time - Nanoseconds */ - __IO uint32_t TIMSECU; /**< System Time - Seconds Update */ - __IO uint32_t TIMNANOU; /**< System Time - Nanoseconds Update */ - __IO uint32_t TIMADD; /**< Timestamp Addend */ - __IO uint32_t TARGSEC; /**< Target Time Seconds */ - __IO uint32_t TARGNANO; /**< Target Time Nanoseconds */ - __IO uint32_t HWORDSEC; /**< System Time-Higher Word Seconds */ - __IO uint32_t TIMSTAT; /**< Timestamp Status */ - __IO uint32_t PPSCTRL; /**< PPS Control */ - __I uint32_t RESERVED12[12]; /**< Reserved */ - __IO uint32_t PPS0INTVL; /**< PPS0 Interval */ - __IO uint32_t PPS0WIDTH; /**< PPS0 Width */ - __I uint32_t RESERVED13[294];/**< Reserved */ - __IO uint32_t DMABUSMOD; /**< DMA Bus Mode */ - __O uint32_t TXPOLLD; /**< Transmit Poll Demand */ - __O uint32_t RXPOLLD; /**< Receive Poll Demand */ - __IO uint32_t RXDLADDR; /**< Receive Descriptor List Address */ - __IO uint32_t TXDLADDR; /**< Transmit Descriptor List Address */ - __IO uint32_t DMARIS; /**< DMA Interrupt Status */ - __IO uint32_t DMAOPMODE; /**< DMA Operation Mode */ - __IO uint32_t DMAIM; /**< DMA Interrupt Mask Register */ - __IO uint32_t MFBOC; /**< Missed Frame and Buffer Overflow Counter*/ - __IO uint32_t RXINTWDT; /**< Receive Interrupt Watchdog Timer */ - __I uint32_t RESERVED14[8]; /**< Reserved */ - __IO uint32_t HOSTXDESC; /**< Current Host Transmit Descriptor */ - __IO uint32_t HOSRXDESC; /**< Current Host Receive Descriptor */ - __IO uint32_t HOSTXBA; /**< Current Host Transmit Buffer Address */ - __IO uint32_t HOSRXBA; /**< Current Host Receive Buffer Address */ - __I uint32_t RESERVED15[218];/**< Reserved */ - __IO uint32_t PP; /**< Peripheral Property Register */ - __IO uint32_t PC; /**< Peripheral Configuration Register */ - __IO uint32_t CC; /**< Clock Configuration Register */ - __I uint32_t RESERVED16[1]; /**< Reserved */ - __I uint32_t PHYRIS; /**< PHY Raw Interrupt Status */ - __IO uint32_t PHYIM; /**< PHY Interrupt Mask */ - __IO uint32_t PHYMISC; /**< PHY Masked Interrupt Status and Clear */ -} ETH_TypeDef; - -/** - * @} - */ - -/** - * @addtogroup Peripheral_memorymap - * @{ - */ - -#define SYSCTL_BASE 0x400FE000 -#define HIB_BASE 0x400FC000 -#define FLASH_BASE 0x400FD000 -#define EEPROM_BASE 0x400AF000 -#define UDMA_BASE 0x400FF000 -#define GPIOA_BASE 0x40058000 -#define GPIOB_BASE 0x40059000 -#define GPIOC_BASE 0x4005A000 -#define GPIOD_BASE 0x4005B000 -#define GPIOE_BASE 0x4005C000 -#define GPIOF_BASE 0x4005D000 -#define GPIOG_BASE 0x4005E000 -#define GPIOH_BASE 0x4005F000 -#define GPIOJ_BASE 0x40060000 -#define GPIOK_BASE 0x40061000 -#define GPIOL_BASE 0x40062000 -#define GPIOM_BASE 0x40063000 -#define GPION_BASE 0x40064000 -#define GPIOP_BASE 0x40065000 -#define GPIOQ_BASE 0x40066000 -#define GPIOR_BASE 0x40067000 -#define GPIOS_BASE 0x40068000 -#define GPIOT_BASE 0x40069000 -#define GPT0_BASE 0x40030000 -#define GPT1_BASE 0x40031000 -#define GPT2_BASE 0x40032000 -#define GPT3_BASE 0x40033000 -#define GPT4_BASE 0x40034000 -#define GPT5_BASE 0x40035000 -#define GPT6_BASE 0x400E0000 -#define GPT7_BASE 0x400E1000 -#define WDT0_BASE 0x40000000 -#define WDT1_BASE 0x40001000 -#define ADC0_BASE 0x40038000 -#define ADC1_BASE 0x40039000 -#define UART0_BASE 0x4000C000 -#define UART1_BASE 0x4000D000 -#define UART2_BASE 0x4000E000 -#define UART3_BASE 0x4000F000 -#define UART4_BASE 0x40010000 -#define UART5_BASE 0x40011000 -#define UART6_BASE 0x40012000 -#define UART7_BASE 0x40013000 -#define SSI0_BASE 0x40008000 -#define SSI1_BASE 0x40009000 -#define SSI2_BASE 0x4000A000 -#define SSI3_BASE 0x4000B000 -#define I2C0_BASE 0x40020000 -#define I2C1_BASE 0x40021000 -#define I2C2_BASE 0x40022000 -#define I2C3_BASE 0x40023000 -#define I2C4_BASE 0x400C0000 -#define I2C5_BASE 0x400C1000 -#define I2C6_BASE 0x400C2000 -#define I2C7_BASE 0x400C3000 -#define I2C8_BASE 0x400B8000 -#define I2C9_BASE 0x400B9000 -#define CAN0_BASE 0x40040000 -#define CAN1_BASE 0x40041000 -// usb -#define ACMP_BASE 0x4003C000 -#define PWM0_BASE 0x40028000 -#define QEI0_BASE 0x4002C000 -#define QEI1_BASE 0x4002D000 - -#define ETH_BASE 0x400EC000 - -/** - * @} - */ - -/** - * @addtogroup Peripheral_declaration - * @{ - */ - -#define SYSCTL ((SYSCTL_TypeDef *) SYSCTL_BASE) -#define HIB ((HIB_TypeDef *) HIB_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_BASE) -#define EEPROM ((EEPROM_TypeDef *) EEPROM_BASE) -#define UDMA ((UDMA_TypeDef *) UDMA_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) -#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) -#define GPIOL ((GPIO_TypeDef *) GPIOL_BASE) -#define GPIOM ((GPIO_TypeDef *) GPIOM_BASE) -#define GPION ((GPIO_TypeDef *) GPION_BASE) -#define GPIOP ((GPIO_TypeDef *) GPIOP_BASE) -#define GPIOQ ((GPIO_TypeDef *) GPIOQ_BASE) -#define GPIOR ((GPIO_TypeDef *) GPIOR_BASE) -#define GPIOS ((GPIO_TypeDef *) GPIOS_BASE) -#define GPIOT ((GPIO_TypeDef *) GPIOT_BASE) -#define GPT0 ((GPT_TypeDef *) GPT0_BASE) -#define GPT1 ((GPT_TypeDef *) GPT1_BASE) -#define GPT2 ((GPT_TypeDef *) GPT2_BASE) -#define GPT3 ((GPT_TypeDef *) GPT3_BASE) -#define GPT4 ((GPT_TypeDef *) GPT4_BASE) -#define GPT5 ((GPT_TypeDef *) GPT5_BASE) -#define GPT6 ((GPT_TypeDef *) GPT6_BASE) -#define GPT7 ((GPT_TypeDef *) GPT7_BASE) -#define WDT0 ((WDT_TypeDef *) WDT0_BASE) -#define WDT1 ((WDT_TypeDef *) WDT1_BASE) -#define ADC0 ((ADC_TypeDef*) ADC0_BASE) -#define ADC1 ((ADC_TypeDef*) ADC1_BASE) -#define UART0 ((UART_TypeDef *) UART0_BASE) -#define UART1 ((UART_TypeDef *) UART1_BASE) -#define UART2 ((UART_TypeDef *) UART2_BASE) -#define UART3 ((UART_TypeDef *) UART3_BASE) -#define UART4 ((UART_TypeDef *) UART4_BASE) -#define UART5 ((UART_TypeDef *) UART5_BASE) -#define UART6 ((UART_TypeDef *) UART6_BASE) -#define UART7 ((UART_TypeDef *) UART7_BASE) -#define SSI0 ((SSI_TypeDef *) SSI0_BASE) -#define SSI1 ((SSI_TypeDef *) SSI1_BASE) -#define SSI2 ((SSI_TypeDef *) SSI2_BASE) -#define SSI3 ((SSI_TypeDef *) SSI3_BASE) -#define I2C0 ((I2C_TypeDef *) I2C0_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define I2C4 ((I2C_TypeDef *) I2C4_BASE) -#define I2C5 ((I2C_TypeDef *) I2C5_BASE) -#define I2C6 ((I2C_TypeDef *) I2C6_BASE) -#define I2C7 ((I2C_TypeDef *) I2C7_BASE) -#define I2C8 ((I2C_TypeDef *) I2C8_BASE) -#define I2C9 ((I2C_TypeDef *) I2C9_BASE) -#define CAN0 ((CAN_TypeDef *) CAN0_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -// usb -#define ACMP ((ACMP_TypeDef *) ACMP_BASE) -#define PWM0 ((PWM_TypeDef *) PWM0_BASE) -#define QEI0 ((QEI_TypeDef *) QEI0_BASE) -#define QEI1 ((QEI_TypeDef *) QEI1_BASE) - -#define ETH ((ETH_TypeDef *) ETH_BASE) - -/** - * @} - */ - -#endif /* __TM4C129x_H */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/ChibiOS_16.1.5/community/os/hal/src/hal_community.c b/ChibiOS_16.1.5/community/os/hal/src/hal_community.c deleted file mode 100644 index 8a39bf1..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/hal_community.c +++ /dev/null @@ -1,87 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file hal_community.c
- * @brief HAL subsystem code.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "hal.h"
-
-#if (HAL_USE_COMMUNITY == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief HAL initialization (community part).
- *
- * @init
- */
-void halCommunityInit(void) {
-
-#if HAL_USE_NAND || defined(__DOXYGEN__)
- nandInit();
-#endif
-
-#if HAL_USE_EICU || defined(__DOXYGEN__)
- eicuInit();
-#endif
-
-#if HAL_USE_CRC || defined(__DOXYGEN__)
- crcInit();
-#endif
-
-#if HAL_USE_RNG || defined(__DOXYGEN__)
- rngInit();
-#endif
-
-#if HAL_USE_USBH || defined(__DOXYGEN__)
- usbhInit();
-#endif
-
-#if HAL_USE_TIMCAP || defined(__DOXYGEN__)
- timcapInit();
-#endif
-
-#if HAL_USE_QEI || defined(__DOXYGEN__)
- qeiInit();
-#endif
-}
-
-#endif /* HAL_USE_COMMUNITY */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/src/hal_crc.c b/ChibiOS_16.1.5/community/os/hal/src/hal_crc.c deleted file mode 100644 index 63799e4..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/hal_crc.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - ChibiOS - Copyright (C) 2015 Michael D. Spradling - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * Hardware Abstraction Layer for CRC Unit - */ -#include "hal.h" - -#if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief CRC Driver initialization. - * - * @init - */ -void crcInit(void) { - crc_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p CRCDriver structure. - * - * @param[out] crcp Pointer to the @p CRCDriver object - * - * @init - */ -void crcObjectInit(CRCDriver *crcp) { - crcp->state = CRC_STOP; - crcp->config = NULL; -#if CRC_USE_DMA == TRUE - crcp->thread = NULL; -#endif -#if CRC_USE_MUTUAL_EXCLUSION == TRUE - osalMutexObjectInit(&crcp->mutex); -#endif -#if defined(CRC_DRIVER_EXT_INIT_HOOK) - CRC_DRIVER_EXT_INIT_HOOK(crcp); -#endif -} - -/** - * @brief Configures and activates the CRC peripheral. - * - * @param[in] crcp Pointer to the @p CRCDriver object - * @param[in] config Pointer to the @p CRCConfig object - * @p NULL if the low level driver implementation - * supports a default configuration - * - * @api - */ -void crcStart(CRCDriver *crcp, const CRCConfig *config) { - osalDbgCheck(crcp != NULL); - - osalSysLock(); - osalDbgAssert((crcp->state == CRC_STOP) || (crcp->state == CRC_READY), - "invalid state"); - crcp->config = config; - crc_lld_start(crcp); - crcp->state = CRC_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the CRC peripheral. - * - * @param[in] crcp Pointer to the @p CRCDriver object - * - * @api - */ -void crcStop(CRCDriver *crcp) { - osalDbgCheck(crcp != NULL); - - osalSysLock(); - osalDbgAssert((crcp->state == CRC_STOP) || (crcp->state == CRC_READY), - "invalid state"); - crc_lld_stop(crcp); - crcp->state = CRC_STOP; - osalSysUnlock(); -} - -/** - * @brief Resets the CRC calculation - * - * @param[in] crcp Pointer to the @p CRCDriver object - * - * @api - */ -void crcReset(CRCDriver *crcp) { - osalSysLock(); - crcResetI(crcp); - osalSysUnlock(); -} - -/** - * @brief Resets the current CRC calculation - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @iclass - */ -void crcResetI(CRCDriver *crcp) { - osalDbgCheck(crcp != NULL); - osalDbgAssert(crcp->state == CRC_READY, "Not ready"); - crc_lld_reset(crcp); -} - -/** - * @brief Performs a CRC calculation. - * @details This synchronous function performs a crc calculation operation. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] n number of bytes to send - * @param[in] buf the pointer to the buffer - * - * @api - */ -uint32_t crcCalc(CRCDriver *crcp, size_t n, const void *buf) { - uint32_t crc; -#if CRC_USE_DMA - osalSysLock(); -#endif - crc = crcCalcI(crcp, n, buf); -#if CRC_USE_DMA - osalSysUnlock(); -#endif - return crc; -} - -/** - * @brief Performs a CRC calculation. - * @details This synchronous function performs a crc calcuation operation. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] n number of bytes to send - * @param[in] buf the pointer to the buffer - * - * @iclass - */ -uint32_t crcCalcI(CRCDriver *crcp, size_t n, const void *buf) { - osalDbgCheck((crcp != NULL) && (n > 0U) && (buf != NULL)); - osalDbgAssert(crcp->state == CRC_READY, "not ready"); -#if CRC_USE_DMA - osalDbgAssert(crcp->config->end_cb == NULL, "callback defined"); - (crcp)->state = CRC_ACTIVE; -#endif - return crc_lld_calc(crcp, n, buf); -} - -#if CRC_USE_DMA == TRUE -/** - * @brief Performs a CRC calculation. - * @details This asynchronous function starts a crc calcuation operation. - * @pre In order to use this function the driver must have been configured - * with callbacks (@p end_cb != @p NULL). - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] n number of bytes to send - * @param[in] buf the pointer to the buffer - * - * @api - */ -void crcStartCalc(CRCDriver *crcp, size_t n, const void *buf) { - osalSysLock(); - crcStartCalcI(crcp, n, buf); - osalSysUnlock(); -} - -/** - * @brief Performs a CRC calculation. - * @details This asynchronous function starts a crc calcuation operation. - * @pre In order to use this function the driver must have been configured - * without callbacks (@p end_cb = @p NULL). - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] crcp pointer to the @p CRCDriver object - * @param[in] n number of bytes to send - * @param[in] buf the pointer to the buffer - * - * - * @iclass - */ -void crcStartCalcI(CRCDriver *crcp, size_t n, const void *buf) { - osalDbgCheck((crcp != NULL) && (n > 0U) && (buf != NULL)); - osalDbgAssert(crcp->state == CRC_READY, "not ready"); - osalDbgAssert(crcp->config->end_cb != NULL, "callback not defined"); - (crcp)->state = CRC_ACTIVE; - crc_lld_start_calc(crcp, n, buf); -} -#endif - -#if (CRC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the CRC unit. - * @details This function tries to gain ownership to the CRC, if the CRC is - * already being used then the invoking thread is queued. - * @pre In order to use this function the option @p CRC_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @api - */ -void crcAcquireUnit(CRCDriver *crcp) { - osalDbgCheck(crcp != NULL); - - osalMutexLock(&crcp->mutex); -} - -/** - * @brief Releases exclusive access to the CRC unit. - * @pre In order to use this function the option @p CRC_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] crcp pointer to the @p CRCDriver object - * - * @api - */ -void crcReleaseUnit(CRCDriver *crcp) { - osalDbgCheck(crcp != NULL); - - osalMutexUnlock(&crcp->mutex); -} -#endif /* CRC_USE_MUTUAL_EXCLUSION == TRUE */ - -#endif /* HAL_USE_CRC */ diff --git a/ChibiOS_16.1.5/community/os/hal/src/hal_ee24xx.c b/ChibiOS_16.1.5/community/os/hal/src/hal_ee24xx.c deleted file mode 100644 index 632ffbb..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/hal_ee24xx.c +++ /dev/null @@ -1,353 +0,0 @@ -/* - Copyright (c) 2013 Timon Wong - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in all - copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - THE SOFTWARE. -*/ - -/* - Copyright 2012 Uladzimir Pylinski aka barthess. - You may use this work without restrictions, as long as this notice is included. - The work is provided "as is" without warranty of any kind, neither express nor implied. -*/ - -/***************************************************************************** - * DATASHEET NOTES - ***************************************************************************** -Write cycle time (byte or page) - 5 ms - -Note: - Page write operations are limited to writing bytes within a single physical - page, regardless of the number of bytes actually being written. Physical page - boundaries start at addresses that are integer multiples of the page buffer - size (or page size and end at addresses that are integer multiples of - [page size]. If a Page Write command attempts to write across a physical - page boundary, the result is that the data wraps around to the beginning of - the current page (overwriting data previously stored there), instead of - being written to the next page as might be expected. -*********************************************************************/ - -#include "hal_ee24xx.h" -#include <string.h> - -#if (defined(HAL_USE_EEPROM) && HAL_USE_EEPROM && EEPROM_USE_EE24XX) || defined(__DOXYGEN__) - -/* - ****************************************************************************** - * DEFINES - ****************************************************************************** - */ -/* -#if defined(SAM7_PLATFORM) -#define EEPROM_I2C_CLOCK (MCK / (((i2cp->config->cwgr & 0xFF) + ((i2cp->config->cwgr >> 8) & 0xFF)) * (1 << ((i2cp->config->cwgr >> 16) & 7)) + 6)) -#else -#define EEPROM_I2C_CLOCK (i2cp->config->clock_speed) -#endif -*/ -#define EEPROM_I2C_CLOCK 400000 - -/* - ****************************************************************************** - * EXTERNS - ****************************************************************************** - */ - -/* - ****************************************************************************** - * GLOBAL VARIABLES - ****************************************************************************** - */ - -/* - ******************************************************************************* - * LOCAL FUNCTIONS - ******************************************************************************* - */ -/** - * @brief Split one uint16_t address to two uint8_t. - * - * @param[in] txbuf pointer to driver transmit buffer - * @param[in] addr uint16_t address - */ -#define eeprom_split_addr(txbuf, addr){ \ - (txbuf)[0] = ((uint8_t)((addr >> 8) & 0xFF)); \ - (txbuf)[1] = ((uint8_t)(addr & 0xFF)); \ - } - -/* - ******************************************************************************* - * EXPORTED FUNCTIONS - ******************************************************************************* - */ - -/** - * @brief Calculates requred timeout. - */ -static systime_t calc_timeout(I2CDriver *i2cp, size_t txbytes, size_t rxbytes) { - (void)i2cp; - const uint32_t bitsinbyte = 10; - uint32_t tmo; - tmo = ((txbytes + rxbytes + 1) * bitsinbyte * 1000); - tmo /= EEPROM_I2C_CLOCK; - tmo += 10; /* some additional milliseconds to be safer */ - return MS2ST(tmo); -} - -/** - * @brief EEPROM read routine. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file - * @param[in] offset addres of 1-st byte to be read - * @param[in] data pointer to buffer with data to be written - * @param[in] len number of bytes to be red - */ -static msg_t eeprom_read(const I2CEepromFileConfig *eepcfg, - uint32_t offset, uint8_t *data, size_t len) { - - msg_t status = MSG_RESET; - systime_t tmo = calc_timeout(eepcfg->i2cp, 2, len); - - osalDbgAssert(((len <= eepcfg->size) && ((offset + len) <= eepcfg->size)), - "out of device bounds"); - - eeprom_split_addr(eepcfg->write_buf, (offset + eepcfg->barrier_low)); - -#if I2C_USE_MUTUAL_EXCLUSION - i2cAcquireBus(eepcfg->i2cp); -#endif - - status = i2cMasterTransmitTimeout(eepcfg->i2cp, eepcfg->addr, - eepcfg->write_buf, 2, data, len, tmo); - -#if I2C_USE_MUTUAL_EXCLUSION - i2cReleaseBus(eepcfg->i2cp); -#endif - - return status; -} - -/** - * @brief EEPROM write routine. - * @details Function writes data to EEPROM. - * @pre Data must be fit to single EEPROM page. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file - * @param[in] offset addres of 1-st byte to be write - * @param[in] data pointer to buffer with data to be written - * @param[in] len number of bytes to be written - */ -static msg_t eeprom_write(const I2CEepromFileConfig *eepcfg, uint32_t offset, - const uint8_t *data, size_t len) { - msg_t status = MSG_RESET; - systime_t tmo = calc_timeout(eepcfg->i2cp, (len + 2), 0); - - osalDbgAssert(((len <= eepcfg->size) && ((offset + len) <= eepcfg->size)), - "out of device bounds"); - osalDbgAssert((((offset + eepcfg->barrier_low) / eepcfg->pagesize) == - (((offset + eepcfg->barrier_low) + len - 1) / eepcfg->pagesize)), - "data can not be fitted in single page"); - - /* write address bytes */ - eeprom_split_addr(eepcfg->write_buf, (offset + eepcfg->barrier_low)); - /* write data bytes */ - memcpy(&(eepcfg->write_buf[2]), data, len); - -#if I2C_USE_MUTUAL_EXCLUSION - i2cAcquireBus(eepcfg->i2cp); -#endif - - status = i2cMasterTransmitTimeout(eepcfg->i2cp, eepcfg->addr, - eepcfg->write_buf, (len + 2), NULL, 0, tmo); - -#if I2C_USE_MUTUAL_EXCLUSION - i2cReleaseBus(eepcfg->i2cp); -#endif - - /* wait until EEPROM process data */ - chThdSleep(eepcfg->write_time); - - return status; -} - -/** - * @brief Determines and returns size of data that can be processed - */ -static size_t __clamp_size(void *ip, size_t n) { - - if (((size_t)eepfs_getposition(ip) + n) > (size_t)eepfs_getsize(ip)) - return eepfs_getsize(ip) - eepfs_getposition(ip); - else - return n; -} - -/** - * @brief Write data that can be fitted in one page boundary - */ -static void __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t *written) { - - msg_t status = MSG_RESET; - - osalDbgAssert(len != 0, "something broken in hi level part"); - - status = eeprom_write(((I2CEepromFileStream *)ip)->cfg, - eepfs_getposition(ip), data, len); - if (status == MSG_OK) { - *written += len; - eepfs_lseek(ip, eepfs_getposition(ip) + len); - } -} - -/** - * @brief Write data to EEPROM. - * @details Only one EEPROM page can be written at once. So fucntion - * splits large data chunks in small EEPROM transactions if needed. - * @note To achieve the maximum effectivity use write operations - * aligned to EEPROM page boundaries. - */ -static size_t write(void *ip, const uint8_t *bp, size_t n) { - - size_t len = 0; /* bytes to be written at one trasaction */ - uint32_t written; /* total bytes successfully written */ - uint16_t pagesize; - uint32_t firstpage; - uint32_t lastpage; - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - - if (n == 0) - return 0; - - n = __clamp_size(ip, n); - if (n == 0) - return 0; - - pagesize = ((EepromFileStream *)ip)->cfg->pagesize; - firstpage = (((EepromFileStream *)ip)->cfg->barrier_low + - eepfs_getposition(ip)) / pagesize; - lastpage = (((EepromFileStream *)ip)->cfg->barrier_low + - eepfs_getposition(ip) + n - 1) / pagesize; - - written = 0; - /* data fitted in single page */ - if (firstpage == lastpage) { - len = n; - __fitted_write(ip, bp, len, &written); - bp += len; - return written; - } - - else { - /* write first piece of data to first page boundary */ - len = ((firstpage + 1) * pagesize) - eepfs_getposition(ip); - len -= ((EepromFileStream *)ip)->cfg->barrier_low; - __fitted_write(ip, bp, len, &written); - bp += len; - - /* now writes blocks at a size of pages (may be no one) */ - while ((n - written) > pagesize) { - len = pagesize; - __fitted_write(ip, bp, len, &written); - bp += len; - } - - /* wrtie tail */ - len = n - written; - if (len == 0) - return written; - else { - __fitted_write(ip, bp, len, &written); - } - } - - return written; -} - -/** - * Read some bytes from current position in file. After successful - * read operation the position pointer will be increased by the number - * of read bytes. - */ -static size_t read(void *ip, uint8_t *bp, size_t n) { - msg_t status = MSG_OK; - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - - if (n == 0) - return 0; - - n = __clamp_size(ip, n); - if (n == 0) - return 0; - - /* Stupid I2C cell in STM32F1x does not allow to read single byte. - So we must read 2 bytes and return needed one. */ -#if defined(STM32F1XX_I2C) - if (n == 1) { - uint8_t __buf[2]; - /* if NOT last byte of file requested */ - if ((eepfs_getposition(ip) + 1) < eepfs_getsize(ip)) { - if (read(ip, __buf, 2) == 2) { - eepfs_lseek(ip, (eepfs_getposition(ip) + 1)); - bp[0] = __buf[0]; - return 1; - } - else - return 0; - } - else { - eepfs_lseek(ip, (eepfs_getposition(ip) - 1)); - if (read(ip, __buf, 2) == 2) { - eepfs_lseek(ip, (eepfs_getposition(ip) + 2)); - bp[0] = __buf[1]; - return 1; - } - else - return 0; - } - } -#endif /* defined(STM32F1XX_I2C) */ - - /* call low level function */ - status = eeprom_read(((I2CEepromFileStream *)ip)->cfg, - eepfs_getposition(ip), bp, n); - if (status != MSG_OK) - return 0; - else { - eepfs_lseek(ip, (eepfs_getposition(ip) + n)); - return n; - } -} - -static const struct EepromFileStreamVMT vmt = { - write, - read, - eepfs_put, - eepfs_get, - eepfs_close, - eepfs_geterror, - eepfs_getsize, - eepfs_getposition, - eepfs_lseek, -}; - -EepromDevice eepdev_24xx = { - EEPROM_DEV_24XX, - &vmt -}; - -#endif /* EEPROM_USE_EE24XX */ diff --git a/ChibiOS_16.1.5/community/os/hal/src/hal_ee25xx.c b/ChibiOS_16.1.5/community/os/hal/src/hal_ee25xx.c deleted file mode 100644 index 102aef8..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/hal_ee25xx.c +++ /dev/null @@ -1,404 +0,0 @@ -/* - Copyright (c) 2013 Timon Wong - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in all - copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - THE SOFTWARE. -*/ - -/* - Copyright 2012 Uladzimir Pylinski aka barthess. - You may use this work without restrictions, as long as this notice is included. - The work is provided "as is" without warranty of any kind, neither express nor implied. -*/ - -/***************************************************************************** - * DATASHEET NOTES - ***************************************************************************** -Write cycle time (byte or page) - 5 ms - -Note: - Page write operations are limited to writing bytes within a single physical - page, regardless of the number of bytes actually being written. Physical page - boundaries start at addresses that are integer multiples of the page buffer - size (or page size and end at addresses that are integer multiples of - [page size]. If a Page Write command attempts to write across a physical - page boundary, the result is that the data wraps around to the beginning of - the current page (overwriting data previously stored there), instead of - being written to the next page as might be expected. -*********************************************************************/ - -#include "hal_ee25xx.h" -#include <string.h> - -#if (defined(HAL_USE_EEPROM) && HAL_USE_EEPROM && EEPROM_USE_EE25XX) || defined(__DOXYGEN__) - -/** - * @name Commands of 25XX chip. - * @{ - */ -#define CMD_READ 0x03 /**< @brief Read data from memory array beginning at - selected address. */ -#define CMD_WRITE 0x02 /**< @brief Write data to memory array beginning at - selected address. */ -#define CMD_WRDI 0x04 /**< Reset the write enable latch (disable write - operations). */ -#define CMD_WREN 0x06 /**< Set the write enable latch (enable write - operations). */ -#define CMD_RDSR 0x05 /**< Read STATUS register. */ -#define CMD_WRSR 0x01 /**< Write STATUS register. */ - -/** @} */ - -/** - * @name Status of 25XX chip. - * @{} - */ -#define STAT_BP1 0x08 /**< @brief Block protection (high). */ -#define STAT_BP0 0x04 /**< @brief Block protection (low). */ -#define STAT_WEL 0x02 /**< @brief Write enable latch. */ -#define STAT_WIP 0x01 /**< @brief Write-In-Progress. */ - -/** @} */ - -/** - * @brief 25XX low level write then read rountine. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file. - * @param[in] txbuf pointer to buffer to be transfered. - * @param[in] txlen number of bytes to be transfered. - * @param[out] rxbuf pointer to buffer to be received. - * @param[in] rxlen number of bytes to be received. - */ -static void ll_25xx_transmit_receive(const SPIEepromFileConfig *eepcfg, - const uint8_t *txbuf, size_t txlen, - uint8_t *rxbuf, size_t rxlen) { - -#if SPI_USE_MUTUAL_EXCLUSION - spiAcquireBus(eepcfg->spip); -#endif - spiSelect(eepcfg->spip); - spiSend(eepcfg->spip, txlen, txbuf); - if (rxlen) /* Check if receive is needed. */ - spiReceive(eepcfg->spip, rxlen, rxbuf); - spiUnselect(eepcfg->spip); - -#if SPI_USE_MUTUAL_EXCLUSION - spiReleaseBus(eepcfg->spip); -#endif -} - -/** - * @brief Check whether the device is busy (writing in progress). - * - * @param[in] eepcfg pointer to configuration structure of eeprom file. - * @return @p true on busy. - */ -static bool ll_eeprom_is_busy(const SPIEepromFileConfig *eepcfg) { - - uint8_t cmd = CMD_RDSR; - uint8_t stat; - ll_25xx_transmit_receive(eepcfg, &cmd, 1, &stat, 1); - if (stat & STAT_WIP) - return TRUE; - return FALSE; -} - -/** - * @brief Lock device. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file. - */ -static void ll_eeprom_lock(const SPIEepromFileConfig *eepcfg) { - - uint8_t cmd = CMD_WRDI; - ll_25xx_transmit_receive(eepcfg, &cmd, 1, NULL, 0); -} - -/** - * @brief Unlock device. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file. - */ -static void ll_eeprom_unlock(const SPIEepromFileConfig *eepcfg) { - - uint8_t cmd = CMD_WREN; - ll_25xx_transmit_receive(eepcfg, &cmd, 1, NULL, 0); -} - -/** - * @brief Prepare byte sequence for command and address - * - * @param[in] seq pointer to first 3byte sequence - * @param[in] size size of the eeprom device - * @param[in] cmd command - * @param[in] addr address - * @return number of bytes of this sequence - */ -static uint8_t ll_eeprom_prepare_seq(uint8_t *seq, uint32_t size, uint8_t cmd, - uint32_t addr) { - - seq[0] = ((uint8_t)cmd & 0xff); - - if (size > 0xffffUL) { - /* High density, 24bit address. */ - seq[1] = (uint8_t)((addr >> 16) & 0xff); - seq[2] = (uint8_t)((addr >> 8) & 0xff); - seq[3] = (uint8_t)(addr & 0xff); - return 4; - } - else if (size > 0x00ffUL) { - /* Medium density, 16bit address. */ - seq[1] = (uint8_t)((addr >> 8) & 0xff); - seq[2] = (uint8_t)(addr & 0xff); - return 3; - } - - /* Low density, 8bit address. */ - seq[1] = (uint8_t)(addr & 0xff); - return 2; -} - -/** - * @brief EEPROM read routine. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file. - * @param[in] offset addres of 1-st byte to be read. - * @param[out] data pointer to buffer with data to be written. - * @param[in] len number of bytes to be red. - */ -static msg_t ll_eeprom_read(const SPIEepromFileConfig *eepcfg, uint32_t offset, - uint8_t *data, size_t len) { - - uint8_t txbuff[4]; - uint8_t txlen; - - osalDbgAssert(((len <= eepcfg->size) && ((offset + len) <= eepcfg->size)), - "out of device bounds"); - - if (eepcfg->spip->state != SPI_READY) - return MSG_RESET; - - txlen = ll_eeprom_prepare_seq(txbuff, eepcfg->size, CMD_READ, - (offset + eepcfg->barrier_low)); - ll_25xx_transmit_receive(eepcfg, txbuff, txlen, data, len); - - return MSG_OK; -} - -/** - * @brief EEPROM write routine. - * @details Function writes data to EEPROM. - * @pre Data must be fit to single EEPROM page. - * - * @param[in] eepcfg pointer to configuration structure of eeprom file. - * @param[in] offset addres of 1-st byte to be writen. - * @param[in] data pointer to buffer with data to be written. - * @param[in] len number of bytes to be written. - */ -static msg_t ll_eeprom_write(const SPIEepromFileConfig *eepcfg, uint32_t offset, - const uint8_t *data, size_t len) { - - uint8_t txbuff[4]; - uint8_t txlen; - systime_t now; - - osalDbgAssert(((len <= eepcfg->size) && ((offset + len) <= eepcfg->size)), - "out of device bounds"); - osalDbgAssert((((offset + eepcfg->barrier_low) / eepcfg->pagesize) == - (((offset + eepcfg->barrier_low) + len - 1) / eepcfg->pagesize)), - "data can not be fitted in single page"); - - if (eepcfg->spip->state != SPI_READY) - return MSG_RESET; - - /* Unlock array for writting. */ - ll_eeprom_unlock(eepcfg); - -#if SPI_USE_MUTUAL_EXCLUSION - spiAcquireBus(eepcfg->spip); -#endif - - spiSelect(eepcfg->spip); - txlen = ll_eeprom_prepare_seq(txbuff, eepcfg->size, CMD_WRITE, - (offset + eepcfg->barrier_low)); - spiSend(eepcfg->spip, txlen, txbuff); - spiSend(eepcfg->spip, len, data); - spiUnselect(eepcfg->spip); - -#if SPI_USE_MUTUAL_EXCLUSION - spiReleaseBus(eepcfg->spip); -#endif - - /* Wait until EEPROM process data. */ - now = chVTGetSystemTimeX(); - while (ll_eeprom_is_busy(eepcfg)) { - if ((chVTGetSystemTimeX() - now) > eepcfg->write_time) { - return MSG_TIMEOUT; - } - - chThdYield(); - } - - /* Lock array preventing unexpected access */ - ll_eeprom_lock(eepcfg); - return MSG_OK; -} - -/** - * @brief Determines and returns size of data that can be processed - */ -static size_t __clamp_size(void *ip, size_t n) { - - if (((size_t)eepfs_getposition(ip) + n) > (size_t)eepfs_getsize(ip)) - return eepfs_getsize(ip) - eepfs_getposition(ip); - else - return n; -} - -/** - * @brief Write data that can be fitted in one page boundary - */ -static msg_t __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t *written) { - - msg_t status = MSG_RESET; - - osalDbgAssert(len != 0, "something broken in hi level part"); - - status = ll_eeprom_write(((SPIEepromFileStream *)ip)->cfg, - eepfs_getposition(ip), data, len); - if (status == MSG_OK) { - *written += len; - eepfs_lseek(ip, eepfs_getposition(ip) + len); - } - return status; -} - -/** - * @brief Write data to EEPROM. - * @details Only one EEPROM page can be written at once. So fucntion - * splits large data chunks in small EEPROM transactions if needed. - * @note To achieve the maximum effectivity use write operations - * aligned to EEPROM page boundaries. - */ -static size_t write(void *ip, const uint8_t *bp, size_t n) { - - size_t len = 0; /* bytes to be written at one trasaction */ - uint32_t written; /* total bytes successfully written */ - uint16_t pagesize; - uint32_t firstpage; - uint32_t lastpage; - - volatile const SPIEepromFileConfig *cfg = ((SPIEepromFileStream *)ip)->cfg; - - osalDbgCheck((ip != NULL) && (((SPIEepromFileStream *)ip)->vmt != NULL)); - - if (n == 0) - return 0; - - n = __clamp_size(ip, n); - if (n == 0) - return 0; - - pagesize = cfg->pagesize; - firstpage = (cfg->barrier_low + eepfs_getposition(ip)) / pagesize; - lastpage = ((cfg->barrier_low + eepfs_getposition(ip) + n) - 1) / pagesize; - - written = 0; - /* data fitted in single page */ - if (firstpage == lastpage) { - len = n; - __fitted_write(ip, bp, len, &written); - bp += len; - return written; - } - else { - /* write first piece of data to first page boundary */ - len = ((firstpage + 1) * pagesize) - eepfs_getposition(ip); - len -= cfg->barrier_low; - __fitted_write(ip, bp, len, &written); - bp += len; - - /* now writes blocks at a size of pages (may be no one) */ - while ((n - written) > pagesize) { - len = pagesize; - if (__fitted_write(ip, bp, len, &written) != MSG_OK) // Fixed: Would increase bp forever and crash in case of timeouts... - return written; - - bp += len; - } - - - /* wrtie tail */ - len = n - written; - if (len == 0) - return written; - else { - __fitted_write(ip, bp, len, &written); - } - } - - return written; -} - -/** - * Read some bytes from current position in file. After successful - * read operation the position pointer will be increased by the number - * of read bytes. - */ -static size_t read(void *ip, uint8_t *bp, size_t n) { - - msg_t status = MSG_OK; - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - - if (n == 0) - return 0; - - n = __clamp_size(ip, n); - if (n == 0) - return 0; - - /* call low level function */ - status = ll_eeprom_read(((SPIEepromFileStream *)ip)->cfg, - eepfs_getposition(ip), bp, n); - if (status != MSG_OK) - return 0; - else { - eepfs_lseek(ip, (eepfs_getposition(ip) + n)); - return n; - } -} - -static const struct EepromFileStreamVMT vmt = { - write, - read, - eepfs_put, - eepfs_get, - eepfs_close, - eepfs_geterror, - eepfs_getsize, - eepfs_getposition, - eepfs_lseek, -}; - -EepromDevice eepdev_25xx = { - EEPROM_DEV_25XX, - &vmt -}; - -#endif /* EEPROM_USE_EE25XX */ diff --git a/ChibiOS_16.1.5/community/os/hal/src/hal_eeprom.c b/ChibiOS_16.1.5/community/os/hal/src/hal_eeprom.c deleted file mode 100644 index f77d616..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/hal_eeprom.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - Copyright (c) 2013 Timon Wong - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in all - copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - THE SOFTWARE. -*/ - -/* - Copyright 2012 Uladzimir Pylinski aka barthess. - You may use this work without restrictions, as long as this notice is included. - The work is provided "as is" without warranty of any kind, neither express nor implied. -*/ - -#include "hal_eeprom.h" -#include <string.h> - -#if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM - -extern EepromDevice eepdev_24xx; -extern EepromDevice eepdev_25xx; - -EepromDevice *__eeprom_drv_table[] = { - /* I2C related. */ -#if HAL_USE_I2C - -# if EEPROM_USE_EE24XX - &eepdev_24xx, -# endif - -#endif /* HAL_USE_I2C */ - - /* SPI related. */ -#if HAL_USE_SPI - -# if EEPROM_USE_EE25XX - &eepdev_25xx, -# endif - -#endif /* HAL_USE_SPI */ -}; - - -/** - * @breif Find low level EEPROM device by id. - */ -const EepromDevice *EepromFindDevice(uint8_t id) { - - uint8_t i; - const EepromDevice *drv; - - for (i = 0; i < EEPROM_TABLE_SIZE; i++) { - drv = __eeprom_drv_table[i]; - if (drv->id == id) { - return drv; - } - } - - return NULL; -} - -/** - * Open EEPROM IC as file and return pointer to the file stream object - * @note Fucntion allways successfully open file. All checking makes - * in read/write functions. - */ -EepromFileStream *EepromFileOpen(EepromFileStream *efs, - const EepromFileConfig *eepcfg, - const EepromDevice *eepdev) { - - osalDbgAssert((efs != NULL) && (eepcfg != NULL) && (eepdev != NULL) && - (eepdev->efsvmt != NULL), "EepromFileOpen"); - osalDbgAssert(efs->vmt != eepdev->efsvmt, "File allready opened"); - osalDbgAssert(eepcfg->barrier_hi > eepcfg->barrier_low, "Low barrier exceeds High barrier"); - osalDbgAssert(eepcfg->pagesize < eepcfg->size, "Pagesize cannot be lager than EEPROM size"); - osalDbgAssert(eepcfg->barrier_hi <= eepcfg->size, "Barrier exceeds EEPROM size"); - - efs->vmt = eepdev->efsvmt; - efs->cfg = eepcfg; - efs->errors = FILE_OK; - efs->position = 0; - return (EepromFileStream *)efs; -} - -uint8_t EepromReadByte(EepromFileStream *efs) { - - uint8_t buf; - fileStreamRead(efs, &buf, sizeof(buf)); - return buf; -} - -uint16_t EepromReadHalfword(EepromFileStream *efs) { - - uint16_t buf; - fileStreamRead(efs, (uint8_t *)&buf, sizeof(buf)); - return buf; -} - -uint32_t EepromReadWord(EepromFileStream *efs) { - - uint32_t buf; - fileStreamRead(efs, (uint8_t *)&buf, sizeof(buf)); - return buf; -} - -size_t EepromWriteByte(EepromFileStream *efs, uint8_t data) { - - return fileStreamWrite(efs, &data, sizeof(data)); -} - -size_t EepromWriteHalfword(EepromFileStream *efs, uint16_t data) { - - return fileStreamWrite(efs, (uint8_t *)&data, sizeof(data)); -} - -size_t EepromWriteWord(EepromFileStream *efs, uint32_t data) { - - return fileStreamWrite(efs, (uint8_t *)&data, sizeof(data)); -} - -msg_t eepfs_getsize(void *ip) { - - uint32_t h, l; - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL) && - (((EepromFileStream *)ip)->cfg != NULL)); - - h = ((EepromFileStream *)ip)->cfg->barrier_hi; - l = ((EepromFileStream *)ip)->cfg->barrier_low; - return h - l; -} - -msg_t eepfs_getposition(void *ip) { - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - - return ((EepromFileStream *)ip)->position; -} - -msg_t eepfs_lseek(void *ip, fileoffset_t offset) { - - uint32_t size; - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - - size = eepfs_getsize(ip); - if (offset > size) - offset = size; - ((EepromFileStream *)ip)->position = offset; - return offset; -} - -msg_t eepfs_close(void *ip) { - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - - ((EepromFileStream *)ip)->errors = FILE_OK; - ((EepromFileStream *)ip)->position = 0; - ((EepromFileStream *)ip)->vmt = NULL; - ((EepromFileStream *)ip)->cfg = NULL; - return FILE_OK; -} - -msg_t eepfs_geterror(void *ip) { - - osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL)); - return ((EepromFileStream *)ip)->errors; -} - -msg_t eepfs_put(void *ip, uint8_t b) { - - (void)ip; - (void)b; - return 0; -} - -msg_t eepfs_get(void *ip) { - - (void)ip; - return 0; -} - -#endif /* #if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM */ diff --git a/ChibiOS_16.1.5/community/os/hal/src/hal_eicu.c b/ChibiOS_16.1.5/community/os/hal/src/hal_eicu.c deleted file mode 100644 index f75c58b..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/hal_eicu.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Rewritten by Emil Fresk (1/5 - 2014) for extended input capture - functionality. And fix for spurious callbacks in the interrupt handler. -*/ -/* - Improved by Uladzimir Pylinsky aka barthess (1/3 - 2015) for support of - 32-bit timers and timers with single capture/compare channels. -*/ - -/* - * Hardware Abstraction Layer for Extended Input Capture Unit - */ -#include "hal.h" - -#if (HAL_USE_EICU == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief EICU Driver initialization. - * - * @init - */ -void eicuInit(void) { - - eicu_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p EICUDriver structure. - * - * @param[out] eicup Pointer to the @p EICUDriver object - * - * @init - */ -void eicuObjectInit(EICUDriver *eicup) { - - eicup->state = EICU_STOP; - eicup->config = NULL; -} - -/** - * @brief Configures and activates the EICU peripheral. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * @param[in] config Pointer to the @p EICUConfig object - * - * @api - */ -void eicuStart(EICUDriver *eicup, const EICUConfig *config) { - - osalDbgCheck((eicup != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((eicup->state == EICU_STOP) || (eicup->state == EICU_READY), - "invalid state"); - eicup->config = config; - eicu_lld_start(eicup); - eicup->state = EICU_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the EICU peripheral. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @api - */ -void eicuStop(EICUDriver *eicup) { - - osalDbgCheck(eicup != NULL); - - osalSysLock(); - osalDbgAssert((eicup->state == EICU_STOP) || (eicup->state == EICU_READY), - "invalid state"); - eicu_lld_stop(eicup); - eicup->state = EICU_STOP; - osalSysUnlock(); -} - -/** - * @brief Enables the extended input capture. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @api - */ -void eicuEnable(EICUDriver *eicup) { - - osalDbgCheck(eicup != NULL); - - osalSysLock(); - osalDbgAssert(eicup->state == EICU_READY, "invalid state"); - eicu_lld_enable(eicup); - eicup->state = EICU_WAITING; - osalSysUnlock(); -} - -/** - * @brief Disables the extended input capture. - * - * @param[in] eicup Pointer to the @p EICUDriver object - * - * @api - */ -void eicuDisable(EICUDriver *eicup) { - - osalDbgCheck(eicup != NULL); - - osalSysLock(); - osalDbgAssert((eicup->state == EICU_READY) || (eicup->state == EICU_IDLE) || - (eicup->state == EICU_ACTIVE) || (eicup->state == EICU_WAITING), - "invalid state"); - eicu_lld_disable(eicup); - eicup->state = EICU_READY; - osalSysUnlock(); -} - -#endif /* HAL_USE_EICU */ diff --git a/ChibiOS_16.1.5/community/os/hal/src/hal_nand.c b/ChibiOS_16.1.5/community/os/hal/src/hal_nand.c deleted file mode 100644 index 24dd6de..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/hal_nand.c +++ /dev/null @@ -1,567 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file nand.c - * @brief NAND Driver code. - * - * @addtogroup NAND - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) - -#include "string.h" /* for memset */ - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Check page size. - * - * @param[in] page_data_size size of page data area - * - * @notapi - */ -static void pagesize_check(size_t page_data_size) { - - /* Page size out of bounds.*/ - osalDbgCheck((page_data_size >= NAND_MIN_PAGE_SIZE) && - (page_data_size <= NAND_MAX_PAGE_SIZE)); - - /* Page size must be power of 2.*/ - osalDbgCheck(((page_data_size - 1) & page_data_size) == 0); -} - -/** - * @brief Translate block-page-offset scheme to NAND internal address. - * - * @param[in] cfg pointer to the @p NANDConfig from - * corresponding NAND driver - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[in] page_offset data offset related to begin of page - * @param[out] addr buffer to store calculated address - * @param[in] addr_len length of address buffer - * - * @notapi - */ -static void calc_addr(const NANDConfig *cfg, uint32_t block, uint32_t page, - uint32_t page_offset, uint8_t *addr, size_t addr_len) { - size_t i = 0; - uint32_t row = 0; - - /* Incorrect buffer length.*/ - osalDbgCheck(cfg->rowcycles + cfg->colcycles == addr_len); - osalDbgCheck((block < cfg->blocks) && (page < cfg->pages_per_block) && - (page_offset < cfg->page_data_size + cfg->page_spare_size)); - - /* convert address to NAND specific */ - memset(addr, 0, addr_len); - row = (block * cfg->pages_per_block) + page; - for (i=0; i<cfg->colcycles; i++){ - addr[i] = page_offset & 0xFF; - page_offset = page_offset >> 8; - } - for (; i<addr_len; i++){ - addr[i] = row & 0xFF; - row = row >> 8; - } -} - -/** - * @brief Translate block number to NAND internal address. - * @note This function designed for erasing purpose. - * - * @param[in] cfg pointer to the @p NANDConfig from - * corresponding NAND driver - * @param[in] block block number - * @param[out] addr buffer to store calculated address - * @param[in] addr_len length of address buffer - * - * @notapi - */ -static void calc_blk_addr(const NANDConfig *cfg, uint32_t block, - uint8_t *addr, size_t addr_len) { - size_t i = 0; - uint32_t row = 0; - - /* Incorrect buffer length.*/ - osalDbgCheck(cfg->rowcycles == addr_len); - osalDbgCheck((block < cfg->blocks)); - - /* convert address to NAND specific */ - memset(addr, 0, addr_len); - row = block * cfg->pages_per_block; - for (i=0; i<addr_len; i++){ - addr[i] = row & 0xFF; - row = row >> 8; - } -} - -/** - * @brief Read block badness mark directly from NAND memory array. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * - * @return block condition - * @retval true if the block is bad. - * @retval false if the block is good. - * - * @notapi - */ -static bool read_is_block_bad(NANDDriver *nandp, size_t block) { - - if (0xFF != nandReadBadMark(nandp, block, 0)) - return true; - if (0xFF != nandReadBadMark(nandp, block, 1)) - return true; - - return false; -} - -/** - * @brief Scan for bad blocks and fill map with their numbers. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void scan_bad_blocks(NANDDriver *nandp) { - - const size_t blocks = nandp->config->blocks; - size_t b; - - osalDbgCheck(bitmapGetBitsCount(nandp->bb_map) >= blocks); - - /* clear map just to be safe */ - bitmapObjectInit(nandp->bb_map, 0); - - /* now write numbers of bad block to map */ - for (b=0; b<blocks; b++) { - if (read_is_block_bad(nandp, b)) { - bitmapSet(nandp->bb_map, b); - } - } -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief NAND Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void nandInit(void) { - - nand_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p NANDDriver structure. - * - * @param[out] nandp pointer to the @p NANDDriver object - * - * @init - */ -void nandObjectInit(NANDDriver *nandp) { - -#if NAND_USE_MUTUAL_EXCLUSION -#if CH_CFG_USE_MUTEXES - chMtxObjectInit(&nandp->mutex); -#else - chSemObjectInit(&nandp->semaphore, 1); -#endif /* CH_CFG_USE_MUTEXES */ -#endif /* NAND_USE_MUTUAL_EXCLUSION */ - - nandp->state = NAND_STOP; - nandp->config = NULL; -} - -/** - * @brief Configures and activates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] config pointer to the @p NANDConfig object - * @param[in] bb_map pointer to the bad block map or @NULL if not need - * - * @api - */ -void nandStart(NANDDriver *nandp, const NANDConfig *config, bitmap_t *bb_map) { - - osalDbgCheck((nandp != NULL) && (config != NULL)); - osalDbgAssert((nandp->state == NAND_STOP) || - (nandp->state == NAND_READY), - "invalid state"); - - nandp->config = config; - pagesize_check(nandp->config->page_data_size); - nand_lld_start(nandp); - nandp->state = NAND_READY; - - if (NULL != bb_map) { - nandp->bb_map = bb_map; - scan_bad_blocks(nandp); - } -} - -/** - * @brief Deactivates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @api - */ -void nandStop(NANDDriver *nandp) { - - osalDbgCheck(nandp != NULL); - osalDbgAssert((nandp->state == NAND_STOP) || - (nandp->state == NAND_READY), - "invalid state"); - nand_lld_stop(nandp); - nandp->state = NAND_STOP; -} - -/** - * @brief Read whole page. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[out] data buffer to store data - * @param[in] datalen length of data buffer - * - * @api - */ -void nandReadPageWhole(NANDDriver *nandp, uint32_t block, uint32_t page, - uint8_t *data, size_t datalen) { - - const NANDConfig *cfg = nandp->config; - uint8_t addrbuf[8]; - size_t addrlen = cfg->rowcycles + cfg->colcycles; - - osalDbgCheck((nandp != NULL) && (data != NULL)); - osalDbgCheck((datalen <= (cfg->page_data_size + cfg->page_spare_size))); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_addr(cfg, block, page, 0, addrbuf, addrlen); - nand_lld_read_data(nandp, data, datalen, addrbuf, addrlen, NULL); -} - -/** - * @brief Write whole page. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[in] data buffer with data to be written - * @param[in] datalen length of data buffer - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @api - */ -uint8_t nandWritePageWhole(NANDDriver *nandp, uint32_t block, uint32_t page, - const uint8_t *data, size_t datalen) { - - uint8_t retval; - const NANDConfig *cfg = nandp->config; - uint8_t addr[8]; - size_t addrlen = cfg->rowcycles + cfg->colcycles; - - osalDbgCheck((nandp != NULL) && (data != NULL)); - osalDbgCheck((datalen <= (cfg->page_data_size + cfg->page_spare_size))); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_addr(cfg, block, page, 0, addr, addrlen); - retval = nand_lld_write_data(nandp, data, datalen, addr, addrlen, NULL); - return retval; -} - -/** - * @brief Read page data without spare area. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[out] data buffer to store data - * @param[in] datalen length of data buffer - * @param[out] ecc pointer to calculated ECC. Ignored when NULL. - * - * @api - */ -void nandReadPageData(NANDDriver *nandp, uint32_t block, uint32_t page, - uint8_t *data, size_t datalen, uint32_t *ecc) { - - const NANDConfig *cfg = nandp->config; - uint8_t addrbuf[8]; - size_t addrlen = cfg->rowcycles + cfg->colcycles; - - osalDbgCheck((nandp != NULL) && (data != NULL)); - osalDbgCheck((datalen <= cfg->page_data_size)); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_addr(cfg, block, page, 0, addrbuf, addrlen); - nand_lld_read_data(nandp, data, datalen, addrbuf, addrlen, ecc); -} - -/** - * @brief Write page data without spare area. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[in] data buffer with data to be written - * @param[in] datalen length of data buffer - * @param[out] ecc pointer to calculated ECC. Ignored when NULL. - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @api - */ -uint8_t nandWritePageData(NANDDriver *nandp, uint32_t block, uint32_t page, - const uint8_t *data, size_t datalen, uint32_t *ecc) { - - uint8_t retval; - const NANDConfig *cfg = nandp->config; - uint8_t addr[8]; - size_t addrlen = cfg->rowcycles + cfg->colcycles; - - osalDbgCheck((nandp != NULL) && (data != NULL)); - osalDbgCheck((datalen <= cfg->page_data_size)); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_addr(cfg, block, page, 0, addr, addrlen); - retval = nand_lld_write_data(nandp, data, datalen, addr, addrlen, ecc); - return retval; -} - -/** - * @brief Read page spare area. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[out] spare buffer to store data - * @param[in] sparelen length of data buffer - * - * @api - */ -void nandReadPageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, - uint8_t *spare, size_t sparelen) { - - const NANDConfig *cfg = nandp->config; - uint8_t addr[8]; - size_t addrlen = cfg->rowcycles + cfg->colcycles; - - osalDbgCheck((NULL != spare) && (nandp != NULL)); - osalDbgCheck(sparelen <= cfg->page_spare_size); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_addr(cfg, block, page, cfg->page_data_size, addr, addrlen); - nand_lld_read_data(nandp, spare, sparelen, addr, addrlen, NULL); -} - -/** - * @brief Write page spare area. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * @param[in] spare buffer with spare data to be written - * @param[in] sparelen length of data buffer - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @api - */ -uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, - const uint8_t *spare, size_t sparelen) { - - uint8_t retVal; - const NANDConfig *cfg = nandp->config; - uint8_t addr[8]; - size_t addrlen = cfg->rowcycles + cfg->colcycles; - - osalDbgCheck((NULL != spare) && (nandp != NULL)); - osalDbgCheck(sparelen <= cfg->page_spare_size); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_addr(cfg, block, page, cfg->page_data_size, addr, addrlen); - retVal = nand_lld_write_data(nandp, spare, sparelen, addr, addrlen, NULL); - return retVal; -} - -/** - * @brief Mark block as bad. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * - * @api - */ -void nandMarkBad(NANDDriver *nandp, uint32_t block) { - - uint8_t bb_mark[2] = {0, 0}; - - nandWritePageSpare(nandp, block, 0, bb_mark, sizeof(bb_mark)); - nandWritePageSpare(nandp, block, 1, bb_mark, sizeof(bb_mark)); - - if (NULL != nandp->bb_map) - bitmapSet(nandp->bb_map, block); -} - -/** - * @brief Read bad mark out. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * @param[in] page page number related to begin of block - * - * @return Bad mark. - * - * @api - */ -uint8_t nandReadBadMark(NANDDriver *nandp, uint32_t block, uint32_t page) { - uint8_t bb_mark[1]; - - nandReadPageSpare(nandp, block, page, bb_mark, sizeof(bb_mark)); - return bb_mark[0]; -} - -/** - * @brief Erase block. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @api - */ -uint8_t nandErase(NANDDriver *nandp, uint32_t block) { - - uint8_t retVal; - const NANDConfig *cfg = nandp->config; - uint8_t addr[4]; - size_t addrlen = cfg->rowcycles; - - osalDbgCheck(nandp != NULL); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - calc_blk_addr(cfg, block, addr, addrlen); - retVal = nand_lld_erase(nandp, addr, addrlen); - return retVal; -} - -/** - * @brief Check block badness. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] block block number - * - * @return block condition - * @retval true if the block is bad. - * @retval false if the block is good. - * - * @api - */ -bool nandIsBad(NANDDriver *nandp, uint32_t block) { - - osalDbgCheck(nandp != NULL); - osalDbgAssert(nandp->state == NAND_READY, "invalid state"); - - if (NULL != nandp->bb_map) - return 1 == bitmapGet(nandp->bb_map, block); - else - return read_is_block_bad(nandp, block); -} - -#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the NAND bus. - * @details This function tries to gain ownership to the NAND bus, if the bus - * is already being used then the invoking thread is queued. - * @pre In order to use this function the option - * @p NAND_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @api - */ -void nandAcquireBus(NANDDriver *nandp) { - - osalDbgCheck(nandp != NULL); - -#if CH_CFG_USE_MUTEXES - chMtxLock(&nandp->mutex); -#elif CH_CFG_USE_SEMAPHORES - chSemWait(&nandp->semaphore); -#endif -} - -/** - * @brief Releases exclusive access to the NAND bus. - * @pre In order to use this function the option - * @p NAND_USE_MUTUAL_EXCLUSION must be enabled. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @api - */ -void nandReleaseBus(NANDDriver *nandp) { - - osalDbgCheck(nandp != NULL); - -#if CH_CFG_USE_MUTEXES - chMtxUnlock(&nandp->mutex); -#elif CH_CFG_USE_SEMAPHORES - chSemSignal(&nandp->semaphore); -#endif -} -#endif /* NAND_USE_MUTUAL_EXCLUSION */ - -#endif /* HAL_USE_NAND */ - -/** @} */ - - - - diff --git a/ChibiOS_16.1.5/community/os/hal/src/hal_onewire.c b/ChibiOS_16.1.5/community/os/hal/src/hal_onewire.c deleted file mode 100644 index a93eec0..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/hal_onewire.c +++ /dev/null @@ -1,890 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/*===========================================================================*/ -/* Main ideas: */ -/*=========================================================================== - -1) switch PWM output pin to open drain mode. -2) start 2 channels _simultaneously_. First (master channel) generates - pulses (read time slots) second (sample channel) generates interrupts - from where read pin function will be called. - -- --------------------------------------- master channel generates pulses - | / . - --............................. <---------- slave (not)pulls down bus here -- -------------------------------- sample channel reads pad state - | | - ------------- - ^ - | read interrupt fires here - -For data write it is only master channel needed. Data bit width updates -on every timer overflow event. -*/ - -/*===========================================================================*/ -/* General recommendations for strong pull usage */ -/*=========================================================================== - * 1) Use separate power rail instead of strong pull up whenever possible. - * Driver's strong pull up feature is very sensible to interrupt jitter. - * 2) Use specialized 1-wire bus master (DS2484 for example) if you are - * forced to handle bus requiring strong pull up feature. - */ - -/** - * @file onewire.c - * @brief 1-wire Driver code. - * - * @addtogroup onewire - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_ONEWIRE == TRUE) || defined(__DOXYGEN__) - -#include <string.h> -#include <limits.h> - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ -/** - * @brief 1MHz clock for PWM driver. - */ -#define ONEWIRE_PWM_FREQUENCY 1000000 - -/** - * @brief Pulse width constants in microseconds. - * @details Inspired by Microchip's AN1199 - * "1-Wire® Communication with PIC® Microcontroller" - */ -#define ONEWIRE_ZERO_WIDTH 60 -#define ONEWIRE_ONE_WIDTH 6 -#define ONEWIRE_SAMPLE_WIDTH 15 -#define ONEWIRE_RECOVERY_WIDTH 10 -#define ONEWIRE_RESET_LOW_WIDTH 480 -#define ONEWIRE_RESET_SAMPLE_WIDTH 550 -#define ONEWIRE_RESET_TOTAL_WIDTH 960 - -/** - * @brief Local function declarations. - */ -static void ow_reset_cb(PWMDriver *pwmp, onewireDriver *owp); -static void pwm_reset_cb(PWMDriver *pwmp); -static void ow_read_bit_cb(PWMDriver *pwmp, onewireDriver *owp); -static void pwm_read_bit_cb(PWMDriver *pwmp); -static void ow_write_bit_cb(PWMDriver *pwmp, onewireDriver *owp); -static void pwm_write_bit_cb(PWMDriver *pwmp); -#if ONEWIRE_USE_SEARCH_ROM -static void ow_search_rom_cb(PWMDriver *pwmp, onewireDriver *owp); -static void pwm_search_rom_cb(PWMDriver *pwmp); -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -/** - * @brief 1-wire driver identifier. - */ -onewireDriver OWD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ -/** - * @brief Look up table for fast 1-wire CRC calculation - */ -static const uint8_t onewire_crc_table[256] = { - 0x0, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83, - 0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41, - 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e, - 0x5f, 0x1, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc, - 0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0, - 0xe1, 0xbf, 0x5d, 0x3, 0x80, 0xde, 0x3c, 0x62, - 0xbe, 0xe0, 0x2, 0x5c, 0xdf, 0x81, 0x63, 0x3d, - 0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff, - 0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5, - 0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x7, - 0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x6, 0x58, - 0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a, - 0x65, 0x3b, 0xd9, 0x87, 0x4, 0x5a, 0xb8, 0xe6, - 0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24, - 0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b, - 0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x5, 0xe7, 0xb9, - 0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0xf, - 0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd, - 0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92, - 0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0xe, 0x50, - 0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c, - 0x6d, 0x33, 0xd1, 0x8f, 0xc, 0x52, 0xb0, 0xee, - 0x32, 0x6c, 0x8e, 0xd0, 0x53, 0xd, 0xef, 0xb1, - 0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73, - 0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49, - 0x8, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b, - 0x57, 0x9, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4, - 0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16, - 0xe9, 0xb7, 0x55, 0xb, 0x88, 0xd6, 0x34, 0x6a, - 0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8, - 0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7, - 0xb6, 0xe8, 0xa, 0x54, 0xd7, 0x89, 0x6b, 0x35 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ -/** - * @brief Put bus in idle mode. - */ -static void ow_bus_idle(onewireDriver *owp) { -#if defined(STM32F1XX) - palSetPadMode(owp->config->port, owp->config->pad, - owp->config->pad_mode_idle); -#endif - pwmStop(owp->config->pwmd); -} - -/** - * @brief Put bus in active mode. - */ -static void ow_bus_active(onewireDriver *owp) { - pwmStart(owp->config->pwmd, owp->config->pwmcfg); -#if defined(STM32F1XX) - palSetPadMode(owp->config->port, owp->config->pad, - owp->config->pad_mode_active); -#endif -} - -/** - * @brief Function performing read of single bit. - * @note It must be callable from any context. - */ -static ioline_t ow_read_bit(onewireDriver *owp) { -#if ONEWIRE_SYNTH_SEARCH_TEST - (void)owp; - return _synth_ow_read_bit(); -#else - return palReadPad(owp->config->port, owp->config->pad); -#endif -} - -/** - * @brief PWM adapter - */ -static void pwm_reset_cb(PWMDriver *pwmp) { - ow_reset_cb(pwmp, &OWD1); -} - -/** - * @brief PWM adapter - */ -static void pwm_read_bit_cb(PWMDriver *pwmp) { - ow_read_bit_cb(pwmp, &OWD1); -} - -/** - * @brief PWM adapter - */ -static void pwm_write_bit_cb(PWMDriver *pwmp) { - ow_write_bit_cb(pwmp, &OWD1); -} - -#if ONEWIRE_USE_SEARCH_ROM -/** - * @brief PWM adapter - */ -static void pwm_search_rom_cb(PWMDriver *pwmp) { - ow_search_rom_cb(pwmp, &OWD1); -} -#endif /* ONEWIRE_USE_SEARCH_ROM */ - -/** - * @brief Write bit routine. - * @details Switch PWM channel to 'width' or 'narrow' pulse depending - * on value of bit need to be transmitted. - * - * @param[in] owp pointer to the @p onewireDriver object - * @param[in] bit value to be written - * - * @notapi - */ -static void ow_write_bit_I(onewireDriver *owp, ioline_t bit) { -#if ONEWIRE_SYNTH_SEARCH_TEST - _synth_ow_write_bit(owp, bit); -#else - osalSysLockFromISR(); - if (0 == bit) { - pwmEnableChannelI(owp->config->pwmd, owp->config->master_channel, - ONEWIRE_ZERO_WIDTH); - } - else { - pwmEnableChannelI(owp->config->pwmd, owp->config->master_channel, - ONEWIRE_ONE_WIDTH); - } - osalSysUnlockFromISR(); -#endif -} - -/** - * @brief 1-wire reset pulse callback. - * @note Must be called from PWM's ISR. - * - * @param[in] pwmp pointer to the @p PWMDriver object - * @param[in] owp pointer to the @p onewireDriver object - * - * @notapi - */ -static void ow_reset_cb(PWMDriver *pwmp, onewireDriver *owp) { - - owp->reg.slave_present = (PAL_LOW == ow_read_bit(owp)); - - osalSysLockFromISR(); - pwmDisableChannelI(pwmp, owp->config->sample_channel); - osalThreadResumeI(&owp->thread, MSG_OK); - osalSysUnlockFromISR(); -} - -/** - * @brief 1-wire read bit callback. - * @note Must be called from PWM's ISR. - * - * @param[in] pwmp pointer to the @p PWMDriver object - * @param[in] owp pointer to the @p onewireDriver object - * - * @notapi - */ -static void ow_read_bit_cb(PWMDriver *pwmp, onewireDriver *owp) { - - if (true == owp->reg.final_timeslot) { - osalSysLockFromISR(); - pwmDisableChannelI(pwmp, owp->config->sample_channel); - osalThreadResumeI(&owp->thread, MSG_OK); - osalSysUnlockFromISR(); - return; - } - else { - *owp->buf |= ow_read_bit(owp) << owp->reg.bit; - owp->reg.bit++; - if (8 == owp->reg.bit) { - owp->reg.bit = 0; - owp->buf++; - owp->reg.bytes--; - if (0 == owp->reg.bytes) { - owp->reg.final_timeslot = true; - osalSysLockFromISR(); - /* Only master channel must be stopped here. - Sample channel will be stopped in next ISR call. - It is still needed to generate final interrupt. */ - pwmDisableChannelI(pwmp, owp->config->master_channel); - osalSysUnlockFromISR(); - } - } - } -} - -/** - * @brief 1-wire bit transmission callback. - * @note Must be called from PWM's ISR. - * - * @param[in] pwmp pointer to the @p PWMDriver object - * @param[in] owp pointer to the @p onewireDriver object - * - * @notapi - */ -static void ow_write_bit_cb(PWMDriver *pwmp, onewireDriver *owp) { - - if (8 == owp->reg.bit) { - owp->buf++; - owp->reg.bit = 0; - owp->reg.bytes--; - - if (0 == owp->reg.bytes) { - osalSysLockFromISR(); - pwmDisableChannelI(pwmp, owp->config->master_channel); - osalSysUnlockFromISR(); - /* used to prevent premature timer stop from userspace */ - owp->reg.final_timeslot = true; - return; - } - } - - /* wait until timer generate last pulse */ - if (true == owp->reg.final_timeslot) { - #if ONEWIRE_USE_STRONG_PULLUP - if (owp->reg.need_pullup) { - owp->reg.state = ONEWIRE_PULL_UP; - owp->config->pullup_assert(); - owp->reg.need_pullup = false; - } - #endif - - osalSysLockFromISR(); - osalThreadResumeI(&owp->thread, MSG_OK); - osalSysUnlockFromISR(); - return; - } - - ow_write_bit_I(owp, (*owp->buf >> owp->reg.bit) & 1); - owp->reg.bit++; -} - -#if ONEWIRE_USE_SEARCH_ROM -/** - * @brief Helper function for collision handler - * - * @param[in] sr pointer to the @p onewire_search_rom_t helper structure - * @param[in] bit discovered bit to be stored in helper structure - */ -static void store_bit(onewire_search_rom_t *sr, uint8_t bit) { - - size_t rb = sr->reg.rombit; - - sr->retbuf[rb / CHAR_BIT] |= bit << (rb % CHAR_BIT); - sr->reg.rombit++; -} - -/** - * @brief Helper function for collision handler - * @details Extract bit from previous search path. - * - * @param[in] path pointer to the array with previous path stored in - * 'search ROM' helper structure - * @param[in] bit number of bit [0..63] - */ -static uint8_t extract_path_bit(const uint8_t *path, size_t bit) { - - return (path[bit / CHAR_BIT] >> (bit % CHAR_BIT)) & 1; -} - -/** - * @brief Collision handler for 'search ROM' procedure. - * @details You can find algorithm details in APPNOTE 187 - * "1-Wire Search Algorithm" from Maxim - * - * @param[in,out] sr pointer to the @p onewire_search_rom_t helper structure - */ -static uint8_t collision_handler(onewire_search_rom_t *sr) { - - uint8_t bit; - - switch(sr->reg.search_iter) { - case ONEWIRE_SEARCH_ROM_NEXT: - if ((int)sr->reg.rombit < sr->last_zero_branch) { - bit = extract_path_bit(sr->prev_path, sr->reg.rombit); - if (0 == bit) { - sr->prev_zero_branch = sr->reg.rombit; - sr->reg.result = ONEWIRE_SEARCH_ROM_SUCCESS; - } - store_bit(sr, bit); - return bit; - } - else if ((int)sr->reg.rombit == sr->last_zero_branch) { - sr->last_zero_branch = sr->prev_zero_branch; - store_bit(sr, 1); - return 1; - } - else { - /* found next branch some levels deeper */ - sr->prev_zero_branch = sr->last_zero_branch; - sr->last_zero_branch = sr->reg.rombit; - store_bit(sr, 0); - sr->reg.result = ONEWIRE_SEARCH_ROM_SUCCESS; - return 0; - } - break; - - case ONEWIRE_SEARCH_ROM_FIRST: - /* always take 0-branch */ - sr->prev_zero_branch = sr->last_zero_branch; - sr->last_zero_branch = sr->reg.rombit; - store_bit(sr, 0); - sr->reg.result = ONEWIRE_SEARCH_ROM_SUCCESS; - return 0; - break; - - default: - osalSysHalt("Unhandled case"); - return 0; /* warning supressor */ - break; - } -} - -/** - * @brief 1-wire search ROM callback. - * @note Must be called from PWM's ISR. - * - * @param[in] pwmp pointer to the @p PWMDriver object - * @param[in] owp pointer to the @p onewireDriver object - * - * @notapi - */ -static void ow_search_rom_cb(PWMDriver *pwmp, onewireDriver *owp) { - - onewire_search_rom_t *sr = &owp->search_rom; - - if (0 == sr->reg.bit_step) { /* read direct bit */ - sr->reg.bit_buf |= ow_read_bit(owp); - sr->reg.bit_step++; - } - else if (1 == sr->reg.bit_step) { /* read complement bit */ - sr->reg.bit_buf |= ow_read_bit(owp) << 1; - sr->reg.bit_step++; - switch(sr->reg.bit_buf){ - case 0b11: - /* no one device on bus or any other fail happened */ - sr->reg.result = ONEWIRE_SEARCH_ROM_ERROR; - goto THE_END; - break; - case 0b01: - /* all slaves have 1 in this position */ - store_bit(sr, 1); - ow_write_bit_I(owp, 1); - break; - case 0b10: - /* all slaves have 0 in this position */ - store_bit(sr, 0); - ow_write_bit_I(owp, 0); - break; - case 0b00: - /* collision */ - sr->reg.single_device = false; - ow_write_bit_I(owp, collision_handler(sr)); - break; - } - } - else { /* start next step */ - #if !ONEWIRE_SYNTH_SEARCH_TEST - ow_write_bit_I(owp, 1); - #endif - sr->reg.bit_step = 0; - sr->reg.bit_buf = 0; - } - - /* one ROM successfully discovered */ - if (64 == sr->reg.rombit) { - sr->reg.devices_found++; - sr->reg.search_iter = ONEWIRE_SEARCH_ROM_NEXT; - if (true == sr->reg.single_device) - sr->reg.result = ONEWIRE_SEARCH_ROM_LAST; - goto THE_END; - } - return; /* next search bit iteration */ - -THE_END: -#if ONEWIRE_SYNTH_SEARCH_TEST - (void)pwmp; - return; -#else - osalSysLockFromISR(); - pwmDisableChannelI(pwmp, owp->config->master_channel); - pwmDisableChannelI(pwmp, owp->config->sample_channel); - osalThreadResumeI(&(owp)->thread, MSG_OK); - osalSysUnlockFromISR(); -#endif -} - -/** - * @brief Helper function. Initialize structures required by 'search ROM'. - * @details Early reset. Call it once before 'search ROM' routine. - * - * @param[in] sr pointer to the @p onewire_search_rom_t helper structure - */ -static void search_clean_start(onewire_search_rom_t *sr) { - - sr->reg.single_device = true; /* presume simplest way at beginning */ - sr->reg.result = ONEWIRE_SEARCH_ROM_LAST; - sr->reg.search_iter = ONEWIRE_SEARCH_ROM_FIRST; - sr->retbuf = NULL; - sr->reg.devices_found = 0; - memset(sr->prev_path, 0, 8); - - sr->reg.rombit = 0; - sr->reg.bit_step = 0; - sr->reg.bit_buf = 0; - sr->last_zero_branch = -1; - sr->prev_zero_branch = -1; -} - -/** - * @brief Helper function. Prepare structures required by 'search ROM'. - * - * @param[in] sr pointer to the @p onewire_search_rom_t helper structure - */ -static void search_clean_iteration(onewire_search_rom_t *sr) { - - sr->reg.rombit = 0; - sr->reg.bit_step = 0; - sr->reg.bit_buf = 0; - sr->reg.result = ONEWIRE_SEARCH_ROM_LAST; -} -#endif /* ONEWIRE_USE_SEARCH_ROM */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Calculates 1-wire CRC. - * - * @param[in] buf pointer to the data buffer - * @param[in] len lenght of data buffer - * - * @init - */ -uint8_t onewireCRC(const uint8_t *buf, size_t len) { - uint8_t ret = 0; - size_t i; - - for (i=0; i<len; i++) - ret = onewire_crc_table[ret ^ buf[i]]; - - return ret; -} - -/** - * @brief Initializes @p onewireDriver structure. - * - * @param[out] owp pointer to the @p onewireDriver object - * - * @init - */ -void onewireObjectInit(onewireDriver *owp) { - - osalDbgCheck(NULL != owp); - - owp->config = NULL; - owp->reg.slave_present = false; - owp->reg.state = ONEWIRE_STOP; - owp->thread = NULL; - - owp->reg.bytes = 0; - owp->reg.bit = 0; - owp->reg.final_timeslot = false; - owp->buf = NULL; - -#if ONEWIRE_USE_STRONG_PULLUP - owp->reg.need_pullup = false; -#endif -} - -/** - * @brief Configures and activates the 1-wire driver. - * - * @param[in] owp pointer to the @p onewireDriver object - * @param[in] config pointer to the @p onewireConfig object - * - * @api - */ -void onewireStart(onewireDriver *owp, const onewireConfig *config) { - - osalDbgCheck((NULL != owp) && (NULL != config)); - osalDbgAssert(PWM_STOP == config->pwmd->state, - "PWM will be started by onewire driver internally"); - osalDbgAssert(ONEWIRE_STOP == owp->reg.state, "Invalid state"); -#if ONEWIRE_USE_STRONG_PULLUP - osalDbgCheck((NULL != config->pullup_assert) && - (NULL != config->pullup_release)); -#endif - - owp->config = config; - owp->config->pwmcfg->frequency = ONEWIRE_PWM_FREQUENCY; - owp->config->pwmcfg->period = ONEWIRE_RESET_TOTAL_WIDTH; - -#if !defined(STM32F1XX) - palSetPadMode(owp->config->port, owp->config->pad, - owp->config->pad_mode_active); -#endif - ow_bus_idle(owp); - owp->reg.state = ONEWIRE_READY; -} - -/** - * @brief Deactivates the UART peripheral. - * - * @param[in] owp pointer to the @p onewireDriver object - * - * @api - */ -void onewireStop(onewireDriver *owp) { - osalDbgCheck(NULL != owp); -#if ONEWIRE_USE_STRONG_PULLUP - owp->config->pullup_release(); -#endif - ow_bus_idle(owp); - pwmStop(owp->config->pwmd); - owp->config = NULL; - owp->reg.state = ONEWIRE_STOP; -} - -/** - * @brief Generate reset pulse on bus. - * - * @param[in] owp pointer to the @p onewireDriver object - * - * @return Bool flag denoting device presence. - * @retval true There is at least one device on bus. - */ -bool onewireReset(onewireDriver *owp) { - PWMDriver *pwmd; - PWMConfig *pwmcfg; - size_t mch, sch; - - osalDbgCheck(NULL != owp); - osalDbgAssert(owp->reg.state == ONEWIRE_READY, "Invalid state"); - - /* short circuit on bus or any other device transmit data */ - if (PAL_LOW == ow_read_bit(owp)) - return false; - - pwmd = owp->config->pwmd; - pwmcfg = owp->config->pwmcfg; - mch = owp->config->master_channel; - sch = owp->config->sample_channel; - - - pwmcfg->period = ONEWIRE_RESET_LOW_WIDTH + ONEWIRE_RESET_SAMPLE_WIDTH; - pwmcfg->callback = NULL; - pwmcfg->channels[mch].callback = NULL; - pwmcfg->channels[mch].mode = owp->config->pwmmode; - pwmcfg->channels[sch].callback = pwm_reset_cb; - pwmcfg->channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW; - - ow_bus_active(owp); - - osalSysLock(); - pwmEnableChannelI(pwmd, mch, ONEWIRE_RESET_LOW_WIDTH); - pwmEnableChannelI(pwmd, sch, ONEWIRE_RESET_SAMPLE_WIDTH); - pwmEnableChannelNotificationI(pwmd, sch); - osalThreadSuspendS(&owp->thread); - osalSysUnlock(); - - ow_bus_idle(owp); - - /* wait until slave release bus to discriminate short circuit condition */ - osalThreadSleepMicroseconds(500); - return (PAL_HIGH == ow_read_bit(owp)) && (true == owp->reg.slave_present); -} - -/** - * @brief Read some bites from slave device. - * - * @param[in] owp pointer to the @p onewireDriver object - * @param[out] rxbuf pointer to the buffer for read data - * @param[in] rxbytes amount of data to be received - */ -void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes) { - PWMDriver *pwmd; - PWMConfig *pwmcfg; - size_t mch, sch; - - osalDbgCheck((NULL != owp) && (NULL != rxbuf)); - osalDbgCheck((rxbytes > 0) && (rxbytes <= ONEWIRE_MAX_TRANSACTION_LEN)); - osalDbgAssert(owp->reg.state == ONEWIRE_READY, "Invalid state"); - - /* Buffer zeroing. This is important because of driver collects - bits using |= operation.*/ - memset(rxbuf, 0, rxbytes); - - pwmd = owp->config->pwmd; - pwmcfg = owp->config->pwmcfg; - mch = owp->config->master_channel; - sch = owp->config->sample_channel; - - owp->reg.bit = 0; - owp->reg.final_timeslot = false; - owp->buf = rxbuf; - owp->reg.bytes = rxbytes; - - pwmcfg->period = ONEWIRE_ZERO_WIDTH + ONEWIRE_RECOVERY_WIDTH; - pwmcfg->callback = NULL; - pwmcfg->channels[mch].callback = NULL; - pwmcfg->channels[mch].mode = owp->config->pwmmode; - pwmcfg->channels[sch].callback = pwm_read_bit_cb; - pwmcfg->channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW; - - ow_bus_active(owp); - osalSysLock(); - pwmEnableChannelI(pwmd, mch, ONEWIRE_ONE_WIDTH); - pwmEnableChannelI(pwmd, sch, ONEWIRE_SAMPLE_WIDTH); - pwmEnableChannelNotificationI(pwmd, sch); - osalThreadSuspendS(&owp->thread); - osalSysUnlock(); - - ow_bus_idle(owp); -} - -/** - * @brief Read some bites from slave device. - * - * @param[in] owp pointer to the @p onewireDriver object - * @param[in] txbuf pointer to the buffer with data to be written - * @param[in] txbytes amount of data to be written - * @param[in] pullup_time how long strong pull up must be activated. Set - * it to 0 if not needed. - */ -void onewireWrite(onewireDriver *owp, uint8_t *txbuf, - size_t txbytes, systime_t pullup_time) { - PWMDriver *pwmd; - PWMConfig *pwmcfg; - size_t mch, sch; - - osalDbgCheck((NULL != owp) && (NULL != txbuf)); - osalDbgCheck((txbytes > 0) && (txbytes <= ONEWIRE_MAX_TRANSACTION_LEN)); - osalDbgAssert(owp->reg.state == ONEWIRE_READY, "Invalid state"); -#if !ONEWIRE_USE_STRONG_PULLUP - osalDbgAssert(0 == pullup_time, - "Non zero time is valid only when strong pull enabled"); -#endif - - pwmd = owp->config->pwmd; - pwmcfg = owp->config->pwmcfg; - mch = owp->config->master_channel; - sch = owp->config->sample_channel; - - owp->buf = txbuf; - owp->reg.bit = 0; - owp->reg.final_timeslot = false; - owp->reg.bytes = txbytes; - - pwmcfg->period = ONEWIRE_ZERO_WIDTH + ONEWIRE_RECOVERY_WIDTH; - pwmcfg->callback = pwm_write_bit_cb; - pwmcfg->channels[mch].callback = NULL; - pwmcfg->channels[mch].mode = owp->config->pwmmode; - pwmcfg->channels[sch].callback = NULL; - pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED; - -#if ONEWIRE_USE_STRONG_PULLUP - if (pullup_time > 0) { - owp->reg.state = ONEWIRE_PULL_UP; - owp->reg.need_pullup = true; - } -#endif - - ow_bus_active(owp); - osalSysLock(); - pwmEnablePeriodicNotificationI(pwmd); - osalThreadSuspendS(&owp->thread); - osalSysUnlock(); - - pwmDisablePeriodicNotification(pwmd); - ow_bus_idle(owp); - -#if ONEWIRE_USE_STRONG_PULLUP - if (pullup_time > 0) { - osalThreadSleep(pullup_time); - owp->config->pullup_release(); - owp->reg.state = ONEWIRE_READY; - } -#endif -} - -#if ONEWIRE_USE_SEARCH_ROM -/** - * @brief Performs tree search on bus. - * @note This function does internal 1-wire reset calls every search - * iteration. - * - * @param[in] owp pointer to a @p OWDriver object - * @param[out] result pointer to buffer for discovered ROMs - * @param[in] max_rom_cnt buffer size in ROMs count for overflow prevention - * - * @return Count of discovered ROMs. May be more than max_rom_cnt. - * @retval 0 no ROMs found or communication error occurred. - */ -size_t onewireSearchRom(onewireDriver *owp, uint8_t *result, - size_t max_rom_cnt) { - PWMDriver *pwmd; - PWMConfig *pwmcfg; - uint8_t cmd; - size_t mch, sch; - - osalDbgCheck(NULL != owp); - osalDbgAssert(ONEWIRE_READY == owp->reg.state, "Invalid state"); - osalDbgCheck((max_rom_cnt <= 256) && (max_rom_cnt > 0)); - - pwmd = owp->config->pwmd; - pwmcfg = owp->config->pwmcfg; - cmd = ONEWIRE_CMD_SEARCH_ROM; - mch = owp->config->master_channel; - sch = owp->config->sample_channel; - - search_clean_start(&owp->search_rom); - - do { - /* every search must be started from reset pulse */ - if (false == onewireReset(owp)) - return 0; - - /* initialize buffer to store result */ - if (owp->search_rom.reg.devices_found >= max_rom_cnt) - owp->search_rom.retbuf = result + 8*(max_rom_cnt-1); - else - owp->search_rom.retbuf = result + 8*owp->search_rom.reg.devices_found; - memset(owp->search_rom.retbuf, 0, 8); - - /* clean iteration state */ - search_clean_iteration(&owp->search_rom); - - /**/ - onewireWrite(&OWD1, &cmd, 1, 0); - - /* Reconfiguration always needed because of previous call onewireWrite.*/ - pwmcfg->period = ONEWIRE_ZERO_WIDTH + ONEWIRE_RECOVERY_WIDTH; - pwmcfg->callback = NULL; - pwmcfg->channels[mch].callback = NULL; - pwmcfg->channels[mch].mode = owp->config->pwmmode; - pwmcfg->channels[sch].callback = pwm_search_rom_cb; - pwmcfg->channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW; - - ow_bus_active(owp); - osalSysLock(); - pwmEnableChannelI(pwmd, mch, ONEWIRE_ONE_WIDTH); - pwmEnableChannelI(pwmd, sch, ONEWIRE_SAMPLE_WIDTH); - pwmEnableChannelNotificationI(pwmd, sch); - osalThreadSuspendS(&owp->thread); - osalSysUnlock(); - - ow_bus_idle(owp); - - if (ONEWIRE_SEARCH_ROM_ERROR != owp->search_rom.reg.result) { - /* check CRC and return 0 (0 == error) if mismatch */ - if (owp->search_rom.retbuf[7] != onewireCRC(owp->search_rom.retbuf, 7)) - return 0; - /* store cached result for usage in next iteration */ - memcpy(owp->search_rom.prev_path, owp->search_rom.retbuf, 8); - } - } - while (ONEWIRE_SEARCH_ROM_SUCCESS == owp->search_rom.reg.result); - - /**/ - if (ONEWIRE_SEARCH_ROM_ERROR == owp->search_rom.reg.result) - return 0; - else - return owp->search_rom.reg.devices_found; -} -#endif /* ONEWIRE_USE_SEARCH_ROM */ - -/* - * Include test code (if enabled). - */ -#if ONEWIRE_SYNTH_SEARCH_TEST -#include "search_rom_synth.c" -#endif - -#endif /* HAL_USE_ONEWIRE */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/src/hal_qei.c b/ChibiOS_16.1.5/community/os/hal/src/hal_qei.c deleted file mode 100644 index a2b7303..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/hal_qei.c +++ /dev/null @@ -1,214 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2016 Martino Migliavacca
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file hal_qei.c
- * @brief QEI Driver code.
- *
- * @addtogroup QEI
- * @{
- */
-
-#include "hal.h"
-
-#if (HAL_USE_QEI == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief QEI Driver initialization.
- * @note This function is implicitly invoked by @p halInit(), there is
- * no need to explicitly initialize the driver.
- *
- * @init
- */
-void qeiInit(void) {
-
- qei_lld_init();
-}
-
-/**
- * @brief Initializes the standard part of a @p QEIDriver structure.
- *
- * @param[out] qeip pointer to the @p QEIDriver object
- *
- * @init
- */
-void qeiObjectInit(QEIDriver *qeip) {
-
- qeip->state = QEI_STOP;
- qeip->last = 0;
- qeip->config = NULL;
-}
-
-/**
- * @brief Configures and activates the QEI peripheral.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- * @param[in] config pointer to the @p QEIConfig object
- *
- * @api
- */
-void qeiStart(QEIDriver *qeip, const QEIConfig *config) {
-
- osalDbgCheck((qeip != NULL) && (config != NULL));
-
- osalSysLock();
- osalDbgAssert((qeip->state == QEI_STOP) || (qeip->state == QEI_READY),
- "invalid state");
- qeip->config = config;
- qei_lld_start(qeip);
- qeip->state = QEI_READY;
- osalSysUnlock();
-}
-
-/**
- * @brief Deactivates the QEI peripheral.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- *
- * @api
- */
-void qeiStop(QEIDriver *qeip) {
-
- osalDbgCheck(qeip != NULL);
-
- osalSysLock();
- osalDbgAssert((qeip->state == QEI_STOP) || (qeip->state == QEI_READY),
- "invalid state");
- qei_lld_stop(qeip);
- qeip->state = QEI_STOP;
- osalSysUnlock();
-}
-
-/**
- * @brief Enables the quadrature encoder interface.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- *
- * @api
- */
-void qeiEnable(QEIDriver *qeip) {
-
- osalDbgCheck(qeip != NULL);
-
- osalSysLock();
- osalDbgAssert(qeip->state == QEI_READY, "invalid state");
- qei_lld_enable(qeip);
- qeip->state = QEI_ACTIVE;
- osalSysUnlock();
-}
-
-/**
- * @brief Disables the quadrature encoder interface.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- *
- * @api
- */
-void qeiDisable(QEIDriver *qeip) {
-
- osalDbgCheck(qeip != NULL);
-
- osalSysLock();
- osalDbgAssert((qeip->state == QEI_READY) || (qeip->state == QEI_ACTIVE),
- "invalid state");
- qei_lld_disable(qeip);
- qeip->state = QEI_READY;
- osalSysUnlock();
-}
-
-/**
- * @brief Returns the counter value.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- * @return The current counter value.
- *
- * @api
- */
-qeicnt_t qeiGetCount(QEIDriver *qeip) {
- qeicnt_t cnt;
-
- osalSysLock();
- cnt = qeiGetCountI(qeip);
- osalSysUnlock();
-
- return cnt;
-}
-
-/**
- * @brief Returns the counter delta from last reading.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- * @return The delta from last read.
- *
- * @api
- */
-qeidelta_t qeiUpdate(QEIDriver *qeip) {
- qeidelta_t diff;
-
- osalSysLock();
- diff = qeiUpdateI(qeip);
- osalSysUnlock();
-
- return diff;
-}
-
-/**
- * @brief Returns the counter delta from last reading.
- *
- * @param[in] qeip pointer to the @p QEIDriver object
- * @return The delta from last read.
- *
- * @iclass
- */
-qeidelta_t qeiUpdateI(QEIDriver *qeip) {
- qeicnt_t cnt;
- qeidelta_t delta;
-
- osalDbgCheckClassI();
- osalDbgCheck(qeip != NULL);
- osalDbgAssert((qeip->state == QEI_READY) || (qeip->state == QEI_ACTIVE),
- "invalid state");
-
- cnt = qei_lld_get_count(qeip);
- delta = cnt - qeip->last;
- qeip->last = cnt;
-
- return delta;
-}
-
-#endif /* HAL_USE_QEI == TRUE */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/src/hal_rng.c b/ChibiOS_16.1.5/community/os/hal/src/hal_rng.c deleted file mode 100644 index 5ff6d2d..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/hal_rng.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - RNG for ChibiOS - Copyright (C) 2016 Stephane D'Alu - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * Hardware Abstraction Layer for RNG Unit - */ -#include "hal.h" - -#if (HAL_USE_RNG == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief RNG Driver initialization. - * - * @init - */ -void rngInit(void) { - rng_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p RNGDriver structure. - * - * @param[out] rngp Pointer to the @p RNGDriver object - * - * @init - */ -void rngObjectInit(RNGDriver *rngp) { - rngp->state = RNG_STOP; - rngp->config = NULL; -#if RNG_USE_MUTUAL_EXCLUSION == TRUE - osalMutexObjectInit(&rngp->mutex); -#endif -#if defined(RNG_DRIVER_EXT_INIT_HOOK) - RNG_DRIVER_EXT_INIT_HOOK(rngp); -#endif -} - -/** - * @brief Configures and activates the RNG peripheral. - * - * @param[in] rngp Pointer to the @p RNGDriver object - * @param[in] config Pointer to the @p RNGConfig object - * @p NULL if the low level driver implementation - * supports a default configuration - * - * @api - */ -void rngStart(RNGDriver *rngp, const RNGConfig *config) { - osalDbgCheck(rngp != NULL); - - osalSysLock(); - osalDbgAssert((rngp->state == RNG_STOP) || (rngp->state == RNG_READY), - "invalid state"); - rngp->config = config; - rng_lld_start(rngp); - rngp->state = RNG_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the RNG peripheral. - * - * @param[in] rngp Pointer to the @p RNGDriver object - * - * @api - */ -void rngStop(RNGDriver *rngp) { - osalDbgCheck(rngp != NULL); - - osalSysLock(); - osalDbgAssert((rngp->state == RNG_STOP) || (rngp->state == RNG_READY), - "invalid state"); - rng_lld_stop(rngp); - rngp->state = RNG_STOP; - osalSysUnlock(); -} - -/** - * @brief Write random bytes - * @details Write the request number of bytes.. - * - * @param[in] rngp pointer to the @p RNGDriver object - * @param[in] buf the pointer to the buffer - * @param[in] n number of bytes to send - * @param[in] timeout timeout value - * - * @api - */ -msg_t rngWrite(RNGDriver *rngp, uint8_t *buf, size_t n, systime_t timeout) { - msg_t msg; - osalSysLock(); - msg = rngWriteI(rngp, buf, n, timeout); - osalSysUnlock(); - return msg; -} - -/** - * @brief Write random bytes - * @details Write the request number of bytes.. - * - * @param[in] rngp pointer to the @p RNGDriver object - * @param[in] buf the pointer to the buffer - * @param[in] n number of bytes to send - * @param[in] timeout timeout value - * - * @iclass - */ -msg_t rngWriteI(RNGDriver *rngp, uint8_t *buf, size_t n, systime_t timeout) { - osalDbgCheck((rngp != NULL) && (n > 0U) && (buf != NULL)); - osalDbgAssert(rngp->state == RNG_READY, "not ready"); - return rng_lld_write(rngp, buf, n, timeout); -} - - -#if (RNG_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) -/** - * @brief Gains exclusive access to the RNG unit. - * @details This function tries to gain ownership to the RNG, if the RNG is - * already being used then the invoking thread is queued. - * @pre In order to use this function the option @p RNG_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] rngp pointer to the @p RNGDriver object - * - * @api - */ -void rngAcquireUnit(RNGDriver *rngp) { - osalDbgCheck(rngp != NULL); - - osalMutexLock(&rngp->mutex); -} - -/** - * @brief Releases exclusive access to the RNG unit. - * @pre In order to use this function the option @p RNG_USE_MUTUAL_EXCLUSION - * must be enabled. - * - * @param[in] rngp pointer to the @p RNGDriver object - * - * @api - */ -void rngReleaseUnit(RNGDriver *rngp) { - osalDbgCheck(rngp != NULL); - - osalMutexUnlock(&rngp->mutex); -} -#endif /* RNG_USE_MUTUAL_EXCLUSION == TRUE */ - -#endif /* HAL_USE_RNG */ diff --git a/ChibiOS_16.1.5/community/os/hal/src/hal_timcap.c b/ChibiOS_16.1.5/community/os/hal/src/hal_timcap.c deleted file mode 100644 index a352490..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/hal_timcap.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see <http://www.gnu.org/licenses/>. -*/ - -/** - * @file timcap.c - * @brief TIMCAP Driver code. - * - * @addtogroup TIMCAP - * @{ - */ - -#include "hal_timcap.h" - -#if HAL_USE_TIMCAP || defined(__DOXYGEN__) - - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief TIMCAP Driver initialization. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. - * - * @init - */ -void timcapInit(void) { - - timcap_lld_init(); -} - -/** - * @brief Initializes the standard part of a @p TIMCAPDriver structure. - * - * @param[out] timcapp pointer to the @p TIMCAPDriver object - * - * @init - */ -void timcapObjectInit(TIMCAPDriver *timcapp) { - - timcapp->state = TIMCAP_STOP; - timcapp->config = NULL; -} - -/** - * @brief Configures and activates the TIMCAP peripheral. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * @param[in] config pointer to the @p TIMCAPConfig object - * - * @api - */ -void timcapStart(TIMCAPDriver *timcapp, const TIMCAPConfig *config) { - - osalDbgCheck((timcapp != NULL) && (config != NULL)); - - osalSysLock(); - osalDbgAssert((timcapp->state == TIMCAP_STOP) || (timcapp->state == TIMCAP_READY), - "invalid state"); - timcapp->config = config; - timcap_lld_start(timcapp); - timcapp->state = TIMCAP_READY; - osalSysUnlock(); -} - -/** - * @brief Deactivates the TIMCAP peripheral. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @api - */ -void timcapStop(TIMCAPDriver *timcapp) { - - osalDbgCheck(timcapp != NULL); - - osalSysLock(); - osalDbgAssert((timcapp->state == TIMCAP_STOP) || (timcapp->state == TIMCAP_READY), - "invalid state"); - timcap_lld_stop(timcapp); - timcapp->state = TIMCAP_STOP; - osalSysUnlock(); -} - -/** - * @brief Enables the input capture. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @api - */ -void timcapEnable(TIMCAPDriver *timcapp) { - - osalDbgCheck(timcapp != NULL); - - osalSysLock(); - osalDbgAssert(timcapp->state == TIMCAP_READY, "invalid state"); - timcap_lld_enable(timcapp); - timcapp->state = TIMCAP_WAITING; - osalSysUnlock(); -} - -/** - * @brief Disables the input capture. - * - * @param[in] timcapp pointer to the @p TIMCAPDriver object - * - * @api - */ -void timcapDisable(TIMCAPDriver *timcapp) { - - osalDbgCheck(timcapp != NULL); - - osalSysLock(); - osalDbgAssert((timcapp->state == TIMCAP_READY) || (timcapp->state == TIMCAP_WAITING) || - (timcapp->state == TIMCAP_ACTIVE) || (timcapp->state == TIMCAP_IDLE), - "invalid state"); - timcap_lld_disable(timcapp); - timcapp->state = TIMCAP_READY; - osalSysUnlock(); -} - -#endif /* HAL_USE_TIMCAP */ - -/** @} */ diff --git a/ChibiOS_16.1.5/community/os/hal/src/hal_usb_hid.c b/ChibiOS_16.1.5/community/os/hal/src/hal_usb_hid.c deleted file mode 100644 index 56be9b7..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/hal_usb_hid.c +++ /dev/null @@ -1,581 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2016 Jonathan Struebel
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file hal_usb_hid.c
- * @brief USB HID Driver code.
- *
- * @addtogroup USB_HID
- * @{
- */
-
-#include "hal.h"
-
-#if (HAL_USE_USB_HID == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-static uint16_t get_hword(uint8_t *p) {
- uint16_t hw;
-
- hw = (uint16_t)*p++;
- hw |= (uint16_t)*p << 8U;
- return hw;
-}
-
-/*
- * Interface implementation.
- */
-
-static size_t write(void *ip, const uint8_t *bp, size_t n) {
-
- if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) {
- return 0;
- }
-
- return obqWriteTimeout(&((USBHIDDriver *)ip)->obqueue, bp,
- n, TIME_INFINITE);
-}
-
-static size_t read(void *ip, uint8_t *bp, size_t n) {
-
- if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) {
- return 0;
- }
-
- return ibqReadTimeout(&((USBHIDDriver *)ip)->ibqueue, bp,
- n, TIME_INFINITE);
-}
-
-static msg_t put(void *ip, uint8_t b) {
-
- if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) {
- return MSG_RESET;
- }
-
- return obqPutTimeout(&((USBHIDDriver *)ip)->obqueue, b, TIME_INFINITE);
-}
-
-static msg_t get(void *ip) {
-
- if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) {
- return MSG_RESET;
- }
-
- return ibqGetTimeout(&((USBHIDDriver *)ip)->ibqueue, TIME_INFINITE);
-}
-
-static msg_t putt(void *ip, uint8_t b, systime_t timeout) {
-
- if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) {
- return MSG_RESET;
- }
-
- return obqPutTimeout(&((USBHIDDriver *)ip)->obqueue, b, timeout);
-}
-
-static msg_t gett(void *ip, systime_t timeout) {
-
- if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) {
- return MSG_RESET;
- }
-
- return ibqGetTimeout(&((USBHIDDriver *)ip)->ibqueue, timeout);
-}
-
-static size_t writet(void *ip, const uint8_t *bp, size_t n, systime_t timeout) {
-
- if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) {
- return 0;
- }
-
- return obqWriteTimeout(&((USBHIDDriver *)ip)->obqueue, bp, n, timeout);
-}
-
-static size_t readt(void *ip, uint8_t *bp, size_t n, systime_t timeout) {
-
- if (usbGetDriverStateI(((USBHIDDriver *)ip)->config->usbp) != USB_ACTIVE) {
- return 0;
- }
-
- return ibqReadTimeout(&((USBHIDDriver *)ip)->ibqueue, bp, n, timeout);
-}
-
-static void flush(void *ip) {
-
- obqFlush(&((USBHIDDriver *)ip)->obqueue);
-}
-
-static const struct USBHIDDriverVMT vmt = {
- write, read, put, get,
- putt, gett, writet, readt,
- flush
-};
-
-/**
- * @brief Notification of empty buffer released into the input buffers queue.
- *
- * @param[in] bqp the buffers queue pointer.
- */
-static void ibnotify(io_buffers_queue_t *bqp) {
- USBHIDDriver *uhdp = bqGetLinkX(bqp);
-
- /* If the USB driver is not in the appropriate state then transactions
- must not be started.*/
- if ((usbGetDriverStateI(uhdp->config->usbp) != USB_ACTIVE) ||
- (uhdp->state != HID_READY)) {
- return;
- }
-
- /* Checking if there is already a transaction ongoing on the endpoint.*/
- if (!usbGetReceiveStatusI(uhdp->config->usbp, uhdp->config->int_out)) {
- /* Trying to get a free buffer.*/
- uint8_t *buf = ibqGetEmptyBufferI(&uhdp->ibqueue);
- if (buf != NULL) {
- /* Buffer found, starting a new transaction.*/
- usbStartReceiveI(uhdp->config->usbp, uhdp->config->int_out,
- buf, SERIAL_USB_BUFFERS_SIZE);
- }
- }
-}
-
-/**
- * @brief Notification of filled buffer inserted into the output buffers queue.
- *
- * @param[in] bqp the buffers queue pointer.
- */
-static void obnotify(io_buffers_queue_t *bqp) {
- size_t n;
- USBHIDDriver *uhdp = bqGetLinkX(bqp);
-
- /* If the USB driver is not in the appropriate state then transactions
- must not be started.*/
- if ((usbGetDriverStateI(uhdp->config->usbp) != USB_ACTIVE) ||
- (uhdp->state != HID_READY)) {
- return;
- }
-
- /* Checking if there is already a transaction ongoing on the endpoint.*/
- if (!usbGetTransmitStatusI(uhdp->config->usbp, uhdp->config->int_in)) {
- /* Trying to get a full buffer.*/
- uint8_t *buf = obqGetFullBufferI(&uhdp->obqueue, &n);
- if (buf != NULL) {
- /* Buffer found, starting a new transaction.*/
- usbStartTransmitI(uhdp->config->usbp, uhdp->config->int_in, buf, n);
- }
- }
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief USB HID Driver initialization.
- * @note This function is implicitly invoked by @p halInit(), there is
- * no need to explicitly initialize the driver.
- *
- * @init
- */
-void hidInit(void) {
-}
-
-/**
- * @brief Initializes a generic full duplex USB HID driver object.
- * @details The HW dependent part of the initialization has to be performed
- * outside, usually in the hardware initialization code.
- *
- * @param[out] uhdp pointer to a @p USBHIDDriver structure
- *
- * @init
- */
-void hidObjectInit(USBHIDDriver *uhdp) {
-
- uhdp->vmt = &vmt;
- osalEventObjectInit(&uhdp->event);
- uhdp->state = HID_STOP;
- ibqObjectInit(&uhdp->ibqueue, uhdp->ib,
- USB_HID_BUFFERS_SIZE, USB_HID_BUFFERS_NUMBER,
- ibnotify, uhdp);
- obqObjectInit(&uhdp->obqueue, uhdp->ob,
- USB_HID_BUFFERS_SIZE, USB_HID_BUFFERS_NUMBER,
- obnotify, uhdp);
-}
-
-/**
- * @brief Configures and starts the driver.
- *
- * @param[in] uhdp pointer to a @p USBHIDDriver object
- * @param[in] config the USB HID driver configuration
- *
- * @api
- */
-void hidStart(USBHIDDriver *uhdp, const USBHIDConfig *config) {
- USBDriver *usbp = config->usbp;
-
- osalDbgCheck(uhdp != NULL);
-
- osalSysLock();
- osalDbgAssert((uhdp->state == HID_STOP) || (uhdp->state == HID_READY),
- "invalid state");
- usbp->in_params[config->int_in - 1U] = uhdp;
- usbp->out_params[config->int_out - 1U] = uhdp;
- uhdp->config = config;
- uhdp->state = HID_READY;
- osalSysUnlock();
-}
-
-/**
- * @brief Stops the driver.
- * @details Any thread waiting on the driver's queues will be awakened with
- * the message @p MSG_RESET.
- *
- * @param[in] uhdp pointer to a @p USBHIDDriver object
- *
- * @api
- */
-void hidStop(USBHIDDriver *uhdp) {
- USBDriver *usbp = uhdp->config->usbp;
-
- osalDbgCheck(uhdp != NULL);
-
- osalSysLock();
- osalDbgAssert((uhdp->state == HID_STOP) || (uhdp->state == HID_READY),
- "invalid state");
-
- /* Driver in stopped state.*/
- usbp->in_params[uhdp->config->int_in - 1U] = NULL;
- usbp->out_params[uhdp->config->int_out - 1U] = NULL;
- uhdp->state = HID_STOP;
-
- /* Enforces a disconnection.*/
- hidDisconnectI(uhdp);
- osalOsRescheduleS();
- osalSysUnlock();
-}
-
-/**
- * @brief USB device disconnection handler.
- * @note If this function is not called from an ISR then an explicit call
- * to @p osalOsRescheduleS() in necessary afterward.
- *
- * @param[in] uhdp pointer to a @p USBHIDDriver object
- *
- * @iclass
- */
-void hidDisconnectI(USBHIDDriver *uhdp) {
-
- /* Queues reset in order to signal the driver stop to the application.*/
- chnAddFlagsI(uhdp, CHN_DISCONNECTED);
- ibqResetI(&uhdp->ibqueue);
- obqResetI(&uhdp->obqueue);
-}
-
-/**
- * @brief USB device configured handler.
- *
- * @param[in] uhdp pointer to a @p USBHIDDriver object
- *
- * @iclass
- */
-void hidConfigureHookI(USBHIDDriver *uhdp) {
- uint8_t *buf;
-
- ibqResetI(&uhdp->ibqueue);
- obqResetI(&uhdp->obqueue);
- chnAddFlagsI(uhdp, CHN_CONNECTED);
-
- /* Starts the first OUT transaction immediately.*/
- buf = ibqGetEmptyBufferI(&uhdp->ibqueue);
-
- osalDbgAssert(buf != NULL, "no free buffer");
-
- usbStartReceiveI(uhdp->config->usbp, uhdp->config->int_out,
- buf, USB_HID_BUFFERS_SIZE);
-}
-
-/**
- * @brief Default requests hook.
- * @details Applications wanting to use the USB HID driver can use
- * this function at the end of the application specific
- * requests hook. The HID_* requests handled here do not
- * transfer any data to the application.
- * The following requests are handled:
- * - HID_GET_IDLE.
- * - HID_GET_PROTOCOL.
- * - HID_SET_REPORT.
- * - HID_SET_IDLE.
- * - HID_SET_PROTOCOL.
- * - USB_REQ_GET_DESCRIPTOR.
- * .
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @return The hook status.
- * @retval true Message handled internally.
- * @retval false Message not handled.
- */
-bool hidRequestsHook(USBDriver *usbp) {
- const USBDescriptor *dp;
-
- if ((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) {
- switch (usbp->setup[1]) {
- case HID_GET_IDLE:
- usbSetupTransfer(usbp, NULL, 0, NULL);
- return true;
- case HID_GET_PROTOCOL:
- return true;
- case HID_SET_REPORT:
- usbSetupTransfer(usbp, NULL, 0, NULL);
- return true;
- case HID_SET_IDLE:
- usbSetupTransfer(usbp, NULL, 0, NULL);
- return true;
- case HID_SET_PROTOCOL:
- return true;
- default:
- return false;
- }
- }
-
- /* GET_DESCRIPTOR from interface not handled by default so handle it here */
- if (((usbp->setup[0] & USB_RTYPE_DIR_MASK) == USB_RTYPE_DIR_DEV2HOST) &&
- ((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) == USB_RTYPE_RECIPIENT_INTERFACE)) {
- switch (usbp->setup[1]) {
- case USB_REQ_GET_DESCRIPTOR:
- dp = usbp->config->get_descriptor_cb(usbp, usbp->setup[3], usbp->setup[2],
- get_hword(&usbp->setup[4]));
- if (dp == NULL)
- return false;
-
- usbSetupTransfer(usbp, (uint8_t *)dp->ud_string, dp->ud_size, NULL);
- return true;
- default:
- return false;
- }
- }
- return false;
-}
-
-/**
- * @brief Default data transmitted callback.
- * @details The application must use this function as callback for the IN
- * data endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep IN endpoint number
- */
-void hidDataTransmitted(USBDriver *usbp, usbep_t ep) {
- uint8_t *buf;
- size_t n;
- USBHIDDriver *uhdp = usbp->in_params[ep - 1U];
-
- if (uhdp == NULL) {
- return;
- }
-
- osalSysLockFromISR();
-
- /* Signaling that space is available in the output queue.*/
- chnAddFlagsI(uhdp, CHN_OUTPUT_EMPTY);
-
- /* Freeing the buffer just transmitted, if it was not a zero size packet.*/
- if (usbp->epc[ep]->in_state->txsize > 0U) {
- obqReleaseEmptyBufferI(&uhdp->obqueue);
- }
-
- /* Checking if there is a buffer ready for transmission.*/
- buf = obqGetFullBufferI(&uhdp->obqueue, &n);
-
- if (buf != NULL) {
- /* The endpoint cannot be busy, we are in the context of the callback,
- so it is safe to transmit without a check.*/
- usbStartTransmitI(usbp, ep, buf, n);
- }
- else if ((usbp->epc[ep]->in_state->txsize > 0U) &&
- ((usbp->epc[ep]->in_state->txsize &
- ((size_t)usbp->epc[ep]->in_maxsize - 1U)) == 0U)) {
- /* Transmit zero sized packet in case the last one has maximum allowed
- size. Otherwise the recipient may expect more data coming soon and
- not return buffered data to app. See section 5.8.3 Bulk Transfer
- Packet Size Constraints of the USB Specification document.*/
- usbStartTransmitI(usbp, ep, usbp->setup, 0);
-
- }
- else {
- /* Nothing to transmit.*/
- }
-
- osalSysUnlockFromISR();
-}
-
-/**
- * @brief Default data received callback.
- * @details The application must use this function as callback for the OUT
- * data endpoint.
- *
- * @param[in] usbp pointer to the @p USBDriver object
- * @param[in] ep OUT endpoint number
- */
-void hidDataReceived(USBDriver *usbp, usbep_t ep) {
- uint8_t *buf;
- USBHIDDriver *uhdp = usbp->out_params[ep - 1U];
-
- if (uhdp == NULL) {
- return;
- }
-
- osalSysLockFromISR();
-
- /* Signaling that data is available in the input queue.*/
- chnAddFlagsI(uhdp, CHN_INPUT_AVAILABLE);
-
- /* Posting the filled buffer in the queue.*/
- ibqPostFullBufferI(&uhdp->ibqueue,
- usbGetReceiveTransactionSizeX(uhdp->config->usbp, ep));
-
- /* The endpoint cannot be busy, we are in the context of the callback,
- so a packet is in the buffer for sure. Trying to get a free buffer
- for the next transaction.*/
- buf = ibqGetEmptyBufferI(&uhdp->ibqueue);
- if (buf != NULL) {
- /* Buffer found, starting a new transaction.*/
- usbStartReceiveI(uhdp->config->usbp, ep, buf, USB_HID_BUFFERS_SIZE);
- }
-
- osalSysUnlockFromISR();
-}
-
-/**
- * @brief Write HID Report
- * @details The function writes data from a buffer to an output queue. The
- * operation completes when the specified amount of data has been
- * transferred or if the queue has been reset.
- *
- * @param[in] uhdp pointer to the @p USBHIDDriver object
- * @param[in] bp pointer to the report data buffer
- * @param[in] n the maximum amount of data to be transferred, the
- * value 0 is reserved
- * @return The number of bytes effectively transferred.
- * @retval 0 if a timeout occurred.
- *
- * @api
- */
-size_t hidWriteReport(USBHIDDriver *uhdp, uint8_t *bp, size_t n) {
- size_t val;
-
- val = uhdp->vmt->write(uhdp, bp, n);
-
- if (val > 0)
- uhdp->vmt->flush(uhdp);
-
- return val;
-}
-
-/**
- * @brief Write HID report with timeout
- * @details The function writes data from a buffer to an output queue. The
- * operation completes when the specified amount of data has been
- * transferred or after the specified timeout or if the queue has
- * been reset.
- *
- * @param[in] uhdp pointer to the @p USBHIDDriver object
- * @param[in] bp pointer to the report data buffer
- * @param[in] n the maximum amount of data to be transferred, the
- * value 0 is reserved
- * @param[in] timeout the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The number of bytes effectively transferred.
- * @retval 0 if a timeout occurred.
- *
- * @api
- */
-size_t hidWriteReportt(USBHIDDriver *uhdp, uint8_t *bp, size_t n, systime_t timeout) {
- size_t val;
-
- val = uhdp->vmt->writet(uhdp, bp, n, timeout);
-
- if (val > 0)
- uhdp->vmt->flush(uhdp);
-
- return val;
-}
-
-/**
- * @brief Read HID report
- * @details The function reads data from an input queue into a buffer.
- * The operation completes when the specified amount of data has been
- * transferred or if the queue has been reset.
- *
- * @param[in] uhdp pointer to the @p input_buffers_queue_t object
- * @param[out] bp pointer to the data buffer
- * @param[in] n the maximum amount of data to be transferred, the
- * value 0 is reserved
- * @return The number of bytes effectively transferred.
- * @retval 0 if a timeout occurred.
- *
- * @api
- */
-size_t hidReadReport(USBHIDDriver *uhdp, uint8_t *bp, size_t n) {
-
- return uhdp->vmt->read(uhdp, bp, n);
-}
-
-/**
- * @brief Read HID report with timeout
- * @details The function reads data from an input queue into a buffer.
- * The operation completes when the specified amount of data has been
- * transferred or after the specified timeout or if the queue has
- * been reset.
- *
- * @param[in] uhdp pointer to the @p input_buffers_queue_t object
- * @param[out] bp pointer to the data buffer
- * @param[in] n the maximum amount of data to be transferred, the
- * value 0 is reserved
- * @param[in] timeout the number of ticks before the operation timeouts,
- * the following special values are allowed:
- * - @a TIME_IMMEDIATE immediate timeout.
- * - @a TIME_INFINITE no timeout.
- * .
- * @return The number of bytes effectively transferred.
- * @retval 0 if a timeout occurred.
- *
- * @api
- */
-size_t hidReadReportt(USBHIDDriver *uhdp, uint8_t *bp, size_t n, systime_t timeout) {
-
- return uhdp->vmt->readt(uhdp, bp, n, timeout);
-}
-
-#endif /* HAL_USE_USB_HID == TRUE */
-
-/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/src/hal_usbh.c b/ChibiOS_16.1.5/community/os/hal/src/hal_usbh.c deleted file mode 100644 index 1caa183..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/hal_usbh.c +++ /dev/null @@ -1,1395 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -#if HAL_USE_USBH - -#include "usbh/dev/hub.h" -#include "usbh/internal.h" -#include <string.h> - -#if USBH_DEBUG_ENABLE_TRACE -#define udbgf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define udbg(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define udbgf(f, ...) do {} while(0) -#define udbg(f, ...) do {} while(0) -#endif - -#if USBH_DEBUG_ENABLE_INFO -#define uinfof(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uinfo(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uinfof(f, ...) do {} while(0) -#define uinfo(f, ...) do {} while(0) -#endif - -#if USBH_DEBUG_ENABLE_WARNINGS -#define uwarnf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uwarn(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uwarnf(f, ...) do {} while(0) -#define uwarn(f, ...) do {} while(0) -#endif - -#if USBH_DEBUG_ENABLE_ERRORS -#define uerrf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uerr(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uerrf(f, ...) do {} while(0) -#define uerr(f, ...) do {} while(0) -#endif - -#if STM32_USBH_USE_OTG1 -USBHDriver USBHD1; -#endif -#if STM32_USBH_USE_OTG2 -USBHDriver USBHD2; -#endif - - -static void _classdriver_process_device(usbh_device_t *dev); -static bool _classdriver_load(usbh_device_t *dev, uint8_t class, - uint8_t subclass, uint8_t protocol, uint8_t *descbuff, uint16_t rem); - - -/*===========================================================================*/ -/* Checks. */ -/*===========================================================================*/ - -static inline void _check_dev(usbh_device_t *dev) { - osalDbgCheck(dev); - //TODO: add more checks. -} - -static inline void _check_ep(usbh_ep_t *ep) { - osalDbgCheck(ep != 0); - _check_dev(ep->device); - osalDbgCheck(ep->type <= 3); - //TODO: add more checks. -} - -static inline void _check_urb(usbh_urb_t *urb) { - osalDbgCheck(urb != 0); - _check_ep(urb->ep); - osalDbgCheck((urb->buff != NULL) || (urb->requestedLength == 0)); - //TODO: add more checks. -} - -/*===========================================================================*/ -/* Main driver API. */ -/*===========================================================================*/ - -void usbhObjectInit(USBHDriver *usbh) { - memset(usbh, 0, sizeof(*usbh)); - usbh->status = USBH_STATUS_STOPPED; -#if HAL_USBH_USE_HUB - INIT_LIST_HEAD(&usbh->hubs); - _usbhub_port_object_init(&usbh->rootport, usbh, 0, 1); -#else - _usbhub_port_object_init(&usbh->rootport, usbh, 1); -#endif -} - -void usbhInit(void) { -#if HAL_USBH_USE_HUB - uint8_t i; - for (i = 0; i < HAL_USBHHUB_MAX_INSTANCES; i++) { - usbhhubObjectInit(&USBHHUBD[i]); - } -#endif - usbh_lld_init(); -} - -void usbhStart(USBHDriver *usbh) { - usbDbgInit(usbh); - - osalSysLock(); - osalDbgAssert((usbh->status == USBH_STATUS_STOPPED) || (usbh->status == USBH_STATUS_STARTED), - "invalid state"); - usbh_lld_start(usbh); - usbh->status = USBH_STATUS_STARTED; - osalOsRescheduleS(); - osalSysUnlock(); -} - - -void usbhStop(USBHDriver *usbh) { - //TODO: implement - (void)usbh; -} -void usbhSuspend(USBHDriver *usbh) { - //TODO: implement - (void)usbh; -} -void usbhResume(USBHDriver *usbh) { - //TODO: implement - (void)usbh; -} - -/*===========================================================================*/ -/* Endpoint API. */ -/*===========================================================================*/ - -void usbhEPObjectInit(usbh_ep_t *ep, usbh_device_t *dev, const usbh_endpoint_descriptor_t *desc) { - osalDbgCheck(ep); - _check_dev(dev); - osalDbgCheck(desc); - - memset(ep, 0, sizeof(*ep)); - ep->device = dev; - ep->wMaxPacketSize = desc->wMaxPacketSize; - ep->address = desc->bEndpointAddress & 0x0F; - ep->type = (usbh_eptype_t) (desc->bmAttributes & 0x03); - if (ep->type != USBH_EPTYPE_CTRL) { - ep->in = (desc->bEndpointAddress & 0x80) ? TRUE : FALSE; - } - ep->bInterval = desc->bInterval; - - /* low-level part */ - usbh_lld_ep_object_init(ep); - - ep->status = USBH_EPSTATUS_CLOSED; -} - - -static void _ep0_object_init(usbh_device_t *dev, uint16_t wMaxPacketSize) { - const usbh_endpoint_descriptor_t ep0_descriptor = { - 7, //bLength - 5, //bDescriptorType - 0, //bEndpointAddress - 0, //bmAttributes - wMaxPacketSize, - 0, //bInterval - }; - usbhEPObjectInit(&dev->ctrl, dev, &ep0_descriptor); - usbhEPSetName(&dev->ctrl, "DEV[CTRL]"); -} - - -/*===========================================================================*/ -/* URB API. */ -/*===========================================================================*/ - -void usbhURBObjectInit(usbh_urb_t *urb, usbh_ep_t *ep, usbh_completion_cb callback, - void *user, void *buff, uint32_t len) { - - osalDbgCheck(urb != 0); - _check_ep(ep); - - /* initialize the common part: */ - urb->ep = ep; - urb->callback = callback; - urb->userData = user; - urb->buff = buff; - urb->requestedLength = len; - urb->actualLength = 0; - urb->status = USBH_URBSTATUS_INITIALIZED; - urb->waitingThread = 0; - urb->abortingThread = 0; - - /* initialize the ll part: */ - usbh_lld_urb_object_init(urb); -} - -void usbhURBObjectResetI(usbh_urb_t *urb) { - osalDbgAssert(!usbhURBIsBusy(urb), "invalid status"); - - osalDbgCheck((urb->waitingThread == 0) && (urb->abortingThread == 0)); - - urb->actualLength = 0; - urb->status = USBH_URBSTATUS_INITIALIZED; - - /* reset the ll part: */ - usbh_lld_urb_object_reset(urb); -} - -void usbhURBSubmitI(usbh_urb_t *urb) { - osalDbgCheckClassI(); - _check_urb(urb); - osalDbgAssert(urb->status == USBH_URBSTATUS_INITIALIZED, "invalid status"); - usbh_ep_t *const ep = urb->ep; - if (ep->status == USBH_EPSTATUS_HALTED) { - _usbh_urb_completeI(urb, USBH_URBSTATUS_STALL); - return; - } - if (ep->status != USBH_EPSTATUS_OPEN) { - _usbh_urb_completeI(urb, USBH_URBSTATUS_DISCONNECTED); - return; - } - if (!(usbhDeviceGetPort(ep->device)->status & USBH_PORTSTATUS_ENABLE)) { - _usbh_urb_completeI(urb, USBH_URBSTATUS_DISCONNECTED); - return; - } - urb->status = USBH_URBSTATUS_PENDING; - usbh_lld_urb_submit(urb); -} - -bool _usbh_urb_abortI(usbh_urb_t *urb, usbh_urbstatus_t status) { - osalDbgCheckClassI(); - _check_urb(urb); - - switch (urb->status) { -/* case USBH_URBSTATUS_UNINITIALIZED: - * case USBH_URBSTATUS_INITIALIZED: - * case USBH_URBSTATUS_ERROR: - * case USBH_URBSTATUS_TIMEOUT: - * case USBH_URBSTATUS_CANCELLED: - * case USBH_URBSTATUS_STALL: - * case USBH_URBSTATUS_DISCONNECTED: - * case USBH_URBSTATUS_OK: */ - default: - /* already finished */ - _usbh_urb_completeI(urb, status); - return TRUE; - -// case USBH_URBSTATUS_QUEUED: - case USBH_URBSTATUS_PENDING: - return usbh_lld_urb_abort(urb, status); - } -} - -void _usbh_urb_abort_and_waitS(usbh_urb_t *urb, usbh_urbstatus_t status) { - osalDbgCheckClassS(); - _check_urb(urb); - - if (_usbh_urb_abortI(urb, status) == FALSE) { - uwarn("URB wasn't aborted immediately, suspend"); - osalThreadSuspendS(&urb->abortingThread); - urb->abortingThread = 0; - } else { - osalOsRescheduleS(); - } - uwarn("URB aborted"); -} - -bool usbhURBCancelI(usbh_urb_t *urb) { - return _usbh_urb_abortI(urb, USBH_URBSTATUS_CANCELLED); -} - -void usbhURBCancelAndWaitS(usbh_urb_t *urb) { - _usbh_urb_abort_and_waitS(urb, USBH_URBSTATUS_CANCELLED); -} - -msg_t usbhURBWaitTimeoutS(usbh_urb_t *urb, systime_t timeout) { - msg_t ret; - - osalDbgCheckClassS(); - _check_urb(urb); - - switch (urb->status) { - case USBH_URBSTATUS_INITIALIZED: - case USBH_URBSTATUS_PENDING: -// case USBH_URBSTATUS_QUEUED: - ret = osalThreadSuspendTimeoutS(&urb->waitingThread, timeout); - urb->waitingThread = 0; - break; - - case USBH_URBSTATUS_OK: - ret = MSG_OK; - osalOsRescheduleS(); - break; - -/* case USBH_URBSTATUS_UNINITIALIZED: - * case USBH_URBSTATUS_ERROR: - * case USBH_URBSTATUS_TIMEOUT: - * case USBH_URBSTATUS_CANCELLED: - * case USBH_URBSTATUS_STALL: - * case USBH_URBSTATUS_DISCONNECTED: */ - default: - ret = MSG_RESET; - osalOsRescheduleS(); - break; - } - return ret; -} - -msg_t usbhURBSubmitAndWaitS(usbh_urb_t *urb, systime_t timeout) { - msg_t ret; - - osalDbgCheckClassS(); - _check_urb(urb); - - usbhURBSubmitI(urb); - ret = usbhURBWaitTimeoutS(urb, timeout); - if (ret == MSG_TIMEOUT) - _usbh_urb_abort_and_waitS(urb, USBH_URBSTATUS_TIMEOUT); - - return ret; -} - -static inline msg_t _wakeup_message(usbh_urbstatus_t status) { - if (status == USBH_URBSTATUS_OK) return MSG_OK; - if (status == USBH_URBSTATUS_TIMEOUT) return MSG_TIMEOUT; - return MSG_RESET; -} - -void _usbh_urb_completeI(usbh_urb_t *urb, usbh_urbstatus_t status) { - osalDbgCheckClassI(); - _check_urb(urb); - urb->status = status; - osalThreadResumeI(&urb->waitingThread, _wakeup_message(status)); - osalThreadResumeI(&urb->abortingThread, MSG_RESET); - if (urb->callback) - urb->callback(urb); -} - -/*===========================================================================*/ -/* Synchronous API. */ -/*===========================================================================*/ - -usbh_urbstatus_t usbhBulkTransfer(usbh_ep_t *ep, - void *data, - uint32_t len, - uint32_t *actual_len, - systime_t timeout) { - - osalDbgCheck(ep != NULL); - osalDbgCheck((data != NULL) || (len == 0)); - osalDbgAssert(ep->type == USBH_EPTYPE_BULK, "wrong ep"); - - usbh_urb_t urb; - usbhURBObjectInit(&urb, ep, 0, 0, data, len); - - osalSysLock(); - usbhURBSubmitAndWaitS(&urb, timeout); - osalSysUnlock(); - - if (actual_len != NULL) - *actual_len = urb.actualLength; - - return urb.status; -} - -usbh_urbstatus_t usbhControlRequestExtended(usbh_device_t *dev, - const usbh_control_request_t *req, - uint8_t *buff, - uint32_t *actual_len, - systime_t timeout) { - - _check_dev(dev); - osalDbgCheck(req != NULL); - - usbh_urb_t urb; - - usbhURBObjectInit(&urb, &dev->ctrl, 0, 0, buff, req->wLength); - urb.setup_buff = req; - - osalSysLock(); - usbhURBSubmitAndWaitS(&urb, timeout); - osalSysUnlock(); - - if (actual_len != NULL) - *actual_len = urb.actualLength; - - return urb.status; -} - -usbh_urbstatus_t usbhControlRequest(usbh_device_t *dev, - uint8_t bmRequestType, - uint8_t bRequest, - uint16_t wValue, - uint16_t wIndex, - uint16_t wLength, - uint8_t *buff) { - - const USBH_DEFINE_BUFFER(usbh_control_request_t, req) = { - bmRequestType, - bRequest, - wValue, - wIndex, - wLength - }; - return usbhControlRequestExtended(dev, &req, buff, NULL, MS2ST(1000)); -} - -/*===========================================================================*/ -/* Standard request helpers. */ -/*===========================================================================*/ - -#define USBH_GET_DESCRIPTOR(type, value, index) \ - USBH_STANDARDIN(type, \ - USBH_REQ_GET_DESCRIPTOR, \ - value, \ - index) \ - -#define USBH_GETDEVICEDESCRIPTOR \ - USBH_GET_DESCRIPTOR(USBH_REQTYPE_DEVICE, (USBH_DT_DEVICE << 8) | 0, 0) - -#define USBH_GETCONFIGURATIONDESCRIPTOR(index) \ - USBH_GET_DESCRIPTOR(USBH_REQTYPE_DEVICE, (USBH_DT_CONFIG << 8) | index, 0) - -#define USBH_GETSTRINGDESCRIPTOR(index, langID) \ - USBH_GET_DESCRIPTOR(USBH_REQTYPE_DEVICE, (USBH_DT_STRING << 8) | index, langID) - -bool usbhStdReqGetDeviceDescriptor(usbh_device_t *dev, - uint16_t wLength, - uint8_t *buf) { - usbh_device_descriptor_t *desc; - usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_GETDEVICEDESCRIPTOR, wLength, buf); - desc = (usbh_device_descriptor_t *)buf; - if ((ret != USBH_URBSTATUS_OK) - || (desc->bLength != USBH_DT_DEVICE_SIZE) - || (desc->bDescriptorType != USBH_DT_DEVICE)) { - return HAL_FAILED; - } - return HAL_SUCCESS; -} - -bool usbhStdReqGetConfigurationDescriptor(usbh_device_t *dev, - uint8_t index, - uint16_t wLength, - uint8_t *buf) { - usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_GETCONFIGURATIONDESCRIPTOR(index), wLength, buf); - usbh_config_descriptor_t *const desc = (usbh_config_descriptor_t *)buf; - if ((ret != USBH_URBSTATUS_OK) - || (desc->bLength < USBH_DT_CONFIG_SIZE) - || (desc->bDescriptorType != USBH_DT_CONFIG)) { - return HAL_FAILED; - } - return HAL_SUCCESS; -} - -bool usbhStdReqGetStringDescriptor(usbh_device_t *dev, - uint8_t index, - uint16_t langID, - uint16_t wLength, - uint8_t *buf) { - - osalDbgAssert(wLength >= USBH_DT_STRING_SIZE, "wrong size"); - usbh_string_descriptor_t *desc = (usbh_string_descriptor_t *)buf; - usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_GETSTRINGDESCRIPTOR(index, langID), wLength, buf); - if ((ret != USBH_URBSTATUS_OK) - || (desc->bLength < USBH_DT_STRING_SIZE) - || (desc->bDescriptorType != USBH_DT_STRING)) { - return HAL_FAILED; - } - return HAL_SUCCESS; -} - - - -#define USBH_SET_INTERFACE(interface, alt) \ - USBH_STANDARDOUT(USBH_REQTYPE_INTERFACE, \ - USBH_REQ_SET_INTERFACE, \ - alt, \ - interface) \ - -#define USBH_GET_INTERFACE(interface) \ - USBH_STANDARDIN(USBH_REQTYPE_INTERFACE, \ - USBH_REQ_GET_INTERFACE, \ - 0, \ - interface) \ - -bool usbhStdReqSetInterface(usbh_device_t *dev, - uint8_t bInterfaceNumber, - uint8_t bAlternateSetting) { - - usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_SET_INTERFACE(bInterfaceNumber, bAlternateSetting), 0, NULL); - if (ret != USBH_URBSTATUS_OK) - return HAL_FAILED; - - return HAL_SUCCESS; -} - -bool usbhStdReqGetInterface(usbh_device_t *dev, - uint8_t bInterfaceNumber, - uint8_t *bAlternateSetting) { - - USBH_DEFINE_BUFFER(uint8_t, alt); - - usbh_urbstatus_t ret = usbhControlRequest(dev, USBH_GET_INTERFACE(bInterfaceNumber), 1, &alt); - if (ret != USBH_URBSTATUS_OK) - return HAL_FAILED; - - *bAlternateSetting = alt; - return HAL_SUCCESS; -} - - -/*===========================================================================*/ -/* Device-related functions. */ -/*===========================================================================*/ - -static uint8_t _find_address(USBHDriver *host) { - uint8_t addr, i, j; - for (i = 0; i < sizeof_array(host->address_bitmap); i++) { - addr = host->address_bitmap[i]; - for (j = 0; j < 8; j++) { - if ((addr & (1 << j)) == 0) { - //found: - addr = i * 8 + j + 1; - host->address_bitmap[i] |= (1 << j); - return addr; - } - } - } - return 0; -} - -static void _free_address(USBHDriver *host, uint8_t addr) { - uinfof("Free address %d", addr); - host->address_bitmap[addr / 8] &= ~(1 << ((addr - 1) & 7)); -} - -static void _device_initialize(usbh_device_t *dev, usbh_devspeed_t speed) { - dev->address = 0; - dev->speed = speed; - dev->status = USBH_DEVSTATUS_DEFAULT; - dev->langID0 = 0; - dev->keepFullCfgDesc = 0; - _ep0_object_init(dev, 64); -} - -static bool _device_setaddress(usbh_device_t *dev, uint8_t address) { - usbh_urbstatus_t ret = usbhControlRequest(dev, - USBH_STANDARDOUT(USBH_REQTYPE_DEVICE, USBH_REQ_SET_ADDRESS, address, 0), - 0, - 0); - if (ret != USBH_URBSTATUS_OK) - return HAL_FAILED; - - dev->address = address; - return HAL_SUCCESS; -} - -static inline bool _device_read_basic_cfgdesc(usbh_device_t *dev, uint8_t bConfiguration) { - /* get configuration descriptor */ - return usbhStdReqGetConfigurationDescriptor(dev, bConfiguration, - sizeof(dev->basicConfigDesc), (uint8_t *)&dev->basicConfigDesc); -} - -static void _device_read_full_cfgdesc(usbh_device_t *dev, uint8_t bConfiguration) { - _check_dev(dev); - - uint8_t i; - - if (dev->fullConfigurationDescriptor != NULL) { - chHeapFree(dev->fullConfigurationDescriptor); - } - - dev->fullConfigurationDescriptor = - (uint8_t *)chHeapAlloc(0, dev->basicConfigDesc.wTotalLength); - - if (!dev->fullConfigurationDescriptor) - return; - - for (i = 0; i < 3; i++) { - if (usbhStdReqGetConfigurationDescriptor(dev, bConfiguration, - dev->basicConfigDesc.wTotalLength, - dev->fullConfigurationDescriptor) == HAL_SUCCESS) { - return; - } - osalThreadSleepMilliseconds(200); - } - - /* error */ - chHeapFree(dev->fullConfigurationDescriptor); - dev->fullConfigurationDescriptor = NULL; -} - -static void _device_free_full_cfgdesc(usbh_device_t *dev) { - osalDbgCheck(dev); - if (dev->fullConfigurationDescriptor != NULL) { - chHeapFree(dev->fullConfigurationDescriptor); - dev->fullConfigurationDescriptor = NULL; - } -} - - -#define USBH_SET_CONFIGURATION(type, value, index) \ - USBH_STANDARDOUT(type, \ - USBH_REQ_SET_CONFIGURATION, \ - value, \ - index) \ - -#define USBH_SETDEVICECONFIGURATION(index) \ - USBH_SET_CONFIGURATION(USBH_REQTYPE_DEVICE, index, 0) - - -static bool _device_set_configuration(usbh_device_t *dev, uint8_t configuration) { - usbh_urbstatus_t ret = usbhControlRequest(dev, - USBH_SETDEVICECONFIGURATION(configuration), - 0, - 0); - if (ret != USBH_URBSTATUS_OK) - return HAL_FAILED; - return HAL_SUCCESS; -} - -static bool _device_configure(usbh_device_t *dev, uint8_t bConfiguration) { - uint8_t i; - - uinfof("Reading basic configuration descriptor %d", bConfiguration); - for (i = 0; i < 3; i++) { - if (!_device_read_basic_cfgdesc(dev, bConfiguration)) - break; - } - - if (i == 3) { - uerrf("Could not read basic configuration descriptor %d; " - "won't configure device", bConfiguration); - return HAL_FAILED; - } - - uinfof("Selecting configuration %d", bConfiguration); - for (i = 0; i < 3; i++) { - if (!_device_set_configuration(dev, dev->basicConfigDesc.bConfigurationValue)) { - /* TODO: check if correctly configured using GET_CONFIGURATION */ - dev->status = USBH_DEVSTATUS_CONFIGURED; - dev->bConfiguration = bConfiguration; - - uinfo("Device configured."); - return HAL_SUCCESS; - } - } - - return HAL_FAILED; -} - -static bool _device_enumerate(usbh_device_t *dev) { - - uinfo("Enumerate."); - uinfo("Get first 8 bytes of device descriptor"); - - /* get first 8 bytes of device descriptor */ - if (usbhStdReqGetDeviceDescriptor(dev, 8, (uint8_t *)&dev->devDesc)) { - uerr("Error"); - return HAL_FAILED; - } - - uinfof("Configure bMaxPacketSize0 = %d", dev->devDesc.bMaxPacketSize0); - /* configure EP0 wMaxPacketSize */ - usbhEPClose(&dev->ctrl); - _ep0_object_init(dev, dev->devDesc.bMaxPacketSize0); - usbhEPOpen(&dev->ctrl); - - uint8_t addr = _find_address(dev->host); - if (addr == 0) { - uerr("No free addresses found"); - return HAL_FAILED; - } - - /* set device address */ - uinfof("Set device address: %d", addr); - if (_device_setaddress(dev, addr)) { - uerr("Error"); - _free_address(dev->host, addr); - return HAL_FAILED; - } - - /* update EP because of the address change */ - usbhEPClose(&dev->ctrl); - _ep0_object_init(dev, dev->devDesc.bMaxPacketSize0); - usbhEPOpen(&dev->ctrl); - - uinfof("Wait stabilization..."); - osalThreadSleepMilliseconds(HAL_USBH_DEVICE_ADDRESS_STABILIZATION); - - /* address is set */ - dev->status = USBH_DEVSTATUS_ADDRESS; - - uinfof("Get full device desc"); - /* get full device descriptor */ - if (usbhStdReqGetDeviceDescriptor(dev, sizeof(dev->devDesc), - (uint8_t *)&dev->devDesc)) { - uerr("Error"); - _device_setaddress(dev, 0); - _free_address(dev->host, addr); - return HAL_FAILED; - } - - uinfof("Enumeration finished."); - return HAL_SUCCESS; -} - -#if USBH_DEBUG_ENABLE && USBH_DEBUG_ENABLE_INFO -void usbhDevicePrintInfo(usbh_device_t *dev) { - USBH_DEFINE_BUFFER(char, str[64]); - usbh_device_descriptor_t *const desc = &dev->devDesc; - - uinfo("----- Device info -----"); - uinfo("Device descriptor:"); - uinfof("\tUSBSpec=%04x, #configurations=%d, langID0=%04x", - desc->bcdUSB, - desc->bNumConfigurations, - dev->langID0); - - uinfof("\tClass=%02x, Subclass=%02x, Protocol=%02x", - desc->bDeviceClass, - desc->bDeviceSubClass, - desc->bDeviceProtocol); - - uinfof("\tVID=%04x, PID=%04x, Release=%04x", - desc->idVendor, - desc->idProduct, - desc->bcdDevice); - - if (dev->langID0) { - usbhDeviceReadString(dev, str, sizeof(str), desc->iManufacturer, dev->langID0); - uinfof("\tManufacturer: %s", str); - usbhDeviceReadString(dev, str, sizeof(str), desc->iProduct, dev->langID0); - uinfof("\tProduct: %s", str); - usbhDeviceReadString(dev, str, sizeof(str), desc->iSerialNumber, dev->langID0); - uinfof("\tSerial Number: %s", str); - } - - if (dev->status == USBH_DEVSTATUS_CONFIGURED) { - uinfo("Configuration descriptor (partial):"); - usbh_config_descriptor_t *const cfg = &dev->basicConfigDesc; - uinfof("\tbConfigurationValue=%d, Length=%d, #interfaces=%d", - cfg->bConfigurationValue, - cfg->wTotalLength, - cfg->bNumInterfaces); - - uinfof("\tCurrent=%dmA", cfg->bMaxPower * 2); - uinfof("\tSelfPowered=%d, RemoteWakeup=%d", - cfg->bmAttributes & 0x40 ? 1 : 0, - cfg->bmAttributes & 0x20 ? 1 : 0); - if (dev->langID0) { - usbhDeviceReadString(dev, str, sizeof(str), cfg->iConfiguration, dev->langID0); - uinfof("\tName: %s", str); - } - } - - uinfo("----- End Device info -----"); - -} - -void usbhDevicePrintConfiguration(const uint8_t *descriptor, uint16_t rem) { - generic_iterator_t iep, icfg, ics; - if_iterator_t iif; - - uinfo("----- Configuration info -----"); - uinfo("Configuration descriptor:"); - cfg_iter_init(&icfg, descriptor, rem); - const usbh_config_descriptor_t *const cfgdesc = cfg_get(&icfg); - uinfof("Configuration %d, #IFs=%d", cfgdesc->bConfigurationValue, cfgdesc->bNumInterfaces); - - for (if_iter_init(&iif, &icfg); iif.valid; if_iter_next(&iif)) { - const usbh_interface_descriptor_t *const ifdesc = if_get(&iif); - - uinfof(" Interface %d, alt=%d, #EPs=%d, " - "Class=%02x, Subclass=%02x, Protocol=%02x", - ifdesc->bInterfaceNumber, ifdesc->bAlternateSetting, ifdesc->bNumEndpoints, - ifdesc->bInterfaceClass, ifdesc->bInterfaceSubClass, ifdesc->bInterfaceProtocol); - - for (cs_iter_init(&ics, (generic_iterator_t *)&iif); ics.valid; cs_iter_next(&ics)) { - uinfof(" Class-Specific descriptor, Length=%d, Type=%02x", - ics.curr[0], ics.curr[1]); - } - - for (ep_iter_init(&iep, &iif); iep.valid; ep_iter_next(&iep)) { - const usbh_endpoint_descriptor_t *const epdesc = ep_get(&iep); - - uinfof(" Endpoint descriptor, Address=%02x, Type=%d, MaxPacket=%d, Interval=%d", - epdesc->bEndpointAddress, - epdesc->bmAttributes & 3, - epdesc->wMaxPacketSize, - epdesc->bInterval); - - for (cs_iter_init(&ics, &iep); ics.valid; cs_iter_next(&ics)) { - uinfof(" Class-Specific descriptor, Length=%d, Type=%02x", - ics.curr[0], ics.curr[1]); - } - } - } - uinfo("----- End Configuration info -----"); -} -#endif - -bool usbhDeviceReadString(usbh_device_t *dev, char *dest, uint8_t size, - uint8_t index, uint16_t langID) { - - usbh_string_descriptor_t *const desc = (usbh_string_descriptor_t *)dest; - osalDbgAssert(size >= 2, "wrong size"); - - *dest = 0; - if (index == 0) - return HAL_SUCCESS; - if (usbhStdReqGetStringDescriptor(dev, index, langID, size, (uint8_t *)dest)) - return HAL_FAILED; - if (desc->bLength & 1) - return HAL_FAILED; - if (desc->bLength <= 2) - return HAL_SUCCESS; - - uint8_t nchars = desc->bLength / 2; /* including the trailing 0 */ - if (size < nchars) - nchars = size; - - char *src = (char *)&desc->wData[0]; - while (--nchars) { - *dest++ = *src; - src += 2; - } - *dest = 0; - return HAL_SUCCESS; -} - - - - -/*===========================================================================*/ -/* Port processing functions. */ -/*===========================================================================*/ - -static void _port_connected(usbh_port_t *port); - -static void _port_reset(usbh_port_t *port) { - usbhhubControlRequest(port->device.host, -#if HAL_USBH_USE_HUB - port->hub, -#endif - USBH_REQTYPE_OUT | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER, - USBH_REQ_SET_FEATURE, - USBH_PORT_FEAT_RESET, - port->number, - 0, - 0); -} - -static void _port_update_status(usbh_port_t *port) { - uint32_t stat; - if (usbhhubControlRequest(port->device.host, -#if HAL_USBH_USE_HUB - port->hub, -#endif - USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_OTHER, - USBH_REQ_GET_STATUS, - 0, - port->number, - 4, - (uint8_t *)&stat) != USBH_URBSTATUS_OK) { - return; - } - port->status = stat & 0xffff; - port->c_status |= stat >> 16; -} - -static void _port_process_status_change(usbh_port_t *port) { - - _port_update_status(port); - - if (port->c_status & USBH_PORTSTATUS_C_CONNECTION) { - /* port connected status changed */ - port->c_status &= ~USBH_PORTSTATUS_C_CONNECTION; - usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_CONNECTION); - if ((port->status & (USBH_PORTSTATUS_CONNECTION | USBH_PORTSTATUS_ENABLE)) - == USBH_PORTSTATUS_CONNECTION) { - if (port->device.status != USBH_DEVSTATUS_DISCONNECTED) { - _usbh_port_disconnected(port); - } - - /* connected, disabled */ - _port_connected(port); - } else { - /* disconnected */ - _usbh_port_disconnected(port); - } - } - - if (port->c_status & USBH_PORTSTATUS_C_RESET) { - port->c_status &= ~USBH_PORTSTATUS_C_RESET; - usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_RESET); - } - - if (port->c_status & USBH_PORTSTATUS_C_ENABLE) { - port->c_status &= ~USBH_PORTSTATUS_C_ENABLE; - usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_ENABLE); - } - - if (port->c_status & USBH_PORTSTATUS_C_OVERCURRENT) { - port->c_status &= ~USBH_PORTSTATUS_C_OVERCURRENT; - usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_OVERCURRENT); - } - - if (port->c_status & USBH_PORTSTATUS_C_SUSPEND) { - port->c_status &= ~USBH_PORTSTATUS_C_SUSPEND; - usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_SUSPEND); - } - -} - - -static void _port_connected(usbh_port_t *port) { - /* connected */ - - systime_t start; - uint8_t i; - uint8_t retries; - usbh_devspeed_t speed; - USBH_DEFINE_BUFFER(usbh_string_descriptor_t, strdesc); - - uinfof("Port %d connected, wait debounce...", port->number); - - port->device.status = USBH_DEVSTATUS_ATTACHED; - - /* wait for attach de-bounce */ - osalThreadSleepMilliseconds(HAL_USBH_PORT_DEBOUNCE_TIME); - - /* check disconnection */ - _port_update_status(port); - if (port->c_status & USBH_PORTSTATUS_C_CONNECTION) { - /* connection state changed; abort */ - goto abort; - } - - port->device.status = USBH_DEVSTATUS_CONNECTED; - retries = 3; - -reset: - for (i = 0; i < 3; i++) { - uinfo("Try reset..."); - port->c_status &= ~(USBH_PORTSTATUS_C_RESET | USBH_PORTSTATUS_C_ENABLE); - _port_reset(port); - osalThreadSleepMilliseconds(20); /* give it some time to reset (min. 10ms) */ - start = osalOsGetSystemTimeX(); - while (TRUE) { - _port_update_status(port); - - /* check for disconnection */ - if (port->c_status & USBH_PORTSTATUS_C_CONNECTION) - goto abort; - - /* check for reset completion */ - if (port->c_status & USBH_PORTSTATUS_C_RESET) { - port->c_status &= ~USBH_PORTSTATUS_C_RESET; - usbhhubClearFeaturePort(port, USBH_PORT_FEAT_C_RESET); - - if ((port->status & (USBH_PORTSTATUS_ENABLE | USBH_PORTSTATUS_CONNECTION)) - == (USBH_PORTSTATUS_ENABLE | USBH_PORTSTATUS_CONNECTION)) { - goto reset_success; - } - } - - /* check for timeout */ - if (osalOsGetSystemTimeX() - start > HAL_USBH_PORT_RESET_TIMEOUT) break; - } - } - - /* reset procedure failed; abort */ - goto abort; - -reset_success: - - uinfo("Reset OK, recovery..."); - - /* reset recovery */ - osalThreadSleepMilliseconds(100); - - /* initialize object */ - if (port->status & USBH_PORTSTATUS_LOW_SPEED) { - speed = USBH_DEVSPEED_LOW; - } else if (port->status & USBH_PORTSTATUS_HIGH_SPEED) { - speed = USBH_DEVSPEED_HIGH; - } else { - speed = USBH_DEVSPEED_FULL; - } - _device_initialize(&port->device, speed); - usbhEPOpen(&port->device.ctrl); - - /* device with default address (0), try enumeration */ - if (_device_enumerate(&port->device)) { - /* enumeration failed */ - usbhEPClose(&port->device.ctrl); - - if (!--retries) - goto abort; - - /* retry reset & enumeration */ - goto reset; - } - - /* load the default language ID */ - uinfo("Loading langID0..."); - if (!usbhStdReqGetStringDescriptor(&port->device, 0, 0, - USBH_DT_STRING_SIZE, (uint8_t *)&strdesc) - && (strdesc.bLength >= 4) - && !usbhStdReqGetStringDescriptor(&port->device, 0, 0, - 4, (uint8_t *)&strdesc)) { - - port->device.langID0 = strdesc.wData[0]; - uinfof("langID0=%04x", port->device.langID0); - } - - /* check if the device has only one configuration */ - if (port->device.devDesc.bNumConfigurations == 1) { - uinfo("Device has only one configuration"); - _device_configure(&port->device, 0); - } - - _classdriver_process_device(&port->device); - return; - -abort: - uerr("Abort"); - port->device.status = USBH_DEVSTATUS_DISCONNECTED; -} - -void _usbh_port_disconnected(usbh_port_t *port) { - if (port->device.status == USBH_DEVSTATUS_DISCONNECTED) - return; - - uinfo("Port disconnected"); - - /* unload drivers */ - while (port->device.drivers) { - usbh_baseclassdriver_t *drv = port->device.drivers; - - /* unload */ - uinfof("Unload driver %s", drv->info->name); - drv->info->vmt->unload(drv); - - /* unlink */ - drv->dev = 0; - port->device.drivers = drv->next; - } - - /* close control endpoint */ - osalSysLock(); - usbhEPCloseS(&port->device.ctrl); - osalSysUnlock(); - - /* free address */ - if (port->device.address) - _free_address(port->device.host, port->device.address); - - _device_free_full_cfgdesc(&port->device); - - port->device.status = USBH_DEVSTATUS_DISCONNECTED; -} - - - -/*===========================================================================*/ -/* Hub processing functions. */ -/*===========================================================================*/ - -#if HAL_USBH_USE_HUB -static void _hub_update_status(USBHDriver *host, USBHHubDriver *hub) { - uint32_t stat; - if (usbhhubControlRequest(host, - hub, - USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE, - USBH_REQ_GET_STATUS, - 0, - 0, - 4, - (uint8_t *)&stat) != USBH_URBSTATUS_OK) { - return; - } - if (hub) { - hub->status = stat & 0xffff; - hub->c_status |= stat >> 16; - } -} - -static void _hub_process_status_change(USBHDriver *host, USBHHubDriver *hub) { - uinfo("Hub status change. GET_STATUS."); - _hub_update_status(host, hub); - - if (hub->c_status & USBH_HUBSTATUS_C_HUB_LOCAL_POWER) { - hub->c_status &= ~USBH_HUBSTATUS_C_HUB_LOCAL_POWER; - uinfo("Clear USBH_HUB_FEAT_C_HUB_LOCAL_POWER"); - usbhhubClearFeatureHub(host, hub, USBH_HUB_FEAT_C_HUB_LOCAL_POWER); - } - - if (hub->c_status & USBH_HUBSTATUS_C_HUB_OVER_CURRENT) { - hub->c_status &= ~USBH_HUBSTATUS_C_HUB_OVER_CURRENT; - uinfo("Clear USBH_HUB_FEAT_C_HUB_OVER_CURRENT"); - usbhhubClearFeatureHub(host, hub, USBH_HUB_FEAT_C_HUB_OVER_CURRENT); - } -} - -static uint32_t _hub_get_status_change_bitmap(USBHDriver *host, USBHHubDriver *hub) { - if (hub != NULL) { - osalSysLock(); - uint32_t ret = hub->statuschange; - hub->statuschange = 0; - osalOsRescheduleS(); - osalSysUnlock(); - return ret; - } - return usbh_lld_roothub_get_statuschange_bitmap(host); -} - -#else -//TODO: replace the functions above -#endif - -#if HAL_USBH_USE_HUB -static void _hub_process(USBHDriver *host, USBHHubDriver *hub) { - uint32_t bitmap = _hub_get_status_change_bitmap(host, hub); - if (!bitmap) - return; - - if (bitmap & 1) { - _hub_process_status_change(host, hub); - bitmap &= ~1; - } - - usbh_port_t *port = (hub == NULL) ? &host->rootport : hub->ports; - uint8_t i; - for (i = 1; i < 32; i++) { - if (!bitmap || !port) - break; - if (bitmap & (1 << i)) { - bitmap &= ~(1 << i); - _port_process_status_change(port); - } - port = port->next; - } - -} -#else -static void _hub_process(USBHDriver *host) { - uint32_t bitmap = usbh_lld_roothub_get_statuschange_bitmap(host); - -#if 0 //TODO: complete _hub_process_status_change for root hub - if (bitmap & 1) { - _hub_process_status_change(host, hub); - bitmap &= ~1; - } -#endif - - if (!bitmap) - return; - - _port_process_status_change(&host->rootport); -} -#endif - -/*===========================================================================*/ -/* Main processing loop (enumeration, loading/unloading drivers, etc). */ -/*===========================================================================*/ -void usbhMainLoop(USBHDriver *usbh) { - - if (usbh->status == USBH_STATUS_STOPPED) - return; - -#if HAL_USBH_USE_HUB - /* process root hub */ - _hub_process(usbh, NULL); - - /* process connected hubs */ - USBHHubDriver *hub; - list_for_each_entry(hub, USBHHubDriver, &usbh->hubs, node) { - _hub_process(usbh, hub); - } -#else - /* process root hub */ - _hub_process(usbh); -#endif -} - - -/*===========================================================================*/ -/* IAD class driver. */ -/*===========================================================================*/ -#if HAL_USBH_USE_IAD -static usbh_baseclassdriver_t *iad_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem); -static void iad_unload(usbh_baseclassdriver_t *drv); -static const usbh_classdriver_vmt_t usbhiadClassDriverVMT = { - iad_load, - iad_unload -}; -static const usbh_classdriverinfo_t usbhiadClassDriverInfo = { - 0xef, 0x02, 0x01, "IAD", &usbhiadClassDriverVMT -}; - -static usbh_baseclassdriver_t *iad_load(usbh_device_t *dev, - const uint8_t *descriptor, uint16_t rem) { - (void)rem; - - if (descriptor[1] != USBH_DT_DEVICE) - return 0; - - uinfo("Load a driver for each IF collection."); - - generic_iterator_t icfg; - if_iterator_t iif; - const usbh_ia_descriptor_t *last_iad = 0; - - cfg_iter_init(&icfg, dev->fullConfigurationDescriptor, - dev->basicConfigDesc.wTotalLength); - if (!icfg.valid) { - uerr("Invalid configuration descriptor."); - return 0; - } - - for (if_iter_init(&iif, &icfg); iif.valid; if_iter_next(&iif)) { - if (iif.iad && (iif.iad != last_iad)) { - last_iad = iif.iad; - if (_classdriver_load(dev, iif.iad->bFunctionClass, - iif.iad->bFunctionSubClass, - iif.iad->bFunctionProtocol, - (uint8_t *)iif.iad, - (uint8_t *)iif.curr - (uint8_t *)iif.iad + iif.rem) != HAL_SUCCESS) { - uwarnf("No drivers found for IF collection #%d:%d", - iif.iad->bFirstInterface, - iif.iad->bFirstInterface + iif.iad->bInterfaceCount - 1); - } - } - } - - return 0; -} - -static void iad_unload(usbh_baseclassdriver_t *drv) { - (void)drv; -} -#endif - - -/*===========================================================================*/ -/* Class driver loader. */ -/*===========================================================================*/ - -static const usbh_classdriverinfo_t *usbh_classdrivers_lookup[] = { -#if HAL_USBH_USE_FTDI - &usbhftdiClassDriverInfo, -#endif -#if HAL_USBH_USE_IAD - &usbhiadClassDriverInfo, -#endif -#if HAL_USBH_USE_UVC - &usbhuvcClassDriverInfo, -#endif -#if HAL_USBH_USE_MSD - &usbhmsdClassDriverInfo, -#endif -#if HAL_USBH_USE_HUB - &usbhhubClassDriverInfo -#endif -}; - -static bool _classdriver_load(usbh_device_t *dev, uint8_t class, - uint8_t subclass, uint8_t protocol, uint8_t *descbuff, uint16_t rem) { - uint8_t i; - usbh_baseclassdriver_t *drv = NULL; - for (i = 0; i < sizeof_array(usbh_classdrivers_lookup); i++) { - const usbh_classdriverinfo_t *const info = usbh_classdrivers_lookup[i]; - if (class == 0xff) { - /* vendor specific */ - if (info->class == 0xff) { - uinfof("Try load vendor-specific driver %s", info->name); - drv = info->vmt->load(dev, descbuff, rem); - if (drv != NULL) - goto success; - } - } else if ((info->class < 0) || ((info->class == class) - && ((info->subclass < 0) || ((info->subclass == subclass) - && ((info->protocol < 0) || (info->protocol == protocol)))))) { - uinfof("Try load driver %s", info->name); - drv = info->vmt->load(dev, descbuff, rem); - -#if HAL_USBH_USE_IAD - /* special case: */ - if (info == &usbhiadClassDriverInfo) - return HAL_SUCCESS; -#endif - - if (drv != NULL) - goto success; - } - } - return HAL_FAILED; - -success: - /* Link this driver to the device */ - drv->next = dev->drivers; - dev->drivers = drv; - drv->dev = dev; - return HAL_SUCCESS; -} - -static void _classdriver_process_device(usbh_device_t *dev) { - uinfo("New device found."); - const usbh_device_descriptor_t *const devdesc = &dev->devDesc; - - usbhDevicePrintInfo(dev); - - /* TODO: Support multiple configurations - * - * Windows doesn't support them, so it's unlikely that any commercial USB device - * will have multiple configurations. - */ - if (dev->status != USBH_DEVSTATUS_CONFIGURED) { - uwarn("Multiple configurations not supported, selecting configuration #0"); - if (_device_configure(dev, 0) != HAL_SUCCESS) { - uerr("Couldn't configure device; abort."); - return; - } - } - - _device_read_full_cfgdesc(dev, dev->bConfiguration); - if (dev->fullConfigurationDescriptor == NULL) { - uerr("Couldn't read full configuration descriptor; abort."); - return; - } - - usbhDevicePrintConfiguration(dev->fullConfigurationDescriptor, - dev->basicConfigDesc.wTotalLength); - - if (devdesc->bDeviceClass == 0) { - /* each interface defines its own device class/subclass/protocol */ - uinfo("Load a driver for each IF."); - - generic_iterator_t icfg; - if_iterator_t iif; - uint8_t last_if = 0xff; - - cfg_iter_init(&icfg, dev->fullConfigurationDescriptor, - dev->basicConfigDesc.wTotalLength); - if (!icfg.valid) { - uerr("Invalid configuration descriptor."); - goto exit; - } - - for (if_iter_init(&iif, &icfg); iif.valid; if_iter_next(&iif)) { - const usbh_interface_descriptor_t *const ifdesc = if_get(&iif); - if (ifdesc->bInterfaceNumber != last_if) { - last_if = ifdesc->bInterfaceNumber; - if (_classdriver_load(dev, ifdesc->bInterfaceClass, - ifdesc->bInterfaceSubClass, - ifdesc->bInterfaceProtocol, - (uint8_t *)ifdesc, iif.rem) != HAL_SUCCESS) { - uwarnf("No drivers found for IF #%d", ifdesc->bInterfaceNumber); - } - } - } - - } else { - if (_classdriver_load(dev, devdesc->bDeviceClass, - devdesc->bDeviceSubClass, - devdesc->bDeviceProtocol, - (uint8_t *)devdesc, USBH_DT_DEVICE_SIZE) != HAL_SUCCESS) { - uwarn("No drivers found."); - } - } - -exit: - if (dev->keepFullCfgDesc == 0) { - _device_free_full_cfgdesc(dev); - } -} - - -#endif - diff --git a/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_debug.c b/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_debug.c deleted file mode 100644 index 9f17189..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_debug.c +++ /dev/null @@ -1,536 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -#if HAL_USE_USBH - -#include "ch.h" -#include "usbh/debug.h" -#include <stdarg.h> -#include "chprintf.h" - -#if USBH_DEBUG_ENABLE - -#define MAX_FILLER 11 -#define FLOAT_PRECISION 9 -#define MPRINTF_USE_FLOAT 0 - -static char *long_to_string_with_divisor(char *p, long num, unsigned radix, long divisor) -{ - int i; - char *q; - long l, ll; - - l = num; - if (divisor == 0) { - ll = num; - } else { - ll = divisor; - } - - q = p + MAX_FILLER; - do { - i = (int)(l % radix); - i += '0'; - if (i > '9') { - i += 'A' - '0' - 10; - } - *--q = i; - l /= radix; - } while ((ll /= radix) != 0); - - i = (int)(p + MAX_FILLER - q); - do { - *p++ = *q++; - } while (--i); - - return p; -} - -static char *ltoa(char *p, long num, unsigned radix) { - - return long_to_string_with_divisor(p, num, radix, 0); -} - -#if MPRINTF_USE_FLOAT -static const long _pow10[FLOAT_PRECISION] = {10, 100, 1000, 10000, 100000, 1000000, - 10000000, 100000000, 1000000000}; -static const double m10[FLOAT_PRECISION] = {5.0/100, 5.0/1000, 5.0/10000, 5.0/100000, 5.0/1000000, - 5.0/10000000, 5.0/100000000, 5.0/1000000000, 5.0/10000000000}; - -static char *ftoa(char *p, double num, unsigned long precision, bool dot) { - long l; - char *q; - double r; - - - if (precision == 0) { - l = (long)(num + 0.5); - return long_to_string_with_divisor(p, l, 10, 0); - } else { - if (precision > FLOAT_PRECISION) precision = FLOAT_PRECISION; - r = m10[precision - 1]; - precision = _pow10[precision - 1]; - - l = (long)num; - p = long_to_string_with_divisor(p, l, 10, 0); - if (dot) *p++ = '.'; - l = (long)((num - l + r) * precision); - q = long_to_string_with_divisor(p, l, 10, precision / 10) - 1; - - while (q > p) { - if (*q != '0') { - break; - } - --q; - } - return ++q; - } - - - - -} -#endif - -static inline void _put(char c) { - input_queue_t *iqp = &USBH_DEBUG_USBHD.iq; - - if (chIQIsFullI(iqp)) - return; - - iqp->q_counter++; - *iqp->q_wrptr++ = c; - if (iqp->q_wrptr >= iqp->q_top) - iqp->q_wrptr = iqp->q_buffer; - -} - -int _dbg_printf(const char *fmt, va_list ap) { - char *p, *s, c, filler; - int i, precision, width; - int n = 0; - bool is_long, left_align, sign; - long l; -#if MPRINTF_USE_FLOAT - double f; - char tmpbuf[2*MAX_FILLER + 1]; -#else - char tmpbuf[MAX_FILLER + 1]; -#endif - - for (;;) { - - //agarrar nuevo caracter de formato - c = *fmt++; - - //chequeo eos - if (c == 0) return n; - - //copio los caracteres comunes - if (c != '%') { - _put(c); - n++; - continue; - } - - //encontré un '%' - p = tmpbuf; - s = tmpbuf; - - //left align - left_align = FALSE; - if (*fmt == '-') { - fmt++; - left_align = TRUE; - } - - sign = FALSE; - if (*fmt == '+') { - fmt++; - sign = TRUE; - } - - //filler - filler = ' '; - if (*fmt == '0') { - fmt++; - filler = '0'; - } - - //width - width = 0; - while (TRUE) { - c = *fmt++; - if (c >= '0' && c <= '9') - c -= '0'; - else if (c == '*') - c = va_arg(ap, int); - else - break; - width = width * 10 + c; - } - - //precision - precision = 0; - if (c == '.') { - - if (*fmt == 'n') { - fmt++; - - } - while (TRUE) { - c = *fmt++; - if (c >= '0' && c <= '9') - c -= '0'; - else if (c == '*') - c = va_arg(ap, int); - else - break; - precision = precision * 10 + c; - } - } - - //long modifier - if (c == 'l' || c == 'L') { - is_long = TRUE; - if (*fmt) - c = *fmt++; - } - else - is_long = (c >= 'A') && (c <= 'Z'); - - /* Command decoding.*/ - switch (c) { - //char - case 'c': - filler = ' '; - *p++ = va_arg(ap, int); - break; - - //string - case 's': - filler = ' '; - if ((s = va_arg(ap, char *)) == 0) - s = (char *)"(null)"; - if (precision == 0) - precision = 32767; - - //strlen con lÃmite hasta precision - for (p = s; *p && (--precision >= 0); p++) - ; - break; - - - - case 'D': - case 'd': - case 'I': - case 'i': - if (is_long) - l = va_arg(ap, long); - else - l = va_arg(ap, int); - if (l < 0) { - *p++ = '-'; - l = -l; - sign = TRUE; - } else if (sign) { - *p++ = '+'; - } - p = ltoa(p, l, 10); - break; - -#if MPRINTF_USE_FLOAT - case 'f': - f = va_arg(ap, double); - if (f < 0) { - *p++ = '-'; - f = -f; - sign = TRUE; - } else if (sign) { - *p++ = '+'; - } - if (prec == FALSE) precision = 6; - p = ftoa(p, f, precision, dot); - break; -#endif - - - case 'X': - case 'x': - c = 16; - goto unsigned_common; - case 'U': - case 'u': - c = 10; - goto unsigned_common; - case 'O': - case 'o': - c = 8; - -unsigned_common: - if (is_long) - l = va_arg(ap, unsigned long); - else - l = va_arg(ap, unsigned int); - p = ltoa(p, l, c); - break; - - //copiar - default: - *p++ = c; - break; - } - - //longitud - i = (int)(p - s); - - //calculo cuántos caracteres de filler debo poner - if ((width -= i) < 0) - width = 0; - - if (left_align == FALSE) - width = -width; - - if (width < 0) { - //alineado a la derecha - - //poner el signo adelante - if (sign && filler == '0') { - _put(*s++); - n++; - i--; - } - - //fill a la izquierda - do { - _put(filler); - n++; - } while (++width != 0); - } - - //copiar los caracteres - while (--i >= 0) { - _put(*s++); - n++; - } - - //fill a la derecha - while (width) { - _put(filler); - n++; - width--; - } - } - - //return n; // can raise 'code is unreachable' warning - -} - -static void _print_hdr(void) -{ - uint32_t hfnum = USBH_DEBUG_USBHD.otg->HFNUM; - uint16_t hfir = USBH_DEBUG_USBHD.otg->HFIR; - - _put(0xff); - _put(0xff); - _put(hfir & 0xff); - _put(hfir >> 8); - _put(hfnum & 0xff); - _put((hfnum >> 8) & 0xff); - _put((hfnum >> 16) & 0xff); - _put((hfnum >> 24) & 0xff); -} - -void usbDbgPrintf(const char *fmt, ...) -{ - va_list ap; - va_start(ap, fmt); - syssts_t sts = chSysGetStatusAndLockX(); - _print_hdr(); - _dbg_printf(fmt, ap); - _put(0); - chThdDequeueNextI(&USBH_DEBUG_USBHD.iq.q_waiting, Q_OK); - chSysRestoreStatusX(sts); - va_end(ap); -} - - -void usbDbgPuts(const char *s) -{ - uint32_t buff[2] = { - 0xffff | (USBH_DEBUG_USBHD.otg->HFIR << 16), - USBH_DEBUG_USBHD.otg->HFNUM - }; - uint8_t *p = (uint8_t *)buff; - uint8_t *top = p + 8; - - syssts_t sts = chSysGetStatusAndLockX(); - input_queue_t *iqp = &USBH_DEBUG_USBHD.iq; - int rem = sizeof(USBH_DEBUG_USBHD.dbg_buff) - iqp->q_counter; - while (rem) { - *iqp->q_wrptr++ = *p; - if (iqp->q_wrptr >= iqp->q_top) - iqp->q_wrptr = iqp->q_buffer; - rem--; - if (++p == top) break; - } - while (rem) { - *iqp->q_wrptr++ = *s; - if (iqp->q_wrptr >= iqp->q_top) - iqp->q_wrptr = iqp->q_buffer; - rem--; - if (!*s++) break; - } - iqp->q_counter = sizeof(USBH_DEBUG_USBHD.dbg_buff) - rem; - chThdDequeueNextI(&USBH_DEBUG_USBHD.iq.q_waiting, Q_OK); - chSysRestoreStatusX(sts); -} - -void usbDbgReset(void) { - const char *msg = "\r\n\r\n==== DEBUG OUTPUT RESET ====\r\n"; - - syssts_t sts = chSysGetStatusAndLockX(); - chIQResetI(&USBH_DEBUG_USBHD.iq); - chOQResetI(&USBH_DEBUG_SD.oqueue); - while (*msg) { - *USBH_DEBUG_SD.oqueue.q_wrptr++ = *msg++; - USBH_DEBUG_SD.oqueue.q_counter--; - } - chSysRestoreStatusX(sts); -} - -static int _get(void) { - if (!USBH_DEBUG_USBHD.iq.q_counter) return -1; - USBH_DEBUG_USBHD.iq.q_counter--; - uint8_t b = *USBH_DEBUG_USBHD.iq.q_rdptr++; - if (USBH_DEBUG_USBHD.iq.q_rdptr >= USBH_DEBUG_USBHD.iq.q_top) { - USBH_DEBUG_USBHD.iq.q_rdptr = USBH_DEBUG_USBHD.iq.q_buffer; - } - return b; -} - -void usbDbgSystemHalted(void) { - while (true) { - if (!((bool)((USBH_DEBUG_SD.oqueue.q_wrptr == USBH_DEBUG_SD.oqueue.q_rdptr) && (USBH_DEBUG_SD.oqueue.q_counter != 0U)))) - break; - USBH_DEBUG_SD.oqueue.q_counter++; - while (!(USART1->SR & USART_SR_TXE)); - USART1->DR = *USBH_DEBUG_SD.oqueue.q_rdptr++; - if (USBH_DEBUG_SD.oqueue.q_rdptr >= USBH_DEBUG_SD.oqueue.q_top) { - USBH_DEBUG_SD.oqueue.q_rdptr = USBH_DEBUG_SD.oqueue.q_buffer; - } - } - - int c; - int state = 0; - for (;;) { - c = _get(); if (c < 0) break; - - if (state == 0) { - if (c == 0xff) state = 1; - } else if (state == 1) { - if (c == 0xff) state = 2; - else (state = 0); - } else { - c = _get(); if (c < 0) return; - c = _get(); if (c < 0) return; - c = _get(); if (c < 0) return; - c = _get(); if (c < 0) return; - c = _get(); if (c < 0) return; - - while (true) { - c = _get(); if (c < 0) return; - if (!c) { - while (!(USART1->SR & USART_SR_TXE)); - USART1->DR = '\r'; - while (!(USART1->SR & USART_SR_TXE)); - USART1->DR = '\n'; - state = 0; - break; - } - while (!(USART1->SR & USART_SR_TXE)); - USART1->DR = c; - } - } - } -} - -static void usb_debug_thread(void *p) { - USBHDriver *host = (USBHDriver *)p; - uint8_t state = 0; - - chRegSetThreadName("USBH_DBG"); - while (true) { - msg_t c = chIQGet(&host->iq); - if (c < 0) goto reset; - - if (state == 0) { - if (c == 0xff) state = 1; - } else if (state == 1) { - if (c == 0xff) state = 2; - else (state = 0); - } else { - uint16_t hfir; - uint32_t hfnum; - - hfir = c; - c = chIQGet(&host->iq); if (c < 0) goto reset; - hfir |= c << 8; - - c = chIQGet(&host->iq); if (c < 0) goto reset; - hfnum = c; - c = chIQGet(&host->iq); if (c < 0) goto reset; - hfnum |= c << 8; - c = chIQGet(&host->iq); if (c < 0) goto reset; - hfnum |= c << 16; - c = chIQGet(&host->iq); if (c < 0) goto reset; - hfnum |= c << 24; - - uint32_t f = hfnum & 0xffff; - uint32_t p = 1000 - ((hfnum >> 16) / (hfir / 1000)); - chprintf((BaseSequentialStream *)&USBH_DEBUG_SD, "%05d.%03d ", f, p); - - while (true) { - c = chIQGet(&host->iq); if (c < 0) goto reset; - if (!c) { - sdPut(&USBH_DEBUG_SD, '\r'); - sdPut(&USBH_DEBUG_SD, '\n'); - state = 0; - break; - } - sdPut(&USBH_DEBUG_SD, (uint8_t)c); - } - } - - continue; -reset: - state = 0; - } -} - -void usbDbgInit(USBHDriver *host) { - if (host != &USBH_DEBUG_USBHD) - return; - chIQObjectInit(&USBH_DEBUG_USBHD.iq, USBH_DEBUG_USBHD.dbg_buff, sizeof(USBH_DEBUG_USBHD.dbg_buff), 0, 0); - chThdCreateStatic(USBH_DEBUG_USBHD.waDebug, sizeof(USBH_DEBUG_USBHD.waDebug), NORMALPRIO, usb_debug_thread, &USBH_DEBUG_USBHD); -} -#endif - -#endif diff --git a/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_desciter.c b/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_desciter.c deleted file mode 100644 index 63137d4..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_desciter.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -#if HAL_USE_USBH - -#include "usbh/defs.h" -#include "usbh/desciter.h" - -void cfg_iter_init(generic_iterator_t *icfg, const uint8_t *buff, uint16_t rem) { - icfg->valid = 0; - - if ((buff[0] < 2) || (rem < 2) || (rem < buff[0]) - || (buff[0] < USBH_DT_CONFIG_SIZE) - || (buff[1] != USBH_DT_CONFIG)) - return; - - if (rem > ((usbh_config_descriptor_t *)buff)->wTotalLength) { - rem = ((usbh_config_descriptor_t *)buff)->wTotalLength; - } - - icfg->valid = 1; - icfg->rem = rem; - icfg->curr = buff; -} - -void if_iter_next(if_iterator_t *iif) { - const uint8_t *curr = iif->curr; - uint16_t rem = iif->rem; - - iif->valid = 0; - - if ((curr[0] < 2) || (rem < 2) || (rem < curr[0])) - return; - - for (;;) { - rem -= curr[0]; - curr += curr[0]; - - if ((curr[0] < 2) || (rem < 2) || (rem < curr[0])) - return; - - if (curr[1] == USBH_DT_INTERFACE_ASSOCIATION) { - if (curr[0] < USBH_DT_INTERFACE_ASSOCIATION_SIZE) - return; - - iif->iad = (usbh_ia_descriptor_t *)curr; - - } else if (curr[1] == USBH_DT_INTERFACE) { - if (curr[0] < USBH_DT_INTERFACE_SIZE) - return; - - if (iif->iad) { - if ((curr[2] < iif->iad->bFirstInterface) - || (curr[2] >= (iif->iad->bFirstInterface + iif->iad->bInterfaceCount))) - iif->iad = 0; - } - break; - } - } - - iif->valid = 1; - iif->rem = rem; - iif->curr = curr; -} - -void if_iter_init(if_iterator_t *iif, const generic_iterator_t *icfg) { - iif->iad = 0; - iif->curr = icfg->curr; - iif->rem = icfg->rem; - if_iter_next(iif); -} - -void ep_iter_next(generic_iterator_t *iep) { - const uint8_t *curr = iep->curr; - uint16_t rem = iep->rem; - - iep->valid = 0; - - if ((curr[0] < 2) || (rem < 2) || (rem < curr[0])) - return; - - for (;;) { - rem -= curr[0]; - curr += curr[0]; - - if ((curr[0] < 2) || (rem < 2) || (rem < curr[0])) - return; - - if ((curr[1] == USBH_DT_INTERFACE_ASSOCIATION) - || (curr[1] == USBH_DT_INTERFACE) - || (curr[1] == USBH_DT_CONFIG)) { - return; - } else if (curr[1] == USBH_DT_ENDPOINT) { - if (curr[0] < USBH_DT_ENDPOINT_SIZE) - return; - - break; - } - } - - iep->valid = 1; - iep->rem = rem; - iep->curr = curr; -} - -void ep_iter_init(generic_iterator_t *iep, const if_iterator_t *iif) { - iep->curr = iif->curr; - iep->rem = iif->rem; - ep_iter_next(iep); -} - -void cs_iter_next(generic_iterator_t *ics) { - const uint8_t *curr = ics->curr; - uint16_t rem = ics->rem; - - ics->valid = 0; - - if ((curr[0] < 2) || (rem < 2) || (rem < curr[0])) - return; - - //for (;;) { - rem -= curr[0]; - curr += curr[0]; - - if ((curr[0] < 2) || (rem < 2) || (rem < curr[0])) - return; - - if ((curr[1] == USBH_DT_INTERFACE_ASSOCIATION) - || (curr[1] == USBH_DT_INTERFACE) - || (curr[1] == USBH_DT_CONFIG) - || (curr[1] == USBH_DT_ENDPOINT)) { - return; - } - - // break; - //} - - ics->valid = 1; - ics->rem = rem; - ics->curr = curr; -} - -void cs_iter_init(generic_iterator_t *ics, const generic_iterator_t *iter) { - ics->curr = iter->curr; - ics->rem = iter->rem; - cs_iter_next(ics); -} - -#endif diff --git a/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_ftdi.c b/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_ftdi.c deleted file mode 100644 index 4bd7296..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_ftdi.c +++ /dev/null @@ -1,717 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" -#include "hal_usbh.h" - -#if HAL_USBH_USE_FTDI - -#if !HAL_USE_USBH -#error "USBHFTDI needs USBH" -#endif - -#include <string.h> -#include "usbh/dev/ftdi.h" -#include "usbh/internal.h" - -//#pragma GCC optimize("Og") - - -#if USBHFTDI_DEBUG_ENABLE_TRACE -#define udbgf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define udbg(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define udbgf(f, ...) do {} while(0) -#define udbg(f, ...) do {} while(0) -#endif - -#if USBHFTDI_DEBUG_ENABLE_INFO -#define uinfof(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uinfo(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uinfof(f, ...) do {} while(0) -#define uinfo(f, ...) do {} while(0) -#endif - -#if USBHFTDI_DEBUG_ENABLE_WARNINGS -#define uwarnf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uwarn(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uwarnf(f, ...) do {} while(0) -#define uwarn(f, ...) do {} while(0) -#endif - -#if USBHFTDI_DEBUG_ENABLE_ERRORS -#define uerrf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uerr(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uerrf(f, ...) do {} while(0) -#define uerr(f, ...) do {} while(0) -#endif - - -/*===========================================================================*/ -/* USB Class driver loader for FTDI */ -/*===========================================================================*/ -USBHFTDIDriver USBHFTDID[HAL_USBHFTDI_MAX_INSTANCES]; - -static usbh_baseclassdriver_t *_ftdi_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem); -static void _ftdi_unload(usbh_baseclassdriver_t *drv); - -static const usbh_classdriver_vmt_t class_driver_vmt = { - _ftdi_load, - _ftdi_unload -}; - -const usbh_classdriverinfo_t usbhftdiClassDriverInfo = { - 0xff, 0xff, 0xff, "FTDI", &class_driver_vmt -}; - -static USBHFTDIPortDriver *_find_port(void) { - uint8_t i; - for (i = 0; i < HAL_USBHFTDI_MAX_PORTS; i++) { - if (FTDIPD[i].ftdip == NULL) - return &FTDIPD[i]; - } - return NULL; -} - -static usbh_baseclassdriver_t *_ftdi_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem) { - int i; - USBHFTDIDriver *ftdip; - - if (dev->devDesc.idVendor != 0x0403) { - uerr("FTDI: Unrecognized VID"); - return NULL; - } - - switch (dev->devDesc.idProduct) { - case 0x6001: - case 0x6010: - case 0x6011: - case 0x6014: - case 0x6015: - break; - default: - uerr("FTDI: Unrecognized PID"); - return NULL; - } - - if ((rem < descriptor[0]) || (descriptor[1] != USBH_DT_INTERFACE)) - return NULL; - - const usbh_interface_descriptor_t * const ifdesc = (const usbh_interface_descriptor_t * const)descriptor; - if (ifdesc->bInterfaceNumber != 0) { - uwarn("FTDI: Will allocate driver along with IF #0"); - } - - /* alloc driver */ - for (i = 0; i < HAL_USBHFTDI_MAX_INSTANCES; i++) { - if (USBHFTDID[i].dev == NULL) { - ftdip = &USBHFTDID[i]; - goto alloc_ok; - } - } - - uwarn("FTDI: Can't alloc driver"); - - /* can't alloc */ - return NULL; - -alloc_ok: - /* initialize the driver's variables */ - ftdip->ports = 0; - switch (dev->devDesc.bcdDevice) { - case 0x200: //AM - uinfo("FTDI: Type A chip"); - ftdip->type = USBHFTDI_TYPE_A; - break; - case 0x400: //BM - case 0x500: //2232C - case 0x600: //R - case 0x1000: //230X - uinfo("FTDI: Type B chip"); - ftdip->type = USBHFTDI_TYPE_B; - break; - case 0x700: //2232H; - case 0x800: //4232H; - case 0x900: //232H; - uinfo("FTDI: Type H chip"); - ftdip->type = USBHFTDI_TYPE_H; - default: - uerr("FTDI: Unrecognized chip type"); - return NULL; - } - usbhEPSetName(&dev->ctrl, "FTD[CTRL]"); - - /* parse the configuration descriptor */ - generic_iterator_t iep, icfg; - if_iterator_t iif; - cfg_iter_init(&icfg, dev->fullConfigurationDescriptor, dev->basicConfigDesc.wTotalLength); - for (if_iter_init(&iif, &icfg); iif.valid; if_iter_next(&iif)) { - const usbh_interface_descriptor_t *const ifdesc = if_get(&iif); - uinfof("FTDI: Interface #%d", ifdesc->bInterfaceNumber); - - USBHFTDIPortDriver *const prt = _find_port(); - if (prt == NULL) { - uwarn("\tCan't alloc port for this interface"); - break; - } - - prt->ifnum = ifdesc->bInterfaceNumber; - prt->epin.status = USBH_EPSTATUS_UNINITIALIZED; - prt->epout.status = USBH_EPSTATUS_UNINITIALIZED; - - for (ep_iter_init(&iep, &iif); iep.valid; ep_iter_next(&iep)) { - const usbh_endpoint_descriptor_t *const epdesc = ep_get(&iep); - if ((epdesc->bEndpointAddress & 0x80) && (epdesc->bmAttributes == USBH_EPTYPE_BULK)) { - uinfof("BULK IN endpoint found: bEndpointAddress=%02x", epdesc->bEndpointAddress); - usbhEPObjectInit(&prt->epin, dev, epdesc); - usbhEPSetName(&prt->epin, "FTD[BIN ]"); - } else if (((epdesc->bEndpointAddress & 0x80) == 0) - && (epdesc->bmAttributes == USBH_EPTYPE_BULK)) { - uinfof("BULK OUT endpoint found: bEndpointAddress=%02x", epdesc->bEndpointAddress); - usbhEPObjectInit(&prt->epout, dev, epdesc); - usbhEPSetName(&prt->epout, "FTD[BOUT]"); - } else { - uinfof("unsupported endpoint found: bEndpointAddress=%02x, bmAttributes=%02x", - epdesc->bEndpointAddress, epdesc->bmAttributes); - } - } - - if ((prt->epin.status != USBH_EPSTATUS_CLOSED) - || (prt->epout.status != USBH_EPSTATUS_CLOSED)) { - uwarn("\tCouldn't find endpoints; can't alloc port for this interface"); - continue; - } - - /* link the new block driver to the list */ - prt->next = ftdip->ports; - ftdip->ports = prt; - prt->ftdip = ftdip; - - prt->state = USBHFTDIP_STATE_ACTIVE; - } - - return (usbh_baseclassdriver_t *)ftdip; - -} - -static void _stop(USBHFTDIPortDriver *ftdipp); -static void _ftdi_unload(usbh_baseclassdriver_t *drv) { - osalDbgCheck(drv != NULL); - USBHFTDIDriver *const ftdip = (USBHFTDIDriver *)drv; - USBHFTDIPortDriver *ftdipp = ftdip->ports; - - osalMutexLock(&ftdip->mtx); - while (ftdipp) { - _stop(ftdipp); - ftdipp = ftdipp->next; - } - - ftdipp = ftdip->ports; - osalSysLock(); - while (ftdipp) { - USBHFTDIPortDriver *next = ftdipp->next; - usbhftdipObjectInit(ftdipp); - ftdipp = next; - } - osalSysUnlock(); - osalMutexUnlock(&ftdip->mtx); -} - - -USBHFTDIPortDriver FTDIPD[HAL_USBHFTDI_MAX_PORTS]; - - -#define FTDI_COMMAND_RESET 0 -#define FTDI_RESET_ALL 0 -#define FTDI_RESET_PURGE_RX 1 -#define FTDI_RESET_PURGE_TX 2 - -#define FTDI_COMMAND_SETFLOW 2 - -#define FTDI_COMMAND_SETBAUD 3 - -#define FTDI_COMMAND_SETDATA 4 -#define FTDI_SETDATA_BREAK (0x1 << 14) - -#if 0 -#define FTDI_COMMAND_MODEMCTRL 1 -#define FTDI_COMMAND_GETMODEMSTATUS 5 /* Retrieve current value of modem status register */ -#define FTDI_COMMAND_SETEVENTCHAR 6 /* Set the event character */ -#define FTDI_COMMAND_SETERRORCHAR 7 /* Set the error character */ -#define FTDI_COMMAND_SETLATENCYTIMER 9 /* Set the latency timer */ -#define FTDI_COMMAND_GETLATENCYTIMER 10 /* Get the latency timer */ -#endif - -/* - * DATA FORMAT - * - * IN Endpoint - * - * The device reserves the first two bytes of data on this endpoint to contain - * the current values of the modem and line status registers. In the absence of - * data, the device generates a message consisting of these two status bytes - * every 40 ms - * - * Byte 0: Modem Status - * - * Offset Description - * B0 Reserved - must be 1 - * B1 Reserved - must be 0 - * B2 Reserved - must be 0 - * B3 Reserved - must be 0 - * B4 Clear to Send (CTS) - * B5 Data Set Ready (DSR) - * B6 Ring Indicator (RI) - * B7 Receive Line Signal Detect (RLSD) - * - * Byte 1: Line Status - * - * Offset Description - * B0 Data Ready (DR) - * B1 Overrun Error (OE) - * B2 Parity Error (PE) - * B3 Framing Error (FE) - * B4 Break Interrupt (BI) - * B5 Transmitter Holding Register (THRE) - * B6 Transmitter Empty (TEMT) - * B7 Error in RCVR FIFO - * - */ -#define FTDI_RS0_CTS (1 << 4) -#define FTDI_RS0_DSR (1 << 5) -#define FTDI_RS0_RI (1 << 6) -#define FTDI_RS0_RLSD (1 << 7) - -#define FTDI_RS_DR 1 -#define FTDI_RS_OE (1<<1) -#define FTDI_RS_PE (1<<2) -#define FTDI_RS_FE (1<<3) -#define FTDI_RS_BI (1<<4) -#define FTDI_RS_THRE (1<<5) -#define FTDI_RS_TEMT (1<<6) -#define FTDI_RS_FIFO (1<<7) - - -static usbh_urbstatus_t _ftdi_port_control(USBHFTDIPortDriver *ftdipp, - uint8_t bRequest, uint8_t wValue, uint8_t bHIndex, uint16_t wLength, - uint8_t *buff) { - - static const uint8_t bmRequestType[] = { - USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //0 FTDI_COMMAND_RESET - USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //1 FTDI_COMMAND_MODEMCTRL - USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //2 FTDI_COMMAND_SETFLOW - USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //3 FTDI_COMMAND_SETBAUD - USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, //4 FTDI_COMMAND_SETDATA - }; - - osalDbgCheck(bRequest < sizeof_array(bmRequestType)); - osalDbgCheck(bRequest != 1); - - const USBH_DEFINE_BUFFER(usbh_control_request_t, req) = { - bmRequestType[bRequest], - bRequest, - wValue, - (bHIndex << 8) | (ftdipp->ifnum + 1), - wLength - }; - - return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, buff, NULL, MS2ST(1000)); -} - -static uint32_t _get_divisor(uint32_t baud, usbhftdi_type_t type) { - static const uint8_t divfrac[8] = {0, 3, 2, 4, 1, 5, 6, 7}; - uint32_t divisor; - - if (type == USBHFTDI_TYPE_A) { - uint32_t divisor3 = ((48000000UL / 2) + baud / 2) / baud; - uinfof("FTDI: desired=%dbps, real=%dbps", baud, (48000000UL / 2) / divisor3); - if ((divisor3 & 0x7) == 7) - divisor3++; /* round x.7/8 up to x+1 */ - - divisor = divisor3 >> 3; - divisor3 &= 0x7; - if (divisor3 == 1) - divisor |= 0xc000; - else if (divisor3 >= 4) - divisor |= 0x4000; - else if (divisor3 != 0) - divisor |= 0x8000; - else if (divisor == 1) - divisor = 0; /* special case for maximum baud rate */ - } else { - if (type == USBHFTDI_TYPE_B) { - divisor = ((48000000UL / 2) + baud / 2) / baud; - uinfof("FTDI: desired=%dbps, real=%dbps", baud, (48000000UL / 2) / divisor); - } else { - /* hi-speed baud rate is 10-bit sampling instead of 16-bit */ - if (baud < 1200) - baud = 1200; - divisor = (120000000UL * 8 + baud * 5) / (baud * 10); - uinfof("FTDI: desired=%dbps, real=%dbps", baud, (120000000UL * 8) / divisor / 10); - } - divisor = (divisor >> 3) | (divfrac[divisor & 0x7] << 14); - - /* Deal with special cases for highest baud rates. */ - if (divisor == 1) - divisor = 0; - else if (divisor == 0x4001) - divisor = 1; - - if (type == USBHFTDI_TYPE_H) - divisor |= 0x00020000; - } - return divisor; -} - -static usbh_urbstatus_t _set_baudrate(USBHFTDIPortDriver *ftdipp, uint32_t baudrate) { - uint32_t divisor = _get_divisor(baudrate, ftdipp->ftdip->type); - uint16_t wValue = (uint16_t)divisor; - uint16_t wIndex = (uint16_t)(divisor >> 16); - if (ftdipp->ftdip->dev->basicConfigDesc.bNumInterfaces > 1) - wIndex = (wIndex << 8) | (ftdipp->ifnum + 1); - - const USBH_DEFINE_BUFFER(usbh_control_request_t, req) = { - USBH_REQTYPE_VENDOR | USBH_REQTYPE_OUT | USBH_REQTYPE_DEVICE, - FTDI_COMMAND_SETBAUD, - wValue, - wIndex, - 0 - }; - return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, NULL, NULL, MS2ST(1000)); -} - - -static void _submitOutI(USBHFTDIPortDriver *ftdipp, uint32_t len) { - udbgf("FTDI: Submit OUT %d", len); - ftdipp->oq_urb.requestedLength = len; - usbhURBObjectResetI(&ftdipp->oq_urb); - usbhURBSubmitI(&ftdipp->oq_urb); -} - -static void _out_cb(usbh_urb_t *urb) { - USBHFTDIPortDriver *const ftdipp = (USBHFTDIPortDriver *)urb->userData; - switch (urb->status) { - case USBH_URBSTATUS_OK: - ftdipp->oq_ptr = ftdipp->oq_buff; - ftdipp->oq_counter = 64; - chThdDequeueNextI(&ftdipp->oq_waiting, Q_OK); - return; - case USBH_URBSTATUS_DISCONNECTED: - uwarn("FTDI: URB OUT disconnected"); - chThdDequeueNextI(&ftdipp->oq_waiting, Q_RESET); - return; - default: - uerrf("FTDI: URB OUT status unexpected = %d", urb->status); - break; - } - usbhURBObjectResetI(&ftdipp->oq_urb); - usbhURBSubmitI(&ftdipp->oq_urb); -} - -static size_t _write_timeout(USBHFTDIPortDriver *ftdipp, const uint8_t *bp, - size_t n, systime_t timeout) { - chDbgCheck(n > 0U); - - size_t w = 0; - chSysLock(); - while (true) { - if (ftdipp->state != USBHFTDIP_STATE_READY) { - chSysUnlock(); - return w; - } - while (usbhURBIsBusy(&ftdipp->oq_urb)) { - if (chThdEnqueueTimeoutS(&ftdipp->oq_waiting, timeout) != Q_OK) { - chSysUnlock(); - return w; - } - } - - *ftdipp->oq_ptr++ = *bp++; - if (--ftdipp->oq_counter == 0) { - _submitOutI(ftdipp, 64); - chSchRescheduleS(); - } - chSysUnlock(); /* Gives a preemption chance in a controlled point.*/ - - w++; - if (--n == 0U) - return w; - - chSysLock(); - } -} - -static msg_t _put_timeout(USBHFTDIPortDriver *ftdipp, uint8_t b, systime_t timeout) { - - chSysLock(); - if (ftdipp->state != USBHFTDIP_STATE_READY) { - chSysUnlock(); - return Q_RESET; - } - - while (usbhURBIsBusy(&ftdipp->oq_urb)) { - msg_t msg = chThdEnqueueTimeoutS(&ftdipp->oq_waiting, timeout); - if (msg < Q_OK) { - chSysUnlock(); - return msg; - } - } - - *ftdipp->oq_ptr++ = b; - if (--ftdipp->oq_counter == 0) { - _submitOutI(ftdipp, 64); - chSchRescheduleS(); - } - chSysUnlock(); - return Q_OK; -} - -static size_t _write(USBHFTDIPortDriver *ftdipp, const uint8_t *bp, size_t n) { - return _write_timeout(ftdipp, bp, n, TIME_INFINITE); -} - -static msg_t _put(USBHFTDIPortDriver *ftdipp, uint8_t b) { - return _put_timeout(ftdipp, b, TIME_INFINITE); -} - -static void _submitInI(USBHFTDIPortDriver *ftdipp) { - udbg("FTDI: Submit IN"); - usbhURBObjectResetI(&ftdipp->iq_urb); - usbhURBSubmitI(&ftdipp->iq_urb); -} - -static void _in_cb(usbh_urb_t *urb) { - USBHFTDIPortDriver *const ftdipp = (USBHFTDIPortDriver *)urb->userData; - switch (urb->status) { - case USBH_URBSTATUS_OK: - if (urb->actualLength < 2) { - uwarnf("FTDI: URB IN actualLength = %d, < 2", urb->actualLength); - } else if (urb->actualLength > 2) { - udbgf("FTDI: URB IN data len=%d, status=%02x %02x", - urb->actualLength - 2, - ((uint8_t *)urb->buff)[0], - ((uint8_t *)urb->buff)[1]); - ftdipp->iq_ptr = ftdipp->iq_buff + 2; - ftdipp->iq_counter = urb->actualLength - 2; - chThdDequeueNextI(&ftdipp->iq_waiting, Q_OK); - return; - } else { - udbgf("FTDI: URB IN no data, status=%02x %02x", - ((uint8_t *)urb->buff)[0], - ((uint8_t *)urb->buff)[1]); - return; - } - break; - case USBH_URBSTATUS_DISCONNECTED: - uwarn("FTDI: URB IN disconnected"); - chThdDequeueNextI(&ftdipp->iq_waiting, Q_RESET); - return; - default: - uerrf("FTDI: URB IN status unexpected = %d", urb->status); - break; - } - _submitInI(ftdipp); -} - -static size_t _read_timeout(USBHFTDIPortDriver *ftdipp, uint8_t *bp, - size_t n, systime_t timeout) { - size_t r = 0; - - chDbgCheck(n > 0U); - - chSysLock(); - while (true) { - if (ftdipp->state != USBHFTDIP_STATE_READY) { - chSysUnlock(); - return r; - } - while (ftdipp->iq_counter == 0) { - if (!usbhURBIsBusy(&ftdipp->iq_urb)) - _submitInI(ftdipp); - if (chThdEnqueueTimeoutS(&ftdipp->iq_waiting, timeout) != Q_OK) { - chSysUnlock(); - return r; - } - } - *bp++ = *ftdipp->iq_ptr++; - if (--ftdipp->iq_counter == 0) { - _submitInI(ftdipp); - chSchRescheduleS(); - } - chSysUnlock(); - - r++; - if (--n == 0U) - return r; - - chSysLock(); - } -} - -static msg_t _get_timeout(USBHFTDIPortDriver *ftdipp, systime_t timeout) { - uint8_t b; - - chSysLock(); - if (ftdipp->state != USBHFTDIP_STATE_READY) { - chSysUnlock(); - return Q_RESET; - } - while (ftdipp->iq_counter == 0) { - if (!usbhURBIsBusy(&ftdipp->iq_urb)) - _submitInI(ftdipp); - msg_t msg = chThdEnqueueTimeoutS(&ftdipp->iq_waiting, timeout); - if (msg < Q_OK) { - chSysUnlock(); - return msg; - } - } - b = *ftdipp->iq_ptr++; - if (--ftdipp->iq_counter == 0) { - _submitInI(ftdipp); - chSchRescheduleS(); - } - chSysUnlock(); - - return (msg_t)b; -} - -static msg_t _get(USBHFTDIPortDriver *ftdipp) { - return _get_timeout(ftdipp, TIME_INFINITE); -} - -static size_t _read(USBHFTDIPortDriver *ftdipp, uint8_t *bp, size_t n) { - return _read_timeout(ftdipp, bp, n, TIME_INFINITE); -} - -static void _vt(void *p) { - USBHFTDIPortDriver *const ftdipp = (USBHFTDIPortDriver *)p; - chSysLockFromISR(); - uint32_t len = ftdipp->oq_ptr - ftdipp->oq_buff; - if (len && !usbhURBIsBusy(&ftdipp->oq_urb)) { - _submitOutI(ftdipp, len); - } - if ((ftdipp->iq_counter == 0) && !usbhURBIsBusy(&ftdipp->iq_urb)) { - _submitInI(ftdipp); - } - chVTSetI(&ftdipp->vt, MS2ST(16), _vt, ftdipp); - chSysUnlockFromISR(); -} - -static const struct FTDIPortDriverVMT async_channel_vmt = { - (size_t (*)(void *, const uint8_t *, size_t))_write, - (size_t (*)(void *, uint8_t *, size_t))_read, - (msg_t (*)(void *, uint8_t))_put, - (msg_t (*)(void *))_get, - (msg_t (*)(void *, uint8_t, systime_t))_put_timeout, - (msg_t (*)(void *, systime_t))_get_timeout, - (size_t (*)(void *, const uint8_t *, size_t, systime_t))_write_timeout, - (size_t (*)(void *, uint8_t *, size_t, systime_t))_read_timeout -}; - - -static void _stop(USBHFTDIPortDriver *ftdipp) { - osalSysLock(); - chVTResetI(&ftdipp->vt); - usbhEPCloseS(&ftdipp->epin); - usbhEPCloseS(&ftdipp->epout); - chThdDequeueAllI(&ftdipp->iq_waiting, Q_RESET); - chThdDequeueAllI(&ftdipp->oq_waiting, Q_RESET); - osalOsRescheduleS(); - ftdipp->state = USBHFTDIP_STATE_ACTIVE; - osalSysUnlock(); -} - -void usbhftdipStop(USBHFTDIPortDriver *ftdipp) { - osalDbgCheck((ftdipp->state == USBHFTDIP_STATE_ACTIVE) - || (ftdipp->state == USBHFTDIP_STATE_READY)); - - if (ftdipp->state == USBHFTDIP_STATE_ACTIVE) { - return; - } - - osalMutexLock(&ftdipp->ftdip->mtx); - _stop(ftdipp); - osalMutexUnlock(&ftdipp->ftdip->mtx); -} - -void usbhftdipStart(USBHFTDIPortDriver *ftdipp, const USBHFTDIPortConfig *config) { - static const USBHFTDIPortConfig default_config = { - HAL_USBHFTDI_DEFAULT_SPEED, - HAL_USBHFTDI_DEFAULT_FRAMING, - HAL_USBHFTDI_DEFAULT_HANDSHAKE, - HAL_USBHFTDI_DEFAULT_XON, - HAL_USBHFTDI_DEFAULT_XOFF - }; - - osalDbgCheck((ftdipp->state == USBHFTDIP_STATE_ACTIVE) - || (ftdipp->state == USBHFTDIP_STATE_READY)); - - if (ftdipp->state == USBHFTDIP_STATE_READY) - return; - - osalMutexLock(&ftdipp->ftdip->mtx); - if (config == NULL) - config = &default_config; - - uint16_t wValue = 0; - _ftdi_port_control(ftdipp, FTDI_COMMAND_RESET, FTDI_RESET_ALL, 0, 0, NULL); - _set_baudrate(ftdipp, config->speed); - _ftdi_port_control(ftdipp, FTDI_COMMAND_SETDATA, config->framing, 0, 0, NULL); - if (config->handshake & USBHFTDI_HANDSHAKE_XON_XOFF) - wValue = (config->xoff_character << 8) | config->xon_character; - _ftdi_port_control(ftdipp, FTDI_COMMAND_SETFLOW, wValue, config->handshake, 0, NULL); - - usbhURBObjectInit(&ftdipp->oq_urb, &ftdipp->epout, _out_cb, ftdipp, ftdipp->oq_buff, 0); - chThdQueueObjectInit(&ftdipp->oq_waiting); - ftdipp->oq_counter = 64; - ftdipp->oq_ptr = ftdipp->oq_buff; - usbhEPOpen(&ftdipp->epout); - - usbhURBObjectInit(&ftdipp->iq_urb, &ftdipp->epin, _in_cb, ftdipp, ftdipp->iq_buff, 64); - chThdQueueObjectInit(&ftdipp->iq_waiting); - ftdipp->iq_counter = 0; - ftdipp->iq_ptr = ftdipp->iq_buff; - usbhEPOpen(&ftdipp->epin); - osalSysLock(); - usbhURBSubmitI(&ftdipp->iq_urb); - osalSysUnlock(); - - chVTObjectInit(&ftdipp->vt); - chVTSet(&ftdipp->vt, MS2ST(16), _vt, ftdipp); - - ftdipp->state = USBHFTDIP_STATE_READY; - osalMutexUnlock(&ftdipp->ftdip->mtx); -} - -void usbhftdiObjectInit(USBHFTDIDriver *ftdip) { - osalDbgCheck(ftdip != NULL); - memset(ftdip, 0, sizeof(*ftdip)); - ftdip->info = &usbhftdiClassDriverInfo; - osalMutexObjectInit(&ftdip->mtx); -} - -void usbhftdipObjectInit(USBHFTDIPortDriver *ftdipp) { - osalDbgCheck(ftdipp != NULL); - memset(ftdipp, 0, sizeof(*ftdipp)); - ftdipp->vmt = &async_channel_vmt; - ftdipp->state = USBHFTDIP_STATE_STOP; -} - -#endif diff --git a/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_hub.c b/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_hub.c deleted file mode 100644 index 7fdcef1..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_hub.c +++ /dev/null @@ -1,302 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" -#include "hal_usbh.h" -#include "usbh/internal.h" - -#if HAL_USBH_USE_HUB - -#if !HAL_USE_USBH -#error "USBHHUB needs HAL_USE_USBH" -#endif - -#include <string.h> -#include "usbh/dev/hub.h" - -#if USBHHUB_DEBUG_ENABLE_TRACE -#define udbgf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define udbg(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define udbgf(f, ...) do {} while(0) -#define udbg(f, ...) do {} while(0) -#endif - -#if USBHHUB_DEBUG_ENABLE_INFO -#define uinfof(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uinfo(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uinfof(f, ...) do {} while(0) -#define uinfo(f, ...) do {} while(0) -#endif - -#if USBHHUB_DEBUG_ENABLE_WARNINGS -#define uwarnf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uwarn(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uwarnf(f, ...) do {} while(0) -#define uwarn(f, ...) do {} while(0) -#endif - -#if USBHHUB_DEBUG_ENABLE_ERRORS -#define uerrf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uerr(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uerrf(f, ...) do {} while(0) -#define uerr(f, ...) do {} while(0) -#endif - - -USBHHubDriver USBHHUBD[HAL_USBHHUB_MAX_INSTANCES]; -usbh_port_t USBHPorts[HAL_USBHHUB_MAX_PORTS]; - -static usbh_baseclassdriver_t *hub_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem); -static void hub_unload(usbh_baseclassdriver_t *drv); -static const usbh_classdriver_vmt_t usbhhubClassDriverVMT = { - hub_load, - hub_unload -}; -const usbh_classdriverinfo_t usbhhubClassDriverInfo = { - 0x09, 0x00, -1, "HUB", &usbhhubClassDriverVMT -}; - - -void _usbhub_port_object_init(usbh_port_t *port, USBHDriver *usbh, - USBHHubDriver *hub, uint8_t number) { - memset(port, 0, sizeof(*port)); - port->number = number; - port->device.host = usbh; - port->hub = hub; -} - -usbh_urbstatus_t usbhhubControlRequest(USBHDriver *host, USBHHubDriver *hub, - uint8_t bmRequestType, - uint8_t bRequest, - uint16_t wValue, - uint16_t wIndex, - uint16_t wLength, - uint8_t *buf) { - if (hub == NULL) - return usbh_lld_root_hub_request(host, bmRequestType, bRequest, wValue, wIndex, wLength, buf); - - return usbhControlRequest(hub->dev, - bmRequestType, bRequest, wValue, wIndex, wLength, buf); -} - - -static void _urb_complete(usbh_urb_t *urb) { - - USBHHubDriver *const hubdp = (USBHHubDriver *)urb->userData; - switch (urb->status) { - case USBH_URBSTATUS_TIMEOUT: - /* the device NAKed */ - udbg("HUB: no info"); - hubdp->statuschange = 0; - break; - case USBH_URBSTATUS_OK: { - uint8_t len = hubdp->hubDesc.bNbrPorts / 8 + 1; - if (urb->actualLength != len) { - uwarnf("Expected %d status change bytes but got %d", len, urb->actualLength); - } - - if (urb->actualLength < len) - len = urb->actualLength; - - if (len > 4) - len = 4; - - uint8_t *sc = (uint8_t *)&hubdp->statuschange; - uint8_t *r = hubdp->scbuff; - while (len--) - *sc++ |= *r++; - - uinfof("HUB: change, %08x", hubdp->statuschange); - } break; - case USBH_URBSTATUS_DISCONNECTED: - uwarn("HUB: URB disconnected, aborting poll"); - return; - default: - uerrf("HUB: URB status unexpected = %d", urb->status); - break; - } - - usbhURBObjectResetI(urb); - usbhURBSubmitI(urb); -} - -static usbh_baseclassdriver_t *hub_load(usbh_device_t *dev, - const uint8_t *descriptor, uint16_t rem) { - int i; - - USBHHubDriver *hubdp; - - if ((rem < descriptor[0]) || (descriptor[1] != USBH_DT_DEVICE)) - return NULL; - - if (dev->devDesc.bDeviceProtocol != 0) - return NULL; - - generic_iterator_t iep, icfg; - if_iterator_t iif; - - cfg_iter_init(&icfg, dev->fullConfigurationDescriptor, - dev->basicConfigDesc.wTotalLength); - - if_iter_init(&iif, &icfg); - if (!iif.valid) - return NULL; - const usbh_interface_descriptor_t *const ifdesc = if_get(&iif); - if ((ifdesc->bInterfaceClass != 0x09) - || (ifdesc->bInterfaceSubClass != 0x00) - || (ifdesc->bInterfaceProtocol != 0x00)) { - return NULL; - } - - ep_iter_init(&iep, &iif); - if (!iep.valid) - return NULL; - const usbh_endpoint_descriptor_t *const epdesc = ep_get(&iep); - if ((epdesc->bmAttributes & 0x03) != USBH_EPTYPE_INT) { - return NULL; - } - - - /* alloc driver */ - for (i = 0; i < HAL_USBHHUB_MAX_INSTANCES; i++) { - if (USBHHUBD[i].dev == NULL) { - hubdp = &USBHHUBD[i]; - goto alloc_ok; - } - } - - uwarn("Can't alloc HUB driver"); - - /* can't alloc */ - return NULL; - -alloc_ok: - /* initialize the driver's variables */ - hubdp->epint.status = USBH_EPSTATUS_UNINITIALIZED; - hubdp->dev = dev; - hubdp->ports = 0; - - usbhEPSetName(&dev->ctrl, "HUB[CTRL]"); - - /* read Hub descriptor */ - uinfo("Read Hub descriptor"); - if (usbhhubControlRequest(dev->host, hubdp, - USBH_REQTYPE_IN | USBH_REQTYPE_CLASS | USBH_REQTYPE_DEVICE, - USBH_REQ_GET_DESCRIPTOR, - (USBH_DT_HUB << 8), 0, sizeof(hubdp->hubDesc), - (uint8_t *)&hubdp->hubDesc) != USBH_URBSTATUS_OK) { - hubdp->dev = NULL; - return NULL; - } - - const usbh_hub_descriptor_t *const hubdesc = &hubdp->hubDesc; - - uinfof("Hub descriptor loaded; %d ports, wHubCharacteristics=%04x, bPwrOn2PwrGood=%d, bHubContrCurrent=%d", - hubdesc->bNbrPorts, - hubdesc->wHubCharacteristics, - hubdesc->bPwrOn2PwrGood, - hubdesc->bHubContrCurrent); - - /* Alloc ports */ - uint8_t ports = hubdesc->bNbrPorts; - for (i = 0; (ports > 0) && (i < HAL_USBHHUB_MAX_PORTS); i++) { - if (USBHPorts[i].hub == NULL) { - uinfof("Alloc port %d", ports); - _usbhub_port_object_init(&USBHPorts[i], dev->host, hubdp, ports); - USBHPorts[i].next = hubdp->ports; - hubdp->ports = &USBHPorts[i]; - --ports; - } - } - - if (ports) { - uwarn("Could not alloc all ports"); - } - - /* link hub to the host's list */ - list_add_tail(&hubdp->node, &dev->host->hubs); - - /* enable power to ports */ - usbh_port_t *port = hubdp->ports; - while (port) { - uinfof("Enable power for port %d", port->number); - usbhhubSetFeaturePort(port, USBH_PORT_FEAT_POWER); - port = port->next; - } - - if (hubdesc->bPwrOn2PwrGood) - osalThreadSleepMilliseconds(2 * hubdesc->bPwrOn2PwrGood); - - /* initialize the status change endpoint and trigger the first transfer */ - usbhEPObjectInit(&hubdp->epint, dev, epdesc); - usbhEPSetName(&hubdp->epint, "HUB[INT ]"); - usbhEPOpen(&hubdp->epint); - - usbhURBObjectInit(&hubdp->urb, &hubdp->epint, - _urb_complete, hubdp, hubdp->scbuff, - (hubdesc->bNbrPorts + 8) / 8); - - osalSysLock(); - usbhURBSubmitI(&hubdp->urb); - osalOsRescheduleS(); - osalSysUnlock(); - - return (usbh_baseclassdriver_t *)hubdp; -} - -static void hub_unload(usbh_baseclassdriver_t *drv) { - osalDbgCheck(drv != NULL); - USBHHubDriver *const hubdp = (USBHHubDriver *)drv; - - /* close the status change endpoint (this cancels ongoing URBs) */ - osalSysLock(); - usbhEPCloseS(&hubdp->epint); - osalSysUnlock(); - - /* de-alloc ports and unload drivers */ - usbh_port_t *port = hubdp->ports; - while (port) { - _usbh_port_disconnected(port); - port->hub = NULL; - port = port->next; - } - - /* unlink the hub from the host's list */ - list_del(&hubdp->node); - -} - -void usbhhubObjectInit(USBHHubDriver *hubdp) { - osalDbgCheck(hubdp != NULL); - memset(hubdp, 0, sizeof(*hubdp)); - hubdp->info = &usbhhubClassDriverInfo; -} -#else - -#if HAL_USE_USBH -void _usbhub_port_object_init(usbh_port_t *port, USBHDriver *usbh, uint8_t number) { - memset(port, 0, sizeof(*port)); - port->number = number; - port->device.host = usbh; -} -#endif - -#endif diff --git a/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_msd.c b/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_msd.c deleted file mode 100644 index 6869a74..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_msd.c +++ /dev/null @@ -1,939 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" -#include "hal_usbh.h" - -#if HAL_USBH_USE_MSD - -#if !HAL_USE_USBH -#error "USBHMSD needs USBH" -#endif - -#include <string.h> -#include "usbh/dev/msd.h" -#include "usbh/internal.h" - -//#pragma GCC optimize("Og") - - -#if USBHMSD_DEBUG_ENABLE_TRACE -#define udbgf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define udbg(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define udbgf(f, ...) do {} while(0) -#define udbg(f, ...) do {} while(0) -#endif - -#if USBHMSD_DEBUG_ENABLE_INFO -#define uinfof(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uinfo(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uinfof(f, ...) do {} while(0) -#define uinfo(f, ...) do {} while(0) -#endif - -#if USBHMSD_DEBUG_ENABLE_WARNINGS -#define uwarnf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uwarn(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uwarnf(f, ...) do {} while(0) -#define uwarn(f, ...) do {} while(0) -#endif - -#if USBHMSD_DEBUG_ENABLE_ERRORS -#define uerrf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uerr(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uerrf(f, ...) do {} while(0) -#define uerr(f, ...) do {} while(0) -#endif - - - - - -/*===========================================================================*/ -/* USB Class driver loader for MSD */ -/*===========================================================================*/ - -USBHMassStorageDriver USBHMSD[HAL_USBHMSD_MAX_INSTANCES]; - -static usbh_baseclassdriver_t *_msd_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem); -static void _msd_unload(usbh_baseclassdriver_t *drv); - -static const usbh_classdriver_vmt_t class_driver_vmt = { - _msd_load, - _msd_unload -}; - -const usbh_classdriverinfo_t usbhmsdClassDriverInfo = { - 0x08, 0x06, 0x50, "MSD", &class_driver_vmt -}; - -#define MSD_REQ_RESET 0xFF -#define MSD_GET_MAX_LUN 0xFE - -static usbh_baseclassdriver_t *_msd_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem) { - int i; - USBHMassStorageDriver *msdp; - uint8_t luns; // should declare it here to eliminate 'control bypass initialization' warning - usbh_urbstatus_t stat; // should declare it here to eliminate 'control bypass initialization' warning - - if ((rem < descriptor[0]) || (descriptor[1] != USBH_DT_INTERFACE)) - return NULL; - - const usbh_interface_descriptor_t * const ifdesc = (const usbh_interface_descriptor_t *)descriptor; - - if ((ifdesc->bAlternateSetting != 0) - || (ifdesc->bNumEndpoints < 2) - || (ifdesc->bInterfaceSubClass != 0x06) - || (ifdesc->bInterfaceProtocol != 0x50)) { - return NULL; - } - - /* alloc driver */ - for (i = 0; i < HAL_USBHMSD_MAX_INSTANCES; i++) { - if (USBHMSD[i].dev == NULL) { - msdp = &USBHMSD[i]; - goto alloc_ok; - } - } - - uwarn("Can't alloc MSD driver"); - - /* can't alloc */ - return NULL; - -alloc_ok: - /* initialize the driver's variables */ - msdp->epin.status = USBH_EPSTATUS_UNINITIALIZED; - msdp->epout.status = USBH_EPSTATUS_UNINITIALIZED; - msdp->max_lun = 0; - msdp->tag = 0; - msdp->luns = 0; - msdp->ifnum = ifdesc->bInterfaceNumber; - usbhEPSetName(&dev->ctrl, "MSD[CTRL]"); - - /* parse the configuration descriptor */ - if_iterator_t iif; - generic_iterator_t iep; - iif.iad = 0; - iif.curr = descriptor; - iif.rem = rem; - for (ep_iter_init(&iep, &iif); iep.valid; ep_iter_next(&iep)) { - const usbh_endpoint_descriptor_t *const epdesc = ep_get(&iep); - if ((epdesc->bEndpointAddress & 0x80) && (epdesc->bmAttributes == USBH_EPTYPE_BULK)) { - uinfof("BULK IN endpoint found: bEndpointAddress=%02x", epdesc->bEndpointAddress); - usbhEPObjectInit(&msdp->epin, dev, epdesc); - usbhEPSetName(&msdp->epin, "MSD[BIN ]"); - } else if (((epdesc->bEndpointAddress & 0x80) == 0) - && (epdesc->bmAttributes == USBH_EPTYPE_BULK)) { - uinfof("BULK OUT endpoint found: bEndpointAddress=%02x", epdesc->bEndpointAddress); - usbhEPObjectInit(&msdp->epout, dev, epdesc); - usbhEPSetName(&msdp->epout, "MSD[BOUT]"); - } else { - uinfof("unsupported endpoint found: bEndpointAddress=%02x, bmAttributes=%02x", - epdesc->bEndpointAddress, epdesc->bmAttributes); - } - } - if ((msdp->epin.status != USBH_EPSTATUS_CLOSED) || (msdp->epout.status != USBH_EPSTATUS_CLOSED)) { - goto deinit; - } - - /* read the number of LUNs */ - uinfo("Reading Max LUN:"); - USBH_DEFINE_BUFFER(uint8_t, buff[4]); - stat = usbhControlRequest(dev, - USBH_CLASSIN(USBH_REQTYPE_INTERFACE, MSD_GET_MAX_LUN, 0, msdp->ifnum), - 1, buff); - if (stat == USBH_URBSTATUS_OK) { - msdp->max_lun = buff[0] + 1; - uinfof("\tmax_lun = %d", msdp->max_lun); - if (msdp->max_lun > HAL_USBHMSD_MAX_LUNS) { - msdp->max_lun = HAL_USBHMSD_MAX_LUNS; - uwarnf("\tUsing max_lun = %d", msdp->max_lun); - } - } else if (stat == USBH_URBSTATUS_STALL) { - uwarn("\tStall, max_lun = 1"); - msdp->max_lun = 1; - } else { - uerr("\tError"); - goto deinit; - } - - /* open the bulk IN/OUT endpoints */ - usbhEPOpen(&msdp->epin); - usbhEPOpen(&msdp->epout); - - /* Alloc one block device per logical unit found */ - luns = msdp->max_lun; - for (i = 0; (luns > 0) && (i < HAL_USBHMSD_MAX_LUNS); i++) { - if (MSBLKD[i].msdp == NULL) { - /* link the new block driver to the list */ - MSBLKD[i].next = msdp->luns; - msdp->luns = &MSBLKD[i]; - MSBLKD[i].msdp = msdp; - - osalSysLock(); - MSBLKD[i].state = BLK_ACTIVE; /* transition directly to active, instead of BLK_STOP */ - osalSysUnlock(); - - /* connect the LUN (TODO: review if it's best to leave the LUN disconnected) */ - usbhmsdLUNConnect(&MSBLKD[i]); - luns--; - } - } - - return (usbh_baseclassdriver_t *)msdp; - -deinit: - /* Here, the enpoints are closed, and the driver is unlinked */ - return NULL; -} - -static void _msd_unload(usbh_baseclassdriver_t *drv) { - osalDbgCheck(drv != NULL); - USBHMassStorageDriver *const msdp = (USBHMassStorageDriver *)drv; - USBHMassStorageLUNDriver *lunp = msdp->luns; - - osalMutexLock(&msdp->mtx); - osalSysLock(); - usbhEPCloseS(&msdp->epin); - usbhEPCloseS(&msdp->epout); - while (lunp) { - lunp->state = BLK_STOP; - lunp = lunp->next; - } - osalSysUnlock(); - osalMutexUnlock(&msdp->mtx); - - /* now that the LUNs are idle, deinit them */ - lunp = msdp->luns; - osalSysLock(); - while (lunp) { - usbhmsdLUNObjectInit(lunp); - lunp = lunp->next; - } - osalSysUnlock(); -} - - -/*===========================================================================*/ -/* MSD Class driver operations (Bulk-Only transport) */ -/*===========================================================================*/ - - - -/* USB Bulk Only Transport SCSI Command block wrapper */ -PACKED_STRUCT { - uint32_t dCBWSignature; - uint32_t dCBWTag; - uint32_t dCBWDataTransferLength; - uint8_t bmCBWFlags; - uint8_t bCBWLUN; - uint8_t bCBWCBLength; - uint8_t CBWCB[16]; -} msd_cbw_t; -#define MSD_CBW_SIGNATURE 0x43425355 -#define MSD_CBWFLAGS_D2H 0x80 -#define MSD_CBWFLAGS_H2D 0x00 - - -/* USB Bulk Only Transport SCSI Command status wrapper */ -PACKED_STRUCT { - uint32_t dCSWSignature; - uint32_t dCSWTag; - uint32_t dCSWDataResidue; - uint8_t bCSWStatus; -} msd_csw_t; -#define MSD_CSW_SIGNATURE 0x53425355 - - -typedef union { - msd_cbw_t cbw; - msd_csw_t csw; -} msd_transaction_t; - -typedef enum { - MSD_TRANSACTIONRESULT_OK, - MSD_TRANSACTIONRESULT_DISCONNECTED, - MSD_TRANSACTIONRESULT_STALL, - MSD_TRANSACTIONRESULT_BUS_ERROR, - MSD_TRANSACTIONRESULT_SYNC_ERROR -} msd_transaction_result_t; - -typedef enum { - MSD_COMMANDRESULT_PASSED = 0, - MSD_COMMANDRESULT_FAILED = 1, - MSD_COMMANDRESULT_PHASE_ERROR = 2 -} msd_command_result_t; - -typedef struct { - msd_transaction_result_t tres; - msd_command_result_t cres; -} msd_result_t; - - -/* ----------------------------------------------------- */ -/* SCSI Commands */ -/* ----------------------------------------------------- */ - -/* Read 10 and Write 10 */ -#define SCSI_CMD_READ_10 0x28 -#define SCSI_CMD_WRITE_10 0x2A - -/* Request sense */ -#define SCSI_CMD_REQUEST_SENSE 0x03 -PACKED_STRUCT { - uint8_t byte[18]; -} scsi_sense_response_t; - -#define SCSI_SENSE_KEY_GOOD 0x00 -#define SCSI_SENSE_KEY_RECOVERED_ERROR 0x01 -#define SCSI_SENSE_KEY_NOT_READY 0x02 -#define SCSI_SENSE_KEY_MEDIUM_ERROR 0x03 -#define SCSI_SENSE_KEY_HARDWARE_ERROR 0x04 -#define SCSI_SENSE_KEY_ILLEGAL_REQUEST 0x05 -#define SCSI_SENSE_KEY_UNIT_ATTENTION 0x06 -#define SCSI_SENSE_KEY_DATA_PROTECT 0x07 -#define SCSI_SENSE_KEY_BLANK_CHECK 0x08 -#define SCSI_SENSE_KEY_VENDOR_SPECIFIC 0x09 -#define SCSI_SENSE_KEY_COPY_ABORTED 0x0A -#define SCSI_SENSE_KEY_ABORTED_COMMAND 0x0B -#define SCSI_SENSE_KEY_VOLUME_OVERFLOW 0x0D -#define SCSI_SENSE_KEY_MISCOMPARE 0x0E -#define SCSI_ASENSE_NO_ADDITIONAL_INFORMATION 0x00 -#define SCSI_ASENSE_LOGICAL_UNIT_NOT_READY 0x04 -#define SCSI_ASENSE_INVALID_FIELD_IN_CDB 0x24 -#define SCSI_ASENSE_NOT_READY_TO_READY_CHANGE 0x28 -#define SCSI_ASENSE_WRITE_PROTECTED 0x27 -#define SCSI_ASENSE_FORMAT_ERROR 0x31 -#define SCSI_ASENSE_INVALID_COMMAND 0x20 -#define SCSI_ASENSE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 -#define SCSI_ASENSE_MEDIUM_NOT_PRESENT 0x3A -#define SCSI_ASENSEQ_NO_QUALIFIER 0x00 -#define SCSI_ASENSEQ_FORMAT_COMMAND_FAILED 0x01 -#define SCSI_ASENSEQ_INITIALIZING_COMMAND_REQUIRED 0x02 -#define SCSI_ASENSEQ_OPERATION_IN_PROGRESS 0x07 - -/* Inquiry */ -#define SCSI_CMD_INQUIRY 0x12 -PACKED_STRUCT { - uint8_t peripheral; - uint8_t removable; - uint8_t version; - uint8_t response_data_format; - uint8_t additional_length; - uint8_t sccstp; - uint8_t bqueetc; - uint8_t cmdque; - uint8_t vendorID[8]; - uint8_t productID[16]; - uint8_t productRev[4]; -} scsi_inquiry_response_t; - -/* Read Capacity 10 */ -#define SCSI_CMD_READ_CAPACITY_10 0x25 -PACKED_STRUCT { - uint32_t last_block_addr; - uint32_t block_size; -} scsi_readcapacity10_response_t; - -/* Start/Stop Unit */ -#define SCSI_CMD_START_STOP_UNIT 0x1B -PACKED_STRUCT { - uint8_t op_code; - uint8_t lun_immed; - uint8_t res1; - uint8_t res2; - uint8_t loej_start; - uint8_t control; -} scsi_startstopunit_request_t; - -/* test unit ready */ -#define SCSI_CMD_TEST_UNIT_READY 0x00 - -/* Other commands, TODO: use or remove them -#define SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E -#define SCSI_CMD_VERIFY_10 0x2F -#define SCSI_CMD_SEND_DIAGNOSTIC 0x1D -#define SCSI_CMD_MODE_SENSE_6 0x1A -*/ - -static inline void _prepare_cbw(msd_transaction_t *tran, USBHMassStorageLUNDriver *lunp) { - tran->cbw.bCBWLUN = (uint8_t)(lunp - &lunp->msdp->luns[0]); - memset(&tran->cbw.CBWCB, 0, sizeof(tran->cbw.CBWCB)); -} - -static msd_transaction_result_t _msd_transaction(msd_transaction_t *tran, USBHMassStorageLUNDriver *lunp, void *data) { - - uint32_t actual_len; - usbh_urbstatus_t status; - - tran->cbw.dCBWSignature = MSD_CBW_SIGNATURE; - tran->cbw.dCBWTag = ++lunp->msdp->tag; - - /* control phase */ - status = usbhBulkTransfer(&lunp->msdp->epout, &tran->cbw, - sizeof(tran->cbw), &actual_len, MS2ST(1000)); - - if (status == USBH_URBSTATUS_CANCELLED) { - uerr("\tMSD: Control phase: USBH_URBSTATUS_CANCELLED"); - return MSD_TRANSACTIONRESULT_DISCONNECTED; - } else if (status == USBH_URBSTATUS_STALL) { - uerr("\tMSD: Control phase: USBH_URBSTATUS_STALL"); - return MSD_TRANSACTIONRESULT_STALL; - } else if (status != USBH_URBSTATUS_OK) { - uerrf("\tMSD: Control phase: status = %d, != OK", status); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } else if (actual_len != sizeof(tran->cbw)) { - uerrf("\tMSD: Control phase: wrong actual_len = %d", actual_len); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } - - - /* data phase */ - if (tran->cbw.dCBWDataTransferLength) { - status = usbhBulkTransfer( - tran->cbw.bmCBWFlags & MSD_CBWFLAGS_D2H ? &lunp->msdp->epin : &lunp->msdp->epout, - data, - tran->cbw.dCBWDataTransferLength, - &actual_len, MS2ST(20000)); - - if (status == USBH_URBSTATUS_CANCELLED) { - uerr("\tMSD: Data phase: USBH_URBSTATUS_CANCELLED"); - return MSD_TRANSACTIONRESULT_DISCONNECTED; - } else if (status == USBH_URBSTATUS_STALL) { - uerr("\tMSD: Data phase: USBH_URBSTATUS_STALL"); - return MSD_TRANSACTIONRESULT_STALL; - } else if (status != USBH_URBSTATUS_OK) { - uerrf("\tMSD: Data phase: status = %d, != OK", status); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } else if (actual_len != tran->cbw.dCBWDataTransferLength) { - uerrf("\tMSD: Data phase: wrong actual_len = %d", actual_len); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } - } - - - /* status phase */ - status = usbhBulkTransfer(&lunp->msdp->epin, &tran->csw, - sizeof(tran->csw), &actual_len, MS2ST(1000)); - - if (status == USBH_URBSTATUS_CANCELLED) { - uerr("\tMSD: Status phase: USBH_URBSTATUS_CANCELLED"); - return MSD_TRANSACTIONRESULT_DISCONNECTED; - } else if (status == USBH_URBSTATUS_STALL) { - uerr("\tMSD: Status phase: USBH_URBSTATUS_STALL"); - return MSD_TRANSACTIONRESULT_STALL; - } else if (status != USBH_URBSTATUS_OK) { - uerrf("\tMSD: Status phase: status = %d, != OK", status); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } else if (actual_len != sizeof(tran->csw)) { - uerrf("\tMSD: Status phase: wrong actual_len = %d", actual_len); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } else if (tran->csw.dCSWSignature != MSD_CSW_SIGNATURE) { - uerr("\tMSD: Status phase: wrong signature"); - return MSD_TRANSACTIONRESULT_BUS_ERROR; - } else if (tran->csw.dCSWTag != lunp->msdp->tag) { - uerrf("\tMSD: Status phase: wrong tag (expected %d, got %d)", - lunp->msdp->tag, tran->csw.dCSWTag); - return MSD_TRANSACTIONRESULT_SYNC_ERROR; - } - - if (tran->csw.dCSWDataResidue) { - uwarnf("\tMSD: Residue=%d", tran->csw.dCSWDataResidue); - } - - return MSD_TRANSACTIONRESULT_OK; -} - - -static msd_result_t scsi_inquiry(USBHMassStorageLUNDriver *lunp, scsi_inquiry_response_t *resp) { - msd_transaction_t transaction; - msd_result_t res; - - _prepare_cbw(&transaction, lunp); - transaction.cbw.dCBWDataTransferLength = sizeof(scsi_inquiry_response_t); - transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H; - transaction.cbw.bCBWCBLength = 6; - transaction.cbw.CBWCB[0] = SCSI_CMD_INQUIRY; - transaction.cbw.CBWCB[4] = sizeof(scsi_inquiry_response_t); - - res.tres = _msd_transaction(&transaction, lunp, resp); - if (res.tres == MSD_TRANSACTIONRESULT_OK) { - res.cres = (msd_command_result_t) transaction.csw.bCSWStatus; - } - return res; -} - -static msd_result_t scsi_requestsense(USBHMassStorageLUNDriver *lunp, scsi_sense_response_t *resp) { - msd_transaction_t transaction; - msd_result_t res; - - _prepare_cbw(&transaction, lunp); - transaction.cbw.dCBWDataTransferLength = sizeof(scsi_sense_response_t); - transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H; - transaction.cbw.bCBWCBLength = 12; - transaction.cbw.CBWCB[0] = SCSI_CMD_REQUEST_SENSE; - transaction.cbw.CBWCB[4] = sizeof(scsi_sense_response_t); - - res.tres = _msd_transaction(&transaction, lunp, resp); - if (res.tres == MSD_TRANSACTIONRESULT_OK) { - res.cres = (msd_command_result_t) transaction.csw.bCSWStatus; - } - return res; -} - -static msd_result_t scsi_testunitready(USBHMassStorageLUNDriver *lunp) { - msd_transaction_t transaction; - msd_result_t res; - - _prepare_cbw(&transaction, lunp); - transaction.cbw.dCBWDataTransferLength = 0; - transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H; - transaction.cbw.bCBWCBLength = 6; - transaction.cbw.CBWCB[0] = SCSI_CMD_TEST_UNIT_READY; - - res.tres = _msd_transaction(&transaction, lunp, NULL); - if (res.tres == MSD_TRANSACTIONRESULT_OK) { - res.cres = (msd_command_result_t) transaction.csw.bCSWStatus; - } - return res; -} - -static msd_result_t scsi_readcapacity10(USBHMassStorageLUNDriver *lunp, scsi_readcapacity10_response_t *resp) { - msd_transaction_t transaction; - msd_result_t res; - - _prepare_cbw(&transaction, lunp); - transaction.cbw.dCBWDataTransferLength = sizeof(scsi_readcapacity10_response_t); - transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H; - transaction.cbw.bCBWCBLength = 12; - transaction.cbw.CBWCB[0] = SCSI_CMD_READ_CAPACITY_10; - - res.tres = _msd_transaction(&transaction, lunp, resp); - if (res.tres == MSD_TRANSACTIONRESULT_OK) { - res.cres = (msd_command_result_t) transaction.csw.bCSWStatus; - } - return res; -} - - -static msd_result_t scsi_read10(USBHMassStorageLUNDriver *lunp, uint32_t lba, uint16_t n, uint8_t *data) { - msd_transaction_t transaction; - msd_result_t res; - - _prepare_cbw(&transaction, lunp); - transaction.cbw.dCBWDataTransferLength = n * lunp->info.blk_size; - transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_D2H; - transaction.cbw.bCBWCBLength = 10; - transaction.cbw.CBWCB[0] = SCSI_CMD_READ_10; - transaction.cbw.CBWCB[2] = (uint8_t)(lba >> 24); - transaction.cbw.CBWCB[3] = (uint8_t)(lba >> 16); - transaction.cbw.CBWCB[4] = (uint8_t)(lba >> 8); - transaction.cbw.CBWCB[5] = (uint8_t)(lba); - transaction.cbw.CBWCB[7] = (uint8_t)(n >> 8); - transaction.cbw.CBWCB[8] = (uint8_t)(n); - - res.tres = _msd_transaction(&transaction, lunp, data); - if (res.tres == MSD_TRANSACTIONRESULT_OK) { - res.cres = (msd_command_result_t) transaction.csw.bCSWStatus; - } - return res; -} - -static msd_result_t scsi_write10(USBHMassStorageLUNDriver *lunp, uint32_t lba, uint16_t n, const uint8_t *data) { - msd_transaction_t transaction; - msd_result_t res; - - _prepare_cbw(&transaction, lunp); - transaction.cbw.dCBWDataTransferLength = n * lunp->info.blk_size; - transaction.cbw.bmCBWFlags = MSD_CBWFLAGS_H2D; - transaction.cbw.bCBWCBLength = 10; - transaction.cbw.CBWCB[0] = SCSI_CMD_WRITE_10; - transaction.cbw.CBWCB[2] = (uint8_t)(lba >> 24); - transaction.cbw.CBWCB[3] = (uint8_t)(lba >> 16); - transaction.cbw.CBWCB[4] = (uint8_t)(lba >> 8); - transaction.cbw.CBWCB[5] = (uint8_t)(lba); - transaction.cbw.CBWCB[7] = (uint8_t)(n >> 8); - transaction.cbw.CBWCB[8] = (uint8_t)(n); - - res.tres = _msd_transaction(&transaction, lunp, (uint8_t *)data); - if (res.tres == MSD_TRANSACTIONRESULT_OK) { - res.cres = (msd_command_result_t) transaction.csw.bCSWStatus; - } - return res; -} - - - -/*===========================================================================*/ -/* Block driver data/functions */ -/*===========================================================================*/ - -USBHMassStorageLUNDriver MSBLKD[HAL_USBHMSD_MAX_LUNS]; - -static const struct USBHMassStorageDriverVMT blk_vmt = { - (bool (*)(void *))usbhmsdLUNIsInserted, - (bool (*)(void *))usbhmsdLUNIsProtected, - (bool (*)(void *))usbhmsdLUNConnect, - (bool (*)(void *))usbhmsdLUNDisconnect, - (bool (*)(void *, uint32_t, uint8_t *, uint32_t))usbhmsdLUNRead, - (bool (*)(void *, uint32_t, const uint8_t *, uint32_t))usbhmsdLUNWrite, - (bool (*)(void *))usbhmsdLUNSync, - (bool (*)(void *, BlockDeviceInfo *))usbhmsdLUNGetInfo -}; - - - -static uint32_t _requestsense(USBHMassStorageLUNDriver *lunp) { - scsi_sense_response_t sense; - msd_result_t res; - - res = scsi_requestsense(lunp, &sense); - if (res.tres != MSD_TRANSACTIONRESULT_OK) { - uerr("\tREQUEST SENSE: Transaction error"); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_FAILED) { - uerr("\tREQUEST SENSE: Command Failed"); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) { - //TODO: Do reset, etc. - uerr("\tREQUEST SENSE: Command Phase Error"); - goto failed; - } - - uerrf("\tREQUEST SENSE: Sense key=%x, ASC=%02x, ASCQ=%02x", - sense.byte[2] & 0xf, sense.byte[12], sense.byte[13]); - - return (sense.byte[2] & 0xf) | (sense.byte[12] << 8) | (sense.byte[13] << 16); - -failed: - return 0xffffffff; -} - -void usbhmsdLUNObjectInit(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - memset(lunp, 0, sizeof(*lunp)); - lunp->vmt = &blk_vmt; - lunp->state = BLK_STOP; - /* Unnecessary because of the memset: - lunp->msdp = NULL; - lunp->next = NULL; - lunp->info.* = 0; - */ -} - -void usbhmsdLUNStart(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - osalSysLock(); - osalDbgAssert((lunp->state == BLK_STOP) || (lunp->state == BLK_ACTIVE), - "invalid state"); - //TODO: complete - //lunp->state = BLK_ACTIVE; - osalSysUnlock(); -} - -void usbhmsdLUNStop(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - osalSysLock(); - osalDbgAssert((lunp->state == BLK_STOP) || (lunp->state == BLK_ACTIVE), - "invalid state"); - //TODO: complete - //lunp->state = BLK_STOP; - osalSysUnlock(); -} - -bool usbhmsdLUNConnect(USBHMassStorageLUNDriver *lunp) { - USBHMassStorageDriver *const msdp = lunp->msdp; - msd_result_t res; - - osalDbgCheck(msdp != NULL); - osalSysLock(); - //osalDbgAssert((lunp->state == BLK_ACTIVE) || (lunp->state == BLK_READY), - // "invalid state"); - if (lunp->state == BLK_READY) { - osalSysUnlock(); - return HAL_SUCCESS; - } else if (lunp->state != BLK_ACTIVE) { - osalSysUnlock(); - return HAL_FAILED; - } - lunp->state = BLK_CONNECTING; - osalSysUnlock(); - - osalMutexLock(&msdp->mtx); - - USBH_DEFINE_BUFFER(union { - scsi_inquiry_response_t inq; - scsi_readcapacity10_response_t cap; }, u); - - uinfo("INQUIRY..."); - res = scsi_inquiry(lunp, &u.inq); - if (res.tres != MSD_TRANSACTIONRESULT_OK) { - uerr("\tINQUIRY: Transaction error"); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_FAILED) { - uerr("\tINQUIRY: Command Failed"); - _requestsense(lunp); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) { - //TODO: Do reset, etc. - uerr("\tINQUIRY: Command Phase Error"); - goto failed; - } - - uinfof("\tPDT=%02x", u.inq.peripheral & 0x1f); - if (u.inq.peripheral != 0) { - uerr("\tUnsupported PDT"); - goto failed; - } - - // Test if unit ready - uint8_t i; - for (i = 0; i < 10; i++) { - uinfo("TEST UNIT READY..."); - res = scsi_testunitready(lunp); - if (res.tres != MSD_TRANSACTIONRESULT_OK) { - uerr("\tTEST UNIT READY: Transaction error"); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_FAILED) { - uerr("\tTEST UNIT READY: Command Failed"); - _requestsense(lunp); - continue; - } else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) { - //TODO: Do reset, etc. - uerr("\tTEST UNIT READY: Command Phase Error"); - goto failed; - } - uinfo("\tReady."); - break; - // osalThreadSleepMilliseconds(200); // will raise 'code is unreachable' warning - } - if (i == 10) goto failed; - - // Read capacity - uinfo("READ CAPACITY(10)..."); - res = scsi_readcapacity10(lunp, &u.cap); - if (res.tres != MSD_TRANSACTIONRESULT_OK) { - uerr("\tREAD CAPACITY(10): Transaction error"); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_FAILED) { - uerr("\tREAD CAPACITY(10): Command Failed"); - _requestsense(lunp); - goto failed; - } else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) { - //TODO: Do reset, etc. - uerr("\tREAD CAPACITY(10): Command Phase Error"); - goto failed; - } - lunp->info.blk_size = __REV(u.cap.block_size); - lunp->info.blk_num = __REV(u.cap.last_block_addr) + 1; - uinfof("\tBlock size=%dbytes, blocks=%u (~%u MB)", lunp->info.blk_size, lunp->info.blk_num, - (uint32_t)(((uint64_t)lunp->info.blk_size * lunp->info.blk_num) / (1024UL * 1024UL))); - - uinfo("MSD Connected."); - - osalMutexUnlock(&msdp->mtx); - osalSysLock(); - lunp->state = BLK_READY; - osalSysUnlock(); - - return HAL_SUCCESS; - - /* Connection failed, state reset to BLK_ACTIVE.*/ -failed: - osalMutexUnlock(&msdp->mtx); - osalSysLock(); - lunp->state = BLK_ACTIVE; - osalSysUnlock(); - return HAL_FAILED; -} - - -bool usbhmsdLUNDisconnect(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - osalSysLock(); - osalDbgAssert((lunp->state == BLK_ACTIVE) || (lunp->state == BLK_READY), - "invalid state"); - if (lunp->state == BLK_ACTIVE) { - osalSysUnlock(); - return HAL_SUCCESS; - } - lunp->state = BLK_DISCONNECTING; - osalSysUnlock(); - - //TODO: complete - - osalSysLock(); - lunp->state = BLK_ACTIVE; - osalSysUnlock(); - return HAL_SUCCESS; -} - -bool usbhmsdLUNRead(USBHMassStorageLUNDriver *lunp, uint32_t startblk, - uint8_t *buffer, uint32_t n) { - - osalDbgCheck(lunp != NULL); - bool ret = HAL_FAILED; - uint16_t blocks; - msd_result_t res; - - osalSysLock(); - if (lunp->state != BLK_READY) { - osalSysUnlock(); - return ret; - } - lunp->state = BLK_READING; - osalSysUnlock(); - - osalMutexLock(&lunp->msdp->mtx); - while (n) { - if (n > 0xffff) { - blocks = 0xffff; - } else { - blocks = (uint16_t)n; - } - res = scsi_read10(lunp, startblk, blocks, buffer); - if (res.tres != MSD_TRANSACTIONRESULT_OK) { - uerr("\tREAD (10): Transaction error"); - goto exit; - } else if (res.cres == MSD_COMMANDRESULT_FAILED) { - //TODO: request sense, and act appropriately - uerr("\tREAD (10): Command Failed"); - _requestsense(lunp); - goto exit; - } else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) { - //TODO: Do reset, etc. - uerr("\tREAD (10): Command Phase Error"); - goto exit; - } - n -= blocks; - startblk += blocks; - buffer += blocks * lunp->info.blk_size; - } - - ret = HAL_SUCCESS; - -exit: - osalMutexUnlock(&lunp->msdp->mtx); - osalSysLock(); - if (lunp->state == BLK_READING) { - lunp->state = BLK_READY; - } else { - osalDbgCheck(lunp->state == BLK_STOP); - uwarn("MSD: State = BLK_STOP"); - } - osalSysUnlock(); - return ret; -} - -bool usbhmsdLUNWrite(USBHMassStorageLUNDriver *lunp, uint32_t startblk, - const uint8_t *buffer, uint32_t n) { - - osalDbgCheck(lunp != NULL); - bool ret = HAL_FAILED; - uint16_t blocks; - msd_result_t res; - - osalSysLock(); - if (lunp->state != BLK_READY) { - osalSysUnlock(); - return ret; - } - lunp->state = BLK_WRITING; - osalSysUnlock(); - - osalMutexLock(&lunp->msdp->mtx); - while (n) { - if (n > 0xffff) { - blocks = 0xffff; - } else { - blocks = (uint16_t)n; - } - res = scsi_write10(lunp, startblk, blocks, buffer); - if (res.tres != MSD_TRANSACTIONRESULT_OK) { - uerr("\tWRITE (10): Transaction error"); - goto exit; - } else if (res.cres == MSD_COMMANDRESULT_FAILED) { - //TODO: request sense, and act appropriately - uerr("\tWRITE (10): Command Failed"); - _requestsense(lunp); - goto exit; - } else if (res.cres == MSD_COMMANDRESULT_PHASE_ERROR) { - //TODO: Do reset, etc. - uerr("\tWRITE (10): Command Phase Error"); - goto exit; - } - n -= blocks; - startblk += blocks; - buffer += blocks * lunp->info.blk_size; - } - - ret = HAL_SUCCESS; - -exit: - osalMutexUnlock(&lunp->msdp->mtx); - osalSysLock(); - if (lunp->state == BLK_WRITING) { - lunp->state = BLK_READY; - } else { - osalDbgCheck(lunp->state == BLK_STOP); - uwarn("MSD: State = BLK_STOP"); - } - osalSysUnlock(); - return ret; -} - -bool usbhmsdLUNSync(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - (void)lunp; - //TODO: Do SCSI Sync - return HAL_SUCCESS; -} - -bool usbhmsdLUNGetInfo(USBHMassStorageLUNDriver *lunp, BlockDeviceInfo *bdip) { - osalDbgCheck(lunp != NULL); - osalDbgCheck(bdip != NULL); - *bdip = lunp->info; - return HAL_SUCCESS; -} - -bool usbhmsdLUNIsInserted(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - blkstate_t state; - osalSysLock(); - state = lunp->state; - osalSysUnlock(); - return (state >= BLK_ACTIVE); -} - -bool usbhmsdLUNIsProtected(USBHMassStorageLUNDriver *lunp) { - osalDbgCheck(lunp != NULL); - return FALSE; -} - -void usbhmsdObjectInit(USBHMassStorageDriver *msdp) { - osalDbgCheck(msdp != NULL); - memset(msdp, 0, sizeof(*msdp)); - msdp->info = &usbhmsdClassDriverInfo; - osalMutexObjectInit(&msdp->mtx); -} - -#endif diff --git a/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_uvc.c b/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_uvc.c deleted file mode 100644 index 09a0f1d..0000000 --- a/ChibiOS_16.1.5/community/os/hal/src/usbh/hal_usbh_uvc.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - Copyright (C) 2015 Diego Ismirlian, TISA, (dismirlian (at) google's mail) - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" -#include "hal_usbh.h" - -#if HAL_USBH_USE_UVC - -#if !HAL_USE_USBH -#error "USBHUVC needs HAL_USE_USBH" -#endif - -#if !HAL_USBH_USE_IAD -#error "USBHUVC needs HAL_USBH_USE_IAD" -#endif - -#if USBHUVC_DEBUG_ENABLE_TRACE -#define udbgf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define udbg(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define udbgf(f, ...) do {} while(0) -#define udbg(f, ...) do {} while(0) -#endif - -#if USBHUVC_DEBUG_ENABLE_INFO -#define uinfof(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uinfo(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uinfof(f, ...) do {} while(0) -#define uinfo(f, ...) do {} while(0) -#endif - -#if USBHUVC_DEBUG_ENABLE_WARNINGS -#define uwarnf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uwarn(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uwarnf(f, ...) do {} while(0) -#define uwarn(f, ...) do {} while(0) -#endif - -#if USBHUVC_DEBUG_ENABLE_ERRORS -#define uerrf(f, ...) usbDbgPrintf(f, ##__VA_ARGS__) -#define uerr(f, ...) usbDbgPuts(f, ##__VA_ARGS__) -#else -#define uerrf(f, ...) do {} while(0) -#define uerr(f, ...) do {} while(0) -#endif - - -static usbh_baseclassdriver_t *uvc_load(usbh_device_t *dev, - const uint8_t *descriptor, uint16_t rem); -static void uvc_unload(usbh_baseclassdriver_t *drv); - -static const usbh_classdriver_vmt_t class_driver_vmt = { - uvc_load, - uvc_unload -}; -const usbh_classdriverinfo_t usbhuvcClassDriverInfo = { - 0x0e, 0x03, 0x00, "UVC", &class_driver_vmt -}; - - -static usbh_baseclassdriver_t *uvc_load(usbh_device_t *dev, const uint8_t *descriptor, uint16_t rem) { - (void)dev; - (void)descriptor; - (void)rem; - return NULL; -} - -static void uvc_unload(usbh_baseclassdriver_t *drv) { - (void)drv; -} - -#endif - |