From 7772ea4579a45bcf63ebd5e68be66ba1a9c72dfa Mon Sep 17 00:00:00 2001 From: Clyne Sullivan Date: Fri, 11 Nov 2016 15:02:17 -0500 Subject: chibios! --- .../STM32/STM32F4xx/IRQ_STORM_FPU/.cproject | 50 + .../testhal/STM32/STM32F4xx/IRQ_STORM_FPU/.project | 38 + .../testhal/STM32/STM32F4xx/IRQ_STORM_FPU/Makefile | 216 ++ .../testhal/STM32/STM32F4xx/IRQ_STORM_FPU/chconf.h | 499 ++++ ...x-IRQ_STORM_FPU (OpenOCD, Flash and Run).launch | 52 + .../STM32/STM32F4xx/IRQ_STORM_FPU/extfunc.c | 23 + .../STM32/STM32F4xx/IRQ_STORM_FPU/halconf.h | 381 +++ .../STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.ewp | 2511 ++++++++++++++++++++ .../STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.eww | 10 + .../STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.icf | 39 + .../STM32/STM32F4xx/IRQ_STORM_FPU/keil/ch.uvproj | 641 +++++ .../testhal/STM32/STM32F4xx/IRQ_STORM_FPU/main.c | 339 +++ .../STM32/STM32F4xx/IRQ_STORM_FPU/mcuconf.h | 342 +++ .../STM32/STM32F4xx/IRQ_STORM_FPU/readme.txt | 30 + 14 files changed, 5171 insertions(+) create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/.cproject create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/.project create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/Makefile create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/chconf.h create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/debug/STM32F4xx-IRQ_STORM_FPU (OpenOCD, Flash and Run).launch create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/extfunc.c create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/halconf.h create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.ewp create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.eww create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.icf create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/keil/ch.uvproj create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/main.c create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/mcuconf.h create mode 100644 ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/readme.txt (limited to 'ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU') diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/.cproject b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/.cproject new file mode 100644 index 0000000..0a482c4 --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/.cproject @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/.project b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/.project new file mode 100644 index 0000000..d2e79b4 --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/.project @@ -0,0 +1,38 @@ + + + STM32F4xx-IRQ_STORM_FPU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/os/hal/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/Makefile b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/Makefile new file mode 100644 index 0000000..94149f7 --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/Makefile @@ -0,0 +1,216 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = hard +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../.. +# Startup files. +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +#include $(CHIBIOS)/test/rt/test.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32F407xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + extfunc.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/chconf.h b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/chconf.h new file mode 100644 index 0000000..7d99062 --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/chconf.h @@ -0,0 +1,499 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_QUEUES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_TRACE FALSE + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/debug/STM32F4xx-IRQ_STORM_FPU (OpenOCD, Flash and Run).launch b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/debug/STM32F4xx-IRQ_STORM_FPU (OpenOCD, Flash and Run).launch new file mode 100644 index 0000000..198b953 --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/debug/STM32F4xx-IRQ_STORM_FPU (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/extfunc.c b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/extfunc.c new file mode 100644 index 0000000..309c24c --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/extfunc.c @@ -0,0 +1,23 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +float ff1(float par) { + return par; +} + +float ff2(float par1, float par2, float par3, float par4) { + return (par1 + par2) * (par3 + par4); +} diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/halconf.h b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/halconf.h new file mode 100644 index 0000000..5bd3910 --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/halconf.h @@ -0,0 +1,381 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.ewp b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.ewp new file mode 100644 index 0000000..98ed089 --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.ewp @@ -0,0 +1,2511 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + os + + hal + + board + + $PROJ_DIR$\..\..\..\..\..\os\hal\boards\ST_STM32F4_DISCOVERY\board.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\boards\ST_STM32F4_DISCOVERY\board.h + + + + include + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\adc.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\can.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\dac.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\ext.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\gpt.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\hal.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\hal_channels.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\hal_files.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\hal_ioblock.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\hal_mmcsd.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\hal_queues.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\hal_streams.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\i2c.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\i2s.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\icu.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\sdc.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\serial_usb.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\st.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\tm.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\uart.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\include\usb_cdc.h + + + + osal + + $PROJ_DIR$\..\..\..\..\..\os\hal\osal\rt\osal.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\osal\rt\osal.h + + + + port + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\STM32F4xx\adc_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\STM32F4xx\adc_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\can_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\can_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\ext_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\ext_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\STM32F4xx\ext_lld_isr.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\STM32F4xx\ext_lld_isr.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\gpt_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\gpt_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\STM32F4xx\hal_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\STM32F4xx\hal_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\I2Cv1\i2c_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\I2Cv1\i2c_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\SPIv1\i2s_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\SPIv1\i2s_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\icu_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\icu_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\mac_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\mac_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\common\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\common\ARMCMx\nvic.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\GPIOv2\pal_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\GPIOv2\pal_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\pwm_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\pwm_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\RTCv2\rtc_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\RTCv2\rtc_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\sdc_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\sdc_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\USARTv1\serial_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\USARTv1\serial_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\SPIv1\spi_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\SPIv1\spi_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\st_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\st_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\STM32F4xx\stm32_dma.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\STM32F4xx\stm32_dma.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\STM32F4xx\stm32_isr.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\OTGv1\stm32_otg.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\STM32F4xx\stm32_rcc.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\STM32F4xx\stm32_registry.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\stm32_tim.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\USARTv1\uart_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\USARTv1\uart_lld.h + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\OTGv1\usb_lld.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\ports\STM32\LLD\OTGv1\usb_lld.h + + + + src + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\dac.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\gpt.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\hal_mmcsd.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\hal_queues.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\i2s.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\icu.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\sdc.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\serial_usb.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\st.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\uart.c + + + $PROJ_DIR$\..\..\..\..\..\os\hal\src\usb.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\ch.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chbsem.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chcond.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chdebug.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chevents.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chheap.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chlicense.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chmempools.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chmsg.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chmtx.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chqueues.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chregistry.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chschd.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chsem.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chstats.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chstreams.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chsys.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chsystypes.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chthreads.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chtm.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\include\chvt.h + + + + port + + $PROJ_DIR$\..\..\..\..\..\os\rt\ports\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\ports\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\ports\ARMCMx\chcore_timer.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\ports\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\ports\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\..\..\..\os\rt\ports\ARMCMx\compilers\IAR\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\..\..\..\os\rt\ports\ARMCMx\compilers\IAR\chtypes.h + + + + src + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chcond.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chdebug.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chevents.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chheap.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chmempools.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chmsg.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chmtx.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chqueues.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chregistry.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chschd.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chsem.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chstats.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chsys.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chthreads.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chtm.c + + + $PROJ_DIR$\..\..\..\..\..\os\rt\src\chvt.c + + + + + startup + + $PROJ_DIR$\..\..\..\..\..\os\common\ports\ARMCMx\compilers\IAR\cstartup.s + + + $PROJ_DIR$\..\..\..\..\..\os\common\ports\ARMCMx\compilers\IAR\vectors.s + + + + + test + + $PROJ_DIR$\..\..\..\..\..\test\rt\test.c + + + $PROJ_DIR$\..\..\..\..\..\test\rt\test.h + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testbmk.c + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testbmk.h + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testdyn.c + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testdyn.h + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testevt.c + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testevt.h + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testheap.c + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testheap.h + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testmbox.c + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testmbox.h + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testmsg.c + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testmsg.h + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testmtx.c + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testmtx.h + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testpools.c + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testpools.h + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testqueues.c + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testqueues.h + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testsem.c + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testsem.h + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testthd.c + + + $PROJ_DIR$\..\..\..\..\..\test\rt\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\extfunc.c + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.eww b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.eww new file mode 100644 index 0000000..f9b3b20 --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.icf b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.icf new file mode 100644 index 0000000..c0a51f4 --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x400; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; +define block SYSHEAP with alignment = 8 {section SYSHEAP}; +define block DATABSS with alignment = 8 {readwrite, zeroinit}; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; +place in ROM_region {readonly}; +place at start of RAM_region {block IRQSTACK}; +place in RAM_region {block DATABSS, block HEAP}; +place in RAM_region {block SYSHEAP}; +place at end of RAM_region {block CSTACK}; diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/keil/ch.uvproj b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/keil/ch.uvproj new file mode 100644 index 0000000..131d511 --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/keil/ch.uvproj @@ -0,0 +1,641 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f4xx.s" ("STM32F4xx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6103 + stm32f4xx.h + + + + + + + + + + SFD\ST\STM32F4xx\STM32F4xx.sfr + 0 + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + STLink\ST-LINKIII-KEIL.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20020000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --c99 -USTM32F40_41xxx + __heap_base__=Image$$$$RW_IRAM1$$$$ZI$$$$Limit __heap_end__=Image$$$$RW_IRAM2$$$$Base + + ..\;..\..\..\..\..\os\common\ports\ARMCMx\devices\STM32F4xx;..\..\..\..\..\os\ext\CMSIS\include;..\..\..\..\..\os\ext\CMSIS\ST;..\..\..\..\..\os\rt\ports\ARMCMx;..\..\..\..\..\os\rt\ports\ARMCMx\compilers\RVCT;..\..\..\..\..\os\rt\include;..\..\..\..\..\os\hal\osal\rt;..\..\..\..\..\os\hal\include;..\..\..\..\..\os\hal\boards\ST_STM32F4_DISCOVERY;..\..\..\..\..\os\hal\ports\common\ARMCMx;..\..\..\..\..\os\hal\ports\STM32\STM32F4xx;..\..\..\..\..\os\hal\ports\STM32\LLD;..\..\..\..\..\os\hal\ports\STM32\LLD\GPIOv2;..\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1;..\..\..\..\..\os\hal\ports\STM32\LLD\USARTv1 + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\;..\..\..\..\..\os\common\ports\ARMCMx\devices\STM32F4xx;..\..\..\..\..\os\rt\ports\ARMCMx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\..\..\os\hal\boards\ST_STM32F4_DISCOVERY\board.c + + + + + port + + + vectors.s + 2 + ..\..\..\..\..\os\common\ports\ARMCMx\compilers\RVCT\vectors.s + + + cstartup.s + 2 + ..\..\..\..\..\os\common\ports\ARMCMx\compilers\RVCT\cstartup.s + + + chcore.c + 1 + ..\..\..\..\..\os\rt\ports\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\..\..\os\rt\ports\ARMCMx\chcore_v7m.c + + + chcoreasm_v7m.s + 2 + ..\..\..\..\..\os\rt\ports\ARMCMx\compilers\RVCT\chcoreasm_v7m.s + + + + + kernel + + + chvt.c + 1 + ..\..\..\..\..\os\rt\src\chvt.c + + + chcond.c + 1 + ..\..\..\..\..\os\rt\src\chcond.c + + + chdebug.c + 1 + ..\..\..\..\..\os\rt\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\..\..\os\rt\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\..\..\os\rt\src\chevents.c + + + chheap.c + 1 + ..\..\..\..\..\os\rt\src\chheap.c + + + chmboxes.c + 1 + ..\..\..\..\..\os\rt\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\..\..\os\rt\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\..\..\os\rt\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\..\..\os\rt\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\..\..\os\rt\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\..\..\os\rt\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\..\..\os\rt\src\chregistry.c + + + chschd.c + 1 + ..\..\..\..\..\os\rt\src\chschd.c + + + chsem.c + 1 + ..\..\..\..\..\os\rt\src\chsem.c + + + chstats.c + 1 + ..\..\..\..\..\os\rt\src\chstats.c + + + chsys.c + 1 + ..\..\..\..\..\os\rt\src\chsys.c + + + chthreads.c + 1 + ..\..\..\..\..\os\rt\src\chthreads.c + + + chtm.c + 1 + ..\..\..\..\..\os\rt\src\chtm.c + + + + + hal + + + serial.c + 1 + ..\..\..\..\..\os\hal\src\serial.c + + + gpt.c + 1 + ..\..\..\..\..\os\hal\src\gpt.c + + + hal.c + 1 + ..\..\..\..\..\os\hal\src\hal.c + + + st.c + 1 + ..\..\..\..\..\os\hal\src\st.c + + + + + platform + + + hal_lld.c + 1 + ..\..\..\..\..\os\hal\ports\STM32\STM32F4xx\hal_lld.c + + + pal_lld.c + 1 + ..\..\..\..\..\os\hal\ports\STM32\LLD\GPIOv2\pal_lld.c + + + gpt_lld.c + 1 + ..\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\gpt_lld.c + + + serial_lld.c + 1 + ..\..\..\..\..\os\hal\ports\STM32\LLD\USARTv1\serial_lld.c + + + st_lld.c + 1 + ..\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\st_lld.c + + + nvic.c + 1 + ..\..\..\..\..\os\hal\ports\common\ARMCMx\nvic.c + + + + + demo + + + main.c + 1 + ..\main.c + + + mcuconf.h + 5 + ..\mcuconf.h + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + extfunc.c + 1 + ..\extfunc.c + + + + + + + + diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/main.c b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/main.c new file mode 100644 index 0000000..37e3793 --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/main.c @@ -0,0 +1,339 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +float ff1(float par); + +float ff2(float par1, float par2, float par3, float par4); + +/*===========================================================================*/ +/* Configurable settings. */ +/*===========================================================================*/ + +#ifndef RANDOMIZE +#define RANDOMIZE FALSE +#endif + +#ifndef ITERATIONS +#define ITERATIONS 100 +#endif + +/*===========================================================================*/ +/* Test related code. */ +/*===========================================================================*/ + +static bool saturated; + +/* + * Test worker thread. + */ +static THD_WORKING_AREA(waWorkerThread, 128); +static THD_FUNCTION(WorkerThread, arg) { + + (void)arg; + + while(1) { + float f1, f2, f3, f4, f5; + + f1 = ff1(3.0f); + f2 = ff1(4.0f); + f3 = ff1(5.0f); + f5 = f1 + f2 + f3; + f4 = ff1(6.0f); + f5 = ff2(f5, f4, f5, f4); + if (f5 != 324.0f) + chSysHalt("float corrupion #1"); + } +} + +/* + * Test periodic thread. + */ +static THD_WORKING_AREA(waPeriodicThread, 128); +static THD_FUNCTION(PeriodicThread, arg) { + + (void)arg; + + while(1) { + float f1, f2, f3, f4, f5; + + f1 = ff1(4.0f); + f2 = ff1(5.0f); + f3 = ff1(6.0f); + f5 = f1 + f2 + f3; + f4 = ff1(7.0f); + f5 = ff2(f5, f4, f5, f4); + if (f5 != 484.0f) + chSysHalt("float corrupion #2"); + chThdSleepSeconds(1); + } +} + +/* + * GPT2 callback. + */ +static void gpt4cb(GPTDriver *gptp) { + float f1, f2, f3, f4, f5; + + (void)gptp; + + f1 = ff1(2.0f); + f2 = ff1(3.0f); + f3 = ff1(4.0f); + f5 = f1 + f2 + f3; + f4 = ff1(5.0f); + f5 = ff2(f5, f4, f5, f4); + if (f5 != 196.0f) + chSysHalt("float corrupion #3"); +} + +/* + * GPT3 callback. + */ +static void gpt3cb(GPTDriver *gptp) { + float f1, f2, f3, f4, f5; + + (void)gptp; + + f1 = ff1(1.0f); + f2 = ff1(2.0f); + f3 = ff1(3.0f); + f5 = f1 + f2 + f3; + f4 = ff1(4.0f); + f5 = ff2(f5, f4, f5, f4); + if (f5 != 100.0f) + chSysHalt("float corrupion #4"); +} + +/* + * GPT4 configuration. + */ +static const GPTConfig gpt4cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt4cb, /* Timer callback.*/ + 0, + 0 +}; + +/* + * GPT3 configuration. + */ +static const GPTConfig gpt3cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt3cb, /* Timer callback.*/ + 0, + 0 +}; + +CH_FAST_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { + float f1, f2, f3, f4, f5; + + TIM1->SR = 0; + + f1 = ff1(3.0f); + f2 = ff1(4.0f); + f3 = ff1(5.0f); + f5 = f1 + f2 + f3; + f4 = ff1(4.0f); + f5 = ff2(f5, f4, f5, f4); + if (f5 != 256.0f) { + chSysHalt("float corrupion #5"); + } +} + +/*===========================================================================*/ +/* Generic demo code. */ +/*===========================================================================*/ + +CH_FAST_IRQ_HANDLER(Vector184) { + + while (1) + ; +} + +static void print(char *p) { + + while (*p) { + chSequentialStreamPut(&SD2, *p++); + } +} + +static void println(char *p) { + + while (*p) { + chSequentialStreamPut(&SD2, *p++); + } + chSequentialStreamWrite(&SD2, (uint8_t *)"\r\n", 2); +} + +static void printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chSequentialStreamPut(&SD2, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chSequentialStreamPut(&SD2, *--p); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + gptcnt_t interval, threshold, worst; + + /* Enables FPU exceptions.*/ + nvicEnableVector(FPU_IRQn, 1); + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepares the Serial driver 2 and GPT drivers 4 and 3. + */ + sdStart(&SD2, NULL); /* Default is 38400-8-N-1.*/ + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); + gptStart(&GPTD4, &gpt4cfg); + gptStart(&GPTD3, &gpt3cfg); + + /* + * Enabling TIM1 as a fast interrupts source. + */ + rccEnableTIM1(false); + nvicEnableVector(STM32_TIM1_UP_NUMBER, 0); + TIM1->ARR = 10000; + TIM1->PSC = 0; + TIM1->CNT = 0; + TIM1->DIER = TIM_DIER_UIE; + TIM1->CR1 = TIM_CR1_CEN; + + /* + * Initializes the worker threads. + */ + chThdCreateStatic(waWorkerThread, sizeof waWorkerThread, + NORMALPRIO - 20, WorkerThread, NULL); + chThdCreateStatic(waPeriodicThread, sizeof waPeriodicThread, + NORMALPRIO - 10, PeriodicThread, NULL); + + /* + * Test procedure. + */ + println(""); + println("*** ChibiOS/RT IRQ-STORM-FPU long duration test"); + println("***"); + print("*** Kernel: "); + println(CH_KERNEL_VERSION); + print("*** Compiled: "); + println(__DATE__ " - " __TIME__); +#ifdef PORT_COMPILER_NAME + print("*** Compiler: "); + println(PORT_COMPILER_NAME); +#endif + print("*** Architecture: "); + println(PORT_ARCHITECTURE_NAME); +#ifdef PORT_CORE_VARIANT_NAME + print("*** Core Variant: "); + println(PORT_CORE_VARIANT_NAME); +#endif +#ifdef PORT_INFO + print("*** Port Info: "); + println(PORT_INFO); +#endif +#ifdef PLATFORM_NAME + print("*** Platform: "); + println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + print("*** Test Board: "); + println(BOARD_NAME); +#endif + println("***"); + print("*** System Clock: "); + printn(STM32_SYSCLK); + println(""); + print("*** Iterations: "); + printn(ITERATIONS); + println(""); + print("*** Randomize: "); + printn(RANDOMIZE); + println(""); + + println(""); + worst = 0; + for (i = 1; i <= ITERATIONS; i++){ + print("Iteration "); + printn(i); + println(""); + saturated = FALSE; + threshold = 0; + for (interval = 2000; interval >= 10; interval -= interval / 10) { + gptStartContinuous(&GPTD4, interval - 1); /* Slightly out of phase.*/ + gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/ + chThdSleepMilliseconds(1000); + gptStopTimer(&GPTD4); + gptStopTimer(&GPTD3); + if (!saturated) + print("."); + else { + print("#"); + if (threshold == 0) + threshold = interval; + } + } + /* Gives the worker threads a chance to empty the mailboxes before next + cycle.*/ + chThdSleepMilliseconds(20); + println(""); + print("Saturated at "); + printn(threshold); + println(" uS"); + println(""); + if (threshold > worst) + worst = threshold; + } + gptStopTimer(&GPTD4); + gptStopTimer(&GPTD3); + + print("Worst case at "); + printn(worst); + println(" uS"); + println(""); + println("Test Complete"); + + /* + * Normal main() thread activity, nothing in this test. + */ + while (true) { + chThdSleepMilliseconds(5000); + } +} diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/mcuconf.h b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/mcuconf.h new file mode 100644 index 0000000..aad4536 --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/mcuconf.h @@ -0,0 +1,342 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 10 +#define STM32_GPT_TIM4_IRQ_PRIORITY 6 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* _MCUCONF_H_ */ diff --git a/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/readme.txt b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/readme.txt new file mode 100644 index 0000000..f110c5e --- /dev/null +++ b/ChibiOS_16.1.5/testhal/STM32/STM32F4xx/IRQ_STORM_FPU/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/HAL - IRQ_STORM_FPU stress test demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx GPT, PAL and Serial +drivers in order to implement a system stress demo involving the FPU. + +** Board Setup ** + +None. + +** Build Procedure ** + +The demo has been tested using YAGARTO 4.6.2. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3