toggle gpio

build.zig

@@ -3,6 +3,7 @@ const std = @import("std");
 pub fn build(b: *std.Build) void {
     const target = b.resolveTargetQuery(.{
         .cpu_arch = .thumb,
+        .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 },
         .os_tag = .freestanding,
         .abi = .none
     });

src/bootstrap.s

@@ -23,7 +23,7 @@ fault5:
     b fault_handler
 
 .section .bss
-.skip 128
+.skip 2048
 stack_top:
 
 .section .isr_vector

src/main.zig

@@ -3,8 +3,44 @@
 //! is to delete this file and start with root.zig instead.
 //const std = @import("std");
 
+const gpio = packed struct {
+    moder: u32,
+    otyper: u32,
+    ospeedr: u32,
+    pupdr: u32,
+    idr: u32,
+    odr: u32,
+    bsrr: u32,
+    lckr: u32,
+    afrl: u32,
+    afrh: u32,
+    brr: u32,
+    ascr: u32,
+};
+
+const cpu = struct {
+    pub fn interrupt_disable() void {
+        asm volatile("cpsid i");
+    }
+
+    pub fn interrupt_enable() void {
+        asm volatile("cpsie i");
+    }
+};
+
+const gpioa: *gpio = @ptrFromInt(0x48000000);
+const rcc: *[39]u32 = @ptrFromInt(0x40021000);
+
 export fn _start() callconv(.C) noreturn {
-    while (true) {}
+    cpu.interrupt_disable();
+
+    rcc[19] |= 1; // gpioaen
+    gpioa.moder &= ~@as(u32, 0x3 << (5 * 2));
+    gpioa.moder |= (1 << (5 * 2));
+
+    while (true) {
+        gpioa.odr ^= (1 << 5);
+    }
 }
 
 export fn fault_handler() callconv(.C) void {