diff options
| author | Clyne Sullivan <clyne@bitgloo.com> | 2023-10-14 19:17:59 -0400 |
|---|---|---|
| committer | Clyne Sullivan <clyne@bitgloo.com> | 2023-10-14 19:17:59 -0400 |
| commit | 3d7a45e5cddc94d7bd5a3433a561f16fdb5e18a0 (patch) | |
| tree | 341b4ac9279a250bd5f807a62d27fa16c48d761e /msp430/alee-msp430.cpp | |
| parent | 5991370657b48f5b44fbcc7877a7c26acf07d99e (diff) | |
msp430.fth
Diffstat (limited to 'msp430/alee-msp430.cpp')
| -rw-r--r-- | msp430/alee-msp430.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/msp430/alee-msp430.cpp b/msp430/alee-msp430.cpp index 3d660a7..6328419 100644 --- a/msp430/alee-msp430.cpp +++ b/msp430/alee-msp430.cpp @@ -36,15 +36,15 @@ int main() { WDTCTL = WDTPW | WDTHOLD; DCOCTL = 0; - BCSCTL1 = CALBC1_1MHZ; - DCOCTL = CALDCO_1MHZ; + BCSCTL1 = CALBC1_16MHZ; + DCOCTL = CALDCO_16MHZ; P1SEL |= BIT1 | BIT2; P1SEL2 |= BIT1 | BIT2; UCA0CTL1 = UCSWRST; UCA0CTL1 |= UCSSEL_2; - UCA0BR0 = 104; + UCA0BR0 = 139; UCA0BR1 = 0; UCA0MCTL = UCBRS0; UCA0CTL1 &= (uint8_t)~UCSWRST; |