initial commit

* combine all source files into this monorepo

* convert all third-party source packages into submodules

* small fixes due to changes in latest third-part packages

47 files changed, 9617 insertions, 0 deletions

diff --git a/firmware/ChibiOS b/firmware/ChibiOS
new file mode 160000
+Subproject dd0783ca6f450486a96deadb98b6df01d6bb6e8
diff --git a/firmware/LICENSE b/firmware/LICENSE
new file mode 100644
index 0000000..6a34f51
--- /dev/null
+++ b/firmware/LICENSE
@@ -0,0 +1,620 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
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+OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
+IS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
+ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+  16. Limitation of Liability.
+
+  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
+THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
+GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
+USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
+DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
+PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
+EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGES.
+
+  17. Interpretation of Sections 15 and 16.
+
+  If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
diff --git a/firmware/Makefile b/firmware/Makefile
new file mode 100644
index 0000000..0db249b
--- /dev/null
+++ b/firmware/Makefile
@@ -0,0 +1,222 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Set the target platform, either L4, G4, or H7
+TARGET_PLATFORM = L4
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+  USE_OPT = -O0 -g3 -ggdb -fomit-frame-pointer -falign-functions=16 --specs=nosys.specs
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+  USE_COPT = 
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+  USE_CPPOPT = -std=c++2a -fno-rtti -fno-exceptions
+endif
+
+# Enable this if you want the linker to remove unused code and data.
+ifeq ($(USE_LINK_GC),)
+  USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+#  USE_LDOPT = -L.,-lzig
+endif
+
+# Enable this if you want link time optimizations (LTO).
+ifeq ($(USE_LTO),)
+  USE_LTO = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+  USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+  USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+  USE_PROCESS_STACKSIZE = 1024
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+  USE_EXCEPTIONS_STACKSIZE = 2048
+endif
+
+# Enables the use of FPU (no, softfp, hard).
+ifeq ($(USE_FPU),)
+  USE_FPU = hard
+endif
+
+# FPU-related options.
+ifeq ($(USE_FPU_OPT),)
+ifeq ($(TARGET_PLATFORM),H7)
+  USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-d16
+endif
+ifeq ($(TARGET_PLATFORM),L4)
+  USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16
+endif
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, target, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Target settings.
+ifeq ($(TARGET_PLATFORM),H7)
+  MCU = cortex-m7
+else
+  MCU = cortex-m4
+endif
+
+# Imported source files and paths.
+CHIBIOS  := ./ChibiOS
+CONFDIR  := ./source/cfg
+BUILDDIR := ./build
+DEPDIR   := ./.dep
+
+# Licensing files.
+include $(CHIBIOS)/os/license/license.mk
+# Startup files.
+ifeq ($(TARGET_PLATFORM),H7)
+  include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk
+else
+  include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk
+endif
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+ifeq ($(TARGET_PLATFORM),H7)
+  include $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/platform.mk
+else
+  include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk
+endif
+include ./source/board/board.mk
+include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+# Auto-build files in ./source recursively.
+#include $(CHIBIOS)/tools/mk/autobuild.mk
+ALLCSRC += $(wildcard source/*.c) $(wildcard source/periph/*.c)
+ALLCPPSRC += $(wildcard source/*.cpp) $(wildcard source/periph/*.cpp)
+ALLASMSRC += $(wildcard source/*.s)
+# Other files (optional).
+#include $(CHIBIOS)/test/lib/test.mk
+#include $(CHIBIOS)/test/rt/rt_test.mk
+#include $(CHIBIOS)/test/oslib/oslib_test.mk
+
+# Define linker script file here
+ifeq ($(TARGET_PLATFORM),H7)
+  LDSCRIPT = source/ld/STM32H723xG.ld
+else
+  LDSCRIPT = source/ld/STM32L476xG.ld
+endif
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(ALLCSRC)
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC = $(ALLCPPSRC)
+
+# List ASM source files here.
+ASMSRC = $(ALLASMSRC)
+
+# List ASM with preprocessor source files here.
+ASMXSRC = $(ALLXASMSRC)
+
+# Inclusion directories.
+INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) \
+         source source/periph
+
+# Define C warning options here.
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -pedantic
+
+# Define C++ warning options here.
+CPPWARN = -Wall -Wextra -Wundef -pedantic -Wno-volatile
+
+#
+# Project, target, sources and paths
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS = -DCORTEX_ENABLE_WFI_IDLE=TRUE \
+        -DPORT_USE_SYSCALL=TRUE \
+        -DPORT_USE_GUARD_MPU_REGION=MPU_REGION_0 \
+        -DTARGET_PLATFORM_$(TARGET_PLATFORM)
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ifeq ($(TARGET_PLATFORM),L4)
+  ULIBS = -lm
+else
+  ULIBS =
+endif
+
+#
+# End of user section
+##############################################################################
+
+##############################################################################
+# Common rules
+#
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
+include $(RULESPATH)/arm-none-eabi.mk
+include $(RULESPATH)/rules.mk
+
+#
+# Common rules
+##############################################################################
+
+##############################################################################
+# Custom rules
+#
+
+#
+# Custom rules
+##############################################################################
diff --git a/firmware/openocd.cfg b/firmware/openocd.cfg
new file mode 100644
index 0000000..47e6c7d
--- /dev/null
+++ b/firmware/openocd.cfg
@@ -0,0 +1,3 @@
+source [find interface/stlink.cfg]
+source [find target/stm32l4x.cfg]
+
diff --git a/firmware/source/board/board.mk b/firmware/source/board/board.mk
new file mode 100644
index 0000000..155285a
--- /dev/null
+++ b/firmware/source/board/board.mk
@@ -0,0 +1,17 @@
+# List of all the board related files.

+ifeq ($(TARGET_PLATFORM),H7)

+  BOARDSRC = ./source/board/board_h7.c

+else

+  BOARDSRC = ./source/board/board_l4.c

+endif

+

+# Required include directories

+ifeq ($(TARGET_PLATFORM),H7)

+  BOARDINC = ./source/board/h7

+else

+  BOARDINC = ./source/board/l4

+endif

+

+# Shared variables

+ALLCSRC += $(BOARDSRC)

+ALLINC  += $(BOARDINC)

diff --git a/firmware/source/board/board_h7.c b/firmware/source/board/board_h7.c
new file mode 100644
index 0000000..74285cf
--- /dev/null
+++ b/firmware/source/board/board_h7.c
@@ -0,0 +1,287 @@
+/*

+    ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/*

+ * This file has been automatically generated using ChibiStudio board

+ * generator plugin. Do not edit manually.

+ */

+

+#include "hal.h"

+#include "stm32_gpio.h"

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Type of STM32 GPIO port setup.

+ */

+typedef struct {

+  uint32_t              moder;

+  uint32_t              otyper;

+  uint32_t              ospeedr;

+  uint32_t              pupdr;

+  uint32_t              odr;

+  uint32_t              afrl;

+  uint32_t              afrh;

+} gpio_setup_t;

+

+/**

+ * @brief   Type of STM32 GPIO initialization data.

+ */

+typedef struct {

+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)

+  gpio_setup_t          PAData;

+#endif

+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)

+  gpio_setup_t          PBData;

+#endif

+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)

+  gpio_setup_t          PCData;

+#endif

+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)

+  gpio_setup_t          PDData;

+#endif

+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)

+  gpio_setup_t          PEData;

+#endif

+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)

+  gpio_setup_t          PFData;

+#endif

+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)

+  gpio_setup_t          PGData;

+#endif

+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)

+  gpio_setup_t          PHData;

+#endif

+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)

+  gpio_setup_t          PIData;

+#endif

+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)

+  gpio_setup_t          PJData;

+#endif

+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)

+  gpio_setup_t          PKData;

+#endif

+} gpio_config_t;

+

+/**

+ * @brief   STM32 GPIO static initialization data.

+ */

+static const gpio_config_t gpio_default_config = {

+#if STM32_HAS_GPIOA

+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,

+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},

+#endif

+#if STM32_HAS_GPIOB

+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,

+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},

+#endif

+#if STM32_HAS_GPIOC

+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,

+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},

+#endif

+#if STM32_HAS_GPIOD

+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,

+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},

+#endif

+#if STM32_HAS_GPIOE

+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,

+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},

+#endif

+#if STM32_HAS_GPIOF

+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,

+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},

+#endif

+#if STM32_HAS_GPIOG

+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,

+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},

+#endif

+#if STM32_HAS_GPIOH

+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,

+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},

+#endif

+#if STM32_HAS_GPIOI

+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,

+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH},

+#endif

+#if STM32_HAS_GPIOJ

+  {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,

+   VAL_GPIOJ_ODR,   VAL_GPIOJ_AFRL,   VAL_GPIOJ_AFRH},

+#endif

+#if STM32_HAS_GPIOK

+  {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,

+   VAL_GPIOK_ODR,   VAL_GPIOK_AFRL,   VAL_GPIOK_AFRH}

+#endif

+};

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {

+

+  gpiop->OTYPER  = config->otyper;

+  gpiop->OSPEEDR = config->ospeedr;

+  gpiop->PUPDR   = config->pupdr;

+  gpiop->ODR     = config->odr;

+  gpiop->AFRL    = config->afrl;

+  gpiop->AFRH    = config->afrh;

+  gpiop->MODER   = config->moder;

+}

+

+static void stm32_gpio_init(void) {

+

+  /* Enabling GPIO-related clocks, the mask comes from the

+     registry header file.*/

+  rccResetAHB4(STM32_GPIO_EN_MASK);

+  rccEnableAHB4(STM32_GPIO_EN_MASK, true);

+

+  /* Initializing all the defined GPIO ports.*/

+#if STM32_HAS_GPIOA

+  gpio_init(GPIOA, &gpio_default_config.PAData);

+#endif

+#if STM32_HAS_GPIOB

+  gpio_init(GPIOB, &gpio_default_config.PBData);

+#endif

+#if STM32_HAS_GPIOC

+  gpio_init(GPIOC, &gpio_default_config.PCData);

+#endif

+#if STM32_HAS_GPIOD

+  gpio_init(GPIOD, &gpio_default_config.PDData);

+#endif

+#if STM32_HAS_GPIOE

+  gpio_init(GPIOE, &gpio_default_config.PEData);

+#endif

+#if STM32_HAS_GPIOF

+  gpio_init(GPIOF, &gpio_default_config.PFData);

+#endif

+#if STM32_HAS_GPIOG

+  gpio_init(GPIOG, &gpio_default_config.PGData);

+#endif

+#if STM32_HAS_GPIOH

+  gpio_init(GPIOH, &gpio_default_config.PHData);

+#endif

+#if STM32_HAS_GPIOI

+  gpio_init(GPIOI, &gpio_default_config.PIData);

+#endif

+#if STM32_HAS_GPIOJ

+  gpio_init(GPIOJ, &gpio_default_config.PJData);

+#endif

+#if STM32_HAS_GPIOK

+  gpio_init(GPIOK, &gpio_default_config.PKData);

+#endif

+}

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Early initialization code.

+ * @details GPIO ports and system clocks are initialized before everything

+ *          else.

+ */

+void __early_init(void) {

+

+  stm32_gpio_init();

+  stm32_clock_init();

+}

+

+#if HAL_USE_SDC || defined(__DOXYGEN__)

+/**

+ * @brief   SDC card detection.

+ */

+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {

+

+  (void)sdcp;

+  /* CHTODO: Fill the implementation.*/

+  return true;

+}

+

+/**

+ * @brief   SDC card write protection detection.

+ */

+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {

+

+  (void)sdcp;

+  /* CHTODO: Fill the implementation.*/

+  return false;

+}

+#endif /* HAL_USE_SDC */

+

+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)

+/**

+ * @brief   MMC_SPI card detection.

+ */

+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {

+

+  (void)mmcp;

+  /* CHTODO: Fill the implementation.*/

+  return true;

+}

+

+/**

+ * @brief   MMC_SPI card write protection detection.

+ */

+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {

+

+  (void)mmcp;

+  /* CHTODO: Fill the implementation.*/

+  return false;

+}

+#endif

+

+/**

+ * @brief   Board-specific initialization code.

+ * @note    You can add your board-specific code here.

+ */

+void boardInit(void) {

+    // Enable the FPU (floating-point unit)

+    SCB->CPACR |= 0xF << 20;

+

+    // Setup the MPU (memory protection unit):

+    //     Region 2: Data for algorithm thread

+    //     Region 3: Code for algorithm thread

+    //     Region 4: User algorithm code

+    mpuConfigureRegion(MPU_REGION_2,

+                       0x20000000,

+                       MPU_RASR_ATTR_AP_RW_RW | MPU_RASR_ATTR_NON_CACHEABLE |

+                       MPU_RASR_SIZE_64K |

+                       MPU_RASR_ENABLE);

+    mpuConfigureRegion(MPU_REGION_3,

+                       0x0807F800,

+                       MPU_RASR_ATTR_AP_RO_RO | MPU_RASR_ATTR_NON_CACHEABLE |

+                       MPU_RASR_SIZE_2K |

+                       MPU_RASR_ENABLE);

+    mpuConfigureRegion(MPU_REGION_4,

+                       0x00000000,

+                       MPU_RASR_ATTR_AP_RW_RW | MPU_RASR_ATTR_NON_CACHEABLE |

+                       MPU_RASR_SIZE_64K |

+                       MPU_RASR_ENABLE);

+}

diff --git a/firmware/source/board/board_l4.c b/firmware/source/board/board_l4.c
new file mode 100644
index 0000000..55af697
--- /dev/null
+++ b/firmware/source/board/board_l4.c
@@ -0,0 +1,307 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/*

+ * This file has been automatically generated using ChibiStudio board

+ * generator plugin. Do not edit manually.

+ */

+

+#include "hal.h"

+#include "stm32_gpio.h"

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Type of STM32 GPIO port setup.

+ */

+typedef struct {

+  uint32_t              moder;

+  uint32_t              otyper;

+  uint32_t              ospeedr;

+  uint32_t              pupdr;

+  uint32_t              odr;

+  uint32_t              afrl;

+  uint32_t              afrh;

+  uint32_t              ascr;

+  uint32_t              lockr;

+} gpio_setup_t;

+

+/**

+ * @brief   Type of STM32 GPIO initialization data.

+ */

+typedef struct {

+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)

+  gpio_setup_t          PAData;

+#endif

+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)

+  gpio_setup_t          PBData;

+#endif

+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)

+  gpio_setup_t          PCData;

+#endif

+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)

+  gpio_setup_t          PDData;

+#endif

+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)

+  gpio_setup_t          PEData;

+#endif

+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)

+  gpio_setup_t          PFData;

+#endif

+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)

+  gpio_setup_t          PGData;

+#endif

+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)

+  gpio_setup_t          PHData;

+#endif

+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)

+  gpio_setup_t          PIData;

+#endif

+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)

+  gpio_setup_t          PJData;

+#endif

+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)

+  gpio_setup_t          PKData;

+#endif

+} gpio_config_t;

+

+/**

+ * @brief   STM32 GPIO static initialization data.

+ */

+static const gpio_config_t gpio_default_config = {

+#if STM32_HAS_GPIOA

+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,

+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH,    VAL_GPIOA_ASCR,

+   VAL_GPIOA_LOCKR},

+#endif

+#if STM32_HAS_GPIOB

+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,

+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH,    VAL_GPIOB_ASCR,

+   VAL_GPIOB_LOCKR},

+#endif

+#if STM32_HAS_GPIOC

+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,

+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH,    VAL_GPIOC_ASCR,

+   VAL_GPIOC_LOCKR},

+#endif

+#if STM32_HAS_GPIOD

+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,

+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH,    VAL_GPIOD_ASCR,

+   VAL_GPIOD_LOCKR},

+#endif

+#if STM32_HAS_GPIOE

+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,

+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH,    VAL_GPIOE_ASCR,

+   VAL_GPIOE_LOCKR},

+#endif

+#if STM32_HAS_GPIOF

+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,

+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH,    VAL_GPIOF_ASCR,

+   VAL_GPIOF_LOCKR},

+#endif

+#if STM32_HAS_GPIOG

+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,

+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH,    VAL_GPIOG_ASCR,

+   VAL_GPIOG_LOCKR},

+#endif

+#if STM32_HAS_GPIOH

+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,

+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH,    VAL_GPIOH_ASCR,

+   VAL_GPIOH_LOCKR},

+#endif

+#if STM32_HAS_GPIOI

+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,

+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH,    VAL_GPIOI_ASCR,

+   VAL_GPIOI_LOCKR},

+#endif

+#if STM32_HAS_GPIOJ

+  {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,

+   VAL_GPIOJ_ODR,   VAL_GPIOJ_AFRL,   VAL_GPIOJ_AFRH,    VAL_GPIOJ_ASCR,

+   VAL_GPIOJ_LOCKR},

+#endif

+#if STM32_HAS_GPIOK

+  {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,

+   VAL_GPIOK_ODR,   VAL_GPIOK_AFRL,   VAL_GPIOK_AFRH,    VAL_GPIOK_ASCR,

+   VAL_GPIOK_LOCKR}

+#endif

+};

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {

+

+  gpiop->OTYPER  = config->otyper;

+  gpiop->ASCR    = config->ascr;

+  gpiop->OSPEEDR = config->ospeedr;

+  gpiop->PUPDR   = config->pupdr;

+  gpiop->ODR     = config->odr;

+  gpiop->AFRL    = config->afrl;

+  gpiop->AFRH    = config->afrh;

+  gpiop->MODER   = config->moder;

+  gpiop->LOCKR   = config->lockr;

+}

+

+static void stm32_gpio_init(void) {

+

+  /* Enabling GPIO-related clocks, the mask comes from the

+     registry header file.*/

+  rccResetAHB2(STM32_GPIO_EN_MASK);

+  rccEnableAHB2(STM32_GPIO_EN_MASK, true);

+

+  /* Initializing all the defined GPIO ports.*/

+#if STM32_HAS_GPIOA

+  gpio_init(GPIOA, &gpio_default_config.PAData);

+#endif

+#if STM32_HAS_GPIOB

+  gpio_init(GPIOB, &gpio_default_config.PBData);

+#endif

+#if STM32_HAS_GPIOC

+  gpio_init(GPIOC, &gpio_default_config.PCData);

+#endif

+#if STM32_HAS_GPIOD

+  gpio_init(GPIOD, &gpio_default_config.PDData);

+#endif

+#if STM32_HAS_GPIOE

+  gpio_init(GPIOE, &gpio_default_config.PEData);

+#endif

+#if STM32_HAS_GPIOF

+  gpio_init(GPIOF, &gpio_default_config.PFData);

+#endif

+#if STM32_HAS_GPIOG

+  gpio_init(GPIOG, &gpio_default_config.PGData);

+#endif

+#if STM32_HAS_GPIOH

+  gpio_init(GPIOH, &gpio_default_config.PHData);

+#endif

+#if STM32_HAS_GPIOI

+  gpio_init(GPIOI, &gpio_default_config.PIData);

+#endif

+#if STM32_HAS_GPIOJ

+  gpio_init(GPIOJ, &gpio_default_config.PJData);

+#endif

+#if STM32_HAS_GPIOK

+  gpio_init(GPIOK, &gpio_default_config.PKData);

+#endif

+}

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Early initialization code.

+ * @details GPIO ports and system clocks are initialized before everything

+ *          else.

+ */

+void __early_init(void) {

+

+  stm32_gpio_init();

+  stm32_clock_init();

+}

+

+#if HAL_USE_SDC || defined(__DOXYGEN__)

+/**

+ * @brief   SDC card detection.

+ */

+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {

+

+  (void)sdcp;

+  /* CHTODO: Fill the implementation.*/

+  return true;

+}

+

+/**

+ * @brief   SDC card write protection detection.

+ */

+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {

+

+  (void)sdcp;

+  /* CHTODO: Fill the implementation.*/

+  return false;

+}

+#endif /* HAL_USE_SDC */

+

+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)

+/**

+ * @brief   MMC_SPI card detection.

+ */

+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {

+

+  (void)mmcp;

+  /* CHTODO: Fill the implementation.*/

+  return true;

+}

+

+/**

+ * @brief   MMC_SPI card write protection detection.

+ */

+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {

+

+  (void)mmcp;

+  /* CHTODO: Fill the implementation.*/

+  return false;

+}

+#endif

+

+/**

+ * @brief   Board-specific initialization code.

+ * @note    You can add your board-specific code here.

+ */

+void boardInit(void) {

+    palSetLineMode(LINE_LED_RED, PAL_MODE_OUTPUT_PUSHPULL);

+    palSetLineMode(LINE_LED_GREEN, PAL_MODE_OUTPUT_PUSHPULL);

+    palSetLineMode(LINE_LED_BLUE, PAL_MODE_OUTPUT_PUSHPULL);

+    palClearLine(LINE_LED_RED);

+    palClearLine(LINE_LED_GREEN);

+    palClearLine(LINE_LED_BLUE);

+

+    SCB->CPACR |= 0xF << 20; // Enable FPU

+

+    // Region 2: Data for algorithm thread and ADC/DAC buffers

+    // Region 3: Code for algorithm thread

+    // Region 4: User algorithm code

+    mpuConfigureRegion(MPU_REGION_2,

+                       0x20008000,

+                       MPU_RASR_ATTR_AP_RW_RW | MPU_RASR_ATTR_NON_CACHEABLE |

+                       MPU_RASR_SIZE_128K |

+                       MPU_RASR_ENABLE);

+    mpuConfigureRegion(MPU_REGION_3,

+                       0x0807F800,

+                       MPU_RASR_ATTR_AP_RO_RO | MPU_RASR_ATTR_NON_CACHEABLE |

+                       MPU_RASR_SIZE_2K |

+                       MPU_RASR_ENABLE);

+    mpuConfigureRegion(MPU_REGION_4,

+                       0x10000000,

+                       MPU_RASR_ATTR_AP_RW_RW | MPU_RASR_ATTR_NON_CACHEABLE |

+                       MPU_RASR_SIZE_32K |

+                       MPU_RASR_ENABLE);

+}

diff --git a/firmware/source/board/h7/board.h b/firmware/source/board/h7/board.h
new file mode 100644
index 0000000..58ba40e
--- /dev/null
+++ b/firmware/source/board/h7/board.h
@@ -0,0 +1,1642 @@
+/*

+    ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/*

+ * This file has been automatically generated using ChibiStudio board

+ * generator plugin. Do not edit manually.

+ */

+

+#ifndef BOARD_H

+#define BOARD_H

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/*

+ * Setup for STMicroelectronics STM32 Nucleo144-H743ZI board.

+ */

+

+/*

+ * Board identifier.

+ */

+#define BOARD_ST_NUCLEO144_H743ZI

+#define BOARD_NAME                  "STMicroelectronics STM32 Nucleo144-H743ZI"

+

+/*

+ * Ethernet PHY type.

+ */

+#define BOARD_PHY_ID                MII_LAN8742A_ID

+#define BOARD_PHY_RMII

+

+/*

+ * Board oscillators-related settings.

+ */

+#if !defined(STM32_LSECLK)

+#define STM32_LSECLK                32768U

+#endif

+

+#define STM32_LSEDRV                (3U << 3U)

+

+#if !defined(STM32_HSECLK)

+#define STM32_HSECLK                8000000U

+#endif

+

+#define STM32_HSE_BYPASS

+

+/*

+ * MCU type as defined in the ST header.

+ */

+#define STM32H723xx

+

+/*

+ * IO pins assignments.

+ */

+#define GPIOA_PIN0                  0U

+#define GPIOA_RMII_REF_CLK          1U

+#define GPIOA_RMII_MDIO             2U

+#define GPIOA_PIN3                  3U

+#define GPIOA_PIN4                  4U

+#define GPIOA_PIN5                  5U

+#define GPIOA_PIN6                  6U

+#define GPIOA_RMII_CRS_DV           7U

+#define GPIOA_USB_SOF               8U

+#define GPIOA_MCO1                  8U

+#define GPIOA_USB_VBUS              9U

+#define GPIOA_USB_ID                10U

+#define GPIOA_USB_DM                11U

+#define GPIOA_USB_DP                12U

+#define GPIOA_SWDIO                 13U

+#define GPIOA_SWCLK                 14U

+#define GPIOA_T_JTDI                15U

+

+#define GPIOB_LED1                  0U

+#define GPIOB_LED_GREEN             0U

+#define GPIOB_LED                   0U

+#define GPIOB_PIN1                  1U

+#define GPIOB_PIN2                  2U

+#define GPIOB_SWO                   3U

+#define GPIOB_PIN4                  4U

+#define GPIOB_PIN5                  5U

+#define GPIOB_PIN6                  6U

+#define GPIOB_PIN7                  7U

+#define GPIOB_PIN8                  8U

+#define GPIOB_PIN9                  9U

+#define GPIOB_PIN10                 10U

+#define GPIOB_PIN11                 11U

+#define GPIOB_PIN12                 12U

+#define GPIOB_RMII_TXD1             13U

+#define GPIOB_LED3                  14U

+#define GPIOB_LED_RED               14U

+#define GPIOB_PIN15                 15U

+

+#define GPIOC_PIN0                  0U

+#define GPIOC_RMII_MDC              1U

+#define GPIOC_PIN2                  2U

+#define GPIOC_PIN3                  3U

+#define GPIOC_RMII_RXD0             4U

+#define GPIOC_RMII_RXD1             5U

+#define GPIOC_PIN6                  6U

+#define GPIOC_PIN7                  7U

+#define GPIOC_PIN8                  8U

+#define GPIOC_PIN9                  9U

+#define GPIOC_PIN10                 10U

+#define GPIOC_PIN11                 11U

+#define GPIOC_PIN12                 12U

+#define GPIOC_BUTTON                13U

+#define GPIOC_OSC32_IN              14U

+#define GPIOC_OSC32_OUT             15U

+

+#define GPIOD_PIN0                  0U

+#define GPIOD_PIN1                  1U

+#define GPIOD_PIN2                  2U

+#define GPIOD_PIN3                  3U

+#define GPIOD_PIN4                  4U

+#define GPIOD_PIN5                  5U

+#define GPIOD_PIN6                  6U

+#define GPIOD_PIN7                  7U

+#define GPIOD_USART3_RX             8U

+#define GPIOD_STLK_RX               8U

+#define GPIOD_USART3_TX             9U

+#define GPIOD_STLK_TX               9U

+#define GPIOD_PIN10                 10U

+#define GPIOD_PIN11                 11U

+#define GPIOD_PIN12                 12U

+#define GPIOD_PIN13                 13U

+#define GPIOD_PIN14                 14U

+#define GPIOD_PIN15                 15U

+

+#define GPIOE_PIN0                  0U

+#define GPIOE_LED2                  1U

+#define GPIOE_LED_YELLOW            1U

+#define GPIOE_PIN2                  2U

+#define GPIOE_PIN3                  3U

+#define GPIOE_PIN4                  4U

+#define GPIOE_PIN5                  5U

+#define GPIOE_PIN6                  6U

+#define GPIOE_PIN7                  7U

+#define GPIOE_PIN8                  8U

+#define GPIOE_PIN9                  9U

+#define GPIOE_PIN10                 10U

+#define GPIOE_PIN11                 11U

+#define GPIOE_PIN12                 12U

+#define GPIOE_PIN13                 13U

+#define GPIOE_PIN14                 14U

+#define GPIOE_PIN15                 15U

+

+#define GPIOF_PIN0                  0U

+#define GPIOF_PIN1                  1U

+#define GPIOF_PIN2                  2U

+#define GPIOF_PIN3                  3U

+#define GPIOF_PIN4                  4U

+#define GPIOF_PIN5                  5U

+#define GPIOF_PIN6                  6U

+#define GPIOF_PIN7                  7U

+#define GPIOF_PIN8                  8U

+#define GPIOF_PIN9                  9U

+#define GPIOF_PIN10                 10U

+#define GPIOF_PIN11                 11U

+#define GPIOF_PIN12                 12U

+#define GPIOF_PIN13                 13U

+#define GPIOF_PIN14                 14U

+#define GPIOF_PIN15                 15U

+

+#define GPIOG_PIN0                  0U

+#define GPIOG_PIN1                  1U

+#define GPIOG_PIN2                  2U

+#define GPIOG_PIN3                  3U

+#define GPIOG_PIN4                  4U

+#define GPIOG_PIN5                  5U

+#define GPIOG_USB_FS_PWR_EN         6U

+#define GPIOG_USB_FS_OVCR           7U

+#define GPIOG_PIN8                  8U

+#define GPIOG_PIN9                  9U

+#define GPIOG_PIN10                 10U

+#define GPIOG_RMII_TX_EN            11U

+#define GPIOG_PIN12                 12U

+#define GPIOG_RMII_TXD0             13U

+#define GPIOG_PIN14                 14U

+#define GPIOG_PIN15                 15U

+

+#define GPIOH_OSC_IN                0U

+#define GPIOH_OSC_OUT               1U

+#define GPIOH_PIN2                  2U

+#define GPIOH_PIN3                  3U

+#define GPIOH_PIN4                  4U

+#define GPIOH_PIN5                  5U

+#define GPIOH_PIN6                  6U

+#define GPIOH_PIN7                  7U

+#define GPIOH_PIN8                  8U

+#define GPIOH_PIN9                  9U

+#define GPIOH_PIN10                 10U

+#define GPIOH_PIN11                 11U

+#define GPIOH_PIN12                 12U

+#define GPIOH_PIN13                 13U

+#define GPIOH_PIN14                 14U

+#define GPIOH_PIN15                 15U

+

+#define GPIOI_PIN0                  0U

+#define GPIOI_PIN1                  1U

+#define GPIOI_PIN2                  2U

+#define GPIOI_PIN3                  3U

+#define GPIOI_PIN4                  4U

+#define GPIOI_PIN5                  5U

+#define GPIOI_PIN6                  6U

+#define GPIOI_PIN7                  7U

+#define GPIOI_PIN8                  8U

+#define GPIOI_PIN9                  9U

+#define GPIOI_PIN10                 10U

+#define GPIOI_PIN11                 11U

+#define GPIOI_PIN12                 12U

+#define GPIOI_PIN13                 13U

+#define GPIOI_PIN14                 14U

+#define GPIOI_PIN15                 15U

+

+#define GPIOJ_PIN0                  0U

+#define GPIOJ_PIN1                  1U

+#define GPIOJ_PIN2                  2U

+#define GPIOJ_PIN3                  3U

+#define GPIOJ_PIN4                  4U

+#define GPIOJ_PIN5                  5U

+#define GPIOJ_PIN6                  6U

+#define GPIOJ_PIN7                  7U

+#define GPIOJ_PIN8                  8U

+#define GPIOJ_PIN9                  9U

+#define GPIOJ_PIN10                 10U

+#define GPIOJ_PIN11                 11U

+#define GPIOJ_PIN12                 12U

+#define GPIOJ_PIN13                 13U

+#define GPIOJ_PIN14                 14U

+#define GPIOJ_PIN15                 15U

+

+#define GPIOK_PIN0                  0U

+#define GPIOK_PIN1                  1U

+#define GPIOK_PIN2                  2U

+#define GPIOK_PIN3                  3U

+#define GPIOK_PIN4                  4U

+#define GPIOK_PIN5                  5U

+#define GPIOK_PIN6                  6U

+#define GPIOK_PIN7                  7U

+#define GPIOK_PIN8                  8U

+#define GPIOK_PIN9                  9U

+#define GPIOK_PIN10                 10U

+#define GPIOK_PIN11                 11U

+#define GPIOK_PIN12                 12U

+#define GPIOK_PIN13                 13U

+#define GPIOK_PIN14                 14U

+#define GPIOK_PIN15                 15U

+

+/*

+ * IO lines assignments.

+ */

+#define LINE_RMII_REF_CLK           PAL_LINE(GPIOA, 1U)

+#define LINE_RMII_MDIO              PAL_LINE(GPIOA, 2U)

+#define LINE_RMII_CRS_DV            PAL_LINE(GPIOA, 7U)

+#define LINE_USB_SOF                PAL_LINE(GPIOA, 8U)

+#define LINE_MCO1                   PAL_LINE(GPIOA, 8U)

+#define LINE_USB_VBUS               PAL_LINE(GPIOA, 9U)

+#define LINE_USB_ID                 PAL_LINE(GPIOA, 10U)

+#define LINE_USB_DM                 PAL_LINE(GPIOA, 11U)

+#define LINE_USB_DP                 PAL_LINE(GPIOA, 12U)

+#define LINE_SWDIO                  PAL_LINE(GPIOA, 13U)

+#define LINE_SWCLK                  PAL_LINE(GPIOA, 14U)

+#define LINE_T_JTDI                 PAL_LINE(GPIOA, 15U)

+#define LINE_LED1                   PAL_LINE(GPIOB, 0U)

+#define LINE_LED_GREEN              PAL_LINE(GPIOB, 0U)

+#define LINE_LED                    PAL_LINE(GPIOB, 0U)

+#define LINE_SWO                    PAL_LINE(GPIOB, 3U)

+#define LINE_LED2                   PAL_LINE(GPIOE, 1U)

+#define LINE_LED_YELLOW             PAL_LINE(GPIOE, 1U)

+#define LINE_RMII_TXD1              PAL_LINE(GPIOB, 13U)

+#define LINE_LED3                   PAL_LINE(GPIOB, 14U)

+#define LINE_LED_RED                PAL_LINE(GPIOB, 14U)

+#define LINE_RMII_MDC               PAL_LINE(GPIOC, 1U)

+#define LINE_RMII_RXD0              PAL_LINE(GPIOC, 4U)

+#define LINE_RMII_RXD1              PAL_LINE(GPIOC, 5U)

+#define LINE_BUTTON                 PAL_LINE(GPIOC, 13U)

+#define LINE_OSC32_IN               PAL_LINE(GPIOC, 14U)

+#define LINE_OSC32_OUT              PAL_LINE(GPIOC, 15U)

+#define LINE_USART3_RX              PAL_LINE(GPIOD, 8U)

+#define LINE_STLK_RX                PAL_LINE(GPIOD, 8U)

+#define LINE_USART3_TX              PAL_LINE(GPIOD, 9U)

+#define LINE_STLK_TX                PAL_LINE(GPIOD, 9U)

+#define LINE_USB_FS_PWR_EN          PAL_LINE(GPIOG, 6U)

+#define LINE_USB_FS_OVCR            PAL_LINE(GPIOG, 7U)

+#define LINE_RMII_TX_EN             PAL_LINE(GPIOG, 11U)

+#define LINE_RMII_TXD0              PAL_LINE(GPIOG, 13U)

+#define LINE_OSC_IN                 PAL_LINE(GPIOH, 0U)

+#define LINE_OSC_OUT                PAL_LINE(GPIOH, 1U)

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/*

+ * I/O ports initial setup, this configuration is established soon after reset

+ * in the initialization code.

+ * Please refer to the STM32 Reference Manual for details.

+ */

+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2U))

+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2U))

+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2U))

+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2U))

+#define PIN_ODR_LOW(n)              (0U << (n))

+#define PIN_ODR_HIGH(n)             (1U << (n))

+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))

+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))

+#define PIN_OSPEED_VERYLOW(n)       (0U << ((n) * 2U))

+#define PIN_OSPEED_LOW(n)           (1U << ((n) * 2U))

+#define PIN_OSPEED_MEDIUM(n)        (2U << ((n) * 2U))

+#define PIN_OSPEED_HIGH(n)          (3U << ((n) * 2U))

+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2U))

+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2U))

+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2U))

+#define PIN_AFIO_AF(n, v)           ((v) << (((n) % 8U) * 4U))

+

+/*

+ * GPIOA setup:

+ *

+ * PA0  - PIN0                      (input pullup).

+ * PA1  - RMII_REF_CLK              (alternate 11).

+ * PA2  - RMII_MDIO                 (alternate 11).

+ * PA3  - PIN3                      (input pullup).

+ * PA4  - PIN4                      (input pullup).

+ * PA5  - PIN5                      (input pullup).

+ * PA6  - PIN6                      (input pullup).

+ * PA7  - RMII_CRS_DV               (alternate 11).

+ * PA8  - USB_SOF MCO1              (alternate 10).

+ * PA9  - USB_VBUS                  (analog).

+ * PA10 - USB_ID                    (alternate 10).

+ * PA11 - USB_DM                    (alternate 10).

+ * PA12 - USB_DP                    (alternate 10).

+ * PA13 - SWDIO                     (alternate 0).

+ * PA14 - SWCLK                     (alternate 0).

+ * PA15 - T_JTDI                    (alternate 0).

+ */

+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_PIN0) |           \

+                                     PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\

+                                     PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) |  \

+                                     PIN_MODE_INPUT(GPIOA_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOA_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOA_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOA_PIN6) |           \

+                                     PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) |\

+                                     PIN_MODE_ALTERNATE(GPIOA_USB_SOF) |    \

+                                     PIN_MODE_ANALOG(GPIOA_USB_VBUS) |      \

+                                     PIN_MODE_ALTERNATE(GPIOA_USB_ID) |     \

+                                     PIN_MODE_ALTERNATE(GPIOA_USB_DM) |     \

+                                     PIN_MODE_ALTERNATE(GPIOA_USB_DP) |     \

+                                     PIN_MODE_ALTERNATE(GPIOA_SWDIO) |      \

+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |      \

+                                     PIN_MODE_ALTERNATE(GPIOA_T_JTDI))

+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\

+                                     PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) |  \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) |\

+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) |   \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_T_JTDI))

+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOA_PIN0) |       \

+                                     PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) |  \

+                                     PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) |     \

+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN3) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN4) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN5) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN6) |       \

+                                     PIN_OSPEED_HIGH(GPIOA_RMII_CRS_DV) |   \

+                                     PIN_OSPEED_HIGH(GPIOA_USB_SOF) |       \

+                                     PIN_OSPEED_HIGH(GPIOA_USB_VBUS) |      \

+                                     PIN_OSPEED_HIGH(GPIOA_USB_ID) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_USB_DM) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_USB_DP) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_SWDIO) |         \

+                                     PIN_OSPEED_HIGH(GPIOA_SWCLK) |         \

+                                     PIN_OSPEED_HIGH(GPIOA_T_JTDI))

+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_PULLUP(GPIOA_PIN0) |         \

+                                     PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\

+                                     PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) |    \

+                                     PIN_PUPDR_PULLUP(GPIOA_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOA_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOA_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOA_RMII_CRS_DV) |  \

+                                     PIN_PUPDR_FLOATING(GPIOA_USB_SOF) |    \

+                                     PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) |   \

+                                     PIN_PUPDR_FLOATING(GPIOA_USB_ID) |     \

+                                     PIN_PUPDR_FLOATING(GPIOA_USB_DM) |     \

+                                     PIN_PUPDR_FLOATING(GPIOA_USB_DP) |     \

+                                     PIN_PUPDR_FLOATING(GPIOA_SWDIO) |      \

+                                     PIN_PUPDR_FLOATING(GPIOA_SWCLK) |      \

+                                     PIN_PUPDR_PULLUP(GPIOA_T_JTDI))

+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) |     \

+                                     PIN_ODR_HIGH(GPIOA_RMII_MDIO) |        \

+                                     PIN_ODR_HIGH(GPIOA_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOA_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOA_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOA_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) |      \

+                                     PIN_ODR_HIGH(GPIOA_USB_SOF) |          \

+                                     PIN_ODR_HIGH(GPIOA_USB_VBUS) |         \

+                                     PIN_ODR_HIGH(GPIOA_USB_ID) |           \

+                                     PIN_ODR_HIGH(GPIOA_USB_DM) |           \

+                                     PIN_ODR_HIGH(GPIOA_USB_DP) |           \

+                                     PIN_ODR_HIGH(GPIOA_SWDIO) |            \

+                                     PIN_ODR_HIGH(GPIOA_SWCLK) |            \

+                                     PIN_ODR_HIGH(GPIOA_T_JTDI))

+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_PIN0, 0U) |          \

+                                     PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \

+                                     PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) |    \

+                                     PIN_AFIO_AF(GPIOA_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOA_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOA_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOA_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11U))

+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) |      \

+                                     PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) |      \

+                                     PIN_AFIO_AF(GPIOA_USB_ID, 10U) |       \

+                                     PIN_AFIO_AF(GPIOA_USB_DM, 10U) |       \

+                                     PIN_AFIO_AF(GPIOA_USB_DP, 10U) |       \

+                                     PIN_AFIO_AF(GPIOA_SWDIO, 0U) |         \

+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0U) |         \

+                                     PIN_AFIO_AF(GPIOA_T_JTDI, 0U))

+

+/*

+ * GPIOB setup:

+ *

+ * PB0  - LED1 LED_GREEN LED        (output pushpull maximum).

+ * PB1  - PIN1                      (input pullup).

+ * PB2  - PIN2                      (input pullup).

+ * PB3  - SWO                       (alternate 0).

+ * PB4  - PIN4                      (input pullup).

+ * PB5  - PIN5                      (input pullup).

+ * PB6  - PIN6                      (input pullup).

+ * PB7  - PIN7                      (input pullup).

+ * PB8  - PIN8                      (input pullup).

+ * PB9  - PIN9                      (input pullup).

+ * PB10 - PIN10                     (input pullup).

+ * PB11 - PIN11                     (input pullup).

+ * PB12 - PIN12                     (input pullup).

+ * PB13 - RMII_TXD1                 (alternate 11).

+ * PB14 - LED3 LED_RED              (output pushpull maximum).

+ * PB15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOB_MODER             (PIN_MODE_OUTPUT(GPIOB_LED1) |          \

+                                     PIN_MODE_INPUT(GPIOB_PIN1) |           \

+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \

+                                     PIN_MODE_ALTERNATE(GPIOB_SWO) |        \

+                                     PIN_MODE_INPUT(GPIOB_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOB_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOB_PIN7) |           \

+                                     PIN_MODE_INPUT(GPIOB_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOB_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOB_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \

+                                     PIN_MODE_ALTERNATE(GPIOB_RMII_TXD1) |  \

+                                     PIN_MODE_OUTPUT(GPIOB_LED3) |          \

+                                     PIN_MODE_INPUT(GPIOB_PIN15))

+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_LED1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_SWO) |        \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_RMII_TXD1) |  \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_LED3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))

+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_HIGH(GPIOB_LED1) |          \

+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN1) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN2) |       \

+                                     PIN_OSPEED_HIGH(GPIOB_SWO) |           \

+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN4) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN5) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN6) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN7) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN8) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN9) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN10) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN11) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN12) |      \

+                                     PIN_OSPEED_HIGH(GPIOB_RMII_TXD1) |     \

+                                     PIN_OSPEED_HIGH(GPIOB_LED3) |          \

+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN15))

+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_FLOATING(GPIOB_LED1) |       \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOB_SWO) |          \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |       \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOB_RMII_TXD1) |    \

+                                     PIN_PUPDR_FLOATING(GPIOB_LED3) |       \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))

+#define VAL_GPIOB_ODR               (PIN_ODR_LOW(GPIOB_LED1) |              \

+                                     PIN_ODR_HIGH(GPIOB_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOB_SWO) |              \

+                                     PIN_ODR_HIGH(GPIOB_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOB_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOB_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOB_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOB_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOB_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOB_RMII_TXD1) |        \

+                                     PIN_ODR_LOW(GPIOB_LED3) |              \

+                                     PIN_ODR_HIGH(GPIOB_PIN15))

+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_LED1, 0U) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN1, 0U) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOB_SWO, 0U) |           \

+                                     PIN_AFIO_AF(GPIOB_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN7, 0U))

+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOB_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOB_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOB_RMII_TXD1, 11U) |    \

+                                     PIN_AFIO_AF(GPIOB_LED3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN15, 0U))

+

+/*

+ * GPIOC setup:

+ *

+ * PC0  - PIN0                      (input pullup).

+ * PC1  - RMII_MDC                  (alternate 11).

+ * PC2  - PIN2                      (input pullup).

+ * PC3  - PIN3                      (input pullup).

+ * PC4  - RMII_RXD0                 (alternate 11).

+ * PC5  - RMII_RXD1                 (alternate 11).

+ * PC6  - PIN6                      (input pullup).

+ * PC7  - PIN7                      (input pullup).

+ * PC8  - PIN8                      (input pullup).

+ * PC9  - PIN9                      (input pullup).

+ * PC10 - PIN10                     (input pullup).

+ * PC11 - PIN11                     (input pullup).

+ * PC12 - PIN12                     (input pullup).

+ * PC13 - BUTTON                    (input floating).

+ * PC14 - OSC32_IN                  (input floating).

+ * PC15 - OSC32_OUT                 (input floating).

+ */

+#define VAL_GPIOC_MODER             (PIN_MODE_INPUT(GPIOC_PIN0) |           \

+                                     PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) |   \

+                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN3) |           \

+                                     PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) |  \

+                                     PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) |  \

+                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN7) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOC_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOC_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOC_BUTTON) |         \

+                                     PIN_MODE_INPUT(GPIOC_OSC32_IN) |       \

+                                     PIN_MODE_INPUT(GPIOC_OSC32_OUT))

+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) |   \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) |  \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) |  \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) |   \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))

+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOC_PIN0) |       \

+                                     PIN_OSPEED_HIGH(GPIOC_RMII_MDC) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN2) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN3) |       \

+                                     PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) |     \

+                                     PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) |     \

+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN6) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN7) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN8) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN9) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN10) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN11) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN12) |      \

+                                     PIN_OSPEED_HIGH(GPIOC_BUTTON) |        \

+                                     PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) |   \

+                                     PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT))

+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_PULLUP(GPIOC_PIN0) |         \

+                                     PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) |   \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN3) |         \

+                                     PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) |  \

+                                     PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) |  \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN7) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN12) |        \

+                                     PIN_PUPDR_FLOATING(GPIOC_BUTTON) |     \

+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) |   \

+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))

+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOC_RMII_MDC) |         \

+                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOC_RMII_RXD0) |        \

+                                     PIN_ODR_HIGH(GPIOC_RMII_RXD1) |        \

+                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOC_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOC_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOC_BUTTON) |           \

+                                     PIN_ODR_HIGH(GPIOC_OSC32_IN) |         \

+                                     PIN_ODR_HIGH(GPIOC_OSC32_OUT))

+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0U) |          \

+                                     PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) |     \

+                                     PIN_AFIO_AF(GPIOC_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) |    \

+                                     PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) |    \

+                                     PIN_AFIO_AF(GPIOC_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN7, 0U))

+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOC_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOC_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOC_BUTTON, 0U) |        \

+                                     PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) |      \

+                                     PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))

+

+/*

+ * GPIOD setup:

+ *

+ * PD0  - PIN0                      (input pullup).

+ * PD1  - PIN1                      (input pullup).

+ * PD2  - PIN2                      (input pullup).

+ * PD3  - PIN3                      (input pullup).

+ * PD4  - PIN4                      (input pullup).

+ * PD5  - PIN5                      (input pullup).

+ * PD6  - PIN6                      (input pullup).

+ * PD7  - PIN7                      (input pullup).

+ * PD8  - USART3_RX STLK_RX         (alternate 7).

+ * PD9  - USART3_TX STLK_TX         (alternate 7).

+ * PD10 - PIN10                     (input pullup).

+ * PD11 - PIN11                     (input pullup).

+ * PD12 - PIN12                     (input pullup).

+ * PD13 - PIN13                     (input pullup).

+ * PD14 - PIN14                     (input pullup).

+ * PD15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \

+                                     PIN_MODE_ALTERNATE(GPIOD_USART3_RX) |  \

+                                     PIN_MODE_ALTERNATE(GPIOD_USART3_TX) |  \

+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOD_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOD_PIN13) |          \

+                                     PIN_MODE_INPUT(GPIOD_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOD_PIN15))

+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) |  \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) |  \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15))

+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOD_PIN0) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN1) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN2) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN3) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN4) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN5) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN6) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN7) |       \

+                                     PIN_OSPEED_HIGH(GPIOD_USART3_RX) |     \

+                                     PIN_OSPEED_HIGH(GPIOD_USART3_TX) |     \

+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN10) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN11) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN12) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN13) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN14) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN15))

+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \

+                                     PIN_PUPDR_FLOATING(GPIOD_USART3_RX) |  \

+                                     PIN_PUPDR_FLOATING(GPIOD_USART3_TX) |  \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN13) |        \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN15))

+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOD_USART3_RX) |        \

+                                     PIN_ODR_HIGH(GPIOD_USART3_TX) |        \

+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN15))

+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN1, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN7, 0U))

+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_USART3_RX, 7U) |     \

+                                     PIN_AFIO_AF(GPIOD_USART3_TX, 7U) |     \

+                                     PIN_AFIO_AF(GPIOD_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOD_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOD_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOD_PIN13, 0U) |         \

+                                     PIN_AFIO_AF(GPIOD_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOD_PIN15, 0U))

+

+/*

+ * GPIOE setup:

+ *

+ * PE0  - PIN0                      (input pullup).

+ * PE1  - PIN1                      (input pullup).

+ * PE2  - PIN2                      (input pullup).

+ * PE3  - PIN3                      (input pullup).

+ * PE4  - PIN4                      (input pullup).

+ * PE5  - PIN5                      (input pullup).

+ * PE6  - PIN6                      (input pullup).

+ * PE7  - PIN7                      (input pullup).

+ * PE8  - PIN8                      (input pullup).

+ * PE9  - PIN9                      (input pullup).

+ * PE10 - PIN10                     (input pullup).

+ * PE11 - PIN11                     (input pullup).

+ * PE12 - PIN12                     (input pullup).

+ * PE13 - PIN13                     (input pullup).

+ * PE14 - PIN14                     (input pullup).

+ * PE15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOE_MODER             (PIN_MODE_INPUT(GPIOE_PIN0) |           \

+                                     PIN_MODE_OUTPUT(GPIOE_LED2) |          \

+                                     PIN_MODE_INPUT(GPIOE_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN7) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOE_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOE_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOE_PIN13) |          \

+                                     PIN_MODE_INPUT(GPIOE_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOE_PIN15))

+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_LED2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN15))

+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOE_PIN0) |       \

+                                     PIN_OSPEED_HIGH(GPIOE_LED2) |          \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN2) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN3) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN4) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN5) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN6) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN7) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN8) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN9) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN10) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN11) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN12) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN13) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN14) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN15))

+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_PULLUP(GPIOE_PIN0) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_LED2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN7) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN13) |        \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN15))

+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_PIN0) |             \

+                                     PIN_ODR_LOW(GPIOE_LED2) |              \

+                                     PIN_ODR_HIGH(GPIOE_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN15))

+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_PIN0, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_LED2, 0U)) |         \

+                                     PIN_AFIO_AF(GPIOE_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN7, 0U)

+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOE_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOE_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOE_PIN13, 0U) |         \

+                                     PIN_AFIO_AF(GPIOE_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOE_PIN15, 0U))

+

+/*

+ * GPIOF setup:

+ *

+ * PF0  - PIN0                      (input pullup).

+ * PF1  - PIN1                      (input pullup).

+ * PF2  - PIN2                      (input pullup).

+ * PF3  - PIN3                      (input pullup).

+ * PF4  - PIN4                      (input pullup).

+ * PF5  - PIN5                      (input pullup).

+ * PF6  - PIN6                      (input pullup).

+ * PF7  - PIN7                      (input pullup).

+ * PF8  - PIN8                      (input pullup).

+ * PF9  - PIN9                      (input pullup).

+ * PF10 - PIN10                     (input pullup).

+ * PF11 - PIN11                     (input pullup).

+ * PF12 - PIN12                     (input pullup).

+ * PF13 - PIN13                     (input pullup).

+ * PF14 - PIN14                     (input pullup).

+ * PF15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_PIN0) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN1) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOF_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \

+                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOF_PIN15))

+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))

+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOF_PIN0) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN1) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN2) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN3) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN4) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN5) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN6) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN7) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN8) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN9) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN10) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN11) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN12) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN13) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN14) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN15))

+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_PULLUP(GPIOF_PIN0) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN1) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN7) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN13) |        \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN15))

+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN15))

+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_PIN0, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN1, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN7, 0U))

+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOF_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOF_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOF_PIN13, 0U) |         \

+                                     PIN_AFIO_AF(GPIOF_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOF_PIN15, 0U))

+

+/*

+ * GPIOG setup:

+ *

+ * PG0  - PIN0                      (input pullup).

+ * PG1  - PIN1                      (input pullup).

+ * PG2  - PIN2                      (input pullup).

+ * PG3  - PIN3                      (input pullup).

+ * PG4  - PIN4                      (input pullup).

+ * PG5  - PIN5                      (input pullup).

+ * PG6  - USB_FS_PWR_EN             (output pushpull minimum).

+ * PG7  - USB_FS_OVCR               (input floating).

+ * PG8  - PIN8                      (input pullup).

+ * PG9  - PIN9                      (input pullup).

+ * PG10 - PIN10                     (input pullup).

+ * PG11 - RMII_TX_EN                (alternate 11).

+ * PG12 - PIN12                     (input pullup).

+ * PG13 - RMII_TXD0                 (alternate 11).

+ * PG14 - PIN14                     (input pullup).

+ * PG15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOG_MODER             (PIN_MODE_INPUT(GPIOG_PIN0) |           \

+                                     PIN_MODE_INPUT(GPIOG_PIN1) |           \

+                                     PIN_MODE_INPUT(GPIOG_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOG_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOG_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOG_PIN5) |           \

+                                     PIN_MODE_OUTPUT(GPIOG_USB_FS_PWR_EN) | \

+                                     PIN_MODE_INPUT(GPIOG_USB_FS_OVCR) |    \

+                                     PIN_MODE_INPUT(GPIOG_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOG_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOG_PIN10) |          \

+                                     PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \

+                                     PIN_MODE_INPUT(GPIOG_PIN12) |          \

+                                     PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) |  \

+                                     PIN_MODE_INPUT(GPIOG_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOG_PIN15))

+#define VAL_GPIOG_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_USB_FS_PWR_EN) |\

+                                     PIN_OTYPE_PUSHPULL(GPIOG_USB_FS_OVCR) |\

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) |  \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN15))

+#define VAL_GPIOG_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOG_PIN0) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN1) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN2) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN3) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN4) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN5) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_USB_FS_PWR_EN) |\

+                                     PIN_OSPEED_VERYLOW(GPIOG_USB_FS_OVCR) |\

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN8) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN9) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN10) |      \

+                                     PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) |    \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN12) |      \

+                                     PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) |     \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN14) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN15))

+#define VAL_GPIOG_PUPDR             (PIN_PUPDR_PULLUP(GPIOG_PIN0) |         \

+                                     PIN_PUPDR_PULLUP(GPIOG_PIN1) |         \

+                                     PIN_PUPDR_PULLUP(GPIOG_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOG_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOG_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOG_PIN5) |         \

+                                     PIN_PUPDR_FLOATING(GPIOG_USB_FS_PWR_EN) |\

+                                     PIN_PUPDR_FLOATING(GPIOG_USB_FS_OVCR) |\

+                                     PIN_PUPDR_PULLUP(GPIOG_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOG_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOG_PIN10) |        \

+                                     PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \

+                                     PIN_PUPDR_PULLUP(GPIOG_PIN12) |        \

+                                     PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) |  \

+                                     PIN_PUPDR_PULLUP(GPIOG_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOG_PIN15))

+#define VAL_GPIOG_ODR               (PIN_ODR_HIGH(GPIOG_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN5) |             \

+                                     PIN_ODR_LOW(GPIOG_USB_FS_PWR_EN) |     \

+                                     PIN_ODR_HIGH(GPIOG_USB_FS_OVCR) |      \

+                                     PIN_ODR_HIGH(GPIOG_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOG_RMII_TX_EN) |       \

+                                     PIN_ODR_HIGH(GPIOG_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOG_RMII_TXD0) |        \

+                                     PIN_ODR_HIGH(GPIOG_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOG_PIN15))

+#define VAL_GPIOG_AFRL              (PIN_AFIO_AF(GPIOG_PIN0, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN1, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_USB_FS_PWR_EN, 0U) | \

+                                     PIN_AFIO_AF(GPIOG_USB_FS_OVCR, 0U))

+#define VAL_GPIOG_AFRH              (PIN_AFIO_AF(GPIOG_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) |   \

+                                     PIN_AFIO_AF(GPIOG_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) |    \

+                                     PIN_AFIO_AF(GPIOG_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOG_PIN15, 0U))

+

+/*

+ * GPIOH setup:

+ *

+ * PH0  - OSC_IN                    (input floating).

+ * PH1  - OSC_OUT                   (input floating).

+ * PH2  - PIN2                      (input pullup).

+ * PH3  - PIN3                      (input pullup).

+ * PH4  - PIN4                      (input pullup).

+ * PH5  - PIN5                      (input pullup).

+ * PH6  - PIN6                      (input pullup).

+ * PH7  - PIN7                      (input pullup).

+ * PH8  - PIN8                      (input pullup).

+ * PH9  - PIN9                      (input pullup).

+ * PH10 - PIN10                     (input pullup).

+ * PH11 - PIN11                     (input pullup).

+ * PH12 - PIN12                     (input pullup).

+ * PH13 - PIN13                     (input pullup).

+ * PH14 - PIN14                     (input pullup).

+ * PH15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOH_MODER             (PIN_MODE_INPUT(GPIOH_OSC_IN) |         \

+                                     PIN_MODE_INPUT(GPIOH_OSC_OUT) |        \

+                                     PIN_MODE_INPUT(GPIOH_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN7) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOH_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOH_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOH_PIN13) |          \

+                                     PIN_MODE_INPUT(GPIOH_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOH_PIN15))

+#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN15))

+#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_HIGH(GPIOH_OSC_IN) |        \

+                                     PIN_OSPEED_HIGH(GPIOH_OSC_OUT) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN2) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN3) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN4) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN5) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN6) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN7) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN8) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN9) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN10) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN11) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN12) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN13) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN14) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN15))

+#define VAL_GPIOH_PUPDR             (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) |     \

+                                     PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) |    \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN7) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN13) |        \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN15))

+#define VAL_GPIOH_ODR               (PIN_ODR_HIGH(GPIOH_OSC_IN) |           \

+                                     PIN_ODR_HIGH(GPIOH_OSC_OUT) |          \

+                                     PIN_ODR_HIGH(GPIOH_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN15))

+#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) |        \

+                                     PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) |       \

+                                     PIN_AFIO_AF(GPIOH_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN7, 0U))

+#define VAL_GPIOH_AFRH              (PIN_AFIO_AF(GPIOH_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOH_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOH_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOH_PIN13, 0U) |         \

+                                     PIN_AFIO_AF(GPIOH_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOH_PIN15, 0U))

+

+/*

+ * GPIOI setup:

+ *

+ * PI0  - PIN0                      (input pullup).

+ * PI1  - PIN1                      (input pullup).

+ * PI2  - PIN2                      (input pullup).

+ * PI3  - PIN3                      (input pullup).

+ * PI4  - PIN4                      (input pullup).

+ * PI5  - PIN5                      (input pullup).

+ * PI6  - PIN6                      (input pullup).

+ * PI7  - PIN7                      (input pullup).

+ * PI8  - PIN8                      (input pullup).

+ * PI9  - PIN9                      (input pullup).

+ * PI10 - PIN10                     (input pullup).

+ * PI11 - PIN11                     (input pullup).

+ * PI12 - PIN12                     (input pullup).

+ * PI13 - PIN13                     (input pullup).

+ * PI14 - PIN14                     (input pullup).

+ * PI15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOI_MODER             (PIN_MODE_INPUT(GPIOI_PIN0) |           \

+                                     PIN_MODE_INPUT(GPIOI_PIN1) |           \

+                                     PIN_MODE_INPUT(GPIOI_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOI_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOI_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOI_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOI_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOI_PIN7) |           \

+                                     PIN_MODE_INPUT(GPIOI_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOI_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOI_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOI_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOI_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOI_PIN13) |          \

+                                     PIN_MODE_INPUT(GPIOI_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOI_PIN15))

+#define VAL_GPIOI_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN15))

+#define VAL_GPIOI_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOI_PIN0) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN1) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN2) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN3) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN4) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN5) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN6) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN7) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN8) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN9) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN10) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN11) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN12) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN13) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN14) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOI_PIN15))

+#define VAL_GPIOI_PUPDR             (PIN_PUPDR_PULLUP(GPIOI_PIN0) |         \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN1) |         \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN7) |         \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN13) |        \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOI_PIN15))

+#define VAL_GPIOI_ODR               (PIN_ODR_HIGH(GPIOI_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOI_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOI_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOI_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOI_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOI_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOI_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOI_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOI_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOI_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOI_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOI_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOI_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOI_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOI_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOI_PIN15))

+#define VAL_GPIOI_AFRL              (PIN_AFIO_AF(GPIOI_PIN0, 0U) |          \

+                                     PIN_AFIO_AF(GPIOI_PIN1, 0U) |          \

+                                     PIN_AFIO_AF(GPIOI_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOI_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOI_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOI_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOI_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOI_PIN7, 0U))

+#define VAL_GPIOI_AFRH              (PIN_AFIO_AF(GPIOI_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOI_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOI_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOI_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOI_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOI_PIN13, 0U) |         \

+                                     PIN_AFIO_AF(GPIOI_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOI_PIN15, 0U))

+

+/*

+ * GPIOJ setup:

+ *

+ * PJ0  - PIN0                      (input pullup).

+ * PJ1  - PIN1                      (input pullup).

+ * PJ2  - PIN2                      (input pullup).

+ * PJ3  - PIN3                      (input pullup).

+ * PJ4  - PIN4                      (input pullup).

+ * PJ5  - PIN5                      (input pullup).

+ * PJ6  - PIN6                      (input pullup).

+ * PJ7  - PIN7                      (input pullup).

+ * PJ8  - PIN8                      (input pullup).

+ * PJ9  - PIN9                      (input pullup).

+ * PJ10 - PIN10                     (input pullup).

+ * PJ11 - PIN11                     (input pullup).

+ * PJ12 - PIN12                     (input pullup).

+ * PJ13 - PIN13                     (input pullup).

+ * PJ14 - PIN14                     (input pullup).

+ * PJ15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOJ_MODER             (PIN_MODE_INPUT(GPIOJ_PIN0) |           \

+                                     PIN_MODE_INPUT(GPIOJ_PIN1) |           \

+                                     PIN_MODE_INPUT(GPIOJ_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOJ_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOJ_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOJ_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOJ_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOJ_PIN7) |           \

+                                     PIN_MODE_INPUT(GPIOJ_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOJ_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOJ_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOJ_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOJ_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOJ_PIN13) |          \

+                                     PIN_MODE_INPUT(GPIOJ_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOJ_PIN15))

+#define VAL_GPIOJ_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOJ_PIN15))

+#define VAL_GPIOJ_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN1) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN2) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN3) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN4) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN5) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN6) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN7) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN8) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN9) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN10) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN11) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN12) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN13) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN14) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOJ_PIN15))

+#define VAL_GPIOJ_PUPDR             (PIN_PUPDR_PULLUP(GPIOJ_PIN0) |         \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN1) |         \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN7) |         \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN13) |        \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOJ_PIN15))

+#define VAL_GPIOJ_ODR               (PIN_ODR_HIGH(GPIOJ_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOJ_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOJ_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOJ_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOJ_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOJ_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOJ_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOJ_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOJ_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOJ_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOJ_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOJ_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOJ_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOJ_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOJ_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOJ_PIN15))

+#define VAL_GPIOJ_AFRL              (PIN_AFIO_AF(GPIOJ_PIN0, 0U) |          \

+                                     PIN_AFIO_AF(GPIOJ_PIN1, 0U) |          \

+                                     PIN_AFIO_AF(GPIOJ_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOJ_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOJ_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOJ_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOJ_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOJ_PIN7, 0U))

+#define VAL_GPIOJ_AFRH              (PIN_AFIO_AF(GPIOJ_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOJ_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOJ_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOJ_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOJ_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOJ_PIN13, 0U) |         \

+                                     PIN_AFIO_AF(GPIOJ_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOJ_PIN15, 0U))

+

+/*

+ * GPIOK setup:

+ *

+ * PK0  - PIN0                      (input pullup).

+ * PK1  - PIN1                      (input pullup).

+ * PK2  - PIN2                      (input pullup).

+ * PK3  - PIN3                      (input pullup).

+ * PK4  - PIN4                      (input pullup).

+ * PK5  - PIN5                      (input pullup).

+ * PK6  - PIN6                      (input pullup).

+ * PK7  - PIN7                      (input pullup).

+ * PK8  - PIN8                      (input pullup).

+ * PK9  - PIN9                      (input pullup).

+ * PK10 - PIN10                     (input pullup).

+ * PK11 - PIN11                     (input pullup).

+ * PK12 - PIN12                     (input pullup).

+ * PK13 - PIN13                     (input pullup).

+ * PK14 - PIN14                     (input pullup).

+ * PK15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOK_MODER             (PIN_MODE_INPUT(GPIOK_PIN0) |           \

+                                     PIN_MODE_INPUT(GPIOK_PIN1) |           \

+                                     PIN_MODE_INPUT(GPIOK_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOK_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOK_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOK_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOK_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOK_PIN7) |           \

+                                     PIN_MODE_INPUT(GPIOK_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOK_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOK_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOK_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOK_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOK_PIN13) |          \

+                                     PIN_MODE_INPUT(GPIOK_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOK_PIN15))

+#define VAL_GPIOK_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOK_PIN15))

+#define VAL_GPIOK_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOK_PIN0) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN1) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN2) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN3) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN4) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN5) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN6) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN7) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN8) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN9) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN10) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN11) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN12) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN13) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN14) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOK_PIN15))

+#define VAL_GPIOK_PUPDR             (PIN_PUPDR_PULLUP(GPIOK_PIN0) |         \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN1) |         \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN7) |         \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN13) |        \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOK_PIN15))

+#define VAL_GPIOK_ODR               (PIN_ODR_HIGH(GPIOK_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOK_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOK_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOK_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOK_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOK_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOK_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOK_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOK_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOK_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOK_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOK_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOK_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOK_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOK_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOK_PIN15))

+#define VAL_GPIOK_AFRL              (PIN_AFIO_AF(GPIOK_PIN0, 0U) |          \

+                                     PIN_AFIO_AF(GPIOK_PIN1, 0U) |          \

+                                     PIN_AFIO_AF(GPIOK_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOK_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOK_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOK_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOK_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOK_PIN7, 0U))

+#define VAL_GPIOK_AFRH              (PIN_AFIO_AF(GPIOK_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOK_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOK_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOK_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOK_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOK_PIN13, 0U) |         \

+                                     PIN_AFIO_AF(GPIOK_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOK_PIN15, 0U))

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#if !defined(_FROM_ASM_)

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void boardInit(void);

+#ifdef __cplusplus

+}

+#endif

+#endif /* _FROM_ASM_ */

+

+#endif /* BOARD_H */

diff --git a/firmware/source/board/l4/board.h b/firmware/source/board/l4/board.h
new file mode 100644
index 0000000..4b2642a
--- /dev/null
+++ b/firmware/source/board/l4/board.h
@@ -0,0 +1,1509 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/*

+ * This file has been automatically generated using ChibiStudio board

+ * generator plugin. Do not edit manually.

+ */

+

+#ifndef BOARD_H

+#define BOARD_H

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/*

+ * Setup for STMicroelectronics STM32 Nucleo64-L476RG board.

+ */

+

+/*

+ * Board identifier.

+ */

+#define BOARD_ST_NUCLEO64_L476RG

+#define BOARD_NAME                  "STMicroelectronics STM32 Nucleo64-L476RG"

+

+/*

+ * Board oscillators-related settings.

+ */

+#if !defined(STM32_LSECLK)

+#define STM32_LSECLK                32768U

+#endif

+

+#define STM32_LSEDRV                (3U << 3U)

+

+#if !defined(STM32_HSECLK)

+#define STM32_HSECLK                8000000U

+#endif

+

+#define STM32_HSE_BYPASS

+

+/*

+ * Board voltages.

+ * Required for performance limits calculation.

+ */

+#define STM32_VDD                   300U

+

+/*

+ * MCU type as defined in the ST header.

+ */

+#define STM32L476xx

+

+/*

+ * IO pins assignments.

+ */

+#define GPIOA_ARD_A0                0U

+#define GPIOA_ACD12_IN5             0U

+#define GPIOA_ARD_A1                1U

+#define GPIOA_ACD12_IN6             1U

+#define GPIOA_ARD_D1                2U

+#define GPIOA_USART2_TX             2U

+#define GPIOA_ARD_D0                3U

+#define GPIOA_USART2_RX             3U

+#define GPIOA_ARD_A2                4U

+#define GPIOA_ACD12_IN9             4U

+#define GPIOA_ARD_D13               5U

+#define GPIOA_LED_GREEN             5U

+#define GPIOA_ARD_D12               6U

+#define GPIOA_ARD_D11               7U

+#define GPIOA_ARD_D7                8U

+#define GPIOA_ARD_D8                9U

+#define GPIOA_ARD_D2                10U

+#define GPIOA_PIN11                 11U

+#define GPIOA_PIN12                 12U

+#define GPIOA_SWDIO                 13U

+#define GPIOA_SWCLK                 14U

+#define GPIOA_PIN15                 15U

+

+#define GPIOB_ARD_A3                0U

+#define GPIOB_ACD12_IN15            0U

+#define GPIOB_PIN1                  1U

+#define GPIOB_PIN2                  2U

+#define GPIOB_ARD_D3                3U

+#define GPIOB_SWO                   3U

+#define GPIOB_ARD_D5                4U

+#define GPIOB_ARD_D4                5U

+#define GPIOB_ARD_D10               6U

+#define GPIOB_PIN7                  7U

+#define GPIOB_ARD_D15               8U

+#define GPIOB_ARD_D14               9U

+#define GPIOB_ARD_D6                10U

+#define GPIOB_PIN11                 11U

+#define GPIOB_PIN12                 12U

+#define GPIOB_PIN13                 13U

+#define GPIOB_PIN14                 14U

+#define GPIOB_PIN15                 15U

+

+#define GPIOC_ARD_A5                0U

+#define GPIOC_ACD123_IN1            0U

+#define GPIOC_ARD_A4                1U

+#define GPIOC_ACD123_IN2            1U

+#define GPIOC_PIN2                  2U

+#define GPIOC_PIN3                  3U

+#define GPIOC_PIN4                  4U

+#define GPIOC_PIN5                  5U

+#define GPIOC_PIN6                  6U

+#define GPIOC_ARD_D9                7U

+#define GPIOC_PIN8                  8U

+#define GPIOC_PIN9                  9U

+#define GPIOC_PIN10                 10U

+#define GPIOC_PIN11                 11U

+#define GPIOC_PIN12                 12U

+#define GPIOC_BUTTON                13U

+#define GPIOC_OSC32_IN              14U

+#define GPIOC_OSC32_OUT             15U

+

+#define GPIOD_PIN0                  0U

+#define GPIOD_PIN1                  1U

+#define GPIOD_PIN2                  2U

+#define GPIOD_PIN3                  3U

+#define GPIOD_PIN4                  4U

+#define GPIOD_PIN5                  5U

+#define GPIOD_PIN6                  6U

+#define GPIOD_PIN7                  7U

+#define GPIOD_PIN8                  8U

+#define GPIOD_PIN9                  9U

+#define GPIOD_PIN10                 10U

+#define GPIOD_PIN11                 11U

+#define GPIOD_PIN12                 12U

+#define GPIOD_PIN13                 13U

+#define GPIOD_PIN14                 14U

+#define GPIOD_PIN15                 15U

+

+#define GPIOE_PIN0                  0U

+#define GPIOE_PIN1                  1U

+#define GPIOE_PIN2                  2U

+#define GPIOE_PIN3                  3U

+#define GPIOE_PIN4                  4U

+#define GPIOE_PIN5                  5U

+#define GPIOE_PIN6                  6U

+#define GPIOE_PIN7                  7U

+#define GPIOE_PIN8                  8U

+#define GPIOE_PIN9                  9U

+#define GPIOE_PIN10                 10U

+#define GPIOE_PIN11                 11U

+#define GPIOE_PIN12                 12U

+#define GPIOE_PIN13                 13U

+#define GPIOE_PIN14                 14U

+#define GPIOE_PIN15                 15U

+

+#define GPIOF_PIN0                  0U

+#define GPIOF_PIN1                  1U

+#define GPIOF_PIN2                  2U

+#define GPIOF_PIN3                  3U

+#define GPIOF_PIN4                  4U

+#define GPIOF_PIN5                  5U

+#define GPIOF_PIN6                  6U

+#define GPIOF_PIN7                  7U

+#define GPIOF_PIN8                  8U

+#define GPIOF_PIN9                  9U

+#define GPIOF_PIN10                 10U

+#define GPIOF_PIN11                 11U

+#define GPIOF_PIN12                 12U

+#define GPIOF_PIN13                 13U

+#define GPIOF_PIN14                 14U

+#define GPIOF_PIN15                 15U

+

+#define GPIOG_PIN0                  0U

+#define GPIOG_PIN1                  1U

+#define GPIOG_PIN2                  2U

+#define GPIOG_PIN3                  3U

+#define GPIOG_PIN4                  4U

+#define GPIOG_PIN5                  5U

+#define GPIOG_PIN6                  6U

+#define GPIOG_PIN7                  7U

+#define GPIOG_PIN8                  8U

+#define GPIOG_PIN9                  9U

+#define GPIOG_PIN10                 10U

+#define GPIOG_PIN11                 11U

+#define GPIOG_PIN12                 12U

+#define GPIOG_PIN13                 13U

+#define GPIOG_PIN14                 14U

+#define GPIOG_PIN15                 15U

+

+#define GPIOH_OSC_IN                0U

+#define GPIOH_OSC_OUT               1U

+#define GPIOH_PIN2                  2U

+#define GPIOH_PIN3                  3U

+#define GPIOH_PIN4                  4U

+#define GPIOH_PIN5                  5U

+#define GPIOH_PIN6                  6U

+#define GPIOH_PIN7                  7U

+#define GPIOH_PIN8                  8U

+#define GPIOH_PIN9                  9U

+#define GPIOH_PIN10                 10U

+#define GPIOH_PIN11                 11U

+#define GPIOH_PIN12                 12U

+#define GPIOH_PIN13                 13U

+#define GPIOH_PIN14                 14U

+#define GPIOH_PIN15                 15U

+

+/*

+ * IO lines assignments.

+ */

+#define LINE_ARD_A0                 PAL_LINE(GPIOA, 0U)

+#define LINE_ACD12_IN5              PAL_LINE(GPIOA, 0U)

+#define LINE_ARD_A1                 PAL_LINE(GPIOA, 1U)

+#define LINE_ACD12_IN6              PAL_LINE(GPIOA, 1U)

+#define LINE_ARD_D1                 PAL_LINE(GPIOA, 2U)

+#define LINE_USART2_TX              PAL_LINE(GPIOA, 2U)

+#define LINE_ARD_D0                 PAL_LINE(GPIOA, 3U)

+#define LINE_USART2_RX              PAL_LINE(GPIOA, 3U)

+#define LINE_ARD_A2                 PAL_LINE(GPIOA, 4U)

+#define LINE_ACD12_IN9              PAL_LINE(GPIOA, 4U)

+#define LINE_ARD_D13                PAL_LINE(GPIOA, 5U)

+//#define LINE_LED_GREEN              PAL_LINE(GPIOA, 5U)

+#define LINE_ARD_D12                PAL_LINE(GPIOA, 6U)

+#define LINE_ARD_D11                PAL_LINE(GPIOA, 7U)

+#define LINE_ARD_D7                 PAL_LINE(GPIOA, 8U)

+#define LINE_ARD_D8                 PAL_LINE(GPIOA, 9U)

+#define LINE_ARD_D2                 PAL_LINE(GPIOA, 10U)

+#define LINE_SWDIO                  PAL_LINE(GPIOA, 13U)

+#define LINE_SWCLK                  PAL_LINE(GPIOA, 14U)

+#define LINE_ARD_A3                 PAL_LINE(GPIOB, 0U)

+#define LINE_ACD12_IN15             PAL_LINE(GPIOB, 0U)

+#define LINE_ARD_D3                 PAL_LINE(GPIOB, 3U)

+#define LINE_SWO                    PAL_LINE(GPIOB, 3U)

+#define LINE_ARD_D5                 PAL_LINE(GPIOB, 4U)

+#define LINE_ARD_D4                 PAL_LINE(GPIOB, 5U)

+#define LINE_ARD_D10                PAL_LINE(GPIOB, 6U)

+#define LINE_ARD_D15                PAL_LINE(GPIOB, 8U)

+#define LINE_ARD_D14                PAL_LINE(GPIOB, 9U)

+#define LINE_ARD_D6                 PAL_LINE(GPIOB, 10U)

+#define LINE_ARD_A5                 PAL_LINE(GPIOC, 0U)

+#define LINE_ACD123_IN1             PAL_LINE(GPIOC, 0U)

+#define LINE_ARD_A4                 PAL_LINE(GPIOC, 1U)

+#define LINE_ACD123_IN2             PAL_LINE(GPIOC, 1U)

+#define LINE_ARD_D9                 PAL_LINE(GPIOC, 7U)

+#define LINE_BUTTON                 PAL_LINE(GPIOC, 13U)

+#define LINE_OSC32_IN               PAL_LINE(GPIOC, 14U)

+#define LINE_OSC32_OUT              PAL_LINE(GPIOC, 15U)

+#define LINE_OSC_IN                 PAL_LINE(GPIOH, 0U)

+#define LINE_OSC_OUT                PAL_LINE(GPIOH, 1U)

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/*

+ * I/O ports initial setup, this configuration is established soon after reset

+ * in the initialization code.

+ * Please refer to the STM32 Reference Manual for details.

+ */

+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2U))

+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2U))

+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2U))

+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2U))

+#define PIN_ODR_LOW(n)              (0U << (n))

+#define PIN_ODR_HIGH(n)             (1U << (n))

+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))

+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))

+#define PIN_OSPEED_VERYLOW(n)       (0U << ((n) * 2U))

+#define PIN_OSPEED_LOW(n)           (1U << ((n) * 2U))

+#define PIN_OSPEED_MEDIUM(n)        (2U << ((n) * 2U))

+#define PIN_OSPEED_HIGH(n)          (3U << ((n) * 2U))

+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2U))

+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2U))

+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2U))

+#define PIN_AFIO_AF(n, v)           ((v) << (((n) % 8U) * 4U))

+#define PIN_ASCR_DISABLED(n)        (0U << (n))

+#define PIN_ASCR_ENABLED(n)         (1U << (n))

+#define PIN_LOCKR_DISABLED(n)       (0U << (n))

+#define PIN_LOCKR_ENABLED(n)        (1U << (n))

+

+/*

+ * GPIOA setup:

+ *

+ * PA0  - ARD_A0 ACD12_IN5          (analog).

+ * PA1  - ARD_A1 ACD12_IN6          (analog).

+ * PA2  - ARD_D1 USART2_TX          (alternate 7).

+ * PA3  - ARD_D0 USART2_RX          (alternate 7).

+ * PA4  - ARD_A2 ACD12_IN9          (analog).

+ * PA5  - ARD_D13 LED_GREEN         (output pushpull maximum).

+ * PA6  - ARD_D12                   (analog).

+ * PA7  - ARD_D11                   (analog).

+ * PA8  - ARD_D7                    (analog).

+ * PA9  - ARD_D8                    (analog).

+ * PA10 - ARD_D2                    (analog).

+ * PA11 - PIN11                     (analog).

+ * PA12 - PIN12                     (analog).

+ * PA13 - SWDIO                     (alternate 0).

+ * PA14 - SWCLK                     (alternate 0).

+ * PA15 - PIN15                     (analog).

+ */

+#define VAL_GPIOA_MODER             (PIN_MODE_ANALOG(GPIOA_ARD_A0) |        \

+                                     PIN_MODE_ANALOG(GPIOA_ARD_A1) |        \

+                                     PIN_MODE_ALTERNATE(GPIOA_ARD_D1) |     \

+                                     PIN_MODE_ALTERNATE(GPIOA_ARD_D0) |     \

+                                     PIN_MODE_ANALOG(GPIOA_ARD_A2) |        \

+                                     PIN_MODE_OUTPUT(GPIOA_ARD_D13) |       \

+                                     PIN_MODE_ANALOG(GPIOA_ARD_D12) |       \

+                                     PIN_MODE_ANALOG(GPIOA_ARD_D11) |       \

+                                     PIN_MODE_ANALOG(GPIOA_ARD_D7) |        \

+                                     PIN_MODE_ANALOG(GPIOA_ARD_D8) |        \

+                                     PIN_MODE_ANALOG(GPIOA_ARD_D2) |        \

+                                     PIN_MODE_ANALOG(GPIOA_PIN11) |         \

+                                     PIN_MODE_ANALOG(GPIOA_PIN12) |         \

+                                     PIN_MODE_ALTERNATE(GPIOA_SWDIO) |      \

+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |      \

+                                     PIN_MODE_ANALOG(GPIOA_PIN15))

+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN15))

+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_HIGH(GPIOA_ARD_A0) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_A1) |        \

+                                     PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) |      \

+                                     PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) |      \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_A2) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_D13) |       \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_D12) |       \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_D11) |       \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_D7) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_D8) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_D2) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_PIN11) |         \

+                                     PIN_OSPEED_HIGH(GPIOA_PIN12) |         \

+                                     PIN_OSPEED_HIGH(GPIOA_SWDIO) |         \

+                                     PIN_OSPEED_HIGH(GPIOA_SWCLK) |         \

+                                     PIN_OSPEED_HIGH(GPIOA_PIN15))

+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_ARD_A0) |     \

+                                     PIN_PUPDR_FLOATING(GPIOA_ARD_A1) |     \

+                                     PIN_PUPDR_FLOATING(GPIOA_ARD_D1) |     \

+                                     PIN_PUPDR_FLOATING(GPIOA_ARD_D0) |     \

+                                     PIN_PUPDR_FLOATING(GPIOA_ARD_A2) |     \

+                                     PIN_PUPDR_FLOATING(GPIOA_ARD_D13) |    \

+                                     PIN_PUPDR_FLOATING(GPIOA_ARD_D12) |    \

+                                     PIN_PUPDR_FLOATING(GPIOA_ARD_D11) |    \

+                                     PIN_PUPDR_FLOATING(GPIOA_ARD_D7) |     \

+                                     PIN_PUPDR_FLOATING(GPIOA_ARD_D8) |     \

+                                     PIN_PUPDR_FLOATING(GPIOA_ARD_D2) |     \

+                                     PIN_PUPDR_FLOATING(GPIOA_PIN11) |      \

+                                     PIN_PUPDR_FLOATING(GPIOA_PIN12) |      \

+                                     PIN_PUPDR_PULLUP(GPIOA_SWDIO) |        \

+                                     PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) |      \

+                                     PIN_PUPDR_FLOATING(GPIOA_PIN15))

+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_ARD_A0) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_A1) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_D1) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_D0) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_A2) |           \

+                                     PIN_ODR_LOW(GPIOA_ARD_D13) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_D12) |          \

+                                     PIN_ODR_HIGH(GPIOA_ARD_D11) |          \

+                                     PIN_ODR_HIGH(GPIOA_ARD_D7) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_D8) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_D2) |           \

+                                     PIN_ODR_HIGH(GPIOA_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOA_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOA_SWDIO) |            \

+                                     PIN_ODR_HIGH(GPIOA_SWCLK) |            \

+                                     PIN_ODR_HIGH(GPIOA_PIN15))

+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) |        \

+                                     PIN_AFIO_AF(GPIOA_ARD_A1, 0U) |        \

+                                     PIN_AFIO_AF(GPIOA_ARD_D1, 7U) |        \

+                                     PIN_AFIO_AF(GPIOA_ARD_D0, 7U) |        \

+                                     PIN_AFIO_AF(GPIOA_ARD_A2, 0U) |        \

+                                     PIN_AFIO_AF(GPIOA_ARD_D13, 0U) |       \

+                                     PIN_AFIO_AF(GPIOA_ARD_D12, 0U) |       \

+                                     PIN_AFIO_AF(GPIOA_ARD_D11, 0U))

+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) |        \

+                                     PIN_AFIO_AF(GPIOA_ARD_D8, 0U) |        \

+                                     PIN_AFIO_AF(GPIOA_ARD_D2, 0U) |        \

+                                     PIN_AFIO_AF(GPIOA_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOA_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOA_SWDIO, 0U) |         \

+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0U) |         \

+                                     PIN_AFIO_AF(GPIOA_PIN15, 0U))

+#define VAL_GPIOA_ASCR              (PIN_ASCR_DISABLED(GPIOA_ARD_A0) |      \

+                                     PIN_ASCR_DISABLED(GPIOA_ARD_A1) |      \

+                                     PIN_ASCR_DISABLED(GPIOA_ARD_D1) |      \

+                                     PIN_ASCR_DISABLED(GPIOA_ARD_D0) |      \

+                                     PIN_ASCR_DISABLED(GPIOA_ARD_A2) |      \

+                                     PIN_ASCR_DISABLED(GPIOA_ARD_D13) |     \

+                                     PIN_ASCR_DISABLED(GPIOA_ARD_D12) |     \

+                                     PIN_ASCR_DISABLED(GPIOA_ARD_D11) |     \

+                                     PIN_ASCR_DISABLED(GPIOA_ARD_D7) |      \

+                                     PIN_ASCR_DISABLED(GPIOA_ARD_D8) |      \

+                                     PIN_ASCR_DISABLED(GPIOA_ARD_D2) |      \

+                                     PIN_ASCR_DISABLED(GPIOA_PIN11) |       \

+                                     PIN_ASCR_DISABLED(GPIOA_PIN12) |       \

+                                     PIN_ASCR_DISABLED(GPIOA_SWDIO) |       \

+                                     PIN_ASCR_DISABLED(GPIOA_SWCLK) |       \

+                                     PIN_ASCR_DISABLED(GPIOA_PIN15))

+#define VAL_GPIOA_LOCKR             (PIN_LOCKR_DISABLED(GPIOA_ARD_A0) |     \

+                                     PIN_LOCKR_DISABLED(GPIOA_ARD_A1) |     \

+                                     PIN_LOCKR_DISABLED(GPIOA_ARD_D1) |     \

+                                     PIN_LOCKR_DISABLED(GPIOA_ARD_D0) |     \

+                                     PIN_LOCKR_DISABLED(GPIOA_ARD_A2) |     \

+                                     PIN_LOCKR_DISABLED(GPIOA_ARD_D13) |    \

+                                     PIN_LOCKR_DISABLED(GPIOA_ARD_D12) |    \

+                                     PIN_LOCKR_DISABLED(GPIOA_ARD_D11) |    \

+                                     PIN_LOCKR_DISABLED(GPIOA_ARD_D7) |     \

+                                     PIN_LOCKR_DISABLED(GPIOA_ARD_D8) |     \

+                                     PIN_LOCKR_DISABLED(GPIOA_ARD_D2) |     \

+                                     PIN_LOCKR_DISABLED(GPIOA_PIN11) |      \

+                                     PIN_LOCKR_DISABLED(GPIOA_PIN12) |      \

+                                     PIN_LOCKR_DISABLED(GPIOA_SWDIO) |      \

+                                     PIN_LOCKR_DISABLED(GPIOA_SWCLK) |      \

+                                     PIN_LOCKR_DISABLED(GPIOA_PIN15))

+

+/*

+ * GPIOB setup:

+ *

+ * PB0  - ARD_A3 ACD12_IN15         (analog).

+ * PB1  - PIN1                      (analog).

+ * PB2  - PIN2                      (analog).

+ * PB3  - ARD_D3 SWO                (analog).

+ * PB4  - ARD_D5                    (analog).

+ * PB5  - ARD_D4                    (analog).

+ * PB6  - ARD_D10                   (analog).

+ * PB7  - PIN7                      (analog).

+ * PB8  - ARD_D15                   (analog).

+ * PB9  - ARD_D14                   (analog).

+ * PB10 - ARD_D6                    (analog).

+ * PB11 - PIN11                     (analog).

+ * PB12 - PIN12                     (analog).

+ * PB13 - PIN13                     (analog).

+ * PB14 - PIN14                     (analog).

+ * PB15 - PIN15                     (analog).

+ */

+#define VAL_GPIOB_MODER             (PIN_MODE_ANALOG(GPIOB_ARD_A3) |        \

+                                     PIN_MODE_ANALOG(GPIOB_PIN1) |          \

+                                     PIN_MODE_ANALOG(GPIOB_PIN2) |          \

+                                     PIN_MODE_ANALOG(GPIOB_ARD_D3) |        \

+                                     PIN_MODE_ANALOG(GPIOB_ARD_D5) |        \

+                                     PIN_MODE_ANALOG(GPIOB_ARD_D4) |        \

+                                     PIN_MODE_ANALOG(GPIOB_ARD_D10) |       \

+                                     PIN_MODE_ANALOG(GPIOB_PIN7) |          \

+                                     PIN_MODE_ANALOG(GPIOB_ARD_D15) |       \

+                                     PIN_MODE_ANALOG(GPIOB_ARD_D14) |       \

+                                     PIN_MODE_ANALOG(GPIOB_ARD_D6) |        \

+                                     PIN_MODE_ANALOG(GPIOB_PIN11) |         \

+                                     PIN_MODE_ANALOG(GPIOB_PIN12) |         \

+                                     PIN_MODE_ANALOG(GPIOB_PIN13) |         \

+                                     PIN_MODE_ANALOG(GPIOB_PIN14) |         \

+                                     PIN_MODE_ANALOG(GPIOB_PIN15))

+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_ARD_D3) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))

+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_HIGH(GPIOB_ARD_A3) |        \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN1) |          \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN2) |          \

+                                     PIN_OSPEED_HIGH(GPIOB_ARD_D3) |        \

+                                     PIN_OSPEED_HIGH(GPIOB_ARD_D5) |        \

+                                     PIN_OSPEED_HIGH(GPIOB_ARD_D4) |        \

+                                     PIN_OSPEED_HIGH(GPIOB_ARD_D10) |       \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN7) |          \

+                                     PIN_OSPEED_HIGH(GPIOB_ARD_D15) |       \

+                                     PIN_OSPEED_HIGH(GPIOB_ARD_D14) |       \

+                                     PIN_OSPEED_HIGH(GPIOB_ARD_D6) |        \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN11) |         \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN12) |         \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN13) |         \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN14) |         \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN15))

+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_FLOATING(GPIOB_ARD_A3) |     \

+                                     PIN_PUPDR_FLOATING(GPIOB_PIN1) |       \

+                                     PIN_PUPDR_FLOATING(GPIOB_PIN2) |       \

+                                     PIN_PUPDR_FLOATING(GPIOB_ARD_D3) |     \

+                                     PIN_PUPDR_FLOATING(GPIOB_ARD_D5) |     \

+                                     PIN_PUPDR_FLOATING(GPIOB_ARD_D4) |     \

+                                     PIN_PUPDR_FLOATING(GPIOB_ARD_D10) |    \

+                                     PIN_PUPDR_FLOATING(GPIOB_PIN7) |       \

+                                     PIN_PUPDR_FLOATING(GPIOB_ARD_D15) |    \

+                                     PIN_PUPDR_FLOATING(GPIOB_ARD_D14) |    \

+                                     PIN_PUPDR_FLOATING(GPIOB_ARD_D6) |     \

+                                     PIN_PUPDR_FLOATING(GPIOB_PIN11) |      \

+                                     PIN_PUPDR_FLOATING(GPIOB_PIN12) |      \

+                                     PIN_PUPDR_FLOATING(GPIOB_PIN13) |      \

+                                     PIN_PUPDR_FLOATING(GPIOB_PIN14) |      \

+                                     PIN_PUPDR_FLOATING(GPIOB_PIN15))

+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_ARD_A3) |           \

+                                     PIN_ODR_HIGH(GPIOB_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOB_ARD_D3) |           \

+                                     PIN_ODR_HIGH(GPIOB_ARD_D5) |           \

+                                     PIN_ODR_HIGH(GPIOB_ARD_D4) |           \

+                                     PIN_ODR_HIGH(GPIOB_ARD_D10) |          \

+                                     PIN_ODR_HIGH(GPIOB_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOB_ARD_D15) |          \

+                                     PIN_ODR_HIGH(GPIOB_ARD_D14) |          \

+                                     PIN_ODR_HIGH(GPIOB_ARD_D6) |           \

+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOB_PIN15))

+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) |        \

+                                     PIN_AFIO_AF(GPIOB_PIN1, 0U) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOB_ARD_D3, 0U) |        \

+                                     PIN_AFIO_AF(GPIOB_ARD_D5, 0U) |        \

+                                     PIN_AFIO_AF(GPIOB_ARD_D4, 0U) |        \

+                                     PIN_AFIO_AF(GPIOB_ARD_D10, 0U) |       \

+                                     PIN_AFIO_AF(GPIOB_PIN7, 0U))

+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) |       \

+                                     PIN_AFIO_AF(GPIOB_ARD_D14, 0U) |       \

+                                     PIN_AFIO_AF(GPIOB_ARD_D6, 0U) |        \

+                                     PIN_AFIO_AF(GPIOB_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOB_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOB_PIN13, 0U) |         \

+                                     PIN_AFIO_AF(GPIOB_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOB_PIN15, 0U))

+#define VAL_GPIOB_ASCR              (PIN_ASCR_DISABLED(GPIOB_ARD_A3) |      \

+                                     PIN_ASCR_DISABLED(GPIOB_PIN1) |        \

+                                     PIN_ASCR_DISABLED(GPIOB_PIN2) |        \

+                                     PIN_ASCR_DISABLED(GPIOB_ARD_D3) |      \

+                                     PIN_ASCR_DISABLED(GPIOB_ARD_D5) |      \

+                                     PIN_ASCR_DISABLED(GPIOB_ARD_D4) |      \

+                                     PIN_ASCR_DISABLED(GPIOB_ARD_D10) |     \

+                                     PIN_ASCR_DISABLED(GPIOB_PIN7) |        \

+                                     PIN_ASCR_DISABLED(GPIOB_ARD_D15) |     \

+                                     PIN_ASCR_DISABLED(GPIOB_ARD_D14) |     \

+                                     PIN_ASCR_DISABLED(GPIOB_ARD_D6) |      \

+                                     PIN_ASCR_DISABLED(GPIOB_PIN11) |       \

+                                     PIN_ASCR_DISABLED(GPIOB_PIN12) |       \

+                                     PIN_ASCR_DISABLED(GPIOB_PIN13) |       \

+                                     PIN_ASCR_DISABLED(GPIOB_PIN14) |       \

+                                     PIN_ASCR_DISABLED(GPIOB_PIN15))

+#define VAL_GPIOB_LOCKR             (PIN_LOCKR_DISABLED(GPIOB_ARD_A3) |     \

+                                     PIN_LOCKR_DISABLED(GPIOB_PIN1) |       \

+                                     PIN_LOCKR_DISABLED(GPIOB_PIN2) |       \

+                                     PIN_LOCKR_DISABLED(GPIOB_ARD_D3) |     \

+                                     PIN_LOCKR_DISABLED(GPIOB_ARD_D5) |     \

+                                     PIN_LOCKR_DISABLED(GPIOB_ARD_D4) |     \

+                                     PIN_LOCKR_DISABLED(GPIOB_ARD_D10) |    \

+                                     PIN_LOCKR_DISABLED(GPIOB_PIN7) |       \

+                                     PIN_LOCKR_DISABLED(GPIOB_ARD_D15) |    \

+                                     PIN_LOCKR_DISABLED(GPIOB_ARD_D14) |    \

+                                     PIN_LOCKR_DISABLED(GPIOB_ARD_D6) |     \

+                                     PIN_LOCKR_DISABLED(GPIOB_PIN11) |      \

+                                     PIN_LOCKR_DISABLED(GPIOB_PIN12) |      \

+                                     PIN_LOCKR_DISABLED(GPIOB_PIN13) |      \

+                                     PIN_LOCKR_DISABLED(GPIOB_PIN14) |      \

+                                     PIN_LOCKR_DISABLED(GPIOB_PIN15))

+

+/*

+ * GPIOC setup:

+ *

+ * PC0  - ARD_A5 ACD123_IN1         (analog).

+ * PC1  - ARD_A4 ACD123_IN2         (analog).

+ * PC2  - PIN2                      (analog).

+ * PC3  - PIN3                      (analog).

+ * PC4  - PIN4                      (analog).

+ * PC5  - PIN5                      (analog).

+ * PC6  - PIN6                      (analog).

+ * PC7  - ARD_D9                    (analog).

+ * PC8  - PIN8                      (analog).

+ * PC9  - PIN9                      (analog).

+ * PC10 - PIN10                     (analog).

+ * PC11 - PIN11                     (analog).

+ * PC12 - PIN12                     (analog).

+ * PC13 - BUTTON                    (input floating).

+ * PC14 - OSC32_IN                  (input floating).

+ * PC15 - OSC32_OUT                 (input floating).

+ */

+#define VAL_GPIOC_MODER             (PIN_MODE_ANALOG(GPIOC_ARD_A5) |        \

+                                     PIN_MODE_ANALOG(GPIOC_ARD_A4) |        \

+                                     PIN_MODE_ANALOG(GPIOC_PIN2) |          \

+                                     PIN_MODE_ANALOG(GPIOC_PIN3) |          \

+                                     PIN_MODE_ANALOG(GPIOC_PIN4) |          \

+                                     PIN_MODE_ANALOG(GPIOC_PIN5) |          \

+                                     PIN_MODE_ANALOG(GPIOC_PIN6) |          \

+                                     PIN_MODE_ANALOG(GPIOC_ARD_D9) |        \

+                                     PIN_MODE_ANALOG(GPIOC_PIN8) |          \

+                                     PIN_MODE_ANALOG(GPIOC_PIN9) |          \

+                                     PIN_MODE_ANALOG(GPIOC_PIN10) |         \

+                                     PIN_MODE_ANALOG(GPIOC_PIN11) |         \

+                                     PIN_MODE_ANALOG(GPIOC_PIN12) |         \

+                                     PIN_MODE_INPUT(GPIOC_BUTTON) |         \

+                                     PIN_MODE_INPUT(GPIOC_OSC32_IN) |       \

+                                     PIN_MODE_INPUT(GPIOC_OSC32_OUT))

+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_ARD_D9) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) |   \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))

+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_HIGH(GPIOC_ARD_A5) |        \

+                                     PIN_OSPEED_HIGH(GPIOC_ARD_A4) |        \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN2) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN3) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN4) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN5) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN6) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_ARD_D9) |        \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN8) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN9) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN10) |         \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN11) |         \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN12) |         \

+                                     PIN_OSPEED_HIGH(GPIOC_BUTTON) |        \

+                                     PIN_OSPEED_HIGH(GPIOC_OSC32_IN) |      \

+                                     PIN_OSPEED_HIGH(GPIOC_OSC32_OUT))

+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_FLOATING(GPIOC_ARD_A5) |     \

+                                     PIN_PUPDR_FLOATING(GPIOC_ARD_A4) |     \

+                                     PIN_PUPDR_FLOATING(GPIOC_PIN2) |       \

+                                     PIN_PUPDR_FLOATING(GPIOC_PIN3) |       \

+                                     PIN_PUPDR_FLOATING(GPIOC_PIN4) |       \

+                                     PIN_PUPDR_FLOATING(GPIOC_PIN5) |       \

+                                     PIN_PUPDR_FLOATING(GPIOC_PIN6) |       \

+                                     PIN_PUPDR_FLOATING(GPIOC_ARD_D9) |     \

+                                     PIN_PUPDR_FLOATING(GPIOC_PIN8) |       \

+                                     PIN_PUPDR_FLOATING(GPIOC_PIN9) |       \

+                                     PIN_PUPDR_FLOATING(GPIOC_PIN10) |      \

+                                     PIN_PUPDR_FLOATING(GPIOC_PIN11) |      \

+                                     PIN_PUPDR_FLOATING(GPIOC_PIN12) |      \

+                                     PIN_PUPDR_FLOATING(GPIOC_BUTTON) |     \

+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) |   \

+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))

+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_ARD_A5) |           \

+                                     PIN_ODR_HIGH(GPIOC_ARD_A4) |           \

+                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOC_ARD_D9) |           \

+                                     PIN_ODR_HIGH(GPIOC_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOC_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOC_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOC_BUTTON) |           \

+                                     PIN_ODR_HIGH(GPIOC_OSC32_IN) |         \

+                                     PIN_ODR_HIGH(GPIOC_OSC32_OUT))

+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) |        \

+                                     PIN_AFIO_AF(GPIOC_ARD_A4, 0U) |        \

+                                     PIN_AFIO_AF(GPIOC_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOC_ARD_D9, 0U))

+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOC_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOC_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOC_BUTTON, 0U) |        \

+                                     PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) |      \

+                                     PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))

+#define VAL_GPIOC_ASCR              (PIN_ASCR_DISABLED(GPIOC_ARD_A5) |      \

+                                     PIN_ASCR_DISABLED(GPIOC_ARD_A4) |      \

+                                     PIN_ASCR_DISABLED(GPIOC_PIN2) |        \

+                                     PIN_ASCR_DISABLED(GPIOC_PIN3) |        \

+                                     PIN_ASCR_DISABLED(GPIOC_PIN4) |        \

+                                     PIN_ASCR_DISABLED(GPIOC_PIN5) |        \

+                                     PIN_ASCR_DISABLED(GPIOC_PIN6) |        \

+                                     PIN_ASCR_DISABLED(GPIOC_ARD_D9) |      \

+                                     PIN_ASCR_DISABLED(GPIOC_PIN8) |        \

+                                     PIN_ASCR_DISABLED(GPIOC_PIN9) |        \

+                                     PIN_ASCR_DISABLED(GPIOC_PIN10) |       \

+                                     PIN_ASCR_DISABLED(GPIOC_PIN11) |       \

+                                     PIN_ASCR_DISABLED(GPIOC_PIN12) |       \

+                                     PIN_ASCR_DISABLED(GPIOC_BUTTON) |      \

+                                     PIN_ASCR_DISABLED(GPIOC_OSC32_IN) |    \

+                                     PIN_ASCR_DISABLED(GPIOC_OSC32_OUT))

+#define VAL_GPIOC_LOCKR             (PIN_LOCKR_DISABLED(GPIOC_ARD_A5) |     \

+                                     PIN_LOCKR_DISABLED(GPIOC_ARD_A4) |     \

+                                     PIN_LOCKR_DISABLED(GPIOC_PIN2) |       \

+                                     PIN_LOCKR_DISABLED(GPIOC_PIN3) |       \

+                                     PIN_LOCKR_DISABLED(GPIOC_PIN4) |       \

+                                     PIN_LOCKR_DISABLED(GPIOC_PIN5) |       \

+                                     PIN_LOCKR_DISABLED(GPIOC_PIN6) |       \

+                                     PIN_LOCKR_DISABLED(GPIOC_ARD_D9) |     \

+                                     PIN_LOCKR_DISABLED(GPIOC_PIN8) |       \

+                                     PIN_LOCKR_DISABLED(GPIOC_PIN9) |       \

+                                     PIN_LOCKR_DISABLED(GPIOC_PIN10) |      \

+                                     PIN_LOCKR_DISABLED(GPIOC_PIN11) |      \

+                                     PIN_LOCKR_DISABLED(GPIOC_PIN12) |      \

+                                     PIN_LOCKR_DISABLED(GPIOC_BUTTON) |     \

+                                     PIN_LOCKR_DISABLED(GPIOC_OSC32_IN) |   \

+                                     PIN_LOCKR_DISABLED(GPIOC_OSC32_OUT))

+

+/*

+ * GPIOD setup:

+ *

+ * PD0  - PIN0                      (analog).

+ * PD1  - PIN1                      (analog).

+ * PD2  - PIN2                      (analog).

+ * PD3  - PIN3                      (analog).

+ * PD4  - PIN4                      (analog).

+ * PD5  - PIN5                      (analog).

+ * PD6  - PIN6                      (analog).

+ * PD7  - PIN7                      (analog).

+ * PD8  - PIN8                      (analog).

+ * PD9  - PIN9                      (analog).

+ * PD10 - PIN10                     (analog).

+ * PD11 - PIN11                     (analog).

+ * PD12 - PIN12                     (analog).

+ * PD13 - PIN13                     (analog).

+ * PD14 - PIN14                     (analog).

+ * PD15 - PIN15                     (analog).

+ */

+#define VAL_GPIOD_MODER             (PIN_MODE_ANALOG(GPIOD_PIN0) |          \

+                                     PIN_MODE_ANALOG(GPIOD_PIN1) |          \

+                                     PIN_MODE_ANALOG(GPIOD_PIN2) |          \

+                                     PIN_MODE_ANALOG(GPIOD_PIN3) |          \

+                                     PIN_MODE_ANALOG(GPIOD_PIN4) |          \

+                                     PIN_MODE_ANALOG(GPIOD_PIN5) |          \

+                                     PIN_MODE_ANALOG(GPIOD_PIN6) |          \

+                                     PIN_MODE_ANALOG(GPIOD_PIN7) |          \

+                                     PIN_MODE_ANALOG(GPIOD_PIN8) |          \

+                                     PIN_MODE_ANALOG(GPIOD_PIN9) |          \

+                                     PIN_MODE_ANALOG(GPIOD_PIN10) |         \

+                                     PIN_MODE_ANALOG(GPIOD_PIN11) |         \

+                                     PIN_MODE_ANALOG(GPIOD_PIN12) |         \

+                                     PIN_MODE_ANALOG(GPIOD_PIN13) |         \

+                                     PIN_MODE_ANALOG(GPIOD_PIN14) |         \

+                                     PIN_MODE_ANALOG(GPIOD_PIN15))

+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15))

+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_HIGH(GPIOD_PIN0) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN1) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN2) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN3) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN4) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN5) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN6) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN7) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN8) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN9) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN10) |         \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN11) |         \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN12) |         \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN13) |         \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN14) |         \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN15))

+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_FLOATING(GPIOD_PIN0) |       \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN1) |       \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN2) |       \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN3) |       \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN4) |       \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN5) |       \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN6) |       \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN7) |       \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN8) |       \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN9) |       \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN10) |      \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN11) |      \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN12) |      \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN13) |      \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN14) |      \

+                                     PIN_PUPDR_FLOATING(GPIOD_PIN15))

+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN15))

+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN1, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN7, 0U))

+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOD_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOD_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOD_PIN13, 0U) |         \

+                                     PIN_AFIO_AF(GPIOD_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOD_PIN15, 0U))

+#define VAL_GPIOD_ASCR              (PIN_ASCR_DISABLED(GPIOD_PIN0) |        \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN1) |        \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN2) |        \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN3) |        \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN4) |        \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN5) |        \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN6) |        \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN7) |        \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN8) |        \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN9) |        \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN10) |       \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN11) |       \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN12) |       \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN13) |       \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN14) |       \

+                                     PIN_ASCR_DISABLED(GPIOD_PIN15))

+#define VAL_GPIOD_LOCKR             (PIN_LOCKR_DISABLED(GPIOD_PIN0) |       \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN1) |       \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN2) |       \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN3) |       \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN4) |       \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN5) |       \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN6) |       \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN7) |       \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN8) |       \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN9) |       \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN10) |      \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN11) |      \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN12) |      \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN13) |      \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN14) |      \

+                                     PIN_LOCKR_DISABLED(GPIOD_PIN15))

+

+/*

+ * GPIOE setup:

+ *

+ * PE0  - PIN0                      (analog).

+ * PE1  - PIN1                      (analog).

+ * PE2  - PIN2                      (analog).

+ * PE3  - PIN3                      (analog).

+ * PE4  - PIN4                      (analog).

+ * PE5  - PIN5                      (analog).

+ * PE6  - PIN6                      (analog).

+ * PE7  - PIN7                      (analog).

+ * PE8  - PIN8                      (analog).

+ * PE9  - PIN9                      (analog).

+ * PE10 - PIN10                     (analog).

+ * PE11 - PIN11                     (analog).

+ * PE12 - PIN12                     (analog).

+ * PE13 - PIN13                     (analog).

+ * PE14 - PIN14                     (analog).

+ * PE15 - PIN15                     (analog).

+ */

+#define VAL_GPIOE_MODER             (PIN_MODE_ANALOG(GPIOE_PIN0) |          \

+                                     PIN_MODE_ANALOG(GPIOE_PIN1) |          \

+                                     PIN_MODE_ANALOG(GPIOE_PIN2) |          \

+                                     PIN_MODE_ANALOG(GPIOE_PIN3) |          \

+                                     PIN_MODE_ANALOG(GPIOE_PIN4) |          \

+                                     PIN_MODE_ANALOG(GPIOE_PIN5) |          \

+                                     PIN_MODE_ANALOG(GPIOE_PIN6) |          \

+                                     PIN_MODE_ANALOG(GPIOE_PIN7) |          \

+                                     PIN_MODE_ANALOG(GPIOE_PIN8) |          \

+                                     PIN_MODE_ANALOG(GPIOE_PIN9) |          \

+                                     PIN_MODE_ANALOG(GPIOE_PIN10) |         \

+                                     PIN_MODE_ANALOG(GPIOE_PIN11) |         \

+                                     PIN_MODE_ANALOG(GPIOE_PIN12) |         \

+                                     PIN_MODE_ANALOG(GPIOE_PIN13) |         \

+                                     PIN_MODE_ANALOG(GPIOE_PIN14) |         \

+                                     PIN_MODE_ANALOG(GPIOE_PIN15))

+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN15))

+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_HIGH(GPIOE_PIN0) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN1) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN2) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN3) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN4) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN5) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN6) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN7) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN8) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN9) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN10) |         \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN11) |         \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN12) |         \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN13) |         \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN14) |         \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN15))

+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_FLOATING(GPIOE_PIN0) |       \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN1) |       \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN2) |       \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN3) |       \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN4) |       \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN5) |       \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN6) |       \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN7) |       \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN8) |       \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN9) |       \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN10) |      \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN11) |      \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN12) |      \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN13) |      \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN14) |      \

+                                     PIN_PUPDR_FLOATING(GPIOE_PIN15))

+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN15))

+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_PIN0, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN1, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN7, 0U))

+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOE_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOE_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOE_PIN13, 0U) |         \

+                                     PIN_AFIO_AF(GPIOE_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOE_PIN15, 0U))

+#define VAL_GPIOE_ASCR              (PIN_ASCR_DISABLED(GPIOE_PIN0) |        \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN1) |        \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN2) |        \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN3) |        \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN4) |        \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN5) |        \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN6) |        \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN7) |        \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN8) |        \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN9) |        \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN10) |       \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN11) |       \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN12) |       \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN13) |       \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN14) |       \

+                                     PIN_ASCR_DISABLED(GPIOE_PIN15))

+#define VAL_GPIOE_LOCKR             (PIN_LOCKR_DISABLED(GPIOE_PIN0) |       \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN1) |       \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN2) |       \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN3) |       \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN4) |       \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN5) |       \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN6) |       \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN7) |       \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN8) |       \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN9) |       \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN10) |      \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN11) |      \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN12) |      \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN13) |      \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN14) |      \

+                                     PIN_LOCKR_DISABLED(GPIOE_PIN15))

+

+/*

+ * GPIOF setup:

+ *

+ * PF0  - PIN0                      (analog).

+ * PF1  - PIN1                      (analog).

+ * PF2  - PIN2                      (analog).

+ * PF3  - PIN3                      (analog).

+ * PF4  - PIN4                      (analog).

+ * PF5  - PIN5                      (analog).

+ * PF6  - PIN6                      (analog).

+ * PF7  - PIN7                      (analog).

+ * PF8  - PIN8                      (analog).

+ * PF9  - PIN9                      (analog).

+ * PF10 - PIN10                     (analog).

+ * PF11 - PIN11                     (analog).

+ * PF12 - PIN12                     (analog).

+ * PF13 - PIN13                     (analog).

+ * PF14 - PIN14                     (analog).

+ * PF15 - PIN15                     (analog).

+ */

+#define VAL_GPIOF_MODER             (PIN_MODE_ANALOG(GPIOF_PIN0) |          \

+                                     PIN_MODE_ANALOG(GPIOF_PIN1) |          \

+                                     PIN_MODE_ANALOG(GPIOF_PIN2) |          \

+                                     PIN_MODE_ANALOG(GPIOF_PIN3) |          \

+                                     PIN_MODE_ANALOG(GPIOF_PIN4) |          \

+                                     PIN_MODE_ANALOG(GPIOF_PIN5) |          \

+                                     PIN_MODE_ANALOG(GPIOF_PIN6) |          \

+                                     PIN_MODE_ANALOG(GPIOF_PIN7) |          \

+                                     PIN_MODE_ANALOG(GPIOF_PIN8) |          \

+                                     PIN_MODE_ANALOG(GPIOF_PIN9) |          \

+                                     PIN_MODE_ANALOG(GPIOF_PIN10) |         \

+                                     PIN_MODE_ANALOG(GPIOF_PIN11) |         \

+                                     PIN_MODE_ANALOG(GPIOF_PIN12) |         \

+                                     PIN_MODE_ANALOG(GPIOF_PIN13) |         \

+                                     PIN_MODE_ANALOG(GPIOF_PIN14) |         \

+                                     PIN_MODE_ANALOG(GPIOF_PIN15))

+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))

+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_HIGH(GPIOF_PIN0) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN1) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN2) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN3) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN4) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN5) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN6) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN7) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN8) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN9) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN10) |         \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN11) |         \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN12) |         \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN13) |         \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN14) |         \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN15))

+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_FLOATING(GPIOF_PIN0) |       \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN1) |       \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN2) |       \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN3) |       \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN4) |       \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN5) |       \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN6) |       \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN7) |       \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN8) |       \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN9) |       \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN10) |      \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN11) |      \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN12) |      \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN13) |      \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN14) |      \

+                                     PIN_PUPDR_FLOATING(GPIOF_PIN15))

+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN15))

+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_PIN0, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN1, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN7, 0U))

+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOF_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOF_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOF_PIN13, 0U) |         \

+                                     PIN_AFIO_AF(GPIOF_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOF_PIN15, 0U))

+#define VAL_GPIOF_ASCR              (PIN_ASCR_DISABLED(GPIOF_PIN0) |        \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN1) |        \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN2) |        \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN3) |        \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN4) |        \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN5) |        \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN6) |        \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN7) |        \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN8) |        \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN9) |        \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN10) |       \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN11) |       \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN12) |       \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN13) |       \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN14) |       \

+                                     PIN_ASCR_DISABLED(GPIOF_PIN15))

+#define VAL_GPIOF_LOCKR             (PIN_LOCKR_DISABLED(GPIOF_PIN0) |       \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN1) |       \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN2) |       \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN3) |       \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN4) |       \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN5) |       \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN6) |       \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN7) |       \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN8) |       \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN9) |       \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN10) |      \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN11) |      \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN12) |      \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN13) |      \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN14) |      \

+                                     PIN_LOCKR_DISABLED(GPIOF_PIN15))

+

+/*

+ * GPIOG setup:

+ *

+ * PG0  - PIN0                      (analog).

+ * PG1  - PIN1                      (analog).

+ * PG2  - PIN2                      (analog).

+ * PG3  - PIN3                      (analog).

+ * PG4  - PIN4                      (analog).

+ * PG5  - PIN5                      (analog).

+ * PG6  - PIN6                      (analog).

+ * PG7  - PIN7                      (analog).

+ * PG8  - PIN8                      (analog).

+ * PG9  - PIN9                      (analog).

+ * PG10 - PIN10                     (analog).

+ * PG11 - PIN11                     (analog).

+ * PG12 - PIN12                     (analog).

+ * PG13 - PIN13                     (analog).

+ * PG14 - PIN14                     (analog).

+ * PG15 - PIN15                     (analog).

+ */

+#define VAL_GPIOG_MODER             (PIN_MODE_ANALOG(GPIOG_PIN0) |          \

+                                     PIN_MODE_ANALOG(GPIOG_PIN1) |          \

+                                     PIN_MODE_ANALOG(GPIOG_PIN2) |          \

+                                     PIN_MODE_ANALOG(GPIOG_PIN3) |          \

+                                     PIN_MODE_ANALOG(GPIOG_PIN4) |          \

+                                     PIN_MODE_ANALOG(GPIOG_PIN5) |          \

+                                     PIN_MODE_ANALOG(GPIOG_PIN6) |          \

+                                     PIN_MODE_ANALOG(GPIOG_PIN7) |          \

+                                     PIN_MODE_ANALOG(GPIOG_PIN8) |          \

+                                     PIN_MODE_ANALOG(GPIOG_PIN9) |          \

+                                     PIN_MODE_ANALOG(GPIOG_PIN10) |         \

+                                     PIN_MODE_ANALOG(GPIOG_PIN11) |         \

+                                     PIN_MODE_ANALOG(GPIOG_PIN12) |         \

+                                     PIN_MODE_ANALOG(GPIOG_PIN13) |         \

+                                     PIN_MODE_ANALOG(GPIOG_PIN14) |         \

+                                     PIN_MODE_ANALOG(GPIOG_PIN15))

+#define VAL_GPIOG_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN15))

+#define VAL_GPIOG_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOG_PIN0) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN1) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN2) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN3) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN4) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN5) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN6) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN7) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN8) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN9) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN10) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN11) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN12) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN13) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN14) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOG_PIN15))

+#define VAL_GPIOG_PUPDR             (PIN_PUPDR_FLOATING(GPIOG_PIN0) |       \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN1) |       \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN2) |       \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN3) |       \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN4) |       \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN5) |       \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN6) |       \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN7) |       \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN8) |       \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN9) |       \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN10) |      \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN11) |      \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN12) |      \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN13) |      \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN14) |      \

+                                     PIN_PUPDR_FLOATING(GPIOG_PIN15))

+#define VAL_GPIOG_ODR               (PIN_ODR_HIGH(GPIOG_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOG_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOG_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOG_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOG_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOG_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOG_PIN15))

+#define VAL_GPIOG_AFRL              (PIN_AFIO_AF(GPIOG_PIN0, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN1, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN7, 0U))

+#define VAL_GPIOG_AFRH              (PIN_AFIO_AF(GPIOG_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOG_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOG_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOG_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOG_PIN13, 0U) |         \

+                                     PIN_AFIO_AF(GPIOG_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOG_PIN15, 0U))

+#define VAL_GPIOG_ASCR              (PIN_ASCR_DISABLED(GPIOG_PIN0) |        \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN1) |        \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN2) |        \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN3) |        \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN4) |        \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN5) |        \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN6) |        \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN7) |        \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN8) |        \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN9) |        \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN10) |       \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN11) |       \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN12) |       \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN13) |       \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN14) |       \

+                                     PIN_ASCR_DISABLED(GPIOG_PIN15))

+#define VAL_GPIOG_LOCKR             (PIN_LOCKR_DISABLED(GPIOG_PIN0) |       \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN1) |       \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN2) |       \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN3) |       \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN4) |       \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN5) |       \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN6) |       \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN7) |       \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN8) |       \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN9) |       \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN10) |      \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN11) |      \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN12) |      \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN13) |      \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN14) |      \

+                                     PIN_LOCKR_DISABLED(GPIOG_PIN15))

+

+/*

+ * GPIOH setup:

+ *

+ * PH0  - OSC_IN                    (input floating).

+ * PH1  - OSC_OUT                   (input floating).

+ * PH2  - PIN2                      (analog).

+ * PH3  - PIN3                      (analog).

+ * PH4  - PIN4                      (analog).

+ * PH5  - PIN5                      (analog).

+ * PH6  - PIN6                      (analog).

+ * PH7  - PIN7                      (analog).

+ * PH8  - PIN8                      (analog).

+ * PH9  - PIN9                      (analog).

+ * PH10 - PIN10                     (analog).

+ * PH11 - PIN11                     (analog).

+ * PH12 - PIN12                     (analog).

+ * PH13 - PIN13                     (analog).

+ * PH14 - PIN14                     (analog).

+ * PH15 - PIN15                     (analog).

+ */

+#define VAL_GPIOH_MODER             (PIN_MODE_INPUT(GPIOH_OSC_IN) |         \

+                                     PIN_MODE_INPUT(GPIOH_OSC_OUT) |        \

+                                     PIN_MODE_ANALOG(GPIOH_PIN2) |          \

+                                     PIN_MODE_ANALOG(GPIOH_PIN3) |          \

+                                     PIN_MODE_ANALOG(GPIOH_PIN4) |          \

+                                     PIN_MODE_ANALOG(GPIOH_PIN5) |          \

+                                     PIN_MODE_ANALOG(GPIOH_PIN6) |          \

+                                     PIN_MODE_ANALOG(GPIOH_PIN7) |          \

+                                     PIN_MODE_ANALOG(GPIOH_PIN8) |          \

+                                     PIN_MODE_ANALOG(GPIOH_PIN9) |          \

+                                     PIN_MODE_ANALOG(GPIOH_PIN10) |         \

+                                     PIN_MODE_ANALOG(GPIOH_PIN11) |         \

+                                     PIN_MODE_ANALOG(GPIOH_PIN12) |         \

+                                     PIN_MODE_ANALOG(GPIOH_PIN13) |         \

+                                     PIN_MODE_ANALOG(GPIOH_PIN14) |         \

+                                     PIN_MODE_ANALOG(GPIOH_PIN15))

+#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN15))

+#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_HIGH(GPIOH_OSC_IN) |        \

+                                     PIN_OSPEED_HIGH(GPIOH_OSC_OUT) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN2) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN3) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN4) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN5) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN6) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN7) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN8) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN9) |       \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN10) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN11) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN12) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN13) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN14) |      \

+                                     PIN_OSPEED_VERYLOW(GPIOH_PIN15))

+#define VAL_GPIOH_PUPDR             (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) |     \

+                                     PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) |    \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN2) |       \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN3) |       \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN4) |       \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN5) |       \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN6) |       \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN7) |       \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN8) |       \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN9) |       \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN10) |      \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN11) |      \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN12) |      \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN13) |      \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN14) |      \

+                                     PIN_PUPDR_FLOATING(GPIOH_PIN15))

+#define VAL_GPIOH_ODR               (PIN_ODR_HIGH(GPIOH_OSC_IN) |           \

+                                     PIN_ODR_HIGH(GPIOH_OSC_OUT) |          \

+                                     PIN_ODR_HIGH(GPIOH_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN15))

+#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) |        \

+                                     PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) |       \

+                                     PIN_AFIO_AF(GPIOH_PIN2, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN3, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN4, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN5, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN6, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN7, 0U))

+#define VAL_GPIOH_AFRH              (PIN_AFIO_AF(GPIOH_PIN8, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN9, 0U) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN10, 0U) |         \

+                                     PIN_AFIO_AF(GPIOH_PIN11, 0U) |         \

+                                     PIN_AFIO_AF(GPIOH_PIN12, 0U) |         \

+                                     PIN_AFIO_AF(GPIOH_PIN13, 0U) |         \

+                                     PIN_AFIO_AF(GPIOH_PIN14, 0U) |         \

+                                     PIN_AFIO_AF(GPIOH_PIN15, 0U))

+#define VAL_GPIOH_ASCR              (PIN_ASCR_DISABLED(GPIOH_OSC_IN) |      \

+                                     PIN_ASCR_DISABLED(GPIOH_OSC_OUT) |     \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN2) |        \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN3) |        \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN4) |        \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN5) |        \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN6) |        \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN7) |        \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN8) |        \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN9) |        \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN10) |       \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN11) |       \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN12) |       \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN13) |       \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN14) |       \

+                                     PIN_ASCR_DISABLED(GPIOH_PIN15))

+#define VAL_GPIOH_LOCKR             (PIN_LOCKR_DISABLED(GPIOH_OSC_IN) |     \

+                                     PIN_LOCKR_DISABLED(GPIOH_OSC_OUT) |    \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN2) |       \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN3) |       \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN4) |       \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN5) |       \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN6) |       \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN7) |       \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN8) |       \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN9) |       \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN10) |      \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN11) |      \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN12) |      \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN13) |      \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN14) |      \

+                                     PIN_LOCKR_DISABLED(GPIOH_PIN15))

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#if !defined(_FROM_ASM_)

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void boardInit(void);

+#ifdef __cplusplus

+}

+#endif

+#endif /* _FROM_ASM_ */

+

+#define LINE_LED_RED   PAL_LINE(GPIOC_BASE, 10U)

+#define LINE_LED_GREEN PAL_LINE(GPIOC_BASE, 11U)

+#define LINE_LED_BLUE  PAL_LINE(GPIOC_BASE, 12U)

+

+#endif /* BOARD_H */

diff --git a/firmware/source/cfg/chconf.h b/firmware/source/cfg/chconf.h
new file mode 100644
index 0000000..628d7e8
--- /dev/null
+++ b/firmware/source/cfg/chconf.h
@@ -0,0 +1,756 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    rt/templates/chconf.h

+ * @brief   Configuration file template.

+ * @details A copy of this file must be placed in each project directory, it

+ *          contains the application specific kernel settings.

+ *

+ * @addtogroup config

+ * @details Kernel related settings and hooks.

+ * @{

+ */

+

+#ifndef CHCONF_H

+#define CHCONF_H

+

+#define _CHIBIOS_RT_CONF_

+#define _CHIBIOS_RT_CONF_VER_6_1_

+

+/*===========================================================================*/

+/**

+ * @name System timers settings

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   System time counter resolution.

+ * @note    Allowed values are 16 or 32 bits.

+ */

+#if !defined(CH_CFG_ST_RESOLUTION)

+#define CH_CFG_ST_RESOLUTION                32

+#endif

+

+/**

+ * @brief   System tick frequency.

+ * @details Frequency of the system timer that drives the system ticks. This

+ *          setting also defines the system tick time unit.

+ */

+#if !defined(CH_CFG_ST_FREQUENCY)

+#define CH_CFG_ST_FREQUENCY                 10000

+#endif

+

+/**

+ * @brief   Time intervals data size.

+ * @note    Allowed values are 16, 32 or 64 bits.

+ */

+#if !defined(CH_CFG_INTERVALS_SIZE)

+#define CH_CFG_INTERVALS_SIZE               32

+#endif

+

+/**

+ * @brief   Time types data size.

+ * @note    Allowed values are 16 or 32 bits.

+ */

+#if !defined(CH_CFG_TIME_TYPES_SIZE)

+#define CH_CFG_TIME_TYPES_SIZE              32

+#endif

+

+/**

+ * @brief   Time delta constant for the tick-less mode.

+ * @note    If this value is zero then the system uses the classic

+ *          periodic tick. This value represents the minimum number

+ *          of ticks that is safe to specify in a timeout directive.

+ *          The value one is not valid, timeouts are rounded up to

+ *          this value.

+ */

+#if !defined(CH_CFG_ST_TIMEDELTA)

+#define CH_CFG_ST_TIMEDELTA                 2

+#endif

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Kernel parameters and options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Round robin interval.

+ * @details This constant is the number of system ticks allowed for the

+ *          threads before preemption occurs. Setting this value to zero

+ *          disables the preemption for threads with equal priority and the

+ *          round robin becomes cooperative. Note that higher priority

+ *          threads can still preempt, the kernel is always preemptive.

+ * @note    Disabling the round robin preemption makes the kernel more compact

+ *          and generally faster.

+ * @note    The round robin preemption is not supported in tickless mode and

+ *          must be set to zero in that case.

+ */

+#if !defined(CH_CFG_TIME_QUANTUM)

+#define CH_CFG_TIME_QUANTUM                 0

+#endif

+

+/**

+ * @brief   Idle thread automatic spawn suppression.

+ * @details When this option is activated the function @p chSysInit()

+ *          does not spawn the idle thread. The application @p main()

+ *          function becomes the idle thread and must implement an

+ *          infinite loop.

+ */

+#if !defined(CH_CFG_NO_IDLE_THREAD)

+#define CH_CFG_NO_IDLE_THREAD               FALSE

+#endif

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Performance options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   OS optimization.

+ * @details If enabled then time efficient rather than space efficient code

+ *          is used when two possible implementations exist.

+ *

+ * @note    This is not related to the compiler optimization options.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_OPTIMIZE_SPEED)

+#define CH_CFG_OPTIMIZE_SPEED               TRUE

+#endif

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Subsystem options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Time Measurement APIs.

+ * @details If enabled then the time measurement APIs are included in

+ *          the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_TM)

+#define CH_CFG_USE_TM                       TRUE

+#endif

+

+/**

+ * @brief   Threads registry APIs.

+ * @details If enabled then the registry APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_REGISTRY)

+#define CH_CFG_USE_REGISTRY                 TRUE

+#endif

+

+/**

+ * @brief   Threads synchronization APIs.

+ * @details If enabled then the @p chThdWait() function is included in

+ *          the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_WAITEXIT)

+#define CH_CFG_USE_WAITEXIT                 TRUE

+#endif

+

+/**

+ * @brief   Semaphores APIs.

+ * @details If enabled then the Semaphores APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_SEMAPHORES)

+#define CH_CFG_USE_SEMAPHORES               TRUE

+#endif

+

+/**

+ * @brief   Semaphores queuing mode.

+ * @details If enabled then the threads are enqueued on semaphores by

+ *          priority rather than in FIFO order.

+ *

+ * @note    The default is @p FALSE. Enable this if you have special

+ *          requirements.

+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.

+ */

+#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)

+#define CH_CFG_USE_SEMAPHORES_PRIORITY      FALSE

+#endif

+

+/**

+ * @brief   Mutexes APIs.

+ * @details If enabled then the mutexes APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_MUTEXES)

+#define CH_CFG_USE_MUTEXES                  TRUE

+#endif

+

+/**

+ * @brief   Enables recursive behavior on mutexes.

+ * @note    Recursive mutexes are heavier and have an increased

+ *          memory footprint.

+ *

+ * @note    The default is @p FALSE.

+ * @note    Requires @p CH_CFG_USE_MUTEXES.

+ */

+#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)

+#define CH_CFG_USE_MUTEXES_RECURSIVE        FALSE

+#endif

+

+/**

+ * @brief   Conditional Variables APIs.

+ * @details If enabled then the conditional variables APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_MUTEXES.

+ */

+#if !defined(CH_CFG_USE_CONDVARS)

+#define CH_CFG_USE_CONDVARS                 TRUE

+#endif

+

+/**

+ * @brief   Conditional Variables APIs with timeout.

+ * @details If enabled then the conditional variables APIs with timeout

+ *          specification are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_CONDVARS.

+ */

+#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)

+#define CH_CFG_USE_CONDVARS_TIMEOUT         TRUE

+#endif

+

+/**

+ * @brief   Events Flags APIs.

+ * @details If enabled then the event flags APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_EVENTS)

+#define CH_CFG_USE_EVENTS                   TRUE

+#endif

+

+/**

+ * @brief   Events Flags APIs with timeout.

+ * @details If enabled then the events APIs with timeout specification

+ *          are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_EVENTS.

+ */

+#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)

+#define CH_CFG_USE_EVENTS_TIMEOUT           TRUE

+#endif

+

+/**

+ * @brief   Synchronous Messages APIs.

+ * @details If enabled then the synchronous messages APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_MESSAGES)

+#define CH_CFG_USE_MESSAGES                 TRUE

+#endif

+

+/**

+ * @brief   Synchronous Messages queuing mode.

+ * @details If enabled then messages are served by priority rather than in

+ *          FIFO order.

+ *

+ * @note    The default is @p FALSE. Enable this if you have special

+ *          requirements.

+ * @note    Requires @p CH_CFG_USE_MESSAGES.

+ */

+#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)

+#define CH_CFG_USE_MESSAGES_PRIORITY        FALSE

+#endif

+

+/**

+ * @brief   Dynamic Threads APIs.

+ * @details If enabled then the dynamic threads creation APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_WAITEXIT.

+ * @note    Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.

+ */

+#if !defined(CH_CFG_USE_DYNAMIC)

+#define CH_CFG_USE_DYNAMIC                  TRUE

+#endif

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name OSLIB options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Mailboxes APIs.

+ * @details If enabled then the asynchronous messages (mailboxes) APIs are

+ *          included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.

+ */

+#if !defined(CH_CFG_USE_MAILBOXES)

+#define CH_CFG_USE_MAILBOXES                TRUE

+#endif

+

+/**

+ * @brief   Core Memory Manager APIs.

+ * @details If enabled then the core memory manager APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_MEMCORE)

+#define CH_CFG_USE_MEMCORE                  TRUE

+#endif

+

+/**

+ * @brief   Managed RAM size.

+ * @details Size of the RAM area to be managed by the OS. If set to zero

+ *          then the whole available RAM is used. The core memory is made

+ *          available to the heap allocator and/or can be used directly through

+ *          the simplified core memory allocator.

+ *

+ * @note    In order to let the OS manage the whole RAM the linker script must

+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.

+ * @note    Requires @p CH_CFG_USE_MEMCORE.

+ */

+#if !defined(CH_CFG_MEMCORE_SIZE)

+#define CH_CFG_MEMCORE_SIZE                 0

+#endif

+

+/**

+ * @brief   Heap Allocator APIs.

+ * @details If enabled then the memory heap allocator APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or

+ *          @p CH_CFG_USE_SEMAPHORES.

+ * @note    Mutexes are recommended.

+ */

+#if !defined(CH_CFG_USE_HEAP)

+#define CH_CFG_USE_HEAP                     TRUE

+#endif

+

+/**

+ * @brief   Memory Pools Allocator APIs.

+ * @details If enabled then the memory pools allocator APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_MEMPOOLS)

+#define CH_CFG_USE_MEMPOOLS                 TRUE

+#endif

+

+/**

+ * @brief   Objects FIFOs APIs.

+ * @details If enabled then the objects FIFOs APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_OBJ_FIFOS)

+#define CH_CFG_USE_OBJ_FIFOS                TRUE

+#endif

+

+/**

+ * @brief   Pipes APIs.

+ * @details If enabled then the pipes APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_PIPES)

+#define CH_CFG_USE_PIPES                    TRUE

+#endif

+

+/**

+ * @brief   Objects Caches APIs.

+ * @details If enabled then the objects caches APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_OBJ_CACHES)

+#define CH_CFG_USE_OBJ_CACHES               TRUE

+#endif

+

+/**

+ * @brief   Delegate threads APIs.

+ * @details If enabled then the delegate threads APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_DELEGATES)

+#define CH_CFG_USE_DELEGATES                TRUE

+#endif

+

+/**

+ * @brief   Jobs Queues APIs.

+ * @details If enabled then the jobs queues APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_CFG_USE_JOBS)

+#define CH_CFG_USE_JOBS                     TRUE

+#endif

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Objects factory options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Objects Factory APIs.

+ * @details If enabled then the objects factory APIs are included in the

+ *          kernel.

+ *

+ * @note    The default is @p FALSE.

+ */

+#if !defined(CH_CFG_USE_FACTORY)

+#define CH_CFG_USE_FACTORY                  TRUE

+#endif

+

+/**

+ * @brief   Maximum length for object names.

+ * @details If the specified length is zero then the name is stored by

+ *          pointer but this could have unintended side effects.

+ */

+#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)

+#define CH_CFG_FACTORY_MAX_NAMES_LENGTH     8

+#endif

+

+/**

+ * @brief   Enables the registry of generic objects.

+ */

+#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)

+#define CH_CFG_FACTORY_OBJECTS_REGISTRY     TRUE

+#endif

+

+/**

+ * @brief   Enables factory for generic buffers.

+ */

+#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)

+#define CH_CFG_FACTORY_GENERIC_BUFFERS      TRUE

+#endif

+

+/**

+ * @brief   Enables factory for semaphores.

+ */

+#if !defined(CH_CFG_FACTORY_SEMAPHORES)

+#define CH_CFG_FACTORY_SEMAPHORES           TRUE

+#endif

+

+/**

+ * @brief   Enables factory for mailboxes.

+ */

+#if !defined(CH_CFG_FACTORY_MAILBOXES)

+#define CH_CFG_FACTORY_MAILBOXES            TRUE

+#endif

+

+/**

+ * @brief   Enables factory for objects FIFOs.

+ */

+#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)

+#define CH_CFG_FACTORY_OBJ_FIFOS            TRUE

+#endif

+

+/**

+ * @brief   Enables factory for Pipes.

+ */

+#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)

+#define CH_CFG_FACTORY_PIPES                TRUE

+#endif

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Debug options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Debug option, kernel statistics.

+ *

+ * @note    The default is @p FALSE.

+ */

+#if !defined(CH_DBG_STATISTICS)

+#define CH_DBG_STATISTICS                   FALSE

+#endif

+

+/**

+ * @brief   Debug option, system state check.

+ * @details If enabled the correct call protocol for system APIs is checked

+ *          at runtime.

+ *

+ * @note    The default is @p FALSE.

+ */

+#if !defined(CH_DBG_SYSTEM_STATE_CHECK)

+#define CH_DBG_SYSTEM_STATE_CHECK           TRUE

+#endif

+

+/**

+ * @brief   Debug option, parameters checks.

+ * @details If enabled then the checks on the API functions input

+ *          parameters are activated.

+ *

+ * @note    The default is @p FALSE.

+ */

+#if !defined(CH_DBG_ENABLE_CHECKS)

+#define CH_DBG_ENABLE_CHECKS                TRUE

+#endif

+

+/**

+ * @brief   Debug option, consistency checks.

+ * @details If enabled then all the assertions in the kernel code are

+ *          activated. This includes consistency checks inside the kernel,

+ *          runtime anomalies and port-defined checks.

+ *

+ * @note    The default is @p FALSE.

+ */

+#if !defined(CH_DBG_ENABLE_ASSERTS)

+#define CH_DBG_ENABLE_ASSERTS               TRUE

+#endif

+

+/**

+ * @brief   Debug option, trace buffer.

+ * @details If enabled then the trace buffer is activated.

+ *

+ * @note    The default is @p CH_DBG_TRACE_MASK_DISABLED.

+ */

+#if !defined(CH_DBG_TRACE_MASK)

+#define CH_DBG_TRACE_MASK                   CH_DBG_TRACE_MASK_NONE

+#endif

+

+/**

+ * @brief   Trace buffer entries.

+ * @note    The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is

+ *          different from @p CH_DBG_TRACE_MASK_DISABLED.

+ */

+#if !defined(CH_DBG_TRACE_BUFFER_SIZE)

+#define CH_DBG_TRACE_BUFFER_SIZE            128

+#endif

+

+/**

+ * @brief   Debug option, stack checks.

+ * @details If enabled then a runtime stack check is performed.

+ *

+ * @note    The default is @p FALSE.

+ * @note    The stack check is performed in a architecture/port dependent way.

+ *          It may not be implemented or some ports.

+ * @note    The default failure mode is to halt the system with the global

+ *          @p panic_msg variable set to @p NULL.

+ */

+#if !defined(CH_DBG_ENABLE_STACK_CHECK)

+#define CH_DBG_ENABLE_STACK_CHECK           FALSE

+#endif

+

+/**

+ * @brief   Debug option, stacks initialization.

+ * @details If enabled then the threads working area is filled with a byte

+ *          value when a thread is created. This can be useful for the

+ *          runtime measurement of the used stack.

+ *

+ * @note    The default is @p FALSE.

+ */

+#if !defined(CH_DBG_FILL_THREADS)

+#define CH_DBG_FILL_THREADS                 FALSE

+#endif

+

+/**

+ * @brief   Debug option, threads profiling.

+ * @details If enabled then a field is added to the @p thread_t structure that

+ *          counts the system ticks occurred while executing the thread.

+ *

+ * @note    The default is @p FALSE.

+ * @note    This debug option is not currently compatible with the

+ *          tickless mode.

+ */

+#if !defined(CH_DBG_THREADS_PROFILING)

+#define CH_DBG_THREADS_PROFILING            FALSE

+#endif

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Kernel hooks

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   System structure extension.

+ * @details User fields added to the end of the @p ch_system_t structure.

+ */

+#define CH_CFG_SYSTEM_EXTRA_FIELDS                                          \

+  /* Add threads custom fields here.*/

+

+/**

+ * @brief   System initialization hook.

+ * @details User initialization code added to the @p chSysInit() function

+ *          just before interrupts are enabled globally.

+ */

+#define CH_CFG_SYSTEM_INIT_HOOK() {                                         \

+  /* Add threads initialization code here.*/                                \

+}

+

+/**

+ * @brief   Threads descriptor structure extension.

+ * @details User fields added to the end of the @p thread_t structure.

+ */

+#define CH_CFG_THREAD_EXTRA_FIELDS                                          \

+  /* Add threads custom fields here.*/

+

+/**

+ * @brief   Threads initialization hook.

+ * @details User initialization code added to the @p _thread_init() function.

+ *

+ * @note    It is invoked from within @p _thread_init() and implicitly from all

+ *          the threads creation APIs.

+ */

+#define CH_CFG_THREAD_INIT_HOOK(tp) {                                       \

+  /* Add threads initialization code here.*/                                \

+}

+

+/**

+ * @brief   Threads finalization hook.

+ * @details User finalization code added to the @p chThdExit() API.

+ */

+#define CH_CFG_THREAD_EXIT_HOOK(tp) {                                       \

+  /* Add threads finalization code here.*/                                  \

+}

+

+/**

+ * @brief   Context switch hook.

+ * @details This hook is invoked just before switching between threads.

+ */

+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \

+  /* Context switch code here.*/                                            \

+}

+

+/**

+ * @brief   ISR enter hook.

+ */

+#define CH_CFG_IRQ_PROLOGUE_HOOK() {                                        \

+  /* IRQ prologue code here.*/                                              \

+}

+

+/**

+ * @brief   ISR exit hook.

+ */

+#define CH_CFG_IRQ_EPILOGUE_HOOK() {                                        \

+  /* IRQ epilogue code here.*/                                              \

+}

+

+/**

+ * @brief   Idle thread enter hook.

+ * @note    This hook is invoked within a critical zone, no OS functions

+ *          should be invoked from here.

+ * @note    This macro can be used to activate a power saving mode.

+ */

+#define CH_CFG_IDLE_ENTER_HOOK() {                                          \

+  /* Idle-enter code here.*/                                                \

+}

+

+/**

+ * @brief   Idle thread leave hook.

+ * @note    This hook is invoked within a critical zone, no OS functions

+ *          should be invoked from here.

+ * @note    This macro can be used to deactivate a power saving mode.

+ */

+#define CH_CFG_IDLE_LEAVE_HOOK() {                                          \

+  /* Idle-leave code here.*/                                                \

+}

+

+/**

+ * @brief   Idle Loop hook.

+ * @details This hook is continuously invoked by the idle thread loop.

+ */

+#define CH_CFG_IDLE_LOOP_HOOK() {                                           \

+  /* Idle loop code here.*/                                                 \

+}

+

+/**

+ * @brief   System tick event hook.

+ * @details This hook is invoked in the system tick handler immediately

+ *          after processing the virtual timers queue.

+ */

+#define CH_CFG_SYSTEM_TICK_HOOK() {                                         \

+  /* System tick event code here.*/                                         \

+}

+

+/**

+ * @brief   System halt hook.

+ * @details This hook is invoked in case to a system halting error before

+ *          the system is halted.

+ */

+#define CH_CFG_SYSTEM_HALT_HOOK(reason) {                                   \

+  /* System halt code here.*/                                               \

+}

+

+/**

+ * @brief   Trace hook.

+ * @details This hook is invoked each time a new record is written in the

+ *          trace buffer.

+ */

+#define CH_CFG_TRACE_HOOK(tep) {                                            \

+  /* Trace code here.*/                                                     \

+}

+

+/** @} */

+

+/*===========================================================================*/

+/* Port-specific settings (override port settings defaulted in chcore.h).    */

+/*===========================================================================*/

+

+#endif  /* CHCONF_H */

+

+/** @} */

diff --git a/firmware/source/cfg/halconf.h b/firmware/source/cfg/halconf.h
new file mode 100644
index 0000000..24c6fde
--- /dev/null
+++ b/firmware/source/cfg/halconf.h
@@ -0,0 +1,531 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    templates/halconf.h

+ * @brief   HAL configuration header.

+ * @details HAL configuration file, this file allows to enable or disable the

+ *          various device drivers from your application. You may also use

+ *          this file in order to override the device drivers default settings.

+ *

+ * @addtogroup HAL_CONF

+ * @{

+ */

+

+#ifndef HALCONF_H

+#define HALCONF_H

+

+#define _CHIBIOS_HAL_CONF_

+#define _CHIBIOS_HAL_CONF_VER_7_1_

+

+#include "mcuconf.h"

+

+/**

+ * @brief   Enables the PAL subsystem.

+ */

+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)

+#define HAL_USE_PAL                         TRUE

+#endif

+

+/**

+ * @brief   Enables the ADC subsystem.

+ */

+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)

+#define HAL_USE_ADC                         TRUE

+#endif

+

+/**

+ * @brief   Enables the CAN subsystem.

+ */

+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)

+#define HAL_USE_CAN                         FALSE

+#endif

+

+/**

+ * @brief   Enables the cryptographic subsystem.

+ */

+#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)

+#define HAL_USE_CRY                         FALSE

+#endif

+

+/**

+ * @brief   Enables the DAC subsystem.

+ */

+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)

+#define HAL_USE_DAC                         TRUE

+#endif

+

+/**

+ * @brief   Enables the EFlash subsystem.

+ */

+#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)

+#define HAL_USE_EFL                         FALSE

+#endif

+

+/**

+ * @brief   Enables the GPT subsystem.

+ */

+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)

+#define HAL_USE_GPT                         TRUE

+#endif

+

+/**

+ * @brief   Enables the I2C subsystem.

+ */

+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)

+#define HAL_USE_I2C                         FALSE

+#endif

+

+/**

+ * @brief   Enables the I2S subsystem.

+ */

+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)

+#define HAL_USE_I2S                         FALSE

+#endif

+

+/**

+ * @brief   Enables the ICU subsystem.

+ */

+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)

+#define HAL_USE_ICU                         FALSE

+#endif

+

+/**

+ * @brief   Enables the MAC subsystem.

+ */

+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)

+#define HAL_USE_MAC                         FALSE

+#endif

+

+/**

+ * @brief   Enables the MMC_SPI subsystem.

+ */

+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)

+#define HAL_USE_MMC_SPI                     FALSE

+#endif

+

+/**

+ * @brief   Enables the PWM subsystem.

+ */

+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)

+#define HAL_USE_PWM                         FALSE

+#endif

+

+/**

+ * @brief   Enables the RTC subsystem.

+ */

+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)

+#define HAL_USE_RTC                         FALSE

+#endif

+

+/**

+ * @brief   Enables the SDC subsystem.

+ */

+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)

+#define HAL_USE_SDC                         FALSE

+#endif

+

+/**

+ * @brief   Enables the SERIAL subsystem.

+ */

+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)

+#define HAL_USE_SERIAL                      FALSE

+#endif

+

+/**

+ * @brief   Enables the SERIAL over USB subsystem.

+ */

+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)

+#define HAL_USE_SERIAL_USB                  TRUE

+#endif

+

+/**

+ * @brief   Enables the SIO subsystem.

+ */

+#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)

+#define HAL_USE_SIO                         FALSE

+#endif

+

+/**

+ * @brief   Enables the SPI subsystem.

+ */

+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)

+#define HAL_USE_SPI                         FALSE

+#endif

+

+/**

+ * @brief   Enables the TRNG subsystem.

+ */

+#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)

+#define HAL_USE_TRNG                        FALSE

+#endif

+

+/**

+ * @brief   Enables the UART subsystem.

+ */

+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)

+#define HAL_USE_UART                        FALSE

+#endif

+

+/**

+ * @brief   Enables the USB subsystem.

+ */

+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)

+#define HAL_USE_USB                         TRUE

+#endif

+

+/**

+ * @brief   Enables the WDG subsystem.

+ */

+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)

+#define HAL_USE_WDG                         FALSE

+#endif

+

+/**

+ * @brief   Enables the WSPI subsystem.

+ */

+#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)

+#define HAL_USE_WSPI                        FALSE

+#endif

+

+/*===========================================================================*/

+/* PAL driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)

+#define PAL_USE_CALLBACKS                   FALSE

+#endif

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)

+#define PAL_USE_WAIT                        FALSE

+#endif

+

+/*===========================================================================*/

+/* ADC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)

+#define ADC_USE_WAIT                        FALSE

+#endif

+

+/**

+ * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define ADC_USE_MUTUAL_EXCLUSION            FALSE

+#endif

+

+/*===========================================================================*/

+/* CAN driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Sleep mode related APIs inclusion switch.

+ */

+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)

+#define CAN_USE_SLEEP_MODE                  TRUE

+#endif

+

+/**

+ * @brief   Enforces the driver to use direct callbacks rather than OSAL events.

+ */

+#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)

+#define CAN_ENFORCE_USE_CALLBACKS           FALSE

+#endif

+

+/*===========================================================================*/

+/* CRY driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables the SW fall-back of the cryptographic driver.

+ * @details When enabled, this option, activates a fall-back software

+ *          implementation for algorithms not supported by the underlying

+ *          hardware.

+ * @note    Fall-back implementations may not be present for all algorithms.

+ */

+#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)

+#define HAL_CRY_USE_FALLBACK                FALSE

+#endif

+

+/**

+ * @brief   Makes the driver forcibly use the fall-back implementations.

+ */

+#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)

+#define HAL_CRY_ENFORCE_FALLBACK            FALSE

+#endif

+

+/*===========================================================================*/

+/* DAC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)

+#define DAC_USE_WAIT                        FALSE

+#endif

+

+/**

+ * @brief   Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define DAC_USE_MUTUAL_EXCLUSION            FALSE

+#endif

+

+/*===========================================================================*/

+/* I2C driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables the mutual exclusion APIs on the I2C bus.

+ */

+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define I2C_USE_MUTUAL_EXCLUSION            TRUE

+#endif

+

+/*===========================================================================*/

+/* MAC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables the zero-copy API.

+ */

+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)

+#define MAC_USE_ZERO_COPY                   FALSE

+#endif

+

+/**

+ * @brief   Enables an event sources for incoming packets.

+ */

+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)

+#define MAC_USE_EVENTS                      TRUE

+#endif

+

+/*===========================================================================*/

+/* MMC_SPI driver related settings.                                          */

+/*===========================================================================*/

+

+/**

+ * @brief   Delays insertions.

+ * @details If enabled this options inserts delays into the MMC waiting

+ *          routines releasing some extra CPU time for the threads with

+ *          lower priority, this may slow down the driver a bit however.

+ *          This option is recommended also if the SPI driver does not

+ *          use a DMA channel and heavily loads the CPU.

+ */

+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)

+#define MMC_NICE_WAITING                    TRUE

+#endif

+

+/*===========================================================================*/

+/* SDC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Number of initialization attempts before rejecting the card.

+ * @note    Attempts are performed at 10mS intervals.

+ */

+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)

+#define SDC_INIT_RETRY                      100

+#endif

+

+/**

+ * @brief   Include support for MMC cards.

+ * @note    MMC support is not yet implemented so this option must be kept

+ *          at @p FALSE.

+ */

+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)

+#define SDC_MMC_SUPPORT                     FALSE

+#endif

+

+/**

+ * @brief   Delays insertions.

+ * @details If enabled this options inserts delays into the MMC waiting

+ *          routines releasing some extra CPU time for the threads with

+ *          lower priority, this may slow down the driver a bit however.

+ */

+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)

+#define SDC_NICE_WAITING                    TRUE

+#endif

+

+/**

+ * @brief   OCR initialization constant for V20 cards.

+ */

+#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)

+#define SDC_INIT_OCR_V20                    0x50FF8000U

+#endif

+

+/**

+ * @brief   OCR initialization constant for non-V20 cards.

+ */

+#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)

+#define SDC_INIT_OCR                        0x80100000U

+#endif

+

+/*===========================================================================*/

+/* SERIAL driver related settings.                                           */

+/*===========================================================================*/

+

+/**

+ * @brief   Default bit rate.

+ * @details Configuration parameter, this is the baud rate selected for the

+ *          default configuration.

+ */

+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)

+#define SERIAL_DEFAULT_BITRATE              38400

+#endif

+

+/**

+ * @brief   Serial buffers size.

+ * @details Configuration parameter, you can change the depth of the queue

+ *          buffers depending on the requirements of your application.

+ * @note    The default is 16 bytes for both the transmission and receive

+ *          buffers.

+ */

+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)

+#define SERIAL_BUFFERS_SIZE                 16

+#endif

+

+/*===========================================================================*/

+/* SERIAL_USB driver related setting.                                        */

+/*===========================================================================*/

+

+/**

+ * @brief   Serial over USB buffers size.

+ * @details Configuration parameter, the buffer size must be a multiple of

+ *          the USB data endpoint maximum packet size.

+ * @note    The default is 256 bytes for both the transmission and receive

+ *          buffers.

+ */

+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)

+#define SERIAL_USB_BUFFERS_SIZE             256

+#endif

+

+/**

+ * @brief   Serial over USB number of buffers.

+ * @note    The default is 2 buffers.

+ */

+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)

+#define SERIAL_USB_BUFFERS_NUMBER           2

+#endif

+

+/*===========================================================================*/

+/* SPI driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)

+#define SPI_USE_WAIT                        TRUE

+#endif

+

+/**

+ * @brief   Enables circular transfers APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)

+#define SPI_USE_CIRCULAR                    FALSE

+#endif

+

+/**

+ * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define SPI_USE_MUTUAL_EXCLUSION            TRUE

+#endif

+

+/**

+ * @brief   Handling method for SPI CS line.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)

+#define SPI_SELECT_MODE                     SPI_SELECT_MODE_PAD

+#endif

+

+/*===========================================================================*/

+/* UART driver related settings.                                             */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)

+#define UART_USE_WAIT                       FALSE

+#endif

+

+/**

+ * @brief   Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define UART_USE_MUTUAL_EXCLUSION           FALSE

+#endif

+

+/*===========================================================================*/

+/* USB driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)

+#define USB_USE_WAIT                        FALSE

+#endif

+

+/*===========================================================================*/

+/* WSPI driver related settings.                                             */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)

+#define WSPI_USE_WAIT                       TRUE

+#endif

+

+/**

+ * @brief   Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define WSPI_USE_MUTUAL_EXCLUSION           TRUE

+#endif

+

+#endif /* HALCONF_H */

+

+/** @} */

diff --git a/firmware/source/cfg/mcuconf.h b/firmware/source/cfg/mcuconf.h
new file mode 100644
index 0000000..0d4d5c1
--- /dev/null
+++ b/firmware/source/cfg/mcuconf.h
@@ -0,0 +1,7 @@
+#if defined(TARGET_PLATFORM_L4)

+#include "mcuconf_l4.h"

+#elif defined(TARGET_PLATFORM_H7)

+#include "mcuconf_h7.h"

+#elif defined(TARGET_PLATFORM_G4)

+#include "mcuconf_g4.h"

+#endif

diff --git a/firmware/source/cfg/mcuconf_h7.h b/firmware/source/cfg/mcuconf_h7.h
new file mode 100644
index 0000000..c6a254b
--- /dev/null
+++ b/firmware/source/cfg/mcuconf_h7.h
@@ -0,0 +1,483 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+#ifndef MCUCONF_H

+#define MCUCONF_H

+

+/*

+ * STM32H7xx drivers configuration.

+ * The following settings override the default settings present in

+ * the various device driver implementation headers.

+ * Note that the settings for each driver only have effect if the whole

+ * driver is enabled in halconf.h.

+ *

+ * IRQ priorities:

+ * 15...0       Lowest...Highest.

+ *

+ * DMA priorities:

+ * 0...3        Lowest...Highest.

+ */

+

+#define STM32H7xx_MCUCONF

+#define STM32H723_MCUCONF

+#define STM32H725_MCUCONF

+//#define STM32H743_MCUCONF

+

+/*

+ * General settings.

+ */

+#define STM32_NO_INIT                       FALSE

+#define STM32_TARGET_CORE                   1

+

+/*

+ * Memory attributes settings.

+ */

+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_1

+#define STM32_NOCACHE_SRAM1_SRAM2           FALSE

+#define STM32_NOCACHE_SRAM3                 FALSE

+#define STM32_NOCACHE_ALLSRAM               TRUE

+

+/*

+ * PWR system settings.

+ * Reading STM32 Reference Manual is required, settings in PWR_CR3 are

+ * very critical.

+ * Register constants are taken from the ST header.

+ */

+#define STM32_VOS                           STM32_VOS_SCALE1

+#define STM32_PWR_CR1                       (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)

+#define STM32_PWR_CR2                       (PWR_CR2_BREN)

+#define STM32_PWR_CR3                       (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)

+#define STM32_PWR_CPUCR                     0

+

+/*

+ * Clock tree static settings.

+ * Reading STM32 Reference Manual is required.

+ */

+#define STM32_HSI_ENABLED                   TRUE

+#define STM32_LSI_ENABLED                   TRUE

+#define STM32_CSI_ENABLED                   FALSE

+#define STM32_HSI48_ENABLED                 TRUE

+#define STM32_HSE_ENABLED                   FALSE

+#define STM32_LSE_ENABLED                   FALSE

+#define STM32_HSIDIV                        STM32_HSIDIV_DIV8 // HSI = 8MHz

+

+/*

+ * PLLs static settings.

+ * Reading STM32 Reference Manual is required.

+ */

+#define STM32_PLLSRC                        STM32_PLLSRC_HSI_CK

+#define STM32_PLLCFGR_MASK                  ~0

+#define STM32_PLL1_ENABLED                  TRUE

+#define STM32_PLL1_P_ENABLED                TRUE

+#define STM32_PLL1_Q_ENABLED                FALSE

+#define STM32_PLL1_R_ENABLED                FALSE

+#define STM32_PLL1_DIVM_VALUE               4   // 8 / 4 = 2MHz

+#define STM32_PLL1_DIVN_VALUE               240 // = 2 * 240

+#define STM32_PLL1_FRACN_VALUE              0

+#define STM32_PLL1_DIVP_VALUE               1   // = 480MHz

+#define STM32_PLL1_DIVQ_VALUE               16

+#define STM32_PLL1_DIVR_VALUE               8

+#define STM32_PLL2_ENABLED                  TRUE  // PLL2 adjusted by adc.cpp

+#define STM32_PLL2_P_ENABLED                TRUE

+#define STM32_PLL2_Q_ENABLED                FALSE

+#define STM32_PLL2_R_ENABLED                FALSE

+#define STM32_PLL2_DIVM_VALUE               4

+#define STM32_PLL2_DIVN_VALUE               80

+#define STM32_PLL2_FRACN_VALUE              0

+#define STM32_PLL2_DIVP_VALUE               20

+#define STM32_PLL2_DIVQ_VALUE               8

+#define STM32_PLL2_DIVR_VALUE               8

+#define STM32_PLL3_ENABLED                  FALSE

+#define STM32_PLL3_P_ENABLED                FALSE

+#define STM32_PLL3_Q_ENABLED                FALSE

+#define STM32_PLL3_R_ENABLED                FALSE

+#define STM32_PLL3_DIVM_VALUE               4

+#define STM32_PLL3_DIVN_VALUE               400

+#define STM32_PLL3_FRACN_VALUE              0

+#define STM32_PLL3_DIVP_VALUE               8

+#define STM32_PLL3_DIVQ_VALUE               8

+#define STM32_PLL3_DIVR_VALUE               8

+

+/*

+ * Core clocks dynamic settings (can be changed at runtime).

+ * Reading STM32 Reference Manual is required.

+ */

+#define STM32_SW                            STM32_SW_PLL1_P_CK

+#define STM32_RTCSEL                        STM32_RTCSEL_LSI_CK

+#define STM32_D1CPRE                        STM32_D1CPRE_DIV1

+#define STM32_D1HPRE                        STM32_D1HPRE_DIV2  // /2 = 240MHz

+#define STM32_D1PPRE3                       STM32_D1PPRE3_DIV2

+#define STM32_D2PPRE1                       STM32_D2PPRE1_DIV2

+#define STM32_D2PPRE2                       STM32_D2PPRE2_DIV2

+#define STM32_D3PPRE4                       STM32_D3PPRE4_DIV2

+

+/*

+ * Peripherals clocks static settings.

+ * Reading STM32 Reference Manual is required.

+ */

+#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI_CK

+#define STM32_MCO1PRE_VALUE                 4

+#define STM32_MCO2SEL                       STM32_MCO2SEL_SYS_CK

+#define STM32_MCO2PRE_VALUE                 4

+#define STM32_TIMPRE_ENABLE                 TRUE

+#define STM32_HRTIMSEL                      0

+#define STM32_STOPKERWUCK                   0

+#define STM32_STOPWUCK                      0

+#define STM32_RTCPRE_VALUE                  8

+#define STM32_CKPERSEL                      STM32_CKPERSEL_HSI_CK

+#define STM32_SDMMCSEL                      STM32_SDMMCSEL_PLL1_Q_CK

+//#define STM32_OCTOSPISEL                    STM32_OCTOSPISEL_HCLK

+//#define STM32_FMCSEL                        STM32_OCTOSPISEL_HCLK

+#define STM32_SWPSEL                        STM32_SWPSEL_PCLK1

+#define STM32_FDCANSEL                      STM32_FDCANSEL_HSE_CK

+#define STM32_DFSDM1SEL                     STM32_DFSDM1SEL_PCLK2

+#define STM32_SPDIFSEL                      STM32_SPDIFSEL_PLL1_Q_CK

+#define STM32_SPI45SEL                      STM32_SPI45SEL_PCLK2

+#define STM32_SPI123SEL                     STM32_SPI123SEL_PLL1_Q_CK

+//#define STM32_SAI23SEL                      STM32_SAI23SEL_PLL1_Q_CK

+#define STM32_SAI1SEL                       STM32_SAI1SEL_PLL1_Q_CK

+#define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK1

+#define STM32_CECSEL                        STM32_CECSEL_LSE_CK

+#define STM32_USBSEL                        STM32_USBSEL_HSI48_CK

+#define STM32_I2C1235SEL                    STM32_I2C1235SEL_PCLK1

+#define STM32_RNGSEL                        STM32_RNGSEL_HSI48_CK

+#define STM32_USART16910SEL                 STM32_USART16910SEL_PCLK2

+#define STM32_USART234578SEL                STM32_USART234578SEL_PCLK1

+#define STM32_SPI6SEL                       STM32_SPI6SEL_PCLK4

+#define STM32_SAI4BSEL                      STM32_SAI4BSEL_PLL1_Q_CK

+#define STM32_SAI4ASEL                      STM32_SAI4ASEL_PLL1_Q_CK

+#define STM32_ADCSEL                        STM32_ADCSEL_PLL2_P_CK

+#define STM32_LPTIM345SEL                   STM32_LPTIM345SEL_PCLK4

+#define STM32_LPTIM2SEL                     STM32_LPTIM2SEL_PCLK4

+#define STM32_I2C4SEL                       STM32_I2C4SEL_PCLK4

+#define STM32_LPUART1SEL                    STM32_LPUART1SEL_PCLK4

+

+/*

+ * IRQ system settings.

+ */

+#define STM32_IRQ_EXTI0_PRIORITY            6

+#define STM32_IRQ_EXTI1_PRIORITY            6

+#define STM32_IRQ_EXTI2_PRIORITY            6

+#define STM32_IRQ_EXTI3_PRIORITY            6

+#define STM32_IRQ_EXTI4_PRIORITY            6

+#define STM32_IRQ_EXTI5_9_PRIORITY          6

+#define STM32_IRQ_EXTI10_15_PRIORITY        6

+#define STM32_IRQ_EXTI16_PRIORITY           6

+#define STM32_IRQ_EXTI17_PRIORITY           6

+#define STM32_IRQ_EXTI18_PRIORITY           6

+#define STM32_IRQ_EXTI19_PRIORITY           6

+#define STM32_IRQ_EXTI20_21_PRIORITY        6

+

+#define STM32_IRQ_FDCAN1_PRIORITY           10

+#define STM32_IRQ_FDCAN2_PRIORITY           10

+

+#define STM32_IRQ_MDMA_PRIORITY             9

+

+#define STM32_IRQ_QUADSPI1_PRIORITY         10

+

+#define STM32_IRQ_SDMMC1_PRIORITY           9

+#define STM32_IRQ_SDMMC2_PRIORITY           9

+

+#define STM32_IRQ_TIM1_UP_PRIORITY          7

+#define STM32_IRQ_TIM1_CC_PRIORITY          7

+#define STM32_IRQ_TIM2_PRIORITY             7

+#define STM32_IRQ_TIM3_PRIORITY             7

+#define STM32_IRQ_TIM4_PRIORITY             7

+#define STM32_IRQ_TIM5_PRIORITY             7

+#define STM32_IRQ_TIM6_PRIORITY             7

+#define STM32_IRQ_TIM7_PRIORITY             7

+#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY   7

+#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY    7

+#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7

+#define STM32_IRQ_TIM8_CC_PRIORITY          7

+#define STM32_IRQ_TIM15_PRIORITY            7

+#define STM32_IRQ_TIM16_PRIORITY            7

+#define STM32_IRQ_TIM17_PRIORITY            7

+

+#define STM32_IRQ_USART1_PRIORITY           12

+#define STM32_IRQ_USART2_PRIORITY           12

+#define STM32_IRQ_USART3_PRIORITY           12

+#define STM32_IRQ_UART4_PRIORITY            12

+#define STM32_IRQ_UART5_PRIORITY            12

+#define STM32_IRQ_USART6_PRIORITY           12

+#define STM32_IRQ_UART7_PRIORITY            12

+#define STM32_IRQ_UART8_PRIORITY            12

+#define STM32_IRQ_LPUART1_PRIORITY          12

+

+/*

+ * ADC driver system settings.

+ */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

+#define STM32_ADC_USE_ADC12                 FALSE

+#define STM32_ADC_USE_ADC3                  TRUE

+#define STM32_ADC_ADC12_DMA_STREAM          STM32_DMA_STREAM_ID_ANY

+#define STM32_ADC_ADC3_BDMA_STREAM          STM32_BDMA_STREAM_ID_ANY

+#define STM32_ADC_ADC12_DMA_PRIORITY        2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC12_IRQ_PRIORITY        5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV4

+#define STM32_ADC_ADC3_CLOCK_MODE           ADC_CCR_CKMODE_ADCCK

+#define STM32_ADC_ADC3_PRESC                (5 << ADC_CCR_PRESC_Pos) // /10

+

+/*

+ * CAN driver system settings.

+ */

+#define STM32_CAN_USE_FDCAN1                FALSE

+#define STM32_CAN_USE_FDCAN2                FALSE

+

+/*

+ * DAC driver system settings.

+ */

+#define STM32_DAC_DUAL_MODE                 FALSE

+#define STM32_DAC_USE_DAC1_CH1              TRUE

+#define STM32_DAC_USE_DAC1_CH2              TRUE

+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10

+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10

+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2

+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2

+#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID_ANY

+#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID_ANY

+

+/*

+ * GPT driver system settings.

+ */

+#define STM32_GPT_USE_TIM1                  FALSE

+#define STM32_GPT_USE_TIM2                  FALSE

+#define STM32_GPT_USE_TIM3                  FALSE

+#define STM32_GPT_USE_TIM4                  FALSE

+#define STM32_GPT_USE_TIM5                  FALSE

+#define STM32_GPT_USE_TIM6                  TRUE

+#define STM32_GPT_USE_TIM7                  FALSE

+#define STM32_GPT_USE_TIM8                  FALSE

+#define STM32_GPT_USE_TIM12                 FALSE

+#define STM32_GPT_USE_TIM13                 FALSE

+#define STM32_GPT_USE_TIM14                 FALSE

+#define STM32_GPT_USE_TIM15                 FALSE

+#define STM32_GPT_USE_TIM16                 FALSE

+#define STM32_GPT_USE_TIM17                 FALSE

+

+/*

+ * I2C driver system settings.

+ */

+#define STM32_I2C_USE_I2C1                  FALSE

+#define STM32_I2C_USE_I2C2                  FALSE

+#define STM32_I2C_USE_I2C3                  FALSE

+#define STM32_I2C_USE_I2C4                  FALSE

+#define STM32_I2C_BUSY_TIMEOUT              50

+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C4_RX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY

+#define STM32_I2C_I2C4_TX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY

+#define STM32_I2C_I2C1_IRQ_PRIORITY         5

+#define STM32_I2C_I2C2_IRQ_PRIORITY         5

+#define STM32_I2C_I2C3_IRQ_PRIORITY         5

+#define STM32_I2C_I2C4_IRQ_PRIORITY         5

+#define STM32_I2C_I2C1_DMA_PRIORITY         3

+#define STM32_I2C_I2C2_DMA_PRIORITY         3

+#define STM32_I2C_I2C3_DMA_PRIORITY         3

+#define STM32_I2C_I2C4_DMA_PRIORITY         3

+#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")

+

+/*

+ * ICU driver system settings.

+ */

+#define STM32_ICU_USE_TIM1                  FALSE

+#define STM32_ICU_USE_TIM2                  FALSE

+#define STM32_ICU_USE_TIM3                  FALSE

+#define STM32_ICU_USE_TIM4                  FALSE

+#define STM32_ICU_USE_TIM5                  FALSE

+#define STM32_ICU_USE_TIM8                  FALSE

+#define STM32_ICU_USE_TIM12                 FALSE

+#define STM32_ICU_USE_TIM13                 FALSE

+#define STM32_ICU_USE_TIM14                 FALSE

+#define STM32_ICU_USE_TIM15                 FALSE

+#define STM32_ICU_USE_TIM16                 FALSE

+#define STM32_ICU_USE_TIM17                 FALSE

+

+/*

+ * MAC driver system settings.

+ */

+#define STM32_MAC_TRANSMIT_BUFFERS          2

+#define STM32_MAC_RECEIVE_BUFFERS           4

+#define STM32_MAC_BUFFERS_SIZE              1522

+#define STM32_MAC_PHY_TIMEOUT               100

+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE

+#define STM32_MAC_ETH1_IRQ_PRIORITY         13

+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0

+

+/*

+ * PWM driver system settings.

+ */

+#define STM32_PWM_USE_ADVANCED              FALSE

+#define STM32_PWM_USE_TIM1                  FALSE

+#define STM32_PWM_USE_TIM2                  FALSE

+#define STM32_PWM_USE_TIM3                  FALSE

+#define STM32_PWM_USE_TIM4                  FALSE

+#define STM32_PWM_USE_TIM5                  FALSE

+#define STM32_PWM_USE_TIM8                  FALSE

+#define STM32_PWM_USE_TIM12                 FALSE

+#define STM32_PWM_USE_TIM13                 FALSE

+#define STM32_PWM_USE_TIM14                 FALSE

+#define STM32_PWM_USE_TIM15                 FALSE

+#define STM32_PWM_USE_TIM16                 FALSE

+#define STM32_PWM_USE_TIM17                 FALSE

+

+/*

+ * RTC driver system settings.

+ */

+#define STM32_RTC_PRESA_VALUE               32

+#define STM32_RTC_PRESS_VALUE               1024

+#define STM32_RTC_CR_INIT                   0

+#define STM32_RTC_TAMPCR_INIT               0

+

+/*

+ * SDC driver system settings.

+ */

+#define STM32_SDC_USE_SDMMC1                FALSE

+#define STM32_SDC_USE_SDMMC2                FALSE

+#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT   TRUE

+#define STM32_SDC_SDMMC_WRITE_TIMEOUT       1000000

+#define STM32_SDC_SDMMC_READ_TIMEOUT        1000000

+#define STM32_SDC_SDMMC_CLOCK_DELAY         10

+#define STM32_SDC_SDMMC_PWRSAV              TRUE

+

+/*

+ * SERIAL driver system settings.

+ */

+#define STM32_SERIAL_USE_USART1             FALSE

+#define STM32_SERIAL_USE_USART2             FALSE

+#define STM32_SERIAL_USE_USART3             FALSE

+#define STM32_SERIAL_USE_UART4              FALSE

+#define STM32_SERIAL_USE_UART5              FALSE

+#define STM32_SERIAL_USE_USART6             FALSE

+#define STM32_SERIAL_USE_UART7              FALSE

+#define STM32_SERIAL_USE_UART8              FALSE

+

+/*

+ * SPI driver system settings.

+ */

+#define STM32_SPI_USE_SPI1                  FALSE

+#define STM32_SPI_USE_SPI2                  FALSE

+#define STM32_SPI_USE_SPI3                  FALSE

+#define STM32_SPI_USE_SPI4                  FALSE

+#define STM32_SPI_USE_SPI5                  FALSE

+#define STM32_SPI_USE_SPI6                  FALSE

+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI4_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI4_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI5_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI5_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI6_RX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY

+#define STM32_SPI_SPI6_TX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY

+#define STM32_SPI_SPI1_DMA_PRIORITY         1

+#define STM32_SPI_SPI2_DMA_PRIORITY         1

+#define STM32_SPI_SPI3_DMA_PRIORITY         1

+#define STM32_SPI_SPI4_DMA_PRIORITY         1

+#define STM32_SPI_SPI5_DMA_PRIORITY         1

+#define STM32_SPI_SPI6_DMA_PRIORITY         1

+#define STM32_SPI_SPI1_IRQ_PRIORITY         10

+#define STM32_SPI_SPI2_IRQ_PRIORITY         10

+#define STM32_SPI_SPI3_IRQ_PRIORITY         10

+#define STM32_SPI_SPI4_IRQ_PRIORITY         10

+#define STM32_SPI_SPI5_IRQ_PRIORITY         10

+#define STM32_SPI_SPI6_IRQ_PRIORITY         10

+#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")

+

+/*

+ * ST driver system settings.

+ */

+#define STM32_ST_IRQ_PRIORITY               8

+#define STM32_ST_USE_TIMER                  2

+

+/*

+ * TRNG driver system settings.

+ */

+#define STM32_TRNG_USE_RNG1                 FALSE

+

+/*

+ * UART driver system settings.

+ */

+#define STM32_UART_USE_USART1               FALSE

+#define STM32_UART_USE_USART2               FALSE

+#define STM32_UART_USE_USART3               FALSE

+#define STM32_UART_USE_UART4                FALSE

+#define STM32_UART_USE_UART5                FALSE

+#define STM32_UART_USE_USART6               FALSE

+#define STM32_UART_USE_UART7                FALSE

+#define STM32_UART_USE_UART8                FALSE

+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART7_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART7_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART8_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART8_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART1_DMA_PRIORITY      0

+#define STM32_UART_USART2_DMA_PRIORITY      0

+#define STM32_UART_USART3_DMA_PRIORITY      0

+#define STM32_UART_UART4_DMA_PRIORITY       0

+#define STM32_UART_UART5_DMA_PRIORITY       0

+#define STM32_UART_USART6_DMA_PRIORITY      0

+#define STM32_UART_UART7_DMA_PRIORITY       0

+#define STM32_UART_UART8_DMA_PRIORITY       0

+#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

+

+/*

+ * USB driver system settings.

+ */

+#define STM32_USB_USE_OTG1                  FALSE

+#define STM32_USB_USE_OTG2                  TRUE

+#define STM32_USB_OTG1_IRQ_PRIORITY         14

+#define STM32_USB_OTG2_IRQ_PRIORITY         14

+#define STM32_USB_OTG1_RX_FIFO_SIZE         512

+#define STM32_USB_OTG2_RX_FIFO_SIZE         1024

+#define STM32_USB_HOST_WAKEUP_DURATION      2

+

+/*

+ * WDG driver system settings.

+ */

+#define STM32_WDG_USE_IWDG                  FALSE

+

+/*

+ * WSPI driver system settings.

+ */

+#define STM32_WSPI_USE_QUADSPI1             FALSE

+#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1

+#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL    STM32_MDMA_CHANNEL_ID_ANY

+#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY   1

+#define STM32_WSPI_MDMA_ERROR_HOOK(qspip)   osalSysHalt("MDMA failure")

+

+#endif /* MCUCONF_H */

diff --git a/firmware/source/cfg/mcuconf_l4.h b/firmware/source/cfg/mcuconf_l4.h
new file mode 100644
index 0000000..bf19f7a
--- /dev/null
+++ b/firmware/source/cfg/mcuconf_l4.h
@@ -0,0 +1,360 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/*

+ * STM32L4xx drivers configuration.

+ * The following settings override the default settings present in

+ * the various device driver implementation headers.

+ * Note that the settings for each driver only have effect if the whole

+ * driver is enabled in halconf.h.

+ *

+ * IRQ priorities:

+ * 15...0       Lowest...Highest.

+ *

+ * DMA priorities:

+ * 0...3        Lowest...Highest.

+ */

+

+#ifndef MCUCONF_H

+#define MCUCONF_H

+

+#define STM32L4xx_MCUCONF

+#define STM32L476_MCUCONF

+//#define STM32L432_MCUCONF

+

+/*

+ * HAL driver system settings.

+ */

+#define STM32_NO_INIT                       FALSE

+#define STM32_VOS                           STM32_VOS_RANGE1

+#define STM32_PVD_ENABLE                    FALSE

+#define STM32_PLS                           STM32_PLS_LEV0

+#define STM32_HSI16_ENABLED                 FALSE

+#define STM32_LSI_ENABLED                   TRUE

+#define STM32_HSE_ENABLED                   FALSE

+#define STM32_LSE_ENABLED                   FALSE

+#define STM32_MSIPLL_ENABLED                FALSE

+#define STM32_MSIRANGE                      STM32_MSIRANGE_4M

+#define STM32_MSISRANGE                     STM32_MSISRANGE_4M

+#define STM32_SW                            STM32_SW_PLL

+#define STM32_PLLSRC                        STM32_PLLSRC_MSI

+#define STM32_PLLM_VALUE                    1

+#define STM32_PLLN_VALUE                    72

+#define STM32_PLLP_VALUE                    7

+#define STM32_PLLQ_VALUE                    6

+#define STM32_PLLR_VALUE                    4

+#define STM32_HPRE                          STM32_HPRE_DIV1

+#define STM32_PPRE1                         STM32_PPRE1_DIV1

+#define STM32_PPRE2                         STM32_PPRE2_DIV1

+#define STM32_STOPWUCK                      STM32_STOPWUCK_MSI

+#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK

+#define STM32_MCOPRE                        STM32_MCOPRE_DIV1

+#define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK

+#define STM32_PLLSAI1N_VALUE                24

+#define STM32_PLLSAI1P_VALUE                7

+#define STM32_PLLSAI1Q_VALUE                2

+#define STM32_PLLSAI1R_VALUE                4

+#define STM32_PLLSAI2N_VALUE                24

+#define STM32_PLLSAI2P_VALUE                7

+#define STM32_PLLSAI2R_VALUE                8

+

+/*

+ * Peripherals clock sources.

+ */

+#define STM32_USART1SEL                     STM32_USART1SEL_SYSCLK

+#define STM32_USART2SEL                     STM32_USART2SEL_SYSCLK

+#define STM32_USART3SEL                     STM32_USART3SEL_SYSCLK

+#define STM32_UART4SEL                      STM32_UART4SEL_SYSCLK

+#define STM32_UART5SEL                      STM32_UART5SEL_SYSCLK

+#define STM32_LPUART1SEL                    STM32_LPUART1SEL_SYSCLK

+#define STM32_I2C1SEL                       STM32_I2C1SEL_SYSCLK

+#define STM32_I2C2SEL                       STM32_I2C2SEL_SYSCLK

+#define STM32_I2C3SEL                       STM32_I2C3SEL_SYSCLK

+#define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK1

+#define STM32_LPTIM2SEL                     STM32_LPTIM2SEL_PCLK1

+#define STM32_SAI1SEL                       STM32_SAI1SEL_OFF

+#define STM32_SAI2SEL                       STM32_SAI2SEL_OFF

+#define STM32_CLK48SEL                      STM32_CLK48SEL_PLLSAI1

+#define STM32_ADCSEL                        STM32_ADCSEL_PLLSAI2

+#define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1

+#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2

+#define STM32_RTCSEL                        STM32_RTCSEL_LSI

+

+/*

+ * IRQ system settings.

+ */

+#define STM32_IRQ_EXTI0_PRIORITY            6

+#define STM32_IRQ_EXTI1_PRIORITY            6

+#define STM32_IRQ_EXTI2_PRIORITY            6

+#define STM32_IRQ_EXTI3_PRIORITY            6

+#define STM32_IRQ_EXTI4_PRIORITY            6

+#define STM32_IRQ_EXTI5_9_PRIORITY          6

+#define STM32_IRQ_EXTI10_15_PRIORITY        6

+#define STM32_IRQ_EXTI1635_38_PRIORITY      6

+#define STM32_IRQ_EXTI18_PRIORITY           6

+#define STM32_IRQ_EXTI19_PRIORITY           6

+#define STM32_IRQ_EXTI20_PRIORITY           6

+#define STM32_IRQ_EXTI21_22_PRIORITY        15

+

+#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY   7

+#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY    7

+#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7

+#define STM32_IRQ_TIM1_CC_PRIORITY          7

+#define STM32_IRQ_TIM2_PRIORITY             7

+#define STM32_IRQ_TIM3_PRIORITY             7

+#define STM32_IRQ_TIM4_PRIORITY             7

+#define STM32_IRQ_TIM5_PRIORITY             7

+#define STM32_IRQ_TIM6_PRIORITY             7

+#define STM32_IRQ_TIM7_PRIORITY             7

+#define STM32_IRQ_TIM8_UP_PRIORITY          7

+#define STM32_IRQ_TIM8_CC_PRIORITY          7

+

+#define STM32_IRQ_USART1_PRIORITY           12

+#define STM32_IRQ_USART2_PRIORITY           12

+#define STM32_IRQ_USART3_PRIORITY           12

+#define STM32_IRQ_UART4_PRIORITY            12

+#define STM32_IRQ_UART5_PRIORITY            12

+#define STM32_IRQ_LPUART1_PRIORITY          12

+

+/*

+ * ADC driver system settings.

+ */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

+#define STM32_ADC_USE_ADC1                  TRUE

+#define STM32_ADC_USE_ADC2                  FALSE

+#define STM32_ADC_USE_ADC3                  TRUE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(1, 2)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(1, 3)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC12_IRQ_PRIORITY        5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC123_CLOCK_MODE         ADC_CCR_CKMODE_ADCCK

+#define STM32_ADC_ADC123_PRESC              ADC_CCR_PRESC_DIV10

+

+//#define ADC123_PRESC_VALUE 1

+

+/*

+ * CAN driver system settings.

+ */

+#define STM32_CAN_USE_CAN1                  FALSE

+#define STM32_CAN_CAN1_IRQ_PRIORITY         11

+

+/*

+ * DAC driver system settings.

+ */

+#define STM32_DAC_DUAL_MODE                 FALSE

+#define STM32_DAC_USE_DAC1_CH1              TRUE

+#define STM32_DAC_USE_DAC1_CH2              TRUE

+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10

+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10

+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2

+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2

+#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(2, 4)

+#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 4)

+

+/*

+ * GPT driver system settings.

+ */

+#define STM32_GPT_USE_TIM1                  FALSE

+#define STM32_GPT_USE_TIM2                  FALSE

+#define STM32_GPT_USE_TIM3                  FALSE

+#define STM32_GPT_USE_TIM4                  FALSE

+#define STM32_GPT_USE_TIM5                  FALSE

+#define STM32_GPT_USE_TIM6                  TRUE

+#define STM32_GPT_USE_TIM7                  TRUE

+#define STM32_GPT_USE_TIM8                  FALSE

+#define STM32_GPT_USE_TIM15                 FALSE

+#define STM32_GPT_USE_TIM16                 FALSE

+#define STM32_GPT_USE_TIM17                 FALSE

+

+/*

+ * I2C driver system settings.

+ */

+#define STM32_I2C_USE_I2C1                  FALSE

+#define STM32_I2C_USE_I2C2                  FALSE

+#define STM32_I2C_USE_I2C3                  FALSE

+#define STM32_I2C_BUSY_TIMEOUT              50

+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)

+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)

+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

+#define STM32_I2C_I2C1_IRQ_PRIORITY         5

+#define STM32_I2C_I2C2_IRQ_PRIORITY         5

+#define STM32_I2C_I2C3_IRQ_PRIORITY         5

+#define STM32_I2C_I2C1_DMA_PRIORITY         3

+#define STM32_I2C_I2C2_DMA_PRIORITY         3

+#define STM32_I2C_I2C3_DMA_PRIORITY         3

+#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")

+

+/*

+ * ICU driver system settings.

+ */

+#define STM32_ICU_USE_TIM1                  FALSE

+#define STM32_ICU_USE_TIM2                  FALSE

+#define STM32_ICU_USE_TIM3                  FALSE

+#define STM32_ICU_USE_TIM4                  FALSE

+#define STM32_ICU_USE_TIM5                  FALSE

+#define STM32_ICU_USE_TIM8                  FALSE

+#define STM32_ICU_USE_TIM15                 FALSE

+#define STM32_ICU_USE_TIM16                 FALSE

+#define STM32_ICU_USE_TIM17                 FALSE

+

+/*

+ * PWM driver system settings.

+ */

+#define STM32_PWM_USE_ADVANCED              FALSE

+#define STM32_PWM_USE_TIM1                  FALSE

+#define STM32_PWM_USE_TIM2                  FALSE

+#define STM32_PWM_USE_TIM3                  FALSE

+#define STM32_PWM_USE_TIM4                  FALSE

+#define STM32_PWM_USE_TIM5                  FALSE

+#define STM32_PWM_USE_TIM8                  FALSE

+#define STM32_PWM_USE_TIM15                 FALSE

+#define STM32_PWM_USE_TIM16                 FALSE

+#define STM32_PWM_USE_TIM17                 FALSE

+

+/*

+ * RTC driver system settings.

+ */

+#define STM32_RTC_PRESA_VALUE               32

+#define STM32_RTC_PRESS_VALUE               1024

+#define STM32_RTC_CR_INIT                   0

+#define STM32_RTC_TAMPCR_INIT               0

+

+/*

+ * SDC driver system settings.

+ */

+#define STM32_SDC_USE_SDMMC1                FALSE

+#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT   TRUE

+#define STM32_SDC_SDMMC_WRITE_TIMEOUT       1000

+#define STM32_SDC_SDMMC_READ_TIMEOUT        1000

+#define STM32_SDC_SDMMC_CLOCK_DELAY         10

+#define STM32_SDC_SDMMC1_DMA_PRIORITY       3

+#define STM32_SDC_SDMMC1_IRQ_PRIORITY       9

+#define STM32_SDC_SDMMC1_DMA_STREAM         STM32_DMA_STREAM_ID(2, 4)

+

+/*

+ * SERIAL driver system settings.

+ */

+#define STM32_SERIAL_USE_USART1             FALSE

+#define STM32_SERIAL_USE_USART2             TRUE

+#define STM32_SERIAL_USE_USART3             FALSE

+#define STM32_SERIAL_USE_UART4              FALSE

+#define STM32_SERIAL_USE_UART5              FALSE

+#define STM32_SERIAL_USE_LPUART1            FALSE

+#define STM32_SERIAL_USART1_PRIORITY        12

+#define STM32_SERIAL_USART2_PRIORITY        12

+#define STM32_SERIAL_USART3_PRIORITY        12

+#define STM32_SERIAL_UART4_PRIORITY         12

+#define STM32_SERIAL_UART5_PRIORITY         12

+#define STM32_SERIAL_LPUART1_PRIORITY       12

+

+/*

+ * SPI driver system settings.

+ */

+#define STM32_SPI_USE_SPI1                  FALSE

+#define STM32_SPI_USE_SPI2                  FALSE

+#define STM32_SPI_USE_SPI3                  FALSE

+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)

+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 4)

+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)

+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)

+#define STM32_SPI_SPI1_DMA_PRIORITY         1

+#define STM32_SPI_SPI2_DMA_PRIORITY         1

+#define STM32_SPI_SPI3_DMA_PRIORITY         1

+#define STM32_SPI_SPI1_IRQ_PRIORITY         10

+#define STM32_SPI_SPI2_IRQ_PRIORITY         10

+#define STM32_SPI_SPI3_IRQ_PRIORITY         10

+#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")

+

+/*

+ * ST driver system settings.

+ */

+#define STM32_ST_IRQ_PRIORITY               8

+#define STM32_ST_USE_TIMER                  2

+

+/*

+ * TRNG driver system settings.

+ */

+#define STM32_TRNG_USE_RNG1                 FALSE

+

+/*

+ * UART driver system settings.

+ */

+#define STM32_UART_USE_USART1               FALSE

+#define STM32_UART_USE_USART2               FALSE

+#define STM32_UART_USE_USART3               FALSE

+#define STM32_UART_USE_UART4                FALSE

+#define STM32_UART_USE_UART5                FALSE

+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)

+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 6)

+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)

+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)

+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)

+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)

+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)

+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)

+#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 2)

+#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 1)

+#define STM32_UART_USART1_IRQ_PRIORITY      12

+#define STM32_UART_USART2_IRQ_PRIORITY      12

+#define STM32_UART_USART3_IRQ_PRIORITY      12

+#define STM32_UART_UART4_IRQ_PRIORITY       12

+#define STM32_UART_UART5_IRQ_PRIORITY       12

+#define STM32_UART_USART1_DMA_PRIORITY      0

+#define STM32_UART_USART2_DMA_PRIORITY      0

+#define STM32_UART_USART3_DMA_PRIORITY      0

+#define STM32_UART_UART4_DMA_PRIORITY       0

+#define STM32_UART_UART5_DMA_PRIORITY       0

+#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

+

+/*

+ * USB driver system settings.

+ */

+#ifdef STM32L476_MCUCONF

+#define STM32_USB_USE_OTG1                  TRUE

+#define STM32_USB_OTG1_IRQ_PRIORITY         14

+#define STM32_USB_OTG1_RX_FIFO_SIZE         512

+#else

+#define STM32_USB_USE_USB1                  TRUE

+#define STM32_USB_LOW_POWER_ON_SUSPEND      FALSE

+#define STM32_USB_USB1_HP_IRQ_PRIORITY      13

+#define STM32_USB_USB1_LP_IRQ_PRIORITY      14

+#endif // STM32L476_MCUCONF

+

+/*

+ * WDG driver system settings.

+ */

+#define STM32_WDG_USE_IWDG                  FALSE

+

+/*

+ * WSPI driver system settings.

+ */

+#define STM32_WSPI_USE_QUADSPI1             FALSE

+#define STM32_WSPI_QUADSPI1_DMA_STREAM      STM32_DMA_STREAM_ID(2, 7)

+

+#endif /* MCUCONF_H */

diff --git a/firmware/source/communication.cpp b/firmware/source/communication.cpp
new file mode 100644
index 0000000..e85828b
--- /dev/null
+++ b/firmware/source/communication.cpp
@@ -0,0 +1,293 @@
+#include "communication.hpp"
+
+#include "ch.h"
+#include "hal.h"
+
+#include "periph/adc.hpp"
+#include "periph/dac.hpp"
+#include "periph/usbserial.hpp"
+#include "elfload.hpp"
+#include "error.hpp"
+#include "conversion.hpp"
+#include "runstatus.hpp"
+#include "samples.hpp"
+
+#include <algorithm>
+#include <tuple>
+
+__attribute__((section(".stacks")))
+std::array<char, 4096> CommunicationManager::m_thread_stack = {};
+
+void CommunicationManager::begin()
+{
+    chThdCreateStatic(m_thread_stack.data(),
+                      m_thread_stack.size(),
+                      NORMALPRIO,
+                      threadComm,
+                      nullptr);
+}
+
+static void writeADCBuffer(unsigned char *);
+static void setBufferSize(unsigned char *);
+static void updateGenerator(unsigned char *);
+static void loadAlgorithm(unsigned char *);
+static void readStatus(unsigned char *);
+static void measureConversion(unsigned char *);
+static void startConversion(unsigned char *);
+static void stopConversion(unsigned char *);
+static void startGenerator(unsigned char *);
+static void readADCBuffer(unsigned char *);
+static void readDACBuffer(unsigned char *);
+static void unloadAlgorithm(unsigned char *);
+static void readIdentifier(unsigned char *);
+static void readExecTime(unsigned char *);
+static void sampleRate(unsigned char *);
+static void readConversionResults(unsigned char *);
+static void readConversionInput(unsigned char *);
+static void readMessage(unsigned char *);
+static void stopGenerator(unsigned char *);
+
+static const std::array<std::pair<char, void (*)(unsigned char *)>, 19> commandTable {{
+    {'A', writeADCBuffer},
+    {'B', setBufferSize},
+    {'D', updateGenerator},
+    {'E', loadAlgorithm},
+    {'I', readStatus},
+    {'M', measureConversion},
+    {'R', startConversion},
+    {'S', stopConversion},
+    {'W', startGenerator},
+    {'a', readADCBuffer},
+    {'d', readDACBuffer},
+    {'e', unloadAlgorithm},
+    {'i', readIdentifier},
+    {'m', readExecTime},
+    {'r', sampleRate},
+    {'s', readConversionResults},
+    {'t', readConversionInput},
+    {'u', readMessage},
+    {'w', stopGenerator}
+}};
+
+void CommunicationManager::threadComm(void *)
+{
+	while (1) {
+        if (USBSerial::isActive()) {
+            // Attempt to receive a command packet
+            if (unsigned char cmd[3]; USBSerial::read(&cmd[0], 1) > 0) {
+                // Packet received, first byte represents the desired command/action
+                auto func = std::find_if(commandTable.cbegin(), commandTable.cend(),
+                                         [&cmd](const auto& f) { return f.first == cmd[0]; });
+                if (func != commandTable.cend())
+                    func->second(cmd);
+            }
+        }
+
+		chThdSleepMicroseconds(100);
+    }
+}
+
+void writeADCBuffer(unsigned char *)
+{
+    USBSerial::read(Samples::In.bytedata(), Samples::In.bytesize());
+}
+
+void setBufferSize(unsigned char *cmd)
+{
+    if (EM.assert(run_status == RunStatus::Idle, Error::NotIdle) &&
+        EM.assert(USBSerial::read(&cmd[1], 2) == 2, Error::BadParamSize))
+    {
+        // count is multiplied by two since this command receives size of buffer
+        // for each algorithm application.
+        unsigned int count = (cmd[1] | (cmd[2] << 8)) * 2;
+        if (EM.assert(count <= MAX_SAMPLE_BUFFER_SIZE, Error::BadParam)) {
+            Samples::In.setSize(count);
+            Samples::Out.setSize(count);
+        }
+    }
+}
+
+void updateGenerator(unsigned char *cmd)
+{
+    if (EM.assert(USBSerial::read(&cmd[1], 2) == 2, Error::BadParamSize)) {
+        unsigned int count = cmd[1] | (cmd[2] << 8);
+        if (EM.assert(count <= MAX_SAMPLE_BUFFER_SIZE, Error::BadParam)) {
+            if (!DAC::isSigGenRunning()) {
+                Samples::Generator.setSize(count);
+                USBSerial::read(
+                    reinterpret_cast<uint8_t *>(Samples::Generator.data()),
+                    Samples::Generator.bytesize());
+            } else {
+                const int more = DAC::sigGenWantsMore();
+                if (more == -1) {
+                    USBSerial::write(reinterpret_cast<const uint8_t *>("\0"), 1);
+                } else {
+                    USBSerial::write(reinterpret_cast<const uint8_t *>("\1"), 1);
+
+                    // Receive streamed samples in half-buffer chunks.
+                    USBSerial::read(reinterpret_cast<uint8_t *>(
+                        more == 0 ? Samples::Generator.data() : Samples::Generator.middata()),
+                        Samples::Generator.bytesize() / 2);
+                }
+            }
+        }
+    }
+}
+
+void loadAlgorithm(unsigned char *cmd)
+{
+    if (EM.assert(run_status == RunStatus::Idle, Error::NotIdle) &&
+        EM.assert(USBSerial::read(&cmd[1], 2) == 2, Error::BadParamSize))
+    {
+        // Only load the binary if it can fit in the memory reserved for it.
+        unsigned int size = cmd[1] | (cmd[2] << 8);
+        if (EM.assert(size < MAX_ELF_FILE_SIZE, Error::BadUserCodeSize)) {
+            USBSerial::read(ELFManager::fileBuffer(), size);
+            auto success = ELFManager::loadFromInternalBuffer();
+            EM.assert(success, Error::BadUserCodeLoad);
+        }
+    }
+}
+
+void readStatus(unsigned char *)
+{
+    unsigned char buf[2] = {
+        static_cast<unsigned char>(run_status),
+        static_cast<unsigned char>(EM.pop())
+    };
+
+    USBSerial::write(buf, sizeof(buf));
+}
+
+void measureConversion(unsigned char *)
+{
+    if (EM.assert(run_status == RunStatus::Running, Error::NotRunning))
+        ConversionManager::startMeasurement();
+}
+
+void startConversion(unsigned char *)
+{
+    if (EM.assert(run_status == RunStatus::Idle, Error::NotIdle)) {
+        run_status = RunStatus::Running;
+        ConversionManager::start();
+    }
+}
+
+void stopConversion(unsigned char *)
+{
+    if (EM.assert(run_status == RunStatus::Running, Error::NotRunning)) {
+        ConversionManager::stop();
+        run_status = RunStatus::Idle;
+    }
+}
+
+void startGenerator(unsigned char *)
+{
+    DAC::start(1, Samples::Generator.data(), Samples::Generator.size());
+}
+
+void readADCBuffer(unsigned char *)
+{
+    USBSerial::write(Samples::In.bytedata(), Samples::In.bytesize());
+}
+
+void readDACBuffer(unsigned char *)
+{
+
+    USBSerial::write(Samples::Out.bytedata(), Samples::Out.bytesize());
+}
+
+void unloadAlgorithm(unsigned char *)
+{
+    ELFManager::unload();
+}
+
+void readIdentifier(unsigned char *)
+{
+#if defined(TARGET_PLATFORM_H7)
+    USBSerial::write(reinterpret_cast<const uint8_t *>("stmdsph"), 7);
+#else
+    USBSerial::write(reinterpret_cast<const uint8_t *>("stmdspl"), 7);
+#endif
+}
+
+void readExecTime(unsigned char *)
+{
+    // Stores the measured execution time.
+    extern time_measurement_t conversion_time_measurement;
+    USBSerial::write(reinterpret_cast<uint8_t *>(&conversion_time_measurement.last),
+                     sizeof(rtcnt_t));
+}
+
+void sampleRate(unsigned char *cmd)
+{
+    if (EM.assert(USBSerial::read(&cmd[1], 1) == 1, Error::BadParamSize)) {
+        if (cmd[1] == 0xFF) {
+            unsigned char r = SClock::getRate();
+            USBSerial::write(&r, 1);
+        } else {
+            auto r = static_cast<SClock::Rate>(cmd[1]);
+            SClock::setRate(r);
+            ADC::setRate(r);
+        }
+    }
+}
+
+void readConversionResults(unsigned char *)
+{
+    if (auto samps = Samples::Out.modified(); samps != nullptr) {
+        unsigned char buf[2] = {
+            static_cast<unsigned char>(Samples::Out.size() / 2 & 0xFF),
+            static_cast<unsigned char>(((Samples::Out.size() / 2) >> 8) & 0xFF)
+        };
+        USBSerial::write(buf, 2);
+        unsigned int total = Samples::Out.bytesize() / 2;
+        unsigned int offset = 0;
+        unsigned char unused;
+        while (total > 512) {
+            USBSerial::write(reinterpret_cast<uint8_t *>(samps) + offset, 512);
+            while (USBSerial::read(&unused, 1) == 0);
+            offset += 512;
+            total -= 512;
+        }
+        USBSerial::write(reinterpret_cast<uint8_t *>(samps) + offset, total);
+        while (USBSerial::read(&unused, 1) == 0);
+    } else {
+        USBSerial::write(reinterpret_cast<const uint8_t *>("\0\0"), 2);
+    }
+}
+
+void readConversionInput(unsigned char *)
+{
+    if (auto samps = Samples::In.modified(); samps != nullptr) {
+        unsigned char buf[2] = {
+            static_cast<unsigned char>(Samples::In.size() / 2 & 0xFF),
+            static_cast<unsigned char>(((Samples::In.size() / 2) >> 8) & 0xFF)
+        };
+        USBSerial::write(buf, 2);
+        unsigned int total = Samples::In.bytesize() / 2;
+        unsigned int offset = 0;
+        unsigned char unused;
+        while (total > 512) {
+            USBSerial::write(reinterpret_cast<uint8_t *>(samps) + offset, 512);
+            while (USBSerial::read(&unused, 1) == 0);
+            offset += 512;
+            total -= 512;
+        }
+        USBSerial::write(reinterpret_cast<uint8_t *>(samps) + offset, total);
+        while (USBSerial::read(&unused, 1) == 0);
+    } else {
+        USBSerial::write(reinterpret_cast<const uint8_t *>("\0\0"), 2);
+    }
+}
+
+void readMessage(unsigned char *)
+{
+    //USBSerial::write(reinterpret_cast<uint8_t *>(userMessageBuffer), userMessageSize);
+}
+
+void stopGenerator(unsigned char *)
+{
+    DAC::stop(1);
+}
+
diff --git a/firmware/source/communication.hpp b/firmware/source/communication.hpp
new file mode 100644
index 0000000..03220b8
--- /dev/null
+++ b/firmware/source/communication.hpp
@@ -0,0 +1,29 @@
+/**
+ * @file communication.hpp
+ * @brief Manages communication with the host computer.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef STMDSP_COMMUNICATION_HPP
+#define STMDSP_COMMUNICATION_HPP
+
+#include <array>
+
+class CommunicationManager
+{
+public:
+    static void begin();
+
+private:
+    static void threadComm(void *);
+
+    static std::array<char, 4096> m_thread_stack;
+};
+
+#endif // STMDSP_COMMUNICATION_HPP
+
diff --git a/firmware/source/conversion.cpp b/firmware/source/conversion.cpp
new file mode 100644
index 0000000..56a689e
--- /dev/null
+++ b/firmware/source/conversion.cpp
@@ -0,0 +1,218 @@
+/**
+ * @file conversion.cpp
+ * @brief Manages algorithm application (converts input samples to output).
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "conversion.hpp"
+
+#include "periph/adc.hpp"
+#include "periph/dac.hpp"
+#include "elfload.hpp"
+#include "error.hpp"
+#include "runstatus.hpp"
+#include "samples.hpp"
+
+// MSG_* things below are macros rather than constexpr
+// to ensure inlining.
+
+#define MSG_CONVFIRST          (1)
+#define MSG_CONVSECOND         (2)
+#define MSG_CONVFIRST_MEASURE  (3)
+#define MSG_CONVSECOND_MEASURE (4)
+
+#define MSG_FOR_FIRST(msg)   (msg & 1)
+#define MSG_FOR_MEASURE(msg) (msg > 2)
+
+__attribute__((section(".convdata")))
+thread_t *ConversionManager::m_thread_monitor = nullptr;
+thread_t *ConversionManager::m_thread_runner = nullptr;
+
+__attribute__((section(".stacks")))
+std::array<char, 1024> ConversionManager::m_thread_monitor_stack = {};
+__attribute__((section(".stacks")))
+std::array<char, THD_WORKING_AREA_SIZE(128)> ConversionManager::m_thread_runner_entry_stack = {};
+__attribute__((section(".convdata")))
+std::array<char, CONVERSION_THREAD_STACK_SIZE> ConversionManager::m_thread_runner_stack = {};
+
+std::array<msg_t, 2> ConversionManager::m_mailbox_buffer;
+mailbox_t ConversionManager::m_mailbox = _MAILBOX_DATA(m_mailbox, m_mailbox_buffer.data(), m_mailbox_buffer.size());
+
+void ConversionManager::begin()
+{
+    m_thread_monitor = chThdCreateStatic(m_thread_monitor_stack.data(),
+                                         m_thread_monitor_stack.size(),
+                                         NORMALPRIO + 1,
+                                         threadMonitor,
+                                         nullptr);
+    auto runner_stack_end = &m_thread_runner_stack[CONVERSION_THREAD_STACK_SIZE];
+    m_thread_runner = chThdCreateStatic(m_thread_runner_entry_stack.data(),
+                                        m_thread_runner_entry_stack.size(),
+                                        HIGHPRIO,
+                                        threadRunnerEntry,
+                                        runner_stack_end);
+}
+
+void ConversionManager::start()
+{
+    Samples::Out.clear();
+    ADC::start(Samples::In.data(), Samples::In.size(), adcReadHandler);
+    DAC::start(0, Samples::Out.data(), Samples::Out.size());
+}
+
+void ConversionManager::startMeasurement()
+{
+    ADC::setOperation(adcReadHandlerMeasure);
+}
+
+void ConversionManager::stop()
+{
+    DAC::stop(0);
+    ADC::stop();
+}
+
+thread_t *ConversionManager::getMonitorHandle()
+{
+    return m_thread_monitor;
+}
+
+void ConversionManager::abort(bool fpu_stacked)
+{
+    ELFManager::unload();
+    EM.add(Error::ConversionAborted);
+    //run_status = RunStatus::Recovering;
+
+    // Confirm that the exception return thread is the algorithm...
+    uint32_t *psp;
+	asm("mrs %0, psp" : "=r" (psp));
+
+    bool isRunnerStack = 
+           (uint32_t)psp >= reinterpret_cast<uint32_t>(m_thread_runner_stack.data()) &&
+           (uint32_t)psp <= reinterpret_cast<uint32_t>(m_thread_runner_stack.data() +
+                                                       m_thread_runner_stack.size());
+
+    if (isRunnerStack)
+    {
+        // If it is, we can force the algorithm to exit by "resetting" its thread.
+        // We do this by rebuilding the thread's stacked exception return.
+        auto newpsp = reinterpret_cast<uint32_t *>(m_thread_runner_stack.data() + 
+                                                   m_thread_runner_stack.size() -
+                                                   (fpu_stacked ? 26 : 8) * sizeof(uint32_t));
+        // Set the LR register to the thread's entry point.
+        newpsp[5] = reinterpret_cast<uint32_t>(threadRunner);
+        // Overwrite the instruction we'll return to with "bx lr" (jump to address in LR).
+        newpsp[6] = psp[6];
+        *reinterpret_cast<uint16_t *>(newpsp[6]) = 0x4770; // "bx lr"
+        // Keep PSR contents (bit set forces Thumb mode, just in case).
+        newpsp[7] = psp[7] | (1 << 24);
+        // Set the new stack pointer.
+	    asm("msr psp, %0" :: "r" (newpsp));
+    }
+}
+
+void ConversionManager::threadMonitor(void *)
+{
+    while (1) {
+        msg_t message;
+        msg_t fetch = chMBFetchTimeout(&m_mailbox, &message, TIME_INFINITE);
+        if (fetch == MSG_OK)
+            chMsgSend(m_thread_runner, message);
+    }
+}
+
+void ConversionManager::threadRunnerEntry(void *stack)
+{
+    ELFManager::unload();
+    port_unprivileged_jump(reinterpret_cast<uint32_t>(threadRunner),
+                           reinterpret_cast<uint32_t>(stack));
+}
+
+__attribute__((section(".convcode")))
+void ConversionManager::threadRunner(void *)
+{
+    while (1) {
+        // Sleep until we receive a mailbox message.
+        msg_t message;
+        asm("svc 0; mov %0, r0" : "=r" (message));
+
+        if (message != 0) {
+            auto samples = MSG_FOR_FIRST(message) ? Samples::In.data()
+                                                  : Samples::In.middata();
+            auto size = Samples::In.size() / 2;
+
+            auto entry = ELFManager::loadedElf();
+            if (entry) {
+                // Below, we remember the stack pointer just in case the
+                // loaded algorithm messes things up.
+                uint32_t sp;
+
+                if (!MSG_FOR_MEASURE(message)) {
+                    asm("mov %0, sp" : "=r" (sp));
+                    samples = entry(samples, size);
+                    asm("mov sp, %0" :: "r" (sp));
+                    volatile auto testRead = *samples;
+                } else {
+                    // Start execution timer:
+                    asm("mov %0, sp; eor r0, r0; svc 2" : "=r" (sp));
+                    samples = entry(samples, size);
+                    // Stop execution timer:
+                    asm("mov r0, #1; svc 2; mov sp, %0" :: "r" (sp));
+                    volatile auto testRead = *samples;
+                } 
+            }
+
+            // Update the sample out buffer with the transformed samples.
+            if (samples != nullptr) {
+                if (MSG_FOR_FIRST(message))
+                    Samples::Out.modify(samples, size);
+                else
+                    Samples::Out.midmodify(samples, size);
+            }
+        }
+    }
+}
+
+void ConversionManager::adcReadHandler(adcsample_t *buffer, size_t)
+{
+    chSysLockFromISR();
+
+    // If previous request hasn't been handled, then we're going too slow.
+    // We'll need to abort.
+    if (chMBGetUsedCountI(&m_mailbox) > 1) {
+        chMBResetI(&m_mailbox);
+        chMBResumeX(&m_mailbox);
+        chSysUnlockFromISR();
+        abort();
+    } else {
+        // Mark the modified samples as 'fresh' or ready for manipulation.
+        if (buffer == Samples::In.data()) {
+            Samples::In.setModified();
+            chMBPostI(&m_mailbox, MSG_CONVFIRST);
+        } else {
+            Samples::In.setMidmodified();
+            chMBPostI(&m_mailbox, MSG_CONVSECOND);
+        }
+        chSysUnlockFromISR();
+    }
+}
+
+void ConversionManager::adcReadHandlerMeasure(adcsample_t *buffer, size_t)
+{
+    chSysLockFromISR();
+    if (buffer == Samples::In.data()) {
+        Samples::In.setModified();
+        chMBPostI(&m_mailbox, MSG_CONVFIRST_MEASURE);
+    } else {
+        Samples::In.setMidmodified();
+        chMBPostI(&m_mailbox, MSG_CONVSECOND_MEASURE);
+    }
+    chSysUnlockFromISR();
+
+    ADC::setOperation(adcReadHandler);
+}
+
diff --git a/firmware/source/conversion.hpp b/firmware/source/conversion.hpp
new file mode 100644
index 0000000..ca0054a
--- /dev/null
+++ b/firmware/source/conversion.hpp
@@ -0,0 +1,64 @@
+/**
+ * @file conversion.hpp
+ * @brief Manages algorithm application (converts input samples to output).
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef STMDSP_CONVERSION_HPP
+#define STMDSP_CONVERSION_HPP
+
+#include "ch.h"
+#include "hal.h"
+
+#include <array>
+
+constexpr unsigned int CONVERSION_THREAD_STACK_SIZE = 
+#if defined(TARGET_PLATFORM_H7)
+                                                  62 * 1024;
+#else
+                                                  15 * 1024;
+#endif
+
+class ConversionManager
+{
+public:
+    static void begin();
+
+    // Begins sample conversion.
+    static void start();
+    // Prepare to measure execution time of next conversion.
+    static void startMeasurement();
+    // Stops conversion.
+    static void stop();
+
+    static thread_t *getMonitorHandle();
+
+    // Internal only: Aborts a running conversion.
+    static void abort(bool fpu_stacked = true);
+
+private:
+    static void threadMonitor(void *);
+    static void threadRunnerEntry(void *stack);
+
+    static void threadRunner(void *);
+    static void adcReadHandler(adcsample_t *buffer, size_t);
+    static void adcReadHandlerMeasure(adcsample_t *buffer, size_t);
+
+    static thread_t *m_thread_monitor;
+    static thread_t *m_thread_runner;
+
+    static std::array<char, 1024> m_thread_monitor_stack;
+    static std::array<char, THD_WORKING_AREA_SIZE(128)> m_thread_runner_entry_stack;
+    static std::array<char, CONVERSION_THREAD_STACK_SIZE> m_thread_runner_stack;
+
+    static std::array<msg_t, 2> m_mailbox_buffer;
+    static mailbox_t m_mailbox;
+};
+
+#endif // STMDSP_CONVERSION_HPP
+
diff --git a/firmware/source/elf.h b/firmware/source/elf.h
new file mode 100644
index 0000000..998356d
--- /dev/null
+++ b/firmware/source/elf.h
@@ -0,0 +1,100 @@
+/**
+ * @file elf.h
+ * @brief Defines ELF binary format info.
+ *
+ * Free to use, written by Clyne Sullivan.
+ */
+
+#ifndef STMDSP_ELF_HPP
+#define STMDSP_ELF_HPP
+
+#include <cstdint>
+
+#define EI_NIDENT 16
+
+#define PT_NULL     0
+#define PT_LOAD     1
+#define PT_DYNAMIC  2
+#define PT_INTERP   3
+#define PT_NOTE     4
+#define PT_SHLIB    5
+#define PT_PHDR     6
+#define PT_RESERVED 0x70000000
+
+#define ELF32_ST_BIND(i)    ((i) >> 4)
+#define ELF32_ST_TYPE(i)    ((i) & 0xF)
+#define ELF32_ST_INFO(b, t) (((b) << 4) + ((t) & 0xF))
+
+#define ELF32_R_SYM(i)     ((i) >> 8)
+#define ELF32_R_TYPE(i)    ((i) & 0xFF)
+#define ELF32_R_INFO(s, t) (((s) << 8) + ((t) & 0xFF))
+
+typedef uint32_t Elf32_Addr;
+typedef uint16_t Elf32_Half;
+typedef uint32_t Elf32_Off;
+typedef uint32_t Elf32_Sword;
+typedef uint32_t Elf32_Word;
+
+typedef struct {
+	unsigned char e_ident[EI_NIDENT];
+	Elf32_Half    e_type;
+	Elf32_Half    e_machine;
+	Elf32_Word    e_version;
+	Elf32_Addr    e_entry;
+	Elf32_Off     e_phoff;
+	Elf32_Off     e_shoff;
+	Elf32_Word    e_flags;
+	Elf32_Half    e_ehsize;
+	Elf32_Half    e_phentsize;
+	Elf32_Half    e_phnum;
+	Elf32_Half    e_shentsize;
+	Elf32_Half    e_shnum;
+	Elf32_Half    e_shstrndx;
+} __attribute__((packed)) Elf32_Ehdr;
+
+typedef struct {
+	Elf32_Word sh_name;
+	Elf32_Word sh_type;
+	Elf32_Word sh_flags;
+	Elf32_Addr sh_addr;
+	Elf32_Off  sh_offset;
+	Elf32_Word sh_size;
+	Elf32_Word sh_link;
+	Elf32_Word sh_info;
+	Elf32_Word sh_addralign;
+	Elf32_Word sh_entsize;
+} __attribute__((packed)) Elf32_Shdr;
+
+typedef struct {
+	Elf32_Word    st_name;
+	Elf32_Addr    st_value;
+	Elf32_Word    st_size;
+	unsigned char st_info;
+	unsigned char st_other;
+	Elf32_Half    st_shndx;
+} __attribute__((packed)) Elf32_Sym;
+
+typedef struct {
+	Elf32_Addr r_offset;
+	Elf32_Word r_info;
+} __attribute__((packed)) Elf32_Rel;
+
+typedef struct {
+	Elf32_Addr  r_offset;
+	Elf32_Word  r_info;
+	Elf32_Sword r_addend;
+} __attribute__((packed)) Elf32_Rela;
+
+typedef struct {
+	Elf32_Word p_type;
+	Elf32_Off  p_offset;
+	Elf32_Addr p_vaddr;
+	Elf32_Addr p_paddr;
+	Elf32_Word p_filesz;
+	Elf32_Word p_memsz;
+	Elf32_Word p_flags;
+	Elf32_Word p_align;
+} __attribute__((packed)) Elf32_Phdr;
+
+#endif // STMDSP_ELF_HPP
+
diff --git a/firmware/source/elfload.cpp b/firmware/source/elfload.cpp
new file mode 100644
index 0000000..87461e4
--- /dev/null
+++ b/firmware/source/elfload.cpp
@@ -0,0 +1,84 @@
+/**
+ * @file elfload.cpp
+ * @brief Loads ELF binary data into memory for execution.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "elfload.hpp"
+#include "elf.h"
+
+#include <algorithm>
+#include <cstring>
+
+__attribute__((section(".convdata")))
+ELFManager::EntryFunc ELFManager::m_entry = nullptr;
+std::array<unsigned char, MAX_ELF_FILE_SIZE> ELFManager::m_file_buffer = {};
+
+static const unsigned char elf_header[] = { '\177', 'E', 'L', 'F' };
+
+__attribute__((section(".convcode")))
+ELFManager::EntryFunc ELFManager::loadedElf()
+{
+    return m_entry;
+}
+
+unsigned char *ELFManager::fileBuffer()
+{
+    return m_file_buffer.data();
+}
+
+void ELFManager::unload()
+{
+    m_entry = nullptr;
+}
+
+template<typename T>
+constexpr static auto ptr_from_offset(void *base, uint32_t offset)
+{
+    return reinterpret_cast<T>(reinterpret_cast<uint8_t *>(base) + offset);
+}
+
+bool ELFManager::loadFromInternalBuffer()
+{
+    m_entry = nullptr;
+
+    auto elf_data = m_file_buffer.data();
+
+    // Check the ELF's header signature
+    auto ehdr = reinterpret_cast<Elf32_Ehdr *>(elf_data);
+    if (!std::equal(ehdr->e_ident, ehdr->e_ident + 4, elf_header))
+        return false;
+
+    // Iterate through program header LOAD sections
+    bool loaded = false;
+    auto phdr = ptr_from_offset<Elf32_Phdr *>(elf_data, ehdr->e_phoff);
+    for (Elf32_Half i = 0; i < ehdr->e_phnum; i++) {
+        if (phdr->p_type == PT_LOAD) {
+            if (phdr->p_filesz == 0) {
+                std::memset(reinterpret_cast<void *>(phdr->p_vaddr),
+                            0,
+                            phdr->p_memsz);
+            } else {
+                std::memcpy(reinterpret_cast<void *>(phdr->p_vaddr),
+                            ptr_from_offset<void *>(elf_data, phdr->p_offset),
+                            phdr->p_filesz);
+                if (!loaded)
+                    loaded = true;
+            }
+        }
+
+        phdr = ptr_from_offset<Elf32_Phdr *>(phdr, ehdr->e_phentsize);
+    }
+
+
+    if (loaded)
+        m_entry = reinterpret_cast<ELFManager::EntryFunc>(ehdr->e_entry);
+
+    return loaded;
+}
+
diff --git a/firmware/source/elfload.hpp b/firmware/source/elfload.hpp
new file mode 100644
index 0000000..10d95d7
--- /dev/null
+++ b/firmware/source/elfload.hpp
@@ -0,0 +1,39 @@
+/**
+ * @file elfload.hpp
+ * @brief Loads ELF binary data into memory for execution.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef ELF_LOAD_HPP_
+#define ELF_LOAD_HPP_
+
+#include "samplebuffer.hpp"
+
+#include <array>
+#include <cstddef>
+
+constexpr unsigned int MAX_ELF_FILE_SIZE = 16 * 1024;
+
+class ELFManager
+{
+public:
+    using EntryFunc = Sample *(*)(Sample *, size_t);
+    
+    static bool loadFromInternalBuffer();
+    static EntryFunc loadedElf();
+    static unsigned char *fileBuffer();
+    static void unload();
+
+private:
+    static EntryFunc m_entry;
+
+    static std::array<unsigned char, MAX_ELF_FILE_SIZE> m_file_buffer;
+};
+
+#endif // ELF_LOAD_HPP_
+
diff --git a/firmware/source/error.cpp b/firmware/source/error.cpp
new file mode 100644
index 0000000..9f2e98f
--- /dev/null
+++ b/firmware/source/error.cpp
@@ -0,0 +1,38 @@
+/**
+ * @file error.cpp
+ * @brief Tracks and reports non-critical errors.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "error.hpp"
+
+ErrorManager EM;
+
+void ErrorManager::add(Error error)
+{ 
+    if (m_index < m_queue.size())
+        m_queue[m_index++] = error;
+}
+
+bool ErrorManager::assert(bool condition, Error error)
+{
+    if (!condition)
+        add(error);
+    return condition;
+}
+
+bool ErrorManager::hasError()
+{
+    return m_index > 0;
+}
+
+Error ErrorManager::pop()
+{
+    return m_index == 0 ? Error::None : m_queue[--m_index];
+}
+
diff --git a/firmware/source/error.hpp b/firmware/source/error.hpp
new file mode 100644
index 0000000..c6a7f5c
--- /dev/null
+++ b/firmware/source/error.hpp
@@ -0,0 +1,47 @@
+/**
+ * @file error.hpp
+ * @brief Tracks and reports non-critical errors.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef STMDSP_ERROR_HPP
+#define STMDSP_ERROR_HPP
+
+#include <array>
+
+enum class Error : char
+{
+    None = 0,
+    BadParam,
+    BadParamSize,
+    BadUserCodeLoad,
+    BadUserCodeSize,
+    NotIdle,
+    ConversionAborted,
+    NotRunning
+};
+
+class ErrorManager
+{
+    constexpr static unsigned int MAX_ERROR_QUEUE_SIZE = 8;
+
+public:
+    void add(Error error);
+    bool assert(bool condition, Error error);
+    bool hasError();
+    Error pop();
+
+private:
+    std::array<Error, MAX_ERROR_QUEUE_SIZE> m_queue;
+    unsigned int m_index = 0;
+};
+
+extern ErrorManager EM;
+
+#endif // STMDSP_ERROR_HPP
+
diff --git a/firmware/source/handlers.cpp b/firmware/source/handlers.cpp
new file mode 100644
index 0000000..43e65c3
--- /dev/null
+++ b/firmware/source/handlers.cpp
@@ -0,0 +1,140 @@
+#include "handlers.hpp"
+
+#include "adc.hpp"
+#include "conversion.hpp"
+#include "cordic.hpp"
+#include "runstatus.hpp"
+
+extern "C" {
+
+time_measurement_t conversion_time_measurement;
+
+__attribute__((naked))
+void port_syscall(struct port_extctx *ctxp, uint32_t n)
+{
+    switch (n) {
+
+    // Sleeps the current thread until a message is received.
+    // Used the algorithm runner to wait for new data.
+    case 0:
+        {
+            chSysLock();
+            chMsgWaitS();
+            auto monitor = ConversionManager::getMonitorHandle();
+            auto msg = chMsgGet(monitor);
+            chMsgReleaseS(monitor, MSG_OK);
+            chSysUnlock();
+            ctxp->r0 = msg;
+        }
+        break;
+
+    // Provides access to advanced math functions.
+    // A service call like this is required for some hardware targets that
+    // provide hardware-accelerated math computations (e.g. CORDIC).
+    case 1:
+        {
+            using mathcall = void (*)();
+            static mathcall funcs[3] = {
+                reinterpret_cast<mathcall>(cordic::sin),
+                reinterpret_cast<mathcall>(cordic::cos),
+                reinterpret_cast<mathcall>(cordic::tan),
+            };
+#if defined(PLATFORM_H7)
+            asm("vmov.f64 d0, %0, %1" :: "r" (ctxp->r1), "r" (ctxp->r2));
+            if (ctxp->r0 < 3) {
+                funcs[ctxp->r0]();
+                asm("vmov.f64 %0, %1, d0" : "=r" (ctxp->r1), "=r" (ctxp->r2));
+            } else {
+                asm("eor r0, r0; vmov.f64 d0, r0, r0");
+            }
+#else
+            asm("vmov.f32 s0, %0" :: "r" (ctxp->r1));
+            if (ctxp->r0 < 3) {
+                funcs[ctxp->r0]();
+                asm("vmov.f32 %0, s0" : "=r" (ctxp->r1));
+            } else {
+                asm("eor r0, r0; vmov.f32 s0, r0");
+            }
+#endif
+        }
+        break;
+
+    // Starts or stops precise cycle time measurement.
+    // Used to measure algorithm execution time.
+    case 2:
+        if (ctxp->r0 == 0) {
+            chTMStartMeasurementX(&conversion_time_measurement);
+        } else {
+            chTMStopMeasurementX(&conversion_time_measurement);
+            // Subtract measurement overhead from the result.
+            // Running an empty algorithm ("bx lr") takes 196 cycles as of 2/4/21.
+            // Only measures algorithm code time (loading args/storing result takes 9 cycles).
+            constexpr rtcnt_t measurement_overhead = 196 - 1;
+            if (conversion_time_measurement.last > measurement_overhead)
+                conversion_time_measurement.last -= measurement_overhead;
+        }
+        break;
+
+    // Reads one of the analog inputs made available for algorithm run-time input.
+    case 3:
+        ctxp->r0 = ADC::readAlt(ctxp->r0);
+        break;
+
+    //case 4:
+    //    {
+    //        const char *str = reinterpret_cast<const char *>(ctxp->r0);
+    //        auto src = str;
+    //        auto dst = userMessageBuffer;
+    //        while (*src)
+    //            *dst++ = *src++;
+    //        *dst = '\0';
+    //        userMessageSize = src - str;
+    //    }
+    //    break;
+    default:
+        while (1);
+        break;
+    }
+
+    asm("svc 0");
+    while (1);
+}
+
+__attribute__((naked))
+void MemManage_Handler()
+{
+    // 1. Get the stack pointer.
+    uint32_t lr;
+    asm("mov %0, lr" : "=r" (lr));
+
+    // 2. Recover from the fault.
+    ConversionManager::abort((lr & (1 << 4)) ? false : true);
+
+    // 3. Return.
+    asm("mov lr, %0; bx lr" :: "r" (lr));
+}
+
+__attribute__((naked))
+void HardFault_Handler()
+{
+    // Get the stack pointer.
+    //uint32_t *stack;
+    uint32_t lr;
+    asm("mov %0, lr" : "=r" (lr));
+    /*asm("\
+        tst lr, #4; \
+        ite eq; \
+        mrseq %0, msp; \
+        mrsne %0, psp; \
+        mov %1, lr; \
+    " : "=r" (stack), "=r" (lr));*/
+
+    // If coming from the algorithm, attempt to recover; otherwise, give up.
+    if (run_status != RunStatus::Running && (lr & 4) != 0)
+        MemManage_Handler();
+
+    while (1);
+}
+
+} // extern "C"
+
diff --git a/firmware/source/handlers.hpp b/firmware/source/handlers.hpp
new file mode 100644
index 0000000..fd7e10c
--- /dev/null
+++ b/firmware/source/handlers.hpp
@@ -0,0 +1,31 @@
+/**
+ * @file handlers.hpp
+ * @brief Interrupt service routine handlers.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef STMDSP_HANDLERS_HPP
+#define STMDSP_HANDLERS_HPP
+
+#include "ch.h"
+
+extern "C" {
+
+__attribute__((naked))
+void port_syscall(struct port_extctx *ctxp, uint32_t n);
+
+__attribute__((naked))
+void MemManage_Handler();
+
+__attribute__((naked))
+void HardFault_Handler();
+
+}
+
+#endif // STMDSP_HANDLERS_HPP
+
diff --git a/firmware/source/ld/STM32H723xG.ld b/firmware/source/ld/STM32H723xG.ld
new file mode 100644
index 0000000..7d5bafb
--- /dev/null
+++ b/firmware/source/ld/STM32H723xG.ld
@@ -0,0 +1,124 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/*

+ * AXI SRAM     - BSS, Data, Heap.

+ * SRAM1        - SIGGEN.

+ * SRAM2        - DAC.

+ * SRAM4        - ADC.

+ * DTCM-RAM     - Process stacks.

+ * ITCM-RAM     - STMDSP Algorithm.

+ * BCKP SRAM    - None.

+ */

+MEMORY

+{

+    flash0 (rx) : org = 0x08000000, len = 1M       /* Flash bank1 + bank2 */

+    flash1 (rx) : org = 0x08000000, len = 510K     /* Flash bank 1 */

+    flashc (rx) : org = 0x0807F800, len = 2K       /* Unprivileged firmware */

+    flash2 (rx) : org = 0x08080000, len = 512K     /* Flash bank 2 */

+    flash3 (rx) : org = 0x00000000, len = 0

+    flash4 (rx) : org = 0x00000000, len = 0

+    flash5 (rx) : org = 0x00000000, len = 0

+    flash6 (rx) : org = 0x00000000, len = 0

+    flash7 (rx) : org = 0x00000000, len = 0

+    ram0   (wx) : org = 0x24000000, len = 320K     /* AXI SRAM */

+    ram1   (wx) : org = 0x30000000, len = 16K      /* AHB SRAM1 */

+    ram2   (wx) : org = 0x30004000, len = 16K      /* AHB SRAM2 */

+    ram3   (wx) : org = 0x38000000, len = 16K      /* AHB SRAM4 */

+    ram4   (wx) : org = 0x00000000, len = 0

+    ramc   (wx) : org = 0x20000000, len = 64K      /* Unprivileged data */

+    ram5   (wx) : org = 0x20010000, len = 64K      /* DTCM-RAM */

+    ram6   (wx) : org = 0x00000000, len = 64K      /* ITCM-RAM */

+    ram7   (wx) : org = 0x38800000, len = 4K       /* BCKP SRAM */

+}

+

+/* For each data/text section two region are defined, a virtual region

+   and a load region (_LMA suffix).*/

+

+/* Flash region to be used for exception vectors.*/

+REGION_ALIAS("VECTORS_FLASH", flash0);

+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);

+

+/* Flash region to be used for constructors and destructors.*/

+REGION_ALIAS("XTORS_FLASH", flash0);

+REGION_ALIAS("XTORS_FLASH_LMA", flash0);

+

+/* Flash region to be used for code text.*/

+REGION_ALIAS("TEXT_FLASH", flash0);

+REGION_ALIAS("TEXT_FLASH_LMA", flash0);

+

+/* Flash region to be used for read only data.*/

+REGION_ALIAS("RODATA_FLASH", flash0);

+REGION_ALIAS("RODATA_FLASH_LMA", flash0);

+

+/* Flash region to be used for various.*/

+REGION_ALIAS("VARIOUS_FLASH", flash0);

+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);

+

+/* Flash region to be used for RAM(n) initialization data.*/

+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);

+

+/* RAM region to be used for Main stack. This stack accommodates the processing

+   of all exceptions and interrupts.*/

+REGION_ALIAS("MAIN_STACK_RAM", ram5);

+

+/* RAM region to be used for the process stack. This is the stack used by

+   the main() function.*/

+REGION_ALIAS("PROCESS_STACK_RAM", ram5);

+

+/* RAM region to be used for data segment.*/

+REGION_ALIAS("DATA_RAM", ram0);

+REGION_ALIAS("DATA_RAM_LMA", flash0);

+

+/* RAM region to be used for BSS segment.*/

+REGION_ALIAS("BSS_RAM", ram0);

+

+/* RAM region to be used for the default heap.*/

+REGION_ALIAS("HEAP_RAM", ram0);

+

+/* Stack rules inclusion.*/

+INCLUDE rules_stacks.ld

+

+SECTIONS

+{

+    .convdata : ALIGN(4)

+    {

+        *(.convdata)

+        . = ALIGN(4);

+    } > ramc

+

+    .stacks : ALIGN(4)

+    {

+        *(.stacks)

+        . = ALIGN(4);

+    } > ram5

+

+    .convcode : ALIGN(4)

+    {

+        *(.convcode)

+        . = ALIGN(4);

+    } > flashc

+}

+

+/* Code rules inclusion.*/

+INCLUDE rules_code.ld

+

+/* Data rules inclusion.*/

+INCLUDE rules_data.ld

+

+/* Memory rules inclusion.*/

+INCLUDE rules_memory.ld

+

diff --git a/firmware/source/ld/STM32L476xG.ld b/firmware/source/ld/STM32L476xG.ld
new file mode 100644
index 0000000..b3a332d
--- /dev/null
+++ b/firmware/source/ld/STM32L476xG.ld
@@ -0,0 +1,116 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/*

+ * STM32L476xG memory setup.

+ * A total of 1MB of flash is available.

+ * Firmware uses first 510K, then 2K after is used for unprivileged code.

+ * A total of 128K of RAM is available.

+ * SRAM2 (32K) is used for ELF binary loading.

+ * 32K of SRAM1 is used for system RAM.

+ * 48K is used for ADC and DAC buffers.

+ * 16K is used for unprivileged data (incl. 8K  stack).

+ */

+MEMORY

+{

+    flash0 (rx) : org = 0x08000000, len = 510K   /* Flash bank 1 (reduced from 1M to 510K) */

+    flash1 (rx) : org = 0x00000000, len = 0

+    flash2 (rx) : org = 0x00000000, len = 0

+    flash3 (rx) : org = 0x00000000, len = 0

+    flash4 (rx) : org = 0x00000000, len = 0

+    flash5 (rx) : org = 0x00000000, len = 0

+    flash6 (rx) : org = 0x00000000, len = 0

+    flash7 (rx) : org = 0x00000000, len = 0

+    ram0   (wx) : org = 0x20000000, len = 32K  /* SRAM (actual total = 96K) */

+    ram1   (wx) : org = 0x20008000, len = 48K  /* ADC/DAC buffers (16K * 3) */

+    ram2   (wx) : org = 0x00000000, len = 0

+    ram3   (wx) : org = 0x00000000, len = 0

+    ram4   (wx) : org = 0x10000000, len = 32K  /* User algorithm */

+    ram5   (wx) : org = 0x00000000, len = 0

+    ram6   (wx) : org = 0x00000000, len = 0

+    ram7   (wx) : org = 0x00000000, len = 0

+    flashc (rx) : org = 0x0807F800, len = 2K   /* Unprivileged firmware */

+    ramc   (wx) : org = 0x20014000, len = 16K  /* Unprivileged data */

+}

+

+/* For each data/text section two region are defined, a virtual region

+   and a load region (_LMA suffix).*/

+

+/* Flash region to be used for exception vectors.*/

+REGION_ALIAS("VECTORS_FLASH", flash0);

+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);

+

+/* Flash region to be used for constructors and destructors.*/

+REGION_ALIAS("XTORS_FLASH", flash0);

+REGION_ALIAS("XTORS_FLASH_LMA", flash0);

+

+/* Flash region to be used for code text.*/

+REGION_ALIAS("TEXT_FLASH", flash0);

+REGION_ALIAS("TEXT_FLASH_LMA", flash0);

+

+/* Flash region to be used for read only data.*/

+REGION_ALIAS("RODATA_FLASH", flash0);

+REGION_ALIAS("RODATA_FLASH_LMA", flash0);

+

+/* Flash region to be used for various.*/

+REGION_ALIAS("VARIOUS_FLASH", flash0);

+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);

+

+/* Flash region to be used for RAM(n) initialization data.*/

+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);

+

+/* RAM region to be used for Main stack. This stack accommodates the processing

+   of all exceptions and interrupts.*/

+REGION_ALIAS("MAIN_STACK_RAM", ram0);

+

+/* RAM region to be used for the process stack. This is the stack used by

+   the main() function.*/

+REGION_ALIAS("PROCESS_STACK_RAM", ram0);

+

+/* RAM region to be used for data segment.*/

+REGION_ALIAS("DATA_RAM", ram0);

+REGION_ALIAS("DATA_RAM_LMA", flash0);

+

+/* RAM region to be used for BSS segment.*/

+REGION_ALIAS("BSS_RAM", ram0);

+

+/* RAM region to be used for the default heap.*/

+REGION_ALIAS("HEAP_RAM", ram0);

+

+SECTIONS

+{

+    .convdata : ALIGN(4)

+    {

+        *(.convdata)

+        . = ALIGN(4);

+    } > ramc

+

+    /*.stacks : ALIGN(4)

+    {

+        *(.stacks)

+        . = ALIGN(4);

+    } > ram5*/

+

+    .convcode : ALIGN(4)

+    {

+        *(.convcode)

+        . = ALIGN(4);

+    } > flashc

+}

+

+

+/* Generic rules inclusion.*/

+INCLUDE rules.ld

diff --git a/firmware/source/main.cpp b/firmware/source/main.cpp
new file mode 100644
index 0000000..9a22a73
--- /dev/null
+++ b/firmware/source/main.cpp
@@ -0,0 +1,58 @@
+/**
+ * @file main.cpp
+ * @brief Program entry point.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#include "adc.hpp"
+#include "cordic.hpp"
+#include "dac.hpp"
+#include "error.hpp"
+#include "sclock.hpp"
+#include "usbserial.hpp"
+
+#include "runstatus.hpp"
+RunStatus run_status = RunStatus::Idle;
+
+// Other variables
+//
+//static char userMessageBuffer[128];
+//static unsigned char userMessageSize = 0;
+
+#include "conversion.hpp"
+#include "communication.hpp"
+#include "monitor.hpp"
+
+int main()
+{
+    // Initialize ChibiOS
+    halInit();
+    chSysInit();
+
+    // Init peripherials
+    ADC::begin();
+    DAC::begin();
+    SClock::begin();
+    USBSerial::begin();
+    cordic::init();
+
+    SClock::setRate(SClock::Rate::R32K);
+    ADC::setRate(SClock::Rate::R32K);
+
+    // Start our threads.
+    ConversionManager::begin();
+    CommunicationManager::begin();
+    Monitor::begin();
+
+    chThdExit(0);
+    return 0;
+}
+
diff --git a/firmware/source/monitor.cpp b/firmware/source/monitor.cpp
new file mode 100644
index 0000000..6ef97e9
--- /dev/null
+++ b/firmware/source/monitor.cpp
@@ -0,0 +1,80 @@
+/**
+ * @file monitor.cpp
+ * @brief Manages the device monitoring thread (status LEDs, etc.).
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "monitor.hpp"
+
+#include "error.hpp"
+#include "runstatus.hpp"
+
+#include "hal.h"
+
+__attribute__((section(".stacks")))
+std::array<char, THD_WORKING_AREA_SIZE(256)> Monitor::m_thread_stack = {};
+
+void Monitor::begin()
+{
+    chThdCreateStatic(m_thread_stack.data(),
+                      m_thread_stack.size(),
+                      LOWPRIO,
+                      threadMonitor,
+                      nullptr);
+}
+
+void Monitor::threadMonitor(void *)
+{
+    palSetLineMode(LINE_BUTTON, PAL_MODE_INPUT_PULLUP);
+    auto readButton = [] {
+#ifdef TARGET_PLATFORM_L4
+        return !palReadLine(LINE_BUTTON);
+#else
+        return palReadLine(LINE_BUTTON);
+#endif
+    };
+
+    palSetLine(LINE_LED_RED);
+    palSetLine(LINE_LED_GREEN);
+    palSetLine(LINE_LED_BLUE);
+
+    while (1) {
+        bool isidle = run_status == RunStatus::Idle;
+        auto led = isidle ? LINE_LED_GREEN : LINE_LED_BLUE;
+        auto delay = isidle ? 500 : 250;
+
+        palToggleLine(led);
+        chThdSleepMilliseconds(delay);
+        palToggleLine(led);
+        chThdSleepMilliseconds(delay);
+
+        if (isidle && readButton()) {
+            palClearLine(LINE_LED_GREEN);
+            palClearLine(LINE_LED_BLUE);
+            chSysLock();
+            while (readButton())
+                asm("nop");
+            while (!readButton())
+                asm("nop");
+            chSysUnlock();
+            palSetLine(LINE_LED_GREEN);
+            palSetLine(LINE_LED_BLUE);
+            chThdSleepMilliseconds(500);
+        }
+
+        static bool erroron = false;
+        if (auto err = EM.hasError(); err ^ erroron) {
+            erroron = err;
+            if (err)
+                palClearLine(LINE_LED_RED);
+            else
+                palSetLine(LINE_LED_RED);
+        }
+    }
+}
+
diff --git a/firmware/source/monitor.hpp b/firmware/source/monitor.hpp
new file mode 100644
index 0000000..93f75e3
--- /dev/null
+++ b/firmware/source/monitor.hpp
@@ -0,0 +1,31 @@
+/**
+ * @file monitor.hpp
+ * @brief Manages the device monitoring thread (status LEDs, etc.).
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef STMDSP_MONITOR_HPP
+#define STMDSP_MONITOR_HPP
+
+#include "ch.h"
+
+#include <array>
+
+class Monitor
+{
+public:
+    static void begin();
+
+private:
+    static void threadMonitor(void *);
+
+    static std::array<char, THD_WORKING_AREA_SIZE(256)> m_thread_stack;
+};
+
+#endif // STMDSP_MONITOR_HPP
+
diff --git a/firmware/source/periph/adc.cpp b/firmware/source/periph/adc.cpp
new file mode 100644
index 0000000..4667307
--- /dev/null
+++ b/firmware/source/periph/adc.cpp
@@ -0,0 +1,245 @@
+/**
+ * @file adc.cpp
+ * @brief Manages signal reading through the ADC.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "adc.hpp"
+
+#if defined(TARGET_PLATFORM_L4)
+ADCDriver *ADC::m_driver = &ADCD1;
+ADCDriver *ADC::m_driver2 = &ADCD3;
+#else
+ADCDriver *ADC::m_driver = &ADCD3;
+//ADCDriver *ADC::m_driver2 = &ADCD1; // TODO
+#endif
+
+const ADCConfig ADC::m_config = {
+    .difsel = 0,
+#if defined(TARGET_PLATFORM_H7)
+    .calibration = 0,
+#endif
+};
+
+const ADCConfig ADC::m_config2 = {
+    .difsel = 0,
+#if defined(TARGET_PLATFORM_H7)
+    .calibration = 0,
+#endif
+};
+
+ADCConversionGroup ADC::m_group_config = {
+    .circular = true,
+    .num_channels = 1,
+    .end_cb = ADC::conversionCallback,
+    .error_cb = nullptr,
+    .cfgr = ADC_CFGR_EXTEN_RISING | ADC_CFGR_EXTSEL_SRC(13),  /* TIM6_TRGO */
+    .cfgr2 = 0,//ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSS_0, // Oversampling 2x
+#if defined(TARGET_PLATFORM_H7)
+    .ccr = 0,
+    .pcsel = 0,
+    .ltr1 = 0, .htr1 = 4095,
+    .ltr2 = 0, .htr2 = 4095,
+    .ltr3 = 0, .htr3 = 4095,
+#else
+    .tr1 = ADC_TR(0, 4095),
+    .tr2 = ADC_TR(0, 4095),
+    .tr3 = ADC_TR(0, 4095),
+    .awd2cr = 0,
+    .awd3cr = 0,
+#endif
+    .smpr = {
+        ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_12P5), 0
+    },
+    .sqr = {
+        ADC_SQR1_SQ1_N(ADC_CHANNEL_IN5),
+        0, 0, 0
+    },
+};
+
+static bool readAltDone = false;
+static void readAltCallback(ADCDriver *)
+{
+    readAltDone = true;
+}
+ADCConversionGroup ADC::m_group_config2 = {
+    .circular = false,
+    .num_channels = 2,
+    .end_cb = readAltCallback,
+    .error_cb = nullptr,
+    .cfgr = ADC_CFGR_EXTEN_RISING | ADC_CFGR_EXTSEL_SRC(13),  /* TIM6_TRGO */
+    .cfgr2 = 0,//ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSS_0, // Oversampling 2x
+#if defined(TARGET_PLATFORM_H7)
+    .ccr = 0,
+    .pcsel = 0,
+    .ltr1 = 0, .htr1 = 4095,
+    .ltr2 = 0, .htr2 = 4095,
+    .ltr3 = 0, .htr3 = 4095,
+#else
+    .tr1 = ADC_TR(0, 4095),
+    .tr2 = ADC_TR(0, 4095),
+    .tr3 = ADC_TR(0, 4095),
+    .awd2cr = 0,
+    .awd3cr = 0,
+#endif
+    .smpr = {
+        ADC_SMPR1_SMP_AN1(ADC_SMPR_SMP_2P5) | ADC_SMPR1_SMP_AN2(ADC_SMPR_SMP_2P5), 0
+    },
+    .sqr = {
+        ADC_SQR1_SQ1_N(ADC_CHANNEL_IN1) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN2),
+        0, 0, 0
+    },
+};
+
+adcsample_t *ADC::m_current_buffer = nullptr;
+size_t ADC::m_current_buffer_size = 0;
+ADC::Operation ADC::m_operation = nullptr;
+
+void ADC::begin()
+{
+#if defined(TARGET_PLATFORM_H7)
+    palSetPadMode(GPIOF, 3, PAL_MODE_INPUT_ANALOG);
+#else
+    palSetPadMode(GPIOA, 0, PAL_MODE_INPUT_ANALOG); // Algorithm in
+    palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG); // Potentiometer 1
+    palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_ANALOG); // Potentiometer 2
+#endif
+
+    adcStart(m_driver, &m_config);
+    adcStart(m_driver2, &m_config2);
+}
+
+void ADC::start(adcsample_t *buffer, size_t count, Operation operation)
+{
+    m_current_buffer = buffer;
+    m_current_buffer_size = count;
+    m_operation = operation;
+
+    adcStartConversion(m_driver, &m_group_config, buffer, count);
+    SClock::start();
+}
+
+void ADC::stop()
+{
+    SClock::stop();
+    adcStopConversion(m_driver);
+
+    m_current_buffer = nullptr;
+    m_current_buffer_size = 0;
+    m_operation = nullptr;
+}
+
+adcsample_t ADC::readAlt(unsigned int id)
+{
+    if (id > 1)
+        return 0;
+    static adcsample_t result[16] = {};
+    readAltDone = false;
+    adcStartConversion(m_driver2, &m_group_config2, result, 8);
+    while (!readAltDone);
+        //__WFI();
+    adcStopConversion(m_driver2);
+    return result[id];
+}
+
+void ADC::setRate(SClock::Rate rate)
+{
+#if defined(TARGET_PLATFORM_H7)
+    std::array<std::array<uint32_t, 2>, 6> m_rate_presets = {{
+         // Rate   PLL N  PLL P
+        {/* 8k  */ 80,    20},
+        {/* 16k */ 80,    10},
+        {/* 20k */ 80,    8},
+        {/* 32k */ 80,    5},
+        {/* 48k */ 96,    4},
+        {/* 96k */ 288,   10}
+    }};
+
+    auto& preset = m_rate_presets[static_cast<unsigned int>(rate)];
+    auto pllbits = (preset[0] << RCC_PLL2DIVR_N2_Pos) |
+                   (preset[1] << RCC_PLL2DIVR_P2_Pos);
+
+    adcStop(m_driver);
+
+    // Adjust PLL2
+    RCC->CR &= ~(RCC_CR_PLL2ON);
+    while ((RCC->CR & RCC_CR_PLL2RDY) == RCC_CR_PLL2RDY);
+    auto pll2divr = RCC->PLL2DIVR &
+                    ~(RCC_PLL2DIVR_N2_Msk | RCC_PLL2DIVR_P2_Msk);
+    pll2divr |= pllbits;
+    RCC->PLL2DIVR = pll2divr;
+    RCC->CR |= RCC_CR_PLL2ON;
+    while ((RCC->CR & RCC_CR_PLL2RDY) != RCC_CR_PLL2RDY);
+
+    m_group_config.smpr[0] = rate != SClock::Rate::R96K ? ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_12P5)
+                                                        : ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_2P5);
+
+    adcStart(m_driver, &m_config);
+#elif defined(TARGET_PLATFORM_L4)
+    std::array<std::array<uint32_t, 3>, 6> m_rate_presets = {{
+        // PLLSAI2 sources MSI of 4MHz, divided by PLLM of /1 = 4MHz.
+        // 4MHz is then multiplied by PLLSAI2N (x8 to x86), with result
+        // between 64 and 344 MHz.
+        //
+        // SAI2N MUST BE AT LEAST 16 TO MAKE 64MHz MINIMUM.
+        //
+        // That is then divided by PLLSAI2R:
+        //     R of 0 = /2; 1 = /4, 2 = /6, 3 = /8.
+        // PLLSAI2 then feeds into the ADC, which has a prescaler of /10.
+        // Finally, the ADC's SMP value produces the desired sample rate.
+        //
+        // 4MHz * N / R / 10 / SMP = sample rate.
+        //
+        // With oversampling, must create faster clock
+        // (x2 oversampling requires x2 sample rate clock).
+        //
+        //  Rate   PLLSAI2N  R  SMPR
+        {/* 8k  */ 16,       1, ADC_SMPR_SMP_12P5}, // R3=32k (min), R1=64k
+        {/* 16k */ 16,       0, ADC_SMPR_SMP_12P5},
+        {/* 20k */ 20,       0, ADC_SMPR_SMP_12P5},
+        {/* 32k */ 32,       0, ADC_SMPR_SMP_12P5},
+        {/* 48k */ 48,       0, ADC_SMPR_SMP_12P5},
+        {/* 96k */ 73,       0, ADC_SMPR_SMP_6P5}   // Technically 96.05263kS/s
+    }};
+
+    auto& preset = m_rate_presets[static_cast<int>(rate)];
+    auto pllnr = (preset[0] << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
+                 (preset[1] << RCC_PLLSAI2CFGR_PLLSAI2R_Pos);
+    auto smpr = preset[2];
+
+    // Adjust PLLSAI2
+    RCC->CR &= ~(RCC_CR_PLLSAI2ON);
+    while ((RCC->CR & RCC_CR_PLLSAI2RDY) == RCC_CR_PLLSAI2RDY);
+    RCC->PLLSAI2CFGR = (RCC->PLLSAI2CFGR & ~(RCC_PLLSAI2CFGR_PLLSAI2N_Msk | RCC_PLLSAI2CFGR_PLLSAI2R_Msk)) | pllnr;
+    RCC->CR |= RCC_CR_PLLSAI2ON;
+    while ((RCC->CR & RCC_CR_PLLSAI2RDY) != RCC_CR_PLLSAI2RDY);
+
+    m_group_config.smpr[0] = ADC_SMPR1_SMP_AN5(smpr);
+
+    // 8x oversample
+    m_group_config.cfgr2 = ADC_CFGR2_ROVSE | (2 << ADC_CFGR2_OVSR_Pos) | (3 << ADC_CFGR2_OVSS_Pos);
+    m_group_config2.cfgr2 = ADC_CFGR2_ROVSE | (2 << ADC_CFGR2_OVSR_Pos) | (3 << ADC_CFGR2_OVSS_Pos);
+#endif
+}
+
+void ADC::setOperation(ADC::Operation operation)
+{
+    m_operation = operation;
+}
+
+void ADC::conversionCallback(ADCDriver *driver)
+{
+    if (m_operation != nullptr) {
+        auto half_size = m_current_buffer_size / 2;
+        if (adcIsBufferComplete(driver))
+            m_operation(m_current_buffer + half_size, half_size);
+        else
+            m_operation(m_current_buffer, half_size);
+    }
+}
+
diff --git a/firmware/source/periph/adc.hpp b/firmware/source/periph/adc.hpp
new file mode 100644
index 0000000..5f7fa08
--- /dev/null
+++ b/firmware/source/periph/adc.hpp
@@ -0,0 +1,53 @@
+/**
+ * @file adc.hpp
+ * @brief Manages signal reading through the ADC.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef STMDSP_ADC_HPP_
+#define STMDSP_ADC_HPP_
+
+#include "hal.h"
+#include "sclock.hpp"
+
+#include <array>
+
+class ADC
+{
+public:
+    using Operation = void (*)(adcsample_t *buffer, size_t count);
+
+    static void begin();
+
+    static void start(adcsample_t *buffer, size_t count, Operation operation);
+    static void stop();
+
+    static adcsample_t readAlt(unsigned int id);
+
+    static void setRate(SClock::Rate rate);
+    static void setOperation(Operation operation);
+
+private:
+    static ADCDriver *m_driver;
+    static ADCDriver *m_driver2;
+
+    static const ADCConfig m_config;
+    static const ADCConfig m_config2;
+    static ADCConversionGroup m_group_config;
+    static ADCConversionGroup m_group_config2;
+
+    static adcsample_t *m_current_buffer;
+    static size_t m_current_buffer_size;
+    static Operation m_operation;
+
+public:
+    static void conversionCallback(ADCDriver *);
+};
+
+#endif // STMDSP_ADC_HPP_
+
diff --git a/firmware/source/periph/cordic.cpp b/firmware/source/periph/cordic.cpp
new file mode 100644
index 0000000..29ee068
--- /dev/null
+++ b/firmware/source/periph/cordic.cpp
@@ -0,0 +1,113 @@
+#include "cordic.hpp"
+#include "hal.h"
+
+#if !defined(TARGET_PLATFORM_L4)
+namespace cordic {
+
+void init()
+{
+    RCC->AHB2ENR |= RCC_AHB2ENR_CORDICEN;
+}
+
+static void prepare() {
+    while (CORDIC->CSR & CORDIC_CSR_RRDY)
+        asm("mov r0, %0" :: "r" (CORDIC->RDATA));
+}
+
+static uint32_t dtoq(double) {
+    uint32_t res;
+    asm("vcvt.s32.f64 d0, d0, #31;"
+        "vmov %0, r5, d0"
+    : "=r" (res));
+    return res;
+}
+__attribute__((naked))
+static double qtod(uint32_t) {
+    asm("eor r1, r1;"
+        "vmov d0, r0, r1;"
+        "vcvt.f64.s32 d0, d0, #31;"
+        "bx lr");
+    return 0;
+}
+__attribute__((naked))
+double mod(double, double) {
+    asm("vdiv.f64   d2, d0, d1;"
+        "vrintz.f64 d2;"
+        "vmul.f64   d1, d1, d2;"
+        "vsub.f64   d0, d0, d1;"
+        "bx lr");
+    return 0;
+}
+
+double cos(double x) {
+    x = mod(x, 2 * math::PI) / math::PI;
+    auto input = dtoq(x > 1. ? x - 2 : x);
+
+    prepare();
+    CORDIC->CSR = CORDIC_CSR_NARGS | CORDIC_CSR_NRES |
+                  (6 << CORDIC_CSR_PRECISION_Pos) |
+                  (0 << CORDIC_CSR_FUNC_Pos);
+
+    CORDIC->WDATA = input;
+    CORDIC->WDATA = input;
+    while (!(CORDIC->CSR & CORDIC_CSR_RRDY));
+
+    double cosx = qtod(CORDIC->RDATA) / x;
+    [[maybe_unused]] auto sinx = CORDIC->RDATA;
+    return cosx;
+}
+
+double sin(double x) {
+    x = mod(x, 2 * math::PI) / math::PI;
+    auto input = dtoq(x > 1. ? x - 2 : x);
+
+    prepare();
+    CORDIC->CSR = CORDIC_CSR_NARGS | CORDIC_CSR_NRES |
+                  (6 << CORDIC_CSR_PRECISION_Pos) |
+                  (1 << CORDIC_CSR_FUNC_Pos);
+
+    CORDIC->WDATA = input;
+    CORDIC->WDATA = input;
+    while (!(CORDIC->CSR & CORDIC_CSR_RRDY));
+
+    double sinx = qtod(CORDIC->RDATA) / x;
+    [[maybe_unused]] auto cosx = CORDIC->RDATA;
+    return sinx;
+}
+
+double tan(double x) {
+    x = mod(x, 2 * math::PI) / math::PI;
+    auto input = dtoq(x > 1. ? x - 2 : x);
+
+    prepare();
+    CORDIC->CSR = CORDIC_CSR_NARGS | CORDIC_CSR_NRES |
+                  (6 << CORDIC_CSR_PRECISION_Pos) |
+                  (1 << CORDIC_CSR_FUNC_Pos);
+
+    CORDIC->WDATA = input;
+    CORDIC->WDATA = input;
+    while (!(CORDIC->CSR & CORDIC_CSR_RRDY));
+
+    double sinx = qtod(CORDIC->RDATA) / x;
+    double tanx = sinx * x / qtod(CORDIC->RDATA);
+    return tanx;
+}
+
+}
+#else // L4
+#include <cmath>
+namespace cordic {
+
+void init() {}
+
+float mod(float a, float b) {
+    return a - (b * std::floor(a / b));
+}
+
+float cos(float x) { return std::cos(x); }
+float sin(float x) { return std::sin(x); }
+float tan(float x) { return std::tan(x); }
+
+}
+#endif
+
diff --git a/firmware/source/periph/cordic.hpp b/firmware/source/periph/cordic.hpp
new file mode 100644
index 0000000..5d640cc
--- /dev/null
+++ b/firmware/source/periph/cordic.hpp
@@ -0,0 +1,25 @@
+#ifndef CORDIC_HPP_
+#define CORDIC_HPP_
+
+namespace cordic {
+    constexpr double PI = 3.1415926535L;
+
+    void init();
+
+#if !defined(TARGET_PLATFORM_L4)
+    double mod(double n, double d);
+
+    double cos(double x);
+    double sin(double x);
+    double tan(double x);
+#else
+    float mod(float n, float d);
+
+    float cos(float x);
+    float sin(float x);
+    float tan(float x);
+#endif
+}
+
+#endif // CORDIC_HPP_
+
diff --git a/firmware/source/periph/dac.cpp b/firmware/source/periph/dac.cpp
new file mode 100644
index 0000000..35c2908
--- /dev/null
+++ b/firmware/source/periph/dac.cpp
@@ -0,0 +1,85 @@
+/**
+ * @file dac.cpp
+ * @brief Manages signal creation using the DAC.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "dac.hpp"
+#include "sclock.hpp"
+
+DACDriver *DAC::m_driver[2] = {
+    &DACD1, &DACD2
+};
+
+const DACConfig DAC::m_config = {
+    .init = 2048,
+    .datamode = DAC_DHRM_12BIT_RIGHT,
+    .cr = 0
+};
+
+static int dacIsDone = -1;
+static void dacEndCallback(DACDriver *dacd)
+{
+    if (dacd == &DACD2)
+        dacIsDone = dacIsBufferComplete(dacd) ? 1 : 0;
+}
+
+const DACConversionGroup DAC::m_group_config = {
+    .num_channels = 1,
+    .end_cb = dacEndCallback,
+    .error_cb = nullptr,
+#if defined(TARGET_PLATFORM_H7)
+    .trigger = 5 // TIM6_TRGO
+#elif defined(TARGET_PLATFORM_L4)
+    .trigger = 0 // TIM6_TRGO
+#endif
+};
+
+void DAC::begin()
+{
+    palSetPadMode(GPIOA, 4, PAL_STM32_MODE_ANALOG);
+    palSetPadMode(GPIOA, 5, PAL_STM32_MODE_ANALOG);
+
+    dacStart(m_driver[0], &m_config);
+    dacStart(m_driver[1], &m_config);
+}
+
+void DAC::start(int channel, dacsample_t *buffer, size_t count)
+{
+    if (channel >= 0 && channel < 2) {
+        if (channel == 1)
+            dacIsDone = -1;
+        dacStartConversion(m_driver[channel], &m_group_config, buffer, count);
+        SClock::start();
+    }
+}
+
+int DAC::sigGenWantsMore()
+{
+    if (dacIsDone != -1) {
+        int tmp = dacIsDone;
+        dacIsDone = -1;
+        return tmp;
+    } else {
+        return -1;
+    }
+}
+
+int DAC::isSigGenRunning()
+{
+    return m_driver[1]->state == DAC_ACTIVE;
+}
+
+void DAC::stop(int channel)
+{
+    if (channel >= 0 && channel < 2) {
+        dacStopConversion(m_driver[channel]);
+        SClock::stop();
+    }
+}
+
diff --git a/firmware/source/periph/dac.hpp b/firmware/source/periph/dac.hpp
new file mode 100644
index 0000000..7250a52
--- /dev/null
+++ b/firmware/source/periph/dac.hpp
@@ -0,0 +1,37 @@
+/**
+ * @file dac.hpp
+ * @brief Manages signal creation using the DAC.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef STMDSP_DAC_HPP_
+#define STMDSP_DAC_HPP_
+
+#include "hal.h"
+#undef DAC
+
+class DAC
+{
+public:
+    static void begin();
+
+    static void start(int channel, dacsample_t *buffer, size_t count);
+    static void stop(int channel);
+
+    static int sigGenWantsMore();
+    static int isSigGenRunning();
+
+private:
+    static DACDriver *m_driver[2];
+
+    static const DACConfig m_config;
+    static const DACConversionGroup m_group_config;
+};
+
+#endif // STMDSP_DAC_HPP_
+
diff --git a/firmware/source/periph/usbcfg.c b/firmware/source/periph/usbcfg.c
new file mode 100644
index 0000000..b726e23
--- /dev/null
+++ b/firmware/source/periph/usbcfg.c
@@ -0,0 +1,346 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+#include "hal.h"

+

+/* Virtual serial port over USB.*/

+SerialUSBDriver SDU1;

+

+/*

+ * Endpoints to be used for USBD1.

+ */

+#define USBD1_DATA_REQUEST_EP           1

+#define USBD1_DATA_AVAILABLE_EP         1

+#define USBD1_INTERRUPT_REQUEST_EP      2

+

+/*

+ * USB Device Descriptor.

+ */

+static const uint8_t vcom_device_descriptor_data[18] = {

+  USB_DESC_DEVICE       (0x0110,        /* bcdUSB (1.1).                    */

+                         0x02,          /* bDeviceClass (CDC).              */

+                         0x00,          /* bDeviceSubClass.                 */

+                         0x00,          /* bDeviceProtocol.                 */

+                         0x40,          /* bMaxPacketSize.                  */

+                         0x0483,        /* idVendor (ST).                   */

+                         0x5740,        /* idProduct.                       */

+                         0x0200,        /* bcdDevice.                       */

+                         1,             /* iManufacturer.                   */

+                         2,             /* iProduct.                        */

+                         3,             /* iSerialNumber.                   */

+                         1)             /* bNumConfigurations.              */

+};

+

+/*

+ * Device Descriptor wrapper.

+ */

+static const USBDescriptor vcom_device_descriptor = {

+  sizeof vcom_device_descriptor_data,

+  vcom_device_descriptor_data

+};

+

+/* Configuration Descriptor tree for a CDC.*/

+static const uint8_t vcom_configuration_descriptor_data[67] = {

+  /* Configuration Descriptor.*/

+  USB_DESC_CONFIGURATION(67,            /* wTotalLength.                    */

+                         0x02,          /* bNumInterfaces.                  */

+                         0x01,          /* bConfigurationValue.             */

+                         0,             /* iConfiguration.                  */

+                         0xC0,          /* bmAttributes (self powered).     */

+                         50),           /* bMaxPower (100mA).               */

+  /* Interface Descriptor.*/

+  USB_DESC_INTERFACE    (0x00,          /* bInterfaceNumber.                */

+                         0x00,          /* bAlternateSetting.               */

+                         0x01,          /* bNumEndpoints.                   */

+                         0x02,          /* bInterfaceClass (Communications

+                                           Interface Class, CDC section

+                                           4.2).                            */

+                         0x02,          /* bInterfaceSubClass (Abstract

+                                         Control Model, CDC section 4.3).   */

+                         0x01,          /* bInterfaceProtocol (AT commands,

+                                           CDC section 4.4).                */

+                         0),            /* iInterface.                      */

+  /* Header Functional Descriptor (CDC section 5.2.3).*/

+  USB_DESC_BYTE         (5),            /* bLength.                         */

+  USB_DESC_BYTE         (0x24),         /* bDescriptorType (CS_INTERFACE).  */

+  USB_DESC_BYTE         (0x00),         /* bDescriptorSubtype (Header

+                                           Functional Descriptor.           */

+  USB_DESC_BCD          (0x0110),       /* bcdCDC.                          */

+  /* Call Management Functional Descriptor. */

+  USB_DESC_BYTE         (5),            /* bFunctionLength.                 */

+  USB_DESC_BYTE         (0x24),         /* bDescriptorType (CS_INTERFACE).  */

+  USB_DESC_BYTE         (0x01),         /* bDescriptorSubtype (Call Management

+                                           Functional Descriptor).          */

+  USB_DESC_BYTE         (0x00),         /* bmCapabilities (D0+D1).          */

+  USB_DESC_BYTE         (0x01),         /* bDataInterface.                  */

+  /* ACM Functional Descriptor.*/

+  USB_DESC_BYTE         (4),            /* bFunctionLength.                 */

+  USB_DESC_BYTE         (0x24),         /* bDescriptorType (CS_INTERFACE).  */

+  USB_DESC_BYTE         (0x02),         /* bDescriptorSubtype (Abstract

+                                           Control Management Descriptor).  */

+  USB_DESC_BYTE         (0x02),         /* bmCapabilities.                  */

+  /* Union Functional Descriptor.*/

+  USB_DESC_BYTE         (5),            /* bFunctionLength.                 */

+  USB_DESC_BYTE         (0x24),         /* bDescriptorType (CS_INTERFACE).  */

+  USB_DESC_BYTE         (0x06),         /* bDescriptorSubtype (Union

+                                           Functional Descriptor).          */

+  USB_DESC_BYTE         (0x00),         /* bMasterInterface (Communication

+                                           Class Interface).                */

+  USB_DESC_BYTE         (0x01),         /* bSlaveInterface0 (Data Class

+                                           Interface).                      */

+  /* Endpoint 2 Descriptor.*/

+  USB_DESC_ENDPOINT     (USBD1_INTERRUPT_REQUEST_EP|0x80,

+                         0x03,          /* bmAttributes (Interrupt).        */

+                         0x0008,        /* wMaxPacketSize.                  */

+                         0xFF),         /* bInterval.                       */

+  /* Interface Descriptor.*/

+  USB_DESC_INTERFACE    (0x01,          /* bInterfaceNumber.                */

+                         0x00,          /* bAlternateSetting.               */

+                         0x02,          /* bNumEndpoints.                   */

+                         0x0A,          /* bInterfaceClass (Data Class

+                                           Interface, CDC section 4.5).     */

+                         0x00,          /* bInterfaceSubClass (CDC section

+                                           4.6).                            */

+                         0x00,          /* bInterfaceProtocol (CDC section

+                                           4.7).                            */

+                         0x00),         /* iInterface.                      */

+  /* Endpoint 3 Descriptor.*/

+  USB_DESC_ENDPOINT     (USBD1_DATA_AVAILABLE_EP,       /* bEndpointAddress.*/

+                         0x02,          /* bmAttributes (Bulk).             */

+                         0x0040,        /* wMaxPacketSize.                  */

+                         0x00),         /* bInterval.                       */

+  /* Endpoint 1 Descriptor.*/

+  USB_DESC_ENDPOINT     (USBD1_DATA_REQUEST_EP|0x80,    /* bEndpointAddress.*/

+                         0x02,          /* bmAttributes (Bulk).             */

+                         0x0040,        /* wMaxPacketSize.                  */

+                         0x00)          /* bInterval.                       */

+};

+

+/*

+ * Configuration Descriptor wrapper.

+ */

+static const USBDescriptor vcom_configuration_descriptor = {

+  sizeof vcom_configuration_descriptor_data,

+  vcom_configuration_descriptor_data

+};

+

+/*

+ * U.S. English language identifier.

+ */

+static const uint8_t vcom_string0[] = {

+  USB_DESC_BYTE(4),                     /* bLength.                         */

+  USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType.                 */

+  USB_DESC_WORD(0x0409)                 /* wLANGID (U.S. English).          */

+};

+

+/*

+ * Vendor string.

+ */

+static const uint8_t vcom_string1[] = {

+  USB_DESC_BYTE(38),                    /* bLength.                         */

+  USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType.                 */

+  'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,

+  'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,

+  'c', 0, 's', 0

+};

+

+/*

+ * Device Description string.

+ */

+static const uint8_t vcom_string2[] = {

+  USB_DESC_BYTE(56),                    /* bLength.                         */

+  USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType.                 */

+  'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0,

+  'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0,

+  'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0,

+  'o', 0, 'r', 0, 't', 0

+};

+

+/*

+ * Serial Number string.

+ */

+static const uint8_t vcom_string3[] = {

+  USB_DESC_BYTE(8),                     /* bLength.                         */

+  USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType.                 */

+  '0' + CH_KERNEL_MAJOR, 0,

+  '0' + CH_KERNEL_MINOR, 0,

+  '0' + CH_KERNEL_PATCH, 0

+};

+

+/*

+ * Strings wrappers array.

+ */

+static const USBDescriptor vcom_strings[] = {

+  {sizeof vcom_string0, vcom_string0},

+  {sizeof vcom_string1, vcom_string1},

+  {sizeof vcom_string2, vcom_string2},

+  {sizeof vcom_string3, vcom_string3}

+};

+

+/*

+ * Handles the GET_DESCRIPTOR callback. All required descriptors must be

+ * handled here.

+ */

+static const USBDescriptor *get_descriptor(USBDriver *usbp,

+                                           uint8_t dtype,

+                                           uint8_t dindex,

+                                           uint16_t lang) {

+

+  (void)usbp;

+  (void)lang;

+  switch (dtype) {

+  case USB_DESCRIPTOR_DEVICE:

+    return &vcom_device_descriptor;

+  case USB_DESCRIPTOR_CONFIGURATION:

+    return &vcom_configuration_descriptor;

+  case USB_DESCRIPTOR_STRING:

+    if (dindex < 4)

+      return &vcom_strings[dindex];

+  }

+  return NULL;

+}

+

+/**

+ * @brief   IN EP1 state.

+ */

+static USBInEndpointState ep1instate;

+

+/**

+ * @brief   OUT EP1 state.

+ */

+static USBOutEndpointState ep1outstate;

+

+/**

+ * @brief   EP1 initialization structure (both IN and OUT).

+ */

+static const USBEndpointConfig ep1config = {

+  USB_EP_MODE_TYPE_BULK,

+  NULL,

+  sduDataTransmitted,

+  sduDataReceived,

+  0x0040,

+  0x0040,

+  &ep1instate,

+  &ep1outstate,

+  1,

+  NULL

+};

+

+/**

+ * @brief   IN EP2 state.

+ */

+static USBInEndpointState ep2instate;

+

+/**

+ * @brief   EP2 initialization structure (IN only).

+ */

+static const USBEndpointConfig ep2config = {

+  USB_EP_MODE_TYPE_INTR,

+  NULL,

+  sduInterruptTransmitted,

+  NULL,

+  0x0010,

+  0x0000,

+  &ep2instate,

+  NULL,

+  1,

+  NULL

+};

+

+/*

+ * Handles the USB driver global events.

+ */

+static void usb_event(USBDriver *usbp, usbevent_t event) {

+  extern SerialUSBDriver SDU1;

+

+  switch (event) {

+  case USB_EVENT_ADDRESS:

+    return;

+  case USB_EVENT_CONFIGURED:

+    chSysLockFromISR();

+

+    /* Enables the endpoints specified into the configuration.

+       Note, this callback is invoked from an ISR so I-Class functions

+       must be used.*/

+    usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config);

+    usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config);

+

+    /* Resetting the state of the CDC subsystem.*/

+    sduConfigureHookI(&SDU1);

+

+    chSysUnlockFromISR();

+    return;

+  case USB_EVENT_RESET:

+    /* Falls into.*/

+  case USB_EVENT_UNCONFIGURED:

+    /* Falls into.*/

+  case USB_EVENT_SUSPEND:

+    chSysLockFromISR();

+

+    /* Disconnection event on suspend.*/

+    sduSuspendHookI(&SDU1);

+

+    chSysUnlockFromISR();

+    return;

+  case USB_EVENT_WAKEUP:

+    chSysLockFromISR();

+

+    /* Connection event on wakeup.*/

+    sduWakeupHookI(&SDU1);

+

+    chSysUnlockFromISR();

+    return;

+  case USB_EVENT_STALLED:

+    return;

+  }

+  return;

+}

+

+/*

+ * Handles the USB driver global events.

+ */

+static void sof_handler(USBDriver *usbp) {

+

+  (void)usbp;

+

+  osalSysLockFromISR();

+  sduSOFHookI(&SDU1);

+  osalSysUnlockFromISR();

+}

+

+/*

+ * USB driver configuration.

+ */

+const USBConfig usbcfg = {

+  usb_event,

+  get_descriptor,

+  sduRequestsHook,

+  sof_handler

+};

+

+/*

+ * Serial over USB driver configuration.

+ */

+const SerialUSBConfig serusbcfg = {

+#if defined(TARGET_PLATFORM_H7)

+  &USBD2,

+#else

+  &USBD1,

+#endif

+  USBD1_DATA_REQUEST_EP,

+  USBD1_DATA_AVAILABLE_EP,

+  USBD1_INTERRUPT_REQUEST_EP

+};

diff --git a/firmware/source/periph/usbcfg.h b/firmware/source/periph/usbcfg.h
new file mode 100644
index 0000000..2fceccb
--- /dev/null
+++ b/firmware/source/periph/usbcfg.h
@@ -0,0 +1,28 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+#ifndef USBCFG_H

+#define USBCFG_H

+

+#include "hal.h"

+

+extern const USBConfig usbcfg;

+extern SerialUSBConfig serusbcfg;

+extern SerialUSBDriver SDU1;

+

+#endif  /* USBCFG_H */

+

+/** @} */

diff --git a/firmware/source/periph/usbserial.cpp b/firmware/source/periph/usbserial.cpp
new file mode 100644
index 0000000..775a911
--- /dev/null
+++ b/firmware/source/periph/usbserial.cpp
@@ -0,0 +1,52 @@
+/**
+ * @file usbserial.cpp
+ * @brief Wrapper for ChibiOS's SerialUSBDriver.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "usbserial.hpp"
+
+SerialUSBDriver *USBSerial::m_driver = &SDU1;
+
+void USBSerial::begin()
+{
+    palSetPadMode(GPIOA, 11, PAL_MODE_ALTERNATE(10));
+    palSetPadMode(GPIOA, 12, PAL_MODE_ALTERNATE(10));
+
+    sduObjectInit(m_driver);
+    sduStart(m_driver, &serusbcfg);
+
+    // Reconnect bus so device can re-enumerate on reset
+    usbDisconnectBus(serusbcfg.usbp);
+    chThdSleepMilliseconds(1500);
+    usbStart(serusbcfg.usbp, &usbcfg);
+    usbConnectBus(serusbcfg.usbp);
+}
+
+bool USBSerial::isActive()
+{
+    if (auto config = m_driver->config; config != nullptr) {
+        if (auto usbp = config->usbp; usbp != nullptr)
+            return usbp->state == USB_ACTIVE && !ibqIsEmptyI(&m_driver->ibqueue);
+    }
+
+    return false;
+}
+
+size_t USBSerial::read(unsigned char *buffer, size_t count)
+{
+    auto bss = reinterpret_cast<BaseSequentialStream *>(m_driver);
+    return streamRead(bss, buffer, count);
+}
+
+size_t USBSerial::write(const unsigned char *buffer, size_t count)
+{
+    auto bss = reinterpret_cast<BaseSequentialStream *>(m_driver);
+    return streamWrite(bss, buffer, count);
+}
+
diff --git a/firmware/source/periph/usbserial.hpp b/firmware/source/periph/usbserial.hpp
new file mode 100644
index 0000000..58113c9
--- /dev/null
+++ b/firmware/source/periph/usbserial.hpp
@@ -0,0 +1,32 @@
+/**
+ * @file usbserial.hpp
+ * @brief Wrapper for ChibiOS's SerialUSBDriver.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef STMDSP_USBSERIAL_HPP_
+#define STMDSP_USBSERIAL_HPP_
+
+#include "usbcfg.h"
+
+class USBSerial
+{
+public:
+    static void begin();
+
+    static bool isActive();
+
+    static size_t read(unsigned char *buffer, size_t count);
+    static size_t write(const unsigned char *buffer, size_t count);
+
+private:
+    static SerialUSBDriver *m_driver;
+};
+
+#endif // STMDSP_USBSERIAL_HPP_
+
diff --git a/firmware/source/runstatus.hpp b/firmware/source/runstatus.hpp
new file mode 100644
index 0000000..ab269b4
--- /dev/null
+++ b/firmware/source/runstatus.hpp
@@ -0,0 +1,11 @@
+// Run status
+//
+enum class RunStatus : char
+{
+    Idle = '1',
+    Running,
+    Recovering
+};
+
+extern RunStatus run_status;
+
diff --git a/firmware/source/samplebuffer.cpp b/firmware/source/samplebuffer.cpp
new file mode 100644
index 0000000..74c6778
--- /dev/null
+++ b/firmware/source/samplebuffer.cpp
@@ -0,0 +1,117 @@
+/**
+ * @file samplebuffer.cpp
+ * @brief Manages ADC/DAC buffer data.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "samplebuffer.hpp"
+
+SampleBuffer::SampleBuffer(Sample *buffer) :
+    m_buffer(buffer) {}
+
+void SampleBuffer::clear() {
+    std::fill(m_buffer, m_buffer + m_size, 2048);
+}
+__attribute__((section(".convcode")))
+void SampleBuffer::modify(Sample *data, unsigned int srcsize) {
+    auto size = srcsize < m_size ? srcsize : m_size;
+    size = (size + 15) & (~15);
+
+    m_modified = m_buffer;
+    const int *src = reinterpret_cast<const int *>(data);
+    const int * const srcend = src + (size / 2);
+    int *dst = reinterpret_cast<int *>(m_buffer);
+    do {
+        int a = src[0];
+        int b = src[1];
+        int c = src[2];
+        int d = src[3];
+        int e = src[4];
+        int f = src[5];
+        int g = src[6];
+        int h = src[7];
+        dst[0] = a;
+        dst[1] = b;
+        dst[2] = c;
+        dst[3] = d;
+        dst[4] = e;
+        dst[5] = f;
+        dst[6] = g;
+        dst[7] = h;
+        src += 8;
+        dst += 8;
+    } while (src < srcend);
+}
+__attribute__((section(".convcode")))
+void SampleBuffer::midmodify(Sample *data, unsigned int srcsize) {
+    auto size = srcsize < m_size / 2 ? srcsize : m_size / 2;
+    size = (size + 15) & (~15);
+
+    m_modified = middata();
+    const int *src = reinterpret_cast<const int *>(data);
+    const int * const srcend = src + (size / 2);
+    int *dst = reinterpret_cast<int *>(middata());
+    do {
+        int a = src[0];
+        int b = src[1];
+        int c = src[2];
+        int d = src[3];
+        int e = src[4];
+        int f = src[5];
+        int g = src[6];
+        int h = src[7];
+        dst[0] = a;
+        dst[1] = b;
+        dst[2] = c;
+        dst[3] = d;
+        dst[4] = e;
+        dst[5] = f;
+        dst[6] = g;
+        dst[7] = h;
+        src += 8;
+        dst += 8;
+    } while (src < srcend);
+}
+
+void SampleBuffer::setModified() {
+    m_modified = m_buffer;
+}
+
+void SampleBuffer::setMidmodified() {
+    m_modified = middata();
+}
+
+void SampleBuffer::setSize(unsigned int size) {
+    m_size = size < MAX_SAMPLE_BUFFER_SIZE ? size : MAX_SAMPLE_BUFFER_SIZE;
+}
+
+__attribute__((section(".convcode")))
+Sample *SampleBuffer::data() {
+    return m_buffer;
+}
+__attribute__((section(".convcode")))
+Sample *SampleBuffer::middata() {
+    return m_buffer + m_size / 2;
+}
+uint8_t *SampleBuffer::bytedata() {
+    return reinterpret_cast<uint8_t *>(m_buffer);
+}
+
+Sample *SampleBuffer::modified() {
+    auto m = m_modified;
+    m_modified = nullptr;
+    return m;
+}
+__attribute__((section(".convcode")))
+unsigned int SampleBuffer::size() const {
+    return m_size;
+}
+unsigned int SampleBuffer::bytesize() const {
+    return m_size * sizeof(Sample);
+}
+
diff --git a/firmware/source/samplebuffer.hpp b/firmware/source/samplebuffer.hpp
new file mode 100644
index 0000000..d13023a
--- /dev/null
+++ b/firmware/source/samplebuffer.hpp
@@ -0,0 +1,51 @@
+/**
+ * @file samplebuffer.hpp
+ * @brief Manages ADC/DAC buffer data.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef SAMPLEBUFFER_HPP_
+#define SAMPLEBUFFER_HPP_
+
+#include <array>
+#include <cstdint>
+
+using Sample = uint16_t;
+
+constexpr unsigned int MAX_SAMPLE_BUFFER_BYTESIZE = sizeof(Sample) * 8192;
+constexpr unsigned int MAX_SAMPLE_BUFFER_SIZE = MAX_SAMPLE_BUFFER_BYTESIZE / sizeof(Sample);
+
+class SampleBuffer
+{
+public:
+    SampleBuffer(Sample *buffer);
+
+    void clear();
+
+    void modify(Sample *data, unsigned int srcsize);
+    void midmodify(Sample *data, unsigned int srcsize);
+    void setModified();
+    void setMidmodified();
+    Sample *modified();
+
+    Sample *data();
+    Sample *middata();
+    uint8_t *bytedata();
+
+    void setSize(unsigned int size);
+    unsigned int size() const;
+    unsigned int bytesize() const;
+
+private:
+    Sample *m_buffer = nullptr;
+    unsigned int m_size = MAX_SAMPLE_BUFFER_SIZE;
+    Sample *m_modified = nullptr;
+};
+
+#endif // SAMPLEBUFFER_HPP_
+
diff --git a/firmware/source/samples.cpp b/firmware/source/samples.cpp
new file mode 100644
index 0000000..cfbf835
--- /dev/null
+++ b/firmware/source/samples.cpp
@@ -0,0 +1,35 @@
+/**
+ * @file samples.cpp
+ * @brief Provides sample buffers for inputs and outputs.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "samples.hpp"
+
+#include "ch.h"
+#include "hal.h"
+
+#include <cstdint>
+
+static_assert(sizeof(adcsample_t) == sizeof(uint16_t));
+static_assert(sizeof(dacsample_t) == sizeof(uint16_t));
+
+#if defined(TARGET_PLATFORM_H7)
+__attribute__((section(".convdata")))
+SampleBuffer Samples::In (reinterpret_cast<Sample *>(0x38000000)); // 16k
+__attribute__((section(".convdata")))
+SampleBuffer Samples::Out (reinterpret_cast<Sample *>(0x30004000)); // 16k
+SampleBuffer Samples::SigGen (reinterpret_cast<Sample *>(0x30000000)); // 16k
+#else
+__attribute__((section(".convdata")))
+SampleBuffer Samples::In (reinterpret_cast<Sample *>(0x20008000)); // 16k
+__attribute__((section(".convdata")))
+SampleBuffer Samples::Out (reinterpret_cast<Sample *>(0x2000C000)); // 16k
+SampleBuffer Samples::Generator (reinterpret_cast<Sample *>(0x20010000)); // 16k
+#endif
+
diff --git a/firmware/source/samples.hpp b/firmware/source/samples.hpp
new file mode 100644
index 0000000..6551e25
--- /dev/null
+++ b/firmware/source/samples.hpp
@@ -0,0 +1,26 @@
+/**
+ * @file samples.hpp
+ * @brief Provides sample buffers for inputs and outputs.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef STMDSP_SAMPLES_HPP
+#define STMDSP_SAMPLES_HPP
+
+#include "samplebuffer.hpp"
+
+class Samples
+{
+public:
+    static SampleBuffer In;
+    static SampleBuffer Out;
+    static SampleBuffer Generator;
+};
+
+#endif // STMDSP_SAMPLES_HPP
+
diff --git a/firmware/source/sclock.cpp b/firmware/source/sclock.cpp
new file mode 100644
index 0000000..6660f95
--- /dev/null
+++ b/firmware/source/sclock.cpp
@@ -0,0 +1,78 @@
+/**
+ * @file sclock.cpp
+ * @brief Manages sampling rate clock speeds.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "sclock.hpp"
+
+GPTDriver *SClock::m_timer = &GPTD6;
+unsigned int SClock::m_div = 1;
+unsigned int SClock::m_runcount = 0;
+
+const GPTConfig SClock::m_timer_config = {
+#if defined(TARGET_PLATFORM_H7)
+    .frequency = 4800000,
+#else
+    .frequency = 36000000,
+#endif
+    .callback = nullptr,
+    .cr2 = TIM_CR2_MMS_1, /* TRGO */
+    .dier = 0
+};
+
+const std::array<unsigned int, 6> SClock::m_rate_divs = {{
+#if defined(TARGET_PLATFORM_H7)
+    /* 8k  */ 600,
+    /* 16k */ 300,
+    /* 20k */ 240,
+    /* 32k */ 150,
+    /* 48k */ 100,
+    /* 96k */ 50
+#else
+    /* 8k  */ 4500,
+    /* 16k */ 2250,
+    /* 20k */ 1800,
+    /* 32k */ 1125,
+    /* 48k */ 750,
+    /* 96k */ 375
+#endif
+}};
+
+void SClock::begin()
+{
+    gptStart(m_timer, &m_timer_config);
+}
+
+void SClock::start()
+{
+    if (m_runcount++ == 0)
+        gptStartContinuous(m_timer, m_div);
+}
+
+void SClock::stop()
+{
+    if (--m_runcount == 0)
+        gptStopTimer(m_timer);
+}
+
+void SClock::setRate(SClock::Rate rate)
+{
+    m_div = m_rate_divs[static_cast<unsigned int>(rate)];
+}
+
+unsigned int SClock::getRate()
+{
+    for (unsigned int i = 0; i < m_rate_divs.size(); ++i) {
+        if (m_rate_divs[i] == m_div)
+            return i;
+    }
+
+    return static_cast<unsigned int>(-1);
+}
+
diff --git a/firmware/source/sclock.hpp b/firmware/source/sclock.hpp
new file mode 100644
index 0000000..d5b93df
--- /dev/null
+++ b/firmware/source/sclock.hpp
@@ -0,0 +1,47 @@
+/**
+ * @file sclock.hpp
+ * @brief Manages sampling rate clock speeds.
+ *
+ * Copyright (C) 2021 Clyne Sullivan
+ *
+ * Distributed under the GNU GPL v3 or later. You should have received a copy of
+ * the GNU General Public License along with this program.
+ * If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef SCLOCK_HPP_
+#define SCLOCK_HPP_
+
+#include "hal.h"
+
+#include <array>
+
+class SClock
+{
+public:
+    enum class Rate : unsigned int {
+        R8K = 0,
+        R16K,
+        R20K,
+        R32K,
+        R48K,
+        R96K
+    };
+
+    static void begin();
+    static void start();
+    static void stop();
+
+    static void setRate(Rate rate);
+    static unsigned int getRate();
+
+private:
+    static GPTDriver *m_timer;
+    static unsigned int m_div;
+    static unsigned int m_runcount;
+    static const GPTConfig m_timer_config;
+    static const std::array<unsigned int, 6> m_rate_divs;
+};
+
+#endif // SCLOCK_HPP_
+