8 Commits (1bc2fe8a97954b6f9c3542cc6927567bbb9d8e4e)

Author SHA1 Message Date
Clyne 31468a0f32
finish rev2 layout 1 year ago
Clyne 1285947d1c
finalize rev2 schematic 1 year ago
Clyne d9f17a9029
use nucleo 3.3v vdda; add 2nd low-pass stage to input 1 year ago
Clyne 836b420aec
wip: schematic fixes based on testing 1 year ago
Clyne 834d719434
design finalized; publish pdfs 1 year ago
Clyne 12caf4acd4
pcb design finalization 1 year ago
Clyne 5d91869649
finalize pcb design; add layout file 1 year ago
Clyne f440728644
initial commit
* combine all source files into this monorepo

* convert all third-party source packages into submodules

* small fixes due to changes in latest third-part packages
1 year ago