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64 lines
1.7 KiB
C
64 lines
1.7 KiB
C
7 years ago
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#include "stm32l476xx.h"
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#define STK_CTRL *((uint32_t *)0xE000E010)
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#define STK_LOAD *((uint32_t *)0xE000E014)
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#define STK_VAL *((uint32_t *)0xE000E018)
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#define STK_CALIB *((uint32_t *)0xE000E01C)
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extern void delay(uint32_t count);
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/**
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* Accomplishments:
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* - GPIO in/out
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* - got to 40MHz clock
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*/
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int main(void)
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{
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// turn on HSI
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RCC->CR |= RCC_CR_HSION;
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while ((RCC->CR & RCC_CR_HSIRDY) != RCC_CR_HSIRDY);
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// get PLLR to 80MHz (max)
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// VCO = C * (N/M) -> 16 * (10/1) = 160
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// SCLK = VCO / R = 160 / 4 = 40 MHz
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RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC); // source HSI, 16MHz
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSI;
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RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLM);
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RCC->PLLCFGR |= 10 << RCC_PLLCFGR_PLLN_Pos;
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RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLR); // /4
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RCC->PLLCFGR |= 1 << RCC_PLLCFGR_PLLR_Pos;
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN; // PLLR on
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// start PLL
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RCC->CR |= RCC_CR_PLLON;
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while ((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY);
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// set system clock to PLL
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RCC->CFGR &= ~(RCC_CFGR_SW);
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);
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// SysTick setup? Assume 4MHz reset clock
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STK_LOAD = 40000;
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STK_CTRL |= 0x07; // AHB, inten, enable
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RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN; // A clk enable
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GPIOA->MODER &= ~(GPIO_MODER_MODE5 | GPIO_MODER_MODE0); // A5 -> output, A0 input
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GPIOA->MODER |= GPIO_MODER_MODE5_0;
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GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPD5 | GPIO_PUPDR_PUPD0);
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GPIOA->PUPDR |= GPIO_PUPDR_PUPD5_0 | GPIO_PUPDR_PUPD0_1; // pd for button
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while (1) {
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delay(500);
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//if (GPIOA->IDR & 0x01)
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GPIOA->BSRR |= 1 << 5;
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delay(500);
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//else
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GPIOA->BRR |= 1 << 5;
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}
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}
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void _exit(int code)
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{ for (;;); }
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