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60 lines
1.4 KiB
C
60 lines
1.4 KiB
C
#include <clock.h>
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#include <stm32l476xx.h>
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#define STK_CTRL *((uint32_t *)0xE000E010)
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#define STK_LOAD *((uint32_t *)0xE000E014)
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#define STK_VAL *((uint32_t *)0xE000E018)
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#define STK_CALIB *((uint32_t *)0xE000E01C)
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// ticks since init
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static uint32_t ticks = 0;
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void clock_init(void)
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{
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// turn on HSI (16MHz)
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RCC->CR |= RCC_CR_HSION;
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while ((RCC->CR & RCC_CR_HSIRDY) != RCC_CR_HSIRDY);
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// get PLLR to 80MHz (max)
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// VCO = C * (N/M) -> 16 * (10/1) = 160
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// SCLK = VCO / R = 160 / 2 = 80 MHz
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RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC);
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSI;
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RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLM);
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RCC->PLLCFGR |= 10 << RCC_PLLCFGR_PLLN_Pos;
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RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLR); // /2
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN; // PLLR on
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// start PLL
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RCC->CR |= RCC_CR_PLLON;
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while ((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY);
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// set system clock to PLL
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RCC->CFGR &= ~(RCC_CFGR_SW);
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);
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// SysTick init. 80MHz / 80000 = 1kHz, ms precision
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STK_LOAD = 80000;
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STK_CTRL |= 0x07; // no div, interrupt, enable
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}
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void delay(uint32_t count)
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{
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uint32_t target = ticks + count;
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while (ticks < target);
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}
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void PendSV_Handler(void) {
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}
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void SysTick_Handler(void)
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{
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// just keep counting
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ticks++;
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if (!(ticks % 500))
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SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
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}
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