diff options
| author | Clyne Sullivan <clyne@bitgloo.com> | 2025-01-27 14:21:30 -0500 |
|---|---|---|
| committer | Clyne Sullivan <clyne@bitgloo.com> | 2025-01-27 14:21:30 -0500 |
| commit | 9592fbf2684b1f3f1892bf02404e41f209b0c5ac (patch) | |
| tree | bb398714808f65c0ba63e428e09cf54b4864dac3 | |
| parent | be2b73fa7b0da33d96200c4f51b8c3f5f76130c3 (diff) | |
reorganize arch's
| -rw-r--r-- | Makefile | 23 | ||||
| -rw-r--r-- | msp430/main.c | 3 | ||||
| -rw-r--r-- | msp430/msp430g2553.h | 955 | ||||
| -rw-r--r-- | msp430/msp430g2553.ld | 315 | ||||
| -rw-r--r-- | msp430/msp430g2553_symbols.ld | 187 | ||||
| -rw-r--r-- | x86/main.c (renamed from main.c) | 0 |
6 files changed, 1473 insertions, 10 deletions
@@ -1,10 +1,17 @@ -CC := gcc -DFOCI_X86_64 -#CC := arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -DFOCI_ARM -#CC := msp430-elf-gcc -DFOCI_MSP430 -mmcu=msp430g2553 -CFLAGS := -O3 -ggdb -g3 -Wall -Wextra +CFLAGS := -O3 -ggdb -g3 -Wall -Wextra -I. -all: foci - $(CC) $(CFLAGS) main.c foci.o -o main +all: x86-64 -foci: - $(CC) $(CFLAGS) -c foci.c +clean: + rm -f main foci.o + +x86-64: CC := gcc -DFOCI_X86_64 +x86-64: x86/main.c foci.o + $(CC) $(CFLAGS) $^ -o main + +arm-cm4: CC := arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -DFOCI_ARM +arm-cm4: foci.o + +msp430: CC := msp430-elf-gcc -DFOCI_MSP430 -mmcu=msp430g2553 +msp430: msp430/main.c foci.o + $(CC) $(CFLAGS) -Lmsp430 $^ -o main diff --git a/msp430/main.c b/msp430/main.c index 5c83c2e..1e691d3 100644 --- a/msp430/main.c +++ b/msp430/main.c @@ -1,7 +1,6 @@ #include <msp430.h> -#define FOCI_MSP430 -#include "../foci.h" +#include "foci.h" int main() { diff --git a/msp430/msp430g2553.h b/msp430/msp430g2553.h new file mode 100644 index 0000000..23261d5 --- /dev/null +++ b/msp430/msp430g2553.h @@ -0,0 +1,955 @@ +/* ============================================================================ */ +/* Copyright (c) 2020, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430 microcontroller. +* +* This file supports assembler and C development for +* MSP430G2553 devices. +* +* Texas Instruments, Version 1.2 +* +* Rev. 1.0, Setup +* Rev. 1.1, added additional Cal Data Labels +* Rev. 1.2, added dummy TRAPINT_VECTOR interrupt vector as bugfix for USCI29 +* +********************************************************************/ + +#ifndef __MSP430G2553 +#define __MSP430G2553 + +#define __MSP430_HEADER_VERSION__ 1212 + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------*/ +/* PERIPHERAL FILE MAP */ +/*----------------------------------------------------------------------------*/ + +#define __MSP430_TI_HEADERS__ + +#include <iomacros.h> + + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001) +#define BIT1 (0x0002) +#define BIT2 (0x0004) +#define BIT3 (0x0008) +#define BIT4 (0x0010) +#define BIT5 (0x0020) +#define BIT6 (0x0040) +#define BIT7 (0x0080) +#define BIT8 (0x0100) +#define BIT9 (0x0200) +#define BITA (0x0400) +#define BITB (0x0800) +#define BITC (0x1000) +#define BITD (0x2000) +#define BITE (0x4000) +#define BITF (0x8000) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001) +#define Z (0x0002) +#define N (0x0004) +#define V (0x0100) +#define GIE (0x0008) +#define CPUOFF (0x0010) +#define OSCOFF (0x0020) +#define SCG0 (0x0040) +#define SCG1 (0x0080) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#ifndef __STDC__ /* Begin #defines for assembler */ +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) +/* End #defines for assembler */ + +#else /* Begin #defines for C */ +#define LPM0_bits (CPUOFF) +#define LPM1_bits (SCG0+CPUOFF) +#define LPM2_bits (SCG1+CPUOFF) +#define LPM3_bits (SCG1+SCG0+CPUOFF) +#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) + +#include "in430.h" + +#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ +#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ +#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ +#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ +#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ +#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ +#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ +#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ +#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ +#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#endif /* End #defines for C */ + +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ + +/************************************************************ +* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS +************************************************************/ + +sfr_b(IE1); /* Interrupt Enable 1 */ +#define WDTIE (0x01) /* Watchdog Interrupt Enable */ +#define OFIE (0x02) /* Osc. Fault Interrupt Enable */ +#define NMIIE (0x10) /* NMI Interrupt Enable */ +#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */ + +sfr_b(IFG1); /* Interrupt Flag 1 */ +#define WDTIFG (0x01) /* Watchdog Interrupt Flag */ +#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */ +#define PORIFG (0x04) /* Power On Interrupt Flag */ +#define RSTIFG (0x08) /* Reset Interrupt Flag */ +#define NMIIFG (0x10) /* NMI Interrupt Flag */ + +sfr_b(IE2); /* Interrupt Enable 2 */ +#define UC0IE IE2 +#define UCA0RXIE (0x01) +#define UCA0TXIE (0x02) +#define UCB0RXIE (0x04) +#define UCB0TXIE (0x08) + +sfr_b(IFG2); /* Interrupt Flag 2 */ +#define UC0IFG IFG2 +#define UCA0RXIFG (0x01) +#define UCA0TXIFG (0x02) +#define UCB0RXIFG (0x04) +#define UCB0TXIFG (0x08) + +/************************************************************ +* ADC10 +************************************************************/ +#define __MSP430_HAS_ADC10__ /* Definition to show that Module is available */ + +sfr_b(ADC10DTC0); /* ADC10 Data Transfer Control 0 */ +sfr_b(ADC10DTC1); /* ADC10 Data Transfer Control 1 */ +sfr_b(ADC10AE0); /* ADC10 Analog Enable 0 */ + +sfr_w(ADC10CTL0); /* ADC10 Control 0 */ +sfr_w(ADC10CTL1); /* ADC10 Control 1 */ +sfr_w(ADC10MEM); /* ADC10 Memory */ +sfr_w(ADC10SA); /* ADC10 Data Transfer Start Address */ + +/* ADC10CTL0 */ +#define ADC10SC (0x001) /* ADC10 Start Conversion */ +#define ENC (0x002) /* ADC10 Enable Conversion */ +#define ADC10IFG (0x004) /* ADC10 Interrupt Flag */ +#define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */ +#define ADC10ON (0x010) /* ADC10 On/Enable */ +#define REFON (0x020) /* ADC10 Reference on */ +#define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */ +#define MSC (0x080) /* ADC10 Multiple SampleConversion */ +#define REFBURST (0x100) /* ADC10 Reference Burst Mode */ +#define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */ +#define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */ +#define ADC10SHT0 (0x800) /* ADC10 Sample Hold Select Bit: 0 */ +#define ADC10SHT1 (0x1000) /* ADC10 Sample Hold Select Bit: 1 */ +#define SREF0 (0x2000) /* ADC10 Reference Select Bit: 0 */ +#define SREF1 (0x4000) /* ADC10 Reference Select Bit: 1 */ +#define SREF2 (0x8000) /* ADC10 Reference Select Bit: 2 */ +#define ADC10SHT_0 (0x0000) /* 4 x ADC10CLKs */ +#define ADC10SHT_1 (0x0800) /* 8 x ADC10CLKs */ +#define ADC10SHT_2 (0x1000) /* 16 x ADC10CLKs */ +#define ADC10SHT_3 (0x1800) /* 64 x ADC10CLKs */ + +#define SREF_0 (0x0000) /* VR+ = AVCC and VR- = AVSS */ +#define SREF_1 (0x2000) /* VR+ = VREF+ and VR- = AVSS */ +#define SREF_2 (0x4000) /* VR+ = VEREF+ and VR- = AVSS */ +#define SREF_3 (0x6000) /* VR+ = VEREF+ and VR- = AVSS */ +#define SREF_4 (0x8000) /* VR+ = AVCC and VR- = VREF-/VEREF- */ +#define SREF_5 (0xA000) /* VR+ = VREF+ and VR- = VREF-/VEREF- */ +#define SREF_6 (0xC000) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */ +#define SREF_7 (0xE000) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */ + +/* ADC10CTL1 */ +#define ADC10BUSY (0x0001) /* ADC10 BUSY */ +#define CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */ +#define CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */ +#define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select Bit: 0 */ +#define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select Bit: 1 */ +#define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select Bit: 0 */ +#define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select Bit: 1 */ +#define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select Bit: 2 */ +#define ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */ +#define ADC10DF (0x0200) /* ADC10 Data Format 0:binary 1:2's complement */ +#define SHS0 (0x0400) /* ADC10 Sample/Hold Source Bit: 0 */ +#define SHS1 (0x0800) /* ADC10 Sample/Hold Source Bit: 1 */ +#define INCH0 (0x1000) /* ADC10 Input Channel Select Bit: 0 */ +#define INCH1 (0x2000) /* ADC10 Input Channel Select Bit: 1 */ +#define INCH2 (0x4000) /* ADC10 Input Channel Select Bit: 2 */ +#define INCH3 (0x8000) /* ADC10 Input Channel Select Bit: 3 */ + +#define CONSEQ_0 (0x0000) /* Single channel single conversion */ +#define CONSEQ_1 (0x0002) /* Sequence of channels */ +#define CONSEQ_2 (0x0004) /* Repeat single channel */ +#define CONSEQ_3 (0x0006) /* Repeat sequence of channels */ + +#define ADC10SSEL_0 (0x0000) /* ADC10OSC */ +#define ADC10SSEL_1 (0x0008) /* ACLK */ +#define ADC10SSEL_2 (0x0010) /* MCLK */ +#define ADC10SSEL_3 (0x0018) /* SMCLK */ + +#define ADC10DIV_0 (0x0000) /* ADC10 Clock Divider Select 0 */ +#define ADC10DIV_1 (0x0020) /* ADC10 Clock Divider Select 1 */ +#define ADC10DIV_2 (0x0040) /* ADC10 Clock Divider Select 2 */ +#define ADC10DIV_3 (0x0060) /* ADC10 Clock Divider Select 3 */ +#define ADC10DIV_4 (0x0080) /* ADC10 Clock Divider Select 4 */ +#define ADC10DIV_5 (0x00A0) /* ADC10 Clock Divider Select 5 */ +#define ADC10DIV_6 (0x00C0) /* ADC10 Clock Divider Select 6 */ +#define ADC10DIV_7 (0x00E0) /* ADC10 Clock Divider Select 7 */ + +#define SHS_0 (0x0000) /* ADC10SC */ +#define SHS_1 (0x0400) /* TA3 OUT1 */ +#define SHS_2 (0x0800) /* TA3 OUT0 */ +#define SHS_3 (0x0C00) /* TA3 OUT2 */ + +#define INCH_0 (0x0000) /* Selects Channel 0 */ +#define INCH_1 (0x1000) /* Selects Channel 1 */ +#define INCH_2 (0x2000) /* Selects Channel 2 */ +#define INCH_3 (0x3000) /* Selects Channel 3 */ +#define INCH_4 (0x4000) /* Selects Channel 4 */ +#define INCH_5 (0x5000) /* Selects Channel 5 */ +#define INCH_6 (0x6000) /* Selects Channel 6 */ +#define INCH_7 (0x7000) /* Selects Channel 7 */ +#define INCH_8 (0x8000) /* Selects Channel 8 */ +#define INCH_9 (0x9000) /* Selects Channel 9 */ +#define INCH_10 (0xA000) /* Selects Channel 10 */ +#define INCH_11 (0xB000) /* Selects Channel 11 */ +#define INCH_12 (0xC000) /* Selects Channel 12 */ +#define INCH_13 (0xD000) /* Selects Channel 13 */ +#define INCH_14 (0xE000) /* Selects Channel 14 */ +#define INCH_15 (0xF000) /* Selects Channel 15 */ + +/* ADC10DTC0 */ +#define ADC10FETCH (0x001) /* This bit should normally be reset */ +#define ADC10B1 (0x002) /* ADC10 block one */ +#define ADC10CT (0x004) /* ADC10 continuous transfer */ +#define ADC10TB (0x008) /* ADC10 two-block mode */ +#define ADC10DISABLE (0x000) /* ADC10DTC1 */ + +/************************************************************ +* Basic Clock Module +************************************************************/ +#define __MSP430_HAS_BC2__ /* Definition to show that Module is available */ + +sfr_b(DCOCTL); /* DCO Clock Frequency Control */ +sfr_b(BCSCTL1); /* Basic Clock System Control 1 */ +sfr_b(BCSCTL2); /* Basic Clock System Control 2 */ +sfr_b(BCSCTL3); /* Basic Clock System Control 3 */ + +#define MOD0 (0x01) /* Modulation Bit 0 */ +#define MOD1 (0x02) /* Modulation Bit 1 */ +#define MOD2 (0x04) /* Modulation Bit 2 */ +#define MOD3 (0x08) /* Modulation Bit 3 */ +#define MOD4 (0x10) /* Modulation Bit 4 */ +#define DCO0 (0x20) /* DCO Select Bit 0 */ +#define DCO1 (0x40) /* DCO Select Bit 1 */ +#define DCO2 (0x80) /* DCO Select Bit 2 */ + +#define RSEL0 (0x01) /* Range Select Bit 0 */ +#define RSEL1 (0x02) /* Range Select Bit 1 */ +#define RSEL2 (0x04) /* Range Select Bit 2 */ +#define RSEL3 (0x08) /* Range Select Bit 3 */ +#define DIVA0 (0x10) /* ACLK Divider 0 */ +#define DIVA1 (0x20) /* ACLK Divider 1 */ +#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */ +#define XT2OFF (0x80) /* Enable XT2CLK */ + +#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */ +#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */ +#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */ +#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */ + +#define DIVS0 (0x02) /* SMCLK Divider 0 */ +#define DIVS1 (0x04) /* SMCLK Divider 1 */ +#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */ +#define DIVM0 (0x10) /* MCLK Divider 0 */ +#define DIVM1 (0x20) /* MCLK Divider 1 */ +#define SELM0 (0x40) /* MCLK Source Select 0 */ +#define SELM1 (0x80) /* MCLK Source Select 1 */ + +#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */ +#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */ +#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */ +#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */ + +#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */ +#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */ +#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */ +#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */ + +#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */ +#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */ +#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */ +#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */ + +#define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */ +#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */ +#define XCAP0 (0x04) /* XIN/XOUT Cap 0 */ +#define XCAP1 (0x08) /* XIN/XOUT Cap 1 */ +#define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */ +#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */ +#define XT2S0 (0x40) /* Mode 0 for XT2 */ +#define XT2S1 (0x80) /* Mode 1 for XT2 */ + +#define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */ +#define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */ +#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */ +#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */ + +#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */ +#define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */ +#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */ +#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */ + +#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */ +#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */ +#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */ +#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */ + +/************************************************************ +* Comparator A +************************************************************/ +#define __MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */ + +sfr_b(CACTL1); /* Comparator A Control 1 */ +sfr_b(CACTL2); /* Comparator A Control 2 */ +sfr_b(CAPD); /* Comparator A Port Disable */ + +#define CAIFG (0x01) /* Comp. A Interrupt Flag */ +#define CAIE (0x02) /* Comp. A Interrupt Enable */ +#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */ +#define CAON (0x08) /* Comp. A enable */ +#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */ +#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */ +#define CARSEL (0x40) /* Comp. A Internal Reference Enable */ +#define CAEX (0x80) /* Comp. A Exchange Inputs */ + +#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */ +#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */ +#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */ +#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/ + +#define CAOUT (0x01) /* Comp. A Output */ +#define CAF (0x02) /* Comp. A Enable Output Filter */ +#define P2CA0 (0x04) /* Comp. A +Terminal Multiplexer */ +#define P2CA1 (0x08) /* Comp. A -Terminal Multiplexer */ +#define P2CA2 (0x10) /* Comp. A -Terminal Multiplexer */ +#define P2CA3 (0x20) /* Comp. A -Terminal Multiplexer */ +#define P2CA4 (0x40) /* Comp. A +Terminal Multiplexer */ +#define CASHORT (0x80) /* Comp. A Short + and - Terminals */ + +#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */ +#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */ +#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */ +#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */ +#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */ +#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */ +#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */ +#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */ + +/************************************************************* +* Flash Memory +*************************************************************/ +#define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */ + +sfr_w(FCTL1); /* FLASH Control 1 */ +sfr_w(FCTL2); /* FLASH Control 2 */ +sfr_w(FCTL3); /* FLASH Control 3 */ + +#define FRKEY (0x9600) /* Flash key returned by read */ +#define FWKEY (0xA500) /* Flash key for write */ +#define FXKEY (0x3300) /* for use with XOR instruction */ + +#define ERASE (0x0002) /* Enable bit for Flash segment erase */ +#define MERAS (0x0004) /* Enable bit for Flash mass erase */ +#define WRT (0x0040) /* Enable bit for Flash write */ +#define BLKWRT (0x0080) /* Enable bit for Flash segment write */ +#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */ + +#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */ +#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */ +#ifndef FN2 +#define FN2 (0x0004) +#endif +#ifndef FN3 +#define FN3 (0x0008) +#endif +#ifndef FN4 +#define FN4 (0x0010) +#endif +#define FN5 (0x0020) +#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */ +#define FSSEL1 (0x0080) /* Flash clock select 1 */ + +#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */ +#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */ +#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */ +#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */ + +#define BUSY (0x0001) /* Flash busy: 1 */ +#define KEYV (0x0002) /* Flash Key violation flag */ +#define ACCVIFG (0x0004) /* Flash Access violation flag */ +#define WAIT (0x0008) /* Wait flag for segment write */ +#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX (0x0020) /* Flash Emergency Exit */ +#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +#define FAIL (0x0080) /* Last Program or Erase failed */ + +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ +#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ + +#define __MSP430_HAS_P1SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P1SEL2__ /* Define for DriverLib */ +#define __MSP430_HAS_P2SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P2SEL2__ /* Define for DriverLib */ + +sfr_b(P1IN); /* Port 1 Input */ +sfr_b(P1OUT); /* Port 1 Output */ +sfr_b(P1DIR); /* Port 1 Direction */ +sfr_b(P1IFG); /* Port 1 Interrupt Flag */ +sfr_b(P1IES); /* Port 1 Interrupt Edge Select */ +sfr_b(P1IE); /* Port 1 Interrupt Enable */ +sfr_b(P1SEL); /* Port 1 Selection */ +sfr_b(P1SEL2); /* Port 1 Selection 2 */ +sfr_b(P1REN); /* Port 1 Resistor Enable */ + +sfr_b(P2IN); /* Port 2 Input */ +sfr_b(P2OUT); /* Port 2 Output */ +sfr_b(P2DIR); /* Port 2 Direction */ +sfr_b(P2IFG); /* Port 2 Interrupt Flag */ +sfr_b(P2IES); /* Port 2 Interrupt Edge Select */ +sfr_b(P2IE); /* Port 2 Interrupt Enable */ +sfr_b(P2SEL); /* Port 2 Selection */ +sfr_b(P2SEL2); /* Port 2 Selection 2 */ +sfr_b(P2REN); /* Port 2 Resistor Enable */ + +/************************************************************ +* DIGITAL I/O Port3 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ + +#define __MSP430_HAS_P3SEL__ /* Define for DriverLib */ +#define __MSP430_HAS_P3SEL2__ /* Define for DriverLib */ + +sfr_b(P3IN); /* Port 3 Input */ +sfr_b(P3OUT); /* Port 3 Output */ +sfr_b(P3DIR); /* Port 3 Direction */ +sfr_b(P3SEL); /* Port 3 Selection */ +sfr_b(P3SEL2); /* Port 3 Selection 2 */ +sfr_b(P3REN); /* Port 3 Resistor Enable */ + +/************************************************************ +* Timer0_A3 +************************************************************/ +#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */ + +sfr_w(TA0IV); /* Timer0_A3 Interrupt Vector Word */ +sfr_w(TA0CTL); /* Timer0_A3 Control */ +sfr_w(TA0CCTL0); /* Timer0_A3 Capture/Compare Control 0 */ +sfr_w(TA0CCTL1); /* Timer0_A3 Capture/Compare Control 1 */ +sfr_w(TA0CCTL2); /* Timer0_A3 Capture/Compare Control 2 */ +sfr_w(TA0R); /* Timer0_A3 Counter Register */ +sfr_w(TA0CCR0); /* Timer0_A3 Capture/Compare 0 */ +sfr_w(TA0CCR1); /* Timer0_A3 Capture/Compare 1 */ +sfr_w(TA0CCR2); /* Timer0_A3 Capture/Compare 2 */ + +/* Alternate register names */ +#define TAIV TA0IV /* Timer A Interrupt Vector Word */ +#define TACTL TA0CTL /* Timer A Control */ +#define TACCTL0 TA0CCTL0 /* Timer A Capture/Compare Control 0 */ +#define TACCTL1 TA0CCTL1 /* Timer A Capture/Compare Control 1 */ +#define TACCTL2 TA0CCTL2 /* Timer A Capture/Compare Control 2 */ +#define TAR TA0R /* Timer A Counter Register */ +#define TACCR0 TA0CCR0 /* Timer A Capture/Compare 0 */ +#define TACCR1 TA0CCR1 /* Timer A Capture/Compare 1 */ +#define TACCR2 TA0CCR2 /* Timer A Capture/Compare 2 */ +#define TAIV_ TA0IV_ /* Timer A Interrupt Vector Word */ +#define TACTL_ TA0CTL_ /* Timer A Control */ +#define TACCTL0_ TA0CCTL0_ /* Timer A Capture/Compare Control 0 */ +#define TACCTL1_ TA0CCTL1_ /* Timer A Capture/Compare Control 1 */ +#define TACCTL2_ TA0CCTL2_ /* Timer A Capture/Compare Control 2 */ +#define TAR_ TA0R_ /* Timer A Counter Register */ +#define TACCR0_ TA0CCR0_ /* Timer A Capture/Compare 0 */ +#define TACCR1_ TA0CCR1_ /* Timer A Capture/Compare 1 */ +#define TACCR2_ TA0CCR2_ /* Timer A Capture/Compare 2 */ + +/* Alternate register names 2 */ +#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */ +#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */ +#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */ +#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */ +#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */ +#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */ +#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */ +#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */ +#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */ +#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */ +#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */ +#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */ + +#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ +#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ +#define ID1 (0x0080) /* Timer A clock input divider 1 */ +#define ID0 (0x0040) /* Timer A clock input divider 0 */ +#define MC1 (0x0020) /* Timer A mode control 1 */ +#define MC0 (0x0010) /* Timer A mode control 0 */ +#define TACLR (0x0004) /* Timer A counter clear */ +#define TAIE (0x0002) /* Timer A counter interrupt enable */ +#define TAIFG (0x0001) /* Timer A counter interrupt flag */ + +#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */ +#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC_2 (0x0020) /* Timer A mode control: 2 - Continous up */ +#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */ +#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */ +#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */ +#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */ +#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */ +#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */ + +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define CCIS1 (0x2000) /* Capture input select 1 */ +#define CCIS0 (0x1000) /* Capture input select 0 */ +#define SCS (0x0800) /* Capture sychronize */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define OUTMOD2 (0x0080) /* Output mode 2 */ +#define OUTMOD1 (0x0040) /* Output mode 1 */ +#define OUTMOD0 (0x0020) /* Output mode 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define COV (0x0002) /* Capture/compare overflow flag */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ + +#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */ +#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */ +#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */ +#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */ +#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */ +#define CM_0 (0x0000) /* Capture mode: 0 - disabled */ +#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */ +#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */ +#define CM_3 (0xC000) /* Capture mode: 1 - both edges */ + +/* T0_A3IV Definitions */ +#define TA0IV_NONE (0x0000) /* No Interrupt pending */ +#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */ +#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */ +#define TA0IV_6 (0x0006) /* Reserved */ +#define TA0IV_8 (0x0008) /* Reserved */ +#define TA0IV_TAIFG (0x000A) /* TA0IFG */ + +/************************************************************ +* Timer1_A3 +************************************************************/ +#define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */ + +sfr_w(TA1IV); /* Timer1_A3 Interrupt Vector Word */ +sfr_w(TA1CTL); /* Timer1_A3 Control */ +sfr_w(TA1CCTL0); /* Timer1_A3 Capture/Compare Control 0 */ +sfr_w(TA1CCTL1); /* Timer1_A3 Capture/Compare Control 1 */ +sfr_w(TA1CCTL2); /* Timer1_A3 Capture/Compare Control 2 */ +sfr_w(TA1R); /* Timer1_A3 Counter Register */ +sfr_w(TA1CCR0); /* Timer1_A3 Capture/Compare 0 */ +sfr_w(TA1CCR1); /* Timer1_A3 Capture/Compare 1 */ +sfr_w(TA1CCR2); /* Timer1_A3 Capture/Compare 2 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* T1_A3IV Definitions */ +#define TA1IV_NONE (0x0000) /* No Interrupt pending */ +#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */ +#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */ +#define TA1IV_6 (0x0006) /* Reserved */ +#define TA1IV_8 (0x0008) /* Reserved */ +#define TA1IV_TAIFG (0x000A) /* TA1IFG */ + +/************************************************************ +* USCI +************************************************************/ +#define __MSP430_HAS_USCI__ /* Definition to show that Module is available */ + +sfr_b(UCA0CTL0); /* USCI A0 Control Register 0 */ +sfr_b(UCA0CTL1); /* USCI A0 Control Register 1 */ +sfr_b(UCA0BR0); /* USCI A0 Baud Rate 0 */ +sfr_b(UCA0BR1); /* USCI A0 Baud Rate 1 */ +sfr_b(UCA0MCTL); /* USCI A0 Modulation Control */ +sfr_b(UCA0STAT); /* USCI A0 Status Register */ +sfr_b(UCA0RXBUF); /* USCI A0 Receive Buffer */ +sfr_b(UCA0TXBUF); /* USCI A0 Transmit Buffer */ +sfr_b(UCA0ABCTL); /* USCI A0 LIN Control */ +sfr_b(UCA0IRTCTL); /* USCI A0 IrDA Transmit Control */ +sfr_b(UCA0IRRCTL); /* USCI A0 IrDA Receive Control */ + + + +sfr_b(UCB0CTL0); /* USCI B0 Control Register 0 */ +sfr_b(UCB0CTL1); /* USCI B0 Control Register 1 */ +sfr_b(UCB0BR0); /* USCI B0 Baud Rate 0 */ +sfr_b(UCB0BR1); /* USCI B0 Baud Rate 1 */ +sfr_b(UCB0I2CIE); /* USCI B0 I2C Interrupt Enable Register */ +sfr_b(UCB0STAT); /* USCI B0 Status Register */ +sfr_b(UCB0RXBUF); /* USCI B0 Receive Buffer */ +sfr_b(UCB0TXBUF); /* USCI B0 Transmit Buffer */ +sfr_w(UCB0I2COA); /* USCI B0 I2C Own Address */ +sfr_w(UCB0I2CSA); /* USCI B0 I2C Slave Address */ + +// UART-Mode Bits +#define UCPEN (0x80) /* Async. Mode: Parity enable */ +#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ + +// SPI-Mode Bits +#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */ +#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */ +#define UCMST (0x08) /* Sync. Mode: Master Select */ + +// I2C-Mode Bits +#define UCA10 (0x80) /* 10-bit Address Mode */ +#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */ +#define UCMM (0x20) /* Multi-Master Environment */ +//#define res (0x10) /* reserved */ +#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */ +#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */ +#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */ +#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */ + +// UART-Mode Bits +#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE (0x20) /* RX Error interrupt enable */ +#define UCBRKIE (0x10) /* Break interrupt enable */ +#define UCDORM (0x08) /* Dormant (Sleep) Mode */ +#define UCTXADDR (0x04) /* Send next Data as Address */ +#define UCTXBRK (0x02) /* Send next Data as Break */ +#define UCSWRST (0x01) /* USCI Software Reset */ + +// SPI-Mode Bits +//#define res (0x20) /* reserved */ +//#define res (0x10) /* reserved */ +//#define res (0x08) /* reserved */ +//#define res (0x04) /* reserved */ +//#define res (0x02) /* reserved */ + +// I2C-Mode Bits +//#define res (0x20) /* reserved */ +#define UCTR (0x10) /* Transmit/Receive Select/Flag */ +#define UCTXNACK (0x08) /* Transmit NACK */ +#define UCTXSTP (0x04) /* Transmit STOP */ +#define UCTXSTT (0x02) /* Transmit START */ +#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */ +#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */ +#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */ +#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */ + +#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */ +#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */ +#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */ + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + +#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */ +#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */ +#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */ +#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */ +#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */ +#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */ +#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */ +#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */ + +#define UCLISTEN (0x80) /* USCI Listen mode */ +#define UCFE (0x40) /* USCI Frame Error Flag */ +#define UCOE (0x20) /* USCI Overrun Error Flag */ +#define UCPE (0x10) /* USCI Parity Error Flag */ +#define UCBRK (0x08) /* USCI Break received */ +#define UCRXERR (0x04) /* USCI RX Error Flag */ +#define UCADDR (0x02) /* USCI Address received Flag */ +#define UCBUSY (0x01) /* USCI Busy Flag */ +#define UCIDLE (0x02) /* USCI Idle line detected Flag */ + +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +//#define res (0x20) /* reserved */ +//#define res (0x10) /* reserved */ +#define UCNACKIE (0x08) /* NACK Condition interrupt enable */ +#define UCSTPIE (0x04) /* STOP Condition interrupt enable */ +#define UCSTTIE (0x02) /* START Condition interrupt enable */ +#define UCALIE (0x01) /* Arbitration Lost interrupt enable */ + +#define UCSCLLOW (0x40) /* SCL low */ +#define UCGC (0x20) /* General Call address received Flag */ +#define UCBBUSY (0x10) /* Bus Busy Flag */ +#define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */ +#define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */ +#define UCSTTIFG (0x02) /* START Condition interrupt Flag */ +#define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */ + +#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */ + +#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */ +#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */ + +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ +#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ +#define UCSTOE (0x08) /* Sync-Field Timeout error */ +#define UCBTOE (0x04) /* Break Timeout error */ +//#define res (0x02) /* reserved */ +#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ + +#define UCGCEN (0x8000) /* I2C General Call enable */ +#define UCOA9 (0x0200) /* I2C Own Address 9 */ +#define UCOA8 (0x0100) /* I2C Own Address 8 */ +#define UCOA7 (0x0080) /* I2C Own Address 7 */ +#define UCOA6 (0x0040) /* I2C Own Address 6 */ +#define UCOA5 (0x0020) /* I2C Own Address 5 */ +#define UCOA4 (0x0010) /* I2C Own Address 4 */ +#define UCOA3 (0x0008) /* I2C Own Address 3 */ +#define UCOA2 (0x0004) /* I2C Own Address 2 */ +#define UCOA1 (0x0002) /* I2C Own Address 1 */ +#define UCOA0 (0x0001) /* I2C Own Address 0 */ + +#define UCSA9 (0x0200) /* I2C Slave Address 9 */ +#define UCSA8 (0x0100) /* I2C Slave Address 8 */ +#define UCSA7 (0x0080) /* I2C Slave Address 7 */ +#define UCSA6 (0x0040) /* I2C Slave Address 6 */ +#define UCSA5 (0x0020) /* I2C Slave Address 5 */ +#define UCSA4 (0x0010) /* I2C Slave Address 4 */ +#define UCSA3 (0x0008) /* I2C Slave Address 3 */ +#define UCSA2 (0x0004) /* I2C Slave Address 2 */ +#define UCSA1 (0x0002) /* I2C Slave Address 1 */ +#define UCSA0 (0x0001) /* I2C Slave Address 0 */ + +/************************************************************ +* WATCHDOG TIMER +************************************************************/ +#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */ + +sfr_w(WDTCTL); /* Watchdog Timer Control */ +/* The bit names have been prefixed with "WDT" */ +#define WDTIS0 (0x0001) +#define WDTIS1 (0x0002) +#define WDTSSEL (0x0004) +#define WDTCNTCL (0x0008) +#define WDTTMSEL (0x0010) +#define WDTNMI (0x0020) +#define WDTNMIES (0x0040) +#define WDTHOLD (0x0080) + +#define WDTPW (0x5A00) + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ + +/* INTERRUPT CONTROL */ +/* These two bits are defined in the Special Function Registers */ +/* #define WDTIE 0x01 */ +/* #define WDTIFG 0x01 */ + +/************************************************************ +* Calibration Data in Info Mem +************************************************************/ + +#ifndef __DisableCalData + +sfr_b(CALDCO_16MHZ); /* DCOCTL Calibration Data for 16MHz */ +sfr_b(CALBC1_16MHZ); /* BCSCTL1 Calibration Data for 16MHz */ +sfr_b(CALDCO_12MHZ); /* DCOCTL Calibration Data for 12MHz */ +sfr_b(CALBC1_12MHZ); /* BCSCTL1 Calibration Data for 12MHz */ +sfr_b(CALDCO_8MHZ); /* DCOCTL Calibration Data for 8MHz */ +sfr_b(CALBC1_8MHZ); /* BCSCTL1 Calibration Data for 8MHz */ +sfr_b(CALDCO_1MHZ); /* DCOCTL Calibration Data for 1MHz */ +sfr_b(CALBC1_1MHZ); /* BCSCTL1 Calibration Data for 1MHz */ + +#endif /* #ifndef __DisableCalData */ + +/************************************************************ +* Calibration Data in Info Mem +************************************************************/ + +/* TLV Calibration Data Structure */ +#define TAG_DCO_30 (0x01) /* Tag for DCO30 Calibration Data */ +#define TAG_ADC10_1 (0x10) /* Tag for ADC10_1 Calibration Data */ +#define TAG_EMPTY (0xFE) /* Tag for Empty Data Field in Calibration Data */ + +#ifndef __DisableCalData +sfr_w(TLV_CHECKSUM); /* TLV CHECK SUM */ +sfr_b(TLV_DCO_30_TAG); /* TLV TAG_DCO30 TAG */ +sfr_b(TLV_DCO_30_LEN); /* TLV TAG_DCO30 LEN */ +sfr_b(TLV_ADC10_1_TAG); /* TLV ADC10_1 TAG */ +sfr_b(TLV_ADC10_1_LEN); /* TLV ADC10_1 LEN */ +#endif + +#define CAL_ADC_25T85 (0x0010) /* Index for 2.5V/85Deg Cal. Value */ +#define CAL_ADC_25T30 (0x000E) /* Index for 2.5V/30Deg Cal. Value */ +#define CAL_ADC_25VREF_FACTOR (0x000C) /* Index for 2.5V Ref. Factor */ +#define CAL_ADC_15T85 (0x000A) /* Index for 1.5V/85Deg Cal. Value */ +#define CAL_ADC_15T30 (0x0008) /* Index for 1.5V/30Deg Cal. Value */ +#define CAL_ADC_15VREF_FACTOR (0x0006) /* Index for ADC 1.5V Ref. Factor */ +#define CAL_ADC_OFFSET (0x0004) /* Index for ADC Offset */ +#define CAL_ADC_GAIN_FACTOR (0x0002) /* Index for ADC Gain Factor */ + +#define CAL_DCO_16MHZ (0x0002) /* Index for DCOCTL Calibration Data for 16MHz */ +#define CAL_BC1_16MHZ (0x0003) /* Index for BCSCTL1 Calibration Data for 16MHz */ +#define CAL_DCO_12MHZ (0x0004) /* Index for DCOCTL Calibration Data for 12MHz */ +#define CAL_BC1_12MHZ (0x0005) /* Index for BCSCTL1 Calibration Data for 12MHz */ +#define CAL_DCO_8MHZ (0x0006) /* Index for DCOCTL Calibration Data for 8MHz */ +#define CAL_BC1_8MHZ (0x0007) /* Index for BCSCTL1 Calibration Data for 8MHz */ +#define CAL_DCO_1MHZ (0x0008) /* Index for DCOCTL Calibration Data for 1MHz */ +#define CAL_BC1_1MHZ (0x0009) /* Index for BCSCTL1 Calibration Data for 1MHz */ + + +/************************************************************ +* Interrupt Vectors (offset from 0xFFE0) +************************************************************/ + +#define TRAPINT_VECTOR ( 1) /* 0xFFE0 TRAPINT */ +#define PORT1_VECTOR ( 3) /* 0xFFE4 Port 1 */ +#define PORT2_VECTOR ( 4) /* 0xFFE6 Port 2 */ +#define ADC10_VECTOR ( 6) /* 0xFFEA ADC10 */ +#define USCIAB0TX_VECTOR ( 7) /* 0xFFEC USCI A0/B0 Transmit */ +#define USCIAB0RX_VECTOR ( 8) /* 0xFFEE USCI A0/B0 Receive */ +#define TIMER0_A1_VECTOR ( 9) /* 0xFFF0 Timer0_A CC1, TA0 */ +#define TIMER0_A0_VECTOR (10) /* 0xFFF2 Timer0_A CC0 */ +#define WDT_VECTOR (11) /* 0xFFF4 Watchdog Timer */ +#define COMPARATORA_VECTOR (12) /* 0xFFF6 Comparator A */ +#define TIMER1_A1_VECTOR (13) /* 0xFFF8 Timer1_A CC1-4, TA1 */ +#define TIMER1_A0_VECTOR (14) /* 0xFFFA Timer1_A CC0 */ +#define NMI_VECTOR (15) /* 0xFFFC Non-maskable */ +#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */ + +/************************************************************ +* End of Modules +************************************************************/ + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* #ifndef __MSP430G2553 */ + diff --git a/msp430/msp430g2553.ld b/msp430/msp430g2553.ld new file mode 100644 index 0000000..94f53de --- /dev/null +++ b/msp430/msp430g2553.ld @@ -0,0 +1,315 @@ +/* ============================================================================ */ +/* Copyright (c) 2021, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports MSP430G2553 devices. */ +/* Version: 1.212 */ +/* Default linker script, for normal executables */ + +OUTPUT_ARCH(msp430) +ENTRY(_start) + +MEMORY { + SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */ + RAM : ORIGIN = 0x0200, LENGTH = 0x0200 /* END=0x03FF, size 512 */ + INFOMEM : ORIGIN = 0x1000, LENGTH = 0x0100 /* END=0x10FF, size 256 as 4 64-byte segments */ + INFOA : ORIGIN = 0x10C0, LENGTH = 0x0040 /* END=0x10FF, size 64 */ + INFOB : ORIGIN = 0x1080, LENGTH = 0x0040 /* END=0x10BF, size 64 */ + INFOC : ORIGIN = 0x1040, LENGTH = 0x0040 /* END=0x107F, size 64 */ + INFOD : ORIGIN = 0x1000, LENGTH = 0x0040 /* END=0x103F, size 64 */ + ROM (rx) : ORIGIN = 0xC000, LENGTH = 0x3FDE /* END=0xFFDD, size 16350 */ + BSLSIGNATURE : ORIGIN = 0xFFDE, LENGTH = 0x0002 + VECT1 : ORIGIN = 0xFFE0, LENGTH = 0x0002 + VECT2 : ORIGIN = 0xFFE2, LENGTH = 0x0002 + VECT3 : ORIGIN = 0xFFE4, LENGTH = 0x0002 + VECT4 : ORIGIN = 0xFFE6, LENGTH = 0x0002 + VECT5 : ORIGIN = 0xFFE8, LENGTH = 0x0002 + VECT6 : ORIGIN = 0xFFEA, LENGTH = 0x0002 + VECT7 : ORIGIN = 0xFFEC, LENGTH = 0x0002 + VECT8 : ORIGIN = 0xFFEE, LENGTH = 0x0002 + VECT9 : ORIGIN = 0xFFF0, LENGTH = 0x0002 + VECT10 : ORIGIN = 0xFFF2, LENGTH = 0x0002 + VECT11 : ORIGIN = 0xFFF4, LENGTH = 0x0002 + VECT12 : ORIGIN = 0xFFF6, LENGTH = 0x0002 + VECT13 : ORIGIN = 0xFFF8, LENGTH = 0x0002 + VECT14 : ORIGIN = 0xFFFA, LENGTH = 0x0002 + VECT15 : ORIGIN = 0xFFFC, LENGTH = 0x0002 + RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002 +} + +SECTIONS +{ + .bslsignature : {} > BSLSIGNATURE + __interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) KEEP (*(__interrupt_vector_trapint)) } > VECT1 + __interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) } > VECT2 + __interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) KEEP (*(__interrupt_vector_port1)) } > VECT3 + __interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) KEEP (*(__interrupt_vector_port2)) } > VECT4 + __interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) } > VECT5 + __interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) KEEP (*(__interrupt_vector_adc10)) } > VECT6 + __interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) KEEP (*(__interrupt_vector_usciab0tx)) } > VECT7 + __interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) KEEP (*(__interrupt_vector_usciab0rx)) } > VECT8 + __interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) KEEP (*(__interrupt_vector_timer0_a1)) } > VECT9 + __interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) KEEP (*(__interrupt_vector_timer0_a0)) } > VECT10 + __interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) KEEP (*(__interrupt_vector_wdt)) } > VECT11 + __interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) KEEP (*(__interrupt_vector_comparatora)) } > VECT12 + __interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) KEEP (*(__interrupt_vector_timer1_a1)) } > VECT13 + __interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) KEEP (*(__interrupt_vector_timer1_a0)) } > VECT14 + __interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) KEEP (*(__interrupt_vector_nmi)) } > VECT15 + __reset_vector : + { + KEEP (*(__interrupt_vector_16)) + KEEP (*(__interrupt_vector_reset)) + KEEP (*(.resetvec)) + } > RESETVEC + + .rodata : + { + . = ALIGN(2); + *(.plt) + *(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*) + *(.rodata1) + KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) + } > ROM + + /* Note: This is a separate .rodata section for sections which are + read only but which older linkers treat as read-write. + This prevents older linkers from marking the entire .rodata + section as read-write. */ + .rodata2 : + { + . = ALIGN(2); + PROVIDE (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + . = ALIGN(2); + PROVIDE (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE (__init_array_end = .); + . = ALIGN(2); + PROVIDE (__fini_array_start = .); + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE (__fini_array_end = .); + . = ALIGN(2); + *(.eh_frame_hdr) + KEEP (*(.eh_frame)) + + /* gcc uses crtbegin.o to find the start of the constructors, so + we make sure it is first. Because this is a wildcard, it + doesn't matter if the user does not actually link against + crtbegin.o; the linker won't look for a file to match a + wildcard. The wildcard also means that it doesn't matter which + directory crtbegin.o is in. */ + KEEP (*crtbegin*.o(.ctors)) + + /* We don't want to include the .ctor section from the crtend.o + file until after the sorted ctors. The .ctor section from + the crtend file contains the end of ctors marker and it must + be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } > ROM + + .text : + { + . = ALIGN(2); + PROVIDE (_start = .); + KEEP (*(SORT(.crt_*))) + *(.lowtext .text .stub .text.* .gnu.linkonce.t.* .text:*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.interp .hash .dynsym .dynstr .gnu.version*) + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + . = ALIGN(2); + KEEP (*(.init)) + KEEP (*(.fini)) + KEEP (*(.tm_clone_table)) + } > ROM + + .data : + { + . = ALIGN(2); + PROVIDE (__datastart = .); + + KEEP (*(.jcr)) + *(.data.rel.ro.local) *(.data.rel.ro*) + *(.dynamic) + + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + *(.data1) + *(.got.plt) *(.got) + + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + . = ALIGN(2); + *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1) + + . = ALIGN(2); + _edata = .; + PROVIDE (edata = .); + PROVIDE (__dataend = .); + } > RAM AT>ROM + + /* Note that crt0 assumes this is a multiple of two; all the + start/stop symbols are also assumed word-aligned. */ + PROVIDE(__romdatastart = LOADADDR(.data)); + PROVIDE (__romdatacopysize = SIZEOF(.data)); + + .bss : + { + . = ALIGN(2); + PROVIDE (__bssstart = .); + *(.dynbss) + *(.sbss .sbss.*) + *(.bss .bss.* .gnu.linkonce.b.*) + . = ALIGN(2); + *(COMMON) + PROVIDE (__bssend = .); + } > RAM + PROVIDE (__bsssize = SIZEOF(.bss)); + + /* This section contains data that is not initialised during load + or application reset. */ + .noinit (NOLOAD) : + { + . = ALIGN(2); + PROVIDE (__noinit_start = .); + *(.noinit) + . = ALIGN(2); + PROVIDE (__noinit_end = .); + end = .; + } > RAM + + /* We create this section so that "end" will always be in the + RAM region (matching .stack below), even if the .bss + section is empty. */ + .heap (NOLOAD) : + { + . = ALIGN(2); + __heap_start__ = .; + _end = __heap_start__; + PROVIDE (end = .); + KEEP (*(.heap)) + _end = .; + PROVIDE (end = .); + /* This word is here so that the section is not empty, and thus + not discarded by the linker. The actual value does not matter + and is ignored. */ + LONG(0); + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > RAM + /* WARNING: Do not place anything in RAM here. + The heap section must be the last section in RAM and the stack + section must be placed at the very end of the RAM region. */ + + .stack (ORIGIN (RAM) + LENGTH(RAM)) : + { + PROVIDE (__stack = .); + *(.stack) + } + + .infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */ + .infoB : {} > INFOB + .infoC : {} > INFOC + .infoD : {} > INFOD + + /* The rest are all not normally part of the runtime image. */ + + .MSP430.attributes 0 : + { + KEEP (*(.MSP430.attributes)) + KEEP (*(.gnu.attributes)) + KEEP (*(__TI_build_attributes)) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1. */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions. */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2. */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2. */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions. */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF Extension. */ + .debug_macro 0 : { *(.debug_macro) } + + /DISCARD/ : { *(.note.GNU-stack) } +} + + +/****************************************************************************/ +/* Include peripherals memory map */ +/****************************************************************************/ + +INCLUDE msp430g2553_symbols.ld + diff --git a/msp430/msp430g2553_symbols.ld b/msp430/msp430g2553_symbols.ld new file mode 100644 index 0000000..0b32749 --- /dev/null +++ b/msp430/msp430g2553_symbols.ld @@ -0,0 +1,187 @@ +/* ============================================================================ */ +/* Copyright (c) 2021, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/* This file supports MSP430G2553 devices. */ +/* Version: 1.212 */ + +/************************************************************ +* STANDARD BITS +************************************************************/ +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ +/************************************************************ +* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS +************************************************************/ +PROVIDE(IE1 = 0x0000); +PROVIDE(IFG1 = 0x0002); +PROVIDE(IE2 = 0x0001); +PROVIDE(IFG2 = 0x0003); +/************************************************************ +* ADC10 +************************************************************/ +PROVIDE(ADC10DTC0 = 0x0048); +PROVIDE(ADC10DTC1 = 0x0049); +PROVIDE(ADC10AE0 = 0x004A); +PROVIDE(ADC10CTL0 = 0x01B0); +PROVIDE(ADC10CTL1 = 0x01B2); +PROVIDE(ADC10MEM = 0x01B4); +PROVIDE(ADC10SA = 0x01BC); +/************************************************************ +* Basic Clock Module +************************************************************/ +PROVIDE(DCOCTL = 0x0056); +PROVIDE(BCSCTL1 = 0x0057); +PROVIDE(BCSCTL2 = 0x0058); +PROVIDE(BCSCTL3 = 0x0053); +/************************************************************ +* Comparator A +************************************************************/ +PROVIDE(CACTL1 = 0x0059); +PROVIDE(CACTL2 = 0x005A); +PROVIDE(CAPD = 0x005B); +/************************************************************* +* Flash Memory +*************************************************************/ +PROVIDE(FCTL1 = 0x0128); +PROVIDE(FCTL2 = 0x012A); +PROVIDE(FCTL3 = 0x012C); +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ +PROVIDE(P1IN = 0x0020); +PROVIDE(P1OUT = 0x0021); +PROVIDE(P1DIR = 0x0022); +PROVIDE(P1IFG = 0x0023); +PROVIDE(P1IES = 0x0024); +PROVIDE(P1IE = 0x0025); +PROVIDE(P1SEL = 0x0026); +PROVIDE(P1SEL2 = 0x0041); +PROVIDE(P1REN = 0x0027); +PROVIDE(P2IN = 0x0028); +PROVIDE(P2OUT = 0x0029); +PROVIDE(P2DIR = 0x002A); +PROVIDE(P2IFG = 0x002B); +PROVIDE(P2IES = 0x002C); +PROVIDE(P2IE = 0x002D); +PROVIDE(P2SEL = 0x002E); +PROVIDE(P2SEL2 = 0x0042); +PROVIDE(P2REN = 0x002F); +/************************************************************ +* DIGITAL I/O Port3 Pull up / Pull down Resistors +************************************************************/ +PROVIDE(P3IN = 0x0018); +PROVIDE(P3OUT = 0x0019); +PROVIDE(P3DIR = 0x001A); +PROVIDE(P3SEL = 0x001B); +PROVIDE(P3SEL2 = 0x0043); +PROVIDE(P3REN = 0x0010); +/************************************************************ +* Timer0_A3 +************************************************************/ +PROVIDE(TA0IV = 0x012E); +PROVIDE(TA0CTL = 0x0160); +PROVIDE(TA0CCTL0 = 0x0162); +PROVIDE(TA0CCTL1 = 0x0164); +PROVIDE(TA0CCTL2 = 0x0166); +PROVIDE(TA0R = 0x0170); +PROVIDE(TA0CCR0 = 0x0172); +PROVIDE(TA0CCR1 = 0x0174); +PROVIDE(TA0CCR2 = 0x0176); +/************************************************************ +* Timer1_A3 +************************************************************/ +PROVIDE(TA1IV = 0x011E); +PROVIDE(TA1CTL = 0x0180); +PROVIDE(TA1CCTL0 = 0x0182); +PROVIDE(TA1CCTL1 = 0x0184); +PROVIDE(TA1CCTL2 = 0x0186); +PROVIDE(TA1R = 0x0190); +PROVIDE(TA1CCR0 = 0x0192); +PROVIDE(TA1CCR1 = 0x0194); +PROVIDE(TA1CCR2 = 0x0196); +/************************************************************ +* USCI +************************************************************/ +PROVIDE(UCA0CTL0 = 0x0060); +PROVIDE(UCA0CTL1 = 0x0061); +PROVIDE(UCA0BR0 = 0x0062); +PROVIDE(UCA0BR1 = 0x0063); +PROVIDE(UCA0MCTL = 0x0064); +PROVIDE(UCA0STAT = 0x0065); +PROVIDE(UCA0RXBUF = 0x0066); +PROVIDE(UCA0TXBUF = 0x0067); +PROVIDE(UCA0ABCTL = 0x005D); +PROVIDE(UCA0IRTCTL = 0x005E); +PROVIDE(UCA0IRRCTL = 0x005F); +PROVIDE(UCB0CTL0 = 0x0068); +PROVIDE(UCB0CTL1 = 0x0069); +PROVIDE(UCB0BR0 = 0x006A); +PROVIDE(UCB0BR1 = 0x006B); +PROVIDE(UCB0I2CIE = 0x006C); +PROVIDE(UCB0STAT = 0x006D); +PROVIDE(UCB0RXBUF = 0x006E); +PROVIDE(UCB0TXBUF = 0x006F); +PROVIDE(UCB0I2COA = 0x0118); +PROVIDE(UCB0I2CSA = 0x011A); +/************************************************************ +* WATCHDOG TIMER +************************************************************/ +PROVIDE(WDTCTL = 0x0120); +/************************************************************ +* Calibration Data in Info Mem +************************************************************/ +PROVIDE(CALDCO_16MHZ = 0x10F8); +PROVIDE(CALBC1_16MHZ = 0x10F9); +PROVIDE(CALDCO_12MHZ = 0x10FA); +PROVIDE(CALBC1_12MHZ = 0x10FB); +PROVIDE(CALDCO_8MHZ = 0x10FC); +PROVIDE(CALBC1_8MHZ = 0x10FD); +PROVIDE(CALDCO_1MHZ = 0x10FE); +PROVIDE(CALBC1_1MHZ = 0x10FF); +/************************************************************ +* Calibration Data in Info Mem +************************************************************/ +PROVIDE(TLV_CHECKSUM = 0x10C0); +PROVIDE(TLV_DCO_30_TAG = 0x10F6); +PROVIDE(TLV_DCO_30_LEN = 0x10F7); +PROVIDE(TLV_ADC10_1_TAG = 0x10DA); +PROVIDE(TLV_ADC10_1_LEN = 0x10DB); +/************************************************************ +* Interrupt Vectors (offset from 0xFFE0) +************************************************************/ +/************************************************************ +* End of Modules +************************************************************/ |