diff options
| author | Clyne Sullivan <clyne@bitgloo.com> | 2025-02-05 15:52:50 -0500 |
|---|---|---|
| committer | Clyne Sullivan <clyne@bitgloo.com> | 2025-02-05 15:52:50 -0500 |
| commit | 6d33ec12204a65613ded8bfc7ac92055712a4338 (patch) | |
| tree | e2fbd5fc8a9fa521878b299973aa7c279917d838 | |
| parent | 4add095344df7d2a800f09de2e3869384d175c2d (diff) | |
add stm32 example
| -rw-r--r-- | example/Makefile | 7 | ||||
| -rw-r--r-- | example/STM32U083xx_FLASH.ld | 187 | ||||
| -rw-r--r-- | example/main.cpp | 32 | ||||
| -rw-r--r-- | example/startup_stm32u083xx.s | 296 | ||||
| -rw-r--r-- | example/stm32u083.hpp | 7431 |
5 files changed, 7953 insertions, 0 deletions
diff --git a/example/Makefile b/example/Makefile new file mode 100644 index 0000000..6b0d2fc --- /dev/null +++ b/example/Makefile @@ -0,0 +1,7 @@ +all: + arm-none-eabi-g++ -mcpu=cortex-m0plus -mthumb -std=c++20 -O1 -I .. \ + -fno-exceptions -fno-rtti -fdata-sections -ffunction-sections \ + main.cpp startup_stm32u083xx.s \ + -o main -T STM32U083xx_FLASH.ld -Wl,-gc-sections + arm-none-eabi-objcopy -Oihex main main.hex + diff --git a/example/STM32U083xx_FLASH.ld b/example/STM32U083xx_FLASH.ld new file mode 100644 index 0000000..e058cbf --- /dev/null +++ b/example/STM32U083xx_FLASH.ld @@ -0,0 +1,187 @@ +/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U083xx Device from STM32U0 series
+** 256Kbytes FLASH
+** 40Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2023 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x0; /* required amount of heap */
+_Min_Stack_Size = 0x100; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
+ FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/example/main.cpp b/example/main.cpp new file mode 100644 index 0000000..9fc545e --- /dev/null +++ b/example/main.cpp @@ -0,0 +1,32 @@ +#include "stm32u083.hpp" + +int main() +{ + using namespace STM32U083; + using LD3 = GPIOC::ODR::OD13; + using LD4 = GPIOA::ODR::OD5; + using LD5 = GPIOB::ODR::OD2; + + RCC::ALL::set< + RCC::IOPENR::GPIOAEN, + RCC::IOPENR::GPIOBEN, + RCC::IOPENR::GPIOCEN, + RCC::APBENR1::USART2EN>(); + + GPIOC::MODER::MODE13::write<1>(); + GPIOA::MODER::MODE5::write<1>(); + GPIOB::MODER::MODE2::write<1>(); + + unsigned i = 0; + while (1) { + if (i & 1) LD3::set(); else LD3::clear(); + if (i & 2) LD4::set(); else LD4::clear(); + if (i & 4) LD5::set(); else LD5::clear(); + + for (int j = 0; j < 100000; j++) + asm("nop"); + + i++; + } +} + diff --git a/example/startup_stm32u083xx.s b/example/startup_stm32u083xx.s new file mode 100644 index 0000000..6190254 --- /dev/null +++ b/example/startup_stm32u083xx.s @@ -0,0 +1,296 @@ +/** + ****************************************************************************** + * @file startup_stm32u083xx.s + * @author Auto-generated by STM32CubeIDE + * @brief STM32U083xx device vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32U083xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IWDG_IRQHandler /* Window watchdog interrupt */ + .word PVD_PVM_IRQHandler /* PVD/PVM1/PVM2/PVM3 interrupt (combined with EXTI lines 16 and 19 and 20 and 21) */ + .word RTC_TAMP_IRQHandler /* RTC and TAMP interrupts(combined EXTI lines 19 and 21) */ + .word FLASH_ECC_IRQHandler /* FLASH global interrupt */ + .word RCC_CRS_IRQHandler /* RCC and CRS global interrupt */ + .word EXTI0_1_IRQHandler /* EXTI lines 0 and 1 interrupt */ + .word EXTI2_3_IRQHandler /* EXTI lines 2 and 3 interrupt */ + .word EXTI4_15_IRQHandler /* EXTI lines 4 to 15 interrupt */ + .word USB_DRD_FS_IRQHandler /* USB global interrupt (combined with EXTI line 33) */ + .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 channel 2 and 3 interrupts */ + .word DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler /* DMA1 channel 4, 5, 6, 7, DMAMUX overrun, DMA2 channel 1, 2, 3, 4, 5 interrupts */ + .word ADC_COMP1_2_IRQHandler /* ADC and COMP interrupts (ADC combined with EXTI lines 17 and 18) */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler/* TIM1 break, update, trigger and commutation interrupts */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */ + .word TIM2_IRQHandler /* TIM2 global interrupt */ + .word TIM3_IRQHandler /* TIM3 global interrupt */ + .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, LPTIM1 and DAC global interrupt (combined with EXTI line 29) */ + .word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 global interrupt (combined with EXTI line 30) */ + .word TIM15_LPTIM3_IRQHandler /* TIM15 and LPTIM3 global interrupt (combined with EXTI line 29) */ + .word TIM16_IRQHandler /* TIM16 global interrupt */ + .word TSC_IRQHandler /* TSC global interrupt */ + .word LCD_IRQHandler /* LCD global interrupt (combined with EXTI line 32) */ + .word I2C1_IRQHandler /* I2C1 global interrupt (combined with EXTI line 23) */ + .word I2C2_3_4_IRQHandler /* I2C2/3/4 global interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt */ + .word SPI2_3_IRQHandler /* SPI2/3 global interrupt */ + .word USART1_IRQHandler /* USART1 global interrupt (combined with EXTI line 25) */ + .word USART2_LPUART2_IRQHandler /* USART2 and LPUART2 global interrupt (combined with EXTI lines 26 and 35) */ + .word USART3_LPUART1_IRQHandler /* USART3 and LPUART1 global interrupt (combined with EXTI lines 24 and 28) */ + .word USART4_LPUART3_IRQHandler /* USART4 and LPUART3 global interrupt (combined with EXTI lines 20 and 34) */ + .word RNG_CRYP_IRQHandler /* RNG and CRYPTO global interrupts */ + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IWDG_IRQHandler + .thumb_set WWDG_IWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_ECC_IRQHandler + .thumb_set FLASH_ECC_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak USB_DRD_FS_IRQHandler + .thumb_set USB_DRD_FS_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler,Default_Handler + + .weak ADC_COMP1_2_IRQHandler + .thumb_set ADC_COMP1_2_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_LPTIM1_IRQHandler + .thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler + + .weak TIM7_LPTIM2_IRQHandler + .thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler + + .weak TIM15_LPTIM3_IRQHandler + .thumb_set TIM15_LPTIM3_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_3_4_IRQHandler + .thumb_set I2C2_3_4_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_3_IRQHandler + .thumb_set SPI2_3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_LPUART2_IRQHandler + .thumb_set USART2_LPUART2_IRQHandler,Default_Handler + + .weak USART3_LPUART1_IRQHandler + .thumb_set USART3_LPUART1_IRQHandler,Default_Handler + + .weak USART4_LPUART3_IRQHandler + .thumb_set USART4_LPUART3_IRQHandler,Default_Handler + + .weak RNG_CRYP_IRQHandler + .thumb_set RNG_CRYP_IRQHandler,Default_Handler + diff --git a/example/stm32u083.hpp b/example/stm32u083.hpp new file mode 100644 index 0000000..bafd7d8 --- /dev/null +++ b/example/stm32u083.hpp @@ -0,0 +1,7431 @@ +#include "funreg.hpp" + +namespace STM32U083 { + using namespace fr; + namespace ADC { + struct ISR : public MemRegister<uint32_t, 0x40012400> { + using ADRDY = RegisterMask<ISR, (0x1u << 0x0u)>; + using EOSMP = RegisterMask<ISR, (0x1u << 0x1u)>; + using EOC = RegisterMask<ISR, (0x1u << 0x2u)>; + using EOS = RegisterMask<ISR, (0x1u << 0x3u)>; + using OVR = RegisterMask<ISR, (0x1u << 0x4u)>; + using AWD1 = RegisterMask<ISR, (0x1u << 0x7u)>; + using AWD2 = RegisterMask<ISR, (0x1u << 0x8u)>; + using AWD3 = RegisterMask<ISR, (0x1u << 0x9u)>; + using EOCAL = RegisterMask<ISR, (0x1u << 0xbu)>; + using CCRDY = RegisterMask<ISR, (0x1u << 0xdu)>; + }; + struct IER : public MemRegister<uint32_t, 0x40012404> { + using ADRDYIE = RegisterMask<IER, (0x1u << 0x0u)>; + using EOSMPIE = RegisterMask<IER, (0x1u << 0x1u)>; + using EOCIE = RegisterMask<IER, (0x1u << 0x2u)>; + using EOSIE = RegisterMask<IER, (0x1u << 0x3u)>; + using OVRIE = RegisterMask<IER, (0x1u << 0x4u)>; + using AWD1IE = RegisterMask<IER, (0x1u << 0x7u)>; + using AWD2IE = RegisterMask<IER, (0x1u << 0x8u)>; + using AWD3IE = RegisterMask<IER, (0x1u << 0x9u)>; + using EOCALIE = RegisterMask<IER, (0x1u << 0xbu)>; + using CCRDYIE = RegisterMask<IER, (0x1u << 0xdu)>; + }; + struct CR : public MemRegister<uint32_t, 0x40012408> { + using ADEN = RegisterMask<CR, (0x1u << 0x0u)>; + using ADDIS = RegisterMask<CR, (0x1u << 0x1u)>; + using ADSTART = RegisterMask<CR, (0x1u << 0x2u)>; + using ADSTP = RegisterMask<CR, (0x1u << 0x4u)>; + using ADVREGEN = RegisterMask<CR, (0x1u << 0x1cu)>; + using ADCAL = RegisterMask<CR, (0x1u << 0x1fu)>; + }; + struct CFGR1 : public MemRegister<uint32_t, 0x4001240c> { + using DMAEN = RegisterMask<CFGR1, (0x1u << 0x0u)>; + using DMACFG = RegisterMask<CFGR1, (0x1u << 0x1u)>; + using SCANDIR = RegisterMask<CFGR1, (0x1u << 0x2u)>; + using RES = RegisterMask<CFGR1, (0x3u << 0x3u)>; + using ALIGN = RegisterMask<CFGR1, (0x1u << 0x5u)>; + using EXTSEL = RegisterMask<CFGR1, (0x7u << 0x6u)>; + using EXTEN = RegisterMask<CFGR1, (0x3u << 0xau)>; + using OVRMOD = RegisterMask<CFGR1, (0x1u << 0xcu)>; + using CONT = RegisterMask<CFGR1, (0x1u << 0xdu)>; + using WAIT = RegisterMask<CFGR1, (0x1u << 0xeu)>; + using AUTOFF = RegisterMask<CFGR1, (0x1u << 0xfu)>; + using DISCEN = RegisterMask<CFGR1, (0x1u << 0x10u)>; + using CHSELRMOD = RegisterMask<CFGR1, (0x1u << 0x15u)>; + using AWD1SGL = RegisterMask<CFGR1, (0x1u << 0x16u)>; + using AWD1EN = RegisterMask<CFGR1, (0x1u << 0x17u)>; + using AWD1CH = RegisterMask<CFGR1, (0x1fu << 0x1au)>; + }; + struct CFGR2 : public MemRegister<uint32_t, 0x40012410> { + using OVSE = RegisterMask<CFGR2, (0x1u << 0x0u)>; + using OVSR = RegisterMask<CFGR2, (0x7u << 0x2u)>; + using OVSS = RegisterMask<CFGR2, (0xfu << 0x5u)>; + using TOVS = RegisterMask<CFGR2, (0x1u << 0x9u)>; + using LFTRIG = RegisterMask<CFGR2, (0x1u << 0x1du)>; + using CKMODE = RegisterMask<CFGR2, (0x3u << 0x1eu)>; + }; + struct SMPR : public MemRegister<uint32_t, 0x40012414> { + using SMP1 = RegisterMask<SMPR, (0x7u << 0x0u)>; + using SMP2 = RegisterMask<SMPR, (0x7u << 0x4u)>; + using SMPSEL0 = RegisterMask<SMPR, (0x1u << 0x8u)>; + using SMPSEL1 = RegisterMask<SMPR, (0x1u << 0x9u)>; + using SMPSEL2 = RegisterMask<SMPR, (0x1u << 0xau)>; + using SMPSEL3 = RegisterMask<SMPR, (0x1u << 0xbu)>; + using SMPSEL4 = RegisterMask<SMPR, (0x1u << 0xcu)>; + using SMPSEL5 = RegisterMask<SMPR, (0x1u << 0xdu)>; + using SMPSEL6 = RegisterMask<SMPR, (0x1u << 0xeu)>; + using SMPSEL7 = RegisterMask<SMPR, (0x1u << 0xfu)>; + using SMPSEL8 = RegisterMask<SMPR, (0x1u << 0x10u)>; + using SMPSEL9 = RegisterMask<SMPR, (0x1u << 0x11u)>; + using SMPSEL10 = RegisterMask<SMPR, (0x1u << 0x12u)>; + using SMPSEL11 = RegisterMask<SMPR, (0x1u << 0x13u)>; + using SMPSEL12 = RegisterMask<SMPR, (0x1u << 0x14u)>; + using SMPSEL13 = RegisterMask<SMPR, (0x1u << 0x15u)>; + using SMPSEL14 = RegisterMask<SMPR, (0x1u << 0x16u)>; + using SMPSEL15 = RegisterMask<SMPR, (0x1u << 0x17u)>; + using SMPSEL16 = RegisterMask<SMPR, (0x1u << 0x18u)>; + using SMPSEL17 = RegisterMask<SMPR, (0x1u << 0x19u)>; + using SMPSEL18 = RegisterMask<SMPR, (0x1u << 0x1au)>; + using SMPSEL19 = RegisterMask<SMPR, (0x1u << 0x1bu)>; + }; + struct AWD1TR : public MemRegister<uint32_t, 0x40012420> { + using LT1 = RegisterMask<AWD1TR, (0xfffu << 0x0u)>; + using HT1 = RegisterMask<AWD1TR, (0xfffu << 0x10u)>; + }; + struct AWD2TR : public MemRegister<uint32_t, 0x40012424> { + using LT2 = RegisterMask<AWD2TR, (0xfffu << 0x0u)>; + using HT2 = RegisterMask<AWD2TR, (0xfffu << 0x10u)>; + }; + struct CHSELR : public MemRegister<uint32_t, 0x40012428> { + using CHSEL0 = RegisterMask<CHSELR, (0x1u << 0x0u)>; + using CHSEL1 = RegisterMask<CHSELR, (0x1u << 0x1u)>; + using CHSEL2 = RegisterMask<CHSELR, (0x1u << 0x2u)>; + using CHSEL3 = RegisterMask<CHSELR, (0x1u << 0x3u)>; + using CHSEL4 = RegisterMask<CHSELR, (0x1u << 0x4u)>; + using CHSEL5 = RegisterMask<CHSELR, (0x1u << 0x5u)>; + using CHSEL6 = RegisterMask<CHSELR, (0x1u << 0x6u)>; + using CHSEL7 = RegisterMask<CHSELR, (0x1u << 0x7u)>; + using CHSEL8 = RegisterMask<CHSELR, (0x1u << 0x8u)>; + using CHSEL9 = RegisterMask<CHSELR, (0x1u << 0x9u)>; + using CHSEL10 = RegisterMask<CHSELR, (0x1u << 0xau)>; + using CHSEL11 = RegisterMask<CHSELR, (0x1u << 0xbu)>; + using CHSEL12 = RegisterMask<CHSELR, (0x1u << 0xcu)>; + using CHSEL13 = RegisterMask<CHSELR, (0x1u << 0xdu)>; + using CHSEL14 = RegisterMask<CHSELR, (0x1u << 0xeu)>; + using CHSEL15 = RegisterMask<CHSELR, (0x1u << 0xfu)>; + using CHSEL16 = RegisterMask<CHSELR, (0x1u << 0x10u)>; + using CHSEL17 = RegisterMask<CHSELR, (0x1u << 0x11u)>; + using CHSEL18 = RegisterMask<CHSELR, (0x1u << 0x12u)>; + using CHSEL19 = RegisterMask<CHSELR, (0x1u << 0x13u)>; + }; + struct CHSELR_ALTERNATE : public MemRegister<uint32_t, 0x40012428> { + using SQ1 = RegisterMask<CHSELR_ALTERNATE, (0xfu << 0x0u)>; + using SQ2 = RegisterMask<CHSELR_ALTERNATE, (0xfu << 0x4u)>; + using SQ3 = RegisterMask<CHSELR_ALTERNATE, (0xfu << 0x8u)>; + using SQ4 = RegisterMask<CHSELR_ALTERNATE, (0xfu << 0xcu)>; + using SQ5 = RegisterMask<CHSELR_ALTERNATE, (0xfu << 0x10u)>; + using SQ6 = RegisterMask<CHSELR_ALTERNATE, (0xfu << 0x14u)>; + using SQ7 = RegisterMask<CHSELR_ALTERNATE, (0xfu << 0x18u)>; + using SQ8 = RegisterMask<CHSELR_ALTERNATE, (0xfu << 0x1cu)>; + }; + struct AWD3TR : public MemRegister<uint32_t, 0x4001242c> { + using LT3 = RegisterMask<AWD3TR, (0xfffu << 0x0u)>; + using HT3 = RegisterMask<AWD3TR, (0xfffu << 0x10u)>; + }; + struct DR : public MemRegister<uint32_t, 0x40012440> { + using DATA = RegisterMask<DR, (0xffffu << 0x0u)>; + }; + struct AWD2CR : public MemRegister<uint32_t, 0x400124a0> { + using AWD2CH0 = RegisterMask<AWD2CR, (0x1u << 0x0u)>; + using AWD2CH1 = RegisterMask<AWD2CR, (0x1u << 0x1u)>; + using AWD2CH2 = RegisterMask<AWD2CR, (0x1u << 0x2u)>; + using AWD2CH3 = RegisterMask<AWD2CR, (0x1u << 0x3u)>; + using AWD2CH4 = RegisterMask<AWD2CR, (0x1u << 0x4u)>; + using AWD2CH5 = RegisterMask<AWD2CR, (0x1u << 0x5u)>; + using AWD2CH6 = RegisterMask<AWD2CR, (0x1u << 0x6u)>; + using AWD2CH7 = RegisterMask<AWD2CR, (0x1u << 0x7u)>; + using AWD2CH8 = RegisterMask<AWD2CR, (0x1u << 0x8u)>; + using AWD2CH9 = RegisterMask<AWD2CR, (0x1u << 0x9u)>; + using AWD2CH10 = RegisterMask<AWD2CR, (0x1u << 0xau)>; + using AWD2CH11 = RegisterMask<AWD2CR, (0x1u << 0xbu)>; + using AWD2CH12 = RegisterMask<AWD2CR, (0x1u << 0xcu)>; + using AWD2CH13 = RegisterMask<AWD2CR, (0x1u << 0xdu)>; + using AWD2CH14 = RegisterMask<AWD2CR, (0x1u << 0xeu)>; + using AWD2CH15 = RegisterMask<AWD2CR, (0x1u << 0xfu)>; + using AWD2CH16 = RegisterMask<AWD2CR, (0x1u << 0x10u)>; + using AWD2CH17 = RegisterMask<AWD2CR, (0x1u << 0x11u)>; + using AWD2CH18 = RegisterMask<AWD2CR, (0x1u << 0x12u)>; + using AWD2CH19 = RegisterMask<AWD2CR, (0x1u << 0x13u)>; + }; + struct AWD3CR : public MemRegister<uint32_t, 0x400124a4> { + using AWD3CH0 = RegisterMask<AWD3CR, (0x1u << 0x0u)>; + using AWD3CH1 = RegisterMask<AWD3CR, (0x1u << 0x1u)>; + using AWD3CH2 = RegisterMask<AWD3CR, (0x1u << 0x2u)>; + using AWD3CH3 = RegisterMask<AWD3CR, (0x1u << 0x3u)>; + using AWD3CH4 = RegisterMask<AWD3CR, (0x1u << 0x4u)>; + using AWD3CH5 = RegisterMask<AWD3CR, (0x1u << 0x5u)>; + using AWD3CH6 = RegisterMask<AWD3CR, (0x1u << 0x6u)>; + using AWD3CH7 = RegisterMask<AWD3CR, (0x1u << 0x7u)>; + using AWD3CH8 = RegisterMask<AWD3CR, (0x1u << 0x8u)>; + using AWD3CH9 = RegisterMask<AWD3CR, (0x1u << 0x9u)>; + using AWD3CH10 = RegisterMask<AWD3CR, (0x1u << 0xau)>; + using AWD3CH11 = RegisterMask<AWD3CR, (0x1u << 0xbu)>; + using AWD3CH12 = RegisterMask<AWD3CR, (0x1u << 0xcu)>; + using AWD3CH13 = RegisterMask<AWD3CR, (0x1u << 0xdu)>; + using AWD3CH14 = RegisterMask<AWD3CR, (0x1u << 0xeu)>; + using AWD3CH15 = RegisterMask<AWD3CR, (0x1u << 0xfu)>; + using AWD3CH16 = RegisterMask<AWD3CR, (0x1u << 0x10u)>; + using AWD3CH17 = RegisterMask<AWD3CR, (0x1u << 0x11u)>; + using AWD3CH18 = RegisterMask<AWD3CR, (0x1u << 0x12u)>; + using AWD3CH19 = RegisterMask<AWD3CR, (0x1u << 0x13u)>; + }; + struct CALFACT : public MemRegister<uint32_t, 0x400124b4> { + using val = RegisterMask<CALFACT, (0x7fu << 0x0u)>; + }; + struct CCR : public MemRegister<uint32_t, 0x40012708> { + using PRESC = RegisterMask<CCR, (0xfu << 0x12u)>; + using VREFEN = RegisterMask<CCR, (0x1u << 0x16u)>; + using TSEN = RegisterMask<CCR, (0x1u << 0x17u)>; + using VBATEN = RegisterMask<CCR, (0x1u << 0x18u)>; + }; + using ALL = RegisterGroup<ISR, IER, CR, CFGR1, CFGR2, SMPR, AWD1TR, AWD2TR, CHSELR, CHSELR_ALTERNATE, AWD3TR, DR, AWD2CR, AWD3CR, CALFACT, CCR>; + } + namespace AES { + struct CR : public MemRegister<uint32_t, 0x40026000> { + using EN = RegisterMask<CR, (0x1u << 0x0u)>; + using DATATYPE = RegisterMask<CR, (0x3u << 0x1u)>; + using MODE = RegisterMask<CR, (0x3u << 0x3u)>; + using CHMOD = RegisterMask<CR, (0x3u << 0x5u)>; + using DMAINEN = RegisterMask<CR, (0x1u << 0xbu)>; + using DMAOUTEN = RegisterMask<CR, (0x1u << 0xcu)>; + using GCMPH = RegisterMask<CR, (0x3u << 0xdu)>; + using CHMOD_1 = RegisterMask<CR, (0x1u << 0x10u)>; + using KEYSIZE = RegisterMask<CR, (0x1u << 0x12u)>; + using NPBLB = RegisterMask<CR, (0xfu << 0x14u)>; + using IPRST = RegisterMask<CR, (0x1u << 0x1fu)>; + }; + struct SR : public MemRegister<uint32_t, 0x40026004> { + using RDERRF = RegisterMask<SR, (0x1u << 0x1u)>; + using WRERRF = RegisterMask<SR, (0x1u << 0x2u)>; + using BUSY = RegisterMask<SR, (0x1u << 0x3u)>; + using KEYVALID = RegisterMask<SR, (0x1u << 0x7u)>; + }; + struct DINR : public MemRegister<uint32_t, 0x40026008> { + using DIN = RegisterMask<DINR, (0x0u << 0x0u)>; + }; + struct DOUTR : public MemRegister<uint32_t, 0x4002600c> { + using DOUT = RegisterMask<DOUTR, (0x0u << 0x0u)>; + }; + struct KEYR0 : public MemRegister<uint32_t, 0x40026010> { + using KEY = RegisterMask<KEYR0, (0x0u << 0x0u)>; + }; + struct KEYR1 : public MemRegister<uint32_t, 0x40026014> { + using KEY = RegisterMask<KEYR1, (0x0u << 0x0u)>; + }; + struct KEYR2 : public MemRegister<uint32_t, 0x40026018> { + using KEY = RegisterMask<KEYR2, (0x0u << 0x0u)>; + }; + struct KEYR3 : public MemRegister<uint32_t, 0x4002601c> { + using KEY = RegisterMask<KEYR3, (0x0u << 0x0u)>; + }; + struct IVR0 : public MemRegister<uint32_t, 0x40026020> { + using IVI = RegisterMask<IVR0, (0x0u << 0x0u)>; + }; + struct IVR1 : public MemRegister<uint32_t, 0x40026024> { + using IVI = RegisterMask<IVR1, (0x0u << 0x0u)>; + }; + struct IVR2 : public MemRegister<uint32_t, 0x40026028> { + using IVI = RegisterMask<IVR2, (0x0u << 0x0u)>; + }; + struct IVR3 : public MemRegister<uint32_t, 0x4002602c> { + using IVI = RegisterMask<IVR3, (0x0u << 0x0u)>; + }; + struct KEYR4 : public MemRegister<uint32_t, 0x40026030> { + using KEY = RegisterMask<KEYR4, (0x0u << 0x0u)>; + }; + struct KEYR5 : public MemRegister<uint32_t, 0x40026034> { + using KEY = RegisterMask<KEYR5, (0x0u << 0x0u)>; + }; + struct KEYR6 : public MemRegister<uint32_t, 0x40026038> { + using KEY = RegisterMask<KEYR6, (0x0u << 0x0u)>; + }; + struct KEYR7 : public MemRegister<uint32_t, 0x4002603c> { + using KEY = RegisterMask<KEYR7, (0x0u << 0x0u)>; + }; + struct SUSPR0 : public MemRegister<uint32_t, 0x40026040> { + using SUSP = RegisterMask<SUSPR0, (0x0u << 0x0u)>; + }; + struct SUSPR1 : public MemRegister<uint32_t, 0x40026044> { + using SUSP = RegisterMask<SUSPR1, (0x0u << 0x0u)>; + }; + struct SUSPR2 : public MemRegister<uint32_t, 0x40026048> { + using SUSP = RegisterMask<SUSPR2, (0x0u << 0x0u)>; + }; + struct SUSPR3 : public MemRegister<uint32_t, 0x4002604c> { + using SUSP = RegisterMask<SUSPR3, (0x0u << 0x0u)>; + }; + struct SUSPR4 : public MemRegister<uint32_t, 0x40026050> { + using SUSP = RegisterMask<SUSPR4, (0x0u << 0x0u)>; + }; + struct SUSPR5 : public MemRegister<uint32_t, 0x40026054> { + using SUSP = RegisterMask<SUSPR5, (0x0u << 0x0u)>; + }; + struct SUSPR6 : public MemRegister<uint32_t, 0x40026058> { + using SUSP = RegisterMask<SUSPR6, (0x0u << 0x0u)>; + }; + struct SUSPR7 : public MemRegister<uint32_t, 0x4002605c> { + using SUSP = RegisterMask<SUSPR7, (0x0u << 0x0u)>; + }; + struct IER : public MemRegister<uint32_t, 0x40026300> { + using CCFIE = RegisterMask<IER, (0x1u << 0x0u)>; + using RWEIE = RegisterMask<IER, (0x1u << 0x1u)>; + using KEIE = RegisterMask<IER, (0x1u << 0x2u)>; + }; + struct ISR : public MemRegister<uint32_t, 0x40026304> { + using CCF = RegisterMask<ISR, (0x1u << 0x0u)>; + using RWEIF = RegisterMask<ISR, (0x1u << 0x1u)>; + using KEIF = RegisterMask<ISR, (0x1u << 0x2u)>; + }; + struct ICR : public MemRegister<uint32_t, 0x40026308> { + using CCF = RegisterMask<ICR, (0x1u << 0x0u)>; + using RWEIF = RegisterMask<ICR, (0x1u << 0x1u)>; + using KEIF = RegisterMask<ICR, (0x1u << 0x2u)>; + }; + using ALL = RegisterGroup<CR, SR, DINR, DOUTR, KEYR0, KEYR1, KEYR2, KEYR3, IVR0, IVR1, IVR2, IVR3, KEYR4, KEYR5, KEYR6, KEYR7, SUSPR0, SUSPR1, SUSPR2, SUSPR3, SUSPR4, SUSPR5, SUSPR6, SUSPR7, IER, ISR, ICR>; + } + namespace COMP { + struct COMP1_CSR : public MemRegister<uint32_t, 0x40010200> { + using EN = RegisterMask<COMP1_CSR, (0x1u << 0x0u)>; + using INMSEL = RegisterMask<COMP1_CSR, (0xfu << 0x4u)>; + using INPSEL = RegisterMask<COMP1_CSR, (0x7u << 0x8u)>; + using WINMODE = RegisterMask<COMP1_CSR, (0x1u << 0xbu)>; + using WINOUT = RegisterMask<COMP1_CSR, (0x1u << 0xeu)>; + using POLARITY = RegisterMask<COMP1_CSR, (0x1u << 0xfu)>; + using HYST = RegisterMask<COMP1_CSR, (0x3u << 0x10u)>; + using PWRMODE = RegisterMask<COMP1_CSR, (0x3u << 0x12u)>; + using BLANKSEL = RegisterMask<COMP1_CSR, (0x1fu << 0x14u)>; + using VALUE = RegisterMask<COMP1_CSR, (0x1u << 0x1eu)>; + using LOCK = RegisterMask<COMP1_CSR, (0x1u << 0x1fu)>; + }; + struct COMP2_CSR : public MemRegister<uint32_t, 0x40010204> { + using EN = RegisterMask<COMP2_CSR, (0x1u << 0x0u)>; + using INMSEL = RegisterMask<COMP2_CSR, (0xfu << 0x4u)>; + using INPSEL = RegisterMask<COMP2_CSR, (0x3u << 0x8u)>; + using WINMODE = RegisterMask<COMP2_CSR, (0x1u << 0xbu)>; + using WINOUT = RegisterMask<COMP2_CSR, (0x1u << 0xeu)>; + using POLARITY = RegisterMask<COMP2_CSR, (0x1u << 0xfu)>; + using HYST = RegisterMask<COMP2_CSR, (0x3u << 0x10u)>; + using PWRMODE = RegisterMask<COMP2_CSR, (0x3u << 0x12u)>; + using BLANKSEL = RegisterMask<COMP2_CSR, (0x1fu << 0x14u)>; + using VALUE = RegisterMask<COMP2_CSR, (0x1u << 0x1eu)>; + using LOCK = RegisterMask<COMP2_CSR, (0x1u << 0x1fu)>; + }; + using ALL = RegisterGroup<COMP1_CSR, COMP2_CSR>; + } + namespace CRC { + struct DR : public MemRegister<uint32_t, 0x40023000> { + using val = RegisterMask<DR, (0x0u << 0x0u)>; + }; + struct IDR : public MemRegister<uint32_t, 0x40023004> { + using val = RegisterMask<IDR, (0x0u << 0x0u)>; + }; + struct CR : public MemRegister<uint32_t, 0x40023008> { + using RESET = RegisterMask<CR, (0x1u << 0x0u)>; + using POLYSIZE = RegisterMask<CR, (0x3u << 0x3u)>; + using REV_IN = RegisterMask<CR, (0x3u << 0x5u)>; + using REV_OUT = RegisterMask<CR, (0x3u << 0x7u)>; + using RTYPE_IN = RegisterMask<CR, (0x1u << 0x9u)>; + using RTYPE_OUT = RegisterMask<CR, (0x1u << 0xau)>; + }; + struct INIT : public MemRegister<uint32_t, 0x40023010> { + using CRC_INIT = RegisterMask<INIT, (0x0u << 0x0u)>; + }; + struct POL : public MemRegister<uint32_t, 0x40023014> { + using val = RegisterMask<POL, (0x0u << 0x0u)>; + }; + using ALL = RegisterGroup<DR, IDR, CR, INIT, POL>; + } + namespace CRS { + struct CR : public MemRegister<uint32_t, 0x40006c00> { + using SYNCOKIE = RegisterMask<CR, (0x1u << 0x0u)>; + using SYNCWARNIE = RegisterMask<CR, (0x1u << 0x1u)>; + using ERRIE = RegisterMask<CR, (0x1u << 0x2u)>; + using ESYNCIE = RegisterMask<CR, (0x1u << 0x3u)>; + using CEN = RegisterMask<CR, (0x1u << 0x5u)>; + using AUTOTRIMEN = RegisterMask<CR, (0x1u << 0x6u)>; + using SWSYNC = RegisterMask<CR, (0x1u << 0x7u)>; + using TRIM = RegisterMask<CR, (0x7fu << 0x8u)>; + }; + struct CFGR : public MemRegister<uint32_t, 0x40006c04> { + using RELOAD = RegisterMask<CFGR, (0xffffu << 0x0u)>; + using FELIM = RegisterMask<CFGR, (0xffu << 0x10u)>; + using SYNCDIV = RegisterMask<CFGR, (0x7u << 0x18u)>; + using SYNCSRC = RegisterMask<CFGR, (0x3u << 0x1cu)>; + using SYNCPOL = RegisterMask<CFGR, (0x1u << 0x1fu)>; + }; + struct ISR : public MemRegister<uint32_t, 0x40006c08> { + using SYNCOKF = RegisterMask<ISR, (0x1u << 0x0u)>; + using SYNCWARNF = RegisterMask<ISR, (0x1u << 0x1u)>; + using ERRF = RegisterMask<ISR, (0x1u << 0x2u)>; + using ESYNCF = RegisterMask<ISR, (0x1u << 0x3u)>; + using SYNCERR = RegisterMask<ISR, (0x1u << 0x8u)>; + using SYNCMISS = RegisterMask<ISR, (0x1u << 0x9u)>; + using TRIMOVF = RegisterMask<ISR, (0x1u << 0xau)>; + using FEDIR = RegisterMask<ISR, (0x1u << 0xfu)>; + using FECAP = RegisterMask<ISR, (0xffffu << 0x10u)>; + }; + struct ICR : public MemRegister<uint32_t, 0x40006c0c> { + using SYNCOKC = RegisterMask<ICR, (0x1u << 0x0u)>; + using SYNCWARNC = RegisterMask<ICR, (0x1u << 0x1u)>; + using ERRC = RegisterMask<ICR, (0x1u << 0x2u)>; + using ESYNCC = RegisterMask<ICR, (0x1u << 0x3u)>; + }; + using ALL = RegisterGroup<CR, CFGR, ISR, ICR>; + } + namespace DAC { + struct CR : public MemRegister<uint32_t, 0x40007400> { + using EN1 = RegisterMask<CR, (0x1u << 0x0u)>; + using TEN1 = RegisterMask<CR, (0x1u << 0x1u)>; + using TSEL1 = RegisterMask<CR, (0xfu << 0x2u)>; + using WAVE1 = RegisterMask<CR, (0x3u << 0x6u)>; + using MAMP1 = RegisterMask<CR, (0xfu << 0x8u)>; + using DMAEN1 = RegisterMask<CR, (0x1u << 0xcu)>; + using DMAUDRIE1 = RegisterMask<CR, (0x1u << 0xdu)>; + using CEN1 = RegisterMask<CR, (0x1u << 0xeu)>; + }; + struct SWTRGR : public MemRegister<uint32_t, 0x40007404> { + using SWTRIG1 = RegisterMask<SWTRGR, (0x1u << 0x0u)>; + }; + struct DHR12R1 : public MemRegister<uint32_t, 0x40007408> { + using DACC1DHR = RegisterMask<DHR12R1, (0xfffu << 0x0u)>; + }; + struct DHR12L1 : public MemRegister<uint32_t, 0x4000740c> { + using DACC1DHR = RegisterMask<DHR12L1, (0xfffu << 0x4u)>; + }; + struct DHR8R1 : public MemRegister<uint32_t, 0x40007410> { + using DACC1DHR = RegisterMask<DHR8R1, (0xffu << 0x0u)>; + }; + struct DOR1 : public MemRegister<uint32_t, 0x4000742c> { + using DACC1DOR = RegisterMask<DOR1, (0xfffu << 0x0u)>; + }; + struct SR : public MemRegister<uint32_t, 0x40007434> { + using DMAUDR1 = RegisterMask<SR, (0x1u << 0xdu)>; + using CAL_FLAG1 = RegisterMask<SR, (0x1u << 0xeu)>; + using BWST1 = RegisterMask<SR, (0x1u << 0xfu)>; + }; + struct CCR : public MemRegister<uint32_t, 0x40007438> { + using OTRIM1 = RegisterMask<CCR, (0x1fu << 0x0u)>; + }; + struct MCR : public MemRegister<uint32_t, 0x4000743c> { + using MODE1 = RegisterMask<MCR, (0x7u << 0x0u)>; + }; + struct SHSR1 : public MemRegister<uint32_t, 0x40007440> { + using TSAMPLE1 = RegisterMask<SHSR1, (0x3ffu << 0x0u)>; + }; + struct SHHR : public MemRegister<uint32_t, 0x40007448> { + using THOLD1 = RegisterMask<SHHR, (0x3ffu << 0x0u)>; + }; + struct SHRR : public MemRegister<uint32_t, 0x4000744c> { + using TREFRESH1 = RegisterMask<SHRR, (0xffu << 0x0u)>; + }; + using ALL = RegisterGroup<CR, SWTRGR, DHR12R1, DHR12L1, DHR8R1, DOR1, SR, CCR, MCR, SHSR1, SHHR, SHRR>; + } + namespace DBGMCU { + struct IDCODE : public MemRegister<uint32_t, 0x40015800> { + using DEV_ID = RegisterMask<IDCODE, (0xfffu << 0x0u)>; + using REV_ID = RegisterMask<IDCODE, (0xffffu << 0x10u)>; + }; + struct CR : public MemRegister<uint32_t, 0x40015804> { + using DBG_STOP = RegisterMask<CR, (0x1u << 0x1u)>; + using DBG_STANDBY = RegisterMask<CR, (0x1u << 0x2u)>; + }; + struct APB1FZR : public MemRegister<uint32_t, 0x40015808> { + using DBG_TIM2_STOP = RegisterMask<APB1FZR, (0x1u << 0x0u)>; + using DBG_TIM3_STOP = RegisterMask<APB1FZR, (0x1u << 0x1u)>; + using DBG_TIM4_STOP = RegisterMask<APB1FZR, (0x1u << 0x2u)>; + using DBG_TIM6_STOP = RegisterMask<APB1FZR, (0x1u << 0x4u)>; + using DBG_TIM7_STOP = RegisterMask<APB1FZR, (0x1u << 0x5u)>; + using DBG_RTC_STOP = RegisterMask<APB1FZR, (0x1u << 0xau)>; + using DBG_WWDG_STOP = RegisterMask<APB1FZR, (0x1u << 0xbu)>; + using DBG_IWDG_STOP = RegisterMask<APB1FZR, (0x1u << 0xcu)>; + using DBG_I2C3_STOP = RegisterMask<APB1FZR, (0x1u << 0x15u)>; + using DBG_I2C1_STOP = RegisterMask<APB1FZR, (0x1u << 0x16u)>; + using DBG_LPTIM2_STOP = RegisterMask<APB1FZR, (0x1u << 0x1eu)>; + using DBG_LPTIM1_STOP = RegisterMask<APB1FZR, (0x1u << 0x1fu)>; + }; + struct APB2FZR : public MemRegister<uint32_t, 0x4001580c> { + using DBG_TIM1_STOP = RegisterMask<APB2FZR, (0x1u << 0xbu)>; + using DBG_TIM14_STOP = RegisterMask<APB2FZR, (0x1u << 0xfu)>; + using DBG_TIM15_STOP = RegisterMask<APB2FZR, (0x1u << 0x10u)>; + using DBG_TIM16_STOP = RegisterMask<APB2FZR, (0x1u << 0x11u)>; + using DBG_LPTIM3_STOP = RegisterMask<APB2FZR, (0x1u << 0x12u)>; + }; + struct SR : public MemRegister<uint32_t, 0x400158fc> { + using AP1_PRESENT = RegisterMask<SR, (0x1u << 0x0u)>; + using AP0_PRESENT = RegisterMask<SR, (0x1u << 0x1u)>; + using AP1_ENABLED = RegisterMask<SR, (0x1u << 0x10u)>; + using AP0_ENABLED = RegisterMask<SR, (0x1u << 0x11u)>; + }; + struct DBG_AUTH_HOST : public MemRegister<uint32_t, 0x40015900> { + using MESSAGE = RegisterMask<DBG_AUTH_HOST, (0x0u << 0x0u)>; + }; + struct DBG_AUTH_DEVICE : public MemRegister<uint32_t, 0x40015904> { + using MESSAGE = RegisterMask<DBG_AUTH_DEVICE, (0x0u << 0x0u)>; + }; + struct PIDR4 : public MemRegister<uint32_t, 0x400167d0> { + using JEP106CON = RegisterMask<PIDR4, (0xfu << 0x0u)>; + using SIZE = RegisterMask<PIDR4, (0xfu << 0x4u)>; + }; + struct PIDR0 : public MemRegister<uint32_t, 0x400167e0> { + using PARTNUM = RegisterMask<PIDR0, (0xffu << 0x0u)>; + }; + struct PIDR1 : public MemRegister<uint32_t, 0x400167e4> { + using PARTNUM = RegisterMask<PIDR1, (0xfu << 0x0u)>; + using JEP106ID = RegisterMask<PIDR1, (0xfu << 0x4u)>; + }; + struct PIDR2 : public MemRegister<uint32_t, 0x400167e8> { + using JEP106ID = RegisterMask<PIDR2, (0x7u << 0x0u)>; + using JEDEC = RegisterMask<PIDR2, (0x1u << 0x3u)>; + using REVISION = RegisterMask<PIDR2, (0xfu << 0x4u)>; + }; + struct PIDR3 : public MemRegister<uint32_t, 0x400167ec> { + using CMOD = RegisterMask<PIDR3, (0xfu << 0x0u)>; + using REVAND = RegisterMask<PIDR3, (0xfu << 0x4u)>; + }; + struct CIDR0 : public MemRegister<uint32_t, 0x400167f0> { + using PREAMBLE = RegisterMask<CIDR0, (0xffu << 0x0u)>; + }; + struct CIDR1 : public MemRegister<uint32_t, 0x400167f4> { + using PREAMBLE = RegisterMask<CIDR1, (0xfu << 0x0u)>; + using CLASS = RegisterMask<CIDR1, (0xfu << 0x4u)>; + }; + struct CIDR2 : public MemRegister<uint32_t, 0x400167f8> { + using PREAMBLE = RegisterMask<CIDR2, (0xffu << 0x0u)>; + }; + struct CIDR3 : public MemRegister<uint32_t, 0x400167fc> { + using PREAMBLE = RegisterMask<CIDR3, (0xffu << 0x0u)>; + }; + using ALL = RegisterGroup<IDCODE, CR, APB1FZR, APB2FZR, SR, DBG_AUTH_HOST, DBG_AUTH_DEVICE, PIDR4, PIDR0, PIDR1, PIDR2, PIDR3, CIDR0, CIDR1, CIDR2, CIDR3>; + } + namespace DMA1 { + struct ISR : public MemRegister<uint32_t, 0x40020000> { + using GIF1 = RegisterMask<ISR, (0x1u << 0x0u)>; + using TCIF1 = RegisterMask<ISR, (0x1u << 0x1u)>; + using HTIF1 = RegisterMask<ISR, (0x1u << 0x2u)>; + using TEIF1 = RegisterMask<ISR, (0x1u << 0x3u)>; + using GIF2 = RegisterMask<ISR, (0x1u << 0x4u)>; + using TCIF2 = RegisterMask<ISR, (0x1u << 0x5u)>; + using HTIF2 = RegisterMask<ISR, (0x1u << 0x6u)>; + using TEIF2 = RegisterMask<ISR, (0x1u << 0x7u)>; + using GIF3 = RegisterMask<ISR, (0x1u << 0x8u)>; + using TCIF3 = RegisterMask<ISR, (0x1u << 0x9u)>; + using HTIF3 = RegisterMask<ISR, (0x1u << 0xau)>; + using TEIF3 = RegisterMask<ISR, (0x1u << 0xbu)>; + using GIF4 = RegisterMask<ISR, (0x1u << 0xcu)>; + using TCIF4 = RegisterMask<ISR, (0x1u << 0xdu)>; + using HTIF4 = RegisterMask<ISR, (0x1u << 0xeu)>; + using TEIF4 = RegisterMask<ISR, (0x1u << 0xfu)>; + using GIF5 = RegisterMask<ISR, (0x1u << 0x10u)>; + using TCIF5 = RegisterMask<ISR, (0x1u << 0x11u)>; + using HTIF5 = RegisterMask<ISR, (0x1u << 0x12u)>; + using TEIF5 = RegisterMask<ISR, (0x1u << 0x13u)>; + using GIF6 = RegisterMask<ISR, (0x1u << 0x14u)>; + using TCIF6 = RegisterMask<ISR, (0x1u << 0x15u)>; + using HTIF6 = RegisterMask<ISR, (0x1u << 0x16u)>; + using TEIF6 = RegisterMask<ISR, (0x1u << 0x17u)>; + using GIF7 = RegisterMask<ISR, (0x1u << 0x18u)>; + using TCIF7 = RegisterMask<ISR, (0x1u << 0x19u)>; + using HTIF7 = RegisterMask<ISR, (0x1u << 0x1au)>; + using TEIF7 = RegisterMask<ISR, (0x1u << 0x1bu)>; + }; + struct IFCR : public MemRegister<uint32_t, 0x40020004> { + using CGIF1 = RegisterMask<IFCR, (0x1u << 0x0u)>; + using CTCIF1 = RegisterMask<IFCR, (0x1u << 0x1u)>; + using CHTIF1 = RegisterMask<IFCR, (0x1u << 0x2u)>; + using CTEIF1 = RegisterMask<IFCR, (0x1u << 0x3u)>; + using CGIF2 = RegisterMask<IFCR, (0x1u << 0x4u)>; + using CTCIF2 = RegisterMask<IFCR, (0x1u << 0x5u)>; + using CHTIF2 = RegisterMask<IFCR, (0x1u << 0x6u)>; + using CTEIF2 = RegisterMask<IFCR, (0x1u << 0x7u)>; + using CGIF3 = RegisterMask<IFCR, (0x1u << 0x8u)>; + using CTCIF3 = RegisterMask<IFCR, (0x1u << 0x9u)>; + using CHTIF3 = RegisterMask<IFCR, (0x1u << 0xau)>; + using CTEIF3 = RegisterMask<IFCR, (0x1u << 0xbu)>; + using CGIF4 = RegisterMask<IFCR, (0x1u << 0xcu)>; + using CTCIF4 = RegisterMask<IFCR, (0x1u << 0xdu)>; + using CHTIF4 = RegisterMask<IFCR, (0x1u << 0xeu)>; + using CTEIF4 = RegisterMask<IFCR, (0x1u << 0xfu)>; + using CGIF5 = RegisterMask<IFCR, (0x1u << 0x10u)>; + using CTCIF5 = RegisterMask<IFCR, (0x1u << 0x11u)>; + using CHTIF5 = RegisterMask<IFCR, (0x1u << 0x12u)>; + using CTEIF5 = RegisterMask<IFCR, (0x1u << 0x13u)>; + using CGIF6 = RegisterMask<IFCR, (0x1u << 0x14u)>; + using CTCIF6 = RegisterMask<IFCR, (0x1u << 0x15u)>; + using CHTIF6 = RegisterMask<IFCR, (0x1u << 0x16u)>; + using CTEIF6 = RegisterMask<IFCR, (0x1u << 0x17u)>; + using CGIF7 = RegisterMask<IFCR, (0x1u << 0x18u)>; + using CTCIF7 = RegisterMask<IFCR, (0x1u << 0x19u)>; + using CHTIF7 = RegisterMask<IFCR, (0x1u << 0x1au)>; + using CTEIF7 = RegisterMask<IFCR, (0x1u << 0x1bu)>; + }; + struct CCR1 : public MemRegister<uint32_t, 0x40020008> { + using EN = RegisterMask<CCR1, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR1, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR1, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR1, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR1, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR1, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR1, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR1, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR1, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR1, (0x3u << 0xau)>; + using PL = RegisterMask<CCR1, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR1, (0x1u << 0xeu)>; + }; + struct CNDTR1 : public MemRegister<uint32_t, 0x4002000c> { + using NDT = RegisterMask<CNDTR1, (0xffffu << 0x0u)>; + }; + struct CPAR1 : public MemRegister<uint32_t, 0x40020010> { + using PA = RegisterMask<CPAR1, (0x0u << 0x0u)>; + }; + struct CMAR1 : public MemRegister<uint32_t, 0x40020014> { + using MA = RegisterMask<CMAR1, (0x0u << 0x0u)>; + }; + struct CCR2 : public MemRegister<uint32_t, 0x4002001c> { + using EN = RegisterMask<CCR2, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR2, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR2, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR2, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR2, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR2, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR2, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR2, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR2, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR2, (0x3u << 0xau)>; + using PL = RegisterMask<CCR2, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR2, (0x1u << 0xeu)>; + }; + struct CNDTR2 : public MemRegister<uint32_t, 0x40020020> { + using NDT = RegisterMask<CNDTR2, (0xffffu << 0x0u)>; + }; + struct CPAR2 : public MemRegister<uint32_t, 0x40020024> { + using PA = RegisterMask<CPAR2, (0x0u << 0x0u)>; + }; + struct CMAR2 : public MemRegister<uint32_t, 0x40020028> { + using MA = RegisterMask<CMAR2, (0x0u << 0x0u)>; + }; + struct CCR3 : public MemRegister<uint32_t, 0x40020030> { + using EN = RegisterMask<CCR3, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR3, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR3, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR3, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR3, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR3, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR3, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR3, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR3, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR3, (0x3u << 0xau)>; + using PL = RegisterMask<CCR3, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR3, (0x1u << 0xeu)>; + }; + struct CNDTR3 : public MemRegister<uint32_t, 0x40020034> { + using NDT = RegisterMask<CNDTR3, (0xffffu << 0x0u)>; + }; + struct CPAR3 : public MemRegister<uint32_t, 0x40020038> { + using PA = RegisterMask<CPAR3, (0x0u << 0x0u)>; + }; + struct CMAR3 : public MemRegister<uint32_t, 0x4002003c> { + using MA = RegisterMask<CMAR3, (0x0u << 0x0u)>; + }; + struct CCR4 : public MemRegister<uint32_t, 0x40020044> { + using EN = RegisterMask<CCR4, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR4, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR4, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR4, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR4, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR4, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR4, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR4, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR4, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR4, (0x3u << 0xau)>; + using PL = RegisterMask<CCR4, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR4, (0x1u << 0xeu)>; + }; + struct CNDTR4 : public MemRegister<uint32_t, 0x40020048> { + using NDT = RegisterMask<CNDTR4, (0xffffu << 0x0u)>; + }; + struct CPAR4 : public MemRegister<uint32_t, 0x4002004c> { + using PA = RegisterMask<CPAR4, (0x0u << 0x0u)>; + }; + struct CMAR4 : public MemRegister<uint32_t, 0x40020050> { + using MA = RegisterMask<CMAR4, (0x0u << 0x0u)>; + }; + struct CCR5 : public MemRegister<uint32_t, 0x40020058> { + using EN = RegisterMask<CCR5, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR5, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR5, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR5, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR5, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR5, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR5, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR5, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR5, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR5, (0x3u << 0xau)>; + using PL = RegisterMask<CCR5, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR5, (0x1u << 0xeu)>; + }; + struct CNDTR5 : public MemRegister<uint32_t, 0x4002005c> { + using NDT = RegisterMask<CNDTR5, (0xffffu << 0x0u)>; + }; + struct CPAR5 : public MemRegister<uint32_t, 0x40020060> { + using PA = RegisterMask<CPAR5, (0x0u << 0x0u)>; + }; + struct CMAR5 : public MemRegister<uint32_t, 0x40020064> { + using MA = RegisterMask<CMAR5, (0x0u << 0x0u)>; + }; + struct CCR6 : public MemRegister<uint32_t, 0x4002006c> { + using EN = RegisterMask<CCR6, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR6, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR6, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR6, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR6, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR6, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR6, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR6, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR6, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR6, (0x3u << 0xau)>; + using PL = RegisterMask<CCR6, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR6, (0x1u << 0xeu)>; + }; + struct CNDTR6 : public MemRegister<uint32_t, 0x40020070> { + using NDT = RegisterMask<CNDTR6, (0xffffu << 0x0u)>; + }; + struct CPAR6 : public MemRegister<uint32_t, 0x40020074> { + using PA = RegisterMask<CPAR6, (0x0u << 0x0u)>; + }; + struct CMAR6 : public MemRegister<uint32_t, 0x40020078> { + using MA = RegisterMask<CMAR6, (0x0u << 0x0u)>; + }; + struct CCR7 : public MemRegister<uint32_t, 0x40020080> { + using EN = RegisterMask<CCR7, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR7, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR7, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR7, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR7, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR7, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR7, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR7, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR7, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR7, (0x3u << 0xau)>; + using PL = RegisterMask<CCR7, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR7, (0x1u << 0xeu)>; + }; + struct CNDTR7 : public MemRegister<uint32_t, 0x40020084> { + using NDT = RegisterMask<CNDTR7, (0xffffu << 0x0u)>; + }; + struct CPAR7 : public MemRegister<uint32_t, 0x40020088> { + using PA = RegisterMask<CPAR7, (0x0u << 0x0u)>; + }; + struct CMAR7 : public MemRegister<uint32_t, 0x4002008c> { + using MA = RegisterMask<CMAR7, (0x0u << 0x0u)>; + }; + using ALL = RegisterGroup<ISR, IFCR, CCR1, CNDTR1, CPAR1, CMAR1, CCR2, CNDTR2, CPAR2, CMAR2, CCR3, CNDTR3, CPAR3, CMAR3, CCR4, CNDTR4, CPAR4, CMAR4, CCR5, CNDTR5, CPAR5, CMAR5, CCR6, CNDTR6, CPAR6, CMAR6, CCR7, CNDTR7, CPAR7, CMAR7>; + } + namespace DMA2 { + struct ISR : public MemRegister<uint32_t, 0x40020400> { + using GIF1 = RegisterMask<ISR, (0x1u << 0x0u)>; + using TCIF1 = RegisterMask<ISR, (0x1u << 0x1u)>; + using HTIF1 = RegisterMask<ISR, (0x1u << 0x2u)>; + using TEIF1 = RegisterMask<ISR, (0x1u << 0x3u)>; + using GIF2 = RegisterMask<ISR, (0x1u << 0x4u)>; + using TCIF2 = RegisterMask<ISR, (0x1u << 0x5u)>; + using HTIF2 = RegisterMask<ISR, (0x1u << 0x6u)>; + using TEIF2 = RegisterMask<ISR, (0x1u << 0x7u)>; + using GIF3 = RegisterMask<ISR, (0x1u << 0x8u)>; + using TCIF3 = RegisterMask<ISR, (0x1u << 0x9u)>; + using HTIF3 = RegisterMask<ISR, (0x1u << 0xau)>; + using TEIF3 = RegisterMask<ISR, (0x1u << 0xbu)>; + using GIF4 = RegisterMask<ISR, (0x1u << 0xcu)>; + using TCIF4 = RegisterMask<ISR, (0x1u << 0xdu)>; + using HTIF4 = RegisterMask<ISR, (0x1u << 0xeu)>; + using TEIF4 = RegisterMask<ISR, (0x1u << 0xfu)>; + using GIF5 = RegisterMask<ISR, (0x1u << 0x10u)>; + using TCIF5 = RegisterMask<ISR, (0x1u << 0x11u)>; + using HTIF5 = RegisterMask<ISR, (0x1u << 0x12u)>; + using TEIF5 = RegisterMask<ISR, (0x1u << 0x13u)>; + using GIF6 = RegisterMask<ISR, (0x1u << 0x14u)>; + using TCIF6 = RegisterMask<ISR, (0x1u << 0x15u)>; + using HTIF6 = RegisterMask<ISR, (0x1u << 0x16u)>; + using TEIF6 = RegisterMask<ISR, (0x1u << 0x17u)>; + using GIF7 = RegisterMask<ISR, (0x1u << 0x18u)>; + using TCIF7 = RegisterMask<ISR, (0x1u << 0x19u)>; + using HTIF7 = RegisterMask<ISR, (0x1u << 0x1au)>; + using TEIF7 = RegisterMask<ISR, (0x1u << 0x1bu)>; + }; + struct IFCR : public MemRegister<uint32_t, 0x40020404> { + using CGIF1 = RegisterMask<IFCR, (0x1u << 0x0u)>; + using CTCIF1 = RegisterMask<IFCR, (0x1u << 0x1u)>; + using CHTIF1 = RegisterMask<IFCR, (0x1u << 0x2u)>; + using CTEIF1 = RegisterMask<IFCR, (0x1u << 0x3u)>; + using CGIF2 = RegisterMask<IFCR, (0x1u << 0x4u)>; + using CTCIF2 = RegisterMask<IFCR, (0x1u << 0x5u)>; + using CHTIF2 = RegisterMask<IFCR, (0x1u << 0x6u)>; + using CTEIF2 = RegisterMask<IFCR, (0x1u << 0x7u)>; + using CGIF3 = RegisterMask<IFCR, (0x1u << 0x8u)>; + using CTCIF3 = RegisterMask<IFCR, (0x1u << 0x9u)>; + using CHTIF3 = RegisterMask<IFCR, (0x1u << 0xau)>; + using CTEIF3 = RegisterMask<IFCR, (0x1u << 0xbu)>; + using CGIF4 = RegisterMask<IFCR, (0x1u << 0xcu)>; + using CTCIF4 = RegisterMask<IFCR, (0x1u << 0xdu)>; + using CHTIF4 = RegisterMask<IFCR, (0x1u << 0xeu)>; + using CTEIF4 = RegisterMask<IFCR, (0x1u << 0xfu)>; + using CGIF5 = RegisterMask<IFCR, (0x1u << 0x10u)>; + using CTCIF5 = RegisterMask<IFCR, (0x1u << 0x11u)>; + using CHTIF5 = RegisterMask<IFCR, (0x1u << 0x12u)>; + using CTEIF5 = RegisterMask<IFCR, (0x1u << 0x13u)>; + using CGIF6 = RegisterMask<IFCR, (0x1u << 0x14u)>; + using CTCIF6 = RegisterMask<IFCR, (0x1u << 0x15u)>; + using CHTIF6 = RegisterMask<IFCR, (0x1u << 0x16u)>; + using CTEIF6 = RegisterMask<IFCR, (0x1u << 0x17u)>; + using CGIF7 = RegisterMask<IFCR, (0x1u << 0x18u)>; + using CTCIF7 = RegisterMask<IFCR, (0x1u << 0x19u)>; + using CHTIF7 = RegisterMask<IFCR, (0x1u << 0x1au)>; + using CTEIF7 = RegisterMask<IFCR, (0x1u << 0x1bu)>; + }; + struct CCR1 : public MemRegister<uint32_t, 0x40020408> { + using EN = RegisterMask<CCR1, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR1, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR1, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR1, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR1, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR1, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR1, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR1, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR1, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR1, (0x3u << 0xau)>; + using PL = RegisterMask<CCR1, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR1, (0x1u << 0xeu)>; + }; + struct CNDTR1 : public MemRegister<uint32_t, 0x4002040c> { + using NDT = RegisterMask<CNDTR1, (0xffffu << 0x0u)>; + }; + struct CPAR1 : public MemRegister<uint32_t, 0x40020410> { + using PA = RegisterMask<CPAR1, (0x0u << 0x0u)>; + }; + struct CMAR1 : public MemRegister<uint32_t, 0x40020414> { + using MA = RegisterMask<CMAR1, (0x0u << 0x0u)>; + }; + struct CCR2 : public MemRegister<uint32_t, 0x4002041c> { + using EN = RegisterMask<CCR2, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR2, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR2, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR2, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR2, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR2, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR2, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR2, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR2, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR2, (0x3u << 0xau)>; + using PL = RegisterMask<CCR2, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR2, (0x1u << 0xeu)>; + }; + struct CNDTR2 : public MemRegister<uint32_t, 0x40020420> { + using NDT = RegisterMask<CNDTR2, (0xffffu << 0x0u)>; + }; + struct CPAR2 : public MemRegister<uint32_t, 0x40020424> { + using PA = RegisterMask<CPAR2, (0x0u << 0x0u)>; + }; + struct CMAR2 : public MemRegister<uint32_t, 0x40020428> { + using MA = RegisterMask<CMAR2, (0x0u << 0x0u)>; + }; + struct CCR3 : public MemRegister<uint32_t, 0x40020430> { + using EN = RegisterMask<CCR3, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR3, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR3, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR3, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR3, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR3, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR3, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR3, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR3, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR3, (0x3u << 0xau)>; + using PL = RegisterMask<CCR3, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR3, (0x1u << 0xeu)>; + }; + struct CNDTR3 : public MemRegister<uint32_t, 0x40020434> { + using NDT = RegisterMask<CNDTR3, (0xffffu << 0x0u)>; + }; + struct CPAR3 : public MemRegister<uint32_t, 0x40020438> { + using PA = RegisterMask<CPAR3, (0x0u << 0x0u)>; + }; + struct CMAR3 : public MemRegister<uint32_t, 0x4002043c> { + using MA = RegisterMask<CMAR3, (0x0u << 0x0u)>; + }; + struct CCR4 : public MemRegister<uint32_t, 0x40020444> { + using EN = RegisterMask<CCR4, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR4, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR4, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR4, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR4, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR4, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR4, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR4, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR4, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR4, (0x3u << 0xau)>; + using PL = RegisterMask<CCR4, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR4, (0x1u << 0xeu)>; + }; + struct CNDTR4 : public MemRegister<uint32_t, 0x40020448> { + using NDT = RegisterMask<CNDTR4, (0xffffu << 0x0u)>; + }; + struct CPAR4 : public MemRegister<uint32_t, 0x4002044c> { + using PA = RegisterMask<CPAR4, (0x0u << 0x0u)>; + }; + struct CMAR4 : public MemRegister<uint32_t, 0x40020450> { + using MA = RegisterMask<CMAR4, (0x0u << 0x0u)>; + }; + struct CCR5 : public MemRegister<uint32_t, 0x40020458> { + using EN = RegisterMask<CCR5, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR5, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR5, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR5, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR5, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR5, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR5, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR5, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR5, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR5, (0x3u << 0xau)>; + using PL = RegisterMask<CCR5, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR5, (0x1u << 0xeu)>; + }; + struct CNDTR5 : public MemRegister<uint32_t, 0x4002045c> { + using NDT = RegisterMask<CNDTR5, (0xffffu << 0x0u)>; + }; + struct CPAR5 : public MemRegister<uint32_t, 0x40020460> { + using PA = RegisterMask<CPAR5, (0x0u << 0x0u)>; + }; + struct CMAR5 : public MemRegister<uint32_t, 0x40020464> { + using MA = RegisterMask<CMAR5, (0x0u << 0x0u)>; + }; + struct CCR6 : public MemRegister<uint32_t, 0x4002046c> { + using EN = RegisterMask<CCR6, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR6, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR6, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR6, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR6, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR6, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR6, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR6, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR6, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR6, (0x3u << 0xau)>; + using PL = RegisterMask<CCR6, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR6, (0x1u << 0xeu)>; + }; + struct CNDTR6 : public MemRegister<uint32_t, 0x40020470> { + using NDT = RegisterMask<CNDTR6, (0xffffu << 0x0u)>; + }; + struct CPAR6 : public MemRegister<uint32_t, 0x40020474> { + using PA = RegisterMask<CPAR6, (0x0u << 0x0u)>; + }; + struct CMAR6 : public MemRegister<uint32_t, 0x40020478> { + using MA = RegisterMask<CMAR6, (0x0u << 0x0u)>; + }; + struct CCR7 : public MemRegister<uint32_t, 0x40020480> { + using EN = RegisterMask<CCR7, (0x1u << 0x0u)>; + using TCIE = RegisterMask<CCR7, (0x1u << 0x1u)>; + using HTIE = RegisterMask<CCR7, (0x1u << 0x2u)>; + using TEIE = RegisterMask<CCR7, (0x1u << 0x3u)>; + using DIR = RegisterMask<CCR7, (0x1u << 0x4u)>; + using CIRC = RegisterMask<CCR7, (0x1u << 0x5u)>; + using PINC = RegisterMask<CCR7, (0x1u << 0x6u)>; + using MINC = RegisterMask<CCR7, (0x1u << 0x7u)>; + using PSIZE = RegisterMask<CCR7, (0x3u << 0x8u)>; + using MSIZE = RegisterMask<CCR7, (0x3u << 0xau)>; + using PL = RegisterMask<CCR7, (0x3u << 0xcu)>; + using MEM2MEM = RegisterMask<CCR7, (0x1u << 0xeu)>; + }; + struct CNDTR7 : public MemRegister<uint32_t, 0x40020484> { + using NDT = RegisterMask<CNDTR7, (0xffffu << 0x0u)>; + }; + struct CPAR7 : public MemRegister<uint32_t, 0x40020488> { + using PA = RegisterMask<CPAR7, (0x0u << 0x0u)>; + }; + struct CMAR7 : public MemRegister<uint32_t, 0x4002048c> { + using MA = RegisterMask<CMAR7, (0x0u << 0x0u)>; + }; + using ALL = RegisterGroup<ISR, IFCR, CCR1, CNDTR1, CPAR1, CMAR1, CCR2, CNDTR2, CPAR2, CMAR2, CCR3, CNDTR3, CPAR3, CMAR3, CCR4, CNDTR4, CPAR4, CMAR4, CCR5, CNDTR5, CPAR5, CMAR5, CCR6, CNDTR6, CPAR6, CMAR6, CCR7, CNDTR7, CPAR7, CMAR7>; + } + namespace DMAMUX { + struct C0CR : public MemRegister<uint32_t, 0x40020800> { + using DMAREQ_ID = RegisterMask<C0CR, (0x7fu << 0x0u)>; + using SOIE = RegisterMask<C0CR, (0x1u << 0x8u)>; + using EGE = RegisterMask<C0CR, (0x1u << 0x9u)>; + using SE = RegisterMask<C0CR, (0x1u << 0x10u)>; + using SPOL = RegisterMask<C0CR, (0x3u << 0x11u)>; + using NBREQ = RegisterMask<C0CR, (0x1fu << 0x13u)>; + using SYNC_ID = RegisterMask<C0CR, (0x1fu << 0x18u)>; + }; + struct C1CR : public MemRegister<uint32_t, 0x40020804> { + using DMAREQ_ID = RegisterMask<C1CR, (0x7fu << 0x0u)>; + using SOIE = RegisterMask<C1CR, (0x1u << 0x8u)>; + using EGE = RegisterMask<C1CR, (0x1u << 0x9u)>; + using SE = RegisterMask<C1CR, (0x1u << 0x10u)>; + using SPOL = RegisterMask<C1CR, (0x3u << 0x11u)>; + using NBREQ = RegisterMask<C1CR, (0x1fu << 0x13u)>; + using SYNC_ID = RegisterMask<C1CR, (0x1fu << 0x18u)>; + }; + struct C2CR : public MemRegister<uint32_t, 0x40020808> { + using DMAREQ_ID = RegisterMask<C2CR, (0x7fu << 0x0u)>; + using SOIE = RegisterMask<C2CR, (0x1u << 0x8u)>; + using EGE = RegisterMask<C2CR, (0x1u << 0x9u)>; + using SE = RegisterMask<C2CR, (0x1u << 0x10u)>; + using SPOL = RegisterMask<C2CR, (0x3u << 0x11u)>; + using NBREQ = RegisterMask<C2CR, (0x1fu << 0x13u)>; + using SYNC_ID = RegisterMask<C2CR, (0x1fu << 0x18u)>; + }; + struct C3CR : public MemRegister<uint32_t, 0x4002080c> { + using DMAREQ_ID = RegisterMask<C3CR, (0x7fu << 0x0u)>; + using SOIE = RegisterMask<C3CR, (0x1u << 0x8u)>; + using EGE = RegisterMask<C3CR, (0x1u << 0x9u)>; + using SE = RegisterMask<C3CR, (0x1u << 0x10u)>; + using SPOL = RegisterMask<C3CR, (0x3u << 0x11u)>; + using NBREQ = RegisterMask<C3CR, (0x1fu << 0x13u)>; + using SYNC_ID = RegisterMask<C3CR, (0x1fu << 0x18u)>; + }; + struct C4CR : public MemRegister<uint32_t, 0x40020810> { + using DMAREQ_ID = RegisterMask<C4CR, (0x7fu << 0x0u)>; + using SOIE = RegisterMask<C4CR, (0x1u << 0x8u)>; + using EGE = RegisterMask<C4CR, (0x1u << 0x9u)>; + using SE = RegisterMask<C4CR, (0x1u << 0x10u)>; + using SPOL = RegisterMask<C4CR, (0x3u << 0x11u)>; + using NBREQ = RegisterMask<C4CR, (0x1fu << 0x13u)>; + using SYNC_ID = RegisterMask<C4CR, (0x1fu << 0x18u)>; + }; + struct C5CR : public MemRegister<uint32_t, 0x40020814> { + using DMAREQ_ID = RegisterMask<C5CR, (0x7fu << 0x0u)>; + using SOIE = RegisterMask<C5CR, (0x1u << 0x8u)>; + using EGE = RegisterMask<C5CR, (0x1u << 0x9u)>; + using SE = RegisterMask<C5CR, (0x1u << 0x10u)>; + using SPOL = RegisterMask<C5CR, (0x3u << 0x11u)>; + using NBREQ = RegisterMask<C5CR, (0x1fu << 0x13u)>; + using SYNC_ID = RegisterMask<C5CR, (0x1fu << 0x18u)>; + }; + struct C6CR : public MemRegister<uint32_t, 0x40020818> { + using DMAREQ_ID = RegisterMask<C6CR, (0x7fu << 0x0u)>; + using SOIE = RegisterMask<C6CR, (0x1u << 0x8u)>; + using EGE = RegisterMask<C6CR, (0x1u << 0x9u)>; + using SE = RegisterMask<C6CR, (0x1u << 0x10u)>; + using SPOL = RegisterMask<C6CR, (0x3u << 0x11u)>; + using NBREQ = RegisterMask<C6CR, (0x1fu << 0x13u)>; + using SYNC_ID = RegisterMask<C6CR, (0x1fu << 0x18u)>; + }; + struct C7CR : public MemRegister<uint32_t, 0x4002081c> { + using DMAREQ_ID = RegisterMask<C7CR, (0x7fu << 0x0u)>; + using SOIE = RegisterMask<C7CR, (0x1u << 0x8u)>; + using EGE = RegisterMask<C7CR, (0x1u << 0x9u)>; + using SE = RegisterMask<C7CR, (0x1u << 0x10u)>; + using SPOL = RegisterMask<C7CR, (0x3u << 0x11u)>; + using NBREQ = RegisterMask<C7CR, (0x1fu << 0x13u)>; + using SYNC_ID = RegisterMask<C7CR, (0x1fu << 0x18u)>; + }; + struct C8CR : public MemRegister<uint32_t, 0x40020820> { + using DMAREQ_ID = RegisterMask<C8CR, (0x7fu << 0x0u)>; + using SOIE = RegisterMask<C8CR, (0x1u << 0x8u)>; + using EGE = RegisterMask<C8CR, (0x1u << 0x9u)>; + using SE = RegisterMask<C8CR, (0x1u << 0x10u)>; + using SPOL = RegisterMask<C8CR, (0x3u << 0x11u)>; + using NBREQ = RegisterMask<C8CR, (0x1fu << 0x13u)>; + using SYNC_ID = RegisterMask<C8CR, (0x1fu << 0x18u)>; + }; + struct C9CR : public MemRegister<uint32_t, 0x40020824> { + using DMAREQ_ID = RegisterMask<C9CR, (0x7fu << 0x0u)>; + using SOIE = RegisterMask<C9CR, (0x1u << 0x8u)>; + using EGE = RegisterMask<C9CR, (0x1u << 0x9u)>; + using SE = RegisterMask<C9CR, (0x1u << 0x10u)>; + using SPOL = RegisterMask<C9CR, (0x3u << 0x11u)>; + using NBREQ = RegisterMask<C9CR, (0x1fu << 0x13u)>; + using SYNC_ID = RegisterMask<C9CR, (0x1fu << 0x18u)>; + }; + struct C10CR : public MemRegister<uint32_t, 0x40020828> { + using DMAREQ_ID = RegisterMask<C10CR, (0x7fu << 0x0u)>; + using SOIE = RegisterMask<C10CR, (0x1u << 0x8u)>; + using EGE = RegisterMask<C10CR, (0x1u << 0x9u)>; + using SE = RegisterMask<C10CR, (0x1u << 0x10u)>; + using SPOL = RegisterMask<C10CR, (0x3u << 0x11u)>; + using NBREQ = RegisterMask<C10CR, (0x1fu << 0x13u)>; + using SYNC_ID = RegisterMask<C10CR, (0x1fu << 0x18u)>; + }; + struct C11CR : public MemRegister<uint32_t, 0x4002082c> { + using DMAREQ_ID = RegisterMask<C11CR, (0x7fu << 0x0u)>; + using SOIE = RegisterMask<C11CR, (0x1u << 0x8u)>; + using EGE = RegisterMask<C11CR, (0x1u << 0x9u)>; + using SE = RegisterMask<C11CR, (0x1u << 0x10u)>; + using SPOL = RegisterMask<C11CR, (0x3u << 0x11u)>; + using NBREQ = RegisterMask<C11CR, (0x1fu << 0x13u)>; + using SYNC_ID = RegisterMask<C11CR, (0x1fu << 0x18u)>; + }; + struct CSR : public MemRegister<uint32_t, 0x40020880> { + using SOF0 = RegisterMask<CSR, (0x1u << 0x0u)>; + using SOF1 = RegisterMask<CSR, (0x1u << 0x1u)>; + using SOF2 = RegisterMask<CSR, (0x1u << 0x2u)>; + using SOF3 = RegisterMask<CSR, (0x1u << 0x3u)>; + using SOF4 = RegisterMask<CSR, (0x1u << 0x4u)>; + using SOF5 = RegisterMask<CSR, (0x1u << 0x5u)>; + using SOF6 = RegisterMask<CSR, (0x1u << 0x6u)>; + using SOF7 = RegisterMask<CSR, (0x1u << 0x7u)>; + using SOF8 = RegisterMask<CSR, (0x1u << 0x8u)>; + using SOF9 = RegisterMask<CSR, (0x1u << 0x9u)>; + using SOF10 = RegisterMask<CSR, (0x1u << 0xau)>; + using SOF11 = RegisterMask<CSR, (0x1u << 0xbu)>; + }; + struct CFR : public MemRegister<uint32_t, 0x40020884> { + using CSOF0 = RegisterMask<CFR, (0x1u << 0x0u)>; + using CSOF1 = RegisterMask<CFR, (0x1u << 0x1u)>; + using CSOF2 = RegisterMask<CFR, (0x1u << 0x2u)>; + using CSOF3 = RegisterMask<CFR, (0x1u << 0x3u)>; + using CSOF4 = RegisterMask<CFR, (0x1u << 0x4u)>; + using CSOF5 = RegisterMask<CFR, (0x1u << 0x5u)>; + using CSOF6 = RegisterMask<CFR, (0x1u << 0x6u)>; + using CSOF7 = RegisterMask<CFR, (0x1u << 0x7u)>; + using CSOF8 = RegisterMask<CFR, (0x1u << 0x8u)>; + using CSOF9 = RegisterMask<CFR, (0x1u << 0x9u)>; + using CSOF10 = RegisterMask<CFR, (0x1u << 0xau)>; + using CSOF11 = RegisterMask<CFR, (0x1u << 0xbu)>; + }; + struct RG0CR : public MemRegister<uint32_t, 0x40020900> { + using SIG_ID = RegisterMask<RG0CR, (0x1fu << 0x0u)>; + using OIE = RegisterMask<RG0CR, (0x1u << 0x8u)>; + using GE = RegisterMask<RG0CR, (0x1u << 0x10u)>; + using GPOL = RegisterMask<RG0CR, (0x3u << 0x11u)>; + using GNBREQ = RegisterMask<RG0CR, (0x1fu << 0x13u)>; + }; + struct RG1CR : public MemRegister<uint32_t, 0x40020904> { + using SIG_ID = RegisterMask<RG1CR, (0x1fu << 0x0u)>; + using OIE = RegisterMask<RG1CR, (0x1u << 0x8u)>; + using GE = RegisterMask<RG1CR, (0x1u << 0x10u)>; + using GPOL = RegisterMask<RG1CR, (0x3u << 0x11u)>; + using GNBREQ = RegisterMask<RG1CR, (0x1fu << 0x13u)>; + }; + struct RG2CR : public MemRegister<uint32_t, 0x40020908> { + using SIG_ID = RegisterMask<RG2CR, (0x1fu << 0x0u)>; + using OIE = RegisterMask<RG2CR, (0x1u << 0x8u)>; + using GE = RegisterMask<RG2CR, (0x1u << 0x10u)>; + using GPOL = RegisterMask<RG2CR, (0x3u << 0x11u)>; + using GNBREQ = RegisterMask<RG2CR, (0x1fu << 0x13u)>; + }; + struct RG3CR : public MemRegister<uint32_t, 0x4002090c> { + using SIG_ID = RegisterMask<RG3CR, (0x1fu << 0x0u)>; + using OIE = RegisterMask<RG3CR, (0x1u << 0x8u)>; + using GE = RegisterMask<RG3CR, (0x1u << 0x10u)>; + using GPOL = RegisterMask<RG3CR, (0x3u << 0x11u)>; + using GNBREQ = RegisterMask<RG3CR, (0x1fu << 0x13u)>; + }; + struct RGSR : public MemRegister<uint32_t, 0x40020940> { + using OF0 = RegisterMask<RGSR, (0x1u << 0x0u)>; + using OF1 = RegisterMask<RGSR, (0x1u << 0x1u)>; + using OF2 = RegisterMask<RGSR, (0x1u << 0x2u)>; + using OF3 = RegisterMask<RGSR, (0x1u << 0x3u)>; + }; + struct RGCFR : public MemRegister<uint32_t, 0x40020944> { + using COF0 = RegisterMask<RGCFR, (0x1u << 0x0u)>; + using COF1 = RegisterMask<RGCFR, (0x1u << 0x1u)>; + using COF2 = RegisterMask<RGCFR, (0x1u << 0x2u)>; + using COF3 = RegisterMask<RGCFR, (0x1u << 0x3u)>; + }; + using ALL = RegisterGroup<C0CR, C1CR, C2CR, C3CR, C4CR, C5CR, C6CR, C7CR, C8CR, C9CR, C10CR, C11CR, CSR, CFR, RG0CR, RG1CR, RG2CR, RG3CR, RGSR, RGCFR>; + } + namespace EXTI { + struct RTSR1 : public MemRegister<uint32_t, 0x40021800> { + using RT0 = RegisterMask<RTSR1, (0x1u << 0x0u)>; + using RT1 = RegisterMask<RTSR1, (0x1u << 0x1u)>; + using RT2 = RegisterMask<RTSR1, (0x1u << 0x2u)>; + using RT3 = RegisterMask<RTSR1, (0x1u << 0x3u)>; + using RT4 = RegisterMask<RTSR1, (0x1u << 0x4u)>; + using RT5 = RegisterMask<RTSR1, (0x1u << 0x5u)>; + using RT6 = RegisterMask<RTSR1, (0x1u << 0x6u)>; + using RT7 = RegisterMask<RTSR1, (0x1u << 0x7u)>; + using RT8 = RegisterMask<RTSR1, (0x1u << 0x8u)>; + using RT9 = RegisterMask<RTSR1, (0x1u << 0x9u)>; + using RT10 = RegisterMask<RTSR1, (0x1u << 0xau)>; + using RT11 = RegisterMask<RTSR1, (0x1u << 0xbu)>; + using RT12 = RegisterMask<RTSR1, (0x1u << 0xcu)>; + using RT13 = RegisterMask<RTSR1, (0x1u << 0xdu)>; + using RT14 = RegisterMask<RTSR1, (0x1u << 0xeu)>; + using RT15 = RegisterMask<RTSR1, (0x1u << 0xfu)>; + using RT16 = RegisterMask<RTSR1, (0x1u << 0x10u)>; + using RT17 = RegisterMask<RTSR1, (0x1u << 0x11u)>; + using RT18 = RegisterMask<RTSR1, (0x1u << 0x12u)>; + using RT19 = RegisterMask<RTSR1, (0x1u << 0x13u)>; + using RT20 = RegisterMask<RTSR1, (0x1u << 0x14u)>; + using RT21 = RegisterMask<RTSR1, (0x1u << 0x15u)>; + }; + struct FTSR1 : public MemRegister<uint32_t, 0x40021804> { + using FT0 = RegisterMask<FTSR1, (0x1u << 0x0u)>; + using FT1 = RegisterMask<FTSR1, (0x1u << 0x1u)>; + using FT2 = RegisterMask<FTSR1, (0x1u << 0x2u)>; + using FT3 = RegisterMask<FTSR1, (0x1u << 0x3u)>; + using FT4 = RegisterMask<FTSR1, (0x1u << 0x4u)>; + using FT5 = RegisterMask<FTSR1, (0x1u << 0x5u)>; + using FT6 = RegisterMask<FTSR1, (0x1u << 0x6u)>; + using FT7 = RegisterMask<FTSR1, (0x1u << 0x7u)>; + using FT8 = RegisterMask<FTSR1, (0x1u << 0x8u)>; + using FT9 = RegisterMask<FTSR1, (0x1u << 0x9u)>; + using FT10 = RegisterMask<FTSR1, (0x1u << 0xau)>; + using FT11 = RegisterMask<FTSR1, (0x1u << 0xbu)>; + using FT12 = RegisterMask<FTSR1, (0x1u << 0xcu)>; + using FT13 = RegisterMask<FTSR1, (0x1u << 0xdu)>; + using FT14 = RegisterMask<FTSR1, (0x1u << 0xeu)>; + using FT15 = RegisterMask<FTSR1, (0x1u << 0xfu)>; + using FT16 = RegisterMask<FTSR1, (0x1u << 0x10u)>; + using FT17 = RegisterMask<FTSR1, (0x1u << 0x11u)>; + using FT18 = RegisterMask<FTSR1, (0x1u << 0x12u)>; + using FT19 = RegisterMask<FTSR1, (0x1u << 0x13u)>; + using FT20 = RegisterMask<FTSR1, (0x1u << 0x14u)>; + using FT21 = RegisterMask<FTSR1, (0x1u << 0x15u)>; + }; + struct SWIER1 : public MemRegister<uint32_t, 0x40021808> { + using SWI0 = RegisterMask<SWIER1, (0x1u << 0x0u)>; + using SWI1 = RegisterMask<SWIER1, (0x1u << 0x1u)>; + using SWI2 = RegisterMask<SWIER1, (0x1u << 0x2u)>; + using SWI3 = RegisterMask<SWIER1, (0x1u << 0x3u)>; + using SWI4 = RegisterMask<SWIER1, (0x1u << 0x4u)>; + using SWI5 = RegisterMask<SWIER1, (0x1u << 0x5u)>; + using SWI6 = RegisterMask<SWIER1, (0x1u << 0x6u)>; + using SWI7 = RegisterMask<SWIER1, (0x1u << 0x7u)>; + using SWI8 = RegisterMask<SWIER1, (0x1u << 0x8u)>; + using SWI9 = RegisterMask<SWIER1, (0x1u << 0x9u)>; + using SWI10 = RegisterMask<SWIER1, (0x1u << 0xau)>; + using SWI11 = RegisterMask<SWIER1, (0x1u << 0xbu)>; + using SWI12 = RegisterMask<SWIER1, (0x1u << 0xcu)>; + using SWI13 = RegisterMask<SWIER1, (0x1u << 0xdu)>; + using SWI14 = RegisterMask<SWIER1, (0x1u << 0xeu)>; + using SWI15 = RegisterMask<SWIER1, (0x1u << 0xfu)>; + using SWI16 = RegisterMask<SWIER1, (0x1u << 0x10u)>; + using SWI17 = RegisterMask<SWIER1, (0x1u << 0x11u)>; + using SWI18 = RegisterMask<SWIER1, (0x1u << 0x12u)>; + using SWI19 = RegisterMask<SWIER1, (0x1u << 0x13u)>; + using SWI20 = RegisterMask<SWIER1, (0x1u << 0x14u)>; + using SWI21 = RegisterMask<SWIER1, (0x1u << 0x15u)>; + }; + struct RPR1 : public MemRegister<uint32_t, 0x4002180c> { + using RPIF0 = RegisterMask<RPR1, (0x1u << 0x0u)>; + using RPIF1 = RegisterMask<RPR1, (0x1u << 0x1u)>; + using RPIF2 = RegisterMask<RPR1, (0x1u << 0x2u)>; + using RPIF3 = RegisterMask<RPR1, (0x1u << 0x3u)>; + using RPIF4 = RegisterMask<RPR1, (0x1u << 0x4u)>; + using RPIF5 = RegisterMask<RPR1, (0x1u << 0x5u)>; + using RPIF6 = RegisterMask<RPR1, (0x1u << 0x6u)>; + using RPIF7 = RegisterMask<RPR1, (0x1u << 0x7u)>; + using RPIF8 = RegisterMask<RPR1, (0x1u << 0x8u)>; + using RPIF9 = RegisterMask<RPR1, (0x1u << 0x9u)>; + using RPIF10 = RegisterMask<RPR1, (0x1u << 0xau)>; + using RPIF11 = RegisterMask<RPR1, (0x1u << 0xbu)>; + using RPIF12 = RegisterMask<RPR1, (0x1u << 0xcu)>; + using RPIF13 = RegisterMask<RPR1, (0x1u << 0xdu)>; + using RPIF14 = RegisterMask<RPR1, (0x1u << 0xeu)>; + using RPIF15 = RegisterMask<RPR1, (0x1u << 0xfu)>; + using RPIF16 = RegisterMask<RPR1, (0x1u << 0x10u)>; + using RPIF17 = RegisterMask<RPR1, (0x1u << 0x11u)>; + using RPIF18 = RegisterMask<RPR1, (0x1u << 0x12u)>; + using RPIF19 = RegisterMask<RPR1, (0x1u << 0x13u)>; + using RPIF20 = RegisterMask<RPR1, (0x1u << 0x14u)>; + using RPIF21 = RegisterMask<RPR1, (0x1u << 0x15u)>; + }; + struct FPR1 : public MemRegister<uint32_t, 0x40021810> { + using FPIF0 = RegisterMask<FPR1, (0x1u << 0x0u)>; + using FPIF1 = RegisterMask<FPR1, (0x1u << 0x1u)>; + using FPIF2 = RegisterMask<FPR1, (0x1u << 0x2u)>; + using FPIF3 = RegisterMask<FPR1, (0x1u << 0x3u)>; + using FPIF4 = RegisterMask<FPR1, (0x1u << 0x4u)>; + using FPIF5 = RegisterMask<FPR1, (0x1u << 0x5u)>; + using FPIF6 = RegisterMask<FPR1, (0x1u << 0x6u)>; + using FPIF7 = RegisterMask<FPR1, (0x1u << 0x7u)>; + using FPIF8 = RegisterMask<FPR1, (0x1u << 0x8u)>; + using FPIF9 = RegisterMask<FPR1, (0x1u << 0x9u)>; + using FPIF10 = RegisterMask<FPR1, (0x1u << 0xau)>; + using FPIF11 = RegisterMask<FPR1, (0x1u << 0xbu)>; + using FPIF12 = RegisterMask<FPR1, (0x1u << 0xcu)>; + using FPIF13 = RegisterMask<FPR1, (0x1u << 0xdu)>; + using FPIF14 = RegisterMask<FPR1, (0x1u << 0xeu)>; + using FPIF15 = RegisterMask<FPR1, (0x1u << 0xfu)>; + using FPIF16 = RegisterMask<FPR1, (0x1u << 0x10u)>; + using FPIF17 = RegisterMask<FPR1, (0x1u << 0x11u)>; + using FPIF18 = RegisterMask<FPR1, (0x1u << 0x12u)>; + using FPIF19 = RegisterMask<FPR1, (0x1u << 0x13u)>; + using FPIF20 = RegisterMask<FPR1, (0x1u << 0x14u)>; + using FPIF21 = RegisterMask<FPR1, (0x1u << 0x15u)>; + }; + struct EXTICR1 : public MemRegister<uint32_t, 0x40021860> { + using EXTI0 = RegisterMask<EXTICR1, (0xffu << 0x0u)>; + using EXTI1 = RegisterMask<EXTICR1, (0xffu << 0x8u)>; + using EXTI2 = RegisterMask<EXTICR1, (0xffu << 0x10u)>; + using EXTI3 = RegisterMask<EXTICR1, (0xffu << 0x18u)>; + }; + struct EXTICR2 : public MemRegister<uint32_t, 0x40021864> { + using EXTI4 = RegisterMask<EXTICR2, (0xffu << 0x0u)>; + using EXTI5 = RegisterMask<EXTICR2, (0xffu << 0x8u)>; + using EXTI6 = RegisterMask<EXTICR2, (0xffu << 0x10u)>; + using EXTI7 = RegisterMask<EXTICR2, (0xffu << 0x18u)>; + }; + struct EXTICR3 : public MemRegister<uint32_t, 0x40021868> { + using EXTI8 = RegisterMask<EXTICR3, (0xffu << 0x0u)>; + using EXTI9 = RegisterMask<EXTICR3, (0xffu << 0x8u)>; + using EXTI10 = RegisterMask<EXTICR3, (0xffu << 0x10u)>; + using EXTI11 = RegisterMask<EXTICR3, (0xffu << 0x18u)>; + }; + struct EXTICR4 : public MemRegister<uint32_t, 0x4002186c> { + using EXTI12 = RegisterMask<EXTICR4, (0xffu << 0x0u)>; + using EXTI13 = RegisterMask<EXTICR4, (0xffu << 0x8u)>; + using EXTI14 = RegisterMask<EXTICR4, (0xffu << 0x10u)>; + using EXTI15 = RegisterMask<EXTICR4, (0xffu << 0x18u)>; + }; + struct IMR1 : public MemRegister<uint32_t, 0x40021880> { + using IM0 = RegisterMask<IMR1, (0x1u << 0x0u)>; + using IM1 = RegisterMask<IMR1, (0x1u << 0x1u)>; + using IM2 = RegisterMask<IMR1, (0x1u << 0x2u)>; + using IM3 = RegisterMask<IMR1, (0x1u << 0x3u)>; + using IM4 = RegisterMask<IMR1, (0x1u << 0x4u)>; + using IM5 = RegisterMask<IMR1, (0x1u << 0x5u)>; + using IM6 = RegisterMask<IMR1, (0x1u << 0x6u)>; + using IM7 = RegisterMask<IMR1, (0x1u << 0x7u)>; + using IM8 = RegisterMask<IMR1, (0x1u << 0x8u)>; + using IM9 = RegisterMask<IMR1, (0x1u << 0x9u)>; + using IM10 = RegisterMask<IMR1, (0x1u << 0xau)>; + using IM11 = RegisterMask<IMR1, (0x1u << 0xbu)>; + using IM12 = RegisterMask<IMR1, (0x1u << 0xcu)>; + using IM13 = RegisterMask<IMR1, (0x1u << 0xdu)>; + using IM14 = RegisterMask<IMR1, (0x1u << 0xeu)>; + using IM15 = RegisterMask<IMR1, (0x1u << 0xfu)>; + using IM16 = RegisterMask<IMR1, (0x1u << 0x10u)>; + using IM17 = RegisterMask<IMR1, (0x1u << 0x11u)>; + using IM18 = RegisterMask<IMR1, (0x1u << 0x12u)>; + using IM19 = RegisterMask<IMR1, (0x1u << 0x13u)>; + using IM20 = RegisterMask<IMR1, (0x1u << 0x14u)>; + using IM21 = RegisterMask<IMR1, (0x1u << 0x15u)>; + using IM22 = RegisterMask<IMR1, (0x1u << 0x16u)>; + using IM23 = RegisterMask<IMR1, (0x1u << 0x17u)>; + using IM24 = RegisterMask<IMR1, (0x1u << 0x18u)>; + using IM25 = RegisterMask<IMR1, (0x1u << 0x19u)>; + using IM26 = RegisterMask<IMR1, (0x1u << 0x1au)>; + using IM27 = RegisterMask<IMR1, (0x1u << 0x1bu)>; + using IM28 = RegisterMask<IMR1, (0x1u << 0x1cu)>; + using IM29 = RegisterMask<IMR1, (0x1u << 0x1du)>; + using IM30 = RegisterMask<IMR1, (0x1u << 0x1eu)>; + using IM31 = RegisterMask<IMR1, (0x1u << 0x1fu)>; + }; + struct EMR1 : public MemRegister<uint32_t, 0x40021884> { + using EM0 = RegisterMask<EMR1, (0x1u << 0x0u)>; + using EM1 = RegisterMask<EMR1, (0x1u << 0x1u)>; + using EM2 = RegisterMask<EMR1, (0x1u << 0x2u)>; + using EM3 = RegisterMask<EMR1, (0x1u << 0x3u)>; + using EM4 = RegisterMask<EMR1, (0x1u << 0x4u)>; + using EM5 = RegisterMask<EMR1, (0x1u << 0x5u)>; + using EM6 = RegisterMask<EMR1, (0x1u << 0x6u)>; + using EM7 = RegisterMask<EMR1, (0x1u << 0x7u)>; + using EM8 = RegisterMask<EMR1, (0x1u << 0x8u)>; + using EM9 = RegisterMask<EMR1, (0x1u << 0x9u)>; + using EM10 = RegisterMask<EMR1, (0x1u << 0xau)>; + using EM11 = RegisterMask<EMR1, (0x1u << 0xbu)>; + using EM12 = RegisterMask<EMR1, (0x1u << 0xcu)>; + using EM13 = RegisterMask<EMR1, (0x1u << 0xdu)>; + using EM14 = RegisterMask<EMR1, (0x1u << 0xeu)>; + using EM15 = RegisterMask<EMR1, (0x1u << 0xfu)>; + using EM16 = RegisterMask<EMR1, (0x1u << 0x10u)>; + using EM17 = RegisterMask<EMR1, (0x1u << 0x11u)>; + using EM18 = RegisterMask<EMR1, (0x1u << 0x12u)>; + using EM19 = RegisterMask<EMR1, (0x1u << 0x13u)>; + using EM20 = RegisterMask<EMR1, (0x1u << 0x14u)>; + using EM21 = RegisterMask<EMR1, (0x1u << 0x15u)>; + using EM22 = RegisterMask<EMR1, (0x1u << 0x16u)>; + using EM23 = RegisterMask<EMR1, (0x1u << 0x17u)>; + using EM24 = RegisterMask<EMR1, (0x1u << 0x18u)>; + using EM25 = RegisterMask<EMR1, (0x1u << 0x19u)>; + using EM26 = RegisterMask<EMR1, (0x1u << 0x1au)>; + using EM27 = RegisterMask<EMR1, (0x1u << 0x1bu)>; + using EM28 = RegisterMask<EMR1, (0x1u << 0x1cu)>; + using EM29 = RegisterMask<EMR1, (0x1u << 0x1du)>; + using EM30 = RegisterMask<EMR1, (0x1u << 0x1eu)>; + using EM31 = RegisterMask<EMR1, (0x1u << 0x1fu)>; + }; + struct IMR2 : public MemRegister<uint32_t, 0x40021890> { + using IM32 = RegisterMask<IMR2, (0x1u << 0x0u)>; + using IM33 = RegisterMask<IMR2, (0x1u << 0x1u)>; + using IM34 = RegisterMask<IMR2, (0x1u << 0x2u)>; + using IM35 = RegisterMask<IMR2, (0x1u << 0x3u)>; + using IM36 = RegisterMask<IMR2, (0x1u << 0x4u)>; + using IM37 = RegisterMask<IMR2, (0x1u << 0x5u)>; + }; + struct EMR2 : public MemRegister<uint32_t, 0x40021894> { + using EM32 = RegisterMask<EMR2, (0x1u << 0x0u)>; + using EM33 = RegisterMask<EMR2, (0x1u << 0x1u)>; + using EM34 = RegisterMask<EMR2, (0x1u << 0x2u)>; + using EM35 = RegisterMask<EMR2, (0x1u << 0x3u)>; + using EM36 = RegisterMask<EMR2, (0x1u << 0x4u)>; + using EM37 = RegisterMask<EMR2, (0x1u << 0x5u)>; + }; + using ALL = RegisterGroup<RTSR1, FTSR1, SWIER1, RPR1, FPR1, EXTICR1, EXTICR2, EXTICR3, EXTICR4, IMR1, EMR1, IMR2, EMR2>; + } + namespace FLASH { + struct ACR : public MemRegister<uint32_t, 0x40022000> { + using LATENCY = RegisterMask<ACR, (0x7u << 0x0u)>; + using PRFTEN = RegisterMask<ACR, (0x1u << 0x8u)>; + using ICEN = RegisterMask<ACR, (0x1u << 0x9u)>; + using ICRST = RegisterMask<ACR, (0x1u << 0xbu)>; + using EMPTY = RegisterMask<ACR, (0x1u << 0x10u)>; + using DBG_SWEN = RegisterMask<ACR, (0x1u << 0x12u)>; + }; + struct KEYR : public MemRegister<uint32_t, 0x40022008> { + using KEY = RegisterMask<KEYR, (0x0u << 0x0u)>; + }; + struct OPTKEYR : public MemRegister<uint32_t, 0x4002200c> { + using OPTKEY = RegisterMask<OPTKEYR, (0x0u << 0x0u)>; + }; + struct SR : public MemRegister<uint32_t, 0x40022010> { + using EOP = RegisterMask<SR, (0x1u << 0x0u)>; + using OPERR = RegisterMask<SR, (0x1u << 0x1u)>; + using PROGERR = RegisterMask<SR, (0x1u << 0x3u)>; + using WRPERR = RegisterMask<SR, (0x1u << 0x4u)>; + using PGAERR = RegisterMask<SR, (0x1u << 0x5u)>; + using SIZERR = RegisterMask<SR, (0x1u << 0x6u)>; + using PGSERR = RegisterMask<SR, (0x1u << 0x7u)>; + using MISSERR = RegisterMask<SR, (0x1u << 0x8u)>; + using FASTERR = RegisterMask<SR, (0x1u << 0x9u)>; + using RDERR = RegisterMask<SR, (0x1u << 0xeu)>; + using OPTVERR = RegisterMask<SR, (0x1u << 0xfu)>; + using BSY1 = RegisterMask<SR, (0x1u << 0x10u)>; + using CFGBSY = RegisterMask<SR, (0x1u << 0x12u)>; + }; + struct CR : public MemRegister<uint32_t, 0x40022014> { + using PG = RegisterMask<CR, (0x1u << 0x0u)>; + using PER = RegisterMask<CR, (0x1u << 0x1u)>; + using MER1 = RegisterMask<CR, (0x1u << 0x2u)>; + using PNB = RegisterMask<CR, (0x7fu << 0x3u)>; + using STRT = RegisterMask<CR, (0x1u << 0x10u)>; + using OPTSTRT = RegisterMask<CR, (0x1u << 0x11u)>; + using FSTPG = RegisterMask<CR, (0x1u << 0x12u)>; + using EOPIE = RegisterMask<CR, (0x1u << 0x18u)>; + using ERRIE = RegisterMask<CR, (0x1u << 0x19u)>; + using RDERRIE = RegisterMask<CR, (0x1u << 0x1au)>; + using OBL_LAUNCH = RegisterMask<CR, (0x1u << 0x1bu)>; + using SEC_PROT = RegisterMask<CR, (0x1u << 0x1cu)>; + using OPTLOCK = RegisterMask<CR, (0x1u << 0x1eu)>; + using LOCK = RegisterMask<CR, (0x1u << 0x1fu)>; + }; + struct ECCR : public MemRegister<uint32_t, 0x40022018> { + using ADDR_ECC = RegisterMask<ECCR, (0x3fffu << 0x0u)>; + using SYSF_ECC = RegisterMask<ECCR, (0x1u << 0x14u)>; + using ECCCIE = RegisterMask<ECCR, (0x1u << 0x18u)>; + using ECCC = RegisterMask<ECCR, (0x1u << 0x1eu)>; + using ECCD = RegisterMask<ECCR, (0x1u << 0x1fu)>; + }; + struct OPTR : public MemRegister<uint32_t, 0x40022020> { + using RDP = RegisterMask<OPTR, (0xffu << 0x0u)>; + using BORR_LEV = RegisterMask<OPTR, (0x7u << 0x8u)>; + using NRST_STOP = RegisterMask<OPTR, (0x1u << 0xdu)>; + using NRST_STDBY = RegisterMask<OPTR, (0x1u << 0xeu)>; + using NRST_SHDW = RegisterMask<OPTR, (0x1u << 0xfu)>; + using IWDG_SW = RegisterMask<OPTR, (0x1u << 0x10u)>; + using IWDG_STOP = RegisterMask<OPTR, (0x1u << 0x11u)>; + using IWDG_STDBY = RegisterMask<OPTR, (0x1u << 0x12u)>; + using WWDG_SW = RegisterMask<OPTR, (0x1u << 0x13u)>; + using BDRST = RegisterMask<OPTR, (0x1u << 0x15u)>; + using RAM_PARITY_CHECK = RegisterMask<OPTR, (0x1u << 0x16u)>; + using BKPSRAM_HW_ERASE_DISABLE = RegisterMask<OPTR, (0x1u << 0x17u)>; + using NBOOT_SEL = RegisterMask<OPTR, (0x1u << 0x18u)>; + using NBOOT1 = RegisterMask<OPTR, (0x1u << 0x19u)>; + using NBOOT0 = RegisterMask<OPTR, (0x1u << 0x1au)>; + using NRST_MODE = RegisterMask<OPTR, (0x3u << 0x1bu)>; + using IRHEN = RegisterMask<OPTR, (0x1u << 0x1du)>; + }; + struct WRP1AR : public MemRegister<uint32_t, 0x4002202c> { + using WRP1A_STRT = RegisterMask<WRP1AR, (0x7fu << 0x0u)>; + using WRP1A_END = RegisterMask<WRP1AR, (0x7fu << 0x10u)>; + }; + struct WRP1BR : public MemRegister<uint32_t, 0x40022030> { + using WRP1B_STRT = RegisterMask<WRP1BR, (0x7fu << 0x0u)>; + using WRP1B_END = RegisterMask<WRP1BR, (0x7fu << 0x10u)>; + }; + struct SECR : public MemRegister<uint32_t, 0x40022080> { + using HDP1_PEND = RegisterMask<SECR, (0x7fu << 0x0u)>; + using BOOT_LOCK = RegisterMask<SECR, (0x1u << 0x10u)>; + using HDP1EN = RegisterMask<SECR, (0xffu << 0x18u)>; + }; + using ALL = RegisterGroup<ACR, KEYR, OPTKEYR, SR, CR, ECCR, OPTR, WRP1AR, WRP1BR, SECR>; + } + namespace GPIOA { + struct MODER : public MemRegister<uint32_t, 0x50000000> { + using MODE0 = RegisterMask<MODER, (0x3u << 0x0u)>; + using MODE1 = RegisterMask<MODER, (0x3u << 0x2u)>; + using MODE2 = RegisterMask<MODER, (0x3u << 0x4u)>; + using MODE3 = RegisterMask<MODER, (0x3u << 0x6u)>; + using MODE4 = RegisterMask<MODER, (0x3u << 0x8u)>; + using MODE5 = RegisterMask<MODER, (0x3u << 0xau)>; + using MODE6 = RegisterMask<MODER, (0x3u << 0xcu)>; + using MODE7 = RegisterMask<MODER, (0x3u << 0xeu)>; + using MODE8 = RegisterMask<MODER, (0x3u << 0x10u)>; + using MODE9 = RegisterMask<MODER, (0x3u << 0x12u)>; + using MODE10 = RegisterMask<MODER, (0x3u << 0x14u)>; + using MODE11 = RegisterMask<MODER, (0x3u << 0x16u)>; + using MODE12 = RegisterMask<MODER, (0x3u << 0x18u)>; + using MODE13 = RegisterMask<MODER, (0x3u << 0x1au)>; + using MODE14 = RegisterMask<MODER, (0x3u << 0x1cu)>; + using MODE15 = RegisterMask<MODER, (0x3u << 0x1eu)>; + }; + struct OTYPER : public MemRegister<uint32_t, 0x50000004> { + using OT0 = RegisterMask<OTYPER, (0x1u << 0x0u)>; + using OT1 = RegisterMask<OTYPER, (0x1u << 0x1u)>; + using OT2 = RegisterMask<OTYPER, (0x1u << 0x2u)>; + using OT3 = RegisterMask<OTYPER, (0x1u << 0x3u)>; + using OT4 = RegisterMask<OTYPER, (0x1u << 0x4u)>; + using OT5 = RegisterMask<OTYPER, (0x1u << 0x5u)>; + using OT6 = RegisterMask<OTYPER, (0x1u << 0x6u)>; + using OT7 = RegisterMask<OTYPER, (0x1u << 0x7u)>; + using OT8 = RegisterMask<OTYPER, (0x1u << 0x8u)>; + using OT9 = RegisterMask<OTYPER, (0x1u << 0x9u)>; + using OT10 = RegisterMask<OTYPER, (0x1u << 0xau)>; + using OT11 = RegisterMask<OTYPER, (0x1u << 0xbu)>; + using OT12 = RegisterMask<OTYPER, (0x1u << 0xcu)>; + using OT13 = RegisterMask<OTYPER, (0x1u << 0xdu)>; + using OT14 = RegisterMask<OTYPER, (0x1u << 0xeu)>; + using OT15 = RegisterMask<OTYPER, (0x1u << 0xfu)>; + }; + struct OSPEEDR : public MemRegister<uint32_t, 0x50000008> { + using OSPEED0 = RegisterMask<OSPEEDR, (0x3u << 0x0u)>; + using OSPEED1 = RegisterMask<OSPEEDR, (0x3u << 0x2u)>; + using OSPEED2 = RegisterMask<OSPEEDR, (0x3u << 0x4u)>; + using OSPEED3 = RegisterMask<OSPEEDR, (0x3u << 0x6u)>; + using OSPEED4 = RegisterMask<OSPEEDR, (0x3u << 0x8u)>; + using OSPEED5 = RegisterMask<OSPEEDR, (0x3u << 0xau)>; + using OSPEED6 = RegisterMask<OSPEEDR, (0x3u << 0xcu)>; + using OSPEED7 = RegisterMask<OSPEEDR, (0x3u << 0xeu)>; + using OSPEED8 = RegisterMask<OSPEEDR, (0x3u << 0x10u)>; + using OSPEED9 = RegisterMask<OSPEEDR, (0x3u << 0x12u)>; + using OSPEED10 = RegisterMask<OSPEEDR, (0x3u << 0x14u)>; + using OSPEED11 = RegisterMask<OSPEEDR, (0x3u << 0x16u)>; + using OSPEED12 = RegisterMask<OSPEEDR, (0x3u << 0x18u)>; + using OSPEED13 = RegisterMask<OSPEEDR, (0x3u << 0x1au)>; + using OSPEED14 = RegisterMask<OSPEEDR, (0x3u << 0x1cu)>; + using OSPEED15 = RegisterMask<OSPEEDR, (0x3u << 0x1eu)>; + }; + struct PUPDR : public MemRegister<uint32_t, 0x5000000c> { + using PUPD0 = RegisterMask<PUPDR, (0x3u << 0x0u)>; + using PUPD1 = RegisterMask<PUPDR, (0x3u << 0x2u)>; + using PUPD2 = RegisterMask<PUPDR, (0x3u << 0x4u)>; + using PUPD3 = RegisterMask<PUPDR, (0x3u << 0x6u)>; + using PUPD4 = RegisterMask<PUPDR, (0x3u << 0x8u)>; + using PUPD5 = RegisterMask<PUPDR, (0x3u << 0xau)>; + using PUPD6 = RegisterMask<PUPDR, (0x3u << 0xcu)>; + using PUPD7 = RegisterMask<PUPDR, (0x3u << 0xeu)>; + using PUPD8 = RegisterMask<PUPDR, (0x3u << 0x10u)>; + using PUPD9 = RegisterMask<PUPDR, (0x3u << 0x12u)>; + using PUPD10 = RegisterMask<PUPDR, (0x3u << 0x14u)>; + using PUPD11 = RegisterMask<PUPDR, (0x3u << 0x16u)>; + using PUPD12 = RegisterMask<PUPDR, (0x3u << 0x18u)>; + using PUPD13 = RegisterMask<PUPDR, (0x3u << 0x1au)>; + using PUPD14 = RegisterMask<PUPDR, (0x3u << 0x1cu)>; + using PUPD15 = RegisterMask<PUPDR, (0x3u << 0x1eu)>; + }; + struct IDR : public MemRegister<uint32_t, 0x50000010> { + using ID0 = RegisterMask<IDR, (0x1u << 0x0u)>; + using ID1 = RegisterMask<IDR, (0x1u << 0x1u)>; + using ID2 = RegisterMask<IDR, (0x1u << 0x2u)>; + using ID3 = RegisterMask<IDR, (0x1u << 0x3u)>; + using ID4 = RegisterMask<IDR, (0x1u << 0x4u)>; + using ID5 = RegisterMask<IDR, (0x1u << 0x5u)>; + using ID6 = RegisterMask<IDR, (0x1u << 0x6u)>; + using ID7 = RegisterMask<IDR, (0x1u << 0x7u)>; + using ID8 = RegisterMask<IDR, (0x1u << 0x8u)>; + using ID9 = RegisterMask<IDR, (0x1u << 0x9u)>; + using ID10 = RegisterMask<IDR, (0x1u << 0xau)>; + using ID11 = RegisterMask<IDR, (0x1u << 0xbu)>; + using ID12 = RegisterMask<IDR, (0x1u << 0xcu)>; + using ID13 = RegisterMask<IDR, (0x1u << 0xdu)>; + using ID14 = RegisterMask<IDR, (0x1u << 0xeu)>; + using ID15 = RegisterMask<IDR, (0x1u << 0xfu)>; + }; + struct ODR : public MemRegister<uint32_t, 0x50000014> { + using OD0 = RegisterMask<ODR, (0x1u << 0x0u)>; + using OD1 = RegisterMask<ODR, (0x1u << 0x1u)>; + using OD2 = RegisterMask<ODR, (0x1u << 0x2u)>; + using OD3 = RegisterMask<ODR, (0x1u << 0x3u)>; + using OD4 = RegisterMask<ODR, (0x1u << 0x4u)>; + using OD5 = RegisterMask<ODR, (0x1u << 0x5u)>; + using OD6 = RegisterMask<ODR, (0x1u << 0x6u)>; + using OD7 = RegisterMask<ODR, (0x1u << 0x7u)>; + using OD8 = RegisterMask<ODR, (0x1u << 0x8u)>; + using OD9 = RegisterMask<ODR, (0x1u << 0x9u)>; + using OD10 = RegisterMask<ODR, (0x1u << 0xau)>; + using OD11 = RegisterMask<ODR, (0x1u << 0xbu)>; + using OD12 = RegisterMask<ODR, (0x1u << 0xcu)>; + using OD13 = RegisterMask<ODR, (0x1u << 0xdu)>; + using OD14 = RegisterMask<ODR, (0x1u << 0xeu)>; + using OD15 = RegisterMask<ODR, (0x1u << 0xfu)>; + }; + struct BSRR : public MemRegister<uint32_t, 0x50000018> { + using BS0 = RegisterMask<BSRR, (0x1u << 0x0u)>; + using BS1 = RegisterMask<BSRR, (0x1u << 0x1u)>; + using BS2 = RegisterMask<BSRR, (0x1u << 0x2u)>; + using BS3 = RegisterMask<BSRR, (0x1u << 0x3u)>; + using BS4 = RegisterMask<BSRR, (0x1u << 0x4u)>; + using BS5 = RegisterMask<BSRR, (0x1u << 0x5u)>; + using BS6 = RegisterMask<BSRR, (0x1u << 0x6u)>; + using BS7 = RegisterMask<BSRR, (0x1u << 0x7u)>; + using BS8 = RegisterMask<BSRR, (0x1u << 0x8u)>; + using BS9 = RegisterMask<BSRR, (0x1u << 0x9u)>; + using BS10 = RegisterMask<BSRR, (0x1u << 0xau)>; + using BS11 = RegisterMask<BSRR, (0x1u << 0xbu)>; + using BS12 = RegisterMask<BSRR, (0x1u << 0xcu)>; + using BS13 = RegisterMask<BSRR, (0x1u << 0xdu)>; + using BS14 = RegisterMask<BSRR, (0x1u << 0xeu)>; + using BS15 = RegisterMask<BSRR, (0x1u << 0xfu)>; + using BR0 = RegisterMask<BSRR, (0x1u << 0x10u)>; + using BR1 = RegisterMask<BSRR, (0x1u << 0x11u)>; + using BR2 = RegisterMask<BSRR, (0x1u << 0x12u)>; + using BR3 = RegisterMask<BSRR, (0x1u << 0x13u)>; + using BR4 = RegisterMask<BSRR, (0x1u << 0x14u)>; + using BR5 = RegisterMask<BSRR, (0x1u << 0x15u)>; + using BR6 = RegisterMask<BSRR, (0x1u << 0x16u)>; + using BR7 = RegisterMask<BSRR, (0x1u << 0x17u)>; + using BR8 = RegisterMask<BSRR, (0x1u << 0x18u)>; + using BR9 = RegisterMask<BSRR, (0x1u << 0x19u)>; + using BR10 = RegisterMask<BSRR, (0x1u << 0x1au)>; + using BR11 = RegisterMask<BSRR, (0x1u << 0x1bu)>; + using BR12 = RegisterMask<BSRR, (0x1u << 0x1cu)>; + using BR13 = RegisterMask<BSRR, (0x1u << 0x1du)>; + using BR14 = RegisterMask<BSRR, (0x1u << 0x1eu)>; + using BR15 = RegisterMask<BSRR, (0x1u << 0x1fu)>; + }; + struct LCKR : public MemRegister<uint32_t, 0x5000001c> { + using LCK0 = RegisterMask<LCKR, (0x1u << 0x0u)>; + using LCK1 = RegisterMask<LCKR, (0x1u << 0x1u)>; + using LCK2 = RegisterMask<LCKR, (0x1u << 0x2u)>; + using LCK3 = RegisterMask<LCKR, (0x1u << 0x3u)>; + using LCK4 = RegisterMask<LCKR, (0x1u << 0x4u)>; + using LCK5 = RegisterMask<LCKR, (0x1u << 0x5u)>; + using LCK6 = RegisterMask<LCKR, (0x1u << 0x6u)>; + using LCK7 = RegisterMask<LCKR, (0x1u << 0x7u)>; + using LCK8 = RegisterMask<LCKR, (0x1u << 0x8u)>; + using LCK9 = RegisterMask<LCKR, (0x1u << 0x9u)>; + using LCK10 = RegisterMask<LCKR, (0x1u << 0xau)>; + using LCK11 = RegisterMask<LCKR, (0x1u << 0xbu)>; + using LCK12 = RegisterMask<LCKR, (0x1u << 0xcu)>; + using LCK13 = RegisterMask<LCKR, (0x1u << 0xdu)>; + using LCK14 = RegisterMask<LCKR, (0x1u << 0xeu)>; + using LCK15 = RegisterMask<LCKR, (0x1u << 0xfu)>; + using LCKK = RegisterMask<LCKR, (0x1u << 0x10u)>; + }; + struct AFRL : public MemRegister<uint32_t, 0x50000020> { + using AFSEL0 = RegisterMask<AFRL, (0xfu << 0x0u)>; + using AFSEL1 = RegisterMask<AFRL, (0xfu << 0x4u)>; + using AFSEL2 = RegisterMask<AFRL, (0xfu << 0x8u)>; + using AFSEL3 = RegisterMask<AFRL, (0xfu << 0xcu)>; + using AFSEL4 = RegisterMask<AFRL, (0xfu << 0x10u)>; + using AFSEL5 = RegisterMask<AFRL, (0xfu << 0x14u)>; + using AFSEL6 = RegisterMask<AFRL, (0xfu << 0x18u)>; + using AFSEL7 = RegisterMask<AFRL, (0xfu << 0x1cu)>; + }; + struct AFRH : public MemRegister<uint32_t, 0x50000024> { + using AFSEL8 = RegisterMask<AFRH, (0xfu << 0x0u)>; + using AFSEL9 = RegisterMask<AFRH, (0xfu << 0x4u)>; + using AFSEL10 = RegisterMask<AFRH, (0xfu << 0x8u)>; + using AFSEL11 = RegisterMask<AFRH, (0xfu << 0xcu)>; + using AFSEL12 = RegisterMask<AFRH, (0xfu << 0x10u)>; + using AFSEL13 = RegisterMask<AFRH, (0xfu << 0x14u)>; + using AFSEL14 = RegisterMask<AFRH, (0xfu << 0x18u)>; + using AFSEL15 = RegisterMask<AFRH, (0xfu << 0x1cu)>; + }; + struct BRR : public MemRegister<uint32_t, 0x50000028> { + using BR0 = RegisterMask<BRR, (0x1u << 0x0u)>; + using BR1 = RegisterMask<BRR, (0x1u << 0x1u)>; + using BR2 = RegisterMask<BRR, (0x1u << 0x2u)>; + using BR3 = RegisterMask<BRR, (0x1u << 0x3u)>; + using BR4 = RegisterMask<BRR, (0x1u << 0x4u)>; + using BR5 = RegisterMask<BRR, (0x1u << 0x5u)>; + using BR6 = RegisterMask<BRR, (0x1u << 0x6u)>; + using BR7 = RegisterMask<BRR, (0x1u << 0x7u)>; + using BR8 = RegisterMask<BRR, (0x1u << 0x8u)>; + using BR9 = RegisterMask<BRR, (0x1u << 0x9u)>; + using BR10 = RegisterMask<BRR, (0x1u << 0xau)>; + using BR11 = RegisterMask<BRR, (0x1u << 0xbu)>; + using BR12 = RegisterMask<BRR, (0x1u << 0xcu)>; + using BR13 = RegisterMask<BRR, (0x1u << 0xdu)>; + using BR14 = RegisterMask<BRR, (0x1u << 0xeu)>; + using BR15 = RegisterMask<BRR, (0x1u << 0xfu)>; + }; + using ALL = RegisterGroup<MODER, OTYPER, OSPEEDR, PUPDR, IDR, ODR, BSRR, LCKR, AFRL, AFRH, BRR>; + } + namespace GPIOB { + struct MODER : public MemRegister<uint32_t, 0x50000400> { + using MODE0 = RegisterMask<MODER, (0x3u << 0x0u)>; + using MODE1 = RegisterMask<MODER, (0x3u << 0x2u)>; + using MODE2 = RegisterMask<MODER, (0x3u << 0x4u)>; + using MODE3 = RegisterMask<MODER, (0x3u << 0x6u)>; + using MODE4 = RegisterMask<MODER, (0x3u << 0x8u)>; + using MODE5 = RegisterMask<MODER, (0x3u << 0xau)>; + using MODE6 = RegisterMask<MODER, (0x3u << 0xcu)>; + using MODE7 = RegisterMask<MODER, (0x3u << 0xeu)>; + using MODE8 = RegisterMask<MODER, (0x3u << 0x10u)>; + using MODE9 = RegisterMask<MODER, (0x3u << 0x12u)>; + using MODE10 = RegisterMask<MODER, (0x3u << 0x14u)>; + using MODE11 = RegisterMask<MODER, (0x3u << 0x16u)>; + using MODE12 = RegisterMask<MODER, (0x3u << 0x18u)>; + using MODE13 = RegisterMask<MODER, (0x3u << 0x1au)>; + using MODE14 = RegisterMask<MODER, (0x3u << 0x1cu)>; + using MODE15 = RegisterMask<MODER, (0x3u << 0x1eu)>; + }; + struct OTYPER : public MemRegister<uint32_t, 0x50000404> { + using OT0 = RegisterMask<OTYPER, (0x1u << 0x0u)>; + using OT1 = RegisterMask<OTYPER, (0x1u << 0x1u)>; + using OT2 = RegisterMask<OTYPER, (0x1u << 0x2u)>; + using OT3 = RegisterMask<OTYPER, (0x1u << 0x3u)>; + using OT4 = RegisterMask<OTYPER, (0x1u << 0x4u)>; + using OT5 = RegisterMask<OTYPER, (0x1u << 0x5u)>; + using OT6 = RegisterMask<OTYPER, (0x1u << 0x6u)>; + using OT7 = RegisterMask<OTYPER, (0x1u << 0x7u)>; + using OT8 = RegisterMask<OTYPER, (0x1u << 0x8u)>; + using OT9 = RegisterMask<OTYPER, (0x1u << 0x9u)>; + using OT10 = RegisterMask<OTYPER, (0x1u << 0xau)>; + using OT11 = RegisterMask<OTYPER, (0x1u << 0xbu)>; + using OT12 = RegisterMask<OTYPER, (0x1u << 0xcu)>; + using OT13 = RegisterMask<OTYPER, (0x1u << 0xdu)>; + using OT14 = RegisterMask<OTYPER, (0x1u << 0xeu)>; + using OT15 = RegisterMask<OTYPER, (0x1u << 0xfu)>; + }; + struct OSPEEDR : public MemRegister<uint32_t, 0x50000408> { + using OSPEED0 = RegisterMask<OSPEEDR, (0x3u << 0x0u)>; + using OSPEED1 = RegisterMask<OSPEEDR, (0x3u << 0x2u)>; + using OSPEED2 = RegisterMask<OSPEEDR, (0x3u << 0x4u)>; + using OSPEED3 = RegisterMask<OSPEEDR, (0x3u << 0x6u)>; + using OSPEED4 = RegisterMask<OSPEEDR, (0x3u << 0x8u)>; + using OSPEED5 = RegisterMask<OSPEEDR, (0x3u << 0xau)>; + using OSPEED6 = RegisterMask<OSPEEDR, (0x3u << 0xcu)>; + using OSPEED7 = RegisterMask<OSPEEDR, (0x3u << 0xeu)>; + using OSPEED8 = RegisterMask<OSPEEDR, (0x3u << 0x10u)>; + using OSPEED9 = RegisterMask<OSPEEDR, (0x3u << 0x12u)>; + using OSPEED10 = RegisterMask<OSPEEDR, (0x3u << 0x14u)>; + using OSPEED11 = RegisterMask<OSPEEDR, (0x3u << 0x16u)>; + using OSPEED12 = RegisterMask<OSPEEDR, (0x3u << 0x18u)>; + using OSPEED13 = RegisterMask<OSPEEDR, (0x3u << 0x1au)>; + using OSPEED14 = RegisterMask<OSPEEDR, (0x3u << 0x1cu)>; + using OSPEED15 = RegisterMask<OSPEEDR, (0x3u << 0x1eu)>; + }; + struct PUPDR : public MemRegister<uint32_t, 0x5000040c> { + using PUPD0 = RegisterMask<PUPDR, (0x3u << 0x0u)>; + using PUPD1 = RegisterMask<PUPDR, (0x3u << 0x2u)>; + using PUPD2 = RegisterMask<PUPDR, (0x3u << 0x4u)>; + using PUPD3 = RegisterMask<PUPDR, (0x3u << 0x6u)>; + using PUPD4 = RegisterMask<PUPDR, (0x3u << 0x8u)>; + using PUPD5 = RegisterMask<PUPDR, (0x3u << 0xau)>; + using PUPD6 = RegisterMask<PUPDR, (0x3u << 0xcu)>; + using PUPD7 = RegisterMask<PUPDR, (0x3u << 0xeu)>; + using PUPD8 = RegisterMask<PUPDR, (0x3u << 0x10u)>; + using PUPD9 = RegisterMask<PUPDR, (0x3u << 0x12u)>; + using PUPD10 = RegisterMask<PUPDR, (0x3u << 0x14u)>; + using PUPD11 = RegisterMask<PUPDR, (0x3u << 0x16u)>; + using PUPD12 = RegisterMask<PUPDR, (0x3u << 0x18u)>; + using PUPD13 = RegisterMask<PUPDR, (0x3u << 0x1au)>; + using PUPD14 = RegisterMask<PUPDR, (0x3u << 0x1cu)>; + using PUPD15 = RegisterMask<PUPDR, (0x3u << 0x1eu)>; + }; + struct IDR : public MemRegister<uint32_t, 0x50000410> { + using ID0 = RegisterMask<IDR, (0x1u << 0x0u)>; + using ID1 = RegisterMask<IDR, (0x1u << 0x1u)>; + using ID2 = RegisterMask<IDR, (0x1u << 0x2u)>; + using ID3 = RegisterMask<IDR, (0x1u << 0x3u)>; + using ID4 = RegisterMask<IDR, (0x1u << 0x4u)>; + using ID5 = RegisterMask<IDR, (0x1u << 0x5u)>; + using ID6 = RegisterMask<IDR, (0x1u << 0x6u)>; + using ID7 = RegisterMask<IDR, (0x1u << 0x7u)>; + using ID8 = RegisterMask<IDR, (0x1u << 0x8u)>; + using ID9 = RegisterMask<IDR, (0x1u << 0x9u)>; + using ID10 = RegisterMask<IDR, (0x1u << 0xau)>; + using ID11 = RegisterMask<IDR, (0x1u << 0xbu)>; + using ID12 = RegisterMask<IDR, (0x1u << 0xcu)>; + using ID13 = RegisterMask<IDR, (0x1u << 0xdu)>; + using ID14 = RegisterMask<IDR, (0x1u << 0xeu)>; + using ID15 = RegisterMask<IDR, (0x1u << 0xfu)>; + }; + struct ODR : public MemRegister<uint32_t, 0x50000414> { + using OD0 = RegisterMask<ODR, (0x1u << 0x0u)>; + using OD1 = RegisterMask<ODR, (0x1u << 0x1u)>; + using OD2 = RegisterMask<ODR, (0x1u << 0x2u)>; + using OD3 = RegisterMask<ODR, (0x1u << 0x3u)>; + using OD4 = RegisterMask<ODR, (0x1u << 0x4u)>; + using OD5 = RegisterMask<ODR, (0x1u << 0x5u)>; + using OD6 = RegisterMask<ODR, (0x1u << 0x6u)>; + using OD7 = RegisterMask<ODR, (0x1u << 0x7u)>; + using OD8 = RegisterMask<ODR, (0x1u << 0x8u)>; + using OD9 = RegisterMask<ODR, (0x1u << 0x9u)>; + using OD10 = RegisterMask<ODR, (0x1u << 0xau)>; + using OD11 = RegisterMask<ODR, (0x1u << 0xbu)>; + using OD12 = RegisterMask<ODR, (0x1u << 0xcu)>; + using OD13 = RegisterMask<ODR, (0x1u << 0xdu)>; + using OD14 = RegisterMask<ODR, (0x1u << 0xeu)>; + using OD15 = RegisterMask<ODR, (0x1u << 0xfu)>; + }; + struct BSRR : public MemRegister<uint32_t, 0x50000418> { + using BS0 = RegisterMask<BSRR, (0x1u << 0x0u)>; + using BS1 = RegisterMask<BSRR, (0x1u << 0x1u)>; + using BS2 = RegisterMask<BSRR, (0x1u << 0x2u)>; + using BS3 = RegisterMask<BSRR, (0x1u << 0x3u)>; + using BS4 = RegisterMask<BSRR, (0x1u << 0x4u)>; + using BS5 = RegisterMask<BSRR, (0x1u << 0x5u)>; + using BS6 = RegisterMask<BSRR, (0x1u << 0x6u)>; + using BS7 = RegisterMask<BSRR, (0x1u << 0x7u)>; + using BS8 = RegisterMask<BSRR, (0x1u << 0x8u)>; + using BS9 = RegisterMask<BSRR, (0x1u << 0x9u)>; + using BS10 = RegisterMask<BSRR, (0x1u << 0xau)>; + using BS11 = RegisterMask<BSRR, (0x1u << 0xbu)>; + using BS12 = RegisterMask<BSRR, (0x1u << 0xcu)>; + using BS13 = RegisterMask<BSRR, (0x1u << 0xdu)>; + using BS14 = RegisterMask<BSRR, (0x1u << 0xeu)>; + using BS15 = RegisterMask<BSRR, (0x1u << 0xfu)>; + using BR0 = RegisterMask<BSRR, (0x1u << 0x10u)>; + using BR1 = RegisterMask<BSRR, (0x1u << 0x11u)>; + using BR2 = RegisterMask<BSRR, (0x1u << 0x12u)>; + using BR3 = RegisterMask<BSRR, (0x1u << 0x13u)>; + using BR4 = RegisterMask<BSRR, (0x1u << 0x14u)>; + using BR5 = RegisterMask<BSRR, (0x1u << 0x15u)>; + using BR6 = RegisterMask<BSRR, (0x1u << 0x16u)>; + using BR7 = RegisterMask<BSRR, (0x1u << 0x17u)>; + using BR8 = RegisterMask<BSRR, (0x1u << 0x18u)>; + using BR9 = RegisterMask<BSRR, (0x1u << 0x19u)>; + using BR10 = RegisterMask<BSRR, (0x1u << 0x1au)>; + using BR11 = RegisterMask<BSRR, (0x1u << 0x1bu)>; + using BR12 = RegisterMask<BSRR, (0x1u << 0x1cu)>; + using BR13 = RegisterMask<BSRR, (0x1u << 0x1du)>; + using BR14 = RegisterMask<BSRR, (0x1u << 0x1eu)>; + using BR15 = RegisterMask<BSRR, (0x1u << 0x1fu)>; + }; + struct LCKR : public MemRegister<uint32_t, 0x5000041c> { + using LCK0 = RegisterMask<LCKR, (0x1u << 0x0u)>; + using LCK1 = RegisterMask<LCKR, (0x1u << 0x1u)>; + using LCK2 = RegisterMask<LCKR, (0x1u << 0x2u)>; + using LCK3 = RegisterMask<LCKR, (0x1u << 0x3u)>; + using LCK4 = RegisterMask<LCKR, (0x1u << 0x4u)>; + using LCK5 = RegisterMask<LCKR, (0x1u << 0x5u)>; + using LCK6 = RegisterMask<LCKR, (0x1u << 0x6u)>; + using LCK7 = RegisterMask<LCKR, (0x1u << 0x7u)>; + using LCK8 = RegisterMask<LCKR, (0x1u << 0x8u)>; + using LCK9 = RegisterMask<LCKR, (0x1u << 0x9u)>; + using LCK10 = RegisterMask<LCKR, (0x1u << 0xau)>; + using LCK11 = RegisterMask<LCKR, (0x1u << 0xbu)>; + using LCK12 = RegisterMask<LCKR, (0x1u << 0xcu)>; + using LCK13 = RegisterMask<LCKR, (0x1u << 0xdu)>; + using LCK14 = RegisterMask<LCKR, (0x1u << 0xeu)>; + using LCK15 = RegisterMask<LCKR, (0x1u << 0xfu)>; + using LCKK = RegisterMask<LCKR, (0x1u << 0x10u)>; + }; + struct AFRL : public MemRegister<uint32_t, 0x50000420> { + using AFSEL0 = RegisterMask<AFRL, (0xfu << 0x0u)>; + using AFSEL1 = RegisterMask<AFRL, (0xfu << 0x4u)>; + using AFSEL2 = RegisterMask<AFRL, (0xfu << 0x8u)>; + using AFSEL3 = RegisterMask<AFRL, (0xfu << 0xcu)>; + using AFSEL4 = RegisterMask<AFRL, (0xfu << 0x10u)>; + using AFSEL5 = RegisterMask<AFRL, (0xfu << 0x14u)>; + using AFSEL6 = RegisterMask<AFRL, (0xfu << 0x18u)>; + using AFSEL7 = RegisterMask<AFRL, (0xfu << 0x1cu)>; + }; + struct AFRH : public MemRegister<uint32_t, 0x50000424> { + using AFSEL8 = RegisterMask<AFRH, (0xfu << 0x0u)>; + using AFSEL9 = RegisterMask<AFRH, (0xfu << 0x4u)>; + using AFSEL10 = RegisterMask<AFRH, (0xfu << 0x8u)>; + using AFSEL11 = RegisterMask<AFRH, (0xfu << 0xcu)>; + using AFSEL12 = RegisterMask<AFRH, (0xfu << 0x10u)>; + using AFSEL13 = RegisterMask<AFRH, (0xfu << 0x14u)>; + using AFSEL14 = RegisterMask<AFRH, (0xfu << 0x18u)>; + using AFSEL15 = RegisterMask<AFRH, (0xfu << 0x1cu)>; + }; + struct BRR : public MemRegister<uint32_t, 0x50000428> { + using BR0 = RegisterMask<BRR, (0x1u << 0x0u)>; + using BR1 = RegisterMask<BRR, (0x1u << 0x1u)>; + using BR2 = RegisterMask<BRR, (0x1u << 0x2u)>; + using BR3 = RegisterMask<BRR, (0x1u << 0x3u)>; + using BR4 = RegisterMask<BRR, (0x1u << 0x4u)>; + using BR5 = RegisterMask<BRR, (0x1u << 0x5u)>; + using BR6 = RegisterMask<BRR, (0x1u << 0x6u)>; + using BR7 = RegisterMask<BRR, (0x1u << 0x7u)>; + using BR8 = RegisterMask<BRR, (0x1u << 0x8u)>; + using BR9 = RegisterMask<BRR, (0x1u << 0x9u)>; + using BR10 = RegisterMask<BRR, (0x1u << 0xau)>; + using BR11 = RegisterMask<BRR, (0x1u << 0xbu)>; + using BR12 = RegisterMask<BRR, (0x1u << 0xcu)>; + using BR13 = RegisterMask<BRR, (0x1u << 0xdu)>; + using BR14 = RegisterMask<BRR, (0x1u << 0xeu)>; + using BR15 = RegisterMask<BRR, (0x1u << 0xfu)>; + }; + using ALL = RegisterGroup<MODER, OTYPER, OSPEEDR, PUPDR, IDR, ODR, BSRR, LCKR, AFRL, AFRH, BRR>; + } + namespace GPIOC { + struct MODER : public MemRegister<uint32_t, 0x50000800> { + using MODE0 = RegisterMask<MODER, (0x3u << 0x0u)>; + using MODE1 = RegisterMask<MODER, (0x3u << 0x2u)>; + using MODE2 = RegisterMask<MODER, (0x3u << 0x4u)>; + using MODE3 = RegisterMask<MODER, (0x3u << 0x6u)>; + using MODE4 = RegisterMask<MODER, (0x3u << 0x8u)>; + using MODE5 = RegisterMask<MODER, (0x3u << 0xau)>; + using MODE6 = RegisterMask<MODER, (0x3u << 0xcu)>; + using MODE7 = RegisterMask<MODER, (0x3u << 0xeu)>; + using MODE8 = RegisterMask<MODER, (0x3u << 0x10u)>; + using MODE9 = RegisterMask<MODER, (0x3u << 0x12u)>; + using MODE10 = RegisterMask<MODER, (0x3u << 0x14u)>; + using MODE11 = RegisterMask<MODER, (0x3u << 0x16u)>; + using MODE12 = RegisterMask<MODER, (0x3u << 0x18u)>; + using MODE13 = RegisterMask<MODER, (0x3u << 0x1au)>; + using MODE14 = RegisterMask<MODER, (0x3u << 0x1cu)>; + using MODE15 = RegisterMask<MODER, (0x3u << 0x1eu)>; + }; + struct OTYPER : public MemRegister<uint32_t, 0x50000804> { + using OT0 = RegisterMask<OTYPER, (0x1u << 0x0u)>; + using OT1 = RegisterMask<OTYPER, (0x1u << 0x1u)>; + using OT2 = RegisterMask<OTYPER, (0x1u << 0x2u)>; + using OT3 = RegisterMask<OTYPER, (0x1u << 0x3u)>; + using OT4 = RegisterMask<OTYPER, (0x1u << 0x4u)>; + using OT5 = RegisterMask<OTYPER, (0x1u << 0x5u)>; + using OT6 = RegisterMask<OTYPER, (0x1u << 0x6u)>; + using OT7 = RegisterMask<OTYPER, (0x1u << 0x7u)>; + using OT8 = RegisterMask<OTYPER, (0x1u << 0x8u)>; + using OT9 = RegisterMask<OTYPER, (0x1u << 0x9u)>; + using OT10 = RegisterMask<OTYPER, (0x1u << 0xau)>; + using OT11 = RegisterMask<OTYPER, (0x1u << 0xbu)>; + using OT12 = RegisterMask<OTYPER, (0x1u << 0xcu)>; + using OT13 = RegisterMask<OTYPER, (0x1u << 0xdu)>; + using OT14 = RegisterMask<OTYPER, (0x1u << 0xeu)>; + using OT15 = RegisterMask<OTYPER, (0x1u << 0xfu)>; + }; + struct OSPEEDR : public MemRegister<uint32_t, 0x50000808> { + using OSPEED0 = RegisterMask<OSPEEDR, (0x3u << 0x0u)>; + using OSPEED1 = RegisterMask<OSPEEDR, (0x3u << 0x2u)>; + using OSPEED2 = RegisterMask<OSPEEDR, (0x3u << 0x4u)>; + using OSPEED3 = RegisterMask<OSPEEDR, (0x3u << 0x6u)>; + using OSPEED4 = RegisterMask<OSPEEDR, (0x3u << 0x8u)>; + using OSPEED5 = RegisterMask<OSPEEDR, (0x3u << 0xau)>; + using OSPEED6 = RegisterMask<OSPEEDR, (0x3u << 0xcu)>; + using OSPEED7 = RegisterMask<OSPEEDR, (0x3u << 0xeu)>; + using OSPEED8 = RegisterMask<OSPEEDR, (0x3u << 0x10u)>; + using OSPEED9 = RegisterMask<OSPEEDR, (0x3u << 0x12u)>; + using OSPEED10 = RegisterMask<OSPEEDR, (0x3u << 0x14u)>; + using OSPEED11 = RegisterMask<OSPEEDR, (0x3u << 0x16u)>; + using OSPEED12 = RegisterMask<OSPEEDR, (0x3u << 0x18u)>; + using OSPEED13 = RegisterMask<OSPEEDR, (0x3u << 0x1au)>; + using OSPEED14 = RegisterMask<OSPEEDR, (0x3u << 0x1cu)>; + using OSPEED15 = RegisterMask<OSPEEDR, (0x3u << 0x1eu)>; + }; + struct PUPDR : public MemRegister<uint32_t, 0x5000080c> { + using PUPD0 = RegisterMask<PUPDR, (0x3u << 0x0u)>; + using PUPD1 = RegisterMask<PUPDR, (0x3u << 0x2u)>; + using PUPD2 = RegisterMask<PUPDR, (0x3u << 0x4u)>; + using PUPD3 = RegisterMask<PUPDR, (0x3u << 0x6u)>; + using PUPD4 = RegisterMask<PUPDR, (0x3u << 0x8u)>; + using PUPD5 = RegisterMask<PUPDR, (0x3u << 0xau)>; + using PUPD6 = RegisterMask<PUPDR, (0x3u << 0xcu)>; + using PUPD7 = RegisterMask<PUPDR, (0x3u << 0xeu)>; + using PUPD8 = RegisterMask<PUPDR, (0x3u << 0x10u)>; + using PUPD9 = RegisterMask<PUPDR, (0x3u << 0x12u)>; + using PUPD10 = RegisterMask<PUPDR, (0x3u << 0x14u)>; + using PUPD11 = RegisterMask<PUPDR, (0x3u << 0x16u)>; + using PUPD12 = RegisterMask<PUPDR, (0x3u << 0x18u)>; + using PUPD13 = RegisterMask<PUPDR, (0x3u << 0x1au)>; + using PUPD14 = RegisterMask<PUPDR, (0x3u << 0x1cu)>; + using PUPD15 = RegisterMask<PUPDR, (0x3u << 0x1eu)>; + }; + struct IDR : public MemRegister<uint32_t, 0x50000810> { + using ID0 = RegisterMask<IDR, (0x1u << 0x0u)>; + using ID1 = RegisterMask<IDR, (0x1u << 0x1u)>; + using ID2 = RegisterMask<IDR, (0x1u << 0x2u)>; + using ID3 = RegisterMask<IDR, (0x1u << 0x3u)>; + using ID4 = RegisterMask<IDR, (0x1u << 0x4u)>; + using ID5 = RegisterMask<IDR, (0x1u << 0x5u)>; + using ID6 = RegisterMask<IDR, (0x1u << 0x6u)>; + using ID7 = RegisterMask<IDR, (0x1u << 0x7u)>; + using ID8 = RegisterMask<IDR, (0x1u << 0x8u)>; + using ID9 = RegisterMask<IDR, (0x1u << 0x9u)>; + using ID10 = RegisterMask<IDR, (0x1u << 0xau)>; + using ID11 = RegisterMask<IDR, (0x1u << 0xbu)>; + using ID12 = RegisterMask<IDR, (0x1u << 0xcu)>; + using ID13 = RegisterMask<IDR, (0x1u << 0xdu)>; + using ID14 = RegisterMask<IDR, (0x1u << 0xeu)>; + using ID15 = RegisterMask<IDR, (0x1u << 0xfu)>; + }; + struct ODR : public MemRegister<uint32_t, 0x50000814> { + using OD0 = RegisterMask<ODR, (0x1u << 0x0u)>; + using OD1 = RegisterMask<ODR, (0x1u << 0x1u)>; + using OD2 = RegisterMask<ODR, (0x1u << 0x2u)>; + using OD3 = RegisterMask<ODR, (0x1u << 0x3u)>; + using OD4 = RegisterMask<ODR, (0x1u << 0x4u)>; + using OD5 = RegisterMask<ODR, (0x1u << 0x5u)>; + using OD6 = RegisterMask<ODR, (0x1u << 0x6u)>; + using OD7 = RegisterMask<ODR, (0x1u << 0x7u)>; + using OD8 = RegisterMask<ODR, (0x1u << 0x8u)>; + using OD9 = RegisterMask<ODR, (0x1u << 0x9u)>; + using OD10 = RegisterMask<ODR, (0x1u << 0xau)>; + using OD11 = RegisterMask<ODR, (0x1u << 0xbu)>; + using OD12 = RegisterMask<ODR, (0x1u << 0xcu)>; + using OD13 = RegisterMask<ODR, (0x1u << 0xdu)>; + using OD14 = RegisterMask<ODR, (0x1u << 0xeu)>; + using OD15 = RegisterMask<ODR, (0x1u << 0xfu)>; + }; + struct BSRR : public MemRegister<uint32_t, 0x50000818> { + using BS0 = RegisterMask<BSRR, (0x1u << 0x0u)>; + using BS1 = RegisterMask<BSRR, (0x1u << 0x1u)>; + using BS2 = RegisterMask<BSRR, (0x1u << 0x2u)>; + using BS3 = RegisterMask<BSRR, (0x1u << 0x3u)>; + using BS4 = RegisterMask<BSRR, (0x1u << 0x4u)>; + using BS5 = RegisterMask<BSRR, (0x1u << 0x5u)>; + using BS6 = RegisterMask<BSRR, (0x1u << 0x6u)>; + using BS7 = RegisterMask<BSRR, (0x1u << 0x7u)>; + using BS8 = RegisterMask<BSRR, (0x1u << 0x8u)>; + using BS9 = RegisterMask<BSRR, (0x1u << 0x9u)>; + using BS10 = RegisterMask<BSRR, (0x1u << 0xau)>; + using BS11 = RegisterMask<BSRR, (0x1u << 0xbu)>; + using BS12 = RegisterMask<BSRR, (0x1u << 0xcu)>; + using BS13 = RegisterMask<BSRR, (0x1u << 0xdu)>; + using BS14 = RegisterMask<BSRR, (0x1u << 0xeu)>; + using BS15 = RegisterMask<BSRR, (0x1u << 0xfu)>; + using BR0 = RegisterMask<BSRR, (0x1u << 0x10u)>; + using BR1 = RegisterMask<BSRR, (0x1u << 0x11u)>; + using BR2 = RegisterMask<BSRR, (0x1u << 0x12u)>; + using BR3 = RegisterMask<BSRR, (0x1u << 0x13u)>; + using BR4 = RegisterMask<BSRR, (0x1u << 0x14u)>; + using BR5 = RegisterMask<BSRR, (0x1u << 0x15u)>; + using BR6 = RegisterMask<BSRR, (0x1u << 0x16u)>; + using BR7 = RegisterMask<BSRR, (0x1u << 0x17u)>; + using BR8 = RegisterMask<BSRR, (0x1u << 0x18u)>; + using BR9 = RegisterMask<BSRR, (0x1u << 0x19u)>; + using BR10 = RegisterMask<BSRR, (0x1u << 0x1au)>; + using BR11 = RegisterMask<BSRR, (0x1u << 0x1bu)>; + using BR12 = RegisterMask<BSRR, (0x1u << 0x1cu)>; + using BR13 = RegisterMask<BSRR, (0x1u << 0x1du)>; + using BR14 = RegisterMask<BSRR, (0x1u << 0x1eu)>; + using BR15 = RegisterMask<BSRR, (0x1u << 0x1fu)>; + }; + struct LCKR : public MemRegister<uint32_t, 0x5000081c> { + using LCK0 = RegisterMask<LCKR, (0x1u << 0x0u)>; + using LCK1 = RegisterMask<LCKR, (0x1u << 0x1u)>; + using LCK2 = RegisterMask<LCKR, (0x1u << 0x2u)>; + using LCK3 = RegisterMask<LCKR, (0x1u << 0x3u)>; + using LCK4 = RegisterMask<LCKR, (0x1u << 0x4u)>; + using LCK5 = RegisterMask<LCKR, (0x1u << 0x5u)>; + using LCK6 = RegisterMask<LCKR, (0x1u << 0x6u)>; + using LCK7 = RegisterMask<LCKR, (0x1u << 0x7u)>; + using LCK8 = RegisterMask<LCKR, (0x1u << 0x8u)>; + using LCK9 = RegisterMask<LCKR, (0x1u << 0x9u)>; + using LCK10 = RegisterMask<LCKR, (0x1u << 0xau)>; + using LCK11 = RegisterMask<LCKR, (0x1u << 0xbu)>; + using LCK12 = RegisterMask<LCKR, (0x1u << 0xcu)>; + using LCK13 = RegisterMask<LCKR, (0x1u << 0xdu)>; + using LCK14 = RegisterMask<LCKR, (0x1u << 0xeu)>; + using LCK15 = RegisterMask<LCKR, (0x1u << 0xfu)>; + using LCKK = RegisterMask<LCKR, (0x1u << 0x10u)>; + }; + struct AFRL : public MemRegister<uint32_t, 0x50000820> { + using AFSEL0 = RegisterMask<AFRL, (0xfu << 0x0u)>; + using AFSEL1 = RegisterMask<AFRL, (0xfu << 0x4u)>; + using AFSEL2 = RegisterMask<AFRL, (0xfu << 0x8u)>; + using AFSEL3 = RegisterMask<AFRL, (0xfu << 0xcu)>; + using AFSEL4 = RegisterMask<AFRL, (0xfu << 0x10u)>; + using AFSEL5 = RegisterMask<AFRL, (0xfu << 0x14u)>; + using AFSEL6 = RegisterMask<AFRL, (0xfu << 0x18u)>; + using AFSEL7 = RegisterMask<AFRL, (0xfu << 0x1cu)>; + }; + struct AFRH : public MemRegister<uint32_t, 0x50000824> { + using AFSEL8 = RegisterMask<AFRH, (0xfu << 0x0u)>; + using AFSEL9 = RegisterMask<AFRH, (0xfu << 0x4u)>; + using AFSEL10 = RegisterMask<AFRH, (0xfu << 0x8u)>; + using AFSEL11 = RegisterMask<AFRH, (0xfu << 0xcu)>; + using AFSEL12 = RegisterMask<AFRH, (0xfu << 0x10u)>; + using AFSEL13 = RegisterMask<AFRH, (0xfu << 0x14u)>; + using AFSEL14 = RegisterMask<AFRH, (0xfu << 0x18u)>; + using AFSEL15 = RegisterMask<AFRH, (0xfu << 0x1cu)>; + }; + struct BRR : public MemRegister<uint32_t, 0x50000828> { + using BR0 = RegisterMask<BRR, (0x1u << 0x0u)>; + using BR1 = RegisterMask<BRR, (0x1u << 0x1u)>; + using BR2 = RegisterMask<BRR, (0x1u << 0x2u)>; + using BR3 = RegisterMask<BRR, (0x1u << 0x3u)>; + using BR4 = RegisterMask<BRR, (0x1u << 0x4u)>; + using BR5 = RegisterMask<BRR, (0x1u << 0x5u)>; + using BR6 = RegisterMask<BRR, (0x1u << 0x6u)>; + using BR7 = RegisterMask<BRR, (0x1u << 0x7u)>; + using BR8 = RegisterMask<BRR, (0x1u << 0x8u)>; + using BR9 = RegisterMask<BRR, (0x1u << 0x9u)>; + using BR10 = RegisterMask<BRR, (0x1u << 0xau)>; + using BR11 = RegisterMask<BRR, (0x1u << 0xbu)>; + using BR12 = RegisterMask<BRR, (0x1u << 0xcu)>; + using BR13 = RegisterMask<BRR, (0x1u << 0xdu)>; + using BR14 = RegisterMask<BRR, (0x1u << 0xeu)>; + using BR15 = RegisterMask<BRR, (0x1u << 0xfu)>; + }; + using ALL = RegisterGroup<MODER, OTYPER, OSPEEDR, PUPDR, IDR, ODR, BSRR, LCKR, AFRL, AFRH, BRR>; + } + namespace GPIOD { + struct MODER : public MemRegister<uint32_t, 0x50000c00> { + using MODE0 = RegisterMask<MODER, (0x3u << 0x0u)>; + using MODE1 = RegisterMask<MODER, (0x3u << 0x2u)>; + using MODE2 = RegisterMask<MODER, (0x3u << 0x4u)>; + using MODE3 = RegisterMask<MODER, (0x3u << 0x6u)>; + using MODE4 = RegisterMask<MODER, (0x3u << 0x8u)>; + using MODE5 = RegisterMask<MODER, (0x3u << 0xau)>; + using MODE6 = RegisterMask<MODER, (0x3u << 0xcu)>; + using MODE7 = RegisterMask<MODER, (0x3u << 0xeu)>; + using MODE8 = RegisterMask<MODER, (0x3u << 0x10u)>; + using MODE9 = RegisterMask<MODER, (0x3u << 0x12u)>; + using MODE10 = RegisterMask<MODER, (0x3u << 0x14u)>; + using MODE11 = RegisterMask<MODER, (0x3u << 0x16u)>; + using MODE12 = RegisterMask<MODER, (0x3u << 0x18u)>; + using MODE13 = RegisterMask<MODER, (0x3u << 0x1au)>; + using MODE14 = RegisterMask<MODER, (0x3u << 0x1cu)>; + using MODE15 = RegisterMask<MODER, (0x3u << 0x1eu)>; + }; + struct OTYPER : public MemRegister<uint32_t, 0x50000c04> { + using OT0 = RegisterMask<OTYPER, (0x1u << 0x0u)>; + using OT1 = RegisterMask<OTYPER, (0x1u << 0x1u)>; + using OT2 = RegisterMask<OTYPER, (0x1u << 0x2u)>; + using OT3 = RegisterMask<OTYPER, (0x1u << 0x3u)>; + using OT4 = RegisterMask<OTYPER, (0x1u << 0x4u)>; + using OT5 = RegisterMask<OTYPER, (0x1u << 0x5u)>; + using OT6 = RegisterMask<OTYPER, (0x1u << 0x6u)>; + using OT7 = RegisterMask<OTYPER, (0x1u << 0x7u)>; + using OT8 = RegisterMask<OTYPER, (0x1u << 0x8u)>; + using OT9 = RegisterMask<OTYPER, (0x1u << 0x9u)>; + using OT10 = RegisterMask<OTYPER, (0x1u << 0xau)>; + using OT11 = RegisterMask<OTYPER, (0x1u << 0xbu)>; + using OT12 = RegisterMask<OTYPER, (0x1u << 0xcu)>; + using OT13 = RegisterMask<OTYPER, (0x1u << 0xdu)>; + using OT14 = RegisterMask<OTYPER, (0x1u << 0xeu)>; + using OT15 = RegisterMask<OTYPER, (0x1u << 0xfu)>; + }; + struct OSPEEDR : public MemRegister<uint32_t, 0x50000c08> { + using OSPEED0 = RegisterMask<OSPEEDR, (0x3u << 0x0u)>; + using OSPEED1 = RegisterMask<OSPEEDR, (0x3u << 0x2u)>; + using OSPEED2 = RegisterMask<OSPEEDR, (0x3u << 0x4u)>; + using OSPEED3 = RegisterMask<OSPEEDR, (0x3u << 0x6u)>; + using OSPEED4 = RegisterMask<OSPEEDR, (0x3u << 0x8u)>; + using OSPEED5 = RegisterMask<OSPEEDR, (0x3u << 0xau)>; + using OSPEED6 = RegisterMask<OSPEEDR, (0x3u << 0xcu)>; + using OSPEED7 = RegisterMask<OSPEEDR, (0x3u << 0xeu)>; + using OSPEED8 = RegisterMask<OSPEEDR, (0x3u << 0x10u)>; + using OSPEED9 = RegisterMask<OSPEEDR, (0x3u << 0x12u)>; + using OSPEED10 = RegisterMask<OSPEEDR, (0x3u << 0x14u)>; + using OSPEED11 = RegisterMask<OSPEEDR, (0x3u << 0x16u)>; + using OSPEED12 = RegisterMask<OSPEEDR, (0x3u << 0x18u)>; + using OSPEED13 = RegisterMask<OSPEEDR, (0x3u << 0x1au)>; + using OSPEED14 = RegisterMask<OSPEEDR, (0x3u << 0x1cu)>; + using OSPEED15 = RegisterMask<OSPEEDR, (0x3u << 0x1eu)>; + }; + struct PUPDR : public MemRegister<uint32_t, 0x50000c0c> { + using PUPD0 = RegisterMask<PUPDR, (0x3u << 0x0u)>; + using PUPD1 = RegisterMask<PUPDR, (0x3u << 0x2u)>; + using PUPD2 = RegisterMask<PUPDR, (0x3u << 0x4u)>; + using PUPD3 = RegisterMask<PUPDR, (0x3u << 0x6u)>; + using PUPD4 = RegisterMask<PUPDR, (0x3u << 0x8u)>; + using PUPD5 = RegisterMask<PUPDR, (0x3u << 0xau)>; + using PUPD6 = RegisterMask<PUPDR, (0x3u << 0xcu)>; + using PUPD7 = RegisterMask<PUPDR, (0x3u << 0xeu)>; + using PUPD8 = RegisterMask<PUPDR, (0x3u << 0x10u)>; + using PUPD9 = RegisterMask<PUPDR, (0x3u << 0x12u)>; + using PUPD10 = RegisterMask<PUPDR, (0x3u << 0x14u)>; + using PUPD11 = RegisterMask<PUPDR, (0x3u << 0x16u)>; + using PUPD12 = RegisterMask<PUPDR, (0x3u << 0x18u)>; + using PUPD13 = RegisterMask<PUPDR, (0x3u << 0x1au)>; + using PUPD14 = RegisterMask<PUPDR, (0x3u << 0x1cu)>; + using PUPD15 = RegisterMask<PUPDR, (0x3u << 0x1eu)>; + }; + struct IDR : public MemRegister<uint32_t, 0x50000c10> { + using ID0 = RegisterMask<IDR, (0x1u << 0x0u)>; + using ID1 = RegisterMask<IDR, (0x1u << 0x1u)>; + using ID2 = RegisterMask<IDR, (0x1u << 0x2u)>; + using ID3 = RegisterMask<IDR, (0x1u << 0x3u)>; + using ID4 = RegisterMask<IDR, (0x1u << 0x4u)>; + using ID5 = RegisterMask<IDR, (0x1u << 0x5u)>; + using ID6 = RegisterMask<IDR, (0x1u << 0x6u)>; + using ID7 = RegisterMask<IDR, (0x1u << 0x7u)>; + using ID8 = RegisterMask<IDR, (0x1u << 0x8u)>; + using ID9 = RegisterMask<IDR, (0x1u << 0x9u)>; + using ID10 = RegisterMask<IDR, (0x1u << 0xau)>; + using ID11 = RegisterMask<IDR, (0x1u << 0xbu)>; + using ID12 = RegisterMask<IDR, (0x1u << 0xcu)>; + using ID13 = RegisterMask<IDR, (0x1u << 0xdu)>; + using ID14 = RegisterMask<IDR, (0x1u << 0xeu)>; + using ID15 = RegisterMask<IDR, (0x1u << 0xfu)>; + }; + struct ODR : public MemRegister<uint32_t, 0x50000c14> { + using OD0 = RegisterMask<ODR, (0x1u << 0x0u)>; + using OD1 = RegisterMask<ODR, (0x1u << 0x1u)>; + using OD2 = RegisterMask<ODR, (0x1u << 0x2u)>; + using OD3 = RegisterMask<ODR, (0x1u << 0x3u)>; + using OD4 = RegisterMask<ODR, (0x1u << 0x4u)>; + using OD5 = RegisterMask<ODR, (0x1u << 0x5u)>; + using OD6 = RegisterMask<ODR, (0x1u << 0x6u)>; + using OD7 = RegisterMask<ODR, (0x1u << 0x7u)>; + using OD8 = RegisterMask<ODR, (0x1u << 0x8u)>; + using OD9 = RegisterMask<ODR, (0x1u << 0x9u)>; + using OD10 = RegisterMask<ODR, (0x1u << 0xau)>; + using OD11 = RegisterMask<ODR, (0x1u << 0xbu)>; + using OD12 = RegisterMask<ODR, (0x1u << 0xcu)>; + using OD13 = RegisterMask<ODR, (0x1u << 0xdu)>; + using OD14 = RegisterMask<ODR, (0x1u << 0xeu)>; + using OD15 = RegisterMask<ODR, (0x1u << 0xfu)>; + }; + struct BSRR : public MemRegister<uint32_t, 0x50000c18> { + using BS0 = RegisterMask<BSRR, (0x1u << 0x0u)>; + using BS1 = RegisterMask<BSRR, (0x1u << 0x1u)>; + using BS2 = RegisterMask<BSRR, (0x1u << 0x2u)>; + using BS3 = RegisterMask<BSRR, (0x1u << 0x3u)>; + using BS4 = RegisterMask<BSRR, (0x1u << 0x4u)>; + using BS5 = RegisterMask<BSRR, (0x1u << 0x5u)>; + using BS6 = RegisterMask<BSRR, (0x1u << 0x6u)>; + using BS7 = RegisterMask<BSRR, (0x1u << 0x7u)>; + using BS8 = RegisterMask<BSRR, (0x1u << 0x8u)>; + using BS9 = RegisterMask<BSRR, (0x1u << 0x9u)>; + using BS10 = RegisterMask<BSRR, (0x1u << 0xau)>; + using BS11 = RegisterMask<BSRR, (0x1u << 0xbu)>; + using BS12 = RegisterMask<BSRR, (0x1u << 0xcu)>; + using BS13 = RegisterMask<BSRR, (0x1u << 0xdu)>; + using BS14 = RegisterMask<BSRR, (0x1u << 0xeu)>; + using BS15 = RegisterMask<BSRR, (0x1u << 0xfu)>; + using BR0 = RegisterMask<BSRR, (0x1u << 0x10u)>; + using BR1 = RegisterMask<BSRR, (0x1u << 0x11u)>; + using BR2 = RegisterMask<BSRR, (0x1u << 0x12u)>; + using BR3 = RegisterMask<BSRR, (0x1u << 0x13u)>; + using BR4 = RegisterMask<BSRR, (0x1u << 0x14u)>; + using BR5 = RegisterMask<BSRR, (0x1u << 0x15u)>; + using BR6 = RegisterMask<BSRR, (0x1u << 0x16u)>; + using BR7 = RegisterMask<BSRR, (0x1u << 0x17u)>; + using BR8 = RegisterMask<BSRR, (0x1u << 0x18u)>; + using BR9 = RegisterMask<BSRR, (0x1u << 0x19u)>; + using BR10 = RegisterMask<BSRR, (0x1u << 0x1au)>; + using BR11 = RegisterMask<BSRR, (0x1u << 0x1bu)>; + using BR12 = RegisterMask<BSRR, (0x1u << 0x1cu)>; + using BR13 = RegisterMask<BSRR, (0x1u << 0x1du)>; + using BR14 = RegisterMask<BSRR, (0x1u << 0x1eu)>; + using BR15 = RegisterMask<BSRR, (0x1u << 0x1fu)>; + }; + struct LCKR : public MemRegister<uint32_t, 0x50000c1c> { + using LCK0 = RegisterMask<LCKR, (0x1u << 0x0u)>; + using LCK1 = RegisterMask<LCKR, (0x1u << 0x1u)>; + using LCK2 = RegisterMask<LCKR, (0x1u << 0x2u)>; + using LCK3 = RegisterMask<LCKR, (0x1u << 0x3u)>; + using LCK4 = RegisterMask<LCKR, (0x1u << 0x4u)>; + using LCK5 = RegisterMask<LCKR, (0x1u << 0x5u)>; + using LCK6 = RegisterMask<LCKR, (0x1u << 0x6u)>; + using LCK7 = RegisterMask<LCKR, (0x1u << 0x7u)>; + using LCK8 = RegisterMask<LCKR, (0x1u << 0x8u)>; + using LCK9 = RegisterMask<LCKR, (0x1u << 0x9u)>; + using LCK10 = RegisterMask<LCKR, (0x1u << 0xau)>; + using LCK11 = RegisterMask<LCKR, (0x1u << 0xbu)>; + using LCK12 = RegisterMask<LCKR, (0x1u << 0xcu)>; + using LCK13 = RegisterMask<LCKR, (0x1u << 0xdu)>; + using LCK14 = RegisterMask<LCKR, (0x1u << 0xeu)>; + using LCK15 = RegisterMask<LCKR, (0x1u << 0xfu)>; + using LCKK = RegisterMask<LCKR, (0x1u << 0x10u)>; + }; + struct AFRL : public MemRegister<uint32_t, 0x50000c20> { + using AFSEL0 = RegisterMask<AFRL, (0xfu << 0x0u)>; + using AFSEL1 = RegisterMask<AFRL, (0xfu << 0x4u)>; + using AFSEL2 = RegisterMask<AFRL, (0xfu << 0x8u)>; + using AFSEL3 = RegisterMask<AFRL, (0xfu << 0xcu)>; + using AFSEL4 = RegisterMask<AFRL, (0xfu << 0x10u)>; + using AFSEL5 = RegisterMask<AFRL, (0xfu << 0x14u)>; + using AFSEL6 = RegisterMask<AFRL, (0xfu << 0x18u)>; + using AFSEL7 = RegisterMask<AFRL, (0xfu << 0x1cu)>; + }; + struct AFRH : public MemRegister<uint32_t, 0x50000c24> { + using AFSEL8 = RegisterMask<AFRH, (0xfu << 0x0u)>; + using AFSEL9 = RegisterMask<AFRH, (0xfu << 0x4u)>; + using AFSEL10 = RegisterMask<AFRH, (0xfu << 0x8u)>; + using AFSEL11 = RegisterMask<AFRH, (0xfu << 0xcu)>; + using AFSEL12 = RegisterMask<AFRH, (0xfu << 0x10u)>; + using AFSEL13 = RegisterMask<AFRH, (0xfu << 0x14u)>; + using AFSEL14 = RegisterMask<AFRH, (0xfu << 0x18u)>; + using AFSEL15 = RegisterMask<AFRH, (0xfu << 0x1cu)>; + }; + struct BRR : public MemRegister<uint32_t, 0x50000c28> { + using BR0 = RegisterMask<BRR, (0x1u << 0x0u)>; + using BR1 = RegisterMask<BRR, (0x1u << 0x1u)>; + using BR2 = RegisterMask<BRR, (0x1u << 0x2u)>; + using BR3 = RegisterMask<BRR, (0x1u << 0x3u)>; + using BR4 = RegisterMask<BRR, (0x1u << 0x4u)>; + using BR5 = RegisterMask<BRR, (0x1u << 0x5u)>; + using BR6 = RegisterMask<BRR, (0x1u << 0x6u)>; + using BR7 = RegisterMask<BRR, (0x1u << 0x7u)>; + using BR8 = RegisterMask<BRR, (0x1u << 0x8u)>; + using BR9 = RegisterMask<BRR, (0x1u << 0x9u)>; + using BR10 = RegisterMask<BRR, (0x1u << 0xau)>; + using BR11 = RegisterMask<BRR, (0x1u << 0xbu)>; + using BR12 = RegisterMask<BRR, (0x1u << 0xcu)>; + using BR13 = RegisterMask<BRR, (0x1u << 0xdu)>; + using BR14 = RegisterMask<BRR, (0x1u << 0xeu)>; + using BR15 = RegisterMask<BRR, (0x1u << 0xfu)>; + }; + using ALL = RegisterGroup<MODER, OTYPER, OSPEEDR, PUPDR, IDR, ODR, BSRR, LCKR, AFRL, AFRH, BRR>; + } + namespace GPIOE { + struct MODER : public MemRegister<uint32_t, 0x50001000> { + using MODE0 = RegisterMask<MODER, (0x3u << 0x0u)>; + using MODE1 = RegisterMask<MODER, (0x3u << 0x2u)>; + using MODE2 = RegisterMask<MODER, (0x3u << 0x4u)>; + using MODE3 = RegisterMask<MODER, (0x3u << 0x6u)>; + using MODE4 = RegisterMask<MODER, (0x3u << 0x8u)>; + using MODE5 = RegisterMask<MODER, (0x3u << 0xau)>; + using MODE6 = RegisterMask<MODER, (0x3u << 0xcu)>; + using MODE7 = RegisterMask<MODER, (0x3u << 0xeu)>; + using MODE8 = RegisterMask<MODER, (0x3u << 0x10u)>; + using MODE9 = RegisterMask<MODER, (0x3u << 0x12u)>; + using MODE10 = RegisterMask<MODER, (0x3u << 0x14u)>; + using MODE11 = RegisterMask<MODER, (0x3u << 0x16u)>; + using MODE12 = RegisterMask<MODER, (0x3u << 0x18u)>; + using MODE13 = RegisterMask<MODER, (0x3u << 0x1au)>; + using MODE14 = RegisterMask<MODER, (0x3u << 0x1cu)>; + using MODE15 = RegisterMask<MODER, (0x3u << 0x1eu)>; + }; + struct OTYPER : public MemRegister<uint32_t, 0x50001004> { + using OT0 = RegisterMask<OTYPER, (0x1u << 0x0u)>; + using OT1 = RegisterMask<OTYPER, (0x1u << 0x1u)>; + using OT2 = RegisterMask<OTYPER, (0x1u << 0x2u)>; + using OT3 = RegisterMask<OTYPER, (0x1u << 0x3u)>; + using OT4 = RegisterMask<OTYPER, (0x1u << 0x4u)>; + using OT5 = RegisterMask<OTYPER, (0x1u << 0x5u)>; + using OT6 = RegisterMask<OTYPER, (0x1u << 0x6u)>; + using OT7 = RegisterMask<OTYPER, (0x1u << 0x7u)>; + using OT8 = RegisterMask<OTYPER, (0x1u << 0x8u)>; + using OT9 = RegisterMask<OTYPER, (0x1u << 0x9u)>; + using OT10 = RegisterMask<OTYPER, (0x1u << 0xau)>; + using OT11 = RegisterMask<OTYPER, (0x1u << 0xbu)>; + using OT12 = RegisterMask<OTYPER, (0x1u << 0xcu)>; + using OT13 = RegisterMask<OTYPER, (0x1u << 0xdu)>; + using OT14 = RegisterMask<OTYPER, (0x1u << 0xeu)>; + using OT15 = RegisterMask<OTYPER, (0x1u << 0xfu)>; + }; + struct OSPEEDR : public MemRegister<uint32_t, 0x50001008> { + using OSPEED0 = RegisterMask<OSPEEDR, (0x3u << 0x0u)>; + using OSPEED1 = RegisterMask<OSPEEDR, (0x3u << 0x2u)>; + using OSPEED2 = RegisterMask<OSPEEDR, (0x3u << 0x4u)>; + using OSPEED3 = RegisterMask<OSPEEDR, (0x3u << 0x6u)>; + using OSPEED4 = RegisterMask<OSPEEDR, (0x3u << 0x8u)>; + using OSPEED5 = RegisterMask<OSPEEDR, (0x3u << 0xau)>; + using OSPEED6 = RegisterMask<OSPEEDR, (0x3u << 0xcu)>; + using OSPEED7 = RegisterMask<OSPEEDR, (0x3u << 0xeu)>; + using OSPEED8 = RegisterMask<OSPEEDR, (0x3u << 0x10u)>; + using OSPEED9 = RegisterMask<OSPEEDR, (0x3u << 0x12u)>; + using OSPEED10 = RegisterMask<OSPEEDR, (0x3u << 0x14u)>; + using OSPEED11 = RegisterMask<OSPEEDR, (0x3u << 0x16u)>; + using OSPEED12 = RegisterMask<OSPEEDR, (0x3u << 0x18u)>; + using OSPEED13 = RegisterMask<OSPEEDR, (0x3u << 0x1au)>; + using OSPEED14 = RegisterMask<OSPEEDR, (0x3u << 0x1cu)>; + using OSPEED15 = RegisterMask<OSPEEDR, (0x3u << 0x1eu)>; + }; + struct PUPDR : public MemRegister<uint32_t, 0x5000100c> { + using PUPD0 = RegisterMask<PUPDR, (0x3u << 0x0u)>; + using PUPD1 = RegisterMask<PUPDR, (0x3u << 0x2u)>; + using PUPD2 = RegisterMask<PUPDR, (0x3u << 0x4u)>; + using PUPD3 = RegisterMask<PUPDR, (0x3u << 0x6u)>; + using PUPD4 = RegisterMask<PUPDR, (0x3u << 0x8u)>; + using PUPD5 = RegisterMask<PUPDR, (0x3u << 0xau)>; + using PUPD6 = RegisterMask<PUPDR, (0x3u << 0xcu)>; + using PUPD7 = RegisterMask<PUPDR, (0x3u << 0xeu)>; + using PUPD8 = RegisterMask<PUPDR, (0x3u << 0x10u)>; + using PUPD9 = RegisterMask<PUPDR, (0x3u << 0x12u)>; + using PUPD10 = RegisterMask<PUPDR, (0x3u << 0x14u)>; + using PUPD11 = RegisterMask<PUPDR, (0x3u << 0x16u)>; + using PUPD12 = RegisterMask<PUPDR, (0x3u << 0x18u)>; + using PUPD13 = RegisterMask<PUPDR, (0x3u << 0x1au)>; + using PUPD14 = RegisterMask<PUPDR, (0x3u << 0x1cu)>; + using PUPD15 = RegisterMask<PUPDR, (0x3u << 0x1eu)>; + }; + struct IDR : public MemRegister<uint32_t, 0x50001010> { + using ID0 = RegisterMask<IDR, (0x1u << 0x0u)>; + using ID1 = RegisterMask<IDR, (0x1u << 0x1u)>; + using ID2 = RegisterMask<IDR, (0x1u << 0x2u)>; + using ID3 = RegisterMask<IDR, (0x1u << 0x3u)>; + using ID4 = RegisterMask<IDR, (0x1u << 0x4u)>; + using ID5 = RegisterMask<IDR, (0x1u << 0x5u)>; + using ID6 = RegisterMask<IDR, (0x1u << 0x6u)>; + using ID7 = RegisterMask<IDR, (0x1u << 0x7u)>; + using ID8 = RegisterMask<IDR, (0x1u << 0x8u)>; + using ID9 = RegisterMask<IDR, (0x1u << 0x9u)>; + using ID10 = RegisterMask<IDR, (0x1u << 0xau)>; + using ID11 = RegisterMask<IDR, (0x1u << 0xbu)>; + using ID12 = RegisterMask<IDR, (0x1u << 0xcu)>; + using ID13 = RegisterMask<IDR, (0x1u << 0xdu)>; + using ID14 = RegisterMask<IDR, (0x1u << 0xeu)>; + using ID15 = RegisterMask<IDR, (0x1u << 0xfu)>; + }; + struct ODR : public MemRegister<uint32_t, 0x50001014> { + using OD0 = RegisterMask<ODR, (0x1u << 0x0u)>; + using OD1 = RegisterMask<ODR, (0x1u << 0x1u)>; + using OD2 = RegisterMask<ODR, (0x1u << 0x2u)>; + using OD3 = RegisterMask<ODR, (0x1u << 0x3u)>; + using OD4 = RegisterMask<ODR, (0x1u << 0x4u)>; + using OD5 = RegisterMask<ODR, (0x1u << 0x5u)>; + using OD6 = RegisterMask<ODR, (0x1u << 0x6u)>; + using OD7 = RegisterMask<ODR, (0x1u << 0x7u)>; + using OD8 = RegisterMask<ODR, (0x1u << 0x8u)>; + using OD9 = RegisterMask<ODR, (0x1u << 0x9u)>; + using OD10 = RegisterMask<ODR, (0x1u << 0xau)>; + using OD11 = RegisterMask<ODR, (0x1u << 0xbu)>; + using OD12 = RegisterMask<ODR, (0x1u << 0xcu)>; + using OD13 = RegisterMask<ODR, (0x1u << 0xdu)>; + using OD14 = RegisterMask<ODR, (0x1u << 0xeu)>; + using OD15 = RegisterMask<ODR, (0x1u << 0xfu)>; + }; + struct BSRR : public MemRegister<uint32_t, 0x50001018> { + using BS0 = RegisterMask<BSRR, (0x1u << 0x0u)>; + using BS1 = RegisterMask<BSRR, (0x1u << 0x1u)>; + using BS2 = RegisterMask<BSRR, (0x1u << 0x2u)>; + using BS3 = RegisterMask<BSRR, (0x1u << 0x3u)>; + using BS4 = RegisterMask<BSRR, (0x1u << 0x4u)>; + using BS5 = RegisterMask<BSRR, (0x1u << 0x5u)>; + using BS6 = RegisterMask<BSRR, (0x1u << 0x6u)>; + using BS7 = RegisterMask<BSRR, (0x1u << 0x7u)>; + using BS8 = RegisterMask<BSRR, (0x1u << 0x8u)>; + using BS9 = RegisterMask<BSRR, (0x1u << 0x9u)>; + using BS10 = RegisterMask<BSRR, (0x1u << 0xau)>; + using BS11 = RegisterMask<BSRR, (0x1u << 0xbu)>; + using BS12 = RegisterMask<BSRR, (0x1u << 0xcu)>; + using BS13 = RegisterMask<BSRR, (0x1u << 0xdu)>; + using BS14 = RegisterMask<BSRR, (0x1u << 0xeu)>; + using BS15 = RegisterMask<BSRR, (0x1u << 0xfu)>; + using BR0 = RegisterMask<BSRR, (0x1u << 0x10u)>; + using BR1 = RegisterMask<BSRR, (0x1u << 0x11u)>; + using BR2 = RegisterMask<BSRR, (0x1u << 0x12u)>; + using BR3 = RegisterMask<BSRR, (0x1u << 0x13u)>; + using BR4 = RegisterMask<BSRR, (0x1u << 0x14u)>; + using BR5 = RegisterMask<BSRR, (0x1u << 0x15u)>; + using BR6 = RegisterMask<BSRR, (0x1u << 0x16u)>; + using BR7 = RegisterMask<BSRR, (0x1u << 0x17u)>; + using BR8 = RegisterMask<BSRR, (0x1u << 0x18u)>; + using BR9 = RegisterMask<BSRR, (0x1u << 0x19u)>; + using BR10 = RegisterMask<BSRR, (0x1u << 0x1au)>; + using BR11 = RegisterMask<BSRR, (0x1u << 0x1bu)>; + using BR12 = RegisterMask<BSRR, (0x1u << 0x1cu)>; + using BR13 = RegisterMask<BSRR, (0x1u << 0x1du)>; + using BR14 = RegisterMask<BSRR, (0x1u << 0x1eu)>; + using BR15 = RegisterMask<BSRR, (0x1u << 0x1fu)>; + }; + struct LCKR : public MemRegister<uint32_t, 0x5000101c> { + using LCK0 = RegisterMask<LCKR, (0x1u << 0x0u)>; + using LCK1 = RegisterMask<LCKR, (0x1u << 0x1u)>; + using LCK2 = RegisterMask<LCKR, (0x1u << 0x2u)>; + using LCK3 = RegisterMask<LCKR, (0x1u << 0x3u)>; + using LCK4 = RegisterMask<LCKR, (0x1u << 0x4u)>; + using LCK5 = RegisterMask<LCKR, (0x1u << 0x5u)>; + using LCK6 = RegisterMask<LCKR, (0x1u << 0x6u)>; + using LCK7 = RegisterMask<LCKR, (0x1u << 0x7u)>; + using LCK8 = RegisterMask<LCKR, (0x1u << 0x8u)>; + using LCK9 = RegisterMask<LCKR, (0x1u << 0x9u)>; + using LCK10 = RegisterMask<LCKR, (0x1u << 0xau)>; + using LCK11 = RegisterMask<LCKR, (0x1u << 0xbu)>; + using LCK12 = RegisterMask<LCKR, (0x1u << 0xcu)>; + using LCK13 = RegisterMask<LCKR, (0x1u << 0xdu)>; + using LCK14 = RegisterMask<LCKR, (0x1u << 0xeu)>; + using LCK15 = RegisterMask<LCKR, (0x1u << 0xfu)>; + using LCKK = RegisterMask<LCKR, (0x1u << 0x10u)>; + }; + struct AFRL : public MemRegister<uint32_t, 0x50001020> { + using AFSEL0 = RegisterMask<AFRL, (0xfu << 0x0u)>; + using AFSEL1 = RegisterMask<AFRL, (0xfu << 0x4u)>; + using AFSEL2 = RegisterMask<AFRL, (0xfu << 0x8u)>; + using AFSEL3 = RegisterMask<AFRL, (0xfu << 0xcu)>; + using AFSEL4 = RegisterMask<AFRL, (0xfu << 0x10u)>; + using AFSEL5 = RegisterMask<AFRL, (0xfu << 0x14u)>; + using AFSEL6 = RegisterMask<AFRL, (0xfu << 0x18u)>; + using AFSEL7 = RegisterMask<AFRL, (0xfu << 0x1cu)>; + }; + struct AFRH : public MemRegister<uint32_t, 0x50001024> { + using AFSEL8 = RegisterMask<AFRH, (0xfu << 0x0u)>; + using AFSEL9 = RegisterMask<AFRH, (0xfu << 0x4u)>; + using AFSEL10 = RegisterMask<AFRH, (0xfu << 0x8u)>; + using AFSEL11 = RegisterMask<AFRH, (0xfu << 0xcu)>; + using AFSEL12 = RegisterMask<AFRH, (0xfu << 0x10u)>; + using AFSEL13 = RegisterMask<AFRH, (0xfu << 0x14u)>; + using AFSEL14 = RegisterMask<AFRH, (0xfu << 0x18u)>; + using AFSEL15 = RegisterMask<AFRH, (0xfu << 0x1cu)>; + }; + struct BRR : public MemRegister<uint32_t, 0x50001028> { + using BR0 = RegisterMask<BRR, (0x1u << 0x0u)>; + using BR1 = RegisterMask<BRR, (0x1u << 0x1u)>; + using BR2 = RegisterMask<BRR, (0x1u << 0x2u)>; + using BR3 = RegisterMask<BRR, (0x1u << 0x3u)>; + using BR4 = RegisterMask<BRR, (0x1u << 0x4u)>; + using BR5 = RegisterMask<BRR, (0x1u << 0x5u)>; + using BR6 = RegisterMask<BRR, (0x1u << 0x6u)>; + using BR7 = RegisterMask<BRR, (0x1u << 0x7u)>; + using BR8 = RegisterMask<BRR, (0x1u << 0x8u)>; + using BR9 = RegisterMask<BRR, (0x1u << 0x9u)>; + using BR10 = RegisterMask<BRR, (0x1u << 0xau)>; + using BR11 = RegisterMask<BRR, (0x1u << 0xbu)>; + using BR12 = RegisterMask<BRR, (0x1u << 0xcu)>; + using BR13 = RegisterMask<BRR, (0x1u << 0xdu)>; + using BR14 = RegisterMask<BRR, (0x1u << 0xeu)>; + using BR15 = RegisterMask<BRR, (0x1u << 0xfu)>; + }; + using ALL = RegisterGroup<MODER, OTYPER, OSPEEDR, PUPDR, IDR, ODR, BSRR, LCKR, AFRL, AFRH, BRR>; + } + namespace GPIOF { + struct MODER : public MemRegister<uint32_t, 0x50001400> { + using MODE0 = RegisterMask<MODER, (0x3u << 0x0u)>; + using MODE1 = RegisterMask<MODER, (0x3u << 0x2u)>; + using MODE2 = RegisterMask<MODER, (0x3u << 0x4u)>; + using MODE3 = RegisterMask<MODER, (0x3u << 0x6u)>; + using MODE4 = RegisterMask<MODER, (0x3u << 0x8u)>; + using MODE5 = RegisterMask<MODER, (0x3u << 0xau)>; + using MODE6 = RegisterMask<MODER, (0x3u << 0xcu)>; + using MODE7 = RegisterMask<MODER, (0x3u << 0xeu)>; + using MODE8 = RegisterMask<MODER, (0x3u << 0x10u)>; + using MODE9 = RegisterMask<MODER, (0x3u << 0x12u)>; + using MODE10 = RegisterMask<MODER, (0x3u << 0x14u)>; + using MODE11 = RegisterMask<MODER, (0x3u << 0x16u)>; + using MODE12 = RegisterMask<MODER, (0x3u << 0x18u)>; + using MODE13 = RegisterMask<MODER, (0x3u << 0x1au)>; + using MODE14 = RegisterMask<MODER, (0x3u << 0x1cu)>; + using MODE15 = RegisterMask<MODER, (0x3u << 0x1eu)>; + }; + struct OTYPER : public MemRegister<uint32_t, 0x50001404> { + using OT0 = RegisterMask<OTYPER, (0x1u << 0x0u)>; + using OT1 = RegisterMask<OTYPER, (0x1u << 0x1u)>; + using OT2 = RegisterMask<OTYPER, (0x1u << 0x2u)>; + using OT3 = RegisterMask<OTYPER, (0x1u << 0x3u)>; + using OT4 = RegisterMask<OTYPER, (0x1u << 0x4u)>; + using OT5 = RegisterMask<OTYPER, (0x1u << 0x5u)>; + using OT6 = RegisterMask<OTYPER, (0x1u << 0x6u)>; + using OT7 = RegisterMask<OTYPER, (0x1u << 0x7u)>; + using OT8 = RegisterMask<OTYPER, (0x1u << 0x8u)>; + using OT9 = RegisterMask<OTYPER, (0x1u << 0x9u)>; + using OT10 = RegisterMask<OTYPER, (0x1u << 0xau)>; + using OT11 = RegisterMask<OTYPER, (0x1u << 0xbu)>; + using OT12 = RegisterMask<OTYPER, (0x1u << 0xcu)>; + using OT13 = RegisterMask<OTYPER, (0x1u << 0xdu)>; + using OT14 = RegisterMask<OTYPER, (0x1u << 0xeu)>; + using OT15 = RegisterMask<OTYPER, (0x1u << 0xfu)>; + }; + struct OSPEEDR : public MemRegister<uint32_t, 0x50001408> { + using OSPEED0 = RegisterMask<OSPEEDR, (0x3u << 0x0u)>; + using OSPEED1 = RegisterMask<OSPEEDR, (0x3u << 0x2u)>; + using OSPEED2 = RegisterMask<OSPEEDR, (0x3u << 0x4u)>; + using OSPEED3 = RegisterMask<OSPEEDR, (0x3u << 0x6u)>; + using OSPEED4 = RegisterMask<OSPEEDR, (0x3u << 0x8u)>; + using OSPEED5 = RegisterMask<OSPEEDR, (0x3u << 0xau)>; + using OSPEED6 = RegisterMask<OSPEEDR, (0x3u << 0xcu)>; + using OSPEED7 = RegisterMask<OSPEEDR, (0x3u << 0xeu)>; + using OSPEED8 = RegisterMask<OSPEEDR, (0x3u << 0x10u)>; + using OSPEED9 = RegisterMask<OSPEEDR, (0x3u << 0x12u)>; + using OSPEED10 = RegisterMask<OSPEEDR, (0x3u << 0x14u)>; + using OSPEED11 = RegisterMask<OSPEEDR, (0x3u << 0x16u)>; + using OSPEED12 = RegisterMask<OSPEEDR, (0x3u << 0x18u)>; + using OSPEED13 = RegisterMask<OSPEEDR, (0x3u << 0x1au)>; + using OSPEED14 = RegisterMask<OSPEEDR, (0x3u << 0x1cu)>; + using OSPEED15 = RegisterMask<OSPEEDR, (0x3u << 0x1eu)>; + }; + struct PUPDR : public MemRegister<uint32_t, 0x5000140c> { + using PUPD0 = RegisterMask<PUPDR, (0x3u << 0x0u)>; + using PUPD1 = RegisterMask<PUPDR, (0x3u << 0x2u)>; + using PUPD2 = RegisterMask<PUPDR, (0x3u << 0x4u)>; + using PUPD3 = RegisterMask<PUPDR, (0x3u << 0x6u)>; + using PUPD4 = RegisterMask<PUPDR, (0x3u << 0x8u)>; + using PUPD5 = RegisterMask<PUPDR, (0x3u << 0xau)>; + using PUPD6 = RegisterMask<PUPDR, (0x3u << 0xcu)>; + using PUPD7 = RegisterMask<PUPDR, (0x3u << 0xeu)>; + using PUPD8 = RegisterMask<PUPDR, (0x3u << 0x10u)>; + using PUPD9 = RegisterMask<PUPDR, (0x3u << 0x12u)>; + using PUPD10 = RegisterMask<PUPDR, (0x3u << 0x14u)>; + using PUPD11 = RegisterMask<PUPDR, (0x3u << 0x16u)>; + using PUPD12 = RegisterMask<PUPDR, (0x3u << 0x18u)>; + using PUPD13 = RegisterMask<PUPDR, (0x3u << 0x1au)>; + using PUPD14 = RegisterMask<PUPDR, (0x3u << 0x1cu)>; + using PUPD15 = RegisterMask<PUPDR, (0x3u << 0x1eu)>; + }; + struct IDR : public MemRegister<uint32_t, 0x50001410> { + using ID0 = RegisterMask<IDR, (0x1u << 0x0u)>; + using ID1 = RegisterMask<IDR, (0x1u << 0x1u)>; + using ID2 = RegisterMask<IDR, (0x1u << 0x2u)>; + using ID3 = RegisterMask<IDR, (0x1u << 0x3u)>; + using ID4 = RegisterMask<IDR, (0x1u << 0x4u)>; + using ID5 = RegisterMask<IDR, (0x1u << 0x5u)>; + using ID6 = RegisterMask<IDR, (0x1u << 0x6u)>; + using ID7 = RegisterMask<IDR, (0x1u << 0x7u)>; + using ID8 = RegisterMask<IDR, (0x1u << 0x8u)>; + using ID9 = RegisterMask<IDR, (0x1u << 0x9u)>; + using ID10 = RegisterMask<IDR, (0x1u << 0xau)>; + using ID11 = RegisterMask<IDR, (0x1u << 0xbu)>; + using ID12 = RegisterMask<IDR, (0x1u << 0xcu)>; + using ID13 = RegisterMask<IDR, (0x1u << 0xdu)>; + using ID14 = RegisterMask<IDR, (0x1u << 0xeu)>; + using ID15 = RegisterMask<IDR, (0x1u << 0xfu)>; + }; + struct ODR : public MemRegister<uint32_t, 0x50001414> { + using OD0 = RegisterMask<ODR, (0x1u << 0x0u)>; + using OD1 = RegisterMask<ODR, (0x1u << 0x1u)>; + using OD2 = RegisterMask<ODR, (0x1u << 0x2u)>; + using OD3 = RegisterMask<ODR, (0x1u << 0x3u)>; + using OD4 = RegisterMask<ODR, (0x1u << 0x4u)>; + using OD5 = RegisterMask<ODR, (0x1u << 0x5u)>; + using OD6 = RegisterMask<ODR, (0x1u << 0x6u)>; + using OD7 = RegisterMask<ODR, (0x1u << 0x7u)>; + using OD8 = RegisterMask<ODR, (0x1u << 0x8u)>; + using OD9 = RegisterMask<ODR, (0x1u << 0x9u)>; + using OD10 = RegisterMask<ODR, (0x1u << 0xau)>; + using OD11 = RegisterMask<ODR, (0x1u << 0xbu)>; + using OD12 = RegisterMask<ODR, (0x1u << 0xcu)>; + using OD13 = RegisterMask<ODR, (0x1u << 0xdu)>; + using OD14 = RegisterMask<ODR, (0x1u << 0xeu)>; + using OD15 = RegisterMask<ODR, (0x1u << 0xfu)>; + }; + struct BSRR : public MemRegister<uint32_t, 0x50001418> { + using BS0 = RegisterMask<BSRR, (0x1u << 0x0u)>; + using BS1 = RegisterMask<BSRR, (0x1u << 0x1u)>; + using BS2 = RegisterMask<BSRR, (0x1u << 0x2u)>; + using BS3 = RegisterMask<BSRR, (0x1u << 0x3u)>; + using BS4 = RegisterMask<BSRR, (0x1u << 0x4u)>; + using BS5 = RegisterMask<BSRR, (0x1u << 0x5u)>; + using BS6 = RegisterMask<BSRR, (0x1u << 0x6u)>; + using BS7 = RegisterMask<BSRR, (0x1u << 0x7u)>; + using BS8 = RegisterMask<BSRR, (0x1u << 0x8u)>; + using BS9 = RegisterMask<BSRR, (0x1u << 0x9u)>; + using BS10 = RegisterMask<BSRR, (0x1u << 0xau)>; + using BS11 = RegisterMask<BSRR, (0x1u << 0xbu)>; + using BS12 = RegisterMask<BSRR, (0x1u << 0xcu)>; + using BS13 = RegisterMask<BSRR, (0x1u << 0xdu)>; + using BS14 = RegisterMask<BSRR, (0x1u << 0xeu)>; + using BS15 = RegisterMask<BSRR, (0x1u << 0xfu)>; + using BR0 = RegisterMask<BSRR, (0x1u << 0x10u)>; + using BR1 = RegisterMask<BSRR, (0x1u << 0x11u)>; + using BR2 = RegisterMask<BSRR, (0x1u << 0x12u)>; + using BR3 = RegisterMask<BSRR, (0x1u << 0x13u)>; + using BR4 = RegisterMask<BSRR, (0x1u << 0x14u)>; + using BR5 = RegisterMask<BSRR, (0x1u << 0x15u)>; + using BR6 = RegisterMask<BSRR, (0x1u << 0x16u)>; + using BR7 = RegisterMask<BSRR, (0x1u << 0x17u)>; + using BR8 = RegisterMask<BSRR, (0x1u << 0x18u)>; + using BR9 = RegisterMask<BSRR, (0x1u << 0x19u)>; + using BR10 = RegisterMask<BSRR, (0x1u << 0x1au)>; + using BR11 = RegisterMask<BSRR, (0x1u << 0x1bu)>; + using BR12 = RegisterMask<BSRR, (0x1u << 0x1cu)>; + using BR13 = RegisterMask<BSRR, (0x1u << 0x1du)>; + using BR14 = RegisterMask<BSRR, (0x1u << 0x1eu)>; + using BR15 = RegisterMask<BSRR, (0x1u << 0x1fu)>; + }; + struct LCKR : public MemRegister<uint32_t, 0x5000141c> { + using LCK0 = RegisterMask<LCKR, (0x1u << 0x0u)>; + using LCK1 = RegisterMask<LCKR, (0x1u << 0x1u)>; + using LCK2 = RegisterMask<LCKR, (0x1u << 0x2u)>; + using LCK3 = RegisterMask<LCKR, (0x1u << 0x3u)>; + using LCK4 = RegisterMask<LCKR, (0x1u << 0x4u)>; + using LCK5 = RegisterMask<LCKR, (0x1u << 0x5u)>; + using LCK6 = RegisterMask<LCKR, (0x1u << 0x6u)>; + using LCK7 = RegisterMask<LCKR, (0x1u << 0x7u)>; + using LCK8 = RegisterMask<LCKR, (0x1u << 0x8u)>; + using LCK9 = RegisterMask<LCKR, (0x1u << 0x9u)>; + using LCK10 = RegisterMask<LCKR, (0x1u << 0xau)>; + using LCK11 = RegisterMask<LCKR, (0x1u << 0xbu)>; + using LCK12 = RegisterMask<LCKR, (0x1u << 0xcu)>; + using LCK13 = RegisterMask<LCKR, (0x1u << 0xdu)>; + using LCK14 = RegisterMask<LCKR, (0x1u << 0xeu)>; + using LCK15 = RegisterMask<LCKR, (0x1u << 0xfu)>; + using LCKK = RegisterMask<LCKR, (0x1u << 0x10u)>; + }; + struct AFRL : public MemRegister<uint32_t, 0x50001420> { + using AFSEL0 = RegisterMask<AFRL, (0xfu << 0x0u)>; + using AFSEL1 = RegisterMask<AFRL, (0xfu << 0x4u)>; + using AFSEL2 = RegisterMask<AFRL, (0xfu << 0x8u)>; + using AFSEL3 = RegisterMask<AFRL, (0xfu << 0xcu)>; + using AFSEL4 = RegisterMask<AFRL, (0xfu << 0x10u)>; + using AFSEL5 = RegisterMask<AFRL, (0xfu << 0x14u)>; + using AFSEL6 = RegisterMask<AFRL, (0xfu << 0x18u)>; + using AFSEL7 = RegisterMask<AFRL, (0xfu << 0x1cu)>; + }; + struct AFRH : public MemRegister<uint32_t, 0x50001424> { + using AFSEL8 = RegisterMask<AFRH, (0xfu << 0x0u)>; + using AFSEL9 = RegisterMask<AFRH, (0xfu << 0x4u)>; + using AFSEL10 = RegisterMask<AFRH, (0xfu << 0x8u)>; + using AFSEL11 = RegisterMask<AFRH, (0xfu << 0xcu)>; + using AFSEL12 = RegisterMask<AFRH, (0xfu << 0x10u)>; + using AFSEL13 = RegisterMask<AFRH, (0xfu << 0x14u)>; + using AFSEL14 = RegisterMask<AFRH, (0xfu << 0x18u)>; + using AFSEL15 = RegisterMask<AFRH, (0xfu << 0x1cu)>; + }; + struct BRR : public MemRegister<uint32_t, 0x50001428> { + using BR0 = RegisterMask<BRR, (0x1u << 0x0u)>; + using BR1 = RegisterMask<BRR, (0x1u << 0x1u)>; + using BR2 = RegisterMask<BRR, (0x1u << 0x2u)>; + using BR3 = RegisterMask<BRR, (0x1u << 0x3u)>; + using BR4 = RegisterMask<BRR, (0x1u << 0x4u)>; + using BR5 = RegisterMask<BRR, (0x1u << 0x5u)>; + using BR6 = RegisterMask<BRR, (0x1u << 0x6u)>; + using BR7 = RegisterMask<BRR, (0x1u << 0x7u)>; + using BR8 = RegisterMask<BRR, (0x1u << 0x8u)>; + using BR9 = RegisterMask<BRR, (0x1u << 0x9u)>; + using BR10 = RegisterMask<BRR, (0x1u << 0xau)>; + using BR11 = RegisterMask<BRR, (0x1u << 0xbu)>; + using BR12 = RegisterMask<BRR, (0x1u << 0xcu)>; + using BR13 = RegisterMask<BRR, (0x1u << 0xdu)>; + using BR14 = RegisterMask<BRR, (0x1u << 0xeu)>; + using BR15 = RegisterMask<BRR, (0x1u << 0xfu)>; + }; + using ALL = RegisterGroup<MODER, OTYPER, OSPEEDR, PUPDR, IDR, ODR, BSRR, LCKR, AFRL, AFRH, BRR>; + } + namespace I2C1 { + struct CR1 : public MemRegister<uint32_t, 0x40005400> { + using PE = RegisterMask<CR1, (0x1u << 0x0u)>; + using TXIE = RegisterMask<CR1, (0x1u << 0x1u)>; + using RXIE = RegisterMask<CR1, (0x1u << 0x2u)>; + using ADDRIE = RegisterMask<CR1, (0x1u << 0x3u)>; + using NACKIE = RegisterMask<CR1, (0x1u << 0x4u)>; + using STOPIE = RegisterMask<CR1, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1, (0x1u << 0x6u)>; + using ERRIE = RegisterMask<CR1, (0x1u << 0x7u)>; + using DNF = RegisterMask<CR1, (0xfu << 0x8u)>; + using ANFOFF = RegisterMask<CR1, (0x1u << 0xcu)>; + using TXDMAEN = RegisterMask<CR1, (0x1u << 0xeu)>; + using RXDMAEN = RegisterMask<CR1, (0x1u << 0xfu)>; + using SBC = RegisterMask<CR1, (0x1u << 0x10u)>; + using NOSTRETCH = RegisterMask<CR1, (0x1u << 0x11u)>; + using WUPEN = RegisterMask<CR1, (0x1u << 0x12u)>; + using GCEN = RegisterMask<CR1, (0x1u << 0x13u)>; + using FMP = RegisterMask<CR1, (0x1u << 0x18u)>; + using ADDRACLR = RegisterMask<CR1, (0x1u << 0x1eu)>; + using STOPFACLR = RegisterMask<CR1, (0x1u << 0x1fu)>; + }; + struct CR2 : public MemRegister<uint32_t, 0x40005404> { + using SADD = RegisterMask<CR2, (0x3ffu << 0x0u)>; + using RD_WRN = RegisterMask<CR2, (0x1u << 0xau)>; + using ADD10 = RegisterMask<CR2, (0x1u << 0xbu)>; + using HEAD10R = RegisterMask<CR2, (0x1u << 0xcu)>; + using START = RegisterMask<CR2, (0x1u << 0xdu)>; + using STOP = RegisterMask<CR2, (0x1u << 0xeu)>; + using NACK = RegisterMask<CR2, (0x1u << 0xfu)>; + using NBYTES = RegisterMask<CR2, (0xffu << 0x10u)>; + using RELOAD = RegisterMask<CR2, (0x1u << 0x18u)>; + using AUTOEND = RegisterMask<CR2, (0x1u << 0x19u)>; + }; + struct OAR1 : public MemRegister<uint32_t, 0x40005408> { + using OA1 = RegisterMask<OAR1, (0x3ffu << 0x0u)>; + using OA1MODE = RegisterMask<OAR1, (0x1u << 0xau)>; + using OA1EN = RegisterMask<OAR1, (0x1u << 0xfu)>; + }; + struct OAR2 : public MemRegister<uint32_t, 0x4000540c> { + using OA2 = RegisterMask<OAR2, (0x7fu << 0x1u)>; + using OA2MSK = RegisterMask<OAR2, (0x7u << 0x8u)>; + using OA2EN = RegisterMask<OAR2, (0x1u << 0xfu)>; + }; + struct TIMINGR : public MemRegister<uint32_t, 0x40005410> { + using SCLL = RegisterMask<TIMINGR, (0xffu << 0x0u)>; + using SCLH = RegisterMask<TIMINGR, (0xffu << 0x8u)>; + using SDADEL = RegisterMask<TIMINGR, (0xfu << 0x10u)>; + using SCLDEL = RegisterMask<TIMINGR, (0xfu << 0x14u)>; + using PRESC = RegisterMask<TIMINGR, (0xfu << 0x1cu)>; + }; + struct TIMEOUTR : public MemRegister<uint32_t, 0x40005414> { + using TIMEOUTA = RegisterMask<TIMEOUTR, (0xfffu << 0x0u)>; + using TIDLE = RegisterMask<TIMEOUTR, (0x1u << 0xcu)>; + using TIMOUTEN = RegisterMask<TIMEOUTR, (0x1u << 0xfu)>; + using TIMEOUTB = RegisterMask<TIMEOUTR, (0xfffu << 0x10u)>; + using TEXTEN = RegisterMask<TIMEOUTR, (0x1u << 0x1fu)>; + }; + struct ISR : public MemRegister<uint32_t, 0x40005418> { + using TXE = RegisterMask<ISR, (0x1u << 0x0u)>; + using TXIS = RegisterMask<ISR, (0x1u << 0x1u)>; + using RXNE = RegisterMask<ISR, (0x1u << 0x2u)>; + using ADDR = RegisterMask<ISR, (0x1u << 0x3u)>; + using NACKF = RegisterMask<ISR, (0x1u << 0x4u)>; + using STOPF = RegisterMask<ISR, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR, (0x1u << 0x6u)>; + using TCR = RegisterMask<ISR, (0x1u << 0x7u)>; + using BERR = RegisterMask<ISR, (0x1u << 0x8u)>; + using ARLO = RegisterMask<ISR, (0x1u << 0x9u)>; + using OVR = RegisterMask<ISR, (0x1u << 0xau)>; + using BUSY = RegisterMask<ISR, (0x1u << 0xfu)>; + using DIR = RegisterMask<ISR, (0x1u << 0x10u)>; + using ADDCODE = RegisterMask<ISR, (0x7fu << 0x11u)>; + }; + struct ICR : public MemRegister<uint32_t, 0x4000541c> { + using ADDRCF = RegisterMask<ICR, (0x1u << 0x3u)>; + using NACKCF = RegisterMask<ICR, (0x1u << 0x4u)>; + using STOPCF = RegisterMask<ICR, (0x1u << 0x5u)>; + using BERRCF = RegisterMask<ICR, (0x1u << 0x8u)>; + using ARLOCF = RegisterMask<ICR, (0x1u << 0x9u)>; + using OVRCF = RegisterMask<ICR, (0x1u << 0xau)>; + }; + struct PECR : public MemRegister<uint32_t, 0x40005420> { + using PEC = RegisterMask<PECR, (0xffu << 0x0u)>; + }; + struct RXDR : public MemRegister<uint32_t, 0x40005424> { + using RXDATA = RegisterMask<RXDR, (0xffu << 0x0u)>; + }; + struct TXDR : public MemRegister<uint32_t, 0x40005428> { + using TXDATA = RegisterMask<TXDR, (0xffu << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR2, OAR1, OAR2, TIMINGR, TIMEOUTR, ISR, ICR, PECR, RXDR, TXDR>; + } + namespace I2C2 { + struct CR1 : public MemRegister<uint32_t, 0x40005800> { + using PE = RegisterMask<CR1, (0x1u << 0x0u)>; + using TXIE = RegisterMask<CR1, (0x1u << 0x1u)>; + using RXIE = RegisterMask<CR1, (0x1u << 0x2u)>; + using ADDRIE = RegisterMask<CR1, (0x1u << 0x3u)>; + using NACKIE = RegisterMask<CR1, (0x1u << 0x4u)>; + using STOPIE = RegisterMask<CR1, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1, (0x1u << 0x6u)>; + using ERRIE = RegisterMask<CR1, (0x1u << 0x7u)>; + using DNF = RegisterMask<CR1, (0xfu << 0x8u)>; + using ANFOFF = RegisterMask<CR1, (0x1u << 0xcu)>; + using TXDMAEN = RegisterMask<CR1, (0x1u << 0xeu)>; + using RXDMAEN = RegisterMask<CR1, (0x1u << 0xfu)>; + using SBC = RegisterMask<CR1, (0x1u << 0x10u)>; + using NOSTRETCH = RegisterMask<CR1, (0x1u << 0x11u)>; + using WUPEN = RegisterMask<CR1, (0x1u << 0x12u)>; + using GCEN = RegisterMask<CR1, (0x1u << 0x13u)>; + using FMP = RegisterMask<CR1, (0x1u << 0x18u)>; + using ADDRACLR = RegisterMask<CR1, (0x1u << 0x1eu)>; + using STOPFACLR = RegisterMask<CR1, (0x1u << 0x1fu)>; + }; + struct CR2 : public MemRegister<uint32_t, 0x40005804> { + using SADD = RegisterMask<CR2, (0x3ffu << 0x0u)>; + using RD_WRN = RegisterMask<CR2, (0x1u << 0xau)>; + using ADD10 = RegisterMask<CR2, (0x1u << 0xbu)>; + using HEAD10R = RegisterMask<CR2, (0x1u << 0xcu)>; + using START = RegisterMask<CR2, (0x1u << 0xdu)>; + using STOP = RegisterMask<CR2, (0x1u << 0xeu)>; + using NACK = RegisterMask<CR2, (0x1u << 0xfu)>; + using NBYTES = RegisterMask<CR2, (0xffu << 0x10u)>; + using RELOAD = RegisterMask<CR2, (0x1u << 0x18u)>; + using AUTOEND = RegisterMask<CR2, (0x1u << 0x19u)>; + }; + struct OAR1 : public MemRegister<uint32_t, 0x40005808> { + using OA1 = RegisterMask<OAR1, (0x3ffu << 0x0u)>; + using OA1MODE = RegisterMask<OAR1, (0x1u << 0xau)>; + using OA1EN = RegisterMask<OAR1, (0x1u << 0xfu)>; + }; + struct OAR2 : public MemRegister<uint32_t, 0x4000580c> { + using OA2 = RegisterMask<OAR2, (0x7fu << 0x1u)>; + using OA2MSK = RegisterMask<OAR2, (0x7u << 0x8u)>; + using OA2EN = RegisterMask<OAR2, (0x1u << 0xfu)>; + }; + struct TIMINGR : public MemRegister<uint32_t, 0x40005810> { + using SCLL = RegisterMask<TIMINGR, (0xffu << 0x0u)>; + using SCLH = RegisterMask<TIMINGR, (0xffu << 0x8u)>; + using SDADEL = RegisterMask<TIMINGR, (0xfu << 0x10u)>; + using SCLDEL = RegisterMask<TIMINGR, (0xfu << 0x14u)>; + using PRESC = RegisterMask<TIMINGR, (0xfu << 0x1cu)>; + }; + struct TIMEOUTR : public MemRegister<uint32_t, 0x40005814> { + using TIMEOUTA = RegisterMask<TIMEOUTR, (0xfffu << 0x0u)>; + using TIDLE = RegisterMask<TIMEOUTR, (0x1u << 0xcu)>; + using TIMOUTEN = RegisterMask<TIMEOUTR, (0x1u << 0xfu)>; + using TIMEOUTB = RegisterMask<TIMEOUTR, (0xfffu << 0x10u)>; + using TEXTEN = RegisterMask<TIMEOUTR, (0x1u << 0x1fu)>; + }; + struct ISR : public MemRegister<uint32_t, 0x40005818> { + using TXE = RegisterMask<ISR, (0x1u << 0x0u)>; + using TXIS = RegisterMask<ISR, (0x1u << 0x1u)>; + using RXNE = RegisterMask<ISR, (0x1u << 0x2u)>; + using ADDR = RegisterMask<ISR, (0x1u << 0x3u)>; + using NACKF = RegisterMask<ISR, (0x1u << 0x4u)>; + using STOPF = RegisterMask<ISR, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR, (0x1u << 0x6u)>; + using TCR = RegisterMask<ISR, (0x1u << 0x7u)>; + using BERR = RegisterMask<ISR, (0x1u << 0x8u)>; + using ARLO = RegisterMask<ISR, (0x1u << 0x9u)>; + using OVR = RegisterMask<ISR, (0x1u << 0xau)>; + using BUSY = RegisterMask<ISR, (0x1u << 0xfu)>; + using DIR = RegisterMask<ISR, (0x1u << 0x10u)>; + using ADDCODE = RegisterMask<ISR, (0x7fu << 0x11u)>; + }; + struct ICR : public MemRegister<uint32_t, 0x4000581c> { + using ADDRCF = RegisterMask<ICR, (0x1u << 0x3u)>; + using NACKCF = RegisterMask<ICR, (0x1u << 0x4u)>; + using STOPCF = RegisterMask<ICR, (0x1u << 0x5u)>; + using BERRCF = RegisterMask<ICR, (0x1u << 0x8u)>; + using ARLOCF = RegisterMask<ICR, (0x1u << 0x9u)>; + using OVRCF = RegisterMask<ICR, (0x1u << 0xau)>; + }; + struct PECR : public MemRegister<uint32_t, 0x40005820> { + using PEC = RegisterMask<PECR, (0xffu << 0x0u)>; + }; + struct RXDR : public MemRegister<uint32_t, 0x40005824> { + using RXDATA = RegisterMask<RXDR, (0xffu << 0x0u)>; + }; + struct TXDR : public MemRegister<uint32_t, 0x40005828> { + using TXDATA = RegisterMask<TXDR, (0xffu << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR2, OAR1, OAR2, TIMINGR, TIMEOUTR, ISR, ICR, PECR, RXDR, TXDR>; + } + namespace I2C3 { + struct CR1 : public MemRegister<uint32_t, 0x40008800> { + using PE = RegisterMask<CR1, (0x1u << 0x0u)>; + using TXIE = RegisterMask<CR1, (0x1u << 0x1u)>; + using RXIE = RegisterMask<CR1, (0x1u << 0x2u)>; + using ADDRIE = RegisterMask<CR1, (0x1u << 0x3u)>; + using NACKIE = RegisterMask<CR1, (0x1u << 0x4u)>; + using STOPIE = RegisterMask<CR1, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1, (0x1u << 0x6u)>; + using ERRIE = RegisterMask<CR1, (0x1u << 0x7u)>; + using DNF = RegisterMask<CR1, (0xfu << 0x8u)>; + using ANFOFF = RegisterMask<CR1, (0x1u << 0xcu)>; + using TXDMAEN = RegisterMask<CR1, (0x1u << 0xeu)>; + using RXDMAEN = RegisterMask<CR1, (0x1u << 0xfu)>; + using SBC = RegisterMask<CR1, (0x1u << 0x10u)>; + using NOSTRETCH = RegisterMask<CR1, (0x1u << 0x11u)>; + using WUPEN = RegisterMask<CR1, (0x1u << 0x12u)>; + using GCEN = RegisterMask<CR1, (0x1u << 0x13u)>; + using FMP = RegisterMask<CR1, (0x1u << 0x18u)>; + using ADDRACLR = RegisterMask<CR1, (0x1u << 0x1eu)>; + using STOPFACLR = RegisterMask<CR1, (0x1u << 0x1fu)>; + }; + struct CR2 : public MemRegister<uint32_t, 0x40008804> { + using SADD = RegisterMask<CR2, (0x3ffu << 0x0u)>; + using RD_WRN = RegisterMask<CR2, (0x1u << 0xau)>; + using ADD10 = RegisterMask<CR2, (0x1u << 0xbu)>; + using HEAD10R = RegisterMask<CR2, (0x1u << 0xcu)>; + using START = RegisterMask<CR2, (0x1u << 0xdu)>; + using STOP = RegisterMask<CR2, (0x1u << 0xeu)>; + using NACK = RegisterMask<CR2, (0x1u << 0xfu)>; + using NBYTES = RegisterMask<CR2, (0xffu << 0x10u)>; + using RELOAD = RegisterMask<CR2, (0x1u << 0x18u)>; + using AUTOEND = RegisterMask<CR2, (0x1u << 0x19u)>; + }; + struct OAR1 : public MemRegister<uint32_t, 0x40008808> { + using OA1 = RegisterMask<OAR1, (0x3ffu << 0x0u)>; + using OA1MODE = RegisterMask<OAR1, (0x1u << 0xau)>; + using OA1EN = RegisterMask<OAR1, (0x1u << 0xfu)>; + }; + struct OAR2 : public MemRegister<uint32_t, 0x4000880c> { + using OA2 = RegisterMask<OAR2, (0x7fu << 0x1u)>; + using OA2MSK = RegisterMask<OAR2, (0x7u << 0x8u)>; + using OA2EN = RegisterMask<OAR2, (0x1u << 0xfu)>; + }; + struct TIMINGR : public MemRegister<uint32_t, 0x40008810> { + using SCLL = RegisterMask<TIMINGR, (0xffu << 0x0u)>; + using SCLH = RegisterMask<TIMINGR, (0xffu << 0x8u)>; + using SDADEL = RegisterMask<TIMINGR, (0xfu << 0x10u)>; + using SCLDEL = RegisterMask<TIMINGR, (0xfu << 0x14u)>; + using PRESC = RegisterMask<TIMINGR, (0xfu << 0x1cu)>; + }; + struct TIMEOUTR : public MemRegister<uint32_t, 0x40008814> { + using TIMEOUTA = RegisterMask<TIMEOUTR, (0xfffu << 0x0u)>; + using TIDLE = RegisterMask<TIMEOUTR, (0x1u << 0xcu)>; + using TIMOUTEN = RegisterMask<TIMEOUTR, (0x1u << 0xfu)>; + using TIMEOUTB = RegisterMask<TIMEOUTR, (0xfffu << 0x10u)>; + using TEXTEN = RegisterMask<TIMEOUTR, (0x1u << 0x1fu)>; + }; + struct ISR : public MemRegister<uint32_t, 0x40008818> { + using TXE = RegisterMask<ISR, (0x1u << 0x0u)>; + using TXIS = RegisterMask<ISR, (0x1u << 0x1u)>; + using RXNE = RegisterMask<ISR, (0x1u << 0x2u)>; + using ADDR = RegisterMask<ISR, (0x1u << 0x3u)>; + using NACKF = RegisterMask<ISR, (0x1u << 0x4u)>; + using STOPF = RegisterMask<ISR, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR, (0x1u << 0x6u)>; + using TCR = RegisterMask<ISR, (0x1u << 0x7u)>; + using BERR = RegisterMask<ISR, (0x1u << 0x8u)>; + using ARLO = RegisterMask<ISR, (0x1u << 0x9u)>; + using OVR = RegisterMask<ISR, (0x1u << 0xau)>; + using BUSY = RegisterMask<ISR, (0x1u << 0xfu)>; + using DIR = RegisterMask<ISR, (0x1u << 0x10u)>; + using ADDCODE = RegisterMask<ISR, (0x7fu << 0x11u)>; + }; + struct ICR : public MemRegister<uint32_t, 0x4000881c> { + using ADDRCF = RegisterMask<ICR, (0x1u << 0x3u)>; + using NACKCF = RegisterMask<ICR, (0x1u << 0x4u)>; + using STOPCF = RegisterMask<ICR, (0x1u << 0x5u)>; + using BERRCF = RegisterMask<ICR, (0x1u << 0x8u)>; + using ARLOCF = RegisterMask<ICR, (0x1u << 0x9u)>; + using OVRCF = RegisterMask<ICR, (0x1u << 0xau)>; + }; + struct PECR : public MemRegister<uint32_t, 0x40008820> { + using PEC = RegisterMask<PECR, (0xffu << 0x0u)>; + }; + struct RXDR : public MemRegister<uint32_t, 0x40008824> { + using RXDATA = RegisterMask<RXDR, (0xffu << 0x0u)>; + }; + struct TXDR : public MemRegister<uint32_t, 0x40008828> { + using TXDATA = RegisterMask<TXDR, (0xffu << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR2, OAR1, OAR2, TIMINGR, TIMEOUTR, ISR, ICR, PECR, RXDR, TXDR>; + } + namespace IWDG { + struct KR : public MemRegister<uint32_t, 0x40003000> { + using KEY = RegisterMask<KR, (0xffffu << 0x0u)>; + }; + struct PR : public MemRegister<uint32_t, 0x40003004> { + using val = RegisterMask<PR, (0xfu << 0x0u)>; + }; + struct RLR : public MemRegister<uint32_t, 0x40003008> { + using RL = RegisterMask<RLR, (0xfffu << 0x0u)>; + }; + struct SR : public MemRegister<uint32_t, 0x4000300c> { + using PVU = RegisterMask<SR, (0x1u << 0x0u)>; + using RVU = RegisterMask<SR, (0x1u << 0x1u)>; + using WVU = RegisterMask<SR, (0x1u << 0x2u)>; + using EWU = RegisterMask<SR, (0x1u << 0x3u)>; + using ONF = RegisterMask<SR, (0x1u << 0x8u)>; + using EWIF = RegisterMask<SR, (0x1u << 0xeu)>; + }; + struct WINR : public MemRegister<uint32_t, 0x40003010> { + using WIN = RegisterMask<WINR, (0xfffu << 0x0u)>; + }; + struct EWCR : public MemRegister<uint32_t, 0x40003014> { + using EWIT = RegisterMask<EWCR, (0xfffu << 0x0u)>; + using EWIC = RegisterMask<EWCR, (0x1u << 0xeu)>; + using EWIE = RegisterMask<EWCR, (0x1u << 0xfu)>; + }; + using ALL = RegisterGroup<KR, PR, RLR, SR, WINR, EWCR>; + } + namespace LCD { + struct CR : public MemRegister<uint32_t, 0x40002400> { + using LCDEN = RegisterMask<CR, (0x1u << 0x0u)>; + using VSEL = RegisterMask<CR, (0x1u << 0x1u)>; + using DUTY = RegisterMask<CR, (0x7u << 0x2u)>; + using BIAS = RegisterMask<CR, (0x3u << 0x5u)>; + using MUX_SEG = RegisterMask<CR, (0x1u << 0x7u)>; + using BUFEN = RegisterMask<CR, (0x1u << 0x8u)>; + }; + struct FCR : public MemRegister<uint32_t, 0x40002404> { + using HD = RegisterMask<FCR, (0x1u << 0x0u)>; + using SOFIE = RegisterMask<FCR, (0x1u << 0x1u)>; + using UDDIE = RegisterMask<FCR, (0x1u << 0x3u)>; + using PON = RegisterMask<FCR, (0x7u << 0x4u)>; + using DEAD = RegisterMask<FCR, (0x7u << 0x7u)>; + using CC = RegisterMask<FCR, (0x7u << 0xau)>; + using BLINKF = RegisterMask<FCR, (0x7u << 0xdu)>; + using BLINK = RegisterMask<FCR, (0x3u << 0x10u)>; + using DIV = RegisterMask<FCR, (0xfu << 0x12u)>; + using PS = RegisterMask<FCR, (0xfu << 0x16u)>; + }; + struct SR : public MemRegister<uint32_t, 0x40002408> { + using ENS = RegisterMask<SR, (0x1u << 0x0u)>; + using SOF = RegisterMask<SR, (0x1u << 0x1u)>; + using UDR = RegisterMask<SR, (0x1u << 0x2u)>; + using UDD = RegisterMask<SR, (0x1u << 0x3u)>; + using RDY = RegisterMask<SR, (0x1u << 0x4u)>; + using FCRSF = RegisterMask<SR, (0x1u << 0x5u)>; + }; + struct CLR : public MemRegister<uint32_t, 0x4000240c> { + using SOFC = RegisterMask<CLR, (0x1u << 0x1u)>; + using UDDC = RegisterMask<CLR, (0x1u << 0x3u)>; + }; + struct RAM0 : public MemRegister<uint32_t, 0x40002414> { + using SEGMENT_DATA = RegisterMask<RAM0, (0x0u << 0x0u)>; + }; + struct RAM1 : public MemRegister<uint32_t, 0x40002418> { + using SEGMENT_DATA = RegisterMask<RAM1, (0xfffffu << 0x0u)>; + }; + struct RAM2 : public MemRegister<uint32_t, 0x4000241c> { + using SEGMENT_DATA = RegisterMask<RAM2, (0x0u << 0x0u)>; + }; + struct RAM3 : public MemRegister<uint32_t, 0x40002420> { + using SEGMENT_DATA = RegisterMask<RAM3, (0xfffffu << 0x0u)>; + }; + struct RAM4 : public MemRegister<uint32_t, 0x40002424> { + using SEGMENT_DATA = RegisterMask<RAM4, (0x0u << 0x0u)>; + }; + struct RAM5 : public MemRegister<uint32_t, 0x40002428> { + using SEGMENT_DATA = RegisterMask<RAM5, (0xfffffu << 0x0u)>; + }; + struct RAM6 : public MemRegister<uint32_t, 0x4000242c> { + using SEGMENT_DATA = RegisterMask<RAM6, (0x0u << 0x0u)>; + }; + struct RAM7 : public MemRegister<uint32_t, 0x40002430> { + using SEGMENT_DATA = RegisterMask<RAM7, (0xfffffu << 0x0u)>; + }; + struct RAM8 : public MemRegister<uint32_t, 0x40002434> { + using SEGMENT_DATA = RegisterMask<RAM8, (0x0u << 0x0u)>; + }; + struct RAM9 : public MemRegister<uint32_t, 0x40002438> { + using SEGMENT_DATA = RegisterMask<RAM9, (0xffffu << 0x0u)>; + }; + struct RAM10 : public MemRegister<uint32_t, 0x4000243c> { + using SEGMENT_DATA = RegisterMask<RAM10, (0x0u << 0x0u)>; + }; + struct RAM11 : public MemRegister<uint32_t, 0x40002440> { + using SEGMENT_DATA = RegisterMask<RAM11, (0xffffu << 0x0u)>; + }; + struct RAM12 : public MemRegister<uint32_t, 0x40002444> { + using SEGMENT_DATA = RegisterMask<RAM12, (0x0u << 0x0u)>; + }; + struct RAM13 : public MemRegister<uint32_t, 0x40002448> { + using SEGMENT_DATA = RegisterMask<RAM13, (0xffffu << 0x0u)>; + }; + struct RAM14 : public MemRegister<uint32_t, 0x4000244c> { + using SEGMENT_DATA = RegisterMask<RAM14, (0x0u << 0x0u)>; + }; + struct RAM15 : public MemRegister<uint32_t, 0x40002450> { + using SEGMENT_DATA = RegisterMask<RAM15, (0xffffu << 0x0u)>; + }; + using ALL = RegisterGroup<CR, FCR, SR, CLR, RAM0, RAM1, RAM2, RAM3, RAM4, RAM5, RAM6, RAM7, RAM8, RAM9, RAM10, RAM11, RAM12, RAM13, RAM14, RAM15>; + } + namespace LPTIM1 { + struct LPTIM1_ISR_OUTPUT : public MemRegister<uint32_t, 0x40007c00> { + using CC1IF = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x0u)>; + using ARRM = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x1u)>; + using EXTTRIG = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x2u)>; + using CMP1OK = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x3u)>; + using ARROK = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x4u)>; + using UP = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x5u)>; + using DOWN = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x6u)>; + using UE = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x7u)>; + using REPOK = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x8u)>; + using CC2IF = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x9u)>; + using CC3IF = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0xau)>; + using CC4IF = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0xbu)>; + using CMP2OK = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x13u)>; + using CMP3OK = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x14u)>; + using CMP4OK = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x15u)>; + using DIEROK = RegisterMask<LPTIM1_ISR_OUTPUT, (0x1u << 0x18u)>; + }; + struct LPTIM1_ISR_INPUT : public MemRegister<uint32_t, 0x40007c00> { + using CC1IF = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0x0u)>; + using ARRM = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0x1u)>; + using EXTTRIG = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0x2u)>; + using ARROK = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0x4u)>; + using UP = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0x5u)>; + using DOWN = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0x6u)>; + using UE = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0x7u)>; + using REPOK = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0x8u)>; + using CC2IF = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0x9u)>; + using CC3IF = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0xau)>; + using CC4IF = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0xbu)>; + using CC1OF = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0xcu)>; + using CC2OF = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0xdu)>; + using CC3OF = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0xeu)>; + using CC4OF = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0xfu)>; + using DIEROK = RegisterMask<LPTIM1_ISR_INPUT, (0x1u << 0x18u)>; + }; + struct LPTIM1_ICR_OUTPUT : public MemRegister<uint32_t, 0x40007c04> { + using CC1CF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x0u)>; + using ARRMCF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x1u)>; + using EXTTRIGCF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x2u)>; + using CMP1OKCF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x3u)>; + using ARROKCF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x4u)>; + using UPCF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x5u)>; + using DOWNCF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x6u)>; + using UECF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x7u)>; + using REPOKCF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x8u)>; + using CC2CF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x9u)>; + using CC3CF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0xau)>; + using CC4CF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0xbu)>; + using CMP2OKCF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x13u)>; + using CMP3OKCF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x14u)>; + using CMP4OKCF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x15u)>; + using DIEROKCF = RegisterMask<LPTIM1_ICR_OUTPUT, (0x1u << 0x18u)>; + }; + struct LPTIM1_ICR_INPUT : public MemRegister<uint32_t, 0x40007c04> { + using CC1CF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0x0u)>; + using ARRMCF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0x1u)>; + using EXTTRIGCF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0x2u)>; + using ARROKCF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0x4u)>; + using UPCF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0x5u)>; + using DOWNCF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0x6u)>; + using UECF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0x7u)>; + using REPOKCF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0x8u)>; + using CC2CF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0x9u)>; + using CC3CF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0xau)>; + using CC4CF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0xbu)>; + using CC1OCF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0xcu)>; + using CC2OCF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0xdu)>; + using CC3OCF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0xeu)>; + using CC4OCF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0xfu)>; + using DIEROKCF = RegisterMask<LPTIM1_ICR_INPUT, (0x1u << 0x18u)>; + }; + struct LPTIM1_DIER_OUTPUT : public MemRegister<uint32_t, 0x40007c08> { + using CC1IE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x0u)>; + using ARRMIE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x1u)>; + using EXTTRIGIE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x2u)>; + using CMP1OKIE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x3u)>; + using ARROKIE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x4u)>; + using UPIE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x5u)>; + using DOWNIE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x6u)>; + using UEIE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x7u)>; + using REPOKIE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x8u)>; + using CC2IE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x9u)>; + using CC3IE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0xau)>; + using CC4IE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0xbu)>; + using CMP2OKIE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x13u)>; + using CMP3OKIE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x14u)>; + using CMP4OKIE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x15u)>; + using UEDE = RegisterMask<LPTIM1_DIER_OUTPUT, (0x1u << 0x17u)>; + }; + struct LPTIM1_DIER_INPUT : public MemRegister<uint32_t, 0x40007c08> { + using CC1IE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x0u)>; + using ARRMIE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x1u)>; + using EXTTRIGIE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x2u)>; + using ARROKIE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x4u)>; + using UPIE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x5u)>; + using DOWNIE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x6u)>; + using UEIE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x7u)>; + using REPOKIE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x8u)>; + using CC2IE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x9u)>; + using CC3IE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0xau)>; + using CC4IE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0xbu)>; + using CC1OIE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0xcu)>; + using CC2OIE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0xdu)>; + using CC3OIE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0xeu)>; + using CC4OIE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0xfu)>; + using CC1DE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x10u)>; + using UEDE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x17u)>; + using CC2DE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x19u)>; + using CC3DE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x1au)>; + using CC4DE = RegisterMask<LPTIM1_DIER_INPUT, (0x1u << 0x1bu)>; + }; + struct LPTIM1_CFGR : public MemRegister<uint32_t, 0x40007c0c> { + using CKSEL = RegisterMask<LPTIM1_CFGR, (0x1u << 0x0u)>; + using CKPOL = RegisterMask<LPTIM1_CFGR, (0x3u << 0x1u)>; + using CKFLT = RegisterMask<LPTIM1_CFGR, (0x3u << 0x3u)>; + using TRGFLT = RegisterMask<LPTIM1_CFGR, (0x3u << 0x6u)>; + using PRESC = RegisterMask<LPTIM1_CFGR, (0x7u << 0x9u)>; + using TRIGSEL = RegisterMask<LPTIM1_CFGR, (0x7u << 0xdu)>; + using TRIGEN = RegisterMask<LPTIM1_CFGR, (0x3u << 0x11u)>; + using TIMOUT = RegisterMask<LPTIM1_CFGR, (0x1u << 0x13u)>; + using WAVE = RegisterMask<LPTIM1_CFGR, (0x1u << 0x14u)>; + using PRELOAD = RegisterMask<LPTIM1_CFGR, (0x1u << 0x16u)>; + using COUNTMODE = RegisterMask<LPTIM1_CFGR, (0x1u << 0x17u)>; + using ENC = RegisterMask<LPTIM1_CFGR, (0x1u << 0x18u)>; + }; + struct LPTIM1_CR : public MemRegister<uint32_t, 0x40007c10> { + using ENABLE = RegisterMask<LPTIM1_CR, (0x1u << 0x0u)>; + using SNGSTRT = RegisterMask<LPTIM1_CR, (0x1u << 0x1u)>; + using CNTSTRT = RegisterMask<LPTIM1_CR, (0x1u << 0x2u)>; + using COUNTRST = RegisterMask<LPTIM1_CR, (0x1u << 0x3u)>; + using RSTARE = RegisterMask<LPTIM1_CR, (0x1u << 0x4u)>; + }; + struct LPTIM1_CCR1 : public MemRegister<uint32_t, 0x40007c14> { + using CCR1 = RegisterMask<LPTIM1_CCR1, (0xffffu << 0x0u)>; + }; + struct LPTIM1_ARR : public MemRegister<uint32_t, 0x40007c18> { + using ARR = RegisterMask<LPTIM1_ARR, (0xffffu << 0x0u)>; + }; + struct LPTIM1_CNT : public MemRegister<uint32_t, 0x40007c1c> { + using CNT = RegisterMask<LPTIM1_CNT, (0xffffu << 0x0u)>; + }; + struct LPTIM1_CFGR2 : public MemRegister<uint32_t, 0x40007c24> { + using IN1SEL = RegisterMask<LPTIM1_CFGR2, (0x3u << 0x0u)>; + using IN2SEL = RegisterMask<LPTIM1_CFGR2, (0x3u << 0x4u)>; + using IC1SEL = RegisterMask<LPTIM1_CFGR2, (0x3u << 0x10u)>; + using IC2SEL = RegisterMask<LPTIM1_CFGR2, (0x3u << 0x14u)>; + }; + struct LPTIM1_RCR : public MemRegister<uint32_t, 0x40007c28> { + using REP = RegisterMask<LPTIM1_RCR, (0xffu << 0x0u)>; + }; + struct LPTIM1_CCMR1 : public MemRegister<uint32_t, 0x40007c2c> { + using CC1SEL = RegisterMask<LPTIM1_CCMR1, (0x1u << 0x0u)>; + using CC1E = RegisterMask<LPTIM1_CCMR1, (0x1u << 0x1u)>; + using CC1P = RegisterMask<LPTIM1_CCMR1, (0x3u << 0x2u)>; + using IC1PSC = RegisterMask<LPTIM1_CCMR1, (0x3u << 0x8u)>; + using IC1F = RegisterMask<LPTIM1_CCMR1, (0x3u << 0xcu)>; + using CC2SEL = RegisterMask<LPTIM1_CCMR1, (0x1u << 0x10u)>; + using CC2E = RegisterMask<LPTIM1_CCMR1, (0x1u << 0x11u)>; + using CC2P = RegisterMask<LPTIM1_CCMR1, (0x3u << 0x12u)>; + using IC2PSC = RegisterMask<LPTIM1_CCMR1, (0x3u << 0x18u)>; + using IC2F = RegisterMask<LPTIM1_CCMR1, (0x3u << 0x1cu)>; + }; + struct LPTIM1_CCMR2 : public MemRegister<uint32_t, 0x40007c30> { + using CC3SEL = RegisterMask<LPTIM1_CCMR2, (0x1u << 0x0u)>; + using CC3E = RegisterMask<LPTIM1_CCMR2, (0x1u << 0x1u)>; + using CC3P = RegisterMask<LPTIM1_CCMR2, (0x3u << 0x2u)>; + using IC3PSC = RegisterMask<LPTIM1_CCMR2, (0x3u << 0x8u)>; + using IC3F = RegisterMask<LPTIM1_CCMR2, (0x3u << 0xcu)>; + using CC4SEL = RegisterMask<LPTIM1_CCMR2, (0x1u << 0x10u)>; + using CC4E = RegisterMask<LPTIM1_CCMR2, (0x1u << 0x11u)>; + using CC4P = RegisterMask<LPTIM1_CCMR2, (0x3u << 0x12u)>; + using IC4PSC = RegisterMask<LPTIM1_CCMR2, (0x3u << 0x18u)>; + using IC4F = RegisterMask<LPTIM1_CCMR2, (0x3u << 0x1cu)>; + }; + struct LPTIM1_CCR2 : public MemRegister<uint32_t, 0x40007c34> { + using CCR2 = RegisterMask<LPTIM1_CCR2, (0xffffu << 0x0u)>; + }; + struct LPTIM1_CCR3 : public MemRegister<uint32_t, 0x40007c38> { + using CCR3 = RegisterMask<LPTIM1_CCR3, (0xffffu << 0x0u)>; + }; + struct LPTIM1_CCR4 : public MemRegister<uint32_t, 0x40007c3c> { + using CCR4 = RegisterMask<LPTIM1_CCR4, (0xffffu << 0x0u)>; + }; + using ALL = RegisterGroup<LPTIM1_ISR_OUTPUT, LPTIM1_ISR_INPUT, LPTIM1_ICR_OUTPUT, LPTIM1_ICR_INPUT, LPTIM1_DIER_OUTPUT, LPTIM1_DIER_INPUT, LPTIM1_CFGR, LPTIM1_CR, LPTIM1_CCR1, LPTIM1_ARR, LPTIM1_CNT, LPTIM1_CFGR2, LPTIM1_RCR, LPTIM1_CCMR1, LPTIM1_CCMR2, LPTIM1_CCR2, LPTIM1_CCR3, LPTIM1_CCR4>; + } + namespace LPTIM2 { + struct LPTIM2_ISR_OUTPUT : public MemRegister<uint32_t, 0x40009400> { + using CC1IF = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x0u)>; + using ARRM = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x1u)>; + using EXTTRIG = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x2u)>; + using CMP1OK = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x3u)>; + using ARROK = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x4u)>; + using UP = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x5u)>; + using DOWN = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x6u)>; + using UE = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x7u)>; + using REPOK = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x8u)>; + using CC2IF = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x9u)>; + using CC3IF = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0xau)>; + using CC4IF = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0xbu)>; + using CMP2OK = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x13u)>; + using CMP3OK = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x14u)>; + using CMP4OK = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x15u)>; + using DIEROK = RegisterMask<LPTIM2_ISR_OUTPUT, (0x1u << 0x18u)>; + }; + struct LPTIM2_ISR_INPUT : public MemRegister<uint32_t, 0x40009400> { + using CC1IF = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0x0u)>; + using ARRM = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0x1u)>; + using EXTTRIG = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0x2u)>; + using ARROK = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0x4u)>; + using UP = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0x5u)>; + using DOWN = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0x6u)>; + using UE = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0x7u)>; + using REPOK = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0x8u)>; + using CC2IF = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0x9u)>; + using CC3IF = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0xau)>; + using CC4IF = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0xbu)>; + using CC1OF = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0xcu)>; + using CC2OF = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0xdu)>; + using CC3OF = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0xeu)>; + using CC4OF = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0xfu)>; + using DIEROK = RegisterMask<LPTIM2_ISR_INPUT, (0x1u << 0x18u)>; + }; + struct LPTIM2_ICR_OUTPUT : public MemRegister<uint32_t, 0x40009404> { + using CC1CF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x0u)>; + using ARRMCF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x1u)>; + using EXTTRIGCF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x2u)>; + using CMP1OKCF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x3u)>; + using ARROKCF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x4u)>; + using UPCF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x5u)>; + using DOWNCF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x6u)>; + using UECF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x7u)>; + using REPOKCF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x8u)>; + using CC2CF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x9u)>; + using CC3CF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0xau)>; + using CC4CF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0xbu)>; + using CMP2OKCF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x13u)>; + using CMP3OKCF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x14u)>; + using CMP4OKCF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x15u)>; + using DIEROKCF = RegisterMask<LPTIM2_ICR_OUTPUT, (0x1u << 0x18u)>; + }; + struct LPTIM2_ICR_INPUT : public MemRegister<uint32_t, 0x40009404> { + using CC1CF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0x0u)>; + using ARRMCF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0x1u)>; + using EXTTRIGCF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0x2u)>; + using ARROKCF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0x4u)>; + using UPCF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0x5u)>; + using DOWNCF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0x6u)>; + using UECF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0x7u)>; + using REPOKCF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0x8u)>; + using CC2CF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0x9u)>; + using CC3CF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0xau)>; + using CC4CF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0xbu)>; + using CC1OCF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0xcu)>; + using CC2OCF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0xdu)>; + using CC3OCF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0xeu)>; + using CC4OCF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0xfu)>; + using DIEROKCF = RegisterMask<LPTIM2_ICR_INPUT, (0x1u << 0x18u)>; + }; + struct LPTIM2_DIER_OUTPUT : public MemRegister<uint32_t, 0x40009408> { + using CC1IE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x0u)>; + using ARRMIE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x1u)>; + using EXTTRIGIE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x2u)>; + using CMP1OKIE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x3u)>; + using ARROKIE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x4u)>; + using UPIE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x5u)>; + using DOWNIE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x6u)>; + using UEIE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x7u)>; + using REPOKIE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x8u)>; + using CC2IE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x9u)>; + using CC3IE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0xau)>; + using CC4IE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0xbu)>; + using CMP2OKIE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x13u)>; + using CMP3OKIE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x14u)>; + using CMP4OKIE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x15u)>; + using UEDE = RegisterMask<LPTIM2_DIER_OUTPUT, (0x1u << 0x17u)>; + }; + struct LPTIM2_DIER_INPUT : public MemRegister<uint32_t, 0x40009408> { + using CC1IE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x0u)>; + using ARRMIE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x1u)>; + using EXTTRIGIE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x2u)>; + using ARROKIE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x4u)>; + using UPIE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x5u)>; + using DOWNIE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x6u)>; + using UEIE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x7u)>; + using REPOKIE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x8u)>; + using CC2IE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x9u)>; + using CC3IE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0xau)>; + using CC4IE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0xbu)>; + using CC1OIE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0xcu)>; + using CC2OIE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0xdu)>; + using CC3OIE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0xeu)>; + using CC4OIE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0xfu)>; + using CC1DE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x10u)>; + using UEDE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x17u)>; + using CC2DE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x19u)>; + using CC3DE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x1au)>; + using CC4DE = RegisterMask<LPTIM2_DIER_INPUT, (0x1u << 0x1bu)>; + }; + struct LPTIM2_CFGR : public MemRegister<uint32_t, 0x4000940c> { + using CKSEL = RegisterMask<LPTIM2_CFGR, (0x1u << 0x0u)>; + using CKPOL = RegisterMask<LPTIM2_CFGR, (0x3u << 0x1u)>; + using CKFLT = RegisterMask<LPTIM2_CFGR, (0x3u << 0x3u)>; + using TRGFLT = RegisterMask<LPTIM2_CFGR, (0x3u << 0x6u)>; + using PRESC = RegisterMask<LPTIM2_CFGR, (0x7u << 0x9u)>; + using TRIGSEL = RegisterMask<LPTIM2_CFGR, (0x7u << 0xdu)>; + using TRIGEN = RegisterMask<LPTIM2_CFGR, (0x3u << 0x11u)>; + using TIMOUT = RegisterMask<LPTIM2_CFGR, (0x1u << 0x13u)>; + using WAVE = RegisterMask<LPTIM2_CFGR, (0x1u << 0x14u)>; + using PRELOAD = RegisterMask<LPTIM2_CFGR, (0x1u << 0x16u)>; + using COUNTMODE = RegisterMask<LPTIM2_CFGR, (0x1u << 0x17u)>; + using ENC = RegisterMask<LPTIM2_CFGR, (0x1u << 0x18u)>; + }; + struct LPTIM2_CR : public MemRegister<uint32_t, 0x40009410> { + using ENABLE = RegisterMask<LPTIM2_CR, (0x1u << 0x0u)>; + using SNGSTRT = RegisterMask<LPTIM2_CR, (0x1u << 0x1u)>; + using CNTSTRT = RegisterMask<LPTIM2_CR, (0x1u << 0x2u)>; + using COUNTRST = RegisterMask<LPTIM2_CR, (0x1u << 0x3u)>; + using RSTARE = RegisterMask<LPTIM2_CR, (0x1u << 0x4u)>; + }; + struct LPTIM2_CCR1 : public MemRegister<uint32_t, 0x40009414> { + using CCR1 = RegisterMask<LPTIM2_CCR1, (0xffffu << 0x0u)>; + }; + struct LPTIM2_ARR : public MemRegister<uint32_t, 0x40009418> { + using ARR = RegisterMask<LPTIM2_ARR, (0xffffu << 0x0u)>; + }; + struct LPTIM2_CNT : public MemRegister<uint32_t, 0x4000941c> { + using CNT = RegisterMask<LPTIM2_CNT, (0xffffu << 0x0u)>; + }; + struct LPTIM2_CFGR2 : public MemRegister<uint32_t, 0x40009424> { + using IN1SEL = RegisterMask<LPTIM2_CFGR2, (0x3u << 0x0u)>; + using IN2SEL = RegisterMask<LPTIM2_CFGR2, (0x3u << 0x4u)>; + using IC1SEL = RegisterMask<LPTIM2_CFGR2, (0x3u << 0x10u)>; + using IC2SEL = RegisterMask<LPTIM2_CFGR2, (0x3u << 0x14u)>; + }; + struct LPTIM2_RCR : public MemRegister<uint32_t, 0x40009428> { + using REP = RegisterMask<LPTIM2_RCR, (0xffu << 0x0u)>; + }; + struct LPTIM2_CCMR1 : public MemRegister<uint32_t, 0x4000942c> { + using CC1SEL = RegisterMask<LPTIM2_CCMR1, (0x1u << 0x0u)>; + using CC1E = RegisterMask<LPTIM2_CCMR1, (0x1u << 0x1u)>; + using CC1P = RegisterMask<LPTIM2_CCMR1, (0x3u << 0x2u)>; + using IC1PSC = RegisterMask<LPTIM2_CCMR1, (0x3u << 0x8u)>; + using IC1F = RegisterMask<LPTIM2_CCMR1, (0x3u << 0xcu)>; + using CC2SEL = RegisterMask<LPTIM2_CCMR1, (0x1u << 0x10u)>; + using CC2E = RegisterMask<LPTIM2_CCMR1, (0x1u << 0x11u)>; + using CC2P = RegisterMask<LPTIM2_CCMR1, (0x3u << 0x12u)>; + using IC2PSC = RegisterMask<LPTIM2_CCMR1, (0x3u << 0x18u)>; + using IC2F = RegisterMask<LPTIM2_CCMR1, (0x3u << 0x1cu)>; + }; + struct LPTIM2_CCMR2 : public MemRegister<uint32_t, 0x40009430> { + using CC3SEL = RegisterMask<LPTIM2_CCMR2, (0x1u << 0x0u)>; + using CC3E = RegisterMask<LPTIM2_CCMR2, (0x1u << 0x1u)>; + using CC3P = RegisterMask<LPTIM2_CCMR2, (0x3u << 0x2u)>; + using IC3PSC = RegisterMask<LPTIM2_CCMR2, (0x3u << 0x8u)>; + using IC3F = RegisterMask<LPTIM2_CCMR2, (0x3u << 0xcu)>; + using CC4SEL = RegisterMask<LPTIM2_CCMR2, (0x1u << 0x10u)>; + using CC4E = RegisterMask<LPTIM2_CCMR2, (0x1u << 0x11u)>; + using CC4P = RegisterMask<LPTIM2_CCMR2, (0x3u << 0x12u)>; + using IC4PSC = RegisterMask<LPTIM2_CCMR2, (0x3u << 0x18u)>; + using IC4F = RegisterMask<LPTIM2_CCMR2, (0x3u << 0x1cu)>; + }; + struct LPTIM2_CCR2 : public MemRegister<uint32_t, 0x40009434> { + using CCR2 = RegisterMask<LPTIM2_CCR2, (0xffffu << 0x0u)>; + }; + struct LPTIM2_CCR3 : public MemRegister<uint32_t, 0x40009438> { + using CCR3 = RegisterMask<LPTIM2_CCR3, (0xffffu << 0x0u)>; + }; + struct LPTIM2_CCR4 : public MemRegister<uint32_t, 0x4000943c> { + using CCR4 = RegisterMask<LPTIM2_CCR4, (0xffffu << 0x0u)>; + }; + using ALL = RegisterGroup<LPTIM2_ISR_OUTPUT, LPTIM2_ISR_INPUT, LPTIM2_ICR_OUTPUT, LPTIM2_ICR_INPUT, LPTIM2_DIER_OUTPUT, LPTIM2_DIER_INPUT, LPTIM2_CFGR, LPTIM2_CR, LPTIM2_CCR1, LPTIM2_ARR, LPTIM2_CNT, LPTIM2_CFGR2, LPTIM2_RCR, LPTIM2_CCMR1, LPTIM2_CCMR2, LPTIM2_CCR2, LPTIM2_CCR3, LPTIM2_CCR4>; + } + namespace LPTIM3 { + struct LPTIM3_ISR_OUTPUT : public MemRegister<uint32_t, 0x40009000> { + using CC1IF = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x0u)>; + using ARRM = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x1u)>; + using EXTTRIG = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x2u)>; + using CMP1OK = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x3u)>; + using ARROK = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x4u)>; + using UP = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x5u)>; + using DOWN = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x6u)>; + using UE = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x7u)>; + using REPOK = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x8u)>; + using CC2IF = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x9u)>; + using CC3IF = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0xau)>; + using CC4IF = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0xbu)>; + using CMP2OK = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x13u)>; + using CMP3OK = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x14u)>; + using CMP4OK = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x15u)>; + using DIEROK = RegisterMask<LPTIM3_ISR_OUTPUT, (0x1u << 0x18u)>; + }; + struct LPTIM3_ISR_INPUT : public MemRegister<uint32_t, 0x40009000> { + using CC1IF = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0x0u)>; + using ARRM = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0x1u)>; + using EXTTRIG = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0x2u)>; + using ARROK = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0x4u)>; + using UP = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0x5u)>; + using DOWN = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0x6u)>; + using UE = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0x7u)>; + using REPOK = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0x8u)>; + using CC2IF = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0x9u)>; + using CC3IF = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0xau)>; + using CC4IF = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0xbu)>; + using CC1OF = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0xcu)>; + using CC2OF = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0xdu)>; + using CC3OF = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0xeu)>; + using CC4OF = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0xfu)>; + using DIEROK = RegisterMask<LPTIM3_ISR_INPUT, (0x1u << 0x18u)>; + }; + struct LPTIM3_ICR_OUTPUT : public MemRegister<uint32_t, 0x40009004> { + using CC1CF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x0u)>; + using ARRMCF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x1u)>; + using EXTTRIGCF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x2u)>; + using CMP1OKCF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x3u)>; + using ARROKCF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x4u)>; + using UPCF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x5u)>; + using DOWNCF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x6u)>; + using UECF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x7u)>; + using REPOKCF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x8u)>; + using CC2CF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x9u)>; + using CC3CF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0xau)>; + using CC4CF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0xbu)>; + using CMP2OKCF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x13u)>; + using CMP3OKCF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x14u)>; + using CMP4OKCF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x15u)>; + using DIEROKCF = RegisterMask<LPTIM3_ICR_OUTPUT, (0x1u << 0x18u)>; + }; + struct LPTIM3_ICR_INPUT : public MemRegister<uint32_t, 0x40009004> { + using CC1CF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0x0u)>; + using ARRMCF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0x1u)>; + using EXTTRIGCF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0x2u)>; + using ARROKCF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0x4u)>; + using UPCF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0x5u)>; + using DOWNCF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0x6u)>; + using UECF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0x7u)>; + using REPOKCF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0x8u)>; + using CC2CF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0x9u)>; + using CC3CF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0xau)>; + using CC4CF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0xbu)>; + using CC1OCF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0xcu)>; + using CC2OCF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0xdu)>; + using CC3OCF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0xeu)>; + using CC4OCF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0xfu)>; + using DIEROKCF = RegisterMask<LPTIM3_ICR_INPUT, (0x1u << 0x18u)>; + }; + struct LPTIM3_DIER_OUTPUT : public MemRegister<uint32_t, 0x40009008> { + using CC1IE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x0u)>; + using ARRMIE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x1u)>; + using EXTTRIGIE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x2u)>; + using CMP1OKIE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x3u)>; + using ARROKIE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x4u)>; + using UPIE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x5u)>; + using DOWNIE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x6u)>; + using UEIE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x7u)>; + using REPOKIE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x8u)>; + using CC2IE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x9u)>; + using CC3IE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0xau)>; + using CC4IE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0xbu)>; + using CMP2OKIE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x13u)>; + using CMP3OKIE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x14u)>; + using CMP4OKIE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x15u)>; + using UEDE = RegisterMask<LPTIM3_DIER_OUTPUT, (0x1u << 0x17u)>; + }; + struct LPTIM3_DIER_INPUT : public MemRegister<uint32_t, 0x40009008> { + using CC1IE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x0u)>; + using ARRMIE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x1u)>; + using EXTTRIGIE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x2u)>; + using ARROKIE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x4u)>; + using UPIE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x5u)>; + using DOWNIE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x6u)>; + using UEIE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x7u)>; + using REPOKIE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x8u)>; + using CC2IE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x9u)>; + using CC3IE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0xau)>; + using CC4IE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0xbu)>; + using CC1OIE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0xcu)>; + using CC2OIE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0xdu)>; + using CC3OIE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0xeu)>; + using CC4OIE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0xfu)>; + using CC1DE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x10u)>; + using UEDE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x17u)>; + using CC2DE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x19u)>; + using CC3DE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x1au)>; + using CC4DE = RegisterMask<LPTIM3_DIER_INPUT, (0x1u << 0x1bu)>; + }; + struct LPTIM3_CFGR : public MemRegister<uint32_t, 0x4000900c> { + using CKSEL = RegisterMask<LPTIM3_CFGR, (0x1u << 0x0u)>; + using CKPOL = RegisterMask<LPTIM3_CFGR, (0x3u << 0x1u)>; + using CKFLT = RegisterMask<LPTIM3_CFGR, (0x3u << 0x3u)>; + using TRGFLT = RegisterMask<LPTIM3_CFGR, (0x3u << 0x6u)>; + using PRESC = RegisterMask<LPTIM3_CFGR, (0x7u << 0x9u)>; + using TRIGSEL = RegisterMask<LPTIM3_CFGR, (0x7u << 0xdu)>; + using TRIGEN = RegisterMask<LPTIM3_CFGR, (0x3u << 0x11u)>; + using TIMOUT = RegisterMask<LPTIM3_CFGR, (0x1u << 0x13u)>; + using WAVE = RegisterMask<LPTIM3_CFGR, (0x1u << 0x14u)>; + using PRELOAD = RegisterMask<LPTIM3_CFGR, (0x1u << 0x16u)>; + using COUNTMODE = RegisterMask<LPTIM3_CFGR, (0x1u << 0x17u)>; + using ENC = RegisterMask<LPTIM3_CFGR, (0x1u << 0x18u)>; + }; + struct LPTIM3_CR : public MemRegister<uint32_t, 0x40009010> { + using ENABLE = RegisterMask<LPTIM3_CR, (0x1u << 0x0u)>; + using SNGSTRT = RegisterMask<LPTIM3_CR, (0x1u << 0x1u)>; + using CNTSTRT = RegisterMask<LPTIM3_CR, (0x1u << 0x2u)>; + using COUNTRST = RegisterMask<LPTIM3_CR, (0x1u << 0x3u)>; + using RSTARE = RegisterMask<LPTIM3_CR, (0x1u << 0x4u)>; + }; + struct LPTIM3_CCR1 : public MemRegister<uint32_t, 0x40009014> { + using CCR1 = RegisterMask<LPTIM3_CCR1, (0xffffu << 0x0u)>; + }; + struct LPTIM3_ARR : public MemRegister<uint32_t, 0x40009018> { + using ARR = RegisterMask<LPTIM3_ARR, (0xffffu << 0x0u)>; + }; + struct LPTIM3_CNT : public MemRegister<uint32_t, 0x4000901c> { + using CNT = RegisterMask<LPTIM3_CNT, (0xffffu << 0x0u)>; + }; + struct LPTIM3_CFGR2 : public MemRegister<uint32_t, 0x40009024> { + using IN1SEL = RegisterMask<LPTIM3_CFGR2, (0x3u << 0x0u)>; + using IN2SEL = RegisterMask<LPTIM3_CFGR2, (0x3u << 0x4u)>; + using IC1SEL = RegisterMask<LPTIM3_CFGR2, (0x3u << 0x10u)>; + using IC2SEL = RegisterMask<LPTIM3_CFGR2, (0x3u << 0x14u)>; + }; + struct LPTIM3_RCR : public MemRegister<uint32_t, 0x40009028> { + using REP = RegisterMask<LPTIM3_RCR, (0xffu << 0x0u)>; + }; + struct LPTIM3_CCMR1 : public MemRegister<uint32_t, 0x4000902c> { + using CC1SEL = RegisterMask<LPTIM3_CCMR1, (0x1u << 0x0u)>; + using CC1E = RegisterMask<LPTIM3_CCMR1, (0x1u << 0x1u)>; + using CC1P = RegisterMask<LPTIM3_CCMR1, (0x3u << 0x2u)>; + using IC1PSC = RegisterMask<LPTIM3_CCMR1, (0x3u << 0x8u)>; + using IC1F = RegisterMask<LPTIM3_CCMR1, (0x3u << 0xcu)>; + using CC2SEL = RegisterMask<LPTIM3_CCMR1, (0x1u << 0x10u)>; + using CC2E = RegisterMask<LPTIM3_CCMR1, (0x1u << 0x11u)>; + using CC2P = RegisterMask<LPTIM3_CCMR1, (0x3u << 0x12u)>; + using IC2PSC = RegisterMask<LPTIM3_CCMR1, (0x3u << 0x18u)>; + using IC2F = RegisterMask<LPTIM3_CCMR1, (0x3u << 0x1cu)>; + }; + struct LPTIM3_CCMR2 : public MemRegister<uint32_t, 0x40009030> { + using CC3SEL = RegisterMask<LPTIM3_CCMR2, (0x1u << 0x0u)>; + using CC3E = RegisterMask<LPTIM3_CCMR2, (0x1u << 0x1u)>; + using CC3P = RegisterMask<LPTIM3_CCMR2, (0x3u << 0x2u)>; + using IC3PSC = RegisterMask<LPTIM3_CCMR2, (0x3u << 0x8u)>; + using IC3F = RegisterMask<LPTIM3_CCMR2, (0x3u << 0xcu)>; + using CC4SEL = RegisterMask<LPTIM3_CCMR2, (0x1u << 0x10u)>; + using CC4E = RegisterMask<LPTIM3_CCMR2, (0x1u << 0x11u)>; + using CC4P = RegisterMask<LPTIM3_CCMR2, (0x3u << 0x12u)>; + using IC4PSC = RegisterMask<LPTIM3_CCMR2, (0x3u << 0x18u)>; + using IC4F = RegisterMask<LPTIM3_CCMR2, (0x3u << 0x1cu)>; + }; + struct LPTIM3_CCR2 : public MemRegister<uint32_t, 0x40009034> { + using CCR2 = RegisterMask<LPTIM3_CCR2, (0xffffu << 0x0u)>; + }; + struct LPTIM3_CCR3 : public MemRegister<uint32_t, 0x40009038> { + using CCR3 = RegisterMask<LPTIM3_CCR3, (0xffffu << 0x0u)>; + }; + struct LPTIM3_CCR4 : public MemRegister<uint32_t, 0x4000903c> { + using CCR4 = RegisterMask<LPTIM3_CCR4, (0xffffu << 0x0u)>; + }; + using ALL = RegisterGroup<LPTIM3_ISR_OUTPUT, LPTIM3_ISR_INPUT, LPTIM3_ICR_OUTPUT, LPTIM3_ICR_INPUT, LPTIM3_DIER_OUTPUT, LPTIM3_DIER_INPUT, LPTIM3_CFGR, LPTIM3_CR, LPTIM3_CCR1, LPTIM3_ARR, LPTIM3_CNT, LPTIM3_CFGR2, LPTIM3_RCR, LPTIM3_CCMR1, LPTIM3_CCMR2, LPTIM3_CCR2, LPTIM3_CCR3, LPTIM3_CCR4>; + } + namespace LPUART1 { + struct CR1 : public MemRegister<uint32_t, 0x40008000> { + using UE = RegisterMask<CR1, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1, (0x1u << 0x4u)>; + using RXFNEIE = RegisterMask<CR1, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1, (0x1u << 0x6u)>; + using TXFNFIE = RegisterMask<CR1, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1, (0x1u << 0xeu)>; + using DEDT = RegisterMask<CR1, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1, (0x1fu << 0x15u)>; + using M1 = RegisterMask<CR1, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1, (0x1u << 0x1du)>; + using TXFEIE = RegisterMask<CR1, (0x1u << 0x1eu)>; + using RXFFIE = RegisterMask<CR1, (0x1u << 0x1fu)>; + }; + struct CR1_ALTERNATE : public MemRegister<uint32_t, 0x40008000> { + using UE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x4u)>; + using RXNEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x6u)>; + using TXEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1_ALTERNATE, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1_ALTERNATE, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1_ALTERNATE, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xeu)>; + using DEDT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x15u)>; + using M1 = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1du)>; + }; + struct CR2 : public MemRegister<uint32_t, 0x40008004> { + using ADDM7 = RegisterMask<CR2, (0x1u << 0x4u)>; + using STOP = RegisterMask<CR2, (0x3u << 0xcu)>; + using SWAP = RegisterMask<CR2, (0x1u << 0xfu)>; + using RXINV = RegisterMask<CR2, (0x1u << 0x10u)>; + using TXINV = RegisterMask<CR2, (0x1u << 0x11u)>; + using DATAINV = RegisterMask<CR2, (0x1u << 0x12u)>; + using MSBFIRST = RegisterMask<CR2, (0x1u << 0x13u)>; + using ADD = RegisterMask<CR2, (0xffu << 0x18u)>; + }; + struct CR3 : public MemRegister<uint32_t, 0x40008008> { + using EIE = RegisterMask<CR3, (0x1u << 0x0u)>; + using HDSEL = RegisterMask<CR3, (0x1u << 0x3u)>; + using DMAR = RegisterMask<CR3, (0x1u << 0x6u)>; + using DMAT = RegisterMask<CR3, (0x1u << 0x7u)>; + using RTSE = RegisterMask<CR3, (0x1u << 0x8u)>; + using CTSE = RegisterMask<CR3, (0x1u << 0x9u)>; + using CTSIE = RegisterMask<CR3, (0x1u << 0xau)>; + using OVRDIS = RegisterMask<CR3, (0x1u << 0xcu)>; + using DDRE = RegisterMask<CR3, (0x1u << 0xdu)>; + using DEM = RegisterMask<CR3, (0x1u << 0xeu)>; + using DEP = RegisterMask<CR3, (0x1u << 0xfu)>; + using WUS0 = RegisterMask<CR3, (0x1u << 0x14u)>; + using WUS1 = RegisterMask<CR3, (0x1u << 0x15u)>; + using WUFIE = RegisterMask<CR3, (0x1u << 0x16u)>; + using TXFTIE = RegisterMask<CR3, (0x1u << 0x17u)>; + using RXFTCFG = RegisterMask<CR3, (0x7u << 0x19u)>; + using RXFTIE = RegisterMask<CR3, (0x1u << 0x1cu)>; + using TXFTCFG = RegisterMask<CR3, (0x7u << 0x1du)>; + }; + struct BRR : public MemRegister<uint32_t, 0x4000800c> { + using val = RegisterMask<BRR, (0xfffffu << 0x0u)>; + }; + struct RQR : public MemRegister<uint32_t, 0x40008018> { + using SBKRQ = RegisterMask<RQR, (0x1u << 0x1u)>; + using MMRQ = RegisterMask<RQR, (0x1u << 0x2u)>; + using RXFRQ = RegisterMask<RQR, (0x1u << 0x3u)>; + using TXFRQ = RegisterMask<RQR, (0x1u << 0x4u)>; + }; + struct ISR : public MemRegister<uint32_t, 0x4000801c> { + using PE = RegisterMask<ISR, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR, (0x1u << 0x4u)>; + using RXFNE = RegisterMask<ISR, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR, (0x1u << 0x6u)>; + using TXFNF = RegisterMask<ISR, (0x1u << 0x7u)>; + using CTSIF = RegisterMask<ISR, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR, (0x1u << 0xau)>; + using BUSY = RegisterMask<ISR, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR, (0x1u << 0x16u)>; + using TXFE = RegisterMask<ISR, (0x1u << 0x17u)>; + using RXFF = RegisterMask<ISR, (0x1u << 0x18u)>; + using RXFT = RegisterMask<ISR, (0x1u << 0x1au)>; + using TXFT = RegisterMask<ISR, (0x1u << 0x1bu)>; + }; + struct ISR_ALTERNATE : public MemRegister<uint32_t, 0x4000801c> { + using PE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x4u)>; + using RXNE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR_ALTERNATE, (0x1u << 0x6u)>; + using TXE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x7u)>; + using CTSIF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR_ALTERNATE, (0x1u << 0xau)>; + using BUSY = RegisterMask<ISR_ALTERNATE, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR_ALTERNATE, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x16u)>; + }; + struct ICR : public MemRegister<uint32_t, 0x40008020> { + using PECF = RegisterMask<ICR, (0x1u << 0x0u)>; + using FECF = RegisterMask<ICR, (0x1u << 0x1u)>; + using NECF = RegisterMask<ICR, (0x1u << 0x2u)>; + using ORECF = RegisterMask<ICR, (0x1u << 0x3u)>; + using IDLECF = RegisterMask<ICR, (0x1u << 0x4u)>; + using TCCF = RegisterMask<ICR, (0x1u << 0x6u)>; + using CTSCF = RegisterMask<ICR, (0x1u << 0x9u)>; + using CMCF = RegisterMask<ICR, (0x1u << 0x11u)>; + using WUCF = RegisterMask<ICR, (0x1u << 0x14u)>; + }; + struct RDR : public MemRegister<uint32_t, 0x40008024> { + using val = RegisterMask<RDR, (0x1ffu << 0x0u)>; + }; + struct TDR : public MemRegister<uint32_t, 0x40008028> { + using val = RegisterMask<TDR, (0x1ffu << 0x0u)>; + }; + struct PRESC : public MemRegister<uint32_t, 0x4000802c> { + using PRESCALER = RegisterMask<PRESC, (0xfu << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR1_ALTERNATE, CR2, CR3, BRR, RQR, ISR, ISR_ALTERNATE, ICR, RDR, TDR, PRESC>; + } + namespace LPUART2 { + struct CR1 : public MemRegister<uint32_t, 0x40008400> { + using UE = RegisterMask<CR1, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1, (0x1u << 0x4u)>; + using RXFNEIE = RegisterMask<CR1, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1, (0x1u << 0x6u)>; + using TXFNFIE = RegisterMask<CR1, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1, (0x1u << 0xeu)>; + using DEDT = RegisterMask<CR1, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1, (0x1fu << 0x15u)>; + using M1 = RegisterMask<CR1, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1, (0x1u << 0x1du)>; + using TXFEIE = RegisterMask<CR1, (0x1u << 0x1eu)>; + using RXFFIE = RegisterMask<CR1, (0x1u << 0x1fu)>; + }; + struct CR1_ALTERNATE : public MemRegister<uint32_t, 0x40008400> { + using UE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x4u)>; + using RXNEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x6u)>; + using TXEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1_ALTERNATE, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1_ALTERNATE, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1_ALTERNATE, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xeu)>; + using DEDT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x15u)>; + using M1 = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1du)>; + }; + struct CR2 : public MemRegister<uint32_t, 0x40008404> { + using ADDM7 = RegisterMask<CR2, (0x1u << 0x4u)>; + using STOP = RegisterMask<CR2, (0x3u << 0xcu)>; + using SWAP = RegisterMask<CR2, (0x1u << 0xfu)>; + using RXINV = RegisterMask<CR2, (0x1u << 0x10u)>; + using TXINV = RegisterMask<CR2, (0x1u << 0x11u)>; + using DATAINV = RegisterMask<CR2, (0x1u << 0x12u)>; + using MSBFIRST = RegisterMask<CR2, (0x1u << 0x13u)>; + using ADD = RegisterMask<CR2, (0xffu << 0x18u)>; + }; + struct CR3 : public MemRegister<uint32_t, 0x40008408> { + using EIE = RegisterMask<CR3, (0x1u << 0x0u)>; + using HDSEL = RegisterMask<CR3, (0x1u << 0x3u)>; + using DMAR = RegisterMask<CR3, (0x1u << 0x6u)>; + using DMAT = RegisterMask<CR3, (0x1u << 0x7u)>; + using RTSE = RegisterMask<CR3, (0x1u << 0x8u)>; + using CTSE = RegisterMask<CR3, (0x1u << 0x9u)>; + using CTSIE = RegisterMask<CR3, (0x1u << 0xau)>; + using OVRDIS = RegisterMask<CR3, (0x1u << 0xcu)>; + using DDRE = RegisterMask<CR3, (0x1u << 0xdu)>; + using DEM = RegisterMask<CR3, (0x1u << 0xeu)>; + using DEP = RegisterMask<CR3, (0x1u << 0xfu)>; + using WUS0 = RegisterMask<CR3, (0x1u << 0x14u)>; + using WUS1 = RegisterMask<CR3, (0x1u << 0x15u)>; + using WUFIE = RegisterMask<CR3, (0x1u << 0x16u)>; + using TXFTIE = RegisterMask<CR3, (0x1u << 0x17u)>; + using RXFTCFG = RegisterMask<CR3, (0x7u << 0x19u)>; + using RXFTIE = RegisterMask<CR3, (0x1u << 0x1cu)>; + using TXFTCFG = RegisterMask<CR3, (0x7u << 0x1du)>; + }; + struct BRR : public MemRegister<uint32_t, 0x4000840c> { + using val = RegisterMask<BRR, (0xfffffu << 0x0u)>; + }; + struct RQR : public MemRegister<uint32_t, 0x40008418> { + using SBKRQ = RegisterMask<RQR, (0x1u << 0x1u)>; + using MMRQ = RegisterMask<RQR, (0x1u << 0x2u)>; + using RXFRQ = RegisterMask<RQR, (0x1u << 0x3u)>; + using TXFRQ = RegisterMask<RQR, (0x1u << 0x4u)>; + }; + struct ISR : public MemRegister<uint32_t, 0x4000841c> { + using PE = RegisterMask<ISR, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR, (0x1u << 0x4u)>; + using RXFNE = RegisterMask<ISR, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR, (0x1u << 0x6u)>; + using TXFNF = RegisterMask<ISR, (0x1u << 0x7u)>; + using CTSIF = RegisterMask<ISR, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR, (0x1u << 0xau)>; + using BUSY = RegisterMask<ISR, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR, (0x1u << 0x16u)>; + using TXFE = RegisterMask<ISR, (0x1u << 0x17u)>; + using RXFF = RegisterMask<ISR, (0x1u << 0x18u)>; + using RXFT = RegisterMask<ISR, (0x1u << 0x1au)>; + using TXFT = RegisterMask<ISR, (0x1u << 0x1bu)>; + }; + struct ISR_ALTERNATE : public MemRegister<uint32_t, 0x4000841c> { + using PE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x4u)>; + using RXNE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR_ALTERNATE, (0x1u << 0x6u)>; + using TXE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x7u)>; + using CTSIF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR_ALTERNATE, (0x1u << 0xau)>; + using BUSY = RegisterMask<ISR_ALTERNATE, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR_ALTERNATE, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x16u)>; + }; + struct ICR : public MemRegister<uint32_t, 0x40008420> { + using PECF = RegisterMask<ICR, (0x1u << 0x0u)>; + using FECF = RegisterMask<ICR, (0x1u << 0x1u)>; + using NECF = RegisterMask<ICR, (0x1u << 0x2u)>; + using ORECF = RegisterMask<ICR, (0x1u << 0x3u)>; + using IDLECF = RegisterMask<ICR, (0x1u << 0x4u)>; + using TCCF = RegisterMask<ICR, (0x1u << 0x6u)>; + using CTSCF = RegisterMask<ICR, (0x1u << 0x9u)>; + using CMCF = RegisterMask<ICR, (0x1u << 0x11u)>; + using WUCF = RegisterMask<ICR, (0x1u << 0x14u)>; + }; + struct RDR : public MemRegister<uint32_t, 0x40008424> { + using val = RegisterMask<RDR, (0x1ffu << 0x0u)>; + }; + struct TDR : public MemRegister<uint32_t, 0x40008428> { + using val = RegisterMask<TDR, (0x1ffu << 0x0u)>; + }; + struct PRESC : public MemRegister<uint32_t, 0x4000842c> { + using PRESCALER = RegisterMask<PRESC, (0xfu << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR1_ALTERNATE, CR2, CR3, BRR, RQR, ISR, ISR_ALTERNATE, ICR, RDR, TDR, PRESC>; + } + namespace LPUART3 { + struct CR1 : public MemRegister<uint32_t, 0x40008c00> { + using UE = RegisterMask<CR1, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1, (0x1u << 0x4u)>; + using RXFNEIE = RegisterMask<CR1, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1, (0x1u << 0x6u)>; + using TXFNFIE = RegisterMask<CR1, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1, (0x1u << 0xeu)>; + using DEDT = RegisterMask<CR1, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1, (0x1fu << 0x15u)>; + using M1 = RegisterMask<CR1, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1, (0x1u << 0x1du)>; + using TXFEIE = RegisterMask<CR1, (0x1u << 0x1eu)>; + using RXFFIE = RegisterMask<CR1, (0x1u << 0x1fu)>; + }; + struct CR1_ALTERNATE : public MemRegister<uint32_t, 0x40008c00> { + using UE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x4u)>; + using RXNEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x6u)>; + using TXEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1_ALTERNATE, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1_ALTERNATE, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1_ALTERNATE, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xeu)>; + using DEDT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x15u)>; + using M1 = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1du)>; + }; + struct CR2 : public MemRegister<uint32_t, 0x40008c04> { + using ADDM7 = RegisterMask<CR2, (0x1u << 0x4u)>; + using STOP = RegisterMask<CR2, (0x3u << 0xcu)>; + using SWAP = RegisterMask<CR2, (0x1u << 0xfu)>; + using RXINV = RegisterMask<CR2, (0x1u << 0x10u)>; + using TXINV = RegisterMask<CR2, (0x1u << 0x11u)>; + using DATAINV = RegisterMask<CR2, (0x1u << 0x12u)>; + using MSBFIRST = RegisterMask<CR2, (0x1u << 0x13u)>; + using ADD = RegisterMask<CR2, (0xffu << 0x18u)>; + }; + struct CR3 : public MemRegister<uint32_t, 0x40008c08> { + using EIE = RegisterMask<CR3, (0x1u << 0x0u)>; + using HDSEL = RegisterMask<CR3, (0x1u << 0x3u)>; + using DMAR = RegisterMask<CR3, (0x1u << 0x6u)>; + using DMAT = RegisterMask<CR3, (0x1u << 0x7u)>; + using RTSE = RegisterMask<CR3, (0x1u << 0x8u)>; + using CTSE = RegisterMask<CR3, (0x1u << 0x9u)>; + using CTSIE = RegisterMask<CR3, (0x1u << 0xau)>; + using OVRDIS = RegisterMask<CR3, (0x1u << 0xcu)>; + using DDRE = RegisterMask<CR3, (0x1u << 0xdu)>; + using DEM = RegisterMask<CR3, (0x1u << 0xeu)>; + using DEP = RegisterMask<CR3, (0x1u << 0xfu)>; + using WUS0 = RegisterMask<CR3, (0x1u << 0x14u)>; + using WUS1 = RegisterMask<CR3, (0x1u << 0x15u)>; + using WUFIE = RegisterMask<CR3, (0x1u << 0x16u)>; + using TXFTIE = RegisterMask<CR3, (0x1u << 0x17u)>; + using RXFTCFG = RegisterMask<CR3, (0x7u << 0x19u)>; + using RXFTIE = RegisterMask<CR3, (0x1u << 0x1cu)>; + using TXFTCFG = RegisterMask<CR3, (0x7u << 0x1du)>; + }; + struct BRR : public MemRegister<uint32_t, 0x40008c0c> { + using val = RegisterMask<BRR, (0xfffffu << 0x0u)>; + }; + struct RQR : public MemRegister<uint32_t, 0x40008c18> { + using SBKRQ = RegisterMask<RQR, (0x1u << 0x1u)>; + using MMRQ = RegisterMask<RQR, (0x1u << 0x2u)>; + using RXFRQ = RegisterMask<RQR, (0x1u << 0x3u)>; + using TXFRQ = RegisterMask<RQR, (0x1u << 0x4u)>; + }; + struct ISR : public MemRegister<uint32_t, 0x40008c1c> { + using PE = RegisterMask<ISR, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR, (0x1u << 0x4u)>; + using RXFNE = RegisterMask<ISR, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR, (0x1u << 0x6u)>; + using TXFNF = RegisterMask<ISR, (0x1u << 0x7u)>; + using CTSIF = RegisterMask<ISR, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR, (0x1u << 0xau)>; + using BUSY = RegisterMask<ISR, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR, (0x1u << 0x16u)>; + using TXFE = RegisterMask<ISR, (0x1u << 0x17u)>; + using RXFF = RegisterMask<ISR, (0x1u << 0x18u)>; + using RXFT = RegisterMask<ISR, (0x1u << 0x1au)>; + using TXFT = RegisterMask<ISR, (0x1u << 0x1bu)>; + }; + struct ISR_ALTERNATE : public MemRegister<uint32_t, 0x40008c1c> { + using PE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x4u)>; + using RXNE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR_ALTERNATE, (0x1u << 0x6u)>; + using TXE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x7u)>; + using CTSIF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR_ALTERNATE, (0x1u << 0xau)>; + using BUSY = RegisterMask<ISR_ALTERNATE, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR_ALTERNATE, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x16u)>; + }; + struct ICR : public MemRegister<uint32_t, 0x40008c20> { + using PECF = RegisterMask<ICR, (0x1u << 0x0u)>; + using FECF = RegisterMask<ICR, (0x1u << 0x1u)>; + using NECF = RegisterMask<ICR, (0x1u << 0x2u)>; + using ORECF = RegisterMask<ICR, (0x1u << 0x3u)>; + using IDLECF = RegisterMask<ICR, (0x1u << 0x4u)>; + using TCCF = RegisterMask<ICR, (0x1u << 0x6u)>; + using CTSCF = RegisterMask<ICR, (0x1u << 0x9u)>; + using CMCF = RegisterMask<ICR, (0x1u << 0x11u)>; + using WUCF = RegisterMask<ICR, (0x1u << 0x14u)>; + }; + struct RDR : public MemRegister<uint32_t, 0x40008c24> { + using val = RegisterMask<RDR, (0x1ffu << 0x0u)>; + }; + struct TDR : public MemRegister<uint32_t, 0x40008c28> { + using val = RegisterMask<TDR, (0x1ffu << 0x0u)>; + }; + struct PRESC : public MemRegister<uint32_t, 0x40008c2c> { + using PRESCALER = RegisterMask<PRESC, (0xfu << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR1_ALTERNATE, CR2, CR3, BRR, RQR, ISR, ISR_ALTERNATE, ICR, RDR, TDR, PRESC>; + } + namespace OPAMP { + struct CSR : public MemRegister<uint32_t, 0x40007800> { + using OPAEN = RegisterMask<CSR, (0x1u << 0x0u)>; + using OPALPM = RegisterMask<CSR, (0x1u << 0x1u)>; + using OPAMODE = RegisterMask<CSR, (0x3u << 0x2u)>; + using PGA_GAIN = RegisterMask<CSR, (0x3u << 0x4u)>; + using VM_SEL = RegisterMask<CSR, (0x3u << 0x8u)>; + using VP_SEL = RegisterMask<CSR, (0x1u << 0xau)>; + using CALON = RegisterMask<CSR, (0x1u << 0xcu)>; + using CALSEL = RegisterMask<CSR, (0x1u << 0xdu)>; + using USERTRIM = RegisterMask<CSR, (0x1u << 0xeu)>; + using CALOUT = RegisterMask<CSR, (0x1u << 0xfu)>; + using OPA_RANGE = RegisterMask<CSR, (0x1u << 0x1fu)>; + }; + struct OTR : public MemRegister<uint32_t, 0x40007804> { + using TRIMOFFSETN = RegisterMask<OTR, (0x1fu << 0x0u)>; + using TRIMOFFSETP = RegisterMask<OTR, (0x1fu << 0x8u)>; + }; + struct LPOTR : public MemRegister<uint32_t, 0x40007808> { + using TRIMLPOFFSETN = RegisterMask<LPOTR, (0x1fu << 0x0u)>; + using TRIMLPOFFSETP = RegisterMask<LPOTR, (0x1fu << 0x8u)>; + }; + using ALL = RegisterGroup<CSR, OTR, LPOTR>; + } + namespace PWR { + struct CR1 : public MemRegister<uint32_t, 0x40007000> { + using LPMS = RegisterMask<CR1, (0x7u << 0x0u)>; + using FPD_STOP = RegisterMask<CR1, (0x1u << 0x3u)>; + using FPD_LPRUN = RegisterMask<CR1, (0x1u << 0x4u)>; + using FPD_LPSLP = RegisterMask<CR1, (0x1u << 0x5u)>; + using DBP = RegisterMask<CR1, (0x1u << 0x8u)>; + using VOS = RegisterMask<CR1, (0x3u << 0x9u)>; + using LPR = RegisterMask<CR1, (0x1u << 0xeu)>; + }; + struct CR2 : public MemRegister<uint32_t, 0x40007004> { + using PVDE = RegisterMask<CR2, (0x1u << 0x0u)>; + using PLS = RegisterMask<CR2, (0x7u << 0x1u)>; + using PVME1 = RegisterMask<CR2, (0x1u << 0x4u)>; + using PVME3 = RegisterMask<CR2, (0x1u << 0x5u)>; + using PVME4 = RegisterMask<CR2, (0x1u << 0x6u)>; + using USV = RegisterMask<CR2, (0x1u << 0xau)>; + }; + struct CR3 : public MemRegister<uint32_t, 0x40007008> { + using EWUP1 = RegisterMask<CR3, (0x1u << 0x0u)>; + using EWUP2 = RegisterMask<CR3, (0x1u << 0x1u)>; + using EWUP3 = RegisterMask<CR3, (0x1u << 0x2u)>; + using EWUP4 = RegisterMask<CR3, (0x1u << 0x3u)>; + using EWUP5 = RegisterMask<CR3, (0x1u << 0x4u)>; + using EWUP7 = RegisterMask<CR3, (0x1u << 0x6u)>; + using RRS = RegisterMask<CR3, (0x1u << 0x8u)>; + using ENULP = RegisterMask<CR3, (0x1u << 0x9u)>; + using APC = RegisterMask<CR3, (0x1u << 0xau)>; + using EIWUL = RegisterMask<CR3, (0x1u << 0xfu)>; + }; + struct CR4 : public MemRegister<uint32_t, 0x4000700c> { + using WP1 = RegisterMask<CR4, (0x1u << 0x0u)>; + using WP2 = RegisterMask<CR4, (0x1u << 0x1u)>; + using WP3 = RegisterMask<CR4, (0x1u << 0x2u)>; + using WP4 = RegisterMask<CR4, (0x1u << 0x3u)>; + using WP5 = RegisterMask<CR4, (0x1u << 0x4u)>; + using WP7 = RegisterMask<CR4, (0x1u << 0x6u)>; + using VBE = RegisterMask<CR4, (0x1u << 0x8u)>; + using VBRS = RegisterMask<CR4, (0x1u << 0x9u)>; + }; + struct SR1 : public MemRegister<uint32_t, 0x40007010> { + using WUF1 = RegisterMask<SR1, (0x1u << 0x0u)>; + using WUF2 = RegisterMask<SR1, (0x1u << 0x1u)>; + using WUF3 = RegisterMask<SR1, (0x1u << 0x2u)>; + using WUF4 = RegisterMask<SR1, (0x1u << 0x3u)>; + using WUF5 = RegisterMask<SR1, (0x1u << 0x4u)>; + using WUF7 = RegisterMask<SR1, (0x1u << 0x6u)>; + using SBF = RegisterMask<SR1, (0x1u << 0x8u)>; + using STOPF = RegisterMask<SR1, (0x7u << 0x9u)>; + using WUFI = RegisterMask<SR1, (0x1u << 0xfu)>; + }; + struct SR2 : public MemRegister<uint32_t, 0x40007014> { + using FLASH_RDY = RegisterMask<SR2, (0x1u << 0x7u)>; + using REGLPS = RegisterMask<SR2, (0x1u << 0x8u)>; + using REGLPF = RegisterMask<SR2, (0x1u << 0x9u)>; + using VOSF = RegisterMask<SR2, (0x1u << 0xau)>; + using PVDO = RegisterMask<SR2, (0x1u << 0xbu)>; + using PVMO1 = RegisterMask<SR2, (0x1u << 0xcu)>; + using PVMO3 = RegisterMask<SR2, (0x1u << 0xeu)>; + using PVMO4 = RegisterMask<SR2, (0x1u << 0xfu)>; + }; + struct SCR : public MemRegister<uint32_t, 0x40007018> { + using CWUF1 = RegisterMask<SCR, (0x1u << 0x0u)>; + using CWUF2 = RegisterMask<SCR, (0x1u << 0x1u)>; + using CWUF3 = RegisterMask<SCR, (0x1u << 0x2u)>; + using CWUF4 = RegisterMask<SCR, (0x1u << 0x3u)>; + using CWUF5 = RegisterMask<SCR, (0x1u << 0x4u)>; + using CWUF7 = RegisterMask<SCR, (0x1u << 0x6u)>; + using CSBF = RegisterMask<SCR, (0x1u << 0x8u)>; + }; + struct PUCRA : public MemRegister<uint32_t, 0x40007020> { + using PU0 = RegisterMask<PUCRA, (0x1u << 0x0u)>; + using PU1 = RegisterMask<PUCRA, (0x1u << 0x1u)>; + using PU2 = RegisterMask<PUCRA, (0x1u << 0x2u)>; + using PU3 = RegisterMask<PUCRA, (0x1u << 0x3u)>; + using PU4 = RegisterMask<PUCRA, (0x1u << 0x4u)>; + using PU5 = RegisterMask<PUCRA, (0x1u << 0x5u)>; + using PU6 = RegisterMask<PUCRA, (0x1u << 0x6u)>; + using PU7 = RegisterMask<PUCRA, (0x1u << 0x7u)>; + using PU8 = RegisterMask<PUCRA, (0x1u << 0x8u)>; + using PU9 = RegisterMask<PUCRA, (0x1u << 0x9u)>; + using PU10 = RegisterMask<PUCRA, (0x1u << 0xau)>; + using PU11 = RegisterMask<PUCRA, (0x1u << 0xbu)>; + using PU12 = RegisterMask<PUCRA, (0x1u << 0xcu)>; + using PU13 = RegisterMask<PUCRA, (0x1u << 0xdu)>; + using PU14 = RegisterMask<PUCRA, (0x1u << 0xeu)>; + using PU15 = RegisterMask<PUCRA, (0x1u << 0xfu)>; + }; + struct PDCRA : public MemRegister<uint32_t, 0x40007024> { + using PD0 = RegisterMask<PDCRA, (0x1u << 0x0u)>; + using PD1 = RegisterMask<PDCRA, (0x1u << 0x1u)>; + using PD2 = RegisterMask<PDCRA, (0x1u << 0x2u)>; + using PD3 = RegisterMask<PDCRA, (0x1u << 0x3u)>; + using PD4 = RegisterMask<PDCRA, (0x1u << 0x4u)>; + using PD5 = RegisterMask<PDCRA, (0x1u << 0x5u)>; + using PD6 = RegisterMask<PDCRA, (0x1u << 0x6u)>; + using PD7 = RegisterMask<PDCRA, (0x1u << 0x7u)>; + using PD8 = RegisterMask<PDCRA, (0x1u << 0x8u)>; + using PD9 = RegisterMask<PDCRA, (0x1u << 0x9u)>; + using PD10 = RegisterMask<PDCRA, (0x1u << 0xau)>; + using PD11 = RegisterMask<PDCRA, (0x1u << 0xbu)>; + using PD12 = RegisterMask<PDCRA, (0x1u << 0xcu)>; + using PD13 = RegisterMask<PDCRA, (0x1u << 0xdu)>; + using PD14 = RegisterMask<PDCRA, (0x1u << 0xeu)>; + using PD15 = RegisterMask<PDCRA, (0x1u << 0xfu)>; + }; + struct PUCRB : public MemRegister<uint32_t, 0x40007028> { + using PU0 = RegisterMask<PUCRB, (0x1u << 0x0u)>; + using PU1 = RegisterMask<PUCRB, (0x1u << 0x1u)>; + using PU2 = RegisterMask<PUCRB, (0x1u << 0x2u)>; + using PU3 = RegisterMask<PUCRB, (0x1u << 0x3u)>; + using PU4 = RegisterMask<PUCRB, (0x1u << 0x4u)>; + using PU5 = RegisterMask<PUCRB, (0x1u << 0x5u)>; + using PU6 = RegisterMask<PUCRB, (0x1u << 0x6u)>; + using PU7 = RegisterMask<PUCRB, (0x1u << 0x7u)>; + using PU8 = RegisterMask<PUCRB, (0x1u << 0x8u)>; + using PU9 = RegisterMask<PUCRB, (0x1u << 0x9u)>; + using PU10 = RegisterMask<PUCRB, (0x1u << 0xau)>; + using PU11 = RegisterMask<PUCRB, (0x1u << 0xbu)>; + using PU12 = RegisterMask<PUCRB, (0x1u << 0xcu)>; + using PU13 = RegisterMask<PUCRB, (0x1u << 0xdu)>; + using PU14 = RegisterMask<PUCRB, (0x1u << 0xeu)>; + using PU15 = RegisterMask<PUCRB, (0x1u << 0xfu)>; + }; + struct PDCRB : public MemRegister<uint32_t, 0x4000702c> { + using PD0 = RegisterMask<PDCRB, (0x1u << 0x0u)>; + using PD1 = RegisterMask<PDCRB, (0x1u << 0x1u)>; + using PD2 = RegisterMask<PDCRB, (0x1u << 0x2u)>; + using PD3 = RegisterMask<PDCRB, (0x1u << 0x3u)>; + using PD4 = RegisterMask<PDCRB, (0x1u << 0x4u)>; + using PD5 = RegisterMask<PDCRB, (0x1u << 0x5u)>; + using PD6 = RegisterMask<PDCRB, (0x1u << 0x6u)>; + using PD7 = RegisterMask<PDCRB, (0x1u << 0x7u)>; + using PD8 = RegisterMask<PDCRB, (0x1u << 0x8u)>; + using PD9 = RegisterMask<PDCRB, (0x1u << 0x9u)>; + using PD10 = RegisterMask<PDCRB, (0x1u << 0xau)>; + using PD11 = RegisterMask<PDCRB, (0x1u << 0xbu)>; + using PD12 = RegisterMask<PDCRB, (0x1u << 0xcu)>; + using PD13 = RegisterMask<PDCRB, (0x1u << 0xdu)>; + using PD14 = RegisterMask<PDCRB, (0x1u << 0xeu)>; + using PD15 = RegisterMask<PDCRB, (0x1u << 0xfu)>; + }; + struct PUCRC : public MemRegister<uint32_t, 0x40007030> { + using PU0 = RegisterMask<PUCRC, (0x1u << 0x0u)>; + using PU1 = RegisterMask<PUCRC, (0x1u << 0x1u)>; + using PU2 = RegisterMask<PUCRC, (0x1u << 0x2u)>; + using PU3 = RegisterMask<PUCRC, (0x1u << 0x3u)>; + using PU4 = RegisterMask<PUCRC, (0x1u << 0x4u)>; + using PU5 = RegisterMask<PUCRC, (0x1u << 0x5u)>; + using PU6 = RegisterMask<PUCRC, (0x1u << 0x6u)>; + using PU7 = RegisterMask<PUCRC, (0x1u << 0x7u)>; + using PU8 = RegisterMask<PUCRC, (0x1u << 0x8u)>; + using PU9 = RegisterMask<PUCRC, (0x1u << 0x9u)>; + using PU10 = RegisterMask<PUCRC, (0x1u << 0xau)>; + using PU11 = RegisterMask<PUCRC, (0x1u << 0xbu)>; + using PU12 = RegisterMask<PUCRC, (0x1u << 0xcu)>; + using PU13 = RegisterMask<PUCRC, (0x1u << 0xdu)>; + using PU14 = RegisterMask<PUCRC, (0x1u << 0xeu)>; + using PU15 = RegisterMask<PUCRC, (0x1u << 0xfu)>; + }; + struct PDCRC : public MemRegister<uint32_t, 0x40007034> { + using PD0 = RegisterMask<PDCRC, (0x1u << 0x0u)>; + using PD1 = RegisterMask<PDCRC, (0x1u << 0x1u)>; + using PD2 = RegisterMask<PDCRC, (0x1u << 0x2u)>; + using PD3 = RegisterMask<PDCRC, (0x1u << 0x3u)>; + using PD4 = RegisterMask<PDCRC, (0x1u << 0x4u)>; + using PD5 = RegisterMask<PDCRC, (0x1u << 0x5u)>; + using PD6 = RegisterMask<PDCRC, (0x1u << 0x6u)>; + using PD7 = RegisterMask<PDCRC, (0x1u << 0x7u)>; + using PD8 = RegisterMask<PDCRC, (0x1u << 0x8u)>; + using PD9 = RegisterMask<PDCRC, (0x1u << 0x9u)>; + using PD10 = RegisterMask<PDCRC, (0x1u << 0xau)>; + using PD11 = RegisterMask<PDCRC, (0x1u << 0xbu)>; + using PD12 = RegisterMask<PDCRC, (0x1u << 0xcu)>; + using PD13 = RegisterMask<PDCRC, (0x1u << 0xdu)>; + using PD14 = RegisterMask<PDCRC, (0x1u << 0xeu)>; + using PD15 = RegisterMask<PDCRC, (0x1u << 0xfu)>; + }; + struct PUCRD : public MemRegister<uint32_t, 0x40007038> { + using PU0 = RegisterMask<PUCRD, (0x1u << 0x0u)>; + using PU1 = RegisterMask<PUCRD, (0x1u << 0x1u)>; + using PU2 = RegisterMask<PUCRD, (0x1u << 0x2u)>; + using PU3 = RegisterMask<PUCRD, (0x1u << 0x3u)>; + using PU4 = RegisterMask<PUCRD, (0x1u << 0x4u)>; + using PU5 = RegisterMask<PUCRD, (0x1u << 0x5u)>; + using PU6 = RegisterMask<PUCRD, (0x1u << 0x6u)>; + using PU8 = RegisterMask<PUCRD, (0x1u << 0x8u)>; + using PU9 = RegisterMask<PUCRD, (0x1u << 0x9u)>; + using PU10 = RegisterMask<PUCRD, (0x1u << 0xau)>; + using PU11 = RegisterMask<PUCRD, (0x1u << 0xbu)>; + using PU12 = RegisterMask<PUCRD, (0x1u << 0xcu)>; + using PU13 = RegisterMask<PUCRD, (0x1u << 0xdu)>; + }; + struct PDCRD : public MemRegister<uint32_t, 0x4000703c> { + using PD0 = RegisterMask<PDCRD, (0x1u << 0x0u)>; + using PD1 = RegisterMask<PDCRD, (0x1u << 0x1u)>; + using PD2 = RegisterMask<PDCRD, (0x1u << 0x2u)>; + using PD3 = RegisterMask<PDCRD, (0x1u << 0x3u)>; + using PD4 = RegisterMask<PDCRD, (0x1u << 0x4u)>; + using PD5 = RegisterMask<PDCRD, (0x1u << 0x5u)>; + using PD6 = RegisterMask<PDCRD, (0x1u << 0x6u)>; + using PD8 = RegisterMask<PDCRD, (0x1u << 0x8u)>; + using PD9 = RegisterMask<PDCRD, (0x1u << 0x9u)>; + using PD10 = RegisterMask<PDCRD, (0x1u << 0xau)>; + using PD11 = RegisterMask<PDCRD, (0x1u << 0xbu)>; + using PD12 = RegisterMask<PDCRD, (0x1u << 0xcu)>; + using PD13 = RegisterMask<PDCRD, (0x1u << 0xdu)>; + }; + struct PUCRE : public MemRegister<uint32_t, 0x40007040> { + using PU3 = RegisterMask<PUCRE, (0x1u << 0x3u)>; + using PU7 = RegisterMask<PUCRE, (0x1u << 0x7u)>; + using PU8 = RegisterMask<PUCRE, (0x1u << 0x8u)>; + using PU9 = RegisterMask<PUCRE, (0x1u << 0x9u)>; + }; + struct PDCRE : public MemRegister<uint32_t, 0x40007044> { + using PD3 = RegisterMask<PDCRE, (0x1u << 0x3u)>; + using PD7 = RegisterMask<PDCRE, (0x1u << 0x7u)>; + using PD8 = RegisterMask<PDCRE, (0x1u << 0x8u)>; + using PD9 = RegisterMask<PDCRE, (0x1u << 0x9u)>; + }; + struct PUCRF : public MemRegister<uint32_t, 0x40007048> { + using PU0 = RegisterMask<PUCRF, (0x1u << 0x0u)>; + using PU1 = RegisterMask<PUCRF, (0x1u << 0x1u)>; + using PU2 = RegisterMask<PUCRF, (0x1u << 0x2u)>; + using PU3 = RegisterMask<PUCRF, (0x1u << 0x3u)>; + }; + struct PDCRF : public MemRegister<uint32_t, 0x4000704c> { + using PD0 = RegisterMask<PDCRF, (0x1u << 0x0u)>; + using PD1 = RegisterMask<PDCRF, (0x1u << 0x1u)>; + using PD2 = RegisterMask<PDCRF, (0x1u << 0x2u)>; + using PD3 = RegisterMask<PDCRF, (0x1u << 0x3u)>; + }; + using ALL = RegisterGroup<CR1, CR2, CR3, CR4, SR1, SR2, SCR, PUCRA, PDCRA, PUCRB, PDCRB, PUCRC, PDCRC, PUCRD, PDCRD, PUCRE, PDCRE, PUCRF, PDCRF>; + } + namespace RCC { + struct CR : public MemRegister<uint32_t, 0x40021000> { + using MSION = RegisterMask<CR, (0x1u << 0x0u)>; + using MSIRDY = RegisterMask<CR, (0x1u << 0x1u)>; + using MSIPLLEN = RegisterMask<CR, (0x1u << 0x2u)>; + using MSIRGSEL = RegisterMask<CR, (0x1u << 0x3u)>; + using MSIRANGE = RegisterMask<CR, (0xfu << 0x4u)>; + using HSION = RegisterMask<CR, (0x1u << 0x8u)>; + using HSIKERON = RegisterMask<CR, (0x1u << 0x9u)>; + using HSIRDY = RegisterMask<CR, (0x1u << 0xau)>; + using HSIASFS = RegisterMask<CR, (0x1u << 0xbu)>; + using HSEON = RegisterMask<CR, (0x1u << 0x10u)>; + using HSERDY = RegisterMask<CR, (0x1u << 0x11u)>; + using HSEBYP = RegisterMask<CR, (0x1u << 0x12u)>; + using CSSON = RegisterMask<CR, (0x1u << 0x13u)>; + using PLLON = RegisterMask<CR, (0x1u << 0x18u)>; + using PLLRDY = RegisterMask<CR, (0x1u << 0x19u)>; + }; + struct ICSCR : public MemRegister<uint32_t, 0x40021004> { + using MSICAL = RegisterMask<ICSCR, (0xffu << 0x0u)>; + using MSITRIM = RegisterMask<ICSCR, (0xffu << 0x8u)>; + using HSICAL = RegisterMask<ICSCR, (0xffu << 0x10u)>; + using HSITRIM = RegisterMask<ICSCR, (0x7fu << 0x18u)>; + }; + struct CFGR : public MemRegister<uint32_t, 0x40021008> { + using SW = RegisterMask<CFGR, (0x7u << 0x0u)>; + using SWS = RegisterMask<CFGR, (0x7u << 0x3u)>; + using HPRE = RegisterMask<CFGR, (0xfu << 0x8u)>; + using PPRE = RegisterMask<CFGR, (0x7u << 0xcu)>; + using STOPWUCK = RegisterMask<CFGR, (0x1u << 0xfu)>; + using MCO2SEL = RegisterMask<CFGR, (0xfu << 0x10u)>; + using MCO2PRE = RegisterMask<CFGR, (0xfu << 0x14u)>; + using MCOSEL = RegisterMask<CFGR, (0xfu << 0x18u)>; + using MCOPRE = RegisterMask<CFGR, (0xfu << 0x1cu)>; + }; + struct PLLCFGR : public MemRegister<uint32_t, 0x4002100c> { + using PLLSRC = RegisterMask<PLLCFGR, (0x3u << 0x0u)>; + using PLLM = RegisterMask<PLLCFGR, (0x7u << 0x4u)>; + using PLLN = RegisterMask<PLLCFGR, (0x7fu << 0x8u)>; + using PLLPEN = RegisterMask<PLLCFGR, (0x1u << 0x10u)>; + using PLLP = RegisterMask<PLLCFGR, (0x1fu << 0x11u)>; + using PLLQEN = RegisterMask<PLLCFGR, (0x1u << 0x18u)>; + using PLLQ = RegisterMask<PLLCFGR, (0x7u << 0x19u)>; + using PLLREN = RegisterMask<PLLCFGR, (0x1u << 0x1cu)>; + using PLLR = RegisterMask<PLLCFGR, (0x7u << 0x1du)>; + }; + struct CIER : public MemRegister<uint32_t, 0x40021018> { + using LSIRDYIE = RegisterMask<CIER, (0x1u << 0x0u)>; + using LSERDYIE = RegisterMask<CIER, (0x1u << 0x1u)>; + using MSIRDYIE = RegisterMask<CIER, (0x1u << 0x2u)>; + using HSIRDYIE = RegisterMask<CIER, (0x1u << 0x3u)>; + using HSERDYIE = RegisterMask<CIER, (0x1u << 0x4u)>; + using PLLRDYIE = RegisterMask<CIER, (0x1u << 0x5u)>; + using LSECSSIE = RegisterMask<CIER, (0x1u << 0x9u)>; + using HSI48RDYIE = RegisterMask<CIER, (0x1u << 0xau)>; + }; + struct CIFR : public MemRegister<uint32_t, 0x4002101c> { + using LSIRDYF = RegisterMask<CIFR, (0x1u << 0x0u)>; + using LSERDYF = RegisterMask<CIFR, (0x1u << 0x1u)>; + using MSIRDYF = RegisterMask<CIFR, (0x1u << 0x2u)>; + using HSIRDYF = RegisterMask<CIFR, (0x1u << 0x3u)>; + using HSERDYF = RegisterMask<CIFR, (0x1u << 0x4u)>; + using PLLRDYF = RegisterMask<CIFR, (0x1u << 0x5u)>; + using CSSF = RegisterMask<CIFR, (0x1u << 0x8u)>; + using LSECSSF = RegisterMask<CIFR, (0x1u << 0x9u)>; + using HSI48RDYF = RegisterMask<CIFR, (0x1u << 0xau)>; + }; + struct CICR : public MemRegister<uint32_t, 0x40021020> { + using LSIRDYC = RegisterMask<CICR, (0x1u << 0x0u)>; + using LSERDYC = RegisterMask<CICR, (0x1u << 0x1u)>; + using MSIRDYC = RegisterMask<CICR, (0x1u << 0x2u)>; + using HSIRDYC = RegisterMask<CICR, (0x1u << 0x3u)>; + using HSERDYC = RegisterMask<CICR, (0x1u << 0x4u)>; + using PLLRDYC = RegisterMask<CICR, (0x1u << 0x5u)>; + using CSSC = RegisterMask<CICR, (0x1u << 0x8u)>; + using LSECSSC = RegisterMask<CICR, (0x1u << 0x9u)>; + using HSI48RDYC = RegisterMask<CICR, (0x1u << 0xau)>; + }; + struct AHBRSTR : public MemRegister<uint32_t, 0x40021028> { + using DMA1RST = RegisterMask<AHBRSTR, (0x1u << 0x0u)>; + using DMA2RST = RegisterMask<AHBRSTR, (0x1u << 0x1u)>; + using FLASHRST = RegisterMask<AHBRSTR, (0x1u << 0x8u)>; + using CRCRST = RegisterMask<AHBRSTR, (0x1u << 0xcu)>; + using AESRST = RegisterMask<AHBRSTR, (0x1u << 0x10u)>; + using RNGRST = RegisterMask<AHBRSTR, (0x1u << 0x12u)>; + using TSCRST = RegisterMask<AHBRSTR, (0x1u << 0x18u)>; + }; + struct IOPRSTR : public MemRegister<uint32_t, 0x4002102c> { + using GPIOARST = RegisterMask<IOPRSTR, (0x1u << 0x0u)>; + using GPIOBRST = RegisterMask<IOPRSTR, (0x1u << 0x1u)>; + using GPIOCRST = RegisterMask<IOPRSTR, (0x1u << 0x2u)>; + using GPIODRST = RegisterMask<IOPRSTR, (0x1u << 0x3u)>; + using GPIOERST = RegisterMask<IOPRSTR, (0x1u << 0x4u)>; + using GPIOFRST = RegisterMask<IOPRSTR, (0x1u << 0x5u)>; + }; + struct APBRSTR1 : public MemRegister<uint32_t, 0x40021038> { + using TIM2RST = RegisterMask<APBRSTR1, (0x1u << 0x0u)>; + using TIM3RST = RegisterMask<APBRSTR1, (0x1u << 0x1u)>; + using TIM6RST = RegisterMask<APBRSTR1, (0x1u << 0x4u)>; + using TIM7RST = RegisterMask<APBRSTR1, (0x1u << 0x5u)>; + using LPUART2RST = RegisterMask<APBRSTR1, (0x1u << 0x7u)>; + using LCDRST = RegisterMask<APBRSTR1, (0x1u << 0x9u)>; + using LPUART3RST = RegisterMask<APBRSTR1, (0x1u << 0xcu)>; + using USBRST = RegisterMask<APBRSTR1, (0x1u << 0xdu)>; + using SPI2RST = RegisterMask<APBRSTR1, (0x1u << 0xeu)>; + using SPI3RST = RegisterMask<APBRSTR1, (0x1u << 0xfu)>; + using CRSRST = RegisterMask<APBRSTR1, (0x1u << 0x10u)>; + using USART2RST = RegisterMask<APBRSTR1, (0x1u << 0x11u)>; + using USART3RST = RegisterMask<APBRSTR1, (0x1u << 0x12u)>; + using USART4RST = RegisterMask<APBRSTR1, (0x1u << 0x13u)>; + using LPUART1RST = RegisterMask<APBRSTR1, (0x1u << 0x14u)>; + using I2C1RST = RegisterMask<APBRSTR1, (0x1u << 0x15u)>; + using I2C2RST = RegisterMask<APBRSTR1, (0x1u << 0x16u)>; + using I2C3RST = RegisterMask<APBRSTR1, (0x1u << 0x17u)>; + using OPAMPRST = RegisterMask<APBRSTR1, (0x1u << 0x18u)>; + using I2C4RST = RegisterMask<APBRSTR1, (0x1u << 0x19u)>; + using LPTIM3RST = RegisterMask<APBRSTR1, (0x1u << 0x1au)>; + using PWRRST = RegisterMask<APBRSTR1, (0x1u << 0x1cu)>; + using DAC1RST = RegisterMask<APBRSTR1, (0x1u << 0x1du)>; + using LPTIM2RST = RegisterMask<APBRSTR1, (0x1u << 0x1eu)>; + using LPTIM1RST = RegisterMask<APBRSTR1, (0x1u << 0x1fu)>; + }; + struct APBRSTR2 : public MemRegister<uint32_t, 0x40021040> { + using SYSCFGRST = RegisterMask<APBRSTR2, (0x1u << 0x0u)>; + using TIM1RST = RegisterMask<APBRSTR2, (0x1u << 0xbu)>; + using SPI1RST = RegisterMask<APBRSTR2, (0x1u << 0xcu)>; + using USART1RST = RegisterMask<APBRSTR2, (0x1u << 0xeu)>; + using TIM15RST = RegisterMask<APBRSTR2, (0x1u << 0x10u)>; + using TIM16RST = RegisterMask<APBRSTR2, (0x1u << 0x11u)>; + using ADCRST = RegisterMask<APBRSTR2, (0x1u << 0x14u)>; + }; + struct AHBENR : public MemRegister<uint32_t, 0x40021048> { + using DMA1EN = RegisterMask<AHBENR, (0x1u << 0x0u)>; + using DMA2EN = RegisterMask<AHBENR, (0x1u << 0x1u)>; + using FLASHEN = RegisterMask<AHBENR, (0x1u << 0x8u)>; + using CRCEN = RegisterMask<AHBENR, (0x1u << 0xcu)>; + using AESEN = RegisterMask<AHBENR, (0x1u << 0x10u)>; + using RNGEN = RegisterMask<AHBENR, (0x1u << 0x12u)>; + using TSCEN = RegisterMask<AHBENR, (0x1u << 0x18u)>; + }; + struct IOPENR : public MemRegister<uint32_t, 0x4002104c> { + using GPIOAEN = RegisterMask<IOPENR, (0x1u << 0x0u)>; + using GPIOBEN = RegisterMask<IOPENR, (0x1u << 0x1u)>; + using GPIOCEN = RegisterMask<IOPENR, (0x1u << 0x2u)>; + using GPIODEN = RegisterMask<IOPENR, (0x1u << 0x3u)>; + using GPIOEEN = RegisterMask<IOPENR, (0x1u << 0x4u)>; + using GPIOFEN = RegisterMask<IOPENR, (0x1u << 0x5u)>; + }; + struct DBGCFGR : public MemRegister<uint32_t, 0x40021050> { + using DBGEN = RegisterMask<DBGCFGR, (0x1u << 0x0u)>; + using DBGRST = RegisterMask<DBGCFGR, (0x1u << 0x1u)>; + }; + struct APBENR1 : public MemRegister<uint32_t, 0x40021058> { + using TIM2EN = RegisterMask<APBENR1, (0x1u << 0x0u)>; + using TIM3EN = RegisterMask<APBENR1, (0x1u << 0x1u)>; + using TIM6EN = RegisterMask<APBENR1, (0x1u << 0x4u)>; + using TIM7EN = RegisterMask<APBENR1, (0x1u << 0x5u)>; + using LPUART2EN = RegisterMask<APBENR1, (0x1u << 0x7u)>; + using LCDEN = RegisterMask<APBENR1, (0x1u << 0x9u)>; + using RTCAPBEN = RegisterMask<APBENR1, (0x1u << 0xau)>; + using WWDGEN = RegisterMask<APBENR1, (0x1u << 0xbu)>; + using LPUART3EN = RegisterMask<APBENR1, (0x1u << 0xcu)>; + using USBEN = RegisterMask<APBENR1, (0x1u << 0xdu)>; + using SPI2EN = RegisterMask<APBENR1, (0x1u << 0xeu)>; + using SPI3EN = RegisterMask<APBENR1, (0x1u << 0xfu)>; + using CRSEN = RegisterMask<APBENR1, (0x1u << 0x10u)>; + using USART2EN = RegisterMask<APBENR1, (0x1u << 0x11u)>; + using USART3EN = RegisterMask<APBENR1, (0x1u << 0x12u)>; + using USART4EN = RegisterMask<APBENR1, (0x1u << 0x13u)>; + using LPUART1EN = RegisterMask<APBENR1, (0x1u << 0x14u)>; + using I2C1EN = RegisterMask<APBENR1, (0x1u << 0x15u)>; + using I2C2EN = RegisterMask<APBENR1, (0x1u << 0x16u)>; + using I2C3EN = RegisterMask<APBENR1, (0x1u << 0x17u)>; + using OPAMPEN = RegisterMask<APBENR1, (0x1u << 0x18u)>; + using I2C4EN = RegisterMask<APBENR1, (0x1u << 0x19u)>; + using LPTIM3EN = RegisterMask<APBENR1, (0x1u << 0x1au)>; + using PWREN = RegisterMask<APBENR1, (0x1u << 0x1cu)>; + using DAC1EN = RegisterMask<APBENR1, (0x1u << 0x1du)>; + using LPTIM2EN = RegisterMask<APBENR1, (0x1u << 0x1eu)>; + using LPTIM1EN = RegisterMask<APBENR1, (0x1u << 0x1fu)>; + }; + struct APBENR2 : public MemRegister<uint32_t, 0x40021060> { + using SYSCFGEN = RegisterMask<APBENR2, (0x1u << 0x0u)>; + using TIM1EN = RegisterMask<APBENR2, (0x1u << 0xbu)>; + using SPI1EN = RegisterMask<APBENR2, (0x1u << 0xcu)>; + using USART1EN = RegisterMask<APBENR2, (0x1u << 0xeu)>; + using TIM15EN = RegisterMask<APBENR2, (0x1u << 0x10u)>; + using TIM16EN = RegisterMask<APBENR2, (0x1u << 0x11u)>; + using ADCEN = RegisterMask<APBENR2, (0x1u << 0x14u)>; + }; + struct AHBSMENR : public MemRegister<uint32_t, 0x40021068> { + using DMA1SMEN = RegisterMask<AHBSMENR, (0x1u << 0x0u)>; + using DMA2SMEN = RegisterMask<AHBSMENR, (0x1u << 0x1u)>; + using FLASHSMEN = RegisterMask<AHBSMENR, (0x1u << 0x8u)>; + using SRAMSMEN = RegisterMask<AHBSMENR, (0x1u << 0x9u)>; + using CRCSMEN = RegisterMask<AHBSMENR, (0x1u << 0xcu)>; + using AESSMEN = RegisterMask<AHBSMENR, (0x1u << 0x10u)>; + using RNGSMEN = RegisterMask<AHBSMENR, (0x1u << 0x12u)>; + using TSCSMEN = RegisterMask<AHBSMENR, (0x1u << 0x18u)>; + }; + struct IOPSMENR : public MemRegister<uint32_t, 0x4002106c> { + using GPIOASMEN = RegisterMask<IOPSMENR, (0x1u << 0x0u)>; + using GPIOBSMEN = RegisterMask<IOPSMENR, (0x1u << 0x1u)>; + using GPIOCSMEN = RegisterMask<IOPSMENR, (0x1u << 0x2u)>; + using GPIODSMEN = RegisterMask<IOPSMENR, (0x1u << 0x3u)>; + using GPIOESMEN = RegisterMask<IOPSMENR, (0x1u << 0x4u)>; + using GPIOFSMEN = RegisterMask<IOPSMENR, (0x1u << 0x5u)>; + }; + struct APBSMENR1 : public MemRegister<uint32_t, 0x40021078> { + using TIM2SMEN = RegisterMask<APBSMENR1, (0x1u << 0x0u)>; + using TIM3SMEN = RegisterMask<APBSMENR1, (0x1u << 0x1u)>; + using TIM6SMEN = RegisterMask<APBSMENR1, (0x1u << 0x4u)>; + using TIM7SMEN = RegisterMask<APBSMENR1, (0x1u << 0x5u)>; + using LPUART2SMEN = RegisterMask<APBSMENR1, (0x1u << 0x7u)>; + using LCDSMEN = RegisterMask<APBSMENR1, (0x1u << 0x9u)>; + using RTCAPBSMEN = RegisterMask<APBSMENR1, (0x1u << 0xau)>; + using WWDGSMEN = RegisterMask<APBSMENR1, (0x1u << 0xbu)>; + using LPUART3SMEN = RegisterMask<APBSMENR1, (0x1u << 0xcu)>; + using USBSMEN = RegisterMask<APBSMENR1, (0x1u << 0xdu)>; + using SPI2SMEN = RegisterMask<APBSMENR1, (0x1u << 0xeu)>; + using SPI3SMEN = RegisterMask<APBSMENR1, (0x1u << 0xfu)>; + using CRSSMEN = RegisterMask<APBSMENR1, (0x1u << 0x10u)>; + using USART2SMEN = RegisterMask<APBSMENR1, (0x1u << 0x11u)>; + using USART3SMEN = RegisterMask<APBSMENR1, (0x1u << 0x12u)>; + using USART4SMEN = RegisterMask<APBSMENR1, (0x1u << 0x13u)>; + using LPUART1SMEN = RegisterMask<APBSMENR1, (0x1u << 0x14u)>; + using I2C1SMEN = RegisterMask<APBSMENR1, (0x1u << 0x15u)>; + using I2C2SMEN = RegisterMask<APBSMENR1, (0x1u << 0x16u)>; + using I2C3SMEN = RegisterMask<APBSMENR1, (0x1u << 0x17u)>; + using OPAMPSMEN = RegisterMask<APBSMENR1, (0x1u << 0x18u)>; + using I2C4SMEN = RegisterMask<APBSMENR1, (0x1u << 0x19u)>; + using LPTIM3SMEN = RegisterMask<APBSMENR1, (0x1u << 0x1au)>; + using PWRSMEN = RegisterMask<APBSMENR1, (0x1u << 0x1cu)>; + using DAC1SMEN = RegisterMask<APBSMENR1, (0x1u << 0x1du)>; + using LPTIM2SMEN = RegisterMask<APBSMENR1, (0x1u << 0x1eu)>; + using LPTIM1SMEN = RegisterMask<APBSMENR1, (0x1u << 0x1fu)>; + }; + struct APBSMENR2 : public MemRegister<uint32_t, 0x40021080> { + using SYSCFGSMEN = RegisterMask<APBSMENR2, (0x1u << 0x0u)>; + using TIM1SMEN = RegisterMask<APBSMENR2, (0x1u << 0xbu)>; + using SPI1SMEN = RegisterMask<APBSMENR2, (0x1u << 0xcu)>; + using USART1SMEN = RegisterMask<APBSMENR2, (0x1u << 0xeu)>; + using TIM15SMEN = RegisterMask<APBSMENR2, (0x1u << 0x10u)>; + using TIM16SMEN = RegisterMask<APBSMENR2, (0x1u << 0x11u)>; + using ADCSMEN = RegisterMask<APBSMENR2, (0x1u << 0x14u)>; + }; + struct CCIPR : public MemRegister<uint32_t, 0x40021088> { + using USART1SEL = RegisterMask<CCIPR, (0x3u << 0x0u)>; + using USART2SEL = RegisterMask<CCIPR, (0x3u << 0x2u)>; + using LPUART3SEL = RegisterMask<CCIPR, (0x3u << 0x6u)>; + using LPUART2SEL = RegisterMask<CCIPR, (0x3u << 0x8u)>; + using LPUART1SEL = RegisterMask<CCIPR, (0x3u << 0xau)>; + using I2C1SEL = RegisterMask<CCIPR, (0x3u << 0xcu)>; + using I2C3SEL = RegisterMask<CCIPR, (0x3u << 0x10u)>; + using LPTIM1SEL = RegisterMask<CCIPR, (0x3u << 0x12u)>; + using LPTIM2SEL = RegisterMask<CCIPR, (0x3u << 0x14u)>; + using LPTIM3SEL = RegisterMask<CCIPR, (0x3u << 0x16u)>; + using TIM1SEL = RegisterMask<CCIPR, (0x1u << 0x18u)>; + using TIM15SEL = RegisterMask<CCIPR, (0x1u << 0x19u)>; + using CLK48SEL = RegisterMask<CCIPR, (0x3u << 0x1au)>; + using ADCSEL = RegisterMask<CCIPR, (0x3u << 0x1cu)>; + }; + struct BDCR : public MemRegister<uint32_t, 0x40021090> { + using LSEON = RegisterMask<BDCR, (0x1u << 0x0u)>; + using LSERDY = RegisterMask<BDCR, (0x1u << 0x1u)>; + using LSEBYP = RegisterMask<BDCR, (0x1u << 0x2u)>; + using LSEDRV = RegisterMask<BDCR, (0x3u << 0x3u)>; + using LSECSSON = RegisterMask<BDCR, (0x1u << 0x5u)>; + using LSECSSD = RegisterMask<BDCR, (0x1u << 0x6u)>; + using LSESYSEN = RegisterMask<BDCR, (0x1u << 0x7u)>; + using RTCSEL = RegisterMask<BDCR, (0x3u << 0x8u)>; + using LSESYSRDY = RegisterMask<BDCR, (0x1u << 0xbu)>; + using RTCEN = RegisterMask<BDCR, (0x1u << 0xfu)>; + using BDRST = RegisterMask<BDCR, (0x1u << 0x10u)>; + using LSCOEN = RegisterMask<BDCR, (0x1u << 0x18u)>; + using LSCOSEL = RegisterMask<BDCR, (0x1u << 0x19u)>; + }; + struct CSR : public MemRegister<uint32_t, 0x40021094> { + using LSION = RegisterMask<CSR, (0x1u << 0x0u)>; + using LSIRDY = RegisterMask<CSR, (0x1u << 0x1u)>; + using LSIPREDIV = RegisterMask<CSR, (0x1u << 0x2u)>; + using MSISRANGE = RegisterMask<CSR, (0xfu << 0x8u)>; + using RMVF = RegisterMask<CSR, (0x1u << 0x17u)>; + using OBLRSTF = RegisterMask<CSR, (0x1u << 0x19u)>; + using PINRSTF = RegisterMask<CSR, (0x1u << 0x1au)>; + using PWRRSTF = RegisterMask<CSR, (0x1u << 0x1bu)>; + using SFTRSTF = RegisterMask<CSR, (0x1u << 0x1cu)>; + using IWDGRSTF = RegisterMask<CSR, (0x1u << 0x1du)>; + using WWDGRSTF = RegisterMask<CSR, (0x1u << 0x1eu)>; + using LPWRRSTF = RegisterMask<CSR, (0x1u << 0x1fu)>; + }; + struct CRRCR : public MemRegister<uint32_t, 0x40021098> { + using HSI48ON = RegisterMask<CRRCR, (0x1u << 0x0u)>; + using HSI48RDY = RegisterMask<CRRCR, (0x1u << 0x1u)>; + using HSI48CAL = RegisterMask<CRRCR, (0x1ffu << 0x7u)>; + }; + using ALL = RegisterGroup<CR, ICSCR, CFGR, PLLCFGR, CIER, CIFR, CICR, AHBRSTR, IOPRSTR, APBRSTR1, APBRSTR2, AHBENR, IOPENR, DBGCFGR, APBENR1, APBENR2, AHBSMENR, IOPSMENR, APBSMENR1, APBSMENR2, CCIPR, BDCR, CSR, CRRCR>; + } + namespace RNG { + struct CR : public MemRegister<uint32_t, 0x40025000> { + using RNGEN = RegisterMask<CR, (0x1u << 0x2u)>; + using IE = RegisterMask<CR, (0x1u << 0x3u)>; + using CED = RegisterMask<CR, (0x1u << 0x5u)>; + using ARDIS = RegisterMask<CR, (0x1u << 0x7u)>; + using RNG_CONFIG3 = RegisterMask<CR, (0xfu << 0x8u)>; + using NISTC = RegisterMask<CR, (0x1u << 0xcu)>; + using RNG_CONFIG2 = RegisterMask<CR, (0x7u << 0xdu)>; + using CLKDIV = RegisterMask<CR, (0xfu << 0x10u)>; + using RNG_CONFIG1 = RegisterMask<CR, (0x3fu << 0x14u)>; + using CONDRST = RegisterMask<CR, (0x1u << 0x1eu)>; + using CONFIGLOCK = RegisterMask<CR, (0x1u << 0x1fu)>; + }; + struct SR : public MemRegister<uint32_t, 0x40025004> { + using DRDY = RegisterMask<SR, (0x1u << 0x0u)>; + using CECS = RegisterMask<SR, (0x1u << 0x1u)>; + using SECS = RegisterMask<SR, (0x1u << 0x2u)>; + using CEIS = RegisterMask<SR, (0x1u << 0x5u)>; + using SEIS = RegisterMask<SR, (0x1u << 0x6u)>; + }; + struct DR : public MemRegister<uint32_t, 0x40025008> { + using RNDATA = RegisterMask<DR, (0x0u << 0x0u)>; + }; + struct HTCR : public MemRegister<uint32_t, 0x40025010> { + using HTCFG = RegisterMask<HTCR, (0x0u << 0x0u)>; + }; + using ALL = RegisterGroup<CR, SR, DR, HTCR>; + } + namespace RTC { + struct TR : public MemRegister<uint32_t, 0x40002800> { + using SU = RegisterMask<TR, (0xfu << 0x0u)>; + using ST = RegisterMask<TR, (0x7u << 0x4u)>; + using MNU = RegisterMask<TR, (0xfu << 0x8u)>; + using MNT = RegisterMask<TR, (0x7u << 0xcu)>; + using HU = RegisterMask<TR, (0xfu << 0x10u)>; + using HT = RegisterMask<TR, (0x3u << 0x14u)>; + using PM = RegisterMask<TR, (0x1u << 0x16u)>; + }; + struct DR : public MemRegister<uint32_t, 0x40002804> { + using DU = RegisterMask<DR, (0xfu << 0x0u)>; + using DT = RegisterMask<DR, (0x3u << 0x4u)>; + using MU = RegisterMask<DR, (0xfu << 0x8u)>; + using MT = RegisterMask<DR, (0x1u << 0xcu)>; + using WDU = RegisterMask<DR, (0x7u << 0xdu)>; + using YU = RegisterMask<DR, (0xfu << 0x10u)>; + using YT = RegisterMask<DR, (0xfu << 0x14u)>; + }; + struct SSR : public MemRegister<uint32_t, 0x40002808> { + using SS = RegisterMask<SSR, (0x0u << 0x0u)>; + }; + struct ICSR : public MemRegister<uint32_t, 0x4000280c> { + using WUTWF = RegisterMask<ICSR, (0x1u << 0x2u)>; + using SHPF = RegisterMask<ICSR, (0x1u << 0x3u)>; + using INITS = RegisterMask<ICSR, (0x1u << 0x4u)>; + using RSF = RegisterMask<ICSR, (0x1u << 0x5u)>; + using INITF = RegisterMask<ICSR, (0x1u << 0x6u)>; + using INIT = RegisterMask<ICSR, (0x1u << 0x7u)>; + using BIN = RegisterMask<ICSR, (0x3u << 0x8u)>; + using BCDU = RegisterMask<ICSR, (0x7u << 0xau)>; + using RECALPF = RegisterMask<ICSR, (0x1u << 0x10u)>; + }; + struct PRER : public MemRegister<uint32_t, 0x40002810> { + using PREDIV_S = RegisterMask<PRER, (0x7fffu << 0x0u)>; + using PREDIV_A = RegisterMask<PRER, (0x7fu << 0x10u)>; + }; + struct WUTR : public MemRegister<uint32_t, 0x40002814> { + using WUT = RegisterMask<WUTR, (0xffffu << 0x0u)>; + using WUTOCLR = RegisterMask<WUTR, (0xffffu << 0x10u)>; + }; + struct CR : public MemRegister<uint32_t, 0x40002818> { + using WUCKSEL = RegisterMask<CR, (0x7u << 0x0u)>; + using TSEDGE = RegisterMask<CR, (0x1u << 0x3u)>; + using REFCKON = RegisterMask<CR, (0x1u << 0x4u)>; + using BYPSHAD = RegisterMask<CR, (0x1u << 0x5u)>; + using FMT = RegisterMask<CR, (0x1u << 0x6u)>; + using SSRUIE = RegisterMask<CR, (0x1u << 0x7u)>; + using ALRAE = RegisterMask<CR, (0x1u << 0x8u)>; + using ALRBE = RegisterMask<CR, (0x1u << 0x9u)>; + using WUTE = RegisterMask<CR, (0x1u << 0xau)>; + using TSE = RegisterMask<CR, (0x1u << 0xbu)>; + using ALRAIE = RegisterMask<CR, (0x1u << 0xcu)>; + using ALRBIE = RegisterMask<CR, (0x1u << 0xdu)>; + using WUTIE = RegisterMask<CR, (0x1u << 0xeu)>; + using TSIE = RegisterMask<CR, (0x1u << 0xfu)>; + using ADD1H = RegisterMask<CR, (0x1u << 0x10u)>; + using SUB1H = RegisterMask<CR, (0x1u << 0x11u)>; + using BKP = RegisterMask<CR, (0x1u << 0x12u)>; + using COSEL = RegisterMask<CR, (0x1u << 0x13u)>; + using POL = RegisterMask<CR, (0x1u << 0x14u)>; + using OSEL = RegisterMask<CR, (0x3u << 0x15u)>; + using COE = RegisterMask<CR, (0x1u << 0x17u)>; + using ITSE = RegisterMask<CR, (0x1u << 0x18u)>; + using TAMPTS = RegisterMask<CR, (0x1u << 0x19u)>; + using TAMPOE = RegisterMask<CR, (0x1u << 0x1au)>; + using ALRAFCLR = RegisterMask<CR, (0x1u << 0x1bu)>; + using ALRBFCLR = RegisterMask<CR, (0x1u << 0x1cu)>; + using TAMPALRM_PU = RegisterMask<CR, (0x1u << 0x1du)>; + using TAMPALRM_TYPE = RegisterMask<CR, (0x1u << 0x1eu)>; + using OUT2EN = RegisterMask<CR, (0x1u << 0x1fu)>; + }; + struct WPR : public MemRegister<uint32_t, 0x40002824> { + using KEY = RegisterMask<WPR, (0xffu << 0x0u)>; + }; + struct CALR : public MemRegister<uint32_t, 0x40002828> { + using CALM = RegisterMask<CALR, (0x1ffu << 0x0u)>; + using LPCAL = RegisterMask<CALR, (0x1u << 0xcu)>; + using CALW16 = RegisterMask<CALR, (0x1u << 0xdu)>; + using CALW8 = RegisterMask<CALR, (0x1u << 0xeu)>; + using CALP = RegisterMask<CALR, (0x1u << 0xfu)>; + }; + struct SHIFTR : public MemRegister<uint32_t, 0x4000282c> { + using SUBFS = RegisterMask<SHIFTR, (0x7fffu << 0x0u)>; + using ADD1S = RegisterMask<SHIFTR, (0x1u << 0x1fu)>; + }; + struct TSTR : public MemRegister<uint32_t, 0x40002830> { + using SU = RegisterMask<TSTR, (0xfu << 0x0u)>; + using ST = RegisterMask<TSTR, (0x7u << 0x4u)>; + using MNU = RegisterMask<TSTR, (0xfu << 0x8u)>; + using MNT = RegisterMask<TSTR, (0x7u << 0xcu)>; + using HU = RegisterMask<TSTR, (0xfu << 0x10u)>; + using HT = RegisterMask<TSTR, (0x3u << 0x14u)>; + using PM = RegisterMask<TSTR, (0x1u << 0x16u)>; + }; + struct TSDR : public MemRegister<uint32_t, 0x40002834> { + using DU = RegisterMask<TSDR, (0xfu << 0x0u)>; + using DT = RegisterMask<TSDR, (0x3u << 0x4u)>; + using MU = RegisterMask<TSDR, (0xfu << 0x8u)>; + using MT = RegisterMask<TSDR, (0x1u << 0xcu)>; + using WDU = RegisterMask<TSDR, (0x7u << 0xdu)>; + }; + struct TSSSR : public MemRegister<uint32_t, 0x40002838> { + using SS = RegisterMask<TSSSR, (0x0u << 0x0u)>; + }; + struct ALRMAR : public MemRegister<uint32_t, 0x40002840> { + using SU = RegisterMask<ALRMAR, (0xfu << 0x0u)>; + using ST = RegisterMask<ALRMAR, (0x7u << 0x4u)>; + using MSK1 = RegisterMask<ALRMAR, (0x1u << 0x7u)>; + using MNU = RegisterMask<ALRMAR, (0xfu << 0x8u)>; + using MNT = RegisterMask<ALRMAR, (0x7u << 0xcu)>; + using MSK2 = RegisterMask<ALRMAR, (0x1u << 0xfu)>; + using HU = RegisterMask<ALRMAR, (0xfu << 0x10u)>; + using HT = RegisterMask<ALRMAR, (0x3u << 0x14u)>; + using PM = RegisterMask<ALRMAR, (0x1u << 0x16u)>; + using MSK3 = RegisterMask<ALRMAR, (0x1u << 0x17u)>; + using DU = RegisterMask<ALRMAR, (0xfu << 0x18u)>; + using DT = RegisterMask<ALRMAR, (0x3u << 0x1cu)>; + using WDSEL = RegisterMask<ALRMAR, (0x1u << 0x1eu)>; + using MSK4 = RegisterMask<ALRMAR, (0x1u << 0x1fu)>; + }; + struct ALRMASSR : public MemRegister<uint32_t, 0x40002844> { + using SS = RegisterMask<ALRMASSR, (0x7fffu << 0x0u)>; + using MASKSS = RegisterMask<ALRMASSR, (0x3fu << 0x18u)>; + using SSCLR = RegisterMask<ALRMASSR, (0x1u << 0x1fu)>; + }; + struct ALRMBR : public MemRegister<uint32_t, 0x40002848> { + using SU = RegisterMask<ALRMBR, (0xfu << 0x0u)>; + using ST = RegisterMask<ALRMBR, (0x7u << 0x4u)>; + using MSK1 = RegisterMask<ALRMBR, (0x1u << 0x7u)>; + using MNU = RegisterMask<ALRMBR, (0xfu << 0x8u)>; + using MNT = RegisterMask<ALRMBR, (0x7u << 0xcu)>; + using MSK2 = RegisterMask<ALRMBR, (0x1u << 0xfu)>; + using HU = RegisterMask<ALRMBR, (0xfu << 0x10u)>; + using HT = RegisterMask<ALRMBR, (0x3u << 0x14u)>; + using PM = RegisterMask<ALRMBR, (0x1u << 0x16u)>; + using MSK3 = RegisterMask<ALRMBR, (0x1u << 0x17u)>; + using DU = RegisterMask<ALRMBR, (0xfu << 0x18u)>; + using DT = RegisterMask<ALRMBR, (0x3u << 0x1cu)>; + using WDSEL = RegisterMask<ALRMBR, (0x1u << 0x1eu)>; + using MSK4 = RegisterMask<ALRMBR, (0x1u << 0x1fu)>; + }; + struct ALRMBSSR : public MemRegister<uint32_t, 0x4000284c> { + using SS = RegisterMask<ALRMBSSR, (0x7fffu << 0x0u)>; + using MASKSS = RegisterMask<ALRMBSSR, (0x3fu << 0x18u)>; + using SSCLR = RegisterMask<ALRMBSSR, (0x1u << 0x1fu)>; + }; + struct SR : public MemRegister<uint32_t, 0x40002850> { + using ALRAF = RegisterMask<SR, (0x1u << 0x0u)>; + using ALRBF = RegisterMask<SR, (0x1u << 0x1u)>; + using WUTF = RegisterMask<SR, (0x1u << 0x2u)>; + using TSF = RegisterMask<SR, (0x1u << 0x3u)>; + using TSOVF = RegisterMask<SR, (0x1u << 0x4u)>; + using ITSF = RegisterMask<SR, (0x1u << 0x5u)>; + using SSRUF = RegisterMask<SR, (0x1u << 0x6u)>; + }; + struct MISR : public MemRegister<uint32_t, 0x40002854> { + using ALRAMF = RegisterMask<MISR, (0x1u << 0x0u)>; + using ALRBMF = RegisterMask<MISR, (0x1u << 0x1u)>; + using WUTMF = RegisterMask<MISR, (0x1u << 0x2u)>; + using TSMF = RegisterMask<MISR, (0x1u << 0x3u)>; + using TSOVMF = RegisterMask<MISR, (0x1u << 0x4u)>; + using ITSMF = RegisterMask<MISR, (0x1u << 0x5u)>; + using SSRUMF = RegisterMask<MISR, (0x1u << 0x6u)>; + }; + struct SCR : public MemRegister<uint32_t, 0x4000285c> { + using CALRAF = RegisterMask<SCR, (0x1u << 0x0u)>; + using CALRBF = RegisterMask<SCR, (0x1u << 0x1u)>; + using CWUTF = RegisterMask<SCR, (0x1u << 0x2u)>; + using CTSF = RegisterMask<SCR, (0x1u << 0x3u)>; + using CTSOVF = RegisterMask<SCR, (0x1u << 0x4u)>; + using CITSF = RegisterMask<SCR, (0x1u << 0x5u)>; + using CSSRUF = RegisterMask<SCR, (0x1u << 0x6u)>; + }; + struct ALRABINR : public MemRegister<uint32_t, 0x40002870> { + using SS = RegisterMask<ALRABINR, (0x0u << 0x0u)>; + }; + struct ALRBBINR : public MemRegister<uint32_t, 0x40002874> { + using SS = RegisterMask<ALRBBINR, (0x0u << 0x0u)>; + }; + using ALL = RegisterGroup<TR, DR, SSR, ICSR, PRER, WUTR, CR, WPR, CALR, SHIFTR, TSTR, TSDR, TSSSR, ALRMAR, ALRMASSR, ALRMBR, ALRMBSSR, SR, MISR, SCR, ALRABINR, ALRBBINR>; + } + namespace SPI1 { + struct CR1 : public MemRegister<uint16_t, 0x40013000> { + using CPHA = RegisterMask<CR1, (0x1u << 0x0u)>; + using CPOL = RegisterMask<CR1, (0x1u << 0x1u)>; + using MSTR = RegisterMask<CR1, (0x1u << 0x2u)>; + using BR = RegisterMask<CR1, (0x7u << 0x3u)>; + using SPE = RegisterMask<CR1, (0x1u << 0x6u)>; + using LSBFIRST = RegisterMask<CR1, (0x1u << 0x7u)>; + using SSI = RegisterMask<CR1, (0x1u << 0x8u)>; + using SSM = RegisterMask<CR1, (0x1u << 0x9u)>; + using RXONLY = RegisterMask<CR1, (0x1u << 0xau)>; + using CRCL = RegisterMask<CR1, (0x1u << 0xbu)>; + using CRCNEXT = RegisterMask<CR1, (0x1u << 0xcu)>; + using CRCEN = RegisterMask<CR1, (0x1u << 0xdu)>; + using BIDIOE = RegisterMask<CR1, (0x1u << 0xeu)>; + using BIDIMODE = RegisterMask<CR1, (0x1u << 0xfu)>; + }; + struct CR2 : public MemRegister<uint16_t, 0x40013004> { + using RXDMAEN = RegisterMask<CR2, (0x1u << 0x0u)>; + using TXDMAEN = RegisterMask<CR2, (0x1u << 0x1u)>; + using SSOE = RegisterMask<CR2, (0x1u << 0x2u)>; + using NSSP = RegisterMask<CR2, (0x1u << 0x3u)>; + using FRF = RegisterMask<CR2, (0x1u << 0x4u)>; + using ERRIE = RegisterMask<CR2, (0x1u << 0x5u)>; + using RXNEIE = RegisterMask<CR2, (0x1u << 0x6u)>; + using TXEIE = RegisterMask<CR2, (0x1u << 0x7u)>; + using DS = RegisterMask<CR2, (0xfu << 0x8u)>; + using FRXTH = RegisterMask<CR2, (0x1u << 0xcu)>; + using LDMA_RX = RegisterMask<CR2, (0x1u << 0xdu)>; + using LDMA_TX = RegisterMask<CR2, (0x1u << 0xeu)>; + }; + struct SR : public MemRegister<uint16_t, 0x40013008> { + using RXNE = RegisterMask<SR, (0x1u << 0x0u)>; + using TXE = RegisterMask<SR, (0x1u << 0x1u)>; + using CRCERR = RegisterMask<SR, (0x1u << 0x4u)>; + using MODF = RegisterMask<SR, (0x1u << 0x5u)>; + using OVR = RegisterMask<SR, (0x1u << 0x6u)>; + using BSY = RegisterMask<SR, (0x1u << 0x7u)>; + using FRE = RegisterMask<SR, (0x1u << 0x8u)>; + using FRLVL = RegisterMask<SR, (0x3u << 0x9u)>; + using FTLVL = RegisterMask<SR, (0x3u << 0xbu)>; + }; + struct DR : public MemRegister<uint16_t, 0x4001300c> { + using val = RegisterMask<DR, (0xffffu << 0x0u)>; + }; + struct CRCPR : public MemRegister<uint16_t, 0x40013010> { + using CRCPOLY = RegisterMask<CRCPR, (0xffffu << 0x0u)>; + }; + struct RXCRCR : public MemRegister<uint16_t, 0x40013014> { + using RXCRC = RegisterMask<RXCRCR, (0xffffu << 0x0u)>; + }; + struct TXCRCR : public MemRegister<uint16_t, 0x40013018> { + using TXCRC = RegisterMask<TXCRCR, (0xffffu << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR2, SR, DR, CRCPR, RXCRCR, TXCRCR>; + } + namespace SPI2 { + struct CR1 : public MemRegister<uint16_t, 0x40003800> { + using CPHA = RegisterMask<CR1, (0x1u << 0x0u)>; + using CPOL = RegisterMask<CR1, (0x1u << 0x1u)>; + using MSTR = RegisterMask<CR1, (0x1u << 0x2u)>; + using BR = RegisterMask<CR1, (0x7u << 0x3u)>; + using SPE = RegisterMask<CR1, (0x1u << 0x6u)>; + using LSBFIRST = RegisterMask<CR1, (0x1u << 0x7u)>; + using SSI = RegisterMask<CR1, (0x1u << 0x8u)>; + using SSM = RegisterMask<CR1, (0x1u << 0x9u)>; + using RXONLY = RegisterMask<CR1, (0x1u << 0xau)>; + using CRCL = RegisterMask<CR1, (0x1u << 0xbu)>; + using CRCNEXT = RegisterMask<CR1, (0x1u << 0xcu)>; + using CRCEN = RegisterMask<CR1, (0x1u << 0xdu)>; + using BIDIOE = RegisterMask<CR1, (0x1u << 0xeu)>; + using BIDIMODE = RegisterMask<CR1, (0x1u << 0xfu)>; + }; + struct CR2 : public MemRegister<uint16_t, 0x40003804> { + using RXDMAEN = RegisterMask<CR2, (0x1u << 0x0u)>; + using TXDMAEN = RegisterMask<CR2, (0x1u << 0x1u)>; + using SSOE = RegisterMask<CR2, (0x1u << 0x2u)>; + using NSSP = RegisterMask<CR2, (0x1u << 0x3u)>; + using FRF = RegisterMask<CR2, (0x1u << 0x4u)>; + using ERRIE = RegisterMask<CR2, (0x1u << 0x5u)>; + using RXNEIE = RegisterMask<CR2, (0x1u << 0x6u)>; + using TXEIE = RegisterMask<CR2, (0x1u << 0x7u)>; + using DS = RegisterMask<CR2, (0xfu << 0x8u)>; + using FRXTH = RegisterMask<CR2, (0x1u << 0xcu)>; + using LDMA_RX = RegisterMask<CR2, (0x1u << 0xdu)>; + using LDMA_TX = RegisterMask<CR2, (0x1u << 0xeu)>; + }; + struct SR : public MemRegister<uint16_t, 0x40003808> { + using RXNE = RegisterMask<SR, (0x1u << 0x0u)>; + using TXE = RegisterMask<SR, (0x1u << 0x1u)>; + using CRCERR = RegisterMask<SR, (0x1u << 0x4u)>; + using MODF = RegisterMask<SR, (0x1u << 0x5u)>; + using OVR = RegisterMask<SR, (0x1u << 0x6u)>; + using BSY = RegisterMask<SR, (0x1u << 0x7u)>; + using FRE = RegisterMask<SR, (0x1u << 0x8u)>; + using FRLVL = RegisterMask<SR, (0x3u << 0x9u)>; + using FTLVL = RegisterMask<SR, (0x3u << 0xbu)>; + }; + struct DR : public MemRegister<uint16_t, 0x4000380c> { + using val = RegisterMask<DR, (0xffffu << 0x0u)>; + }; + struct CRCPR : public MemRegister<uint16_t, 0x40003810> { + using CRCPOLY = RegisterMask<CRCPR, (0xffffu << 0x0u)>; + }; + struct RXCRCR : public MemRegister<uint16_t, 0x40003814> { + using RXCRC = RegisterMask<RXCRCR, (0xffffu << 0x0u)>; + }; + struct TXCRCR : public MemRegister<uint16_t, 0x40003818> { + using TXCRC = RegisterMask<TXCRCR, (0xffffu << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR2, SR, DR, CRCPR, RXCRCR, TXCRCR>; + } + namespace SPI3 { + struct CR1 : public MemRegister<uint16_t, 0x40003c00> { + using CPHA = RegisterMask<CR1, (0x1u << 0x0u)>; + using CPOL = RegisterMask<CR1, (0x1u << 0x1u)>; + using MSTR = RegisterMask<CR1, (0x1u << 0x2u)>; + using BR = RegisterMask<CR1, (0x7u << 0x3u)>; + using SPE = RegisterMask<CR1, (0x1u << 0x6u)>; + using LSBFIRST = RegisterMask<CR1, (0x1u << 0x7u)>; + using SSI = RegisterMask<CR1, (0x1u << 0x8u)>; + using SSM = RegisterMask<CR1, (0x1u << 0x9u)>; + using RXONLY = RegisterMask<CR1, (0x1u << 0xau)>; + using CRCL = RegisterMask<CR1, (0x1u << 0xbu)>; + using CRCNEXT = RegisterMask<CR1, (0x1u << 0xcu)>; + using CRCEN = RegisterMask<CR1, (0x1u << 0xdu)>; + using BIDIOE = RegisterMask<CR1, (0x1u << 0xeu)>; + using BIDIMODE = RegisterMask<CR1, (0x1u << 0xfu)>; + }; + struct CR2 : public MemRegister<uint16_t, 0x40003c04> { + using RXDMAEN = RegisterMask<CR2, (0x1u << 0x0u)>; + using TXDMAEN = RegisterMask<CR2, (0x1u << 0x1u)>; + using SSOE = RegisterMask<CR2, (0x1u << 0x2u)>; + using NSSP = RegisterMask<CR2, (0x1u << 0x3u)>; + using FRF = RegisterMask<CR2, (0x1u << 0x4u)>; + using ERRIE = RegisterMask<CR2, (0x1u << 0x5u)>; + using RXNEIE = RegisterMask<CR2, (0x1u << 0x6u)>; + using TXEIE = RegisterMask<CR2, (0x1u << 0x7u)>; + using DS = RegisterMask<CR2, (0xfu << 0x8u)>; + using FRXTH = RegisterMask<CR2, (0x1u << 0xcu)>; + using LDMA_RX = RegisterMask<CR2, (0x1u << 0xdu)>; + using LDMA_TX = RegisterMask<CR2, (0x1u << 0xeu)>; + }; + struct SR : public MemRegister<uint16_t, 0x40003c08> { + using RXNE = RegisterMask<SR, (0x1u << 0x0u)>; + using TXE = RegisterMask<SR, (0x1u << 0x1u)>; + using CRCERR = RegisterMask<SR, (0x1u << 0x4u)>; + using MODF = RegisterMask<SR, (0x1u << 0x5u)>; + using OVR = RegisterMask<SR, (0x1u << 0x6u)>; + using BSY = RegisterMask<SR, (0x1u << 0x7u)>; + using FRE = RegisterMask<SR, (0x1u << 0x8u)>; + using FRLVL = RegisterMask<SR, (0x3u << 0x9u)>; + using FTLVL = RegisterMask<SR, (0x3u << 0xbu)>; + }; + struct DR : public MemRegister<uint16_t, 0x40003c0c> { + using val = RegisterMask<DR, (0xffffu << 0x0u)>; + }; + struct CRCPR : public MemRegister<uint16_t, 0x40003c10> { + using CRCPOLY = RegisterMask<CRCPR, (0xffffu << 0x0u)>; + }; + struct RXCRCR : public MemRegister<uint16_t, 0x40003c14> { + using RXCRC = RegisterMask<RXCRCR, (0xffffu << 0x0u)>; + }; + struct TXCRCR : public MemRegister<uint16_t, 0x40003c18> { + using TXCRC = RegisterMask<TXCRCR, (0xffffu << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR2, SR, DR, CRCPR, RXCRCR, TXCRCR>; + } + namespace SYSCFG { + struct CFGR1 : public MemRegister<uint32_t, 0x40010000> { + using MEM_MODE = RegisterMask<CFGR1, (0x3u << 0x0u)>; + using PA11_RMP = RegisterMask<CFGR1, (0x1u << 0x3u)>; + using PA12_RMP = RegisterMask<CFGR1, (0x1u << 0x4u)>; + using IR_POL = RegisterMask<CFGR1, (0x1u << 0x5u)>; + using IR_MOD = RegisterMask<CFGR1, (0x3u << 0x6u)>; + using BOOSTEN = RegisterMask<CFGR1, (0x1u << 0x8u)>; + using I2C_PB6_FMP = RegisterMask<CFGR1, (0x1u << 0x10u)>; + using I2C_PB7_FMP = RegisterMask<CFGR1, (0x1u << 0x11u)>; + using I2C_PB8_FMP = RegisterMask<CFGR1, (0x1u << 0x12u)>; + using I2C_PB9_FMP = RegisterMask<CFGR1, (0x1u << 0x13u)>; + using I2C_PA9_FMP = RegisterMask<CFGR1, (0x1u << 0x16u)>; + using I2C_PA10_FMP = RegisterMask<CFGR1, (0x1u << 0x17u)>; + using I2C3_FMP = RegisterMask<CFGR1, (0x1u << 0x18u)>; + }; + struct CFGR2 : public MemRegister<uint32_t, 0x40010018> { + using CCL = RegisterMask<CFGR2, (0x1u << 0x0u)>; + using SPL = RegisterMask<CFGR2, (0x1u << 0x1u)>; + using PVDL = RegisterMask<CFGR2, (0x1u << 0x2u)>; + using ECCL = RegisterMask<CFGR2, (0x1u << 0x3u)>; + using BKPL = RegisterMask<CFGR2, (0x1u << 0x4u)>; + using BKPF = RegisterMask<CFGR2, (0x1u << 0x7u)>; + using SPF = RegisterMask<CFGR2, (0x1u << 0x8u)>; + }; + struct SCSR : public MemRegister<uint32_t, 0x4001001c> { + using SRAM2ER = RegisterMask<SCSR, (0x1u << 0x0u)>; + using SRAM2BSY = RegisterMask<SCSR, (0x1u << 0x1u)>; + }; + struct SKR : public MemRegister<uint32_t, 0x40010020> { + using KEY = RegisterMask<SKR, (0xffu << 0x0u)>; + }; + struct TSCCR : public MemRegister<uint32_t, 0x40010024> { + using G2_IO1 = RegisterMask<TSCCR, (0x1u << 0x0u)>; + using G2_IO3 = RegisterMask<TSCCR, (0x1u << 0x1u)>; + using G4_IO3 = RegisterMask<TSCCR, (0x1u << 0x2u)>; + using G6_IO1 = RegisterMask<TSCCR, (0x1u << 0x3u)>; + using G7_IO1 = RegisterMask<TSCCR, (0x1u << 0x4u)>; + using TSC_IOCTRL = RegisterMask<TSCCR, (0x1u << 0x5u)>; + }; + struct ITLINE0 : public MemRegister<uint32_t, 0x40010080> { + using WWDG = RegisterMask<ITLINE0, (0x1u << 0x0u)>; + }; + struct ITLINE1 : public MemRegister<uint32_t, 0x40010084> { + using PVDOUT = RegisterMask<ITLINE1, (0x1u << 0x0u)>; + using PVMOUT1 = RegisterMask<ITLINE1, (0x1u << 0x1u)>; + using PVMOUT3 = RegisterMask<ITLINE1, (0x1u << 0x2u)>; + using PVMOUT4 = RegisterMask<ITLINE1, (0x1u << 0x3u)>; + }; + struct ITLINE2 : public MemRegister<uint32_t, 0x40010088> { + using TAMP = RegisterMask<ITLINE2, (0x1u << 0x0u)>; + using RTC = RegisterMask<ITLINE2, (0x1u << 0x1u)>; + }; + struct ITLINE3 : public MemRegister<uint32_t, 0x4001008c> { + using FLASH_ITF = RegisterMask<ITLINE3, (0x1u << 0x0u)>; + using FLASH_ECC = RegisterMask<ITLINE3, (0x1u << 0x1u)>; + }; + struct ITLINE4 : public MemRegister<uint32_t, 0x40010090> { + using RCC = RegisterMask<ITLINE4, (0x1u << 0x0u)>; + using CRS = RegisterMask<ITLINE4, (0x1u << 0x1u)>; + }; + struct ITLINE5 : public MemRegister<uint32_t, 0x40010094> { + using EXTI0 = RegisterMask<ITLINE5, (0x1u << 0x0u)>; + using EXTI1 = RegisterMask<ITLINE5, (0x1u << 0x1u)>; + }; + struct ITLINE6 : public MemRegister<uint32_t, 0x40010098> { + using EXTI2 = RegisterMask<ITLINE6, (0x1u << 0x0u)>; + using EXTI3 = RegisterMask<ITLINE6, (0x1u << 0x1u)>; + }; + struct ITLINE7 : public MemRegister<uint32_t, 0x4001009c> { + using EXTI4 = RegisterMask<ITLINE7, (0x1u << 0x0u)>; + using EXTI5 = RegisterMask<ITLINE7, (0x1u << 0x1u)>; + using EXTI6 = RegisterMask<ITLINE7, (0x1u << 0x2u)>; + using EXTI7 = RegisterMask<ITLINE7, (0x1u << 0x3u)>; + using EXTI8 = RegisterMask<ITLINE7, (0x1u << 0x4u)>; + using EXTI9 = RegisterMask<ITLINE7, (0x1u << 0x5u)>; + using EXTI10 = RegisterMask<ITLINE7, (0x1u << 0x6u)>; + using EXTI11 = RegisterMask<ITLINE7, (0x1u << 0x7u)>; + using EXTI12 = RegisterMask<ITLINE7, (0x1u << 0x8u)>; + using EXTI13 = RegisterMask<ITLINE7, (0x1u << 0x9u)>; + using EXTI14 = RegisterMask<ITLINE7, (0x1u << 0xau)>; + using EXTI15 = RegisterMask<ITLINE7, (0x1u << 0xbu)>; + }; + struct ITLINE8 : public MemRegister<uint32_t, 0x400100a0> { + using USB = RegisterMask<ITLINE8, (0x1u << 0x0u)>; + }; + struct ITLINE9 : public MemRegister<uint32_t, 0x400100a4> { + using DMA1_CH1 = RegisterMask<ITLINE9, (0x1u << 0x0u)>; + }; + struct ITLINE10 : public MemRegister<uint32_t, 0x400100a8> { + using DMA1_CH2 = RegisterMask<ITLINE10, (0x1u << 0x0u)>; + using DMA1_CH3 = RegisterMask<ITLINE10, (0x1u << 0x1u)>; + }; + struct ITLINE11 : public MemRegister<uint32_t, 0x400100ac> { + using DMAMUX = RegisterMask<ITLINE11, (0x1u << 0x0u)>; + using DMA1_CH4 = RegisterMask<ITLINE11, (0x1u << 0x1u)>; + using DMA1_CH5 = RegisterMask<ITLINE11, (0x1u << 0x2u)>; + using DMA1_CH6 = RegisterMask<ITLINE11, (0x1u << 0x3u)>; + using DMA1_CH7 = RegisterMask<ITLINE11, (0x1u << 0x4u)>; + using DMA2_CH1 = RegisterMask<ITLINE11, (0x1u << 0x5u)>; + using DMA2_CH2 = RegisterMask<ITLINE11, (0x1u << 0x6u)>; + using DMA2_CH3 = RegisterMask<ITLINE11, (0x1u << 0x7u)>; + using DMA2_CH4 = RegisterMask<ITLINE11, (0x1u << 0x8u)>; + using DMA2_CH5 = RegisterMask<ITLINE11, (0x1u << 0x9u)>; + }; + struct ITLINE12 : public MemRegister<uint32_t, 0x400100b0> { + using ADC = RegisterMask<ITLINE12, (0x1u << 0x0u)>; + using COMP1 = RegisterMask<ITLINE12, (0x1u << 0x1u)>; + using COMP2 = RegisterMask<ITLINE12, (0x1u << 0x2u)>; + }; + struct ITLINE13 : public MemRegister<uint32_t, 0x400100b4> { + using TIM1_CCU = RegisterMask<ITLINE13, (0x1u << 0x0u)>; + using TIM1_TRG = RegisterMask<ITLINE13, (0x1u << 0x1u)>; + using TIM1_UPD = RegisterMask<ITLINE13, (0x1u << 0x2u)>; + using TIM1_BRK = RegisterMask<ITLINE13, (0x1u << 0x3u)>; + }; + struct ITLINE14 : public MemRegister<uint32_t, 0x400100b8> { + using TIM1_CC1 = RegisterMask<ITLINE14, (0x1u << 0x0u)>; + using TIM1_CC2 = RegisterMask<ITLINE14, (0x1u << 0x1u)>; + using TIM1_CC3 = RegisterMask<ITLINE14, (0x1u << 0x2u)>; + using TIM1_CC4 = RegisterMask<ITLINE14, (0x1u << 0x3u)>; + }; + struct ITLINE15 : public MemRegister<uint32_t, 0x400100bc> { + using TIM2 = RegisterMask<ITLINE15, (0x1u << 0x0u)>; + }; + struct ITLINE16 : public MemRegister<uint32_t, 0x400100c0> { + using TIM3 = RegisterMask<ITLINE16, (0x1u << 0x0u)>; + }; + struct ITLINE17 : public MemRegister<uint32_t, 0x400100c4> { + using TIM6 = RegisterMask<ITLINE17, (0x1u << 0x0u)>; + using DAC = RegisterMask<ITLINE17, (0x1u << 0x1u)>; + using LPTIM1 = RegisterMask<ITLINE17, (0x1u << 0x2u)>; + }; + struct ITLINE18 : public MemRegister<uint32_t, 0x400100c8> { + using TIM7 = RegisterMask<ITLINE18, (0x1u << 0x0u)>; + using LPTIM2 = RegisterMask<ITLINE18, (0x1u << 0x1u)>; + }; + struct ITLINE19 : public MemRegister<uint32_t, 0x400100cc> { + using TIM15 = RegisterMask<ITLINE19, (0x1u << 0x0u)>; + using LPTIM3 = RegisterMask<ITLINE19, (0x1u << 0x1u)>; + }; + struct ITLINE20 : public MemRegister<uint32_t, 0x400100d0> { + using TIM16 = RegisterMask<ITLINE20, (0x1u << 0x0u)>; + }; + struct ITLINE21 : public MemRegister<uint32_t, 0x400100d4> { + using TSC_MCE = RegisterMask<ITLINE21, (0x1u << 0x0u)>; + using TSC_EOA = RegisterMask<ITLINE21, (0x1u << 0x1u)>; + }; + struct ITLINE22 : public MemRegister<uint32_t, 0x400100d8> { + using LCD = RegisterMask<ITLINE22, (0x1u << 0x0u)>; + }; + struct ITLINE23 : public MemRegister<uint32_t, 0x400100dc> { + using I2C1 = RegisterMask<ITLINE23, (0x1u << 0x0u)>; + }; + struct ITLINE24 : public MemRegister<uint32_t, 0x400100e0> { + using I2C2 = RegisterMask<ITLINE24, (0x1u << 0x0u)>; + using I2C4 = RegisterMask<ITLINE24, (0x1u << 0x1u)>; + using I2C3 = RegisterMask<ITLINE24, (0x1u << 0x2u)>; + }; + struct ITLINE25 : public MemRegister<uint32_t, 0x400100e4> { + using SPI1 = RegisterMask<ITLINE25, (0x1u << 0x0u)>; + }; + struct ITLINE26 : public MemRegister<uint32_t, 0x400100e8> { + using SPI2 = RegisterMask<ITLINE26, (0x1u << 0x0u)>; + using SPI3 = RegisterMask<ITLINE26, (0x1u << 0x1u)>; + }; + struct ITLINE27 : public MemRegister<uint32_t, 0x400100ec> { + using USART1 = RegisterMask<ITLINE27, (0x1u << 0x0u)>; + }; + struct ITLINE28 : public MemRegister<uint32_t, 0x400100f0> { + using USART2 = RegisterMask<ITLINE28, (0x1u << 0x0u)>; + using LPUART2 = RegisterMask<ITLINE28, (0x1u << 0x1u)>; + }; + struct ITLINE29 : public MemRegister<uint32_t, 0x400100f4> { + using USART3 = RegisterMask<ITLINE29, (0x1u << 0x0u)>; + using LPUART1 = RegisterMask<ITLINE29, (0x1u << 0x1u)>; + }; + struct ITLINE30 : public MemRegister<uint32_t, 0x400100f8> { + using USART4 = RegisterMask<ITLINE30, (0x1u << 0x0u)>; + using LPUART3 = RegisterMask<ITLINE30, (0x1u << 0x1u)>; + }; + struct ITLINE31 : public MemRegister<uint32_t, 0x400100fc> { + using RNG = RegisterMask<ITLINE31, (0x1u << 0x0u)>; + using AES = RegisterMask<ITLINE31, (0x1u << 0x1u)>; + }; + using ALL = RegisterGroup<CFGR1, CFGR2, SCSR, SKR, TSCCR, ITLINE0, ITLINE1, ITLINE2, ITLINE3, ITLINE4, ITLINE5, ITLINE6, ITLINE7, ITLINE8, ITLINE9, ITLINE10, ITLINE11, ITLINE12, ITLINE13, ITLINE14, ITLINE15, ITLINE16, ITLINE17, ITLINE18, ITLINE19, ITLINE20, ITLINE21, ITLINE22, ITLINE23, ITLINE24, ITLINE25, ITLINE26, ITLINE27, ITLINE28, ITLINE29, ITLINE30, ITLINE31>; + } + namespace TAMP { + struct CR1 : public MemRegister<uint32_t, 0x4000b000> { + using TAMP1E = RegisterMask<CR1, (0x1u << 0x0u)>; + using TAMP2E = RegisterMask<CR1, (0x1u << 0x1u)>; + using TAMP3E = RegisterMask<CR1, (0x1u << 0x2u)>; + using TAMP4E = RegisterMask<CR1, (0x1u << 0x3u)>; + using TAMP5E = RegisterMask<CR1, (0x1u << 0x4u)>; + using ITAMP3E = RegisterMask<CR1, (0x1u << 0x12u)>; + using ITAMP4E = RegisterMask<CR1, (0x1u << 0x13u)>; + using ITAMP5E = RegisterMask<CR1, (0x1u << 0x14u)>; + using ITAMP6E = RegisterMask<CR1, (0x1u << 0x15u)>; + }; + struct CR2 : public MemRegister<uint32_t, 0x4000b004> { + using TAMP1POM = RegisterMask<CR2, (0x1u << 0x0u)>; + using TAMP2POM = RegisterMask<CR2, (0x1u << 0x1u)>; + using TAMP3POM = RegisterMask<CR2, (0x1u << 0x2u)>; + using TAMP4POM = RegisterMask<CR2, (0x1u << 0x3u)>; + using TAMP5POM = RegisterMask<CR2, (0x1u << 0x4u)>; + using TAMP1MSK = RegisterMask<CR2, (0x1u << 0x10u)>; + using TAMP2MSK = RegisterMask<CR2, (0x1u << 0x11u)>; + using TAMP3MSK = RegisterMask<CR2, (0x1u << 0x12u)>; + using BKBLOCK = RegisterMask<CR2, (0x1u << 0x16u)>; + using BKERASE = RegisterMask<CR2, (0x1u << 0x17u)>; + using TAMP1TRG = RegisterMask<CR2, (0x1u << 0x18u)>; + using TAMP2TRG = RegisterMask<CR2, (0x1u << 0x19u)>; + using TAMP3TRG = RegisterMask<CR2, (0x1u << 0x1au)>; + using TAMP4TRG = RegisterMask<CR2, (0x1u << 0x1bu)>; + using TAMP5TRG = RegisterMask<CR2, (0x1u << 0x1cu)>; + }; + struct CR3 : public MemRegister<uint32_t, 0x4000b008> { + using ITAMP3POM = RegisterMask<CR3, (0x1u << 0x2u)>; + using ITAMP4POM = RegisterMask<CR3, (0x1u << 0x3u)>; + using ITAMP5POM = RegisterMask<CR3, (0x1u << 0x4u)>; + using ITAMP6POM = RegisterMask<CR3, (0x1u << 0x5u)>; + }; + struct FLTCR : public MemRegister<uint32_t, 0x4000b00c> { + using TAMPFREQ = RegisterMask<FLTCR, (0x7u << 0x0u)>; + using TAMPFLT = RegisterMask<FLTCR, (0x3u << 0x3u)>; + using TAMPPRCH = RegisterMask<FLTCR, (0x3u << 0x5u)>; + using TAMPPUDIS = RegisterMask<FLTCR, (0x1u << 0x7u)>; + }; + struct IER : public MemRegister<uint32_t, 0x4000b02c> { + using TAMP1IE = RegisterMask<IER, (0x1u << 0x0u)>; + using TAMP2IE = RegisterMask<IER, (0x1u << 0x1u)>; + using TAMP3IE = RegisterMask<IER, (0x1u << 0x2u)>; + using TAMP4IE = RegisterMask<IER, (0x1u << 0x3u)>; + using TAMP5IE = RegisterMask<IER, (0x1u << 0x4u)>; + using ITAMP3IE = RegisterMask<IER, (0x1u << 0x12u)>; + using ITAMP4IE = RegisterMask<IER, (0x1u << 0x13u)>; + using ITAMP5IE = RegisterMask<IER, (0x1u << 0x14u)>; + using ITAMP6IE = RegisterMask<IER, (0x1u << 0x15u)>; + }; + struct SR : public MemRegister<uint32_t, 0x4000b030> { + using TAMP1F = RegisterMask<SR, (0x1u << 0x0u)>; + using TAMP2F = RegisterMask<SR, (0x1u << 0x1u)>; + using TAMP3F = RegisterMask<SR, (0x1u << 0x2u)>; + using TAMP4F = RegisterMask<SR, (0x1u << 0x3u)>; + using TAMP5F = RegisterMask<SR, (0x1u << 0x4u)>; + using ITAMP3F = RegisterMask<SR, (0x1u << 0x12u)>; + using ITAMP4F = RegisterMask<SR, (0x1u << 0x13u)>; + using ITAMP5F = RegisterMask<SR, (0x1u << 0x14u)>; + using ITAMP6F = RegisterMask<SR, (0x1u << 0x15u)>; + }; + struct MISR : public MemRegister<uint32_t, 0x4000b034> { + using TAMP1MF = RegisterMask<MISR, (0x1u << 0x0u)>; + using TAMP2MF = RegisterMask<MISR, (0x1u << 0x1u)>; + using TAMP3MF = RegisterMask<MISR, (0x1u << 0x2u)>; + using TAMP4MF = RegisterMask<MISR, (0x1u << 0x3u)>; + using TAMP5MF = RegisterMask<MISR, (0x1u << 0x4u)>; + using ITAMP3MF = RegisterMask<MISR, (0x1u << 0x12u)>; + using ITAMP4MF = RegisterMask<MISR, (0x1u << 0x13u)>; + using ITAMP5MF = RegisterMask<MISR, (0x1u << 0x14u)>; + using ITAMP6MF = RegisterMask<MISR, (0x1u << 0x15u)>; + }; + struct SCR : public MemRegister<uint32_t, 0x4000b03c> { + using CTAMP1F = RegisterMask<SCR, (0x1u << 0x0u)>; + using CTAMP2F = RegisterMask<SCR, (0x1u << 0x1u)>; + using CTAMP3F = RegisterMask<SCR, (0x1u << 0x2u)>; + using CTAMP4F = RegisterMask<SCR, (0x1u << 0x3u)>; + using CTAMP5F = RegisterMask<SCR, (0x1u << 0x4u)>; + using CITAMP3F = RegisterMask<SCR, (0x1u << 0x12u)>; + using CITAMP4F = RegisterMask<SCR, (0x1u << 0x13u)>; + using CITAMP5F = RegisterMask<SCR, (0x1u << 0x14u)>; + using CITAMP6F = RegisterMask<SCR, (0x1u << 0x15u)>; + }; + struct BKP0R : public MemRegister<uint32_t, 0x4000b100> { + using BKP = RegisterMask<BKP0R, (0x0u << 0x0u)>; + }; + struct BKP1R : public MemRegister<uint32_t, 0x4000b104> { + using BKP = RegisterMask<BKP1R, (0x0u << 0x0u)>; + }; + struct BKP2R : public MemRegister<uint32_t, 0x4000b108> { + using BKP = RegisterMask<BKP2R, (0x0u << 0x0u)>; + }; + struct BKP3R : public MemRegister<uint32_t, 0x4000b10c> { + using BKP = RegisterMask<BKP3R, (0x0u << 0x0u)>; + }; + struct BKP4R : public MemRegister<uint32_t, 0x4000b110> { + using BKP = RegisterMask<BKP4R, (0x0u << 0x0u)>; + }; + struct BKP5R : public MemRegister<uint32_t, 0x4000b114> { + using BKP = RegisterMask<BKP5R, (0x0u << 0x0u)>; + }; + struct BKP6R : public MemRegister<uint32_t, 0x4000b118> { + using BKP = RegisterMask<BKP6R, (0x0u << 0x0u)>; + }; + struct BKP7R : public MemRegister<uint32_t, 0x4000b11c> { + using BKP = RegisterMask<BKP7R, (0x0u << 0x0u)>; + }; + struct BKP8R : public MemRegister<uint32_t, 0x4000b120> { + using BKP = RegisterMask<BKP8R, (0x0u << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR2, CR3, FLTCR, IER, SR, MISR, SCR, BKP0R, BKP1R, BKP2R, BKP3R, BKP4R, BKP5R, BKP6R, BKP7R, BKP8R>; + } + namespace TIM1 { + struct TIM1_CR1 : public MemRegister<uint16_t, 0x40012c00> { + using CEN = RegisterMask<TIM1_CR1, (0x1u << 0x0u)>; + using UDIS = RegisterMask<TIM1_CR1, (0x1u << 0x1u)>; + using URS = RegisterMask<TIM1_CR1, (0x1u << 0x2u)>; + using OPM = RegisterMask<TIM1_CR1, (0x1u << 0x3u)>; + using DIR = RegisterMask<TIM1_CR1, (0x1u << 0x4u)>; + using CMS = RegisterMask<TIM1_CR1, (0x3u << 0x5u)>; + using ARPE = RegisterMask<TIM1_CR1, (0x1u << 0x7u)>; + using CKD = RegisterMask<TIM1_CR1, (0x3u << 0x8u)>; + using UIFREMAP = RegisterMask<TIM1_CR1, (0x1u << 0xbu)>; + }; + struct TIM1_CR2 : public MemRegister<uint32_t, 0x40012c04> { + using CCPC = RegisterMask<TIM1_CR2, (0x1u << 0x0u)>; + using CCUS = RegisterMask<TIM1_CR2, (0x1u << 0x2u)>; + using CCDS = RegisterMask<TIM1_CR2, (0x1u << 0x3u)>; + using MMS = RegisterMask<TIM1_CR2, (0x7u << 0x4u)>; + using TI1S = RegisterMask<TIM1_CR2, (0x1u << 0x7u)>; + using OIS1 = RegisterMask<TIM1_CR2, (0x1u << 0x8u)>; + using OIS1N = RegisterMask<TIM1_CR2, (0x1u << 0x9u)>; + using OIS2 = RegisterMask<TIM1_CR2, (0x1u << 0xau)>; + using OIS2N = RegisterMask<TIM1_CR2, (0x1u << 0xbu)>; + using OIS3 = RegisterMask<TIM1_CR2, (0x1u << 0xcu)>; + using OIS3N = RegisterMask<TIM1_CR2, (0x1u << 0xdu)>; + using OIS4 = RegisterMask<TIM1_CR2, (0x1u << 0xeu)>; + using OIS5 = RegisterMask<TIM1_CR2, (0x1u << 0x10u)>; + using OIS6 = RegisterMask<TIM1_CR2, (0x1u << 0x12u)>; + using MMS2 = RegisterMask<TIM1_CR2, (0xfu << 0x14u)>; + }; + struct TIM1_SMCR : public MemRegister<uint32_t, 0x40012c08> { + using SMS = RegisterMask<TIM1_SMCR, (0x7u << 0x0u)>; + using OCCS = RegisterMask<TIM1_SMCR, (0x1u << 0x3u)>; + using TS = RegisterMask<TIM1_SMCR, (0x7u << 0x4u)>; + using MSM = RegisterMask<TIM1_SMCR, (0x1u << 0x7u)>; + using ETF = RegisterMask<TIM1_SMCR, (0xfu << 0x8u)>; + using ETPS = RegisterMask<TIM1_SMCR, (0x3u << 0xcu)>; + using ECE = RegisterMask<TIM1_SMCR, (0x1u << 0xeu)>; + using ETP = RegisterMask<TIM1_SMCR, (0x1u << 0xfu)>; + using SMS_1 = RegisterMask<TIM1_SMCR, (0x1u << 0x10u)>; + using TS_1 = RegisterMask<TIM1_SMCR, (0x3u << 0x14u)>; + }; + struct TIM1_DIER : public MemRegister<uint16_t, 0x40012c0c> { + using UIE = RegisterMask<TIM1_DIER, (0x1u << 0x0u)>; + using CC1IE = RegisterMask<TIM1_DIER, (0x1u << 0x1u)>; + using CC2IE = RegisterMask<TIM1_DIER, (0x1u << 0x2u)>; + using CC3IE = RegisterMask<TIM1_DIER, (0x1u << 0x3u)>; + using CC4IE = RegisterMask<TIM1_DIER, (0x1u << 0x4u)>; + using COMIE = RegisterMask<TIM1_DIER, (0x1u << 0x5u)>; + using TIE = RegisterMask<TIM1_DIER, (0x1u << 0x6u)>; + using BIE = RegisterMask<TIM1_DIER, (0x1u << 0x7u)>; + using UDE = RegisterMask<TIM1_DIER, (0x1u << 0x8u)>; + using CC1DE = RegisterMask<TIM1_DIER, (0x1u << 0x9u)>; + using CC2DE = RegisterMask<TIM1_DIER, (0x1u << 0xau)>; + using CC3DE = RegisterMask<TIM1_DIER, (0x1u << 0xbu)>; + using CC4DE = RegisterMask<TIM1_DIER, (0x1u << 0xcu)>; + using COMDE = RegisterMask<TIM1_DIER, (0x1u << 0xdu)>; + using TDE = RegisterMask<TIM1_DIER, (0x1u << 0xeu)>; + }; + struct TIM1_SR : public MemRegister<uint32_t, 0x40012c10> { + using UIF = RegisterMask<TIM1_SR, (0x1u << 0x0u)>; + using CC1IF = RegisterMask<TIM1_SR, (0x1u << 0x1u)>; + using CC2IF = RegisterMask<TIM1_SR, (0x1u << 0x2u)>; + using CC3IF = RegisterMask<TIM1_SR, (0x1u << 0x3u)>; + using CC4IF = RegisterMask<TIM1_SR, (0x1u << 0x4u)>; + using COMIF = RegisterMask<TIM1_SR, (0x1u << 0x5u)>; + using TIF = RegisterMask<TIM1_SR, (0x1u << 0x6u)>; + using BIF = RegisterMask<TIM1_SR, (0x1u << 0x7u)>; + using B2IF = RegisterMask<TIM1_SR, (0x1u << 0x8u)>; + using CC1OF = RegisterMask<TIM1_SR, (0x1u << 0x9u)>; + using CC2OF = RegisterMask<TIM1_SR, (0x1u << 0xau)>; + using CC3OF = RegisterMask<TIM1_SR, (0x1u << 0xbu)>; + using CC4OF = RegisterMask<TIM1_SR, (0x1u << 0xcu)>; + using SBIF = RegisterMask<TIM1_SR, (0x1u << 0xdu)>; + using CC5IF = RegisterMask<TIM1_SR, (0x1u << 0x10u)>; + using CC6IF = RegisterMask<TIM1_SR, (0x1u << 0x11u)>; + }; + struct TIM1_EGR : public MemRegister<uint16_t, 0x40012c14> { + using UG = RegisterMask<TIM1_EGR, (0x1u << 0x0u)>; + using CC1G = RegisterMask<TIM1_EGR, (0x1u << 0x1u)>; + using CC2G = RegisterMask<TIM1_EGR, (0x1u << 0x2u)>; + using CC3G = RegisterMask<TIM1_EGR, (0x1u << 0x3u)>; + using CC4G = RegisterMask<TIM1_EGR, (0x1u << 0x4u)>; + using COMG = RegisterMask<TIM1_EGR, (0x1u << 0x5u)>; + using TG = RegisterMask<TIM1_EGR, (0x1u << 0x6u)>; + using BG = RegisterMask<TIM1_EGR, (0x1u << 0x7u)>; + using B2G = RegisterMask<TIM1_EGR, (0x1u << 0x8u)>; + }; + struct TIM1_CCMR1_INPUT : public MemRegister<uint32_t, 0x40012c18> { + using CC1S = RegisterMask<TIM1_CCMR1_INPUT, (0x3u << 0x0u)>; + using IC1PSC = RegisterMask<TIM1_CCMR1_INPUT, (0x3u << 0x2u)>; + using IC1F = RegisterMask<TIM1_CCMR1_INPUT, (0xfu << 0x4u)>; + using CC2S = RegisterMask<TIM1_CCMR1_INPUT, (0x3u << 0x8u)>; + using IC2PSC = RegisterMask<TIM1_CCMR1_INPUT, (0x3u << 0xau)>; + using IC2F = RegisterMask<TIM1_CCMR1_INPUT, (0xfu << 0xcu)>; + }; + struct TIM1_CCMR1_OUTPUT : public MemRegister<uint32_t, 0x40012c18> { + using CC1S = RegisterMask<TIM1_CCMR1_OUTPUT, (0x3u << 0x0u)>; + using OC1FE = RegisterMask<TIM1_CCMR1_OUTPUT, (0x1u << 0x2u)>; + using OC1PE = RegisterMask<TIM1_CCMR1_OUTPUT, (0x1u << 0x3u)>; + using OC1M = RegisterMask<TIM1_CCMR1_OUTPUT, (0x7u << 0x4u)>; + using OC1CE = RegisterMask<TIM1_CCMR1_OUTPUT, (0x1u << 0x7u)>; + using CC2S = RegisterMask<TIM1_CCMR1_OUTPUT, (0x3u << 0x8u)>; + using OC2FE = RegisterMask<TIM1_CCMR1_OUTPUT, (0x1u << 0xau)>; + using OC2PE = RegisterMask<TIM1_CCMR1_OUTPUT, (0x1u << 0xbu)>; + using OC2M = RegisterMask<TIM1_CCMR1_OUTPUT, (0x7u << 0xcu)>; + using OC2CE = RegisterMask<TIM1_CCMR1_OUTPUT, (0x1u << 0xfu)>; + using OC1M_1 = RegisterMask<TIM1_CCMR1_OUTPUT, (0x1u << 0x10u)>; + using OC2M_1 = RegisterMask<TIM1_CCMR1_OUTPUT, (0x1u << 0x18u)>; + }; + struct TIM1_CCMR2_INPUT : public MemRegister<uint32_t, 0x40012c1c> { + using CC3S = RegisterMask<TIM1_CCMR2_INPUT, (0x3u << 0x0u)>; + using IC3PSC = RegisterMask<TIM1_CCMR2_INPUT, (0x3u << 0x2u)>; + using IC3F = RegisterMask<TIM1_CCMR2_INPUT, (0xfu << 0x4u)>; + using CC4S = RegisterMask<TIM1_CCMR2_INPUT, (0x3u << 0x8u)>; + using IC4PSC = RegisterMask<TIM1_CCMR2_INPUT, (0x3u << 0xau)>; + using IC4F = RegisterMask<TIM1_CCMR2_INPUT, (0xfu << 0xcu)>; + }; + struct TIM1_CCMR2_OUTPUT : public MemRegister<uint32_t, 0x40012c1c> { + using CC3S = RegisterMask<TIM1_CCMR2_OUTPUT, (0x3u << 0x0u)>; + using OC3FE = RegisterMask<TIM1_CCMR2_OUTPUT, (0x1u << 0x2u)>; + using OC3PE = RegisterMask<TIM1_CCMR2_OUTPUT, (0x1u << 0x3u)>; + using OC3M = RegisterMask<TIM1_CCMR2_OUTPUT, (0x7u << 0x4u)>; + using OC3CE = RegisterMask<TIM1_CCMR2_OUTPUT, (0x1u << 0x7u)>; + using CC4S = RegisterMask<TIM1_CCMR2_OUTPUT, (0x3u << 0x8u)>; + using OC4FE = RegisterMask<TIM1_CCMR2_OUTPUT, (0x1u << 0xau)>; + using OC4PE = RegisterMask<TIM1_CCMR2_OUTPUT, (0x1u << 0xbu)>; + using OC4M = RegisterMask<TIM1_CCMR2_OUTPUT, (0x7u << 0xcu)>; + using OC4CE = RegisterMask<TIM1_CCMR2_OUTPUT, (0x1u << 0xfu)>; + using OC3M_1 = RegisterMask<TIM1_CCMR2_OUTPUT, (0x1u << 0x10u)>; + using OC4M_1 = RegisterMask<TIM1_CCMR2_OUTPUT, (0x1u << 0x18u)>; + }; + struct TIM1_CCER : public MemRegister<uint32_t, 0x40012c20> { + using CC1E = RegisterMask<TIM1_CCER, (0x1u << 0x0u)>; + using CC1P = RegisterMask<TIM1_CCER, (0x1u << 0x1u)>; + using CC1NE = RegisterMask<TIM1_CCER, (0x1u << 0x2u)>; + using CC1NP = RegisterMask<TIM1_CCER, (0x1u << 0x3u)>; + using CC2E = RegisterMask<TIM1_CCER, (0x1u << 0x4u)>; + using CC2P = RegisterMask<TIM1_CCER, (0x1u << 0x5u)>; + using CC2NE = RegisterMask<TIM1_CCER, (0x1u << 0x6u)>; + using CC2NP = RegisterMask<TIM1_CCER, (0x1u << 0x7u)>; + using CC3E = RegisterMask<TIM1_CCER, (0x1u << 0x8u)>; + using CC3P = RegisterMask<TIM1_CCER, (0x1u << 0x9u)>; + using CC3NE = RegisterMask<TIM1_CCER, (0x1u << 0xau)>; + using CC3NP = RegisterMask<TIM1_CCER, (0x1u << 0xbu)>; + using CC4E = RegisterMask<TIM1_CCER, (0x1u << 0xcu)>; + using CC4P = RegisterMask<TIM1_CCER, (0x1u << 0xdu)>; + using CC4NP = RegisterMask<TIM1_CCER, (0x1u << 0xfu)>; + using CC5E = RegisterMask<TIM1_CCER, (0x1u << 0x10u)>; + using CC5P = RegisterMask<TIM1_CCER, (0x1u << 0x11u)>; + using CC6E = RegisterMask<TIM1_CCER, (0x1u << 0x14u)>; + using CC6P = RegisterMask<TIM1_CCER, (0x1u << 0x15u)>; + }; + struct TIM1_CNT : public MemRegister<uint32_t, 0x40012c24> { + using CNT = RegisterMask<TIM1_CNT, (0xffffu << 0x0u)>; + using UIFCPY = RegisterMask<TIM1_CNT, (0x1u << 0x1fu)>; + }; + struct TIM1_PSC : public MemRegister<uint16_t, 0x40012c28> { + using PSC = RegisterMask<TIM1_PSC, (0xffffu << 0x0u)>; + }; + struct TIM1_ARR : public MemRegister<uint16_t, 0x40012c2c> { + using ARR = RegisterMask<TIM1_ARR, (0xffffu << 0x0u)>; + }; + struct TIM1_RCR : public MemRegister<uint16_t, 0x40012c30> { + using REP = RegisterMask<TIM1_RCR, (0xffffu << 0x0u)>; + }; + struct TIM1_CCR1 : public MemRegister<uint16_t, 0x40012c34> { + using CCR1 = RegisterMask<TIM1_CCR1, (0xffffu << 0x0u)>; + }; + struct TIM1_CCR2 : public MemRegister<uint16_t, 0x40012c38> { + using CCR2 = RegisterMask<TIM1_CCR2, (0xffffu << 0x0u)>; + }; + struct TIM1_CCR3 : public MemRegister<uint16_t, 0x40012c3c> { + using CCR3 = RegisterMask<TIM1_CCR3, (0xffffu << 0x0u)>; + }; + struct TIM1_CCR4 : public MemRegister<uint16_t, 0x40012c40> { + using CCR4 = RegisterMask<TIM1_CCR4, (0xffffu << 0x0u)>; + }; + struct TIM1_BDTR : public MemRegister<uint32_t, 0x40012c44> { + using DTG = RegisterMask<TIM1_BDTR, (0xffu << 0x0u)>; + using LOCK = RegisterMask<TIM1_BDTR, (0x3u << 0x8u)>; + using OSSI = RegisterMask<TIM1_BDTR, (0x1u << 0xau)>; + using OSSR = RegisterMask<TIM1_BDTR, (0x1u << 0xbu)>; + using BKE = RegisterMask<TIM1_BDTR, (0x1u << 0xcu)>; + using BKP = RegisterMask<TIM1_BDTR, (0x1u << 0xdu)>; + using AOE = RegisterMask<TIM1_BDTR, (0x1u << 0xeu)>; + using MOE = RegisterMask<TIM1_BDTR, (0x1u << 0xfu)>; + using BKF = RegisterMask<TIM1_BDTR, (0xfu << 0x10u)>; + using BK2F = RegisterMask<TIM1_BDTR, (0xfu << 0x14u)>; + using BK2E = RegisterMask<TIM1_BDTR, (0x1u << 0x18u)>; + using BK2P = RegisterMask<TIM1_BDTR, (0x1u << 0x19u)>; + using BKDSRM = RegisterMask<TIM1_BDTR, (0x1u << 0x1au)>; + using BK2DSRM = RegisterMask<TIM1_BDTR, (0x1u << 0x1bu)>; + using BKBID = RegisterMask<TIM1_BDTR, (0x1u << 0x1cu)>; + using BK2BID = RegisterMask<TIM1_BDTR, (0x1u << 0x1du)>; + }; + struct TIM1_DCR : public MemRegister<uint16_t, 0x40012c48> { + using DBA = RegisterMask<TIM1_DCR, (0x1fu << 0x0u)>; + using DBL = RegisterMask<TIM1_DCR, (0x1fu << 0x8u)>; + }; + struct TIM1_DMAR : public MemRegister<uint32_t, 0x40012c4c> { + using DMAB = RegisterMask<TIM1_DMAR, (0x0u << 0x0u)>; + }; + struct TIM1_OR1 : public MemRegister<uint32_t, 0x40012c50> { + using OCREF_CLR = RegisterMask<TIM1_OR1, (0x3u << 0x0u)>; + }; + struct TIM1_CCMR3 : public MemRegister<uint32_t, 0x40012c54> { + using OC5FE = RegisterMask<TIM1_CCMR3, (0x1u << 0x2u)>; + using OC5PE = RegisterMask<TIM1_CCMR3, (0x1u << 0x3u)>; + using OC5M = RegisterMask<TIM1_CCMR3, (0x7u << 0x4u)>; + using OC5CE = RegisterMask<TIM1_CCMR3, (0x1u << 0x7u)>; + using OC6FE = RegisterMask<TIM1_CCMR3, (0x1u << 0xau)>; + using OC6PE = RegisterMask<TIM1_CCMR3, (0x1u << 0xbu)>; + using OC6M = RegisterMask<TIM1_CCMR3, (0x7u << 0xcu)>; + using OC6CE = RegisterMask<TIM1_CCMR3, (0x1u << 0xfu)>; + using OC5M_1 = RegisterMask<TIM1_CCMR3, (0x1u << 0x10u)>; + using OC6M_1 = RegisterMask<TIM1_CCMR3, (0x1u << 0x18u)>; + }; + struct TIM1_CCR5 : public MemRegister<uint32_t, 0x40012c58> { + using CCR5 = RegisterMask<TIM1_CCR5, (0xffffu << 0x0u)>; + using GC5C1 = RegisterMask<TIM1_CCR5, (0x1u << 0x1du)>; + using GC5C2 = RegisterMask<TIM1_CCR5, (0x1u << 0x1eu)>; + using GC5C3 = RegisterMask<TIM1_CCR5, (0x1u << 0x1fu)>; + }; + struct TIM1_CCR6 : public MemRegister<uint16_t, 0x40012c5c> { + using CCR6 = RegisterMask<TIM1_CCR6, (0xffffu << 0x0u)>; + }; + struct TIM1_AF1 : public MemRegister<uint32_t, 0x40012c60> { + using BKINE = RegisterMask<TIM1_AF1, (0x1u << 0x0u)>; + using BKCMP1E = RegisterMask<TIM1_AF1, (0x1u << 0x1u)>; + using BKCMP2E = RegisterMask<TIM1_AF1, (0x1u << 0x2u)>; + using BKINP = RegisterMask<TIM1_AF1, (0x1u << 0x9u)>; + using BKCMP1P = RegisterMask<TIM1_AF1, (0x1u << 0xau)>; + using BKCMP2P = RegisterMask<TIM1_AF1, (0x1u << 0xbu)>; + using ETRSEL = RegisterMask<TIM1_AF1, (0xfu << 0xeu)>; + }; + struct TIM1_AF2 : public MemRegister<uint32_t, 0x40012c64> { + using BK2INE = RegisterMask<TIM1_AF2, (0x1u << 0x0u)>; + using BK2CMP1E = RegisterMask<TIM1_AF2, (0x1u << 0x1u)>; + using BK2CMP2E = RegisterMask<TIM1_AF2, (0x1u << 0x2u)>; + using BK2INP = RegisterMask<TIM1_AF2, (0x1u << 0x9u)>; + using BK2CMP1P = RegisterMask<TIM1_AF2, (0x1u << 0xau)>; + using BK2CMP2P = RegisterMask<TIM1_AF2, (0x1u << 0xbu)>; + }; + struct TIM1_TISEL : public MemRegister<uint32_t, 0x40012c68> { + using TI1SEL = RegisterMask<TIM1_TISEL, (0xfu << 0x0u)>; + using TI2SEL = RegisterMask<TIM1_TISEL, (0xfu << 0x8u)>; + using TI3SEL = RegisterMask<TIM1_TISEL, (0xfu << 0x10u)>; + using TI4SEL = RegisterMask<TIM1_TISEL, (0xfu << 0x18u)>; + }; + using ALL = RegisterGroup<TIM1_CR1, TIM1_CR2, TIM1_SMCR, TIM1_DIER, TIM1_SR, TIM1_EGR, TIM1_CCMR1_INPUT, TIM1_CCMR1_OUTPUT, TIM1_CCMR2_INPUT, TIM1_CCMR2_OUTPUT, TIM1_CCER, TIM1_CNT, TIM1_PSC, TIM1_ARR, TIM1_RCR, TIM1_CCR1, TIM1_CCR2, TIM1_CCR3, TIM1_CCR4, TIM1_BDTR, TIM1_DCR, TIM1_DMAR, TIM1_OR1, TIM1_CCMR3, TIM1_CCR5, TIM1_CCR6, TIM1_AF1, TIM1_AF2, TIM1_TISEL>; + } + namespace TIM15 { + struct TIM15_CR1 : public MemRegister<uint16_t, 0x40014000> { + using CEN = RegisterMask<TIM15_CR1, (0x1u << 0x0u)>; + using UDIS = RegisterMask<TIM15_CR1, (0x1u << 0x1u)>; + using URS = RegisterMask<TIM15_CR1, (0x1u << 0x2u)>; + using OPM = RegisterMask<TIM15_CR1, (0x1u << 0x3u)>; + using ARPE = RegisterMask<TIM15_CR1, (0x1u << 0x7u)>; + using CKD = RegisterMask<TIM15_CR1, (0x3u << 0x8u)>; + using UIFREMAP = RegisterMask<TIM15_CR1, (0x1u << 0xbu)>; + }; + struct TIM15_CR2 : public MemRegister<uint16_t, 0x40014004> { + using CCPC = RegisterMask<TIM15_CR2, (0x1u << 0x0u)>; + using CCUS = RegisterMask<TIM15_CR2, (0x1u << 0x2u)>; + using CCDS = RegisterMask<TIM15_CR2, (0x1u << 0x3u)>; + using MMS = RegisterMask<TIM15_CR2, (0x7u << 0x4u)>; + using TI1S = RegisterMask<TIM15_CR2, (0x1u << 0x7u)>; + using OIS1 = RegisterMask<TIM15_CR2, (0x1u << 0x8u)>; + using OIS1N = RegisterMask<TIM15_CR2, (0x1u << 0x9u)>; + using OIS2 = RegisterMask<TIM15_CR2, (0x1u << 0xau)>; + }; + struct TIM15_SMCR : public MemRegister<uint32_t, 0x40014008> { + using SMS = RegisterMask<TIM15_SMCR, (0x7u << 0x0u)>; + using TS = RegisterMask<TIM15_SMCR, (0x7u << 0x4u)>; + using MSM = RegisterMask<TIM15_SMCR, (0x1u << 0x7u)>; + using SMS_1 = RegisterMask<TIM15_SMCR, (0x1u << 0x10u)>; + using TS_1 = RegisterMask<TIM15_SMCR, (0x3u << 0x14u)>; + }; + struct TIM15_DIER : public MemRegister<uint16_t, 0x4001400c> { + using UIE = RegisterMask<TIM15_DIER, (0x1u << 0x0u)>; + using CC1IE = RegisterMask<TIM15_DIER, (0x1u << 0x1u)>; + using CC2IE = RegisterMask<TIM15_DIER, (0x1u << 0x2u)>; + using COMIE = RegisterMask<TIM15_DIER, (0x1u << 0x5u)>; + using TIE = RegisterMask<TIM15_DIER, (0x1u << 0x6u)>; + using BIE = RegisterMask<TIM15_DIER, (0x1u << 0x7u)>; + using UDE = RegisterMask<TIM15_DIER, (0x1u << 0x8u)>; + using CC1DE = RegisterMask<TIM15_DIER, (0x1u << 0x9u)>; + using COMDE = RegisterMask<TIM15_DIER, (0x1u << 0xdu)>; + using TDE = RegisterMask<TIM15_DIER, (0x1u << 0xeu)>; + }; + struct TIM15_SR : public MemRegister<uint16_t, 0x40014010> { + using UIF = RegisterMask<TIM15_SR, (0x1u << 0x0u)>; + using CC1IF = RegisterMask<TIM15_SR, (0x1u << 0x1u)>; + using CC2IF = RegisterMask<TIM15_SR, (0x1u << 0x2u)>; + using COMIF = RegisterMask<TIM15_SR, (0x1u << 0x5u)>; + using TIF = RegisterMask<TIM15_SR, (0x1u << 0x6u)>; + using BIF = RegisterMask<TIM15_SR, (0x1u << 0x7u)>; + using CC1OF = RegisterMask<TIM15_SR, (0x1u << 0x9u)>; + using CC2OF = RegisterMask<TIM15_SR, (0x1u << 0xau)>; + }; + struct TIM15_EGR : public MemRegister<uint16_t, 0x40014014> { + using UG = RegisterMask<TIM15_EGR, (0x1u << 0x0u)>; + using CC1G = RegisterMask<TIM15_EGR, (0x1u << 0x1u)>; + using CC2G = RegisterMask<TIM15_EGR, (0x1u << 0x2u)>; + using COMG = RegisterMask<TIM15_EGR, (0x1u << 0x5u)>; + using TG = RegisterMask<TIM15_EGR, (0x1u << 0x6u)>; + using BG = RegisterMask<TIM15_EGR, (0x1u << 0x7u)>; + }; + struct TIM15_CCMR1 : public MemRegister<uint32_t, 0x40014018> { + using CC1S = RegisterMask<TIM15_CCMR1, (0x3u << 0x0u)>; + using IC1PSC = RegisterMask<TIM15_CCMR1, (0x3u << 0x2u)>; + using IC1F = RegisterMask<TIM15_CCMR1, (0xfu << 0x4u)>; + using CC2S = RegisterMask<TIM15_CCMR1, (0x3u << 0x8u)>; + using IC2PSC = RegisterMask<TIM15_CCMR1, (0x3u << 0xau)>; + using IC2F = RegisterMask<TIM15_CCMR1, (0xfu << 0xcu)>; + }; + struct TIM15_CCMR1_ALTERNATE1 : public MemRegister<uint32_t, 0x40014018> { + using CC1S = RegisterMask<TIM15_CCMR1_ALTERNATE1, (0x3u << 0x0u)>; + using OC1FE = RegisterMask<TIM15_CCMR1_ALTERNATE1, (0x1u << 0x2u)>; + using OC1PE = RegisterMask<TIM15_CCMR1_ALTERNATE1, (0x1u << 0x3u)>; + using OC1M = RegisterMask<TIM15_CCMR1_ALTERNATE1, (0x7u << 0x4u)>; + using CC2S = RegisterMask<TIM15_CCMR1_ALTERNATE1, (0x3u << 0x8u)>; + using OC2FE = RegisterMask<TIM15_CCMR1_ALTERNATE1, (0x1u << 0xau)>; + using OC2PE = RegisterMask<TIM15_CCMR1_ALTERNATE1, (0x1u << 0xbu)>; + using OC2M = RegisterMask<TIM15_CCMR1_ALTERNATE1, (0x7u << 0xcu)>; + using OC1M_1 = RegisterMask<TIM15_CCMR1_ALTERNATE1, (0x1u << 0x10u)>; + using OC2M_1 = RegisterMask<TIM15_CCMR1_ALTERNATE1, (0x1u << 0x18u)>; + }; + struct TIM15_CCER : public MemRegister<uint16_t, 0x40014020> { + using CC1E = RegisterMask<TIM15_CCER, (0x1u << 0x0u)>; + using CC1P = RegisterMask<TIM15_CCER, (0x1u << 0x1u)>; + using CC1NE = RegisterMask<TIM15_CCER, (0x1u << 0x2u)>; + using CC1NP = RegisterMask<TIM15_CCER, (0x1u << 0x3u)>; + using CC2E = RegisterMask<TIM15_CCER, (0x1u << 0x4u)>; + using CC2P = RegisterMask<TIM15_CCER, (0x1u << 0x5u)>; + using CC2NP = RegisterMask<TIM15_CCER, (0x1u << 0x7u)>; + }; + struct TIM15_CNT : public MemRegister<uint32_t, 0x40014024> { + using CNT = RegisterMask<TIM15_CNT, (0xffffu << 0x0u)>; + using UIFCPY = RegisterMask<TIM15_CNT, (0x1u << 0x1fu)>; + }; + struct TIM15_PSC : public MemRegister<uint16_t, 0x40014028> { + using PSC = RegisterMask<TIM15_PSC, (0xffffu << 0x0u)>; + }; + struct TIM15_ARR : public MemRegister<uint16_t, 0x4001402c> { + using ARR = RegisterMask<TIM15_ARR, (0xffffu << 0x0u)>; + }; + struct TIM15_RCR : public MemRegister<uint16_t, 0x40014030> { + using REP = RegisterMask<TIM15_RCR, (0xffu << 0x0u)>; + }; + struct TIM15_CCR1 : public MemRegister<uint16_t, 0x40014034> { + using CCR1 = RegisterMask<TIM15_CCR1, (0xffffu << 0x0u)>; + }; + struct TIM15_CCR2 : public MemRegister<uint16_t, 0x40014038> { + using CCR2 = RegisterMask<TIM15_CCR2, (0xffffu << 0x0u)>; + }; + struct TIM15_BDTR : public MemRegister<uint32_t, 0x40014044> { + using DTG = RegisterMask<TIM15_BDTR, (0xffu << 0x0u)>; + using LOCK = RegisterMask<TIM15_BDTR, (0x3u << 0x8u)>; + using OSSI = RegisterMask<TIM15_BDTR, (0x1u << 0xau)>; + using OSSR = RegisterMask<TIM15_BDTR, (0x1u << 0xbu)>; + using BKE = RegisterMask<TIM15_BDTR, (0x1u << 0xcu)>; + using BKP = RegisterMask<TIM15_BDTR, (0x1u << 0xdu)>; + using AOE = RegisterMask<TIM15_BDTR, (0x1u << 0xeu)>; + using MOE = RegisterMask<TIM15_BDTR, (0x1u << 0xfu)>; + using BKF = RegisterMask<TIM15_BDTR, (0xfu << 0x10u)>; + using BKDSRM = RegisterMask<TIM15_BDTR, (0x1u << 0x1au)>; + using BKBID = RegisterMask<TIM15_BDTR, (0x1u << 0x1cu)>; + }; + struct TIM15_DCR : public MemRegister<uint16_t, 0x40014048> { + using DBA = RegisterMask<TIM15_DCR, (0x1fu << 0x0u)>; + using DBL = RegisterMask<TIM15_DCR, (0x1fu << 0x8u)>; + }; + struct TIM15_DMAR : public MemRegister<uint16_t, 0x4001404c> { + using DMAB = RegisterMask<TIM15_DMAR, (0xffffu << 0x0u)>; + }; + struct TIM15_AF1 : public MemRegister<uint32_t, 0x40014060> { + using BKINE = RegisterMask<TIM15_AF1, (0x1u << 0x0u)>; + using BKCMP1E = RegisterMask<TIM15_AF1, (0x1u << 0x1u)>; + using BKCMP2E = RegisterMask<TIM15_AF1, (0x1u << 0x2u)>; + using BKINP = RegisterMask<TIM15_AF1, (0x1u << 0x9u)>; + using BKCMP1P = RegisterMask<TIM15_AF1, (0x1u << 0xau)>; + using BKCMP2P = RegisterMask<TIM15_AF1, (0x1u << 0xbu)>; + }; + struct TIM15_TISEL : public MemRegister<uint32_t, 0x40014068> { + using TI1SEL = RegisterMask<TIM15_TISEL, (0xfu << 0x0u)>; + using TI2SEL = RegisterMask<TIM15_TISEL, (0xfu << 0x8u)>; + }; + using ALL = RegisterGroup<TIM15_CR1, TIM15_CR2, TIM15_SMCR, TIM15_DIER, TIM15_SR, TIM15_EGR, TIM15_CCMR1, TIM15_CCMR1_ALTERNATE1, TIM15_CCER, TIM15_CNT, TIM15_PSC, TIM15_ARR, TIM15_RCR, TIM15_CCR1, TIM15_CCR2, TIM15_BDTR, TIM15_DCR, TIM15_DMAR, TIM15_AF1, TIM15_TISEL>; + } + namespace TIM16 { + struct TIM16_CR1 : public MemRegister<uint16_t, 0x40014400> { + using CEN = RegisterMask<TIM16_CR1, (0x1u << 0x0u)>; + using UDIS = RegisterMask<TIM16_CR1, (0x1u << 0x1u)>; + using URS = RegisterMask<TIM16_CR1, (0x1u << 0x2u)>; + using OPM = RegisterMask<TIM16_CR1, (0x1u << 0x3u)>; + using ARPE = RegisterMask<TIM16_CR1, (0x1u << 0x7u)>; + using CKD = RegisterMask<TIM16_CR1, (0x3u << 0x8u)>; + using UIFREMAP = RegisterMask<TIM16_CR1, (0x1u << 0xbu)>; + }; + struct TIM16_CR2 : public MemRegister<uint16_t, 0x40014404> { + using CCPC = RegisterMask<TIM16_CR2, (0x1u << 0x0u)>; + using CCUS = RegisterMask<TIM16_CR2, (0x1u << 0x2u)>; + using CCDS = RegisterMask<TIM16_CR2, (0x1u << 0x3u)>; + using OIS1 = RegisterMask<TIM16_CR2, (0x1u << 0x8u)>; + using OIS1N = RegisterMask<TIM16_CR2, (0x1u << 0x9u)>; + }; + struct TIM16_DIER : public MemRegister<uint16_t, 0x4001440c> { + using UIE = RegisterMask<TIM16_DIER, (0x1u << 0x0u)>; + using CC1IE = RegisterMask<TIM16_DIER, (0x1u << 0x1u)>; + using COMIE = RegisterMask<TIM16_DIER, (0x1u << 0x5u)>; + using BIE = RegisterMask<TIM16_DIER, (0x1u << 0x7u)>; + using UDE = RegisterMask<TIM16_DIER, (0x1u << 0x8u)>; + using CC1DE = RegisterMask<TIM16_DIER, (0x1u << 0x9u)>; + }; + struct TIM16_SR : public MemRegister<uint16_t, 0x40014410> { + using UIF = RegisterMask<TIM16_SR, (0x1u << 0x0u)>; + using CC1IF = RegisterMask<TIM16_SR, (0x1u << 0x1u)>; + using COMIF = RegisterMask<TIM16_SR, (0x1u << 0x5u)>; + using BIF = RegisterMask<TIM16_SR, (0x1u << 0x7u)>; + using CC1OF = RegisterMask<TIM16_SR, (0x1u << 0x9u)>; + }; + struct TIM16_EGR : public MemRegister<uint16_t, 0x40014414> { + using UG = RegisterMask<TIM16_EGR, (0x1u << 0x0u)>; + using CC1G = RegisterMask<TIM16_EGR, (0x1u << 0x1u)>; + using COMG = RegisterMask<TIM16_EGR, (0x1u << 0x5u)>; + using BG = RegisterMask<TIM16_EGR, (0x1u << 0x7u)>; + }; + struct TIM16_CCMR1 : public MemRegister<uint32_t, 0x40014418> { + using CC1S = RegisterMask<TIM16_CCMR1, (0x3u << 0x0u)>; + using IC1PSC = RegisterMask<TIM16_CCMR1, (0x3u << 0x2u)>; + using IC1F = RegisterMask<TIM16_CCMR1, (0xfu << 0x4u)>; + }; + struct TIM16_CCMR1_ALTERNATE1 : public MemRegister<uint32_t, 0x40014418> { + using CC1S = RegisterMask<TIM16_CCMR1_ALTERNATE1, (0x3u << 0x0u)>; + using OC1FE = RegisterMask<TIM16_CCMR1_ALTERNATE1, (0x1u << 0x2u)>; + using OC1PE = RegisterMask<TIM16_CCMR1_ALTERNATE1, (0x1u << 0x3u)>; + using OC1M = RegisterMask<TIM16_CCMR1_ALTERNATE1, (0x7u << 0x4u)>; + using OC1M_1 = RegisterMask<TIM16_CCMR1_ALTERNATE1, (0x1u << 0x10u)>; + }; + struct TIM16_CCER : public MemRegister<uint16_t, 0x40014420> { + using CC1E = RegisterMask<TIM16_CCER, (0x1u << 0x0u)>; + using CC1P = RegisterMask<TIM16_CCER, (0x1u << 0x1u)>; + using CC1NE = RegisterMask<TIM16_CCER, (0x1u << 0x2u)>; + using CC1NP = RegisterMask<TIM16_CCER, (0x1u << 0x3u)>; + }; + struct TIM16_CNT : public MemRegister<uint32_t, 0x40014424> { + using CNT = RegisterMask<TIM16_CNT, (0xffffu << 0x0u)>; + using UIFCPY = RegisterMask<TIM16_CNT, (0x1u << 0x1fu)>; + }; + struct TIM16_PSC : public MemRegister<uint16_t, 0x40014428> { + using PSC = RegisterMask<TIM16_PSC, (0xffffu << 0x0u)>; + }; + struct TIM16_ARR : public MemRegister<uint16_t, 0x4001442c> { + using ARR = RegisterMask<TIM16_ARR, (0xffffu << 0x0u)>; + }; + struct TIM16_RCR : public MemRegister<uint16_t, 0x40014430> { + using REP = RegisterMask<TIM16_RCR, (0xffu << 0x0u)>; + }; + struct TIM16_CCR1 : public MemRegister<uint16_t, 0x40014434> { + using CCR1 = RegisterMask<TIM16_CCR1, (0xffffu << 0x0u)>; + }; + struct TIM16_BDTR : public MemRegister<uint32_t, 0x40014444> { + using DTG = RegisterMask<TIM16_BDTR, (0xffu << 0x0u)>; + using LOCK = RegisterMask<TIM16_BDTR, (0x3u << 0x8u)>; + using OSSI = RegisterMask<TIM16_BDTR, (0x1u << 0xau)>; + using OSSR = RegisterMask<TIM16_BDTR, (0x1u << 0xbu)>; + using BKE = RegisterMask<TIM16_BDTR, (0x1u << 0xcu)>; + using BKP = RegisterMask<TIM16_BDTR, (0x1u << 0xdu)>; + using AOE = RegisterMask<TIM16_BDTR, (0x1u << 0xeu)>; + using MOE = RegisterMask<TIM16_BDTR, (0x1u << 0xfu)>; + using BKF = RegisterMask<TIM16_BDTR, (0xfu << 0x10u)>; + using BKDSRM = RegisterMask<TIM16_BDTR, (0x1u << 0x1au)>; + using BKBID = RegisterMask<TIM16_BDTR, (0x1u << 0x1cu)>; + }; + struct TIM16_DCR : public MemRegister<uint16_t, 0x40014448> { + using DBA = RegisterMask<TIM16_DCR, (0x1fu << 0x0u)>; + using DBL = RegisterMask<TIM16_DCR, (0x1fu << 0x8u)>; + }; + struct TIM16_DMAR : public MemRegister<uint16_t, 0x4001444c> { + using DMAB = RegisterMask<TIM16_DMAR, (0xffffu << 0x0u)>; + }; + struct TIM16_AF1 : public MemRegister<uint32_t, 0x40014460> { + using BKINE = RegisterMask<TIM16_AF1, (0x1u << 0x0u)>; + using BKCMP1E = RegisterMask<TIM16_AF1, (0x1u << 0x1u)>; + using BKCMP2E = RegisterMask<TIM16_AF1, (0x1u << 0x2u)>; + using BKINP = RegisterMask<TIM16_AF1, (0x1u << 0x9u)>; + using BKCMP1P = RegisterMask<TIM16_AF1, (0x1u << 0xau)>; + using BKCMP2P = RegisterMask<TIM16_AF1, (0x1u << 0xbu)>; + }; + struct TIM16_TISEL : public MemRegister<uint32_t, 0x40014468> { + using TI1SEL = RegisterMask<TIM16_TISEL, (0xfu << 0x0u)>; + }; + using ALL = RegisterGroup<TIM16_CR1, TIM16_CR2, TIM16_DIER, TIM16_SR, TIM16_EGR, TIM16_CCMR1, TIM16_CCMR1_ALTERNATE1, TIM16_CCER, TIM16_CNT, TIM16_PSC, TIM16_ARR, TIM16_RCR, TIM16_CCR1, TIM16_BDTR, TIM16_DCR, TIM16_DMAR, TIM16_AF1, TIM16_TISEL>; + } + namespace TIM2 { + struct TIM2_CR1 : public MemRegister<uint16_t, 0x40000000> { + using CEN = RegisterMask<TIM2_CR1, (0x1u << 0x0u)>; + using UDIS = RegisterMask<TIM2_CR1, (0x1u << 0x1u)>; + using URS = RegisterMask<TIM2_CR1, (0x1u << 0x2u)>; + using OPM = RegisterMask<TIM2_CR1, (0x1u << 0x3u)>; + using DIR = RegisterMask<TIM2_CR1, (0x1u << 0x4u)>; + using CMS = RegisterMask<TIM2_CR1, (0x3u << 0x5u)>; + using ARPE = RegisterMask<TIM2_CR1, (0x1u << 0x7u)>; + using CKD = RegisterMask<TIM2_CR1, (0x3u << 0x8u)>; + using UIFREMAP = RegisterMask<TIM2_CR1, (0x1u << 0xbu)>; + }; + struct TIM2_CR2 : public MemRegister<uint16_t, 0x40000004> { + using CCDS = RegisterMask<TIM2_CR2, (0x1u << 0x3u)>; + using MMS = RegisterMask<TIM2_CR2, (0x7u << 0x4u)>; + using TI1S = RegisterMask<TIM2_CR2, (0x1u << 0x7u)>; + }; + struct TIM2_SMCR : public MemRegister<uint32_t, 0x40000008> { + using SMS = RegisterMask<TIM2_SMCR, (0x7u << 0x0u)>; + using OCCS = RegisterMask<TIM2_SMCR, (0x1u << 0x3u)>; + using TS = RegisterMask<TIM2_SMCR, (0x7u << 0x4u)>; + using MSM = RegisterMask<TIM2_SMCR, (0x1u << 0x7u)>; + using ETF = RegisterMask<TIM2_SMCR, (0xfu << 0x8u)>; + using ETPS = RegisterMask<TIM2_SMCR, (0x3u << 0xcu)>; + using ECE = RegisterMask<TIM2_SMCR, (0x1u << 0xeu)>; + using ETP = RegisterMask<TIM2_SMCR, (0x1u << 0xfu)>; + using SMS_1 = RegisterMask<TIM2_SMCR, (0x1u << 0x10u)>; + using TS_1 = RegisterMask<TIM2_SMCR, (0x3u << 0x14u)>; + }; + struct TIM2_DIER : public MemRegister<uint16_t, 0x4000000c> { + using UIE = RegisterMask<TIM2_DIER, (0x1u << 0x0u)>; + using CC1IE = RegisterMask<TIM2_DIER, (0x1u << 0x1u)>; + using CC2IE = RegisterMask<TIM2_DIER, (0x1u << 0x2u)>; + using CC3IE = RegisterMask<TIM2_DIER, (0x1u << 0x3u)>; + using CC4IE = RegisterMask<TIM2_DIER, (0x1u << 0x4u)>; + using TIE = RegisterMask<TIM2_DIER, (0x1u << 0x6u)>; + using UDE = RegisterMask<TIM2_DIER, (0x1u << 0x8u)>; + using CC1DE = RegisterMask<TIM2_DIER, (0x1u << 0x9u)>; + using CC2DE = RegisterMask<TIM2_DIER, (0x1u << 0xau)>; + using CC3DE = RegisterMask<TIM2_DIER, (0x1u << 0xbu)>; + using CC4DE = RegisterMask<TIM2_DIER, (0x1u << 0xcu)>; + using TDE = RegisterMask<TIM2_DIER, (0x1u << 0xeu)>; + }; + struct TIM2_SR : public MemRegister<uint16_t, 0x40000010> { + using UIF = RegisterMask<TIM2_SR, (0x1u << 0x0u)>; + using CC1IF = RegisterMask<TIM2_SR, (0x1u << 0x1u)>; + using CC2IF = RegisterMask<TIM2_SR, (0x1u << 0x2u)>; + using CC3IF = RegisterMask<TIM2_SR, (0x1u << 0x3u)>; + using CC4IF = RegisterMask<TIM2_SR, (0x1u << 0x4u)>; + using TIF = RegisterMask<TIM2_SR, (0x1u << 0x6u)>; + using CC1OF = RegisterMask<TIM2_SR, (0x1u << 0x9u)>; + using CC2OF = RegisterMask<TIM2_SR, (0x1u << 0xau)>; + using CC3OF = RegisterMask<TIM2_SR, (0x1u << 0xbu)>; + using CC4OF = RegisterMask<TIM2_SR, (0x1u << 0xcu)>; + }; + struct TIM2_EGR : public MemRegister<uint16_t, 0x40000014> { + using UG = RegisterMask<TIM2_EGR, (0x1u << 0x0u)>; + using CC1G = RegisterMask<TIM2_EGR, (0x1u << 0x1u)>; + using CC2G = RegisterMask<TIM2_EGR, (0x1u << 0x2u)>; + using CC3G = RegisterMask<TIM2_EGR, (0x1u << 0x3u)>; + using CC4G = RegisterMask<TIM2_EGR, (0x1u << 0x4u)>; + using TG = RegisterMask<TIM2_EGR, (0x1u << 0x6u)>; + }; + struct TIM2_CCMR1 : public MemRegister<uint32_t, 0x40000018> { + using CC1S = RegisterMask<TIM2_CCMR1, (0x3u << 0x0u)>; + using IC1PSC = RegisterMask<TIM2_CCMR1, (0x3u << 0x2u)>; + using IC1F = RegisterMask<TIM2_CCMR1, (0xfu << 0x4u)>; + using CC2S = RegisterMask<TIM2_CCMR1, (0x3u << 0x8u)>; + using IC2PSC = RegisterMask<TIM2_CCMR1, (0x3u << 0xau)>; + using IC2F = RegisterMask<TIM2_CCMR1, (0xfu << 0xcu)>; + }; + struct TIM2_CCMR1_ALTERNATE1 : public MemRegister<uint32_t, 0x40000018> { + using CC1S = RegisterMask<TIM2_CCMR1_ALTERNATE1, (0x3u << 0x0u)>; + using OC1FE = RegisterMask<TIM2_CCMR1_ALTERNATE1, (0x1u << 0x2u)>; + using OC1PE = RegisterMask<TIM2_CCMR1_ALTERNATE1, (0x1u << 0x3u)>; + using OC1M = RegisterMask<TIM2_CCMR1_ALTERNATE1, (0x7u << 0x4u)>; + using OC1CE = RegisterMask<TIM2_CCMR1_ALTERNATE1, (0x1u << 0x7u)>; + using CC2S = RegisterMask<TIM2_CCMR1_ALTERNATE1, (0x3u << 0x8u)>; + using OC2FE = RegisterMask<TIM2_CCMR1_ALTERNATE1, (0x1u << 0xau)>; + using OC2PE = RegisterMask<TIM2_CCMR1_ALTERNATE1, (0x1u << 0xbu)>; + using OC2M = RegisterMask<TIM2_CCMR1_ALTERNATE1, (0x7u << 0xcu)>; + using OC2CE = RegisterMask<TIM2_CCMR1_ALTERNATE1, (0x1u << 0xfu)>; + using OC1M_1 = RegisterMask<TIM2_CCMR1_ALTERNATE1, (0x1u << 0x10u)>; + using OC2M_1 = RegisterMask<TIM2_CCMR1_ALTERNATE1, (0x1u << 0x18u)>; + }; + struct TIM2_CCMR2 : public MemRegister<uint32_t, 0x4000001c> { + using CC3S = RegisterMask<TIM2_CCMR2, (0x3u << 0x0u)>; + using IC3PSC = RegisterMask<TIM2_CCMR2, (0x3u << 0x2u)>; + using IC3F = RegisterMask<TIM2_CCMR2, (0xfu << 0x4u)>; + using CC4S = RegisterMask<TIM2_CCMR2, (0x3u << 0x8u)>; + using IC4PSC = RegisterMask<TIM2_CCMR2, (0x3u << 0xau)>; + using IC4F = RegisterMask<TIM2_CCMR2, (0xfu << 0xcu)>; + }; + struct TIM2_CCMR2_ALTERNATE1 : public MemRegister<uint32_t, 0x4000001c> { + using CC3S = RegisterMask<TIM2_CCMR2_ALTERNATE1, (0x3u << 0x0u)>; + using OC3FE = RegisterMask<TIM2_CCMR2_ALTERNATE1, (0x1u << 0x2u)>; + using OC3PE = RegisterMask<TIM2_CCMR2_ALTERNATE1, (0x1u << 0x3u)>; + using OC3M = RegisterMask<TIM2_CCMR2_ALTERNATE1, (0x7u << 0x4u)>; + using OC3CE = RegisterMask<TIM2_CCMR2_ALTERNATE1, (0x1u << 0x7u)>; + using CC4S = RegisterMask<TIM2_CCMR2_ALTERNATE1, (0x3u << 0x8u)>; + using OC4FE = RegisterMask<TIM2_CCMR2_ALTERNATE1, (0x1u << 0xau)>; + using OC4PE = RegisterMask<TIM2_CCMR2_ALTERNATE1, (0x1u << 0xbu)>; + using OC4M = RegisterMask<TIM2_CCMR2_ALTERNATE1, (0x7u << 0xcu)>; + using OC4CE = RegisterMask<TIM2_CCMR2_ALTERNATE1, (0x1u << 0xfu)>; + using OC3M_1 = RegisterMask<TIM2_CCMR2_ALTERNATE1, (0x1u << 0x10u)>; + using OC4M_1 = RegisterMask<TIM2_CCMR2_ALTERNATE1, (0x1u << 0x18u)>; + }; + struct TIM2_CCER : public MemRegister<uint16_t, 0x40000020> { + using CC1E = RegisterMask<TIM2_CCER, (0x1u << 0x0u)>; + using CC1P = RegisterMask<TIM2_CCER, (0x1u << 0x1u)>; + using CC1NP = RegisterMask<TIM2_CCER, (0x1u << 0x3u)>; + using CC2E = RegisterMask<TIM2_CCER, (0x1u << 0x4u)>; + using CC2P = RegisterMask<TIM2_CCER, (0x1u << 0x5u)>; + using CC2NP = RegisterMask<TIM2_CCER, (0x1u << 0x7u)>; + using CC3E = RegisterMask<TIM2_CCER, (0x1u << 0x8u)>; + using CC3P = RegisterMask<TIM2_CCER, (0x1u << 0x9u)>; + using CC3NP = RegisterMask<TIM2_CCER, (0x1u << 0xbu)>; + using CC4E = RegisterMask<TIM2_CCER, (0x1u << 0xcu)>; + using CC4P = RegisterMask<TIM2_CCER, (0x1u << 0xdu)>; + using CC4NP = RegisterMask<TIM2_CCER, (0x1u << 0xfu)>; + }; + struct TIM2_CNT : public MemRegister<uint32_t, 0x40000024> { + using CNT = RegisterMask<TIM2_CNT, (0x0u << 0x0u)>; + }; + struct TIM2_CNT_ALTERNATE1 : public MemRegister<uint32_t, 0x40000024> { + using CNT = RegisterMask<TIM2_CNT_ALTERNATE1, (0x7fffffffu << 0x0u)>; + using UIFCPY = RegisterMask<TIM2_CNT_ALTERNATE1, (0x1u << 0x1fu)>; + }; + struct TIM2_PSC : public MemRegister<uint16_t, 0x40000028> { + using PSC = RegisterMask<TIM2_PSC, (0xffffu << 0x0u)>; + }; + struct TIM2_ARR : public MemRegister<uint32_t, 0x4000002c> { + using ARR = RegisterMask<TIM2_ARR, (0x0u << 0x0u)>; + }; + struct TIM2_CCR1 : public MemRegister<uint32_t, 0x40000034> { + using CCR1 = RegisterMask<TIM2_CCR1, (0x0u << 0x0u)>; + }; + struct TIM2_CCR2 : public MemRegister<uint32_t, 0x40000038> { + using CCR2 = RegisterMask<TIM2_CCR2, (0x0u << 0x0u)>; + }; + struct TIM2_CCR3 : public MemRegister<uint32_t, 0x4000003c> { + using CCR3 = RegisterMask<TIM2_CCR3, (0x0u << 0x0u)>; + }; + struct TIM2_CCR4 : public MemRegister<uint32_t, 0x40000040> { + using CCR4 = RegisterMask<TIM2_CCR4, (0x0u << 0x0u)>; + }; + struct TIM2_DCR : public MemRegister<uint16_t, 0x40000048> { + using DBA = RegisterMask<TIM2_DCR, (0x1fu << 0x0u)>; + using DBL = RegisterMask<TIM2_DCR, (0x1fu << 0x8u)>; + }; + struct TIM2_DMAR : public MemRegister<uint16_t, 0x4000004c> { + using DMAB = RegisterMask<TIM2_DMAR, (0xffffu << 0x0u)>; + }; + struct TIM2_OR1 : public MemRegister<uint32_t, 0x40000050> { + using OCREF_CLR = RegisterMask<TIM2_OR1, (0x3u << 0x0u)>; + }; + struct TIM2_AF1 : public MemRegister<uint32_t, 0x40000060> { + using ETRSEL = RegisterMask<TIM2_AF1, (0xfu << 0xeu)>; + }; + struct TIM2_TISEL : public MemRegister<uint32_t, 0x40000068> { + using TI1SEL = RegisterMask<TIM2_TISEL, (0xfu << 0x0u)>; + using TI2SEL = RegisterMask<TIM2_TISEL, (0xfu << 0x8u)>; + using TI3SEL = RegisterMask<TIM2_TISEL, (0xfu << 0x10u)>; + }; + using ALL = RegisterGroup<TIM2_CR1, TIM2_CR2, TIM2_SMCR, TIM2_DIER, TIM2_SR, TIM2_EGR, TIM2_CCMR1, TIM2_CCMR1_ALTERNATE1, TIM2_CCMR2, TIM2_CCMR2_ALTERNATE1, TIM2_CCER, TIM2_CNT, TIM2_CNT_ALTERNATE1, TIM2_PSC, TIM2_ARR, TIM2_CCR1, TIM2_CCR2, TIM2_CCR3, TIM2_CCR4, TIM2_DCR, TIM2_DMAR, TIM2_OR1, TIM2_AF1, TIM2_TISEL>; + } + namespace TIM3 { + struct TIM3_CR1 : public MemRegister<uint16_t, 0x40000400> { + using CEN = RegisterMask<TIM3_CR1, (0x1u << 0x0u)>; + using UDIS = RegisterMask<TIM3_CR1, (0x1u << 0x1u)>; + using URS = RegisterMask<TIM3_CR1, (0x1u << 0x2u)>; + using OPM = RegisterMask<TIM3_CR1, (0x1u << 0x3u)>; + using DIR = RegisterMask<TIM3_CR1, (0x1u << 0x4u)>; + using CMS = RegisterMask<TIM3_CR1, (0x3u << 0x5u)>; + using ARPE = RegisterMask<TIM3_CR1, (0x1u << 0x7u)>; + using CKD = RegisterMask<TIM3_CR1, (0x3u << 0x8u)>; + using UIFREMAP = RegisterMask<TIM3_CR1, (0x1u << 0xbu)>; + }; + struct TIM3_CR2 : public MemRegister<uint16_t, 0x40000404> { + using CCDS = RegisterMask<TIM3_CR2, (0x1u << 0x3u)>; + using MMS = RegisterMask<TIM3_CR2, (0x7u << 0x4u)>; + using TI1S = RegisterMask<TIM3_CR2, (0x1u << 0x7u)>; + }; + struct TIM3_SMCR : public MemRegister<uint32_t, 0x40000408> { + using SMS = RegisterMask<TIM3_SMCR, (0x7u << 0x0u)>; + using OCCS = RegisterMask<TIM3_SMCR, (0x1u << 0x3u)>; + using TS = RegisterMask<TIM3_SMCR, (0x7u << 0x4u)>; + using MSM = RegisterMask<TIM3_SMCR, (0x1u << 0x7u)>; + using ETF = RegisterMask<TIM3_SMCR, (0xfu << 0x8u)>; + using ETPS = RegisterMask<TIM3_SMCR, (0x3u << 0xcu)>; + using ECE = RegisterMask<TIM3_SMCR, (0x1u << 0xeu)>; + using ETP = RegisterMask<TIM3_SMCR, (0x1u << 0xfu)>; + using SMS_1 = RegisterMask<TIM3_SMCR, (0x1u << 0x10u)>; + using TS_1 = RegisterMask<TIM3_SMCR, (0x3u << 0x14u)>; + }; + struct TIM3_DIER : public MemRegister<uint16_t, 0x4000040c> { + using UIE = RegisterMask<TIM3_DIER, (0x1u << 0x0u)>; + using CC1IE = RegisterMask<TIM3_DIER, (0x1u << 0x1u)>; + using CC2IE = RegisterMask<TIM3_DIER, (0x1u << 0x2u)>; + using CC3IE = RegisterMask<TIM3_DIER, (0x1u << 0x3u)>; + using CC4IE = RegisterMask<TIM3_DIER, (0x1u << 0x4u)>; + using TIE = RegisterMask<TIM3_DIER, (0x1u << 0x6u)>; + using UDE = RegisterMask<TIM3_DIER, (0x1u << 0x8u)>; + using CC1DE = RegisterMask<TIM3_DIER, (0x1u << 0x9u)>; + using CC2DE = RegisterMask<TIM3_DIER, (0x1u << 0xau)>; + using CC3DE = RegisterMask<TIM3_DIER, (0x1u << 0xbu)>; + using CC4DE = RegisterMask<TIM3_DIER, (0x1u << 0xcu)>; + using TDE = RegisterMask<TIM3_DIER, (0x1u << 0xeu)>; + }; + struct TIM3_SR : public MemRegister<uint16_t, 0x40000410> { + using UIF = RegisterMask<TIM3_SR, (0x1u << 0x0u)>; + using CC1IF = RegisterMask<TIM3_SR, (0x1u << 0x1u)>; + using CC2IF = RegisterMask<TIM3_SR, (0x1u << 0x2u)>; + using CC3IF = RegisterMask<TIM3_SR, (0x1u << 0x3u)>; + using CC4IF = RegisterMask<TIM3_SR, (0x1u << 0x4u)>; + using TIF = RegisterMask<TIM3_SR, (0x1u << 0x6u)>; + using CC1OF = RegisterMask<TIM3_SR, (0x1u << 0x9u)>; + using CC2OF = RegisterMask<TIM3_SR, (0x1u << 0xau)>; + using CC3OF = RegisterMask<TIM3_SR, (0x1u << 0xbu)>; + using CC4OF = RegisterMask<TIM3_SR, (0x1u << 0xcu)>; + }; + struct TIM3_EGR : public MemRegister<uint16_t, 0x40000414> { + using UG = RegisterMask<TIM3_EGR, (0x1u << 0x0u)>; + using CC1G = RegisterMask<TIM3_EGR, (0x1u << 0x1u)>; + using CC2G = RegisterMask<TIM3_EGR, (0x1u << 0x2u)>; + using CC3G = RegisterMask<TIM3_EGR, (0x1u << 0x3u)>; + using CC4G = RegisterMask<TIM3_EGR, (0x1u << 0x4u)>; + using TG = RegisterMask<TIM3_EGR, (0x1u << 0x6u)>; + }; + struct TIM3_CCMR1 : public MemRegister<uint32_t, 0x40000418> { + using CC1S = RegisterMask<TIM3_CCMR1, (0x3u << 0x0u)>; + using IC1PSC = RegisterMask<TIM3_CCMR1, (0x3u << 0x2u)>; + using IC1F = RegisterMask<TIM3_CCMR1, (0xfu << 0x4u)>; + using CC2S = RegisterMask<TIM3_CCMR1, (0x3u << 0x8u)>; + using IC2PSC = RegisterMask<TIM3_CCMR1, (0x3u << 0xau)>; + using IC2F = RegisterMask<TIM3_CCMR1, (0xfu << 0xcu)>; + }; + struct TIM3_CCMR1_ALTERNATE1 : public MemRegister<uint32_t, 0x40000418> { + using CC1S = RegisterMask<TIM3_CCMR1_ALTERNATE1, (0x3u << 0x0u)>; + using OC1FE = RegisterMask<TIM3_CCMR1_ALTERNATE1, (0x1u << 0x2u)>; + using OC1PE = RegisterMask<TIM3_CCMR1_ALTERNATE1, (0x1u << 0x3u)>; + using OC1M = RegisterMask<TIM3_CCMR1_ALTERNATE1, (0x7u << 0x4u)>; + using OC1CE = RegisterMask<TIM3_CCMR1_ALTERNATE1, (0x1u << 0x7u)>; + using CC2S = RegisterMask<TIM3_CCMR1_ALTERNATE1, (0x3u << 0x8u)>; + using OC2FE = RegisterMask<TIM3_CCMR1_ALTERNATE1, (0x1u << 0xau)>; + using OC2PE = RegisterMask<TIM3_CCMR1_ALTERNATE1, (0x1u << 0xbu)>; + using OC2M = RegisterMask<TIM3_CCMR1_ALTERNATE1, (0x7u << 0xcu)>; + using OC2CE = RegisterMask<TIM3_CCMR1_ALTERNATE1, (0x1u << 0xfu)>; + using OC1M_1 = RegisterMask<TIM3_CCMR1_ALTERNATE1, (0x1u << 0x10u)>; + using OC2M_1 = RegisterMask<TIM3_CCMR1_ALTERNATE1, (0x1u << 0x18u)>; + }; + struct TIM3_CCMR2 : public MemRegister<uint32_t, 0x4000041c> { + using CC3S = RegisterMask<TIM3_CCMR2, (0x3u << 0x0u)>; + using IC3PSC = RegisterMask<TIM3_CCMR2, (0x3u << 0x2u)>; + using IC3F = RegisterMask<TIM3_CCMR2, (0xfu << 0x4u)>; + using CC4S = RegisterMask<TIM3_CCMR2, (0x3u << 0x8u)>; + using IC4PSC = RegisterMask<TIM3_CCMR2, (0x3u << 0xau)>; + using IC4F = RegisterMask<TIM3_CCMR2, (0xfu << 0xcu)>; + }; + struct TIM3_CCMR2_ALTERNATE1 : public MemRegister<uint32_t, 0x4000041c> { + using CC3S = RegisterMask<TIM3_CCMR2_ALTERNATE1, (0x3u << 0x0u)>; + using OC3FE = RegisterMask<TIM3_CCMR2_ALTERNATE1, (0x1u << 0x2u)>; + using OC3PE = RegisterMask<TIM3_CCMR2_ALTERNATE1, (0x1u << 0x3u)>; + using OC3M = RegisterMask<TIM3_CCMR2_ALTERNATE1, (0x7u << 0x4u)>; + using OC3CE = RegisterMask<TIM3_CCMR2_ALTERNATE1, (0x1u << 0x7u)>; + using CC4S = RegisterMask<TIM3_CCMR2_ALTERNATE1, (0x3u << 0x8u)>; + using OC4FE = RegisterMask<TIM3_CCMR2_ALTERNATE1, (0x1u << 0xau)>; + using OC4PE = RegisterMask<TIM3_CCMR2_ALTERNATE1, (0x1u << 0xbu)>; + using OC4M = RegisterMask<TIM3_CCMR2_ALTERNATE1, (0x7u << 0xcu)>; + using OC4CE = RegisterMask<TIM3_CCMR2_ALTERNATE1, (0x1u << 0xfu)>; + using OC3M_1 = RegisterMask<TIM3_CCMR2_ALTERNATE1, (0x1u << 0x10u)>; + using OC4M_1 = RegisterMask<TIM3_CCMR2_ALTERNATE1, (0x1u << 0x18u)>; + }; + struct TIM3_CCER : public MemRegister<uint16_t, 0x40000420> { + using CC1E = RegisterMask<TIM3_CCER, (0x1u << 0x0u)>; + using CC1P = RegisterMask<TIM3_CCER, (0x1u << 0x1u)>; + using CC1NP = RegisterMask<TIM3_CCER, (0x1u << 0x3u)>; + using CC2E = RegisterMask<TIM3_CCER, (0x1u << 0x4u)>; + using CC2P = RegisterMask<TIM3_CCER, (0x1u << 0x5u)>; + using CC2NP = RegisterMask<TIM3_CCER, (0x1u << 0x7u)>; + using CC3E = RegisterMask<TIM3_CCER, (0x1u << 0x8u)>; + using CC3P = RegisterMask<TIM3_CCER, (0x1u << 0x9u)>; + using CC3NP = RegisterMask<TIM3_CCER, (0x1u << 0xbu)>; + using CC4E = RegisterMask<TIM3_CCER, (0x1u << 0xcu)>; + using CC4P = RegisterMask<TIM3_CCER, (0x1u << 0xdu)>; + using CC4NP = RegisterMask<TIM3_CCER, (0x1u << 0xfu)>; + }; + struct TIM3_CNT : public MemRegister<uint32_t, 0x40000424> { + using CNT = RegisterMask<TIM3_CNT, (0x0u << 0x0u)>; + }; + struct TIM3_CNT_ALTERNATE1 : public MemRegister<uint32_t, 0x40000424> { + using CNT = RegisterMask<TIM3_CNT_ALTERNATE1, (0x7fffffffu << 0x0u)>; + using UIFCPY = RegisterMask<TIM3_CNT_ALTERNATE1, (0x1u << 0x1fu)>; + }; + struct TIM3_PSC : public MemRegister<uint16_t, 0x40000428> { + using PSC = RegisterMask<TIM3_PSC, (0xffffu << 0x0u)>; + }; + struct TIM3_ARR : public MemRegister<uint32_t, 0x4000042c> { + using ARR = RegisterMask<TIM3_ARR, (0x0u << 0x0u)>; + }; + struct TIM3_CCR1 : public MemRegister<uint32_t, 0x40000434> { + using CCR1 = RegisterMask<TIM3_CCR1, (0x0u << 0x0u)>; + }; + struct TIM3_CCR2 : public MemRegister<uint32_t, 0x40000438> { + using CCR2 = RegisterMask<TIM3_CCR2, (0x0u << 0x0u)>; + }; + struct TIM3_CCR3 : public MemRegister<uint32_t, 0x4000043c> { + using CCR3 = RegisterMask<TIM3_CCR3, (0x0u << 0x0u)>; + }; + struct TIM3_CCR4 : public MemRegister<uint32_t, 0x40000440> { + using CCR4 = RegisterMask<TIM3_CCR4, (0x0u << 0x0u)>; + }; + struct TIM3_DCR : public MemRegister<uint16_t, 0x40000448> { + using DBA = RegisterMask<TIM3_DCR, (0x1fu << 0x0u)>; + using DBL = RegisterMask<TIM3_DCR, (0x1fu << 0x8u)>; + }; + struct TIM3_DMAR : public MemRegister<uint16_t, 0x4000044c> { + using DMAB = RegisterMask<TIM3_DMAR, (0xffffu << 0x0u)>; + }; + struct TIM3_OR1 : public MemRegister<uint32_t, 0x40000450> { + using OCREF_CLR = RegisterMask<TIM3_OR1, (0x3u << 0x0u)>; + }; + struct TIM3_AF1 : public MemRegister<uint32_t, 0x40000460> { + using ETRSEL = RegisterMask<TIM3_AF1, (0xfu << 0xeu)>; + }; + struct TIM3_TISEL : public MemRegister<uint32_t, 0x40000468> { + using TI1SEL = RegisterMask<TIM3_TISEL, (0xfu << 0x0u)>; + using TI2SEL = RegisterMask<TIM3_TISEL, (0xfu << 0x8u)>; + using TI3SEL = RegisterMask<TIM3_TISEL, (0xfu << 0x10u)>; + }; + using ALL = RegisterGroup<TIM3_CR1, TIM3_CR2, TIM3_SMCR, TIM3_DIER, TIM3_SR, TIM3_EGR, TIM3_CCMR1, TIM3_CCMR1_ALTERNATE1, TIM3_CCMR2, TIM3_CCMR2_ALTERNATE1, TIM3_CCER, TIM3_CNT, TIM3_CNT_ALTERNATE1, TIM3_PSC, TIM3_ARR, TIM3_CCR1, TIM3_CCR2, TIM3_CCR3, TIM3_CCR4, TIM3_DCR, TIM3_DMAR, TIM3_OR1, TIM3_AF1, TIM3_TISEL>; + } + namespace TIM6 { + struct TIM6_CR1 : public MemRegister<uint16_t, 0x40001000> { + using CEN = RegisterMask<TIM6_CR1, (0x1u << 0x0u)>; + using UDIS = RegisterMask<TIM6_CR1, (0x1u << 0x1u)>; + using URS = RegisterMask<TIM6_CR1, (0x1u << 0x2u)>; + using OPM = RegisterMask<TIM6_CR1, (0x1u << 0x3u)>; + using ARPE = RegisterMask<TIM6_CR1, (0x1u << 0x7u)>; + using UIFREMAP = RegisterMask<TIM6_CR1, (0x1u << 0xbu)>; + }; + struct TIM6_CR2 : public MemRegister<uint16_t, 0x40001004> { + using MMS = RegisterMask<TIM6_CR2, (0x7u << 0x4u)>; + }; + struct TIM6_DIER : public MemRegister<uint16_t, 0x4000100c> { + using UIE = RegisterMask<TIM6_DIER, (0x1u << 0x0u)>; + using UDE = RegisterMask<TIM6_DIER, (0x1u << 0x8u)>; + }; + struct TIM6_SR : public MemRegister<uint16_t, 0x40001010> { + using UIF = RegisterMask<TIM6_SR, (0x1u << 0x0u)>; + }; + struct TIM6_EGR : public MemRegister<uint16_t, 0x40001014> { + using UG = RegisterMask<TIM6_EGR, (0x1u << 0x0u)>; + }; + struct TIM6_CNT : public MemRegister<uint32_t, 0x40001024> { + using CNT = RegisterMask<TIM6_CNT, (0xffffu << 0x0u)>; + using UIFCPY = RegisterMask<TIM6_CNT, (0x1u << 0x1fu)>; + }; + struct TIM6_PSC : public MemRegister<uint16_t, 0x40001028> { + using PSC = RegisterMask<TIM6_PSC, (0xffffu << 0x0u)>; + }; + struct TIM6_ARR : public MemRegister<uint16_t, 0x4000102c> { + using ARR = RegisterMask<TIM6_ARR, (0xffffu << 0x0u)>; + }; + using ALL = RegisterGroup<TIM6_CR1, TIM6_CR2, TIM6_DIER, TIM6_SR, TIM6_EGR, TIM6_CNT, TIM6_PSC, TIM6_ARR>; + } + namespace TIM7 { + struct TIM7_CR1 : public MemRegister<uint16_t, 0x40001400> { + using CEN = RegisterMask<TIM7_CR1, (0x1u << 0x0u)>; + using UDIS = RegisterMask<TIM7_CR1, (0x1u << 0x1u)>; + using URS = RegisterMask<TIM7_CR1, (0x1u << 0x2u)>; + using OPM = RegisterMask<TIM7_CR1, (0x1u << 0x3u)>; + using ARPE = RegisterMask<TIM7_CR1, (0x1u << 0x7u)>; + using UIFREMAP = RegisterMask<TIM7_CR1, (0x1u << 0xbu)>; + }; + struct TIM7_CR2 : public MemRegister<uint16_t, 0x40001404> { + using MMS = RegisterMask<TIM7_CR2, (0x7u << 0x4u)>; + }; + struct TIM7_DIER : public MemRegister<uint16_t, 0x4000140c> { + using UIE = RegisterMask<TIM7_DIER, (0x1u << 0x0u)>; + using UDE = RegisterMask<TIM7_DIER, (0x1u << 0x8u)>; + }; + struct TIM7_SR : public MemRegister<uint16_t, 0x40001410> { + using UIF = RegisterMask<TIM7_SR, (0x1u << 0x0u)>; + }; + struct TIM7_EGR : public MemRegister<uint16_t, 0x40001414> { + using UG = RegisterMask<TIM7_EGR, (0x1u << 0x0u)>; + }; + struct TIM7_CNT : public MemRegister<uint32_t, 0x40001424> { + using CNT = RegisterMask<TIM7_CNT, (0xffffu << 0x0u)>; + using UIFCPY = RegisterMask<TIM7_CNT, (0x1u << 0x1fu)>; + }; + struct TIM7_PSC : public MemRegister<uint16_t, 0x40001428> { + using PSC = RegisterMask<TIM7_PSC, (0xffffu << 0x0u)>; + }; + struct TIM7_ARR : public MemRegister<uint16_t, 0x4000142c> { + using ARR = RegisterMask<TIM7_ARR, (0xffffu << 0x0u)>; + }; + using ALL = RegisterGroup<TIM7_CR1, TIM7_CR2, TIM7_DIER, TIM7_SR, TIM7_EGR, TIM7_CNT, TIM7_PSC, TIM7_ARR>; + } + namespace TSC { + struct CR : public MemRegister<uint32_t, 0x40024000> { + using TSCE = RegisterMask<CR, (0x1u << 0x0u)>; + using START = RegisterMask<CR, (0x1u << 0x1u)>; + using AM = RegisterMask<CR, (0x1u << 0x2u)>; + using SYNCPOL = RegisterMask<CR, (0x1u << 0x3u)>; + using IODEF = RegisterMask<CR, (0x1u << 0x4u)>; + using MCV = RegisterMask<CR, (0x7u << 0x5u)>; + using PGPSC = RegisterMask<CR, (0x7u << 0xcu)>; + using SSPSC = RegisterMask<CR, (0x1u << 0xfu)>; + using SSE = RegisterMask<CR, (0x1u << 0x10u)>; + using SSD = RegisterMask<CR, (0x7fu << 0x11u)>; + using CTPL = RegisterMask<CR, (0xfu << 0x18u)>; + using CTPH = RegisterMask<CR, (0xfu << 0x1cu)>; + }; + struct IER : public MemRegister<uint32_t, 0x40024004> { + using EOAIE = RegisterMask<IER, (0x1u << 0x0u)>; + using MCEIE = RegisterMask<IER, (0x1u << 0x1u)>; + }; + struct ICR : public MemRegister<uint32_t, 0x40024008> { + using EOAIC = RegisterMask<ICR, (0x1u << 0x0u)>; + using MCEIC = RegisterMask<ICR, (0x1u << 0x1u)>; + }; + struct ISR : public MemRegister<uint32_t, 0x4002400c> { + using EOAF = RegisterMask<ISR, (0x1u << 0x0u)>; + using MCEF = RegisterMask<ISR, (0x1u << 0x1u)>; + }; + struct IOHCR : public MemRegister<uint32_t, 0x40024010> { + using G1_IO1 = RegisterMask<IOHCR, (0x1u << 0x0u)>; + using G1_IO2 = RegisterMask<IOHCR, (0x1u << 0x1u)>; + using G1_IO3 = RegisterMask<IOHCR, (0x1u << 0x2u)>; + using G1_IO4 = RegisterMask<IOHCR, (0x1u << 0x3u)>; + using G2_IO1 = RegisterMask<IOHCR, (0x1u << 0x4u)>; + using G2_IO2 = RegisterMask<IOHCR, (0x1u << 0x5u)>; + using G2_IO3 = RegisterMask<IOHCR, (0x1u << 0x6u)>; + using G2_IO4 = RegisterMask<IOHCR, (0x1u << 0x7u)>; + using G3_IO1 = RegisterMask<IOHCR, (0x1u << 0x8u)>; + using G3_IO2 = RegisterMask<IOHCR, (0x1u << 0x9u)>; + using G3_IO3 = RegisterMask<IOHCR, (0x1u << 0xau)>; + using G3_IO4 = RegisterMask<IOHCR, (0x1u << 0xbu)>; + using G4_IO1 = RegisterMask<IOHCR, (0x1u << 0xcu)>; + using G4_IO2 = RegisterMask<IOHCR, (0x1u << 0xdu)>; + using G4_IO3 = RegisterMask<IOHCR, (0x1u << 0xeu)>; + using G4_IO4 = RegisterMask<IOHCR, (0x1u << 0xfu)>; + using G5_IO1 = RegisterMask<IOHCR, (0x1u << 0x10u)>; + using G5_IO2 = RegisterMask<IOHCR, (0x1u << 0x11u)>; + using G5_IO3 = RegisterMask<IOHCR, (0x1u << 0x12u)>; + using G5_IO4 = RegisterMask<IOHCR, (0x1u << 0x13u)>; + using G6_IO1 = RegisterMask<IOHCR, (0x1u << 0x14u)>; + using G6_IO2 = RegisterMask<IOHCR, (0x1u << 0x15u)>; + using G6_IO3 = RegisterMask<IOHCR, (0x1u << 0x16u)>; + using G6_IO4 = RegisterMask<IOHCR, (0x1u << 0x17u)>; + using G7_IO1 = RegisterMask<IOHCR, (0x1u << 0x18u)>; + using G7_IO2 = RegisterMask<IOHCR, (0x1u << 0x19u)>; + using G7_IO3 = RegisterMask<IOHCR, (0x1u << 0x1au)>; + using G7_IO4 = RegisterMask<IOHCR, (0x1u << 0x1bu)>; + }; + struct IOASCR : public MemRegister<uint32_t, 0x40024018> { + using G1_IO1 = RegisterMask<IOASCR, (0x1u << 0x0u)>; + using G1_IO2 = RegisterMask<IOASCR, (0x1u << 0x1u)>; + using G1_IO3 = RegisterMask<IOASCR, (0x1u << 0x2u)>; + using G1_IO4 = RegisterMask<IOASCR, (0x1u << 0x3u)>; + using G2_IO1 = RegisterMask<IOASCR, (0x1u << 0x4u)>; + using G2_IO2 = RegisterMask<IOASCR, (0x1u << 0x5u)>; + using G2_IO3 = RegisterMask<IOASCR, (0x1u << 0x6u)>; + using G2_IO4 = RegisterMask<IOASCR, (0x1u << 0x7u)>; + using G3_IO1 = RegisterMask<IOASCR, (0x1u << 0x8u)>; + using G3_IO2 = RegisterMask<IOASCR, (0x1u << 0x9u)>; + using G3_IO3 = RegisterMask<IOASCR, (0x1u << 0xau)>; + using G3_IO4 = RegisterMask<IOASCR, (0x1u << 0xbu)>; + using G4_IO1 = RegisterMask<IOASCR, (0x1u << 0xcu)>; + using G4_IO2 = RegisterMask<IOASCR, (0x1u << 0xdu)>; + using G4_IO3 = RegisterMask<IOASCR, (0x1u << 0xeu)>; + using G4_IO4 = RegisterMask<IOASCR, (0x1u << 0xfu)>; + using G5_IO1 = RegisterMask<IOASCR, (0x1u << 0x10u)>; + using G5_IO2 = RegisterMask<IOASCR, (0x1u << 0x11u)>; + using G5_IO3 = RegisterMask<IOASCR, (0x1u << 0x12u)>; + using G5_IO4 = RegisterMask<IOASCR, (0x1u << 0x13u)>; + using G6_IO1 = RegisterMask<IOASCR, (0x1u << 0x14u)>; + using G6_IO2 = RegisterMask<IOASCR, (0x1u << 0x15u)>; + using G6_IO3 = RegisterMask<IOASCR, (0x1u << 0x16u)>; + using G6_IO4 = RegisterMask<IOASCR, (0x1u << 0x17u)>; + using G7_IO1 = RegisterMask<IOASCR, (0x1u << 0x18u)>; + using G7_IO2 = RegisterMask<IOASCR, (0x1u << 0x19u)>; + using G7_IO3 = RegisterMask<IOASCR, (0x1u << 0x1au)>; + using G7_IO4 = RegisterMask<IOASCR, (0x1u << 0x1bu)>; + }; + struct IOSCR : public MemRegister<uint32_t, 0x40024020> { + using G1_IO1 = RegisterMask<IOSCR, (0x1u << 0x0u)>; + using G1_IO2 = RegisterMask<IOSCR, (0x1u << 0x1u)>; + using G1_IO3 = RegisterMask<IOSCR, (0x1u << 0x2u)>; + using G1_IO4 = RegisterMask<IOSCR, (0x1u << 0x3u)>; + using G2_IO1 = RegisterMask<IOSCR, (0x1u << 0x4u)>; + using G2_IO2 = RegisterMask<IOSCR, (0x1u << 0x5u)>; + using G2_IO3 = RegisterMask<IOSCR, (0x1u << 0x6u)>; + using G2_IO4 = RegisterMask<IOSCR, (0x1u << 0x7u)>; + using G3_IO1 = RegisterMask<IOSCR, (0x1u << 0x8u)>; + using G3_IO2 = RegisterMask<IOSCR, (0x1u << 0x9u)>; + using G3_IO3 = RegisterMask<IOSCR, (0x1u << 0xau)>; + using G3_IO4 = RegisterMask<IOSCR, (0x1u << 0xbu)>; + using G4_IO1 = RegisterMask<IOSCR, (0x1u << 0xcu)>; + using G4_IO2 = RegisterMask<IOSCR, (0x1u << 0xdu)>; + using G4_IO3 = RegisterMask<IOSCR, (0x1u << 0xeu)>; + using G4_IO4 = RegisterMask<IOSCR, (0x1u << 0xfu)>; + using G5_IO1 = RegisterMask<IOSCR, (0x1u << 0x10u)>; + using G5_IO2 = RegisterMask<IOSCR, (0x1u << 0x11u)>; + using G5_IO3 = RegisterMask<IOSCR, (0x1u << 0x12u)>; + using G5_IO4 = RegisterMask<IOSCR, (0x1u << 0x13u)>; + using G6_IO1 = RegisterMask<IOSCR, (0x1u << 0x14u)>; + using G6_IO2 = RegisterMask<IOSCR, (0x1u << 0x15u)>; + using G6_IO3 = RegisterMask<IOSCR, (0x1u << 0x16u)>; + using G6_IO4 = RegisterMask<IOSCR, (0x1u << 0x17u)>; + using G7_IO1 = RegisterMask<IOSCR, (0x1u << 0x18u)>; + using G7_IO2 = RegisterMask<IOSCR, (0x1u << 0x19u)>; + using G7_IO3 = RegisterMask<IOSCR, (0x1u << 0x1au)>; + using G7_IO4 = RegisterMask<IOSCR, (0x1u << 0x1bu)>; + }; + struct IOCCR : public MemRegister<uint32_t, 0x40024028> { + using G1_IO1 = RegisterMask<IOCCR, (0x1u << 0x0u)>; + using G1_IO2 = RegisterMask<IOCCR, (0x1u << 0x1u)>; + using G1_IO3 = RegisterMask<IOCCR, (0x1u << 0x2u)>; + using G1_IO4 = RegisterMask<IOCCR, (0x1u << 0x3u)>; + using G2_IO1 = RegisterMask<IOCCR, (0x1u << 0x4u)>; + using G2_IO2 = RegisterMask<IOCCR, (0x1u << 0x5u)>; + using G2_IO3 = RegisterMask<IOCCR, (0x1u << 0x6u)>; + using G2_IO4 = RegisterMask<IOCCR, (0x1u << 0x7u)>; + using G3_IO1 = RegisterMask<IOCCR, (0x1u << 0x8u)>; + using G3_IO2 = RegisterMask<IOCCR, (0x1u << 0x9u)>; + using G3_IO3 = RegisterMask<IOCCR, (0x1u << 0xau)>; + using G3_IO4 = RegisterMask<IOCCR, (0x1u << 0xbu)>; + using G4_IO1 = RegisterMask<IOCCR, (0x1u << 0xcu)>; + using G4_IO2 = RegisterMask<IOCCR, (0x1u << 0xdu)>; + using G4_IO3 = RegisterMask<IOCCR, (0x1u << 0xeu)>; + using G4_IO4 = RegisterMask<IOCCR, (0x1u << 0xfu)>; + using G5_IO1 = RegisterMask<IOCCR, (0x1u << 0x10u)>; + using G5_IO2 = RegisterMask<IOCCR, (0x1u << 0x11u)>; + using G5_IO3 = RegisterMask<IOCCR, (0x1u << 0x12u)>; + using G5_IO4 = RegisterMask<IOCCR, (0x1u << 0x13u)>; + using G6_IO1 = RegisterMask<IOCCR, (0x1u << 0x14u)>; + using G6_IO2 = RegisterMask<IOCCR, (0x1u << 0x15u)>; + using G6_IO3 = RegisterMask<IOCCR, (0x1u << 0x16u)>; + using G6_IO4 = RegisterMask<IOCCR, (0x1u << 0x17u)>; + using G7_IO1 = RegisterMask<IOCCR, (0x1u << 0x18u)>; + using G7_IO2 = RegisterMask<IOCCR, (0x1u << 0x19u)>; + using G7_IO3 = RegisterMask<IOCCR, (0x1u << 0x1au)>; + using G7_IO4 = RegisterMask<IOCCR, (0x1u << 0x1bu)>; + }; + struct IOGCSR : public MemRegister<uint32_t, 0x40024030> { + using G1E = RegisterMask<IOGCSR, (0x1u << 0x0u)>; + using G2E = RegisterMask<IOGCSR, (0x1u << 0x1u)>; + using G3E = RegisterMask<IOGCSR, (0x1u << 0x2u)>; + using G4E = RegisterMask<IOGCSR, (0x1u << 0x3u)>; + using G5E = RegisterMask<IOGCSR, (0x1u << 0x4u)>; + using G6E = RegisterMask<IOGCSR, (0x1u << 0x5u)>; + using G7E = RegisterMask<IOGCSR, (0x1u << 0x6u)>; + using G1S = RegisterMask<IOGCSR, (0x1u << 0x10u)>; + using G2S = RegisterMask<IOGCSR, (0x1u << 0x11u)>; + using G3S = RegisterMask<IOGCSR, (0x1u << 0x12u)>; + using G4S = RegisterMask<IOGCSR, (0x1u << 0x13u)>; + using G5S = RegisterMask<IOGCSR, (0x1u << 0x14u)>; + using G6S = RegisterMask<IOGCSR, (0x1u << 0x15u)>; + using G7S = RegisterMask<IOGCSR, (0x1u << 0x16u)>; + }; + struct IOG1CR : public MemRegister<uint32_t, 0x40024034> { + using CNT = RegisterMask<IOG1CR, (0x3fffu << 0x0u)>; + }; + struct IOG2CR : public MemRegister<uint32_t, 0x40024038> { + using CNT = RegisterMask<IOG2CR, (0x3fffu << 0x0u)>; + }; + struct IOG3CR : public MemRegister<uint32_t, 0x4002403c> { + using CNT = RegisterMask<IOG3CR, (0x3fffu << 0x0u)>; + }; + struct IOG4CR : public MemRegister<uint32_t, 0x40024040> { + using CNT = RegisterMask<IOG4CR, (0x3fffu << 0x0u)>; + }; + struct IOG5CR : public MemRegister<uint32_t, 0x40024044> { + using CNT = RegisterMask<IOG5CR, (0x3fffu << 0x0u)>; + }; + struct IOG6CR : public MemRegister<uint32_t, 0x40024048> { + using CNT = RegisterMask<IOG6CR, (0x3fffu << 0x0u)>; + }; + struct IOG7CR : public MemRegister<uint32_t, 0x4002404c> { + using CNT = RegisterMask<IOG7CR, (0x3fffu << 0x0u)>; + }; + using ALL = RegisterGroup<CR, IER, ICR, ISR, IOHCR, IOASCR, IOSCR, IOCCR, IOGCSR, IOG1CR, IOG2CR, IOG3CR, IOG4CR, IOG5CR, IOG6CR, IOG7CR>; + } + namespace USART1 { + struct CR1 : public MemRegister<uint32_t, 0x40013800> { + using UE = RegisterMask<CR1, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1, (0x1u << 0x4u)>; + using RXFNEIE = RegisterMask<CR1, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1, (0x1u << 0x6u)>; + using TXFNFIE = RegisterMask<CR1, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1, (0x1u << 0xeu)>; + using OVER8 = RegisterMask<CR1, (0x1u << 0xfu)>; + using DEDT = RegisterMask<CR1, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1, (0x1fu << 0x15u)>; + using RTOIE = RegisterMask<CR1, (0x1u << 0x1au)>; + using EOBIE = RegisterMask<CR1, (0x1u << 0x1bu)>; + using M1 = RegisterMask<CR1, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1, (0x1u << 0x1du)>; + using TXFEIE = RegisterMask<CR1, (0x1u << 0x1eu)>; + using RXFFIE = RegisterMask<CR1, (0x1u << 0x1fu)>; + }; + struct CR1_ALTERNATE : public MemRegister<uint32_t, 0x40013800> { + using UE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x4u)>; + using RXNEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x6u)>; + using TXEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1_ALTERNATE, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1_ALTERNATE, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1_ALTERNATE, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xeu)>; + using OVER8 = RegisterMask<CR1_ALTERNATE, (0x1u << 0xfu)>; + using DEDT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x15u)>; + using RTOIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1au)>; + using EOBIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1bu)>; + using M1 = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1du)>; + }; + struct CR2 : public MemRegister<uint32_t, 0x40013804> { + using SLVEN = RegisterMask<CR2, (0x1u << 0x0u)>; + using DIS_NSS = RegisterMask<CR2, (0x1u << 0x3u)>; + using ADDM7 = RegisterMask<CR2, (0x1u << 0x4u)>; + using LBDL = RegisterMask<CR2, (0x1u << 0x5u)>; + using LBDIE = RegisterMask<CR2, (0x1u << 0x6u)>; + using LBCL = RegisterMask<CR2, (0x1u << 0x8u)>; + using CPHA = RegisterMask<CR2, (0x1u << 0x9u)>; + using CPOL = RegisterMask<CR2, (0x1u << 0xau)>; + using CLKEN = RegisterMask<CR2, (0x1u << 0xbu)>; + using STOP = RegisterMask<CR2, (0x3u << 0xcu)>; + using LINEN = RegisterMask<CR2, (0x1u << 0xeu)>; + using SWAP = RegisterMask<CR2, (0x1u << 0xfu)>; + using RXINV = RegisterMask<CR2, (0x1u << 0x10u)>; + using TXINV = RegisterMask<CR2, (0x1u << 0x11u)>; + using DATAINV = RegisterMask<CR2, (0x1u << 0x12u)>; + using MSBFIRST = RegisterMask<CR2, (0x1u << 0x13u)>; + using ABREN = RegisterMask<CR2, (0x1u << 0x14u)>; + using ABRMOD = RegisterMask<CR2, (0x3u << 0x15u)>; + using RTOEN = RegisterMask<CR2, (0x1u << 0x17u)>; + using ADD = RegisterMask<CR2, (0xffu << 0x18u)>; + }; + struct CR3 : public MemRegister<uint32_t, 0x40013808> { + using EIE = RegisterMask<CR3, (0x1u << 0x0u)>; + using IREN = RegisterMask<CR3, (0x1u << 0x1u)>; + using IRLP = RegisterMask<CR3, (0x1u << 0x2u)>; + using HDSEL = RegisterMask<CR3, (0x1u << 0x3u)>; + using NACK = RegisterMask<CR3, (0x1u << 0x4u)>; + using SCEN = RegisterMask<CR3, (0x1u << 0x5u)>; + using DMAR = RegisterMask<CR3, (0x1u << 0x6u)>; + using DMAT = RegisterMask<CR3, (0x1u << 0x7u)>; + using RTSE = RegisterMask<CR3, (0x1u << 0x8u)>; + using CTSE = RegisterMask<CR3, (0x1u << 0x9u)>; + using CTSIE = RegisterMask<CR3, (0x1u << 0xau)>; + using ONEBIT = RegisterMask<CR3, (0x1u << 0xbu)>; + using OVRDIS = RegisterMask<CR3, (0x1u << 0xcu)>; + using DDRE = RegisterMask<CR3, (0x1u << 0xdu)>; + using DEM = RegisterMask<CR3, (0x1u << 0xeu)>; + using DEP = RegisterMask<CR3, (0x1u << 0xfu)>; + using SCARCNT = RegisterMask<CR3, (0x7u << 0x11u)>; + using WUS0 = RegisterMask<CR3, (0x1u << 0x14u)>; + using WUS1 = RegisterMask<CR3, (0x1u << 0x15u)>; + using WUFIE = RegisterMask<CR3, (0x1u << 0x16u)>; + using TXFTIE = RegisterMask<CR3, (0x1u << 0x17u)>; + using TCBGTIE = RegisterMask<CR3, (0x1u << 0x18u)>; + using RXFTCFG = RegisterMask<CR3, (0x7u << 0x19u)>; + using RXFTIE = RegisterMask<CR3, (0x1u << 0x1cu)>; + using TXFTCFG = RegisterMask<CR3, (0x7u << 0x1du)>; + }; + struct BRR : public MemRegister<uint32_t, 0x4001380c> { + using val = RegisterMask<BRR, (0xffffu << 0x0u)>; + }; + struct GTPR : public MemRegister<uint32_t, 0x40013810> { + using PSC = RegisterMask<GTPR, (0xffu << 0x0u)>; + using GT = RegisterMask<GTPR, (0xffu << 0x8u)>; + }; + struct RTOR : public MemRegister<uint32_t, 0x40013814> { + using RTO = RegisterMask<RTOR, (0xffffffu << 0x0u)>; + using BLEN = RegisterMask<RTOR, (0xffu << 0x18u)>; + }; + struct RQR : public MemRegister<uint32_t, 0x40013818> { + using ABRRQ = RegisterMask<RQR, (0x1u << 0x0u)>; + using SBKRQ = RegisterMask<RQR, (0x1u << 0x1u)>; + using MMRQ = RegisterMask<RQR, (0x1u << 0x2u)>; + using RXFRQ = RegisterMask<RQR, (0x1u << 0x3u)>; + using TXFRQ = RegisterMask<RQR, (0x1u << 0x4u)>; + }; + struct ISR : public MemRegister<uint32_t, 0x4001381c> { + using PE = RegisterMask<ISR, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR, (0x1u << 0x4u)>; + using RXFNE = RegisterMask<ISR, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR, (0x1u << 0x6u)>; + using TXFNF = RegisterMask<ISR, (0x1u << 0x7u)>; + using LBDF = RegisterMask<ISR, (0x1u << 0x8u)>; + using CTSIF = RegisterMask<ISR, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR, (0x1u << 0xau)>; + using RTOF = RegisterMask<ISR, (0x1u << 0xbu)>; + using EOBF = RegisterMask<ISR, (0x1u << 0xcu)>; + using UDR = RegisterMask<ISR, (0x1u << 0xdu)>; + using ABRE = RegisterMask<ISR, (0x1u << 0xeu)>; + using ABRF = RegisterMask<ISR, (0x1u << 0xfu)>; + using BUSY = RegisterMask<ISR, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR, (0x1u << 0x16u)>; + using TXFE = RegisterMask<ISR, (0x1u << 0x17u)>; + using RXFF = RegisterMask<ISR, (0x1u << 0x18u)>; + using TCBGT = RegisterMask<ISR, (0x1u << 0x19u)>; + using RXFT = RegisterMask<ISR, (0x1u << 0x1au)>; + using TXFT = RegisterMask<ISR, (0x1u << 0x1bu)>; + }; + struct ISR_ALTERNATE : public MemRegister<uint32_t, 0x4001381c> { + using PE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x4u)>; + using RXNE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR_ALTERNATE, (0x1u << 0x6u)>; + using TXE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x7u)>; + using LBDF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x8u)>; + using CTSIF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR_ALTERNATE, (0x1u << 0xau)>; + using RTOF = RegisterMask<ISR_ALTERNATE, (0x1u << 0xbu)>; + using EOBF = RegisterMask<ISR_ALTERNATE, (0x1u << 0xcu)>; + using UDR = RegisterMask<ISR_ALTERNATE, (0x1u << 0xdu)>; + using ABRE = RegisterMask<ISR_ALTERNATE, (0x1u << 0xeu)>; + using ABRF = RegisterMask<ISR_ALTERNATE, (0x1u << 0xfu)>; + using BUSY = RegisterMask<ISR_ALTERNATE, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR_ALTERNATE, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x16u)>; + using TCBGT = RegisterMask<ISR_ALTERNATE, (0x1u << 0x19u)>; + }; + struct ICR : public MemRegister<uint32_t, 0x40013820> { + using PECF = RegisterMask<ICR, (0x1u << 0x0u)>; + using FECF = RegisterMask<ICR, (0x1u << 0x1u)>; + using NECF = RegisterMask<ICR, (0x1u << 0x2u)>; + using ORECF = RegisterMask<ICR, (0x1u << 0x3u)>; + using IDLECF = RegisterMask<ICR, (0x1u << 0x4u)>; + using TXFECF = RegisterMask<ICR, (0x1u << 0x5u)>; + using TCCF = RegisterMask<ICR, (0x1u << 0x6u)>; + using TCBGTCF = RegisterMask<ICR, (0x1u << 0x7u)>; + using LBDCF = RegisterMask<ICR, (0x1u << 0x8u)>; + using CTSCF = RegisterMask<ICR, (0x1u << 0x9u)>; + using RTOCF = RegisterMask<ICR, (0x1u << 0xbu)>; + using EOBCF = RegisterMask<ICR, (0x1u << 0xcu)>; + using UDRCF = RegisterMask<ICR, (0x1u << 0xdu)>; + using CMCF = RegisterMask<ICR, (0x1u << 0x11u)>; + using WUCF = RegisterMask<ICR, (0x1u << 0x14u)>; + }; + struct RDR : public MemRegister<uint32_t, 0x40013824> { + using val = RegisterMask<RDR, (0x1ffu << 0x0u)>; + }; + struct TDR : public MemRegister<uint32_t, 0x40013828> { + using val = RegisterMask<TDR, (0x1ffu << 0x0u)>; + }; + struct PRESC : public MemRegister<uint32_t, 0x4001382c> { + using PRESCALER = RegisterMask<PRESC, (0xfu << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR1_ALTERNATE, CR2, CR3, BRR, GTPR, RTOR, RQR, ISR, ISR_ALTERNATE, ICR, RDR, TDR, PRESC>; + } + namespace USART2 { + struct CR1 : public MemRegister<uint32_t, 0x40004400> { + using UE = RegisterMask<CR1, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1, (0x1u << 0x4u)>; + using RXFNEIE = RegisterMask<CR1, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1, (0x1u << 0x6u)>; + using TXFNFIE = RegisterMask<CR1, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1, (0x1u << 0xeu)>; + using OVER8 = RegisterMask<CR1, (0x1u << 0xfu)>; + using DEDT = RegisterMask<CR1, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1, (0x1fu << 0x15u)>; + using RTOIE = RegisterMask<CR1, (0x1u << 0x1au)>; + using EOBIE = RegisterMask<CR1, (0x1u << 0x1bu)>; + using M1 = RegisterMask<CR1, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1, (0x1u << 0x1du)>; + using TXFEIE = RegisterMask<CR1, (0x1u << 0x1eu)>; + using RXFFIE = RegisterMask<CR1, (0x1u << 0x1fu)>; + }; + struct CR1_ALTERNATE : public MemRegister<uint32_t, 0x40004400> { + using UE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x4u)>; + using RXNEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x6u)>; + using TXEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1_ALTERNATE, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1_ALTERNATE, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1_ALTERNATE, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xeu)>; + using OVER8 = RegisterMask<CR1_ALTERNATE, (0x1u << 0xfu)>; + using DEDT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x15u)>; + using RTOIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1au)>; + using EOBIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1bu)>; + using M1 = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1du)>; + }; + struct CR2 : public MemRegister<uint32_t, 0x40004404> { + using SLVEN = RegisterMask<CR2, (0x1u << 0x0u)>; + using DIS_NSS = RegisterMask<CR2, (0x1u << 0x3u)>; + using ADDM7 = RegisterMask<CR2, (0x1u << 0x4u)>; + using LBDL = RegisterMask<CR2, (0x1u << 0x5u)>; + using LBDIE = RegisterMask<CR2, (0x1u << 0x6u)>; + using LBCL = RegisterMask<CR2, (0x1u << 0x8u)>; + using CPHA = RegisterMask<CR2, (0x1u << 0x9u)>; + using CPOL = RegisterMask<CR2, (0x1u << 0xau)>; + using CLKEN = RegisterMask<CR2, (0x1u << 0xbu)>; + using STOP = RegisterMask<CR2, (0x3u << 0xcu)>; + using LINEN = RegisterMask<CR2, (0x1u << 0xeu)>; + using SWAP = RegisterMask<CR2, (0x1u << 0xfu)>; + using RXINV = RegisterMask<CR2, (0x1u << 0x10u)>; + using TXINV = RegisterMask<CR2, (0x1u << 0x11u)>; + using DATAINV = RegisterMask<CR2, (0x1u << 0x12u)>; + using MSBFIRST = RegisterMask<CR2, (0x1u << 0x13u)>; + using ABREN = RegisterMask<CR2, (0x1u << 0x14u)>; + using ABRMOD = RegisterMask<CR2, (0x3u << 0x15u)>; + using RTOEN = RegisterMask<CR2, (0x1u << 0x17u)>; + using ADD = RegisterMask<CR2, (0xffu << 0x18u)>; + }; + struct CR3 : public MemRegister<uint32_t, 0x40004408> { + using EIE = RegisterMask<CR3, (0x1u << 0x0u)>; + using IREN = RegisterMask<CR3, (0x1u << 0x1u)>; + using IRLP = RegisterMask<CR3, (0x1u << 0x2u)>; + using HDSEL = RegisterMask<CR3, (0x1u << 0x3u)>; + using NACK = RegisterMask<CR3, (0x1u << 0x4u)>; + using SCEN = RegisterMask<CR3, (0x1u << 0x5u)>; + using DMAR = RegisterMask<CR3, (0x1u << 0x6u)>; + using DMAT = RegisterMask<CR3, (0x1u << 0x7u)>; + using RTSE = RegisterMask<CR3, (0x1u << 0x8u)>; + using CTSE = RegisterMask<CR3, (0x1u << 0x9u)>; + using CTSIE = RegisterMask<CR3, (0x1u << 0xau)>; + using ONEBIT = RegisterMask<CR3, (0x1u << 0xbu)>; + using OVRDIS = RegisterMask<CR3, (0x1u << 0xcu)>; + using DDRE = RegisterMask<CR3, (0x1u << 0xdu)>; + using DEM = RegisterMask<CR3, (0x1u << 0xeu)>; + using DEP = RegisterMask<CR3, (0x1u << 0xfu)>; + using SCARCNT = RegisterMask<CR3, (0x7u << 0x11u)>; + using WUS0 = RegisterMask<CR3, (0x1u << 0x14u)>; + using WUS1 = RegisterMask<CR3, (0x1u << 0x15u)>; + using WUFIE = RegisterMask<CR3, (0x1u << 0x16u)>; + using TXFTIE = RegisterMask<CR3, (0x1u << 0x17u)>; + using TCBGTIE = RegisterMask<CR3, (0x1u << 0x18u)>; + using RXFTCFG = RegisterMask<CR3, (0x7u << 0x19u)>; + using RXFTIE = RegisterMask<CR3, (0x1u << 0x1cu)>; + using TXFTCFG = RegisterMask<CR3, (0x7u << 0x1du)>; + }; + struct BRR : public MemRegister<uint32_t, 0x4000440c> { + using val = RegisterMask<BRR, (0xffffu << 0x0u)>; + }; + struct GTPR : public MemRegister<uint32_t, 0x40004410> { + using PSC = RegisterMask<GTPR, (0xffu << 0x0u)>; + using GT = RegisterMask<GTPR, (0xffu << 0x8u)>; + }; + struct RTOR : public MemRegister<uint32_t, 0x40004414> { + using RTO = RegisterMask<RTOR, (0xffffffu << 0x0u)>; + using BLEN = RegisterMask<RTOR, (0xffu << 0x18u)>; + }; + struct RQR : public MemRegister<uint32_t, 0x40004418> { + using ABRRQ = RegisterMask<RQR, (0x1u << 0x0u)>; + using SBKRQ = RegisterMask<RQR, (0x1u << 0x1u)>; + using MMRQ = RegisterMask<RQR, (0x1u << 0x2u)>; + using RXFRQ = RegisterMask<RQR, (0x1u << 0x3u)>; + using TXFRQ = RegisterMask<RQR, (0x1u << 0x4u)>; + }; + struct ISR : public MemRegister<uint32_t, 0x4000441c> { + using PE = RegisterMask<ISR, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR, (0x1u << 0x4u)>; + using RXFNE = RegisterMask<ISR, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR, (0x1u << 0x6u)>; + using TXFNF = RegisterMask<ISR, (0x1u << 0x7u)>; + using LBDF = RegisterMask<ISR, (0x1u << 0x8u)>; + using CTSIF = RegisterMask<ISR, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR, (0x1u << 0xau)>; + using RTOF = RegisterMask<ISR, (0x1u << 0xbu)>; + using EOBF = RegisterMask<ISR, (0x1u << 0xcu)>; + using UDR = RegisterMask<ISR, (0x1u << 0xdu)>; + using ABRE = RegisterMask<ISR, (0x1u << 0xeu)>; + using ABRF = RegisterMask<ISR, (0x1u << 0xfu)>; + using BUSY = RegisterMask<ISR, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR, (0x1u << 0x16u)>; + using TXFE = RegisterMask<ISR, (0x1u << 0x17u)>; + using RXFF = RegisterMask<ISR, (0x1u << 0x18u)>; + using TCBGT = RegisterMask<ISR, (0x1u << 0x19u)>; + using RXFT = RegisterMask<ISR, (0x1u << 0x1au)>; + using TXFT = RegisterMask<ISR, (0x1u << 0x1bu)>; + }; + struct ISR_ALTERNATE : public MemRegister<uint32_t, 0x4000441c> { + using PE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x4u)>; + using RXNE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR_ALTERNATE, (0x1u << 0x6u)>; + using TXE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x7u)>; + using LBDF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x8u)>; + using CTSIF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR_ALTERNATE, (0x1u << 0xau)>; + using RTOF = RegisterMask<ISR_ALTERNATE, (0x1u << 0xbu)>; + using EOBF = RegisterMask<ISR_ALTERNATE, (0x1u << 0xcu)>; + using UDR = RegisterMask<ISR_ALTERNATE, (0x1u << 0xdu)>; + using ABRE = RegisterMask<ISR_ALTERNATE, (0x1u << 0xeu)>; + using ABRF = RegisterMask<ISR_ALTERNATE, (0x1u << 0xfu)>; + using BUSY = RegisterMask<ISR_ALTERNATE, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR_ALTERNATE, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x16u)>; + using TCBGT = RegisterMask<ISR_ALTERNATE, (0x1u << 0x19u)>; + }; + struct ICR : public MemRegister<uint32_t, 0x40004420> { + using PECF = RegisterMask<ICR, (0x1u << 0x0u)>; + using FECF = RegisterMask<ICR, (0x1u << 0x1u)>; + using NECF = RegisterMask<ICR, (0x1u << 0x2u)>; + using ORECF = RegisterMask<ICR, (0x1u << 0x3u)>; + using IDLECF = RegisterMask<ICR, (0x1u << 0x4u)>; + using TXFECF = RegisterMask<ICR, (0x1u << 0x5u)>; + using TCCF = RegisterMask<ICR, (0x1u << 0x6u)>; + using TCBGTCF = RegisterMask<ICR, (0x1u << 0x7u)>; + using LBDCF = RegisterMask<ICR, (0x1u << 0x8u)>; + using CTSCF = RegisterMask<ICR, (0x1u << 0x9u)>; + using RTOCF = RegisterMask<ICR, (0x1u << 0xbu)>; + using EOBCF = RegisterMask<ICR, (0x1u << 0xcu)>; + using UDRCF = RegisterMask<ICR, (0x1u << 0xdu)>; + using CMCF = RegisterMask<ICR, (0x1u << 0x11u)>; + using WUCF = RegisterMask<ICR, (0x1u << 0x14u)>; + }; + struct RDR : public MemRegister<uint32_t, 0x40004424> { + using val = RegisterMask<RDR, (0x1ffu << 0x0u)>; + }; + struct TDR : public MemRegister<uint32_t, 0x40004428> { + using val = RegisterMask<TDR, (0x1ffu << 0x0u)>; + }; + struct PRESC : public MemRegister<uint32_t, 0x4000442c> { + using PRESCALER = RegisterMask<PRESC, (0xfu << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR1_ALTERNATE, CR2, CR3, BRR, GTPR, RTOR, RQR, ISR, ISR_ALTERNATE, ICR, RDR, TDR, PRESC>; + } + namespace USART3 { + struct CR1 : public MemRegister<uint32_t, 0x40004800> { + using UE = RegisterMask<CR1, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1, (0x1u << 0x4u)>; + using RXFNEIE = RegisterMask<CR1, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1, (0x1u << 0x6u)>; + using TXFNFIE = RegisterMask<CR1, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1, (0x1u << 0xeu)>; + using OVER8 = RegisterMask<CR1, (0x1u << 0xfu)>; + using DEDT = RegisterMask<CR1, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1, (0x1fu << 0x15u)>; + using RTOIE = RegisterMask<CR1, (0x1u << 0x1au)>; + using EOBIE = RegisterMask<CR1, (0x1u << 0x1bu)>; + using M1 = RegisterMask<CR1, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1, (0x1u << 0x1du)>; + using TXFEIE = RegisterMask<CR1, (0x1u << 0x1eu)>; + using RXFFIE = RegisterMask<CR1, (0x1u << 0x1fu)>; + }; + struct CR1_ALTERNATE : public MemRegister<uint32_t, 0x40004800> { + using UE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x4u)>; + using RXNEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x6u)>; + using TXEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1_ALTERNATE, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1_ALTERNATE, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1_ALTERNATE, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xeu)>; + using OVER8 = RegisterMask<CR1_ALTERNATE, (0x1u << 0xfu)>; + using DEDT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x15u)>; + using RTOIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1au)>; + using EOBIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1bu)>; + using M1 = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1du)>; + }; + struct CR2 : public MemRegister<uint32_t, 0x40004804> { + using SLVEN = RegisterMask<CR2, (0x1u << 0x0u)>; + using DIS_NSS = RegisterMask<CR2, (0x1u << 0x3u)>; + using ADDM7 = RegisterMask<CR2, (0x1u << 0x4u)>; + using LBDL = RegisterMask<CR2, (0x1u << 0x5u)>; + using LBDIE = RegisterMask<CR2, (0x1u << 0x6u)>; + using LBCL = RegisterMask<CR2, (0x1u << 0x8u)>; + using CPHA = RegisterMask<CR2, (0x1u << 0x9u)>; + using CPOL = RegisterMask<CR2, (0x1u << 0xau)>; + using CLKEN = RegisterMask<CR2, (0x1u << 0xbu)>; + using STOP = RegisterMask<CR2, (0x3u << 0xcu)>; + using LINEN = RegisterMask<CR2, (0x1u << 0xeu)>; + using SWAP = RegisterMask<CR2, (0x1u << 0xfu)>; + using RXINV = RegisterMask<CR2, (0x1u << 0x10u)>; + using TXINV = RegisterMask<CR2, (0x1u << 0x11u)>; + using DATAINV = RegisterMask<CR2, (0x1u << 0x12u)>; + using MSBFIRST = RegisterMask<CR2, (0x1u << 0x13u)>; + using ABREN = RegisterMask<CR2, (0x1u << 0x14u)>; + using ABRMOD = RegisterMask<CR2, (0x3u << 0x15u)>; + using RTOEN = RegisterMask<CR2, (0x1u << 0x17u)>; + using ADD = RegisterMask<CR2, (0xffu << 0x18u)>; + }; + struct CR3 : public MemRegister<uint32_t, 0x40004808> { + using EIE = RegisterMask<CR3, (0x1u << 0x0u)>; + using IREN = RegisterMask<CR3, (0x1u << 0x1u)>; + using IRLP = RegisterMask<CR3, (0x1u << 0x2u)>; + using HDSEL = RegisterMask<CR3, (0x1u << 0x3u)>; + using NACK = RegisterMask<CR3, (0x1u << 0x4u)>; + using SCEN = RegisterMask<CR3, (0x1u << 0x5u)>; + using DMAR = RegisterMask<CR3, (0x1u << 0x6u)>; + using DMAT = RegisterMask<CR3, (0x1u << 0x7u)>; + using RTSE = RegisterMask<CR3, (0x1u << 0x8u)>; + using CTSE = RegisterMask<CR3, (0x1u << 0x9u)>; + using CTSIE = RegisterMask<CR3, (0x1u << 0xau)>; + using ONEBIT = RegisterMask<CR3, (0x1u << 0xbu)>; + using OVRDIS = RegisterMask<CR3, (0x1u << 0xcu)>; + using DDRE = RegisterMask<CR3, (0x1u << 0xdu)>; + using DEM = RegisterMask<CR3, (0x1u << 0xeu)>; + using DEP = RegisterMask<CR3, (0x1u << 0xfu)>; + using SCARCNT = RegisterMask<CR3, (0x7u << 0x11u)>; + using WUS0 = RegisterMask<CR3, (0x1u << 0x14u)>; + using WUS1 = RegisterMask<CR3, (0x1u << 0x15u)>; + using WUFIE = RegisterMask<CR3, (0x1u << 0x16u)>; + using TXFTIE = RegisterMask<CR3, (0x1u << 0x17u)>; + using TCBGTIE = RegisterMask<CR3, (0x1u << 0x18u)>; + using RXFTCFG = RegisterMask<CR3, (0x7u << 0x19u)>; + using RXFTIE = RegisterMask<CR3, (0x1u << 0x1cu)>; + using TXFTCFG = RegisterMask<CR3, (0x7u << 0x1du)>; + }; + struct BRR : public MemRegister<uint32_t, 0x4000480c> { + using val = RegisterMask<BRR, (0xffffu << 0x0u)>; + }; + struct GTPR : public MemRegister<uint32_t, 0x40004810> { + using PSC = RegisterMask<GTPR, (0xffu << 0x0u)>; + using GT = RegisterMask<GTPR, (0xffu << 0x8u)>; + }; + struct RTOR : public MemRegister<uint32_t, 0x40004814> { + using RTO = RegisterMask<RTOR, (0xffffffu << 0x0u)>; + using BLEN = RegisterMask<RTOR, (0xffu << 0x18u)>; + }; + struct RQR : public MemRegister<uint32_t, 0x40004818> { + using ABRRQ = RegisterMask<RQR, (0x1u << 0x0u)>; + using SBKRQ = RegisterMask<RQR, (0x1u << 0x1u)>; + using MMRQ = RegisterMask<RQR, (0x1u << 0x2u)>; + using RXFRQ = RegisterMask<RQR, (0x1u << 0x3u)>; + using TXFRQ = RegisterMask<RQR, (0x1u << 0x4u)>; + }; + struct ISR : public MemRegister<uint32_t, 0x4000481c> { + using PE = RegisterMask<ISR, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR, (0x1u << 0x4u)>; + using RXFNE = RegisterMask<ISR, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR, (0x1u << 0x6u)>; + using TXFNF = RegisterMask<ISR, (0x1u << 0x7u)>; + using LBDF = RegisterMask<ISR, (0x1u << 0x8u)>; + using CTSIF = RegisterMask<ISR, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR, (0x1u << 0xau)>; + using RTOF = RegisterMask<ISR, (0x1u << 0xbu)>; + using EOBF = RegisterMask<ISR, (0x1u << 0xcu)>; + using UDR = RegisterMask<ISR, (0x1u << 0xdu)>; + using ABRE = RegisterMask<ISR, (0x1u << 0xeu)>; + using ABRF = RegisterMask<ISR, (0x1u << 0xfu)>; + using BUSY = RegisterMask<ISR, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR, (0x1u << 0x16u)>; + using TXFE = RegisterMask<ISR, (0x1u << 0x17u)>; + using RXFF = RegisterMask<ISR, (0x1u << 0x18u)>; + using TCBGT = RegisterMask<ISR, (0x1u << 0x19u)>; + using RXFT = RegisterMask<ISR, (0x1u << 0x1au)>; + using TXFT = RegisterMask<ISR, (0x1u << 0x1bu)>; + }; + struct ISR_ALTERNATE : public MemRegister<uint32_t, 0x4000481c> { + using PE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x4u)>; + using RXNE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR_ALTERNATE, (0x1u << 0x6u)>; + using TXE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x7u)>; + using LBDF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x8u)>; + using CTSIF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR_ALTERNATE, (0x1u << 0xau)>; + using RTOF = RegisterMask<ISR_ALTERNATE, (0x1u << 0xbu)>; + using EOBF = RegisterMask<ISR_ALTERNATE, (0x1u << 0xcu)>; + using UDR = RegisterMask<ISR_ALTERNATE, (0x1u << 0xdu)>; + using ABRE = RegisterMask<ISR_ALTERNATE, (0x1u << 0xeu)>; + using ABRF = RegisterMask<ISR_ALTERNATE, (0x1u << 0xfu)>; + using BUSY = RegisterMask<ISR_ALTERNATE, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR_ALTERNATE, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x16u)>; + using TCBGT = RegisterMask<ISR_ALTERNATE, (0x1u << 0x19u)>; + }; + struct ICR : public MemRegister<uint32_t, 0x40004820> { + using PECF = RegisterMask<ICR, (0x1u << 0x0u)>; + using FECF = RegisterMask<ICR, (0x1u << 0x1u)>; + using NECF = RegisterMask<ICR, (0x1u << 0x2u)>; + using ORECF = RegisterMask<ICR, (0x1u << 0x3u)>; + using IDLECF = RegisterMask<ICR, (0x1u << 0x4u)>; + using TXFECF = RegisterMask<ICR, (0x1u << 0x5u)>; + using TCCF = RegisterMask<ICR, (0x1u << 0x6u)>; + using TCBGTCF = RegisterMask<ICR, (0x1u << 0x7u)>; + using LBDCF = RegisterMask<ICR, (0x1u << 0x8u)>; + using CTSCF = RegisterMask<ICR, (0x1u << 0x9u)>; + using RTOCF = RegisterMask<ICR, (0x1u << 0xbu)>; + using EOBCF = RegisterMask<ICR, (0x1u << 0xcu)>; + using UDRCF = RegisterMask<ICR, (0x1u << 0xdu)>; + using CMCF = RegisterMask<ICR, (0x1u << 0x11u)>; + using WUCF = RegisterMask<ICR, (0x1u << 0x14u)>; + }; + struct RDR : public MemRegister<uint32_t, 0x40004824> { + using val = RegisterMask<RDR, (0x1ffu << 0x0u)>; + }; + struct TDR : public MemRegister<uint32_t, 0x40004828> { + using val = RegisterMask<TDR, (0x1ffu << 0x0u)>; + }; + struct PRESC : public MemRegister<uint32_t, 0x4000482c> { + using PRESCALER = RegisterMask<PRESC, (0xfu << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR1_ALTERNATE, CR2, CR3, BRR, GTPR, RTOR, RQR, ISR, ISR_ALTERNATE, ICR, RDR, TDR, PRESC>; + } + namespace USART4 { + struct CR1 : public MemRegister<uint32_t, 0x40004c00> { + using UE = RegisterMask<CR1, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1, (0x1u << 0x4u)>; + using RXFNEIE = RegisterMask<CR1, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1, (0x1u << 0x6u)>; + using TXFNFIE = RegisterMask<CR1, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1, (0x1u << 0xeu)>; + using OVER8 = RegisterMask<CR1, (0x1u << 0xfu)>; + using DEDT = RegisterMask<CR1, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1, (0x1fu << 0x15u)>; + using RTOIE = RegisterMask<CR1, (0x1u << 0x1au)>; + using EOBIE = RegisterMask<CR1, (0x1u << 0x1bu)>; + using M1 = RegisterMask<CR1, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1, (0x1u << 0x1du)>; + using TXFEIE = RegisterMask<CR1, (0x1u << 0x1eu)>; + using RXFFIE = RegisterMask<CR1, (0x1u << 0x1fu)>; + }; + struct CR1_ALTERNATE : public MemRegister<uint32_t, 0x40004c00> { + using UE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x0u)>; + using UESM = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1u)>; + using RE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x2u)>; + using TE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x3u)>; + using IDLEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x4u)>; + using RXNEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x5u)>; + using TCIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x6u)>; + using TXEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x7u)>; + using PEIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x8u)>; + using PS = RegisterMask<CR1_ALTERNATE, (0x1u << 0x9u)>; + using PCE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xau)>; + using WAKE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xbu)>; + using M0 = RegisterMask<CR1_ALTERNATE, (0x1u << 0xcu)>; + using MME = RegisterMask<CR1_ALTERNATE, (0x1u << 0xdu)>; + using CMIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0xeu)>; + using OVER8 = RegisterMask<CR1_ALTERNATE, (0x1u << 0xfu)>; + using DEDT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x10u)>; + using DEAT = RegisterMask<CR1_ALTERNATE, (0x1fu << 0x15u)>; + using RTOIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1au)>; + using EOBIE = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1bu)>; + using M1 = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1cu)>; + using FIFOEN = RegisterMask<CR1_ALTERNATE, (0x1u << 0x1du)>; + }; + struct CR2 : public MemRegister<uint32_t, 0x40004c04> { + using SLVEN = RegisterMask<CR2, (0x1u << 0x0u)>; + using DIS_NSS = RegisterMask<CR2, (0x1u << 0x3u)>; + using ADDM7 = RegisterMask<CR2, (0x1u << 0x4u)>; + using LBDL = RegisterMask<CR2, (0x1u << 0x5u)>; + using LBDIE = RegisterMask<CR2, (0x1u << 0x6u)>; + using LBCL = RegisterMask<CR2, (0x1u << 0x8u)>; + using CPHA = RegisterMask<CR2, (0x1u << 0x9u)>; + using CPOL = RegisterMask<CR2, (0x1u << 0xau)>; + using CLKEN = RegisterMask<CR2, (0x1u << 0xbu)>; + using STOP = RegisterMask<CR2, (0x3u << 0xcu)>; + using LINEN = RegisterMask<CR2, (0x1u << 0xeu)>; + using SWAP = RegisterMask<CR2, (0x1u << 0xfu)>; + using RXINV = RegisterMask<CR2, (0x1u << 0x10u)>; + using TXINV = RegisterMask<CR2, (0x1u << 0x11u)>; + using DATAINV = RegisterMask<CR2, (0x1u << 0x12u)>; + using MSBFIRST = RegisterMask<CR2, (0x1u << 0x13u)>; + using ABREN = RegisterMask<CR2, (0x1u << 0x14u)>; + using ABRMOD = RegisterMask<CR2, (0x3u << 0x15u)>; + using RTOEN = RegisterMask<CR2, (0x1u << 0x17u)>; + using ADD = RegisterMask<CR2, (0xffu << 0x18u)>; + }; + struct CR3 : public MemRegister<uint32_t, 0x40004c08> { + using EIE = RegisterMask<CR3, (0x1u << 0x0u)>; + using IREN = RegisterMask<CR3, (0x1u << 0x1u)>; + using IRLP = RegisterMask<CR3, (0x1u << 0x2u)>; + using HDSEL = RegisterMask<CR3, (0x1u << 0x3u)>; + using NACK = RegisterMask<CR3, (0x1u << 0x4u)>; + using SCEN = RegisterMask<CR3, (0x1u << 0x5u)>; + using DMAR = RegisterMask<CR3, (0x1u << 0x6u)>; + using DMAT = RegisterMask<CR3, (0x1u << 0x7u)>; + using RTSE = RegisterMask<CR3, (0x1u << 0x8u)>; + using CTSE = RegisterMask<CR3, (0x1u << 0x9u)>; + using CTSIE = RegisterMask<CR3, (0x1u << 0xau)>; + using ONEBIT = RegisterMask<CR3, (0x1u << 0xbu)>; + using OVRDIS = RegisterMask<CR3, (0x1u << 0xcu)>; + using DDRE = RegisterMask<CR3, (0x1u << 0xdu)>; + using DEM = RegisterMask<CR3, (0x1u << 0xeu)>; + using DEP = RegisterMask<CR3, (0x1u << 0xfu)>; + using SCARCNT = RegisterMask<CR3, (0x7u << 0x11u)>; + using WUS0 = RegisterMask<CR3, (0x1u << 0x14u)>; + using WUS1 = RegisterMask<CR3, (0x1u << 0x15u)>; + using WUFIE = RegisterMask<CR3, (0x1u << 0x16u)>; + using TXFTIE = RegisterMask<CR3, (0x1u << 0x17u)>; + using TCBGTIE = RegisterMask<CR3, (0x1u << 0x18u)>; + using RXFTCFG = RegisterMask<CR3, (0x7u << 0x19u)>; + using RXFTIE = RegisterMask<CR3, (0x1u << 0x1cu)>; + using TXFTCFG = RegisterMask<CR3, (0x7u << 0x1du)>; + }; + struct BRR : public MemRegister<uint32_t, 0x40004c0c> { + using val = RegisterMask<BRR, (0xffffu << 0x0u)>; + }; + struct GTPR : public MemRegister<uint32_t, 0x40004c10> { + using PSC = RegisterMask<GTPR, (0xffu << 0x0u)>; + using GT = RegisterMask<GTPR, (0xffu << 0x8u)>; + }; + struct RTOR : public MemRegister<uint32_t, 0x40004c14> { + using RTO = RegisterMask<RTOR, (0xffffffu << 0x0u)>; + using BLEN = RegisterMask<RTOR, (0xffu << 0x18u)>; + }; + struct RQR : public MemRegister<uint32_t, 0x40004c18> { + using ABRRQ = RegisterMask<RQR, (0x1u << 0x0u)>; + using SBKRQ = RegisterMask<RQR, (0x1u << 0x1u)>; + using MMRQ = RegisterMask<RQR, (0x1u << 0x2u)>; + using RXFRQ = RegisterMask<RQR, (0x1u << 0x3u)>; + using TXFRQ = RegisterMask<RQR, (0x1u << 0x4u)>; + }; + struct ISR : public MemRegister<uint32_t, 0x40004c1c> { + using PE = RegisterMask<ISR, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR, (0x1u << 0x4u)>; + using RXFNE = RegisterMask<ISR, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR, (0x1u << 0x6u)>; + using TXFNF = RegisterMask<ISR, (0x1u << 0x7u)>; + using LBDF = RegisterMask<ISR, (0x1u << 0x8u)>; + using CTSIF = RegisterMask<ISR, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR, (0x1u << 0xau)>; + using RTOF = RegisterMask<ISR, (0x1u << 0xbu)>; + using EOBF = RegisterMask<ISR, (0x1u << 0xcu)>; + using UDR = RegisterMask<ISR, (0x1u << 0xdu)>; + using ABRE = RegisterMask<ISR, (0x1u << 0xeu)>; + using ABRF = RegisterMask<ISR, (0x1u << 0xfu)>; + using BUSY = RegisterMask<ISR, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR, (0x1u << 0x16u)>; + using TXFE = RegisterMask<ISR, (0x1u << 0x17u)>; + using RXFF = RegisterMask<ISR, (0x1u << 0x18u)>; + using TCBGT = RegisterMask<ISR, (0x1u << 0x19u)>; + using RXFT = RegisterMask<ISR, (0x1u << 0x1au)>; + using TXFT = RegisterMask<ISR, (0x1u << 0x1bu)>; + }; + struct ISR_ALTERNATE : public MemRegister<uint32_t, 0x40004c1c> { + using PE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x0u)>; + using FE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x1u)>; + using NE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x2u)>; + using ORE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x3u)>; + using IDLE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x4u)>; + using RXNE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x5u)>; + using TC = RegisterMask<ISR_ALTERNATE, (0x1u << 0x6u)>; + using TXE = RegisterMask<ISR_ALTERNATE, (0x1u << 0x7u)>; + using LBDF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x8u)>; + using CTSIF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x9u)>; + using CTS = RegisterMask<ISR_ALTERNATE, (0x1u << 0xau)>; + using RTOF = RegisterMask<ISR_ALTERNATE, (0x1u << 0xbu)>; + using EOBF = RegisterMask<ISR_ALTERNATE, (0x1u << 0xcu)>; + using UDR = RegisterMask<ISR_ALTERNATE, (0x1u << 0xdu)>; + using ABRE = RegisterMask<ISR_ALTERNATE, (0x1u << 0xeu)>; + using ABRF = RegisterMask<ISR_ALTERNATE, (0x1u << 0xfu)>; + using BUSY = RegisterMask<ISR_ALTERNATE, (0x1u << 0x10u)>; + using CMF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x11u)>; + using SBKF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x12u)>; + using RWU = RegisterMask<ISR_ALTERNATE, (0x1u << 0x13u)>; + using WUF = RegisterMask<ISR_ALTERNATE, (0x1u << 0x14u)>; + using TEACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x15u)>; + using REACK = RegisterMask<ISR_ALTERNATE, (0x1u << 0x16u)>; + using TCBGT = RegisterMask<ISR_ALTERNATE, (0x1u << 0x19u)>; + }; + struct ICR : public MemRegister<uint32_t, 0x40004c20> { + using PECF = RegisterMask<ICR, (0x1u << 0x0u)>; + using FECF = RegisterMask<ICR, (0x1u << 0x1u)>; + using NECF = RegisterMask<ICR, (0x1u << 0x2u)>; + using ORECF = RegisterMask<ICR, (0x1u << 0x3u)>; + using IDLECF = RegisterMask<ICR, (0x1u << 0x4u)>; + using TXFECF = RegisterMask<ICR, (0x1u << 0x5u)>; + using TCCF = RegisterMask<ICR, (0x1u << 0x6u)>; + using TCBGTCF = RegisterMask<ICR, (0x1u << 0x7u)>; + using LBDCF = RegisterMask<ICR, (0x1u << 0x8u)>; + using CTSCF = RegisterMask<ICR, (0x1u << 0x9u)>; + using RTOCF = RegisterMask<ICR, (0x1u << 0xbu)>; + using EOBCF = RegisterMask<ICR, (0x1u << 0xcu)>; + using UDRCF = RegisterMask<ICR, (0x1u << 0xdu)>; + using CMCF = RegisterMask<ICR, (0x1u << 0x11u)>; + using WUCF = RegisterMask<ICR, (0x1u << 0x14u)>; + }; + struct RDR : public MemRegister<uint32_t, 0x40004c24> { + using val = RegisterMask<RDR, (0x1ffu << 0x0u)>; + }; + struct TDR : public MemRegister<uint32_t, 0x40004c28> { + using val = RegisterMask<TDR, (0x1ffu << 0x0u)>; + }; + struct PRESC : public MemRegister<uint32_t, 0x40004c2c> { + using PRESCALER = RegisterMask<PRESC, (0xfu << 0x0u)>; + }; + using ALL = RegisterGroup<CR1, CR1_ALTERNATE, CR2, CR3, BRR, GTPR, RTOR, RQR, ISR, ISR_ALTERNATE, ICR, RDR, TDR, PRESC>; + } + namespace USB { + struct CHEP0R : public MemRegister<uint32_t, 0x40005c00> { + using EA = RegisterMask<CHEP0R, (0xfu << 0x0u)>; + using STATTX = RegisterMask<CHEP0R, (0x3u << 0x4u)>; + using DTOGTX = RegisterMask<CHEP0R, (0x1u << 0x6u)>; + using VTTX = RegisterMask<CHEP0R, (0x1u << 0x7u)>; + using EPKIND = RegisterMask<CHEP0R, (0x1u << 0x8u)>; + using UTYPE = RegisterMask<CHEP0R, (0x3u << 0x9u)>; + using SETUP = RegisterMask<CHEP0R, (0x1u << 0xbu)>; + using STATRX = RegisterMask<CHEP0R, (0x3u << 0xcu)>; + using DTOGRX = RegisterMask<CHEP0R, (0x1u << 0xeu)>; + using VTRX = RegisterMask<CHEP0R, (0x1u << 0xfu)>; + using DEVADDR = RegisterMask<CHEP0R, (0x7fu << 0x10u)>; + using NAK = RegisterMask<CHEP0R, (0x1u << 0x17u)>; + using LS_EP = RegisterMask<CHEP0R, (0x1u << 0x18u)>; + using ERR_TX = RegisterMask<CHEP0R, (0x1u << 0x19u)>; + using ERR_RX = RegisterMask<CHEP0R, (0x1u << 0x1au)>; + using THREE_ERR_TX = RegisterMask<CHEP0R, (0x3u << 0x1bu)>; + using THREE_ERR_RX = RegisterMask<CHEP0R, (0x3u << 0x1du)>; + }; + struct CHEP1R : public MemRegister<uint32_t, 0x40005c04> { + using EA = RegisterMask<CHEP1R, (0xfu << 0x0u)>; + using STATTX = RegisterMask<CHEP1R, (0x3u << 0x4u)>; + using DTOGTX = RegisterMask<CHEP1R, (0x1u << 0x6u)>; + using VTTX = RegisterMask<CHEP1R, (0x1u << 0x7u)>; + using EPKIND = RegisterMask<CHEP1R, (0x1u << 0x8u)>; + using UTYPE = RegisterMask<CHEP1R, (0x3u << 0x9u)>; + using SETUP = RegisterMask<CHEP1R, (0x1u << 0xbu)>; + using STATRX = RegisterMask<CHEP1R, (0x3u << 0xcu)>; + using DTOGRX = RegisterMask<CHEP1R, (0x1u << 0xeu)>; + using VTRX = RegisterMask<CHEP1R, (0x1u << 0xfu)>; + using DEVADDR = RegisterMask<CHEP1R, (0x7fu << 0x10u)>; + using NAK = RegisterMask<CHEP1R, (0x1u << 0x17u)>; + using LS_EP = RegisterMask<CHEP1R, (0x1u << 0x18u)>; + using ERR_TX = RegisterMask<CHEP1R, (0x1u << 0x19u)>; + using ERR_RX = RegisterMask<CHEP1R, (0x1u << 0x1au)>; + using THREE_ERR_TX = RegisterMask<CHEP1R, (0x3u << 0x1bu)>; + using THREE_ERR_RX = RegisterMask<CHEP1R, (0x3u << 0x1du)>; + }; + struct CHEP2R : public MemRegister<uint32_t, 0x40005c08> { + using EA = RegisterMask<CHEP2R, (0xfu << 0x0u)>; + using STATTX = RegisterMask<CHEP2R, (0x3u << 0x4u)>; + using DTOGTX = RegisterMask<CHEP2R, (0x1u << 0x6u)>; + using VTTX = RegisterMask<CHEP2R, (0x1u << 0x7u)>; + using EPKIND = RegisterMask<CHEP2R, (0x1u << 0x8u)>; + using UTYPE = RegisterMask<CHEP2R, (0x3u << 0x9u)>; + using SETUP = RegisterMask<CHEP2R, (0x1u << 0xbu)>; + using STATRX = RegisterMask<CHEP2R, (0x3u << 0xcu)>; + using DTOGRX = RegisterMask<CHEP2R, (0x1u << 0xeu)>; + using VTRX = RegisterMask<CHEP2R, (0x1u << 0xfu)>; + using DEVADDR = RegisterMask<CHEP2R, (0x7fu << 0x10u)>; + using NAK = RegisterMask<CHEP2R, (0x1u << 0x17u)>; + using LS_EP = RegisterMask<CHEP2R, (0x1u << 0x18u)>; + using ERR_TX = RegisterMask<CHEP2R, (0x1u << 0x19u)>; + using ERR_RX = RegisterMask<CHEP2R, (0x1u << 0x1au)>; + using THREE_ERR_TX = RegisterMask<CHEP2R, (0x3u << 0x1bu)>; + using THREE_ERR_RX = RegisterMask<CHEP2R, (0x3u << 0x1du)>; + }; + struct CHEP3R : public MemRegister<uint32_t, 0x40005c0c> { + using EA = RegisterMask<CHEP3R, (0xfu << 0x0u)>; + using STATTX = RegisterMask<CHEP3R, (0x3u << 0x4u)>; + using DTOGTX = RegisterMask<CHEP3R, (0x1u << 0x6u)>; + using VTTX = RegisterMask<CHEP3R, (0x1u << 0x7u)>; + using EPKIND = RegisterMask<CHEP3R, (0x1u << 0x8u)>; + using UTYPE = RegisterMask<CHEP3R, (0x3u << 0x9u)>; + using SETUP = RegisterMask<CHEP3R, (0x1u << 0xbu)>; + using STATRX = RegisterMask<CHEP3R, (0x3u << 0xcu)>; + using DTOGRX = RegisterMask<CHEP3R, (0x1u << 0xeu)>; + using VTRX = RegisterMask<CHEP3R, (0x1u << 0xfu)>; + using DEVADDR = RegisterMask<CHEP3R, (0x7fu << 0x10u)>; + using NAK = RegisterMask<CHEP3R, (0x1u << 0x17u)>; + using LS_EP = RegisterMask<CHEP3R, (0x1u << 0x18u)>; + using ERR_TX = RegisterMask<CHEP3R, (0x1u << 0x19u)>; + using ERR_RX = RegisterMask<CHEP3R, (0x1u << 0x1au)>; + using THREE_ERR_TX = RegisterMask<CHEP3R, (0x3u << 0x1bu)>; + using THREE_ERR_RX = RegisterMask<CHEP3R, (0x3u << 0x1du)>; + }; + struct CHEP4R : public MemRegister<uint32_t, 0x40005c10> { + using EA = RegisterMask<CHEP4R, (0xfu << 0x0u)>; + using STATTX = RegisterMask<CHEP4R, (0x3u << 0x4u)>; + using DTOGTX = RegisterMask<CHEP4R, (0x1u << 0x6u)>; + using VTTX = RegisterMask<CHEP4R, (0x1u << 0x7u)>; + using EPKIND = RegisterMask<CHEP4R, (0x1u << 0x8u)>; + using UTYPE = RegisterMask<CHEP4R, (0x3u << 0x9u)>; + using SETUP = RegisterMask<CHEP4R, (0x1u << 0xbu)>; + using STATRX = RegisterMask<CHEP4R, (0x3u << 0xcu)>; + using DTOGRX = RegisterMask<CHEP4R, (0x1u << 0xeu)>; + using VTRX = RegisterMask<CHEP4R, (0x1u << 0xfu)>; + using DEVADDR = RegisterMask<CHEP4R, (0x7fu << 0x10u)>; + using NAK = RegisterMask<CHEP4R, (0x1u << 0x17u)>; + using LS_EP = RegisterMask<CHEP4R, (0x1u << 0x18u)>; + using ERR_TX = RegisterMask<CHEP4R, (0x1u << 0x19u)>; + using ERR_RX = RegisterMask<CHEP4R, (0x1u << 0x1au)>; + using THREE_ERR_TX = RegisterMask<CHEP4R, (0x3u << 0x1bu)>; + using THREE_ERR_RX = RegisterMask<CHEP4R, (0x3u << 0x1du)>; + }; + struct CHEP5R : public MemRegister<uint32_t, 0x40005c14> { + using EA = RegisterMask<CHEP5R, (0xfu << 0x0u)>; + using STATTX = RegisterMask<CHEP5R, (0x3u << 0x4u)>; + using DTOGTX = RegisterMask<CHEP5R, (0x1u << 0x6u)>; + using VTTX = RegisterMask<CHEP5R, (0x1u << 0x7u)>; + using EPKIND = RegisterMask<CHEP5R, (0x1u << 0x8u)>; + using UTYPE = RegisterMask<CHEP5R, (0x3u << 0x9u)>; + using SETUP = RegisterMask<CHEP5R, (0x1u << 0xbu)>; + using STATRX = RegisterMask<CHEP5R, (0x3u << 0xcu)>; + using DTOGRX = RegisterMask<CHEP5R, (0x1u << 0xeu)>; + using VTRX = RegisterMask<CHEP5R, (0x1u << 0xfu)>; + using DEVADDR = RegisterMask<CHEP5R, (0x7fu << 0x10u)>; + using NAK = RegisterMask<CHEP5R, (0x1u << 0x17u)>; + using LS_EP = RegisterMask<CHEP5R, (0x1u << 0x18u)>; + using ERR_TX = RegisterMask<CHEP5R, (0x1u << 0x19u)>; + using ERR_RX = RegisterMask<CHEP5R, (0x1u << 0x1au)>; + using THREE_ERR_TX = RegisterMask<CHEP5R, (0x3u << 0x1bu)>; + using THREE_ERR_RX = RegisterMask<CHEP5R, (0x3u << 0x1du)>; + }; + struct CHEP6R : public MemRegister<uint32_t, 0x40005c18> { + using EA = RegisterMask<CHEP6R, (0xfu << 0x0u)>; + using STATTX = RegisterMask<CHEP6R, (0x3u << 0x4u)>; + using DTOGTX = RegisterMask<CHEP6R, (0x1u << 0x6u)>; + using VTTX = RegisterMask<CHEP6R, (0x1u << 0x7u)>; + using EPKIND = RegisterMask<CHEP6R, (0x1u << 0x8u)>; + using UTYPE = RegisterMask<CHEP6R, (0x3u << 0x9u)>; + using SETUP = RegisterMask<CHEP6R, (0x1u << 0xbu)>; + using STATRX = RegisterMask<CHEP6R, (0x3u << 0xcu)>; + using DTOGRX = RegisterMask<CHEP6R, (0x1u << 0xeu)>; + using VTRX = RegisterMask<CHEP6R, (0x1u << 0xfu)>; + using DEVADDR = RegisterMask<CHEP6R, (0x7fu << 0x10u)>; + using NAK = RegisterMask<CHEP6R, (0x1u << 0x17u)>; + using LS_EP = RegisterMask<CHEP6R, (0x1u << 0x18u)>; + using ERR_TX = RegisterMask<CHEP6R, (0x1u << 0x19u)>; + using ERR_RX = RegisterMask<CHEP6R, (0x1u << 0x1au)>; + using THREE_ERR_TX = RegisterMask<CHEP6R, (0x3u << 0x1bu)>; + using THREE_ERR_RX = RegisterMask<CHEP6R, (0x3u << 0x1du)>; + }; + struct CHEP7R : public MemRegister<uint32_t, 0x40005c1c> { + using EA = RegisterMask<CHEP7R, (0xfu << 0x0u)>; + using STATTX = RegisterMask<CHEP7R, (0x3u << 0x4u)>; + using DTOGTX = RegisterMask<CHEP7R, (0x1u << 0x6u)>; + using VTTX = RegisterMask<CHEP7R, (0x1u << 0x7u)>; + using EPKIND = RegisterMask<CHEP7R, (0x1u << 0x8u)>; + using UTYPE = RegisterMask<CHEP7R, (0x3u << 0x9u)>; + using SETUP = RegisterMask<CHEP7R, (0x1u << 0xbu)>; + using STATRX = RegisterMask<CHEP7R, (0x3u << 0xcu)>; + using DTOGRX = RegisterMask<CHEP7R, (0x1u << 0xeu)>; + using VTRX = RegisterMask<CHEP7R, (0x1u << 0xfu)>; + using DEVADDR = RegisterMask<CHEP7R, (0x7fu << 0x10u)>; + using NAK = RegisterMask<CHEP7R, (0x1u << 0x17u)>; + using LS_EP = RegisterMask<CHEP7R, (0x1u << 0x18u)>; + using ERR_TX = RegisterMask<CHEP7R, (0x1u << 0x19u)>; + using ERR_RX = RegisterMask<CHEP7R, (0x1u << 0x1au)>; + using THREE_ERR_TX = RegisterMask<CHEP7R, (0x3u << 0x1bu)>; + using THREE_ERR_RX = RegisterMask<CHEP7R, (0x3u << 0x1du)>; + }; + struct CNTR : public MemRegister<uint32_t, 0x40005c40> { + using USBRST = RegisterMask<CNTR, (0x1u << 0x0u)>; + using PDWN = RegisterMask<CNTR, (0x1u << 0x1u)>; + using SUSPRDY = RegisterMask<CNTR, (0x1u << 0x2u)>; + using SUSPEN = RegisterMask<CNTR, (0x1u << 0x3u)>; + using L2RES = RegisterMask<CNTR, (0x1u << 0x4u)>; + using L1RES = RegisterMask<CNTR, (0x1u << 0x5u)>; + using L1REQM = RegisterMask<CNTR, (0x1u << 0x7u)>; + using ESOFM = RegisterMask<CNTR, (0x1u << 0x8u)>; + using SOFM = RegisterMask<CNTR, (0x1u << 0x9u)>; + using RST_DCONM = RegisterMask<CNTR, (0x1u << 0xau)>; + using SUSPM = RegisterMask<CNTR, (0x1u << 0xbu)>; + using WKUPM = RegisterMask<CNTR, (0x1u << 0xcu)>; + using ERRM = RegisterMask<CNTR, (0x1u << 0xdu)>; + using PMAOVRM = RegisterMask<CNTR, (0x1u << 0xeu)>; + using CTRM = RegisterMask<CNTR, (0x1u << 0xfu)>; + using THR512M = RegisterMask<CNTR, (0x1u << 0x10u)>; + using DDISCM = RegisterMask<CNTR, (0x1u << 0x11u)>; + using HOST = RegisterMask<CNTR, (0x1u << 0x1fu)>; + }; + struct ISTR : public MemRegister<uint32_t, 0x40005c44> { + using IDN = RegisterMask<ISTR, (0xfu << 0x0u)>; + using DIR = RegisterMask<ISTR, (0x1u << 0x4u)>; + using L1REQ = RegisterMask<ISTR, (0x1u << 0x7u)>; + using ESOF = RegisterMask<ISTR, (0x1u << 0x8u)>; + using SOF = RegisterMask<ISTR, (0x1u << 0x9u)>; + using RST_DCON = RegisterMask<ISTR, (0x1u << 0xau)>; + using SUSP = RegisterMask<ISTR, (0x1u << 0xbu)>; + using WKUP = RegisterMask<ISTR, (0x1u << 0xcu)>; + using ERR = RegisterMask<ISTR, (0x1u << 0xdu)>; + using PMAOVR = RegisterMask<ISTR, (0x1u << 0xeu)>; + using CTR = RegisterMask<ISTR, (0x1u << 0xfu)>; + using THR512 = RegisterMask<ISTR, (0x1u << 0x10u)>; + using DDISC = RegisterMask<ISTR, (0x1u << 0x11u)>; + using DCON_STAT = RegisterMask<ISTR, (0x1u << 0x1du)>; + using LS_DCON = RegisterMask<ISTR, (0x1u << 0x1eu)>; + }; + struct FNR : public MemRegister<uint32_t, 0x40005c48> { + using FN = RegisterMask<FNR, (0x7ffu << 0x0u)>; + using LSOF = RegisterMask<FNR, (0x3u << 0xbu)>; + using LCK = RegisterMask<FNR, (0x1u << 0xdu)>; + using RXDM = RegisterMask<FNR, (0x1u << 0xeu)>; + using RXDP = RegisterMask<FNR, (0x1u << 0xfu)>; + }; + struct DADDR : public MemRegister<uint32_t, 0x40005c4c> { + using ADD = RegisterMask<DADDR, (0x7fu << 0x0u)>; + using EF = RegisterMask<DADDR, (0x1u << 0x7u)>; + }; + struct LPMCSR : public MemRegister<uint32_t, 0x40005c54> { + using LPMEN = RegisterMask<LPMCSR, (0x1u << 0x0u)>; + using LPMACK = RegisterMask<LPMCSR, (0x1u << 0x1u)>; + using REMWAKE = RegisterMask<LPMCSR, (0x1u << 0x3u)>; + using BESL = RegisterMask<LPMCSR, (0xfu << 0x4u)>; + }; + struct BCDR : public MemRegister<uint32_t, 0x40005c58> { + using BCDEN = RegisterMask<BCDR, (0x1u << 0x0u)>; + using DCDEN = RegisterMask<BCDR, (0x1u << 0x1u)>; + using PDEN = RegisterMask<BCDR, (0x1u << 0x2u)>; + using SDEN = RegisterMask<BCDR, (0x1u << 0x3u)>; + using DCDET = RegisterMask<BCDR, (0x1u << 0x4u)>; + using PDET = RegisterMask<BCDR, (0x1u << 0x5u)>; + using SDET = RegisterMask<BCDR, (0x1u << 0x6u)>; + using PS2DET = RegisterMask<BCDR, (0x1u << 0x7u)>; + using DPPU_DPD = RegisterMask<BCDR, (0x1u << 0xfu)>; + }; + using ALL = RegisterGroup<CHEP0R, CHEP1R, CHEP2R, CHEP3R, CHEP4R, CHEP5R, CHEP6R, CHEP7R, CNTR, ISTR, FNR, DADDR, LPMCSR, BCDR>; + } + namespace VREFBUF { + struct CSR : public MemRegister<uint32_t, 0x40010030> { + using ENVR = RegisterMask<CSR, (0x1u << 0x0u)>; + using HIZ = RegisterMask<CSR, (0x1u << 0x1u)>; + using VRS = RegisterMask<CSR, (0x1u << 0x2u)>; + using VRR = RegisterMask<CSR, (0x1u << 0x3u)>; + }; + struct CCR : public MemRegister<uint32_t, 0x40010034> { + using TRIM = RegisterMask<CCR, (0x3fu << 0x0u)>; + }; + using ALL = RegisterGroup<CSR, CCR>; + } + namespace WWDG { + struct CR : public MemRegister<uint32_t, 0x40002c00> { + using T = RegisterMask<CR, (0x7fu << 0x0u)>; + using WDGA = RegisterMask<CR, (0x1u << 0x7u)>; + }; + struct CFR : public MemRegister<uint32_t, 0x40002c04> { + using W = RegisterMask<CFR, (0x7fu << 0x0u)>; + using EWI = RegisterMask<CFR, (0x1u << 0x9u)>; + using WDGTB = RegisterMask<CFR, (0x7u << 0xbu)>; + }; + struct SR : public MemRegister<uint32_t, 0x40002c08> { + using EWIF = RegisterMask<SR, (0x1u << 0x0u)>; + }; + using ALL = RegisterGroup<CR, CFR, SR>; + } +} |