blob: d743e598055b11d5c964d71df67fd6e40cb90ae6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
|
#include <stdint.h>
#define MSP430_SR_C (1 << 0)
#define MSP430_SR_Z (1 << 1)
#define MSP430_SR_N (1 << 2)
#define MSP430_SR_V (1 << 8)
// r0 = pc
// r1 = sp
// r2 = sr
typedef struct {
uint16_t reg[16];
uint8_t *mem;
} msp430_t;
extern uint16_t *msp430_do_cycle_get_single_operand(msp430_t *state, uint16_t opcode);
extern uint16_t *msp430_do_cycle_get_source_operand(msp430_t *state, uint16_t opcode);
extern uint16_t *msp430_do_cycle_get_dest_operand(msp430_t *state, uint16_t opcode);
int msp430_do_cycle_single_operand(msp430_t *state, uint16_t opcode)
{
uint16_t *operand = msp430_do_cycle_get_single_operand(state, opcode);
if (operand == 0)
return -1;
switch ((opcode & 0x0380) >> 7) {
case 0: {
// RRC
uint16_t res = *operand;
uint16_t sr = 0;
if (res & 1)
sr |= MSP430_SR_C;
res >>= 1;
if (state->reg[2] & MSP430_SR_C)
res |= 0x8000;
if (res == 0)
sr |= MSP430_SR_Z;
if ((int16_t)res < 0)
sr |= MSP430_SR_N;
*operand = res;
state->reg[2] = sr;
break; }
case 1: {
// SWPB
uint16_t swapped = ((*operand & 0xFF00) >> 8) | ((*operand & 0x00FF) << 8);
*operand = swapped;
break; }
case 2: {
// RRA
uint16_t res = *operand;
uint16_t sr = 0;
if (res & 1)
sr |= MSP430_SR_C;
res >>= 1;
if (res == 0)
sr |= MSP430_SR_Z;
if ((int16_t)res < 0)
sr |= MSP430_SR_N;
*operand = res;
state->reg[2] = sr;
break; }
case 3: {
// SXT
uint16_t sr = 0;
uint16_t res = (*operand & 0x80) ? (*operand | 0xFF00) : *operand;
if ((int16_t)res < 0)
sr |= MSP430_SR_N;
if (res == 0)
sr |= MSP430_SR_Z;
if (res != 0)
sr |= MSP430_SR_C;
*operand = res;
state->reg[2] = sr;
break; }
case 4: {
// PUSH
uint16_t sp = state->reg[1] - 2;
*((uint16_t *)(state->mem + sp)) = *operand;
state->reg[1] = sp;
break; }
case 5: {
// CALL
uint16_t sp = state->reg[1] - 2;
*((uint16_t *)(state->mem + sp)) = state->reg[0];
state->reg[0] = *operand;
state->reg[1] = sp;
break; }
case 6: {
// RETI
uint16_t sp = state->reg[1];
state->reg[2] = *((uint16_t *)(state->mem + sp));
state->reg[0] = *((uint16_t *)(state->mem + sp + 2));
state->reg[1] = sp + 4;
break; }
default:
return -1;
break;
}
return 0;
}
int msp430_do_cycle_dual_operand(msp430_t *state, uint16_t opcode)
{
uint16_t *src = msp430_do_cycle_get_source_operand(state, opcode);
uint16_t *dst = msp430_do_cycle_get_dest_operand(state, opcode);
if (src == 0 || dst == 0)
return -1;
switch ((opcode & 0xF000) >> 12) {
case 4:
// MOV
*dst = *src;
break;
case 5: {
// ADD
uint32_t res = *src + *dst;
uint16_t sr = 0;
if ((int16_t)(res & 0xFFFF) < 0)
sr |= MSP430_SR_N;
if ((res & 0xFFFF) == 0)
sr |= MSP430_SR_Z;
if ((res & 0xFFFF0000) != 0)
sr |= MSP430_SR_C;
if (((*src & 0x8000) ^ (*dst & 0x8000)) == 0 && (*src & 0x8000) != (res & 0x8000))
sr |= MSP430_SR_V;
*dst = (uint16_t)res;
state->reg[2] = sr;
break; }
case 6: {
// ADDC
uint32_t res = *src + *dst + (state->reg[2] & MSP430_SR_C);
uint16_t sr = 0;
if ((int16_t)res < 0)
sr |= MSP430_SR_N;
if (res == 0)
sr |= MSP430_SR_Z;
if ((res & 0xFFFF0000) != 0)
sr |= MSP430_SR_C;
if (((*src & 0x8000) ^ (*dst & 0x8000)) == 0 && (*src & 0x8000) != (res & 0x8000))
sr |= MSP430_SR_V;
*dst = (uint16_t)res;
state->reg[2] = sr;
break; }
case 7: {
// SUBC
uint32_t res = *dst + ~(*src) + (state->reg[2] & MSP430_SR_C);
uint16_t sr = 0;
if ((int16_t)res < 0)
sr |= MSP430_SR_N;
if (res == 0)
sr |= MSP430_SR_Z;
if ((res & 0xFFFF0000) != 0)
sr |= MSP430_SR_C;
if (((*src & 0x8000) ^ (*dst & 0x8000)) == 0 && (*src & 0x8000) != (res & 0x8000))
sr |= MSP430_SR_V;
*dst = (uint16_t)res;
state->reg[2] = sr;
break; }
case 8: {
// SUB
uint32_t res = *dst + ~(*src) + 1;
uint16_t sr = 0;
if ((int16_t)res < 0)
sr |= MSP430_SR_N;
if (res == 0)
sr |= MSP430_SR_Z;
if ((res & 0xFFFF0000) != 0) // TODO confirm
sr |= MSP430_SR_C;
if (((*src & 0x8000) ^ (*dst & 0x8000)) == 0 && (*src & 0x8000) != (res & 0x8000))
sr |= MSP430_SR_V;
*dst = (uint16_t)res;
state->reg[2] = sr;
break; }
case 9: {
// CMP
uint32_t res = *dst + ~(*src) + 1;
uint16_t sr = 0;
if ((int16_t)res < 0)
sr |= MSP430_SR_N;
if (res == 0)
sr |= MSP430_SR_Z;
if ((res & 0xFFFF0000) != 0)
sr |= MSP430_SR_C;
if (((*src & 0x8000) ^ (*dst & 0x8000)) == 0 && (*src & 0x8000) != (res & 0x8000))
sr |= MSP430_SR_V;
state->reg[2] = sr;
break; }
case 10:
// DADD TODO
break;
case 11: {
// BIT
uint16_t res = *dst & *src;
uint16_t sr = 0;
if (res & 0x8000)
sr |= MSP430_SR_N;
if (res == 0)
sr |= MSP430_SR_Z;
if (res != 0)
sr |= MSP430_SR_C;
state->reg[2] = sr;
break; }
case 12:
// BIC
*dst &= ~(*src);
break;
case 13:
// BIS
*dst |= *src;
break;
case 14: {
// XOR
uint16_t res = *dst ^ *src;
uint16_t sr = 0;
if (res & 0x8000)
sr |= MSP430_SR_N;
if (res == 0)
sr |= MSP430_SR_Z;
if (res != 0)
sr |= MSP430_SR_C;
if ((*dst & 0x8000) && (*src & 0x8000))
sr |= MSP430_SR_V;
*dst = res;
state->reg[2] = sr;
break; }
case 15: {
// AND
uint16_t res = *dst & *src;
uint16_t sr = 0;
if (res & 0x8000)
sr |= MSP430_SR_N;
if (res == 0)
sr |= MSP430_SR_Z;
if (res != 0)
sr |= MSP430_SR_C;
*dst = res;
state->reg[2] = sr;
break; }
default:
return -1;
}
return 0;
}
|
