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157 lines
4.1 KiB
Diff
157 lines
4.1 KiB
Diff
3 years ago
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--- arch/x86/kernel/cpu/bugs.c.new 2022-04-21 10:22:57.337425325 -0400
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+++ arch/x86/kernel/cpu/bugs.c 2022-04-21 10:34:47.550249356 -0400
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@@ -36,6 +36,7 @@
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#include "cpu.h"
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+#ifndef CONFIG_M486
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static void __init spectre_v1_select_mitigation(void);
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static void __init spectre_v2_select_mitigation(void);
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static void __init ssb_select_mitigation(void);
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@@ -45,6 +46,7 @@
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static void __init taa_select_mitigation(void);
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static void __init srbds_select_mitigation(void);
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static void __init l1d_flush_select_mitigation(void);
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+#endif // CONFIG_M486
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/* The base value of the SPEC_CTRL MSR that always has to be preserved. */
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u64 x86_spec_ctrl_base;
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@@ -112,6 +114,7 @@
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if (boot_cpu_has(X86_FEATURE_STIBP))
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x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
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+#ifndef CONFIG_M486
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/* Select the proper CPU mitigations before patching alternatives: */
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spectre_v1_select_mitigation();
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spectre_v2_select_mitigation();
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@@ -127,6 +130,7 @@
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* mitigation until after TAA mitigation selection is done.
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*/
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mds_print_mitigation();
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+#endif // CONFIG_M486
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arch_smt_update();
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@@ -248,6 +252,7 @@
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[MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
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};
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+#ifndef CONFIG_M486
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static void __init mds_select_mitigation(void)
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{
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if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
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@@ -274,6 +279,7 @@
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pr_info("%s\n", mds_strings[mds_mitigation]);
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}
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+#endif // CONFIG_M486
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static int __init mds_cmdline(char *str)
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{
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@@ -317,6 +323,7 @@
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[TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled",
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};
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+#ifndef CONFIG_M486
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static void __init taa_select_mitigation(void)
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{
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u64 ia32_cap;
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@@ -388,6 +395,7 @@
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out:
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pr_info("%s\n", taa_strings[taa_mitigation]);
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}
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+#endif // CONFIG_M486
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static int __init tsx_async_abort_parse_cmdline(char *str)
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{
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@@ -463,6 +471,7 @@
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wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
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}
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+#ifndef CONFIG_M486
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static void __init srbds_select_mitigation(void)
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{
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u64 ia32_cap;
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@@ -487,6 +496,7 @@
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update_srbds_msr();
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pr_info("%s\n", srbds_strings[srbds_mitigation]);
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}
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+#endif // CONFIG_M486
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static int __init srbds_parse_cmdline(char *str)
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{
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@@ -504,6 +514,7 @@
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#undef pr_fmt
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#define pr_fmt(fmt) "L1D Flush : " fmt
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+#ifndef CONFIG_M486
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enum l1d_flush_mitigations {
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L1D_FLUSH_OFF = 0,
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L1D_FLUSH_ON,
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@@ -528,10 +539,12 @@
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return 0;
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}
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early_param("l1d_flush", l1d_flush_parse_cmdline);
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+#endif // CONFIG_M486
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#undef pr_fmt
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#define pr_fmt(fmt) "Spectre V1 : " fmt
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+#ifndef CONFIG_M486
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enum spectre_v1_mitigation {
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SPECTRE_V1_MITIGATION_NONE,
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SPECTRE_V1_MITIGATION_AUTO,
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@@ -618,6 +631,7 @@
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return 0;
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}
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early_param("nospectre_v1", nospectre_v1_cmdline);
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+#endif // CONFIG_M486
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#undef pr_fmt
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#define pr_fmt(fmt) "Spectre V2 : " fmt
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@@ -729,6 +743,7 @@
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{ "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false },
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};
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+#ifndef CONFIG_M486
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static void __init spec_v2_user_print_cond(const char *reason, bool secure)
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{
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if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
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@@ -1071,6 +1086,7 @@
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/* Set up IBPB and STIBP depending on the general spectre V2 command */
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spectre_v2_user_select_mitigation(cmd);
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}
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+#endif // CONFIG_M486
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static void update_stibp_msr(void * __unused)
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{
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@@ -1207,6 +1223,7 @@
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{ "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
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};
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+#ifndef CONFIG_M486
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static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
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{
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enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
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@@ -1316,6 +1333,7 @@
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if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
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pr_info("%s\n", ssb_strings[ssb_mode]);
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}
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+#endif // CONFIG_M486
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#undef pr_fmt
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#define pr_fmt(fmt) "Speculation prctl: " fmt
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@@ -1573,6 +1591,7 @@
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enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
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EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
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+#ifndef CONFIG_M486
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/*
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* These CPUs all support 44bits physical address space internally in the
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* cache but CPUID can report a smaller number of physical address bits.
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@@ -1926,3 +1945,4 @@
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return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
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}
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#endif
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+#endif // CONFIG_M486
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