go os-less; filter in sram; consider dynamic freq
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3267C8EBF3F9AFC7
@ -0,0 +1,68 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file templates/halconf.h
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* @brief Bare-metal OSAL configuration header.
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*
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* @addtogroup OSAL_CONF
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* @{
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*/
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#ifndef OSALCONF_H
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#define OSALCONF_H
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/**
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* @brief Frequency in Hertz of the system tick.
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*/
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#if !defined(OSAL_ST_FREQUENCY) || defined(__DOXYGEN__)
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#define OSAL_ST_FREQUENCY 20
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#endif
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/**
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* @brief Enables OSAL assertions.
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*/
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#if !defined(OSAL_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
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#define OSAL_DBG_ENABLE_ASSERTS FALSE
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#endif
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/**
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* @brief Enables OSAL functions parameters checks.
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*/
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#if !defined(OSAL_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
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#define OSAL_DBG_ENABLE_CHECKS FALSE
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#endif
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/**
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* @brief OSAL initialization hook.
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*/
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#if !defined(OSAL_INIT_HOOK) || defined(__DOXYGEN__)
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#define OSAL_INIT_HOOK() { \
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}
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#endif
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/**
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* @brief Idle loop hook macro.
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*/
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#if !defined(OSAL_IDLE_HOOK) || defined(__DOXYGEN__)
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#define OSAL_IDLE_HOOK() { \
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asm("wfi"); \
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}
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#endif
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#endif /* OSALCONF_H */
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/** @} */
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@ -0,0 +1,381 @@
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inline float qfp_fpow(float b, float e)
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{
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return qfp_fexp(qfp_fmul(e, qfp_fln(b)));
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}
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inline float qfp_flog10(float x)
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{
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static const auto ln10 = qfp_fln(10.f);
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return qfp_fdiv(qfp_fln(x), ln10);
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}
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__attribute__((naked, section(".data")))
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inline float qfp_fadd_asm(float, float)
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{
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asm(R"(
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.syntax unified
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push {r4,r5,r6,r14}
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asrs r4,r0,#31
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lsls r2,r0,#1
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lsrs r2,#24 @ x exponent
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beq fa_xe0
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cmp r2,#255
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beq fa_xe255
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fa_xe:
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asrs r5,r1,#31
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lsls r3,r1,#1
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lsrs r3,#24 @ y exponent
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beq fa_ye0
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cmp r3,#255
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beq fa_ye255
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fa_ye:
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ldr r6,=#0x007fffff
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ands r0,r0,r6 @ extract mantissa bits
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ands r1,r1,r6
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adds r6,#1 @ r6=0x00800000
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orrs r0,r0,r6 @ set implied 1
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orrs r1,r1,r6
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eors r0,r0,r4 @ complement...
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eors r1,r1,r5
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subs r0,r0,r4 @ ... and add 1 if sign bit is set: 2's complement
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subs r1,r1,r5
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subs r5,r3,r2 @ ye-xe
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subs r4,r2,r3 @ xe-ye
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bmi fa_ygtx
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@ here xe>=ye
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cmp r4,#30
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bge fa_xmgty @ xe much greater than ye?
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adds r5,#32
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movs r3,r2 @ save exponent
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@ here y in r1 must be shifted down r4 places to align with x in r0
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movs r2,r1
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lsls r2,r2,r5 @ keep the bits we will shift off the bottom of r1
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asrs r1,r1,r4
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b fa_0
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.ltorg
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fa_ymgtx:
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movs r2,#0 @ result is just y
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movs r0,r1
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b fa_1
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fa_xmgty:
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movs r3,r2 @ result is just x
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movs r2,#0
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b fa_1
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fa_ygtx:
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@ here ye>xe
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cmp r5,#30
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bge fa_ymgtx @ ye much greater than xe?
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adds r4,#32
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@ here x in r0 must be shifted down r5 places to align with y in r1
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movs r2,r0
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lsls r2,r2,r4 @ keep the bits we will shift off the bottom of r0
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asrs r0,r0,r5
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fa_0:
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adds r0,r1 @ result is now in r0:r2, possibly highly denormalised or zero; exponent in r3
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beq fa_9 @ if zero, inputs must have been of identical magnitude and opposite sign, so return +0
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fa_1:
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lsrs r1,r0,#31 @ sign bit
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beq fa_8
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mvns r0,r0
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rsbs r2,r2,#0
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bne fa_8
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adds r0,#1
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fa_8:
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adds r6,r6
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@ r6=0x01000000
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cmp r0,r6
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bhs fa_2
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fa_3:
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adds r2,r2 @ normalisation loop
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adcs r0,r0
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subs r3,#1 @ adjust exponent
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cmp r0,r6
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blo fa_3
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fa_2:
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@ here r0:r2 is the result mantissa 0x01000000<=r0<0x02000000, r3 the exponent, and r1 the sign bit
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lsrs r0,#1
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bcc fa_4
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@ rounding bits here are 1:r2
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adds r0,#1 @ round up
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cmp r2,#0
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beq fa_5 @ sticky bits all zero?
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fa_4:
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cmp r3,#254
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bhs fa_6 @ exponent too large or negative?
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lsls r1,#31 @ pack everything
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add r0,r1
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lsls r3,#23
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add r0,r3
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fa_end:
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pop {r4,r5,r6,r15}
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fa_9:
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cmp r2,#0 @ result zero?
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beq fa_end @ return +0
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b fa_1
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fa_5:
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lsrs r0,#1
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lsls r0,#1 @ round to even
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b fa_4
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fa_6:
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bge fa_7
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@ underflow
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@ can handle denormals here
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lsls r0,r1,#31 @ result is signed zero
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pop {r4,r5,r6,r15}
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fa_7:
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@ overflow
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lsls r0,r1,#8
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adds r0,#255
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lsls r0,#23 @ result is signed infinity
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pop {r4,r5,r6,r15}
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fa_xe0:
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@ can handle denormals here
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subs r2,#32
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adds r2,r4 @ exponent -32 for +Inf, -33 for -Inf
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b fa_xe
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fa_xe255:
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@ can handle NaNs here
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lsls r2,#8
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add r2,r2,r4 @ exponent ~64k for +Inf, ~64k-1 for -Inf
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b fa_xe
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fa_ye0:
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@ can handle denormals here
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subs r3,#32
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adds r3,r5 @ exponent -32 for +Inf, -33 for -Inf
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b fa_ye
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fa_ye255:
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@ can handle NaNs here
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lsls r3,#8
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add r3,r3,r5 @ exponent ~64k for +Inf, ~64k-1 for -Inf
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b fa_ye
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)");
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}
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__attribute__((naked, section(".data")))
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inline float qfp_fmul_asm(float, float)
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{
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asm(R"(
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.syntax unified
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push {r7,r14}
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mov r2,r0
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eors r2,r1 @ sign of result
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lsrs r2,#31
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lsls r2,#31
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mov r14,r2
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lsls r0,#1
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lsls r1,#1
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lsrs r2,r0,#24 @ xe
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beq fm_xe0
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cmp r2,#255
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beq fm_xe255
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fm_xe:
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lsrs r3,r1,#24 @ ye
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beq fm_ye0
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cmp r3,#255
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beq fm_ye255
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fm_ye:
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adds r7,r2,r3 @ exponent of result (will possibly be incremented)
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subs r7,#128 @ adjust bias for packing
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lsls r0,#8 @ x mantissa
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lsls r1,#8 @ y mantissa
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lsrs r0,#9
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lsrs r1,#9
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adds r2,r0,r1 @ for later
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mov r12,r2
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lsrs r2,r0,#7 @ x[22..7] Q16
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lsrs r3,r1,#7 @ y[22..7] Q16
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muls r2,r2,r3 @ result [45..14] Q32: never an overestimate and worst case error is 2*(2^7-1)*(2^23-2^7)+(2^7-1)^2 = 2130690049 < 2^31
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muls r0,r0,r1 @ result [31..0] Q46
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lsrs r2,#18 @ result [45..32] Q14
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bcc 1f
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cmp r0,#0
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bmi 1f
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adds r2,#1 @ fix error in r2
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1:
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lsls r3,r0,#9 @ bits off bottom of result
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lsrs r0,#23 @ Q23
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lsls r2,#9
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adds r0,r2 @ cut'n'shut
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add r0,r12 @ implied 1*(x+y) to compensate for no insertion of implied 1s
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@ result-1 in r3:r0 Q23+32, i.e., in range [0,3)
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lsrs r1,r0,#23
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bne fm_0 @ branch if we need to shift down one place
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@ here 1<=result<2
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cmp r7,#254
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bhs fm_3a @ catches both underflow and overflow
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lsls r3,#1 @ sticky bits at top of R3, rounding bit in carry
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bcc fm_1 @ no rounding
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beq fm_2 @ rounding tie?
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adds r0,#1 @ round up
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fm_1:
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adds r7,#1 @ for implied 1
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lsls r7,#23 @ pack result
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add r0,r7
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add r0,r14
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pop {r7,r15}
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fm_2: @ rounding tie
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adds r0,#1
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fm_3:
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lsrs r0,#1
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lsls r0,#1 @ clear bottom bit
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b fm_1
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@ here 1<=result-1<3
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fm_0:
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adds r7,#1 @ increment exponent
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cmp r7,#254
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bhs fm_3b @ catches both underflow and overflow
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lsrs r0,#1 @ shift mantissa down
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bcc fm_1a @ no rounding
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adds r0,#1 @ assume we will round up
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cmp r3,#0 @ sticky bits
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beq fm_3c @ rounding tie?
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fm_1a:
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adds r7,r7
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adds r7,#1 @ for implied 1
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lsls r7,#22 @ pack result
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add r0,r7
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add r0,r14
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pop {r7,r15}
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fm_3c:
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lsrs r0,#1
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lsls r0,#1 @ clear bottom bit
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b fm_1a
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fm_xe0:
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subs r2,#16
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fm_xe255:
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lsls r2,#8
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b fm_xe
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fm_ye0:
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subs r3,#16
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fm_ye255:
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lsls r3,#8
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b fm_ye
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@ here the result is under- or overflowing
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fm_3b:
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bge fm_4 @ branch on overflow
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@ trap case where result is denormal 0x007fffff + 0.5ulp or more
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adds r7,#1 @ exponent=-1?
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bne fm_5
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@ corrected mantissa will be >= 3.FFFFFC (0x1fffffe Q23)
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@ so r0 >= 2.FFFFFC (0x17ffffe Q23)
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adds r0,#2
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lsrs r0,#23
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cmp r0,#3
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bne fm_5
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b fm_6
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fm_3a:
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bge fm_4 @ branch on overflow
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@ trap case where result is denormal 0x007fffff + 0.5ulp or more
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adds r7,#1 @ exponent=-1?
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bne fm_5
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adds r0,#1 @ mantissa=0xffffff (i.e., r0=0x7fffff)?
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lsrs r0,#23
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beq fm_5
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fm_6:
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movs r0,#1 @ return smallest normal
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lsls r0,#23
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add r0,r14
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pop {r7,r15}
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fm_5:
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mov r0,r14
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pop {r7,r15}
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fm_4:
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movs r0,#0xff
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lsls r0,#23
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add r0,r14
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pop {r7,r15}
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)");
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}
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__attribute__((naked, section(".data")))
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inline float qfp_int2float_asm(int)
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{
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asm(R"(
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.syntax unified
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movs r1,#0 @ fall through
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push {r4,r5,r6,r14}
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movs r2,#29
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subs r2,r1 @ fix exponent
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movs r5,#0
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bl qfp_int2float_packx
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pop {r4,r5,r6,r15}
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qfp_int2float_packx:
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lsrs r4,r0,#31 @ save sign bit
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lsls r4,r4,#31 @ sign now in b31
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bpl 2f @ skip if positive
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cmp r5,#0
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beq 11f
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adds r0,#1 @ fiddle carry in to following rsb if sticky bits are non-zero
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11:
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rsbs r0,#0 @ can now treat r0 as unsigned
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bmi 3f @ catch r0=0x80000000 case
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2:
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subs r2,#1 @ normalisation loop
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adds r0,r0
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beq 1f @ zero? special case
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bpl 2b @ normalise so leading "1" in bit 31
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3:
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adds r2,#129 @ (mis-)offset exponent
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bne 12f @ special case: highest denormal can round to lowest normal
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adds r0,#0x80 @ in special case, need to add 256 to r0 for rounding
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bcs 4f @ tripped carry? then have leading 1 in C as required
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12:
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adds r0,#0x80 @ rounding
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bcs 4f @ tripped carry? then have leading 1 in C as required (and result is even so can ignore sticky bits)
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cmp r5,#0
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beq 7f @ sticky bits zero?
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8:
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lsls r0,#1 @ remove leading 1
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9:
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subs r2,#1 @ compensate exponent on this path
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4:
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cmp r2,#254
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bge 5f @ overflow?
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adds r2,#1 @ correct exponent offset
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ble 10f @ denormal/underflow?
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lsrs r0,#9 @ align mantissa
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lsls r2,#23 @ align exponent
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orrs r0,r2 @ assemble exponent and mantissa
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6:
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orrs r0,r4 @ apply sign
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1:
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bx r14
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5:
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movs r0,#0xff @ create infinity
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lsls r0,#23
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b 6b
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10:
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movs r0,#0 @ create zero
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bx r14
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7: @ sticky bit rounding case
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lsls r5,r0,#24 @ check bottom 8 bits of r0
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bne 8b @ in rounding-tie case?
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lsrs r0,#9 @ ensure even result
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lsls r0,#10
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b 9b
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)");
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}
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