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72 lines
1.9 KiB
Markdown
72 lines
1.9 KiB
Markdown
2 years ago
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# 2. DAC output with an IIR filter
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## DAC initialization
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This example uses the DAC with minimal configuration.
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Enable the DAC's clock through the RCC:
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```cpp
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RCC->APB1ENR1 |= RCC_APB1ENR1_DAC1EN;
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```
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Then, just enable DAC channel one. This will output over pin PA4:
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```cpp
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DAC1->CR = DAC_CR_EN1;
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```
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We rely on the default/reset configuration of the other DAC registers. In this
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configuration, the DAC is running without a hardware or software trigger;
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instead, the DAC will update its output whenever we provide a new output value.
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There is a variety of output registers available for different bit-sizes and
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alignments. We will stick to the basic 12-bit, right-aligned register
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`DHR12R1`.
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## IIR filter
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The filter will run in a `while` loop, reading samples from the ADC and using
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them to produce new DAC output data.
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The first-order recursive equation is `y[n] = a*y[n-1] + b*x[n]`. Constants `a`
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and `b` set the weights for the previous output sample and current input
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sample; their sum should not be greater than one.
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```cpp
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const float a = 0.5f;
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const float b = 0.5f;
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```
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In the `while` loop, we read our input sample from the ADC (`x[n]`) and
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calculate the new output value `y`:
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```cpp
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unsigned int yprev = 0; // y[n-1]
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while (1) {
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unsigned int x = adc_read();
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unsigned int y = a * yprev + b * x;
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```
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The new output value is then sent out over the DAC and stored in `yprev` for
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the next calculation/iteration.
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```cpp
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DAC1->DHR12R1 = y;
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yprev = y;
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```
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Finally, we add a small delay to have some basic control over the sampling
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rate. Increasing the loop's max value may make the filter's effect more
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visible, while decreasing it will minimize the observed effect.
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Ideally, the sampling rate would instead be controlled by setting the speed of
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the clock given to the ADC and configuring the registers responsible for the
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conversion and sampling timings.
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```cpp
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for (int i = 0; i < 100; ++i);
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}
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```
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