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50 lines
1.7 KiB
C
50 lines
1.7 KiB
C
#include <stm32l476xx.h>
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int main(void)
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{
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// Disable interrupts
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asm("cpsid i");
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// Running at 80MHz requires configuring flash wait-states:
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FLASH->ACR = (FLASH->ACR & ~(FLASH_ACR_LATENCY)) | FLASH_ACR_LATENCY_4WS;
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// Configure the PLL to output 80MHz:
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// 1. MSI clock is 4MHz at reset, use MSI as source for PLL
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// 2. Set PLLN multiplier to 40: 4MHz * 40 = 160MHz
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// 3. PLLM divider is set to zero, no division there
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// 4. Set PLLR system clock divider to zero = division by two
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// 160MHz / 2 = 80MHz
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RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_MSI |
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(40 << RCC_PLLCFGR_PLLN_Pos) |
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(0 << RCC_PLLCFGR_PLLR_Pos) |
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RCC_PLLCFGR_PLLREN;
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// Enable the PLL
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RCC->CR |= RCC_CR_PLLON;
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while ((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY);
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// Set the system clock to use PLL
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// Also clear the HPRE divider to be safe
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RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_HPRE_Msk | RCC_CFGR_SW_Msk)) |
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RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);
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// The processor is now running at 80MHz!
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// Enable MCO to output the system clock over PA8
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RCC->CFGR &= ~(RCC_CFGR_MCOPRE_Msk);
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RCC->CFGR |= 2 << RCC_CFGR_MCOSEL_Pos;
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// Configure PA8 for alternate function zero (MCO)
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RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
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GPIOA->MODER &= ~(GPIO_MODER_MODE8_Msk);
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GPIOA->MODER |= 2 << GPIO_MODER_MODE8_Pos;
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GPIOA->AFR[1] &= ~(GPIO_AFRH_AFSEL8_Msk);
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// Using a volatile assembly instruction ensures that this loop is not
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// optimized away by the compiler.
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while (1)
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asm volatile("nop");
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}
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